diff --git a/0001-LoongArch-Fixup-configure-file-error.patch b/0001-LoongArch-Fixup-configure-file-error.patch new file mode 100644 index 0000000000000000000000000000000000000000..eb8a21a8b7af0ae31f965937d9768be29d29d69e --- /dev/null +++ b/0001-LoongArch-Fixup-configure-file-error.patch @@ -0,0 +1,153 @@ +From 77dd77cc1400180914b26c19704dbe990cb36878 Mon Sep 17 00:00:00 2001 +From: Xing Li +Date: Mon, 31 Oct 2022 20:12:09 +0800 +Subject: [PATCH] LoongArch: Fixup configure file error + +configure error lead to the default macros not correct during compile +initialize, such as dwarf2out_as_loc_support and dwarf2out_as_locview_support + +Signed-off-by: Xing Li +--- + gcc/configure | 67 +++++++++++++++++++++++++++++++++++++++++++++--- + libgcc/configure | 5 +++- + 2 files changed, 67 insertions(+), 5 deletions(-) + +diff --git a/gcc/configure b/gcc/configure +index 56566e3f1..f0b5dbc00 100755 +--- a/gcc/configure ++++ b/gcc/configure +@@ -5075,6 +5075,9 @@ case "${target}" in + # sets the default TLS model and affects inlining. + PICFLAG_FOR_TARGET=-fPIC + ;; ++ loongarch*-*-*) ++ PICFLAG_FOR_TARGET=-fpic ++ ;; + mips-sgi-irix6*) + # PIC is the default. + ;; +@@ -7525,6 +7528,9 @@ else + enable_fixed_point=yes + ;; + ++ loongarch*-*-*) ++ enable_fixed_point=yes ++ ;; + mips*-*-*) + enable_fixed_point=yes + ;; +@@ -24085,6 +24091,18 @@ x: + tls_first_minor=16 + tls_as_opt='-32 --fatal-warnings' + ;; ++ loongarch*-*-*) ++ conftest_s=' ++ .section .tdata,"awT",@progbits ++x: .word 2 ++ .text ++ la.tls.gd $a0,x ++ bl __tls_get_addr' ++ tls_first_major=0 ++ tls_first_minor=0 ++ tls_as_opt='--fatal-warnings' ++ ;; ++ + m68k-*-*) + conftest_s=' + .section .tdata,"awT",@progbits +@@ -27644,6 +27662,47 @@ fi + as_fn_error "Requesting --with-nan= requires assembler support for -mnan=" "$LINENO" 5 + fi + ;; ++ loongarch*-*-*) ++ { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .dtprelword support" >&5 ++$as_echo_n "checking assembler for .dtprelword support... " >&6; } ++if test "${gcc_cv_as_loongarch_dtprelword+set}" = set; then : ++ $as_echo_n "(cached) " >&6 ++else ++ gcc_cv_as_loongarch_dtprelword=no ++ if test $in_tree_gas = yes; then ++ if test $gcc_cv_gas_vers -ge `expr \( \( 2 \* 1000 \) + 18 \) \* 1000 + 0` ++ then gcc_cv_as_loongarch_dtprelword=yes ++fi ++ elif test x$gcc_cv_as != x; then ++ $as_echo '.section .tdata,"awT",@progbits ++x: ++ .word 2 ++ .text ++ .dtprelword x+0x8000' > conftest.s ++ if { ac_try='$gcc_cv_as $gcc_cv_as_flags -o conftest.o conftest.s >&5' ++ { { eval echo "\"\$as_me\":${as_lineno-$LINENO}: \"$ac_try\""; } >&5 ++ (eval $ac_try) 2>&5 ++ ac_status=$? ++ $as_echo "$as_me:${as_lineno-$LINENO}: \$? = $ac_status" >&5 ++ test $ac_status = 0; }; } ++ then ++ gcc_cv_as_loongarch_dtprelword=yes ++ else ++ echo "configure: failed program was" >&5 ++ cat conftest.s >&5 ++ fi ++ rm -f conftest.o conftest.s ++ fi ++fi ++{ $as_echo "$as_me:${as_lineno-$LINENO}: result: $gcc_cv_as_loongarch_dtprelword" >&5 ++$as_echo "$gcc_cv_as_loongarch_dtprelword" >&6; } ++if test $gcc_cv_as_loongarch_dtprelword = yes; then ++ ++$as_echo "#define HAVE_AS_DTPRELWORD 1" >>confdefs.h ++ ++fi ++ ++ ;; + s390*-*-*) + { $as_echo "$as_me:${as_lineno-$LINENO}: checking assembler for .gnu_attribute support" >&5 + $as_echo_n "checking assembler for .gnu_attribute support... " >&6; } +@@ -27827,7 +27886,7 @@ esac + # Linux on IA64 might be able to use the Intel assembler. + + case "$target" in +- mips*-*-* | *-*-hpux* ) ++ mips*-*-* | loongarch*-*-* | *-*-hpux* ) + if test x$gas_flag = xyes \ + || test x"$host" != x"$build" \ + || test ! -x "$gcc_cv_as" \ +@@ -27847,9 +27906,9 @@ esac + # ??? Once 2.11 is released, probably need to add first known working + # version to the per-target configury. + case "$cpu_type" in +- aarch64 | alpha | arc | arm | avr | bfin | cris | i386 | m32c | m68k \ +- | microblaze | mips | nios2 | pa | riscv | rs6000 | score | sparc | spu \ +- | tilegx | tilepro | visium | xstormy16 | xtensa) ++ aarch64 | alpha | arc | arm | avr | bfin | cris | i386 | loongarch | m32c \ ++ | m68k | microblaze | mips | nios2 | pa | riscv | rs6000 | score | sparc \ ++ | spu | tilegx | tilepro | visium | xstormy16 | xtensa) + insn="nop" + ;; + ia64 | s390) +diff --git a/libgcc/configure b/libgcc/configure +index aac5e5fb6..170b470dd 100755 +--- a/libgcc/configure ++++ b/libgcc/configure +@@ -2362,6 +2362,9 @@ case "${host}" in + # sets the default TLS model and affects inlining. + PICFLAG=-fPIC + ;; ++ loongarch*-*-*) ++ PICFLAG=-fpic ++ ;; + mips-sgi-irix6*) + # PIC is the default. + ;; +@@ -4938,7 +4941,7 @@ $as_echo "$libgcc_cv_cfi" >&6; } + # word size rather than the address size. + cat > conftest.c < +Date: Tue, 1 Nov 2022 09:41:17 +0800 +Subject: [PATCH 2/2] LoongArch: Rename config file for loongarch + +Signed-off-by: Xing Li +--- + config/{mt-loongnix-gnu => mt-loongarch-gnu} | 0 + 1 file changed, 0 insertions(+), 0 deletions(-) + rename config/{mt-loongnix-gnu => mt-loongarch-gnu} (100%) + +diff --git a/config/mt-loongnix-gnu b/config/mt-loongarch-gnu +similarity index 100% +rename from config/mt-loongnix-gnu +rename to config/mt-loongarch-gnu +-- +2.27.0 + diff --git a/LoongArch-Fix-atomic_exchange-expanding-PR107713.patch b/LoongArch-Fix-atomic_exchange-expanding-PR107713.patch new file mode 100644 index 0000000000000000000000000000000000000000..16602890c26dfd2c3489455f3a1a7c6ca05b88bc --- /dev/null +++ b/LoongArch-Fix-atomic_exchange-expanding-PR107713.patch @@ -0,0 +1,164 @@ +From 438fe2208b9a219e3a3d729f39a55c6831082181 Mon Sep 17 00:00:00 2001 +From: Xing Li +Date: Fri, 2 Dec 2022 10:35:54 +0800 +Subject: [PATCH] LoongArch: Fix atomic_exchange expanding [PR107713] + +We used to expand atomic_exchange_n(ptr, new, mem_order) for subword types +into something like: + + { + __typeof__(*ptr) t = atomic_load_n(ptr, mem_order); + atomic_compare_exchange_n(ptr, &t, new, true, mem_order, mem_order); + return t; + } + +It's incorrect because another thread may store a different value into *ptr +after atomic_load_n. Then atomic_compare_exchange_n will not store into +*ptr, but atomic_exchange_n should always perform the store. + +gcc/ChangeLog: + + PR target/107713 + * config/loongarch/sync.md + (atomic_cas_value_exchange_7_): New define_insn. + (atomic_exchange): Use atomic_cas_value_exchange_7_si instead of + atomic_cas_value_cmp_and_7_si. + +gcc/testsuite/ChangeLog: + + PR target/107713 + * gcc.target/loongarch/pr107713-1.c: New test. + * gcc.target/loongarch/pr107713-2.c: New test. + +Signed-off-by: Xing Li +Signed-off-by: Jinyang He +--- + gcc/config/loongarch/sync.md | 27 +++++++++- + .../gcc.target/loongarch/pr107713-1.c | 50 +++++++++++++++++++ + .../gcc.target/loongarch/pr107713-2.c | 9 ++++ + 3 files changed, 84 insertions(+), 2 deletions(-) + create mode 100644 gcc/testsuite/gcc.target/loongarch/pr107713-1.c + create mode 100644 gcc/testsuite/gcc.target/loongarch/pr107713-2.c + +diff --git a/gcc/config/loongarch/sync.md b/gcc/config/loongarch/sync.md +index e3eb43e16..5a16c4fa3 100644 +--- a/gcc/config/loongarch/sync.md ++++ b/gcc/config/loongarch/sync.md +@@ -461,6 +461,29 @@ + } + [(set (attr "length") (const_int 32))]) + ++(define_insn "atomic_cas_value_exchange_7_" ++ [(set (match_operand:GPR 0 "register_operand" "=&r") ++ (match_operand:GPR 1 "memory_operand" "+ZC")) ++ (set (match_dup 1) ++ (unspec_volatile:GPR [(match_operand:GPR 2 "reg_or_0_operand" "rJ") ++ (match_operand:GPR 3 "reg_or_0_operand" "rJ") ++ (match_operand:GPR 4 "reg_or_0_operand" "rJ") ++ (match_operand:GPR 5 "reg_or_0_operand" "rJ") ++ (match_operand:SI 6 "const_int_operand")] ;; model ++ UNSPEC_SYNC_EXCHANGE)) ++ (clobber (match_scratch:GPR 7 "=&r"))] ++ "" ++{ ++ return "%G6\\n\\t" ++ "1:\\n\\t" ++ "ll.\\t%0,%1\\n\\t" ++ "and\\t%7,%0,%z3\\n\\t" ++ "or%i5\\t%7,%7,%5\\n\\t" ++ "sc.\\t%7,%1\\n\\t" ++ "beqz\\t%7,1b\\n\\t"; ++} ++ [(set (attr "length") (const_int 20))]) ++ + (define_expand "atomic_exchange" + [(set (match_operand:SHORT 0 "register_operand") + (unspec_volatile:SHORT +@@ -472,11 +495,11 @@ + "" + { + union loongarch_gen_fn_ptrs generator; +- generator.fn_7 = gen_atomic_cas_value_cmp_and_7_si; ++ generator.fn_7 = gen_atomic_cas_value_exchange_7_si; + loongarch_expand_atomic_qihi (generator, + operands[0], + operands[1], +- operands[1], ++ const0_rtx, + operands[2], + operands[3]); + DONE; +diff --git a/gcc/testsuite/gcc.target/loongarch/pr107713-1.c b/gcc/testsuite/gcc.target/loongarch/pr107713-1.c +new file mode 100644 +index 000000000..c307bf87b +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/pr107713-1.c +@@ -0,0 +1,50 @@ ++/* { dg-do run } */ ++/* { dg-require-effective-target pthread } */ ++/* { dg-options "-pthread" } */ ++ ++#include ++ ++char x, x1, x2; ++ ++void * ++work1 (void *none) ++{ ++ for (int i = 0; i < 100; i++) ++ x1 = __atomic_exchange_n (&x, x1, __ATOMIC_SEQ_CST); ++ return NULL; ++} ++ ++void * ++work2 (void *none) ++{ ++ for (int i = 0; i < 100; i++) ++ x2 = __atomic_exchange_n (&x, x2, __ATOMIC_SEQ_CST); ++ return NULL; ++} ++ ++void ++test (void) ++{ ++ x = 0; ++ x1 = 1; ++ x2 = 2; ++ pthread_t w1, w2; ++ if (pthread_create (&w1, NULL, work1, NULL) != 0) ++ __builtin_abort (); ++ if (pthread_create (&w2, NULL, work2, NULL) != 0) ++ __builtin_abort (); ++ if (pthread_join (w1, NULL) != 0) ++ __builtin_abort (); ++ if (pthread_join (w2, NULL) != 0) ++ __builtin_abort (); ++ if ((x ^ x1 ^ x2) != 3) ++ __builtin_abort (); ++} ++ ++int ++main () ++{ ++ int i; ++ for (i = 0; i < 10000; i++) ++ test (); ++} +diff --git a/gcc/testsuite/gcc.target/loongarch/pr107713-2.c b/gcc/testsuite/gcc.target/loongarch/pr107713-2.c +new file mode 100644 +index 000000000..82d44db3d +--- /dev/null ++++ b/gcc/testsuite/gcc.target/loongarch/pr107713-2.c +@@ -0,0 +1,9 @@ ++/* { dg-do compile } */ ++/* { dg-options "-O2" } */ ++/* { dg-final { scan-assembler-times "beq|bne" 1 } } */ ++ ++char ++t (char *p, char x) ++{ ++ return __atomic_exchange_n (p, x, __ATOMIC_RELAXED); ++} +-- +2.27.0 + diff --git a/gcc.spec b/gcc.spec index fad6ea20817c963e22fe21e4b8e05f93a1b28d76..e6b29f629007b59363e1b3bbae7fbfb07c6a2177 100644 --- a/gcc.spec +++ b/gcc.spec @@ -1,4 +1,4 @@ -%define anolis_release .0.1 +%define anolis_release .0.2 %global DATE 20210514 %global gitrev a3253c88425835d5b339d6998a1110a66ccd8b44 %global gcc_version 8.5.0 @@ -301,6 +301,9 @@ Patch10000: 0001-gcc-anolis-Rebrand-for-OpenAnolis.patch Patch1003: 0001-Add-LoongArch-support-for-anolis-a8-gcc.patch Patch1004: 0002-loongarch-fix-multilib-osdirnames-to-lib64.patch +Patch1005: 0001-LoongArch-Fixup-configure-file-error.patch +Patch1006: 0002-LoongArch-Rename-config-file-for-loongarch.patch +Patch1007: LoongArch-Fix-atomic_exchange-expanding-PR107713.patch # On ARM EABI systems, we do want -gnueabi to be part of the @@ -928,6 +931,9 @@ rm -f gcc/testsuite/go.test/test/chan/goroutines.go %ifarch loongarch64 %patch1003 -p1 %patch1004 -p1 +%patch1005 -p1 +%patch1006 -p1 +%patch1007 -p1 %endif %build @@ -3234,6 +3240,11 @@ fi %endif %changelog +* Fri Dec 2 2022 Xing Li 8.5.0-10.1.0.2 +- Fixup LoongArch configure file error. (lixing@loongson.cn) +- Rename mt config file for LoongArch . (lixing@loongson.cn) +- Fixup LoongArch atomic_exchange error . (lixing@loongson.cn) + * Tue Jul 5 2022 Xue haolin 8.5.0-10.1.0.1 - Rebrand for Anolis OS. (xuehaolin@openanolis.org) - Add loongarch support. (lixing@loongson.cn)