diff --git a/bsp/hc32f4a0/.config b/bsp/hc32f4a0/.config new file mode 100644 index 0000000000000000000000000000000000000000..bd8816050a218e3d80082411300692aedc467d10 --- /dev/null +++ b/bsp/hc32f4a0/.config @@ -0,0 +1,533 @@ +# +# Automatically generated file; DO NOT EDIT. +# RT-Thread Project Configuration +# + +# +# RT-Thread Kernel +# +CONFIG_RT_NAME_MAX=8 +# CONFIG_RT_USING_ARCH_DATA_TYPE is not set +# CONFIG_RT_USING_SMP is not set +CONFIG_RT_ALIGN_SIZE=4 +# CONFIG_RT_THREAD_PRIORITY_8 is not set +CONFIG_RT_THREAD_PRIORITY_32=y +# CONFIG_RT_THREAD_PRIORITY_256 is not set +CONFIG_RT_THREAD_PRIORITY_MAX=32 +CONFIG_RT_TICK_PER_SECOND=1000 +CONFIG_RT_USING_OVERFLOW_CHECK=y +CONFIG_RT_USING_HOOK=y +CONFIG_RT_USING_IDLE_HOOK=y +CONFIG_RT_IDLE_HOOK_LIST_SIZE=4 +CONFIG_IDLE_THREAD_STACK_SIZE=256 +CONFIG_RT_USING_TIMER_SOFT=y +CONFIG_RT_TIMER_THREAD_PRIO=4 +CONFIG_RT_TIMER_THREAD_STACK_SIZE=512 +CONFIG_RT_DEBUG=y +# CONFIG_RT_DEBUG_COLOR is not set +# CONFIG_RT_DEBUG_INIT_CONFIG is not set +# CONFIG_RT_DEBUG_THREAD_CONFIG is not set +# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set +# CONFIG_RT_DEBUG_IPC_CONFIG is not set +# CONFIG_RT_DEBUG_TIMER_CONFIG is not set +# CONFIG_RT_DEBUG_IRQ_CONFIG is not set +# CONFIG_RT_DEBUG_MEM_CONFIG is not set +# CONFIG_RT_DEBUG_SLAB_CONFIG is not set +# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set +# CONFIG_RT_DEBUG_MODULE_CONFIG is not set + +# +# Inter-Thread communication +# +CONFIG_RT_USING_SEMAPHORE=y +CONFIG_RT_USING_MUTEX=y +CONFIG_RT_USING_EVENT=y +CONFIG_RT_USING_MAILBOX=y +CONFIG_RT_USING_MESSAGEQUEUE=y +# CONFIG_RT_USING_SIGNALS is not set + +# +# Memory Management +# +CONFIG_RT_USING_MEMPOOL=y +# CONFIG_RT_USING_MEMHEAP is not set +# CONFIG_RT_USING_NOHEAP is not set +CONFIG_RT_USING_SMALL_MEM=y +# CONFIG_RT_USING_SLAB is not set +# CONFIG_RT_USING_USERHEAP is not set +# CONFIG_RT_USING_MEMTRACE is not set +CONFIG_RT_USING_HEAP=y + +# +# Kernel Device Object +# +CONFIG_RT_USING_DEVICE=y +# CONFIG_RT_USING_DEVICE_OPS is not set +# CONFIG_RT_USING_INTERRUPT_INFO is not set +CONFIG_RT_USING_CONSOLE=y +CONFIG_RT_CONSOLEBUF_SIZE=128 +CONFIG_RT_CONSOLE_DEVICE_NAME="uart1" +CONFIG_RT_VER_NUM=0x40003 +CONFIG_ARCH_ARM=y +CONFIG_RT_USING_CPU_FFS=y +CONFIG_ARCH_ARM_CORTEX_M=y +CONFIG_ARCH_ARM_CORTEX_M4=y +# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set + +# +# RT-Thread Components +# +CONFIG_RT_USING_COMPONENTS_INIT=y +CONFIG_RT_USING_USER_MAIN=y +CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048 +CONFIG_RT_MAIN_THREAD_PRIORITY=10 + +# +# C++ features +# +# CONFIG_RT_USING_CPLUSPLUS is not set + +# +# Command shell +# +CONFIG_RT_USING_FINSH=y +CONFIG_FINSH_THREAD_NAME="tshell" +CONFIG_FINSH_USING_HISTORY=y +CONFIG_FINSH_HISTORY_LINES=5 +CONFIG_FINSH_USING_SYMTAB=y +CONFIG_FINSH_USING_DESCRIPTION=y +# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set +CONFIG_FINSH_THREAD_PRIORITY=20 +CONFIG_FINSH_THREAD_STACK_SIZE=4096 +CONFIG_FINSH_CMD_SIZE=80 +# CONFIG_FINSH_USING_AUTH is not set +CONFIG_FINSH_USING_MSH=y +CONFIG_FINSH_USING_MSH_DEFAULT=y +# CONFIG_FINSH_USING_MSH_ONLY is not set +CONFIG_FINSH_ARG_MAX=10 + +# +# Device virtual file system +# +CONFIG_RT_USING_DFS=y +CONFIG_DFS_USING_WORKDIR=y +CONFIG_DFS_FILESYSTEMS_MAX=2 +CONFIG_DFS_FILESYSTEM_TYPES_MAX=2 +CONFIG_DFS_FD_MAX=16 +# CONFIG_RT_USING_DFS_MNTTABLE is not set +# CONFIG_RT_USING_DFS_ELMFAT is not set +CONFIG_RT_USING_DFS_DEVFS=y +# CONFIG_RT_USING_DFS_ROMFS is not set +# CONFIG_RT_USING_DFS_RAMFS is not set +# CONFIG_RT_USING_DFS_UFFS is not set +# CONFIG_RT_USING_DFS_JFFS2 is not set + +# +# Device Drivers +# +CONFIG_RT_USING_DEVICE_IPC=y +CONFIG_RT_PIPE_BUFSZ=512 +# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set +CONFIG_RT_USING_SERIAL=y +CONFIG_RT_SERIAL_USING_DMA=y +CONFIG_RT_SERIAL_RB_BUFSZ=64 +# CONFIG_RT_USING_CAN is not set +# CONFIG_RT_USING_HWTIMER is not set +# CONFIG_RT_USING_CPUTIME is not set +# CONFIG_RT_USING_I2C is not set +# CONFIG_RT_USING_PHY is not set +CONFIG_RT_USING_PIN=y +# CONFIG_RT_USING_ADC is not set +# CONFIG_RT_USING_DAC is not set +# CONFIG_RT_USING_PWM is not set +# CONFIG_RT_USING_MTD_NOR is not set +# CONFIG_RT_USING_MTD_NAND is not set +# CONFIG_RT_USING_PM is not set +# CONFIG_RT_USING_RTC is not set +# CONFIG_RT_USING_SDIO is not set +# CONFIG_RT_USING_SPI is not set +# CONFIG_RT_USING_WDT is not set +# CONFIG_RT_USING_AUDIO is not set +# CONFIG_RT_USING_SENSOR is not set +# CONFIG_RT_USING_TOUCH is not set +# CONFIG_RT_USING_HWCRYPTO is not set +# CONFIG_RT_USING_PULSE_ENCODER is not set +# CONFIG_RT_USING_INPUT_CAPTURE is not set +# CONFIG_RT_USING_WIFI is not set + +# +# Using USB +# +# CONFIG_RT_USING_USB_HOST is not set +# CONFIG_RT_USING_USB_DEVICE is not set + +# +# POSIX layer and C standard library +# +CONFIG_RT_USING_LIBC=y +# CONFIG_RT_USING_PTHREADS is not set +CONFIG_RT_USING_POSIX=y +# CONFIG_RT_USING_POSIX_MMAP is not set +# CONFIG_RT_USING_POSIX_TERMIOS is not set +# CONFIG_RT_USING_POSIX_GETLINE is not set +# CONFIG_RT_USING_POSIX_AIO is not set +# CONFIG_RT_USING_MODULE is not set + +# +# Network +# + +# +# Socket abstraction layer +# +# CONFIG_RT_USING_SAL is not set + +# +# Network interface device +# +# CONFIG_RT_USING_NETDEV is not set + +# +# light weight TCP/IP stack +# +# CONFIG_RT_USING_LWIP is not set + +# +# AT commands +# +# CONFIG_RT_USING_AT is not set + +# +# VBUS(Virtual Software BUS) +# +# CONFIG_RT_USING_VBUS is not set + +# +# Utilities +# +# CONFIG_RT_USING_RYM is not set +# CONFIG_RT_USING_ULOG is not set +# CONFIG_RT_USING_UTEST is not set +# CONFIG_RT_USING_LWP is not set + +# +# RT-Thread online packages +# + +# +# IoT - internet of things +# +# CONFIG_PKG_USING_LORAWAN_DRIVER is not set +# CONFIG_PKG_USING_PAHOMQTT is not set +# CONFIG_PKG_USING_UMQTT is not set +# CONFIG_PKG_USING_WEBCLIENT is not set +# CONFIG_PKG_USING_WEBNET is not set +# CONFIG_PKG_USING_MONGOOSE is not set +# CONFIG_PKG_USING_MYMQTT is not set +# CONFIG_PKG_USING_KAWAII_MQTT is not set +# CONFIG_PKG_USING_BC28_MQTT is not set +# CONFIG_PKG_USING_WEBTERMINAL is not set +# CONFIG_PKG_USING_CJSON is not set +# CONFIG_PKG_USING_JSMN is not set +# CONFIG_PKG_USING_LIBMODBUS is not set +# CONFIG_PKG_USING_FREEMODBUS is not set +# CONFIG_PKG_USING_LJSON is not set +# CONFIG_PKG_USING_EZXML is not set +# CONFIG_PKG_USING_NANOPB is not set + +# +# Wi-Fi +# + +# +# Marvell WiFi +# +# CONFIG_PKG_USING_WLANMARVELL is not set + +# +# Wiced WiFi +# +# CONFIG_PKG_USING_WLAN_WICED is not set +# CONFIG_PKG_USING_RW007 is not set +# CONFIG_PKG_USING_COAP is not set +# CONFIG_PKG_USING_NOPOLL is not set +# CONFIG_PKG_USING_NETUTILS is not set +# CONFIG_PKG_USING_CMUX is not set +# CONFIG_PKG_USING_PPP_DEVICE is not set +# CONFIG_PKG_USING_AT_DEVICE is not set +# CONFIG_PKG_USING_ATSRV_SOCKET is not set +# CONFIG_PKG_USING_WIZNET is not set + +# +# IoT Cloud +# +# CONFIG_PKG_USING_ONENET is not set +# CONFIG_PKG_USING_GAGENT_CLOUD is not set +# CONFIG_PKG_USING_ALI_IOTKIT is not set +# CONFIG_PKG_USING_AZURE is not set +# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set +# CONFIG_PKG_USING_JIOT-C-SDK is not set +# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set +# CONFIG_PKG_USING_JOYLINK is not set +# CONFIG_PKG_USING_NIMBLE is not set +# CONFIG_PKG_USING_OTA_DOWNLOADER is not set +# CONFIG_PKG_USING_IPMSG is not set +# CONFIG_PKG_USING_LSSDP is not set +# CONFIG_PKG_USING_AIRKISS_OPEN is not set +# CONFIG_PKG_USING_LIBRWS is not set +# CONFIG_PKG_USING_TCPSERVER is not set +# CONFIG_PKG_USING_PROTOBUF_C is not set +# CONFIG_PKG_USING_ONNX_PARSER is not set +# CONFIG_PKG_USING_ONNX_BACKEND is not set +# CONFIG_PKG_USING_DLT645 is not set +# CONFIG_PKG_USING_QXWZ is not set +# CONFIG_PKG_USING_SMTP_CLIENT is not set +# CONFIG_PKG_USING_ABUP_FOTA is not set +# CONFIG_PKG_USING_LIBCURL2RTT is not set +# CONFIG_PKG_USING_CAPNP is not set +# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set +# CONFIG_PKG_USING_AGILE_TELNET is not set +# CONFIG_PKG_USING_NMEALIB is not set +# CONFIG_PKG_USING_AGILE_JSMN is not set +# CONFIG_PKG_USING_PDULIB is not set +# CONFIG_PKG_USING_BTSTACK is not set +# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set +# CONFIG_PKG_USING_WAYZ_IOTKIT is not set + +# +# security packages +# +# CONFIG_PKG_USING_MBEDTLS is not set +# CONFIG_PKG_USING_libsodium is not set +# CONFIG_PKG_USING_TINYCRYPT is not set +# CONFIG_PKG_USING_TFM is not set +# CONFIG_PKG_USING_YD_CRYPTO is not set + +# +# language packages +# +# CONFIG_PKG_USING_LUA is not set +# CONFIG_PKG_USING_JERRYSCRIPT is not set +# CONFIG_PKG_USING_MICROPYTHON is not set + +# +# multimedia packages +# +# CONFIG_PKG_USING_OPENMV is not set +# CONFIG_PKG_USING_MUPDF is not set +# CONFIG_PKG_USING_STEMWIN is not set +# CONFIG_PKG_USING_WAVPLAYER is not set +# CONFIG_PKG_USING_TJPGD is not set +# CONFIG_PKG_USING_HELIX is not set +# CONFIG_PKG_USING_AZUREGUIX is not set +# CONFIG_PKG_USING_TOUCHGFX2RTT is not set + +# +# tools packages +# +# CONFIG_PKG_USING_CMBACKTRACE is not set +# CONFIG_PKG_USING_EASYFLASH is not set +# CONFIG_PKG_USING_EASYLOGGER is not set +# CONFIG_PKG_USING_SYSTEMVIEW is not set +# CONFIG_PKG_USING_RDB is not set +# CONFIG_PKG_USING_QRCODE is not set +# CONFIG_PKG_USING_ULOG_EASYFLASH is not set +# CONFIG_PKG_USING_ADBD is not set +# CONFIG_PKG_USING_COREMARK is not set +# CONFIG_PKG_USING_DHRYSTONE is not set +# CONFIG_PKG_USING_MEMORYPERF is not set +# CONFIG_PKG_USING_NR_MICRO_SHELL is not set +# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set +# CONFIG_PKG_USING_LUNAR_CALENDAR is not set +# CONFIG_PKG_USING_BS8116A is not set +# CONFIG_PKG_USING_GPS_RMC is not set +# CONFIG_PKG_USING_URLENCODE is not set +# CONFIG_PKG_USING_UMCN is not set +# CONFIG_PKG_USING_LWRB2RTT is not set +# CONFIG_PKG_USING_CPU_USAGE is not set +# CONFIG_PKG_USING_GBK2UTF8 is not set +# CONFIG_PKG_USING_VCONSOLE is not set + +# +# system packages +# +# CONFIG_PKG_USING_GUIENGINE is not set +# CONFIG_PKG_USING_PERSIMMON is not set +# CONFIG_PKG_USING_CAIRO is not set +# CONFIG_PKG_USING_PIXMAN is not set +# CONFIG_PKG_USING_LWEXT4 is not set +# CONFIG_PKG_USING_PARTITION is not set +# CONFIG_PKG_USING_FAL is not set +# CONFIG_PKG_USING_FLASHDB is not set +# CONFIG_PKG_USING_SQLITE is not set +# CONFIG_PKG_USING_RTI is not set +# CONFIG_PKG_USING_LITTLEVGL2RTT is not set +# CONFIG_PKG_USING_CMSIS is not set +# CONFIG_PKG_USING_DFS_YAFFS is not set +# CONFIG_PKG_USING_LITTLEFS is not set +# CONFIG_PKG_USING_THREAD_POOL is not set +# CONFIG_PKG_USING_ROBOTS is not set +# CONFIG_PKG_USING_EV is not set +# CONFIG_PKG_USING_SYSWATCH is not set +# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set +# CONFIG_PKG_USING_PLCCORE is not set +# CONFIG_PKG_USING_RAMDISK is not set +# CONFIG_PKG_USING_MININI is not set +# CONFIG_PKG_USING_QBOOT is not set + +# +# Micrium: Micrium software products porting for RT-Thread +# +# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set +# CONFIG_PKG_USING_UCOSII_WRAPPER is not set +# CONFIG_PKG_USING_UC_CRC is not set +# CONFIG_PKG_USING_UC_CLK is not set +# CONFIG_PKG_USING_UC_COMMON is not set +# CONFIG_PKG_USING_UC_MODBUS is not set +# CONFIG_PKG_USING_PPOOL is not set + +# +# peripheral libraries and drivers +# +# CONFIG_PKG_USING_SENSORS_DRIVERS is not set +# CONFIG_PKG_USING_REALTEK_AMEBA is not set +# CONFIG_PKG_USING_SHT2X is not set +# CONFIG_PKG_USING_SHT3X is not set +# CONFIG_PKG_USING_STM32_SDIO is not set +# CONFIG_PKG_USING_ICM20608 is not set +# CONFIG_PKG_USING_U8G2 is not set +# CONFIG_PKG_USING_BUTTON is not set +# CONFIG_PKG_USING_PCF8574 is not set +# CONFIG_PKG_USING_SX12XX is not set +# CONFIG_PKG_USING_SIGNAL_LED is not set +# CONFIG_PKG_USING_LEDBLINK is not set +# CONFIG_PKG_USING_LITTLED is not set +# CONFIG_PKG_USING_LKDGUI is not set +# CONFIG_PKG_USING_NRF5X_SDK is not set +# CONFIG_PKG_USING_NRFX is not set +# CONFIG_PKG_USING_WM_LIBRARIES is not set +# CONFIG_PKG_USING_KENDRYTE_SDK is not set +# CONFIG_PKG_USING_INFRARED is not set +# CONFIG_PKG_USING_ROSSERIAL is not set +# CONFIG_PKG_USING_AGILE_BUTTON is not set +# CONFIG_PKG_USING_AGILE_LED is not set +# CONFIG_PKG_USING_AT24CXX is not set +# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set +# CONFIG_PKG_USING_AD7746 is not set +# CONFIG_PKG_USING_PCA9685 is not set +# CONFIG_PKG_USING_I2C_TOOLS is not set +# CONFIG_PKG_USING_NRF24L01 is not set +# CONFIG_PKG_USING_TOUCH_DRIVERS is not set +# CONFIG_PKG_USING_MAX17048 is not set +# CONFIG_PKG_USING_RPLIDAR is not set +# CONFIG_PKG_USING_AS608 is not set +# CONFIG_PKG_USING_RC522 is not set +# CONFIG_PKG_USING_WS2812B is not set +# CONFIG_PKG_USING_EMBARC_BSP is not set +# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set +# CONFIG_PKG_USING_MULTI_RTIMER is not set +# CONFIG_PKG_USING_MAX7219 is not set +# CONFIG_PKG_USING_BEEP is not set +# CONFIG_PKG_USING_EASYBLINK is not set +# CONFIG_PKG_USING_PMS_SERIES is not set +# CONFIG_PKG_USING_CAN_YMODEM is not set +# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set +# CONFIG_PKG_USING_QLED is not set +# CONFIG_PKG_USING_PAJ7620 is not set +# CONFIG_PKG_USING_AGILE_CONSOLE is not set +# CONFIG_PKG_USING_LD3320 is not set +# CONFIG_PKG_USING_WK2124 is not set +# CONFIG_PKG_USING_LY68L6400 is not set +# CONFIG_PKG_USING_DM9051 is not set +# CONFIG_PKG_USING_SSD1306 is not set +# CONFIG_PKG_USING_QKEY is not set +# CONFIG_PKG_USING_RS485 is not set +# CONFIG_PKG_USING_NES is not set +# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set +# CONFIG_PKG_USING_VDEVICE is not set + +# +# miscellaneous packages +# +# CONFIG_PKG_USING_LIBCSV is not set +# CONFIG_PKG_USING_OPTPARSE is not set +# CONFIG_PKG_USING_FASTLZ is not set +# CONFIG_PKG_USING_MINILZO is not set +# CONFIG_PKG_USING_QUICKLZ is not set +# CONFIG_PKG_USING_LZMA is not set +# CONFIG_PKG_USING_MULTIBUTTON is not set +# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set +# CONFIG_PKG_USING_CANFESTIVAL is not set +# CONFIG_PKG_USING_ZLIB is not set +# CONFIG_PKG_USING_DSTR is not set +# CONFIG_PKG_USING_TINYFRAME is not set +# CONFIG_PKG_USING_KENDRYTE_DEMO is not set +# CONFIG_PKG_USING_DIGITALCTRL is not set +# CONFIG_PKG_USING_UPACKER is not set +# CONFIG_PKG_USING_UPARAM is not set + +# +# samples: kernel and components samples +# +# CONFIG_PKG_USING_KERNEL_SAMPLES is not set +# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set +# CONFIG_PKG_USING_NETWORK_SAMPLES is not set +# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set +# CONFIG_PKG_USING_HELLO is not set +# CONFIG_PKG_USING_VI is not set +# CONFIG_PKG_USING_KI is not set +# CONFIG_PKG_USING_NNOM is not set +# CONFIG_PKG_USING_LIBANN is not set +# CONFIG_PKG_USING_ELAPACK is not set +# CONFIG_PKG_USING_ARMv7M_DWT is not set +# CONFIG_PKG_USING_VT100 is not set +# CONFIG_PKG_USING_ULAPACK is not set +# CONFIG_PKG_USING_UKAL is not set +# CONFIG_PKG_USING_CRCLIB is not set + +# +# games: games run on RT-Thread console +# +# CONFIG_PKG_USING_THREES is not set +# CONFIG_PKG_USING_2048 is not set +# CONFIG_PKG_USING_SNAKE is not set +# CONFIG_PKG_USING_TETRIS is not set +# CONFIG_PKG_USING_LWGPS is not set +# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set + +# +# Hardware Drivers Config +# +CONFIG_MCU_HC32F4A0=y + +# +# Onboard Peripheral Drivers +# + +# +# On-chip Peripheral Drivers +# +CONFIG_BSP_USING_GPIO=y +CONFIG_BSP_USING_UART=y +CONFIG_BSP_USING_UART1=y +CONFIG_BSP_UART1_RX_USING_DMA=y +CONFIG_BSP_UART1_TX_USING_DMA=y +# CONFIG_BSP_USING_UART2 is not set +# CONFIG_BSP_USING_UART3 is not set +# CONFIG_BSP_USING_UART4 is not set +# CONFIG_BSP_USING_UART5 is not set +# CONFIG_BSP_USING_UART6 is not set +# CONFIG_BSP_USING_UART7 is not set +# CONFIG_BSP_USING_UART8 is not set +# CONFIG_BSP_USING_UART9 is not set +# CONFIG_BSP_USING_UART10 is not set +# CONFIG_BSP_USING_I2C1 is not set +# CONFIG_BSP_USING_SPI is not set +# CONFIG_BSP_USING_RTC is not set +# CONFIG_BSP_USING_PWM is not set +# CONFIG_BSP_USING_TIMER is not set +# CONFIG_BSP_USING_PULSE_ENCODER is not set + +# +# Board extended module Drivers +# diff --git a/bsp/hc32f4a0/.gitignore b/bsp/hc32f4a0/.gitignore new file mode 100644 index 0000000000000000000000000000000000000000..7221bde019df6157cbf9e42ef5ab8a78420e3b68 --- /dev/null +++ b/bsp/hc32f4a0/.gitignore @@ -0,0 +1,42 @@ +*.pyc +*.map +*.dblite +*.elf +*.bin +*.hex +*.axf +*.exe +*.pdb +*.idb +*.ilk +*.old +build +Debug +documentation/html +packages/ +*~ +*.o +*.obj +*.out +*.bak +*.dep +*.lib +*.i +*.d +.DS_Stor* +.config 3 +.config 4 +.config 5 +Midea-X1 +*.uimg +GPATH +GRTAGS +GTAGS +.vscode +JLinkLog.txt +JLinkSettings.ini +DebugConfig/ +RTE/ +settings/ +*.uvguix* +cconfig.h diff --git a/bsp/hc32f4a0/Kconfig b/bsp/hc32f4a0/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..f4ed99b3fa61b46daa8b57f7fc82c548b10f39f8 --- /dev/null +++ b/bsp/hc32f4a0/Kconfig @@ -0,0 +1,23 @@ +mainmenu "RT-Thread Project Configuration" + +config BSP_DIR + string + option env="BSP_ROOT" + default "." + +config RTT_DIR + string + option env="RTT_ROOT" + default "../.." + +config PKGS_DIR + string + option env="PKGS_ROOT" + default "packages" + +source "$RTT_DIR/Kconfig" +source "$PKGS_DIR/Kconfig" +source "board/Kconfig" + + + diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/ddl_config.h b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/ddl_config.h new file mode 100644 index 0000000000000000000000000000000000000000..980e6cb20568e20f0e3a7d2d773f863a262d84d9 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/ddl_config.h @@ -0,0 +1,214 @@ +/** + ******************************************************************************* + * @file adc/adc_01_base/source/ddl_config.h + * @brief This file contains HC32 Series Device Driver Library usage management. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __DDL_CONFIG_H__ +#define __DDL_CONFIG_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Chip module on-off define */ +#define DDL_ON (1U) +#define DDL_OFF (0U) + +/** + * @brief This is the list of modules to be used in the Device Driver Library. + * Select the modules you need to use to DDL_ON. + * @note DDL_ICG_ENABLE must be turned on(DDL_ON) to ensure that the chip works + * properly. + * @note DDL_UTILITY_ENABLE must be turned on(DDL_ON) if using Device Driver + * Library. + * @note DDL_PRINT_ENABLE must be turned on(DDL_ON) if using printf function. + */ +#define DDL_ICG_ENABLE (DDL_ON) +#define DDL_UTILITY_ENABLE (DDL_ON) +#define DDL_PRINT_ENABLE (DDL_ON) + +#define DDL_ADC_ENABLE (DDL_ON) +#define DDL_AES_ENABLE (DDL_ON) +#define DDL_CAN_ENABLE (DDL_ON) +#define DDL_CLK_ENABLE (DDL_ON) +#define DDL_CMP_ENABLE (DDL_ON) +#define DDL_CRC_ENABLE (DDL_ON) +#define DDL_CTC_ENABLE (DDL_ON) +#define DDL_DAC_ENABLE (DDL_ON) +#define DDL_DCU_ENABLE (DDL_ON) +#define DDL_DMA_ENABLE (DDL_ON) +#define DDL_DMC_ENABLE (DDL_ON) +#define DDL_DVP_ENABLE (DDL_ON) +#define DDL_EFM_ENABLE (DDL_ON) +#define DDL_EMB_ENABLE (DDL_ON) +#define DDL_ETH_ENABLE (DDL_ON) +#define DDL_EVENT_PORT_ENABLE (DDL_OFF) +#define DDL_FCM_ENABLE (DDL_ON) +#define DDL_FMAC_ENABLE (DDL_ON) +#define DDL_GPIO_ENABLE (DDL_ON) +#define DDL_HASH_ENABLE (DDL_ON) +#define DDL_HRPWM_ENABLE (DDL_ON) +#define DDL_I2C_ENABLE (DDL_ON) +#define DDL_I2S_ENABLE (DDL_ON) +#define DDL_INTERRUPTS_ENABLE (DDL_ON) +#define DDL_KEYSCAN_ENABLE (DDL_ON) +#define DDL_MAU_ENABLE (DDL_ON) +#define DDL_MPU_ENABLE (DDL_ON) +#define DDL_NFC_ENABLE (DDL_ON) +#define DDL_OTS_ENABLE (DDL_ON) +#define DDL_PWC_ENABLE (DDL_ON) +#define DDL_QSPI_ENABLE (DDL_ON) +#define DDL_RMU_ENABLE (DDL_ON) +#define DDL_RTC_ENABLE (DDL_ON) +#define DDL_SDIOC_ENABLE (DDL_ON) +#define DDL_SMC_ENABLE (DDL_ON) +#define DDL_SPI_ENABLE (DDL_ON) +#define DDL_SRAM_ENABLE (DDL_ON) +#define DDL_SWDT_ENABLE (DDL_ON) +#define DDL_TMR0_ENABLE (DDL_ON) +#define DDL_TMR2_ENABLE (DDL_ON) +#define DDL_TMR4_ENABLE (DDL_ON) +#define DDL_TMR6_ENABLE (DDL_ON) +#define DDL_TMRA_ENABLE (DDL_ON) +#define DDL_TRNG_ENABLE (DDL_ON) +#define DDL_USART_ENABLE (DDL_ON) +#define DDL_USBFS_ENABLE (DDL_OFF) +#define DDL_USBHS_ENABLE (DDL_OFF) +#define DDL_WDT_ENABLE (DDL_ON) + +/* BSP on-off define */ +#define BSP_ON (1U) +#define BSP_OFF (0U) + +/** + * @brief The following is a list of currently supported BSP boards. + */ +#define BSP_EV_HC32F4A0_LQFP176 (1U) +#define BSP_MS_HC32F4A0_LQFP176_050_MEM (2U) + +/** + * @brief The macro BSP_EV_HC32F4A0 is used to specify the BSP board currently + * in use. + * The value should be set to one of the list of currently supported BSP boards. + * @note If there is no supported BSP board or the BSP function is not used, + * the value needs to be set to BSP_EV_HC32F4A0. + */ +#define BSP_EV_HC32F4A0 (BSP_EV_HC32F4A0) + +/** + * @brief This is the list of BSP components to be used. + * Select the components you need to use to BSP_ON. + */ +#define BSP_CY62167EV30LL_ENABLE (BSP_OFF) +#define BSP_IS42S16400J7TLI_ENABLE (BSP_OFF) +#define BSP_IS62WV51216_ENABLE (BSP_OFF) +#define BSP_MT29F2G08AB_ENABLE (BSP_OFF) +#define BSP_NT35510_ENABLE (BSP_OFF) +#define BSP_OV5640_ENABLE (BSP_OFF) +#define BSP_S29GL064N90TFI03_ENABLE (BSP_OFF) +#define BSP_TCA9539_ENABLE (BSP_OFF) +#define BSP_W25QXX_ENABLE (BSP_OFF) +#define BSP_WM8731_ENABLE (BSP_OFF) + +/** + * @brief Ethernet and PHY Configuration. + * @note PHY delay these values are based on a 1 ms Systick interrupt. + */ +/* MAC ADDRESS */ +#define ETH_MAC_ADDR0 (2U) +#define ETH_MAC_ADDR1 (0U) +#define ETH_MAC_ADDR2 (0U) +#define ETH_MAC_ADDR3 (0U) +#define ETH_MAC_ADDR4 (0U) +#define ETH_MAC_ADDR5 (0U) + +/* Ethernet driver buffers size and count */ +#define ETH_TXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for receive */ +#define ETH_RXBUF_SIZE (ETH_PACKET_MAX_SIZE) /* Buffer size for transmit */ +#define ETH_TXBUF_NUMBER (4UL) /* 4 Rx buffers of size ETH_RX_BUF_SIZE */ +#define ETH_RXBUF_NUMBER (4UL) /* 4 Tx buffers of size ETH_TX_BUF_SIZE */ + +/* PHY Address*/ +#define PHY_ADDRESS (0x00U) /* RTL8201F */ + +/* PHY Configuration delay */ +#define PHY_HW_RESET_DELAY (0x0000003FUL) +#define PHY_RESET_DELAY (0x0000007FUL) +#define PHY_CONFIG_DELAY (0x0000003FUL) +#define PHY_READ_TIMEOUT (0x00000005UL) +#define PHY_WRITE_TIMEOUT (0x00000005UL) + +/* Common PHY Registers */ +#define PHY_BCR (0x00U) /*!< Basic Control Register */ +#define PHY_BSR (0x01U) /*!< Basic Status Register */ + +#define PHY_SOFT_RESET (0x8000U) /*!< PHY Soft Reset */ +#define PHY_LOOPBACK (0x4000U) /*!< Select loop-back mode */ +#define PHY_FULLDUPLEX_100M (0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ +#define PHY_HALFDUPLEX_100M (0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ +#define PHY_FULLDUPLEX_10M (0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ +#define PHY_HALFDUPLEX_10M (0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ +#define PHY_AUTONEGOTIATION (0x1000U) /*!< Enable auto-negotiation function */ +#define PHY_POWERDOWN (0x0800U) /*!< Select the power down mode */ +#define PHY_ISOLATE (0x0400U) /*!< Isolate PHY from MII */ +#define PHY_RESTART_AUTONEGOTIATION (0x0200U) /*!< Restart auto-negotiation function */ + +#define PHY_100BASE_TX_FD (0x4000U) /*!< 100Base-TX full duplex support */ +#define PHY_100BASE_TX_HD (0x2000U) /*!< 100Base-TX half duplex support */ +#define PHY_10BASE_T_FD (0x1000U) /*!< 10Base-T full duplex support */ +#define PHY_10BASE_T_HD (0x0800U) /*!< 10Base-T half duplex support */ +#define PHY_AUTONEGO_COMPLETE (0x0020U) /*!< Auto-Negotiation process completed */ +#define PHY_LINK_STATUS (0x0004U) /*!< Valid link established */ +#define PHY_JABBER_DETECTION (0x0002U) /*!< Jabber condition detected */ + +/** + * @brief External clock source for I2S peripheral + */ +#ifndef I2S_EXT_CLK_FREQ + #define I2S_EXT_CLK_FREQ (12288000UL) /*!< Value of the external oscillator */ +#endif /* I2S_EXT_CLK_FREQ */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __DDL_CONFIG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32_common.h b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32_common.h new file mode 100644 index 0000000000000000000000000000000000000000..12e7b2ecdc6b6913e0717fb75a61b9c2130afc4e --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32_common.h @@ -0,0 +1,319 @@ +/** + ******************************************************************************* + * @file hc32_common.h + * @brief This file contains the common part of the HC32 series. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-09-07 Yangjp Add the precompiled configuration of ARM compiler V6 + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_COMMON_H__ +#define __HC32_COMMON_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32_Common_Part + * @{ + */ + +/** + * @brief HC32 Common Device Include + */ +#if defined(HC32F120) + #include "hc32f120.h" + #include "system_hc32f120.h" +#elif defined(HC32F4A0) + #include "hc32f4a0.h" + #include "system_hc32f4a0.h" +#elif defined(HC32M120) + #include "hc32m120.h" + #include "system_hc32m120.h" +#elif defined(HC32M423) + #include "hc32m423.h" + #include "system_hc32m423.h" +#else + #error "Please select first the target HC32xxxx device used in your application (in hc32xxxx.h file)" +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup HC32_Common_Global_Types HC32 Common Global Types + * @{ + */ + +/** + * @brief Single precision floating point number (4 byte) + */ +typedef float float32_t; + +/** + * @brief Double precision floating point number (8 byte) + */ +typedef double float64_t; + +/** + * @brief Function pointer type to void/void function + */ +typedef void (*func_ptr_t)(void); + +/** + * @brief Function pointer type to void/uint8_t function + */ +typedef void (*func_ptr_arg1_t)(uint8_t); + +/** + * @brief Functional state + */ +typedef enum +{ + Disable = 0U, + Enable = 1U, +} en_functional_state_t; + +/* Check if it is a functional state */ +#define IS_FUNCTIONAL_STATE(state) (((state) == Disable) || ((state) == Enable)) + +/** + * @brief Flag status + */ +typedef enum +{ + Reset = 0U, + Set = 1U, +} en_flag_status_t, en_int_status_t; + +/** + * @brief Generic error codes + */ +typedef enum +{ + Ok = 0U, /*!< No error */ + Error = 1U, /*!< Non-specific error code */ + ErrorAddressAlignment = 2U, /*!< Address alignment does not match */ + ErrorAccessRights = 3U, /*!< Wrong mode (e.g. user/system) mode is set */ + ErrorInvalidParameter = 4U, /*!< Provided parameter is not valid */ + ErrorOperationInProgress = 5U, /*!< A conflicting or requested operation is still in progress */ + ErrorInvalidMode = 6U, /*!< Operation not allowed in current mode */ + ErrorUninitialized = 7U, /*!< Module (or part of it) was not initialized properly */ + ErrorBufferEmpty = 8U, /*!< Circular buffer can not be read because the buffer is empty */ + ErrorBufferFull = 9U, /*!< Circular buffer can not be written because the buffer is full */ + ErrorTimeout = 10U, /*!< Time Out error occurred (e.g. I2C arbitration lost, Flash time-out, etc.) */ + ErrorNotReady = 11U, /*!< A requested final state is not reached */ + OperationInProgress = 12U, /*!< Indicator for operation in progress (e.g. ADC conversion not finished, DMA channel used, etc.) */ +} en_result_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HC32_Common_Global_Macros HC32 Common Global Macros + * @{ + */ + +/** + * @brief Compiler Macro Definitions + */ +#ifndef __UNUSED + #define __UNUSED __attribute__((unused)) +#endif /* __UNUSED */ + +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __attribute__((aligned(4))) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) + /* Usage: void __RAM_FUNC foo(void) */ + #endif /* __RAM_FUNC */ + #ifndef __NO_INIT + #define __NO_INIT + #endif /* __NO_INIT */ +#elif defined ( __GNUC__ ) && !defined (__CC_ARM) /*!< GNU Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __attribute__((aligned (4))) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __attribute__((long_call, section(".ramfunc"))) + /* Usage: void __RAM_FUNC foo(void) */ + #endif /* __RAM_FUNC */ + #ifndef __NO_INIT + #define __NO_INIT __attribute__((section(".noinit"))) + #endif /* __NO_INIT */ +#elif defined (__ICCARM__) /*!< IAR Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __weak + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN _Pragma("data_alignment=4") + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE _Pragma("optimize = no_inline") + #endif /* __NOINLINE */ + #ifndef __RAM_FUNC + #define __RAM_FUNC __ramfunc + #endif /* __RAM_FUNC */ +#ifndef __NO_INIT + #define __NO_INIT __no_init +#endif /* __NO_INIT */ +#elif defined (__CC_ARM) /*!< ARM Compiler */ + #ifndef __WEAKDEF + #define __WEAKDEF __attribute__((weak)) + #endif /* __WEAKDEF */ + #ifndef __ALIGN_BEGIN + #define __ALIGN_BEGIN __align(4) + #endif /* __ALIGN_BEGIN */ + #ifndef __NOINLINE + #define __NOINLINE __attribute__((noinline)) + #endif /* __NOINLINE */ + #ifndef __NO_INIT + #define __NO_INIT + #endif /* __NO_INIT */ + /* RAM functions are defined using the toolchain options. + Functions that are executed in RAM should reside in a separate source module. + Using the 'Options for File' dialog you can simply change the 'Code / Const' + area of a module to a memory space in physical RAM. */ + #define __RAM_FUNC +#else + #error "unsupported compiler!!" +#endif + +/** + * @defgroup Extend_Macro_Definitions Extend Macro Definitions + * @{ + */ +/* Decimal to BCD */ +#define DEC2BCD(x) ((((x) / 10U) << 4U) + ((x) % 10U)) + +/* BCD to decimal */ +#define BCD2DEC(x) ((((x) >> 4U) * 10U) + ((x) & 0x0FU)) + +/* Returns the dimension of an array */ +#define ARRAY_SZ(x) ((sizeof(x)) / (sizeof((x)[0]))) +/** + * @} + */ + +/** + * @defgroup Address_Align Address Align + * @{ + */ +#define IS_ADDRESS_ALIGN(addr, align) (0UL == (((uint32_t)(addr)) & (((uint32_t)(align)) - 1UL))) +#define IS_ADDRESS_ALIGN_HALFWORD(addr) (0UL == (((uint32_t)(addr)) & 0x1UL)) +#define IS_ADDRESS_ALIGN_WORD(addr) (0UL == (((uint32_t)(addr)) & 0x3UL)) +/** + * @} + */ + +/** + * @defgroup Register_Macro_Definitions Register Macro Definitions + * @{ + */ +#define RW_MEM8(addr) (*(volatile uint8_t *)(addr)) +#define RW_MEM16(addr) (*(volatile uint16_t *)(addr)) +#define RW_MEM32(addr) (*(volatile uint32_t *)(addr)) + +#define SET_REG8_BIT(REG, BIT) ((REG) |= ((uint8_t)(BIT))) +#define SET_REG16_BIT(REG, BIT) ((REG) |= ((uint16_t)(BIT))) +#define SET_REG32_BIT(REG, BIT) ((REG) |= ((uint32_t)(BIT))) + +#define CLEAR_REG8_BIT(REG, BIT) ((REG) &= ((uint8_t)(~((uint8_t)(BIT))))) +#define CLEAR_REG16_BIT(REG, BIT) ((REG) &= ((uint16_t)(~((uint16_t)(BIT))))) +#define CLEAR_REG32_BIT(REG, BIT) ((REG) &= ((uint32_t)(~((uint32_t)(BIT))))) + +#define READ_REG8_BIT(REG, BIT) ((REG) & ((uint8_t)(BIT))) +#define READ_REG16_BIT(REG, BIT) ((REG) & ((uint16_t)(BIT))) +#define READ_REG32_BIT(REG, BIT) ((REG) & ((uint32_t)(BIT))) + +#define CLEAR_REG8(REG) ((REG) = ((uint8_t)(0U))) +#define CLEAR_REG16(REG) ((REG) = ((uint16_t)(0U))) +#define CLEAR_REG32(REG) ((REG) = ((uint32_t)(0UL))) + +#define WRITE_REG8(REG, VAL) ((REG) = ((uint8_t)(VAL))) +#define WRITE_REG16(REG, VAL) ((REG) = ((uint16_t)(VAL))) +#define WRITE_REG32(REG, VAL) ((REG) = ((uint32_t)(VAL))) + +#define READ_REG8(REG) (REG) +#define READ_REG16(REG) (REG) +#define READ_REG32(REG) (REG) + +#define MODIFY_REG8(REGS, CLEARMASK, SETMASK) (WRITE_REG8((REGS), (((READ_REG8((REGS))) & ((uint8_t)(~((uint8_t)(CLEARMASK))))) | ((uint8_t)(SETMASK) & (uint8_t)(CLEARMASK))))) +#define MODIFY_REG16(REGS, CLEARMASK, SETMASK) (WRITE_REG16((REGS), (((READ_REG16((REGS))) & ((uint16_t)(~((uint16_t)(CLEARMASK))))) | ((uint16_t)(SETMASK) & (uint16_t)(CLEARMASK))))) +#define MODIFY_REG32(REGS, CLEARMASK, SETMASK) (WRITE_REG32((REGS), (((READ_REG32((REGS))) & ((uint32_t)(~((uint32_t)(CLEARMASK))))) | ((uint32_t)(SETMASK) & (uint32_t)(CLEARMASK))))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_COMMON_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32_ddl.h b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32_ddl.h new file mode 100644 index 0000000000000000000000000000000000000000..f973175a5a649f2c7eb84ed8e3f19a4c2705060b --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32_ddl.h @@ -0,0 +1,346 @@ +/** + ******************************************************************************* + * @file hc32_ddl.h + * @brief This file contains HC32 Series Device Driver Library file call + * management. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32_DDL_H__ +#define __HC32_DDL_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Defined use Device Driver Library */ +#if !defined (USE_DDL_DRIVER) +/** + * @brief Comment the line below if you will not use the Device Driver Library. + * In this case, the application code will be based on direct access to + * peripherals registers. + */ + /* #define USE_DDL_DRIVER */ +#endif /* USE_DDL_DRIVER */ + +/** + * @brief HC32 Series Device Driver Library version number + */ +#define HC32_DDL_VERSION_MAIN 0x01U /*!< [31:24] main version */ +#define HC32_DDL_VERSION_SUB1 0x00U /*!< [23:16] sub1 version */ +#define HC32_DDL_VERSION_SUB2 0x04U /*!< [15:8] sub2 version */ +#define HC32_DDL_VERSION_RC 0x00U /*!< [7:0] release candidate */ +#define HC32_DDL_VERSION ((HC32_DDL_VERSION_MAIN << 24) | \ + (HC32_DDL_VERSION_SUB1 << 16) | \ + (HC32_DDL_VERSION_SUB2 << 8 ) | \ + (HC32_DDL_VERSION_RC)) + +/* Use Device Driver Library */ +#if defined (USE_DDL_DRIVER) + +/** + * @brief Include peripheral module's header file + */ +#if (DDL_ADC_ENABLE == DDL_ON) + #include "hc32f4a0_adc.h" +#endif /* DDL_ADC_ENABLE */ + +#if (DDL_AES_ENABLE == DDL_ON) + #include "hc32f4a0_aes.h" +#endif /* DDL_AES_ENABLE */ + +#if (DDL_CAN_ENABLE == DDL_ON) + #include "hc32f4a0_can.h" +#endif /* DDL_CAN_ENABLE */ + +#if (DDL_CLK_ENABLE == DDL_ON) + #include "hc32f4a0_clk.h" +#endif /* DDL_CLK_ENABLE */ + +#if (DDL_CMP_ENABLE == DDL_ON) + #include "hc32f4a0_cmp.h" +#endif /* DDL_CMP_ENABLE */ + +#if (DDL_CRC_ENABLE == DDL_ON) + #include "hc32f4a0_crc.h" +#endif /* DDL_CRC_ENABLE */ + +#if (DDL_CTC_ENABLE == DDL_ON) + #include "hc32f4a0_ctc.h" +#endif /* DDL_CTC_ENABLE */ + +#if (DDL_DAC_ENABLE == DDL_ON) + #include "hc32f4a0_dac.h" +#endif /* DDL_DAC_ENABLE */ + +#if (DDL_DCU_ENABLE == DDL_ON) + #include "hc32f4a0_dcu.h" +#endif /* DDL_DCU_ENABLE */ + +#if (DDL_DMA_ENABLE == DDL_ON) + #include "hc32f4a0_dma.h" +#endif /* DDL_DMA_ENABLE */ + +#if (DDL_DMC_ENABLE == DDL_ON) + #include "hc32f4a0_dmc.h" +#endif /* DDL_DMC_ENABLE */ + +#if (DDL_DVP_ENABLE == DDL_ON) + #include "hc32f4a0_dvp.h" +#endif /* DDL_DVP_ENABLE */ + +#if (DDL_EFM_ENABLE == DDL_ON) + #include "hc32f4a0_efm.h" +#endif /* DDL_EFM_ENABLE */ + +#if (DDL_EMB_ENABLE == DDL_ON) + #include "hc32f4a0_emb.h" +#endif /* DDL_EMB_ENABLE */ + +#if (DDL_ETH_ENABLE == DDL_ON) + #include "hc32f4a0_eth.h" +#endif /* DDL_ETH_ENABLE */ + +#if (DDL_EVENT_PORT_ENABLE == DDL_ON) + #include "hc32f4a0_event_port.h" +#endif /* DDL_EVENT_PORT_ENABLE */ + +#if (DDL_FCM_ENABLE == DDL_ON) + #include "hc32f4a0_fcm.h" +#endif /* DDL_FCM_ENABLE */ + +#if (DDL_FMAC_ENABLE == DDL_ON) + #include "hc32f4a0_fmac.h" +#endif /* DDL_FMAC_ENABLE */ + +#if (DDL_GPIO_ENABLE == DDL_ON) + #include "hc32f4a0_gpio.h" +#endif /* DDL_GPIO_ENABLE */ + +#if (DDL_HASH_ENABLE == DDL_ON) + #include "hc32f4a0_hash.h" +#endif /* DDL_HASH_ENABLE */ + +#if (DDL_I2C_ENABLE == DDL_ON) + #include "hc32f4a0_i2c.h" +#endif /* DDL_I2C_ENABLE */ + +#if (DDL_I2S_ENABLE == DDL_ON) + #include "hc32f4a0_i2s.h" +#endif /* DDL_I2S_ENABLE */ + +#if (DDL_ICG_ENABLE == DDL_ON) + #include "hc32f4a0_icg.h" +#endif /* DDL_ICG_ENABLE */ + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + #include "hc32f4a0_interrupts.h" +#endif /* DDL_INTERRUPTS_ENABLE */ + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + #include "hc32f4a0_keyscan.h" +#endif /* DDL_KEYSCAN_ENABLE */ + +#if (DDL_MAU_ENABLE == DDL_ON) + #include "hc32f4a0_mau.h" +#endif /* DDL_MAU_ENABLE */ + +#if (DDL_MPU_ENABLE == DDL_ON) + #include "hc32f4a0_mpu.h" +#endif /* DDL_MPU_ENABLE */ + +#if (DDL_NFC_ENABLE == DDL_ON) + #include "hc32f4a0_nfc.h" +#endif /* DDL_NFC_ENABLE */ + +#if (DDL_OTS_ENABLE == DDL_ON) + #include "hc32f4a0_ots.h" +#endif /* DDL_OTS_ENABLE */ + +#if (DDL_PWC_ENABLE == DDL_ON) + #include "hc32f4a0_pwc.h" +#endif /* DDL_PWC_ENABLE */ + +#if (DDL_QSPI_ENABLE == DDL_ON) + #include "hc32f4a0_qspi.h" +#endif /* DDL_QSPI_ENABLE */ + +#if (DDL_RMU_ENABLE == DDL_ON) + #include "hc32f4a0_rmu.h" +#endif /* DDL_RMU_ENABLE */ + +#if (DDL_RTC_ENABLE == DDL_ON) + #include "hc32f4a0_rtc.h" +#endif /* DDL_RTC_ENABLE */ + +#if (DDL_SDIOC_ENABLE == DDL_ON) + #include "hc32f4a0_sdioc.h" +#endif /* DDL_SDIOC_ENABLE */ + +#if (DDL_SMC_ENABLE == DDL_ON) + #include "hc32f4a0_smc.h" +#endif /* DDL_SMC_ENABLE */ + +#if (DDL_SPI_ENABLE == DDL_ON) + #include "hc32f4a0_spi.h" +#endif /* DDL_SPI_ENABLE */ + +#if (DDL_SRAM_ENABLE == DDL_ON) + #include "hc32f4a0_sram.h" +#endif /* DDL_SRAM_ENABLE */ + +#if (DDL_SWDT_ENABLE == DDL_ON) + #include "hc32f4a0_swdt.h" +#endif /* DDL_SWDT_ENABLE */ + +#if (DDL_TMR0_ENABLE == DDL_ON) + #include "hc32f4a0_tmr0.h" +#endif /* DDL_TMR0_ENABLE */ + +#if (DDL_TMR2_ENABLE == DDL_ON) + #include "hc32f4a0_tmr2.h" +#endif /* DDL_TMR2_ENABLE */ + +#if (DDL_TMR4_ENABLE == DDL_ON) + #include "hc32f4a0_tmr4.h" +#endif /* DDL_TMR4_ENABLE */ + +#if (DDL_TMR6_ENABLE == DDL_ON) + #include "hc32f4a0_tmr6.h" +#endif /* DDL_TMR6_ENABLE */ + +#if (DDL_TMRA_ENABLE == DDL_ON) + #include "hc32f4a0_tmra.h" +#endif /* DDL_TMRA_ENABLE */ + +#if (DDL_TRNG_ENABLE == DDL_ON) + #include "hc32f4a0_trng.h" +#endif /* DDL_TRNG_ENABLE */ + +#if (DDL_USART_ENABLE == DDL_ON) + #include "hc32f4a0_usart.h" +#endif /* DDL_USART_ENABLE */ + +#if (DDL_USBFS_ENABLE == DDL_ON) + #include "hc32f4a0_usbfs.h" +#endif /* DDL_USBFS_ENABLE */ + +#if (DDL_USBHS_ENABLE == DDL_ON) + #include "hc32f4a0_usbhs.h" +#endif /* DDL_USBHS_ENABLE */ + +#if (DDL_UTILITY_ENABLE == DDL_ON) + #include "hc32f4a0_utility.h" +#endif /* DDL_UTILITY_ENABLE */ + +#if (DDL_WDT_ENABLE == DDL_ON) + #include "hc32f4a0_wdt.h" +#endif /* DDL_WDT_ENABLE */ + +#if (DDL_HRPWM_ENABLE == DDL_ON) + #include "hc32f4a0_hrpwm.h" +#endif /* DDL_HRPWM_ENABLE */ + + +/** + * @brief Include BSP board's header file + */ +#if (BSP_EV_HC32F4A0_LQFP176 == BSP_EV_HC32F4A0) + #include "ev_hc32f4a0_lqfp176.h" +#endif /* BSP_EV_HC32F4A0_LQFP176 */ + +#if (BSP_MS_HC32F4A0_LQFP176_050_MEM == BSP_EV_HC32F4A0) + #include "ms_hc32f4a0_lqfp176_050_mem.h" +#endif /* BSP_MS_HC32F4A0_LQFP176_050_MEM */ + + +/** + * @brief Include BSP device component's header file + */ +#if (BSP_CY62167EV30LL_ENABLE == BSP_ON) + #include "cy62167ev30ll.h" +#endif /* BSP_CY62167EV30LL_ENABLE */ + +#if (BSP_IS42S16400J7TLI_ENABLE == BSP_ON) + #include "is42s16400j7tli.h" +#endif /* BSP_IS42S16400J7TLI_ENABLE */ + +#if (BSP_IS62WV51216_ENABLE == BSP_ON) + #include "is62wv51216.h" +#endif /* BSP_IS62WV51216_ENABLE */ + +#if (BSP_MT29F2G08AB_ENABLE == BSP_ON) + #include "mt29f2g08ab.h" +#endif /* BSP_MT29F2G08AB_ENABLE */ + +#if (BSP_NT35510_ENABLE == BSP_ON) + #include "nt35510.h" +#endif /* BSP_NT35510_ENABLE */ + +#if (BSP_OV5640_ENABLE == BSP_ON) + #include "ov5640.h" +#endif /* BSP_OV5640_ENABLE */ + +#if (BSP_S29GL064N90TFI03_ENABLE == BSP_ON) + #include "s29gl064n90tfi03.h" +#endif /* BSP_S29GL064N90TFI03_ENABLE */ + +#if (BSP_TCA9539_ENABLE == BSP_ON) + #include "ev_hc32f4a0_lqfp176_tca9539.h" + #include "tca9539.h" +#endif /* BSP_TCA9539_ENABLE */ + +#if (BSP_W25QXX_ENABLE == BSP_ON) + #include "w25qxx.h" +#endif /* BSP_W25QXX_ENABLE */ + +#if (BSP_WM8731_ENABLE == BSP_ON) + #include "wm8731.h" +#endif /* BSP_WM8731_ENABLE */ + +#endif /* USE_DDL_DRIVER */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32_DDL_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32f4a0.h b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32f4a0.h new file mode 100644 index 0000000000000000000000000000000000000000..c829401e3cb8d804f473865d67906ccdb7e22886 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/hc32f4a0.h @@ -0,0 +1,48442 @@ +/** + ******************************************************************************* + * @file HC32F4A0.h + * @brief Headerfile for HC32F4A0 series MCU + @verbatim + Change Logs: + Date Author Notes + 2020-09-14 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + */ + +#ifndef __HC32F4A0_H__ +#define __HC32F4A0_H__ + +#ifdef __cplusplus +extern "C" { +#endif + +/******************************************************************************* + * Configuration of the Cortex-M4 Processor and Core Peripherals + ******************************************************************************/ +#define __MPU_PRESENT 1 /*!< HC32F4A0 provides MPU */ +#define __VTOR_PRESENT 1 /*!< HC32F4A0 supported vector table registers */ +#define __NVIC_PRIO_BITS 4 /*!< HC32F4A0 uses 4 Bits for the Priority Levels */ +#define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */ +#define __FPU_PRESENT 1 /*!< FPU present */ + +/******************************************************************************* + * Interrupt Number Definition + ******************************************************************************/ +typedef enum IRQn +{ + NMI_IRQn = -14, /* 2 Non Maskable */ + HardFault_IRQn = -13, /* 3 Hard Fault */ + MemManageFault_IRQn = -12, /* 4 MemManage Fault */ + BusFault_IRQn = -11, /* 5 Bus Fault */ + UsageFault_IRQn = -10, /* 6 Usage Fault */ + SVC_IRQn = -5, /* 11 SVCall */ + DebugMonitor_IRQn = -4, /* 12 DebugMonitor */ + PendSV_IRQn = -2, /* 14 Pend SV */ + SysTick_IRQn = -1, /* 15 System Tick */ + Int000_IRQn = 0, + Int001_IRQn = 1, + Int002_IRQn = 2, + Int003_IRQn = 3, + Int004_IRQn = 4, + Int005_IRQn = 5, + Int006_IRQn = 6, + Int007_IRQn = 7, + Int008_IRQn = 8, + Int009_IRQn = 9, + Int010_IRQn = 10, + Int011_IRQn = 11, + Int012_IRQn = 12, + Int013_IRQn = 13, + Int014_IRQn = 14, + Int015_IRQn = 15, + Int016_IRQn = 16, + Int017_IRQn = 17, + Int018_IRQn = 18, + Int019_IRQn = 19, + Int020_IRQn = 20, + Int021_IRQn = 21, + Int022_IRQn = 22, + Int023_IRQn = 23, + Int024_IRQn = 24, + Int025_IRQn = 25, + Int026_IRQn = 26, + Int027_IRQn = 27, + Int028_IRQn = 28, + Int029_IRQn = 29, + Int030_IRQn = 30, + Int031_IRQn = 31, + Int032_IRQn = 32, + Int033_IRQn = 33, + Int034_IRQn = 34, + Int035_IRQn = 35, + Int036_IRQn = 36, + Int037_IRQn = 37, + Int038_IRQn = 38, + Int039_IRQn = 39, + Int040_IRQn = 40, + Int041_IRQn = 41, + Int042_IRQn = 42, + Int043_IRQn = 43, + Int044_IRQn = 44, + Int045_IRQn = 45, + Int046_IRQn = 46, + Int047_IRQn = 47, + Int048_IRQn = 48, + Int049_IRQn = 49, + Int050_IRQn = 50, + Int051_IRQn = 51, + Int052_IRQn = 52, + Int053_IRQn = 53, + Int054_IRQn = 54, + Int055_IRQn = 55, + Int056_IRQn = 56, + Int057_IRQn = 57, + Int058_IRQn = 58, + Int059_IRQn = 59, + Int060_IRQn = 60, + Int061_IRQn = 61, + Int062_IRQn = 62, + Int063_IRQn = 63, + Int064_IRQn = 64, + Int065_IRQn = 65, + Int066_IRQn = 66, + Int067_IRQn = 67, + Int068_IRQn = 68, + Int069_IRQn = 69, + Int070_IRQn = 70, + Int071_IRQn = 71, + Int072_IRQn = 72, + Int073_IRQn = 73, + Int074_IRQn = 74, + Int075_IRQn = 75, + Int076_IRQn = 76, + Int077_IRQn = 77, + Int078_IRQn = 78, + Int079_IRQn = 79, + Int080_IRQn = 80, + Int081_IRQn = 81, + Int082_IRQn = 82, + Int083_IRQn = 83, + Int084_IRQn = 84, + Int085_IRQn = 85, + Int086_IRQn = 86, + Int087_IRQn = 87, + Int088_IRQn = 88, + Int089_IRQn = 89, + Int090_IRQn = 90, + Int091_IRQn = 91, + Int092_IRQn = 92, + Int093_IRQn = 93, + Int094_IRQn = 94, + Int095_IRQn = 95, + Int096_IRQn = 96, + Int097_IRQn = 97, + Int098_IRQn = 98, + Int099_IRQn = 99, + Int100_IRQn = 100, + Int101_IRQn = 101, + Int102_IRQn = 102, + Int103_IRQn = 103, + Int104_IRQn = 104, + Int105_IRQn = 105, + Int106_IRQn = 106, + Int107_IRQn = 107, + Int108_IRQn = 108, + Int109_IRQn = 109, + Int110_IRQn = 110, + Int111_IRQn = 111, + Int112_IRQn = 112, + Int113_IRQn = 113, + Int114_IRQn = 114, + Int115_IRQn = 115, + Int116_IRQn = 116, + Int117_IRQn = 117, + Int118_IRQn = 118, + Int119_IRQn = 119, + Int120_IRQn = 120, + Int121_IRQn = 121, + Int122_IRQn = 122, + Int123_IRQn = 123, + Int124_IRQn = 124, + Int125_IRQn = 125, + Int126_IRQn = 126, + Int127_IRQn = 127, + Int128_IRQn = 128, + Int129_IRQn = 129, + Int130_IRQn = 130, + Int131_IRQn = 131, + Int132_IRQn = 132, + Int133_IRQn = 133, + Int134_IRQn = 134, + Int135_IRQn = 135, + Int136_IRQn = 136, + Int137_IRQn = 137, + Int138_IRQn = 138, + Int139_IRQn = 139, + Int140_IRQn = 140, + Int141_IRQn = 141, + Int142_IRQn = 142, + Int143_IRQn = 143, + +} IRQn_Type; + +#include +#include + +/** + ******************************************************************************* + ** \brief Event number enumeration + ******************************************************************************/ +typedef enum en_event_src +{ + EVT_SWI_IRQ0 = 0U, + EVT_SWI_IRQ1 = 1U, + EVT_SWI_IRQ2 = 2U, + EVT_SWI_IRQ3 = 3U, + EVT_SWI_IRQ4 = 4U, + EVT_SWI_IRQ5 = 5U, + EVT_SWI_IRQ6 = 6U, + EVT_SWI_IRQ7 = 7U, + EVT_SWI_IRQ8 = 8U, + EVT_SWI_IRQ9 = 9U, + EVT_SWI_IRQ10 = 10U, + EVT_SWI_IRQ11 = 11U, + EVT_SWI_IRQ12 = 12U, + EVT_SWI_IRQ13 = 13U, + EVT_SWI_IRQ14 = 14U, + EVT_SWI_IRQ15 = 15U, + EVT_SWI_IRQ16 = 16U, + EVT_SWI_IRQ17 = 17U, + EVT_SWI_IRQ18 = 18U, + EVT_SWI_IRQ19 = 19U, + EVT_SWI_IRQ20 = 20U, + EVT_SWI_IRQ21 = 21U, + EVT_SWI_IRQ22 = 22U, + EVT_SWI_IRQ23 = 23U, + EVT_SWI_IRQ24 = 24U, + EVT_SWI_IRQ25 = 25U, + EVT_SWI_IRQ26 = 26U, + EVT_SWI_IRQ27 = 27U, + EVT_SWI_IRQ28 = 28U, + EVT_SWI_IRQ29 = 29U, + EVT_SWI_IRQ30 = 30U, + EVT_SWI_IRQ31 = 31U, + /* External Interrupt */ + EVT_PORT_EIRQ0 = 0U, + EVT_PORT_EIRQ1 = 1U, + EVT_PORT_EIRQ2 = 2U, + EVT_PORT_EIRQ3 = 3U, + EVT_PORT_EIRQ4 = 4U, + EVT_PORT_EIRQ5 = 5U, + EVT_PORT_EIRQ6 = 6U, + EVT_PORT_EIRQ7 = 7U, + EVT_PORT_EIRQ8 = 8U, + EVT_PORT_EIRQ9 = 9U, + EVT_PORT_EIRQ10 = 10U, + EVT_PORT_EIRQ11 = 11U, + EVT_PORT_EIRQ12 = 12U, + EVT_PORT_EIRQ13 = 13U, + EVT_PORT_EIRQ14 = 14U, + EVT_PORT_EIRQ15 = 15U, + /* DMA_1 */ + EVT_DMA1_TC0 = 32U, + EVT_DMA1_TC1 = 33U, + EVT_DMA1_TC2 = 34U, + EVT_DMA1_TC3 = 35U, + EVT_DMA1_TC4 = 36U, + EVT_DMA1_TC5 = 37U, + EVT_DMA1_TC6 = 38U, + EVT_DMA1_TC7 = 39U, + EVT_DMA1_BTC0 = 40U, + EVT_DMA1_BTC1 = 41U, + EVT_DMA1_BTC2 = 42U, + EVT_DMA1_BTC3 = 43U, + EVT_DMA1_BTC4 = 44U, + EVT_DMA1_BTC5 = 45U, + EVT_DMA1_BTC6 = 46U, + EVT_DMA1_BTC7 = 47U, + /* EFM */ + EVT_EFM_OPTEND = 51U, + /* USBFS */ + EVT_USBFS_SOF = 52U, + /* USBHS */ + EVT_USBHS_SOF = 53U, + /* DCU */ + EVT_DCU1 = 55U, + EVT_DCU2 = 56U, + EVT_DCU3 = 57U, + EVT_DCU4 = 58U, + EVT_DCU5 = 59U, + EVT_DCU6 = 60U, + EVT_DCU7 = 61U, + EVT_DCU8 = 62U, + /* DMA_2 */ + EVT_DMA2_TC0 = 64U, + EVT_DMA2_TC1 = 65U, + EVT_DMA2_TC2 = 66U, + EVT_DMA2_TC3 = 67U, + EVT_DMA2_TC4 = 68U, + EVT_DMA2_TC5 = 69U, + EVT_DMA2_TC6 = 70U, + EVT_DMA2_TC7 = 71U, + EVT_DMA2_BTC0 = 72U, + EVT_DMA2_BTC1 = 73U, + EVT_DMA2_BTC2 = 74U, + EVT_DMA2_BTC3 = 75U, + EVT_DMA2_BTC4 = 76U, + EVT_DMA2_BTC5 = 77U, + EVT_DMA2_BTC6 = 78U, + EVT_DMA2_BTC7 = 79U, + /* MAU */ + EVT_MAU_SQRT = 83U, + /* DVP */ + EVT_DVP_FRAMSTA = 84U, + EVT_DVP_LINESTA = 85U, + EVT_DVP_LINEEND = 86U, + EVT_DVP_FRAMEND = 87U, + EVT_DVP_SQUERR = 88U, + EVT_DVP_FIFOERR = 89U, + EVT_DVP_DMAREQ = 90U, + /* FMAC */ + EVT_FMAC_1 = 91U, + EVT_FMAC_2 = 92U, + EVT_FMAC_3 = 93U, + EVT_FMAC_4 = 94U, + /* TIMER0 */ + EVT_TMR0_1_CMPA = 96U, + EVT_TMR0_1_CMPB = 97U, + EVT_TMR0_2_CMPA = 98U, + EVT_TMR0_2_CMPB = 99U, + /* TIMER2 */ + EVT_TMR2_1_CMPA = 100U, + EVT_TMR2_1_CMPB = 101U, + EVT_TMR2_1_OVFA = 102U, + EVT_TMR2_1_OVFB = 103U, + EVT_TMR2_2_CMPA = 104U, + EVT_TMR2_2_CMPB = 105U, + EVT_TMR2_2_OVFA = 106U, + EVT_TMR2_2_OVFB = 107U, + EVT_TMR2_3_CMPA = 108U, + EVT_TMR2_3_CMPB = 109U, + EVT_TMR2_3_OVFA = 110U, + EVT_TMR2_3_OVFB = 111U, + EVT_TMR2_4_CMPA = 112U, + EVT_TMR2_4_CMPB = 113U, + EVT_TMR2_4_OVFA = 114U, + EVT_TMR2_4_OVFB = 115U, + /* RTC */ + EVT_RTC_ALM = 121U, + EVT_RTC_PRD = 122U, + /* TIMER6_1 */ + EVT_TMR6_1_GCMA = 128U, + EVT_TMR6_1_GCMB = 129U, + EVT_TMR6_1_GCMC = 130U, + EVT_TMR6_1_GCMD = 131U, + EVT_TMR6_1_GCME = 132U, + EVT_TMR6_1_GCMF = 133U, + EVT_TMR6_1_GOVF = 134U, + EVT_TMR6_1_GUDF = 135U, + /* TIMER4_1 */ + EVT_TMR4_1_SCMUH = 136U, + EVT_TMR4_1_SCMUL = 137U, + EVT_TMR4_1_SCMVH = 138U, + EVT_TMR4_1_SCMVL = 139U, + EVT_TMR4_1_SCMWH = 140U, + EVT_TMR4_1_SCMWL = 141U, + /* TIMER6_2 */ + EVT_TMR6_2_GCMA = 144U, + EVT_TMR6_2_GCMB = 145U, + EVT_TMR6_2_GCMC = 146U, + EVT_TMR6_2_GCMD = 147U, + EVT_TMR6_2_GCME = 148U, + EVT_TMR6_2_GCMF = 149U, + EVT_TMR6_2_GOVF = 150U, + EVT_TMR6_2_GUDF = 151U, + /* TIMER4_2 */ + EVT_TMR4_2_SCMUH = 152U, + EVT_TMR4_2_SCMUL = 153U, + EVT_TMR4_2_SCMVH = 154U, + EVT_TMR4_2_SCMVL = 155U, + EVT_TMR4_2_SCMWH = 156U, + EVT_TMR4_2_SCMWL = 157U, + /* TIMER6_3 */ + EVT_TMR6_3_GCMA = 160U, + EVT_TMR6_3_GCMB = 161U, + EVT_TMR6_3_GCMC = 162U, + EVT_TMR6_3_GCMD = 163U, + EVT_TMR6_3_GCME = 164U, + EVT_TMR6_3_GCMF = 165U, + EVT_TMR6_3_GOVF = 166U, + EVT_TMR6_3_GUDF = 167U, + /* TIMER4_3 */ + EVT_TMR4_3_SCMUH = 168U, + EVT_TMR4_3_SCMUL = 169U, + EVT_TMR4_3_SCMVH = 170U, + EVT_TMR4_3_SCMVL = 171U, + EVT_TMR4_3_SCMWH = 172U, + EVT_TMR4_3_SCMWL = 173U, + /* TIMER6 */ + EVT_TMR6_1_SCMA = 179U, + EVT_TMR6_1_SCMB = 180U, + EVT_TMR6_2_SCMA = 187U, + EVT_TMR6_2_SCMB = 188U, + EVT_TMR6_3_SCMA = 195U, + EVT_TMR6_3_SCMB = 196U, + EVT_TMR6_4_GCMA = 208U, + EVT_TMR6_4_GCMB = 209U, + EVT_TMR6_4_GCMC = 210U, + EVT_TMR6_4_GCMD = 211U, + EVT_TMR6_4_GCME = 212U, + EVT_TMR6_4_GCMF = 213U, + EVT_TMR6_4_GOVF = 214U, + EVT_TMR6_4_GUDF = 215U, + EVT_TMR6_4_SCMA = 219U, + EVT_TMR6_4_SCMB = 220U, + EVT_TMR6_5_GCMA = 224U, + EVT_TMR6_5_GCMB = 225U, + EVT_TMR6_5_GCMC = 226U, + EVT_TMR6_5_GCMD = 227U, + EVT_TMR6_5_GCME = 228U, + EVT_TMR6_5_GCMF = 229U, + EVT_TMR6_5_GOVF = 230U, + EVT_TMR6_5_GUDF = 231U, + EVT_TMR6_5_SCMA = 235U, + EVT_TMR6_5_SCMB = 236U, + /* TIMERA_1 */ + EVT_TMRA_1_OVF = 237U, + EVT_TMRA_1_UDF = 238U, + EVT_TMRA_1_CMP = 239U, + /* TIMER6_6 */ + EVT_TMR6_6_GCMA = 240U, + EVT_TMR6_6_GCMB = 241U, + EVT_TMR6_6_GCMC = 242U, + EVT_TMR6_6_GCMD = 243U, + EVT_TMR6_6_GCME = 244U, + EVT_TMR6_6_GCMF = 245U, + EVT_TMR6_6_GOVF = 246U, + EVT_TMR6_6_GUDF = 247U, + EVT_TMR6_6_SCMA = 251U, + EVT_TMR6_6_SCMB = 252U, + /* TIMERA_2 */ + EVT_TMRA_2_OVF = 253U, + EVT_TMRA_2_UDF = 254U, + EVT_TMRA_2_CMP = 255U, + /* TIMER6_7 */ + EVT_TMR6_7_GCMA = 256U, + EVT_TMR6_7_GCMB = 257U, + EVT_TMR6_7_GCMC = 258U, + EVT_TMR6_7_GCMD = 259U, + EVT_TMR6_7_GCME = 260U, + EVT_TMR6_7_GCMF = 261U, + EVT_TMR6_7_GOVF = 262U, + EVT_TMR6_7_GUDF = 263U, + EVT_TMR6_7_SCMA = 267U, + EVT_TMR6_7_SCMB = 268U, + /* TIMERA_3 */ + EVT_TMRA_3_OVF = 269U, + EVT_TMRA_3_UDF = 270U, + EVT_TMRA_3_CMP = 271U, + /* TIMER6_8 */ + EVT_TMR6_8_GCMA = 272U, + EVT_TMR6_8_GCMB = 273U, + EVT_TMR6_8_GCMC = 274U, + EVT_TMR6_8_GCMD = 275U, + EVT_TMR6_8_GCME = 276U, + EVT_TMR6_8_GCMF = 277U, + EVT_TMR6_8_GOVF = 278U, + EVT_TMR6_8_GUDF = 279U, + EVT_TMR6_8_SCMA = 283U, + EVT_TMR6_8_SCMB = 284U, + /* TIMERA_4 */ + EVT_TMRA_4_OVF = 285U, + EVT_TMRA_4_UDF = 286U, + EVT_TMRA_4_CMP = 287U, + /* AOS_STRG */ + EVT_AOS_STRG = 299U, + /* USART1 USART2 */ + EVT_USART1_EI = 300U, + EVT_USART1_RI = 301U, + EVT_USART1_TI = 302U, + EVT_USART1_TCI = 303U, + EVT_USART1_RTO = 304U, + EVT_USART2_EI = 305U, + EVT_USART2_RI = 306U, + EVT_USART2_TI = 307U, + EVT_USART2_TCI = 308U, + EVT_USART2_RTO = 309U, + /* SPI1 SPI2 */ + EVT_SPI1_SPRI = 310U, + EVT_SPI1_SPTI = 311U, + EVT_SPI1_SPII = 312U, + EVT_SPI1_SPEI = 313U, + EVT_SPI1_SPEND = 314U, + EVT_SPI2_SPRI = 315U, + EVT_SPI2_SPTI = 316U, + EVT_SPI2_SPII = 317U, + EVT_SPI2_SPEI = 318U, + EVT_SPI2_SPEND = 319U, + /* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */ + EVT_TMRA_5_OVF = 320U, + EVT_TMRA_5_UDF = 321U, + EVT_TMRA_5_CMP = 322U, + EVT_TMRA_6_OVF = 323U, + EVT_TMRA_6_UDF = 324U, + EVT_TMRA_6_CMP = 325U, + EVT_TMRA_7_OVF = 326U, + EVT_TMRA_7_UDF = 327U, + EVT_TMRA_7_CMP = 328U, + EVT_TMRA_8_OVF = 329U, + EVT_TMRA_8_UDF = 330U, + EVT_TMRA_8_CMP = 331U, + /* USART3 USART4 */ + EVT_USART3_EI = 332U, + EVT_USART3_RI = 333U, + EVT_USART3_TI = 334U, + EVT_USART3_TCI = 335U, + EVT_USART4_EI = 336U, + EVT_USART4_RI = 337U, + EVT_USART4_TI = 338U, + EVT_USART4_TCI = 339U, + /* SPI3 SPI4 */ + EVT_SPI3_SPRI = 342U, + EVT_SPI3_SPTI = 343U, + EVT_SPI3_SPII = 344U, + EVT_SPI3_SPEI = 345U, + EVT_SPI3_SPEND = 346U, + EVT_SPI4_SPRI = 347U, + EVT_SPI4_SPTI = 348U, + EVT_SPI4_SPII = 349U, + EVT_SPI4_SPEI = 350U, + EVT_SPI4_SPEND = 351U, + /* TIMERA_9 TIMERA_10 TIMERA_11 TIMERA_12 */ + EVT_TMRA_9_OVF = 352U, + EVT_TMRA_9_UDF = 353U, + EVT_TMRA_9_CMP = 354U, + EVT_TMRA_10_OVF = 355U, + EVT_TMRA_10_UDF = 356U, + EVT_TMRA_10_CMP = 357U, + EVT_TMRA_11_OVF = 358U, + EVT_TMRA_11_UDF = 359U, + EVT_TMRA_11_CMP = 360U, + EVT_TMRA_12_OVF = 361U, + EVT_TMRA_12_UDF = 362U, + EVT_TMRA_12_CMP = 363U, + /* USART5 USART6 */ + EVT_USART5_BRKWKPI = 364U, + EVT_USART5_EI = 365U, + EVT_USART5_RI = 366U, + EVT_USART5_TI = 367U, + EVT_USART5_TCI = 368U, + EVT_USART6_EI = 369U, + EVT_USART6_RI = 370U, + EVT_USART6_TI = 371U, + EVT_USART6_TCI = 372U, + EVT_USART6_RTO = 373U, + /* SPI5 SPI6 */ + EVT_SPI5_SPRI = 374U, + EVT_SPI5_SPTI = 375U, + EVT_SPI5_SPII = 376U, + EVT_SPI5_SPEI = 377U, + EVT_SPI5_SPEND = 378U, + EVT_SPI6_SPRI = 379U, + EVT_SPI6_SPTI = 380U, + EVT_SPI6_SPII = 381U, + EVT_SPI6_SPEI = 382U, + EVT_SPI6_SPEND = 383U, + /* I2S1 I2S2 */ + EVT_I2S1_TXIRQOUT = 384U, + EVT_I2S1_RXIRQOUT = 385U, + EVT_I2S2_TXIRQOUT = 387U, + EVT_I2S2_RXIRQOUT = 388U, + /* USART7 USART8 */ + EVT_USART7_EI = 390U, + EVT_USART7_RI = 391U, + EVT_USART7_TI = 392U, + EVT_USART7_TCI = 393U, + EVT_USART7_RTO = 394U, + EVT_USART8_EI = 395U, + EVT_USART8_RI = 396U, + EVT_USART8_TI = 397U, + EVT_USART8_TCI = 398U, + /* HASH */ + EVT_HASH = 401U, + /* SDIOC */ + EVT_SDIOC1_DMAR = 402U, + EVT_SDIOC1_DMAW = 403U, + EVT_SDIOC2_DMAR = 405U, + EVT_SDIOC2_DMAW = 406U, + /* EVENT PORT */ + EVT_EVENT_PORT1 = 408U, + EVT_EVENT_PORT2 = 409U, + EVT_EVENT_PORT3 = 410U, + EVT_EVENT_PORT4 = 411U, + /* ETHER */ + EVT_ETH_PPS_OUT_0 = 414U, + EVT_ETH_PPS_OUT_1 = 415U, + /* I2S3 I2S4 */ + EVT_I2S3_TXIRQOUT = 416U, + EVT_I2S3_RXIRQOUT = 417U, + EVT_I2S4_TXIRQOUT = 419U, + EVT_I2S4_RXIRQOUT = 420U, + /* USART9 USART10 */ + EVT_USART9_EI = 422U, + EVT_USART9_RI = 423U, + EVT_USART9_TI = 424U, + EVT_USART9_TCI = 425U, + EVT_USART10_BRKWKPI = 426U, + EVT_USART10_EI = 427U, + EVT_USART10_RI = 428U, + EVT_USART10_TI = 429U, + EVT_USART10_TCI = 430U, + /* I2C1 I2C2 I2C3 */ + EVT_I2C1_RXI = 432U, + EVT_I2C1_TXI = 433U, + EVT_I2C1_TEI = 434U, + EVT_I2C1_EEI = 435U, + EVT_I2C2_RXI = 436U, + EVT_I2C2_TXI = 437U, + EVT_I2C2_TEI = 438U, + EVT_I2C2_EEI = 439U, + EVT_I2C3_RXI = 440U, + EVT_I2C3_TXI = 441U, + EVT_I2C3_TEI = 442U, + EVT_I2C3_EEI = 443U, + /* ACMP */ + EVT_CMP1 = 444U, + EVT_CMP2 = 445U, + EVT_CMP3 = 446U, + EVT_CMP4 = 447U, + /* I2C4 I2C5 I2C6 */ + EVT_I2C4_RXI = 448U, + EVT_I2C4_TXI = 449U, + EVT_I2C4_TEI = 450U, + EVT_I2C4_EEI = 451U, + EVT_I2C5_RXI = 452U, + EVT_I2C5_TXI = 453U, + EVT_I2C5_TEI = 454U, + EVT_I2C5_EEI = 455U, + EVT_I2C6_RXI = 456U, + EVT_I2C6_TXI = 457U, + EVT_I2C6_TEI = 458U, + EVT_I2C6_EEI = 459U, + /* PVD */ + EVT_PVD_PVD1 = 461U, + EVT_PVD_PVD2 = 462U, + /* OTS */ + EVT_OTS = 463U, + /* WDT */ + EVT_WDT_REFUDF = 467U, + /* ADC */ + EVT_ADC1_EOCA = 480U, + EVT_ADC1_EOCB = 481U, + EVT_ADC1_CHCMP = 482U, + EVT_ADC1_SEQCMP = 483U, + EVT_ADC2_EOCA = 484U, + EVT_ADC2_EOCB = 485U, + EVT_ADC2_CHCMP = 486U, + EVT_ADC2_SEQCMP = 487U, + EVT_ADC3_EOCA = 488U, + EVT_ADC3_EOCB = 489U, + EVT_ADC3_CHCMP = 490U, + EVT_ADC3_SEQCMP = 491U, + /* TRNG */ + EVT_TRNG_END = 492U, + EVT_MAX = 511U, +} en_event_src_t; + +/** + ******************************************************************************* + ** \brief InterrUpt nUmber enumeration + ******************************************************************************/ +typedef enum en_int_src +{ + INT_SWI_IRQ0 = 0U, + INT_SWI_IRQ1 = 1U, + INT_SWI_IRQ2 = 2U, + INT_SWI_IRQ3 = 3U, + INT_SWI_IRQ4 = 4U, + INT_SWI_IRQ5 = 5U, + INT_SWI_IRQ6 = 6U, + INT_SWI_IRQ7 = 7U, + INT_SWI_IRQ8 = 8U, + INT_SWI_IRQ9 = 9U, + INT_SWI_IRQ10 = 10U, + INT_SWI_IRQ11 = 11U, + INT_SWI_IRQ12 = 12U, + INT_SWI_IRQ13 = 13U, + INT_SWI_IRQ14 = 14U, + INT_SWI_IRQ15 = 15U, + INT_SWI_IRQ16 = 16U, + INT_SWI_IRQ17 = 17U, + INT_SWI_IRQ18 = 18U, + INT_SWI_IRQ19 = 19U, + INT_SWI_IRQ20 = 20U, + INT_SWI_IRQ21 = 21U, + INT_SWI_IRQ22 = 22U, + INT_SWI_IRQ23 = 23U, + INT_SWI_IRQ24 = 24U, + INT_SWI_IRQ25 = 25U, + INT_SWI_IRQ26 = 26U, + INT_SWI_IRQ27 = 27U, + INT_SWI_IRQ28 = 28U, + INT_SWI_IRQ29 = 29U, + INT_SWI_IRQ30 = 30U, + INT_SWI_IRQ31 = 31U, + /* External Interrupt */ + INT_PORT_EIRQ0 = 0U, + INT_PORT_EIRQ1 = 1U, + INT_PORT_EIRQ2 = 2U, + INT_PORT_EIRQ3 = 3U, + INT_PORT_EIRQ4 = 4U, + INT_PORT_EIRQ5 = 5U, + INT_PORT_EIRQ6 = 6U, + INT_PORT_EIRQ7 = 7U, + INT_PORT_EIRQ8 = 8U, + INT_PORT_EIRQ9 = 9U, + INT_PORT_EIRQ10 = 10U, + INT_PORT_EIRQ11 = 11U, + INT_PORT_EIRQ12 = 12U, + INT_PORT_EIRQ13 = 13U, + INT_PORT_EIRQ14 = 14U, + INT_PORT_EIRQ15 = 15U, + /* DMA_1 */ + INT_DMA1_TC0 = 32U, + INT_DMA1_TC1 = 33U, + INT_DMA1_TC2 = 34U, + INT_DMA1_TC3 = 35U, + INT_DMA1_TC4 = 36U, + INT_DMA1_TC5 = 37U, + INT_DMA1_TC6 = 38U, + INT_DMA1_TC7 = 39U, + INT_DMA1_BTC0 = 40U, + INT_DMA1_BTC1 = 41U, + INT_DMA1_BTC2 = 42U, + INT_DMA1_BTC3 = 43U, + INT_DAM1_BTC4 = 44U, + INT_DMA1_BTC5 = 45U, + INT_DMA1_BTC6 = 46U, + INT_DMA1_BTC7 = 47U, + INT_DMA1_ERR = 48U, + /* EFM */ + INT_EFM_PEERR = 49U, + INT_EFM_RDCOL = 50U, + INT_EFM_OPTEND = 51U, + /* QSPI */ + INT_QSPI_INTR = 54U, + /* DCU */ + INT_DCU1 = 55U, + INT_DCU2 = 56U, + INT_DCU3 = 57U, + INT_DCU4 = 58U, + INT_DCU5 = 59U, + INT_DCU6 = 60U, + INT_DCU7 = 61U, + INT_DCU8 = 62U, + /* DMA2 */ + INT_DMA2_TC0 = 64U, + INT_DMA2_TC1 = 65U, + INT_DMA2_TC2 = 66U, + INT_DMA2_TC3 = 67U, + INT_DMA2_TC4 = 68U, + INT_DMA2_TC5 = 69U, + INT_DMA2_TC6 = 70U, + INT_DMA2_TC7 = 71U, + INT_DMA2_BTC0 = 72U, + INT_DMA2_BTC1 = 73U, + INT_DMA2_BTC2 = 74U, + INT_DMA2_BTC3 = 75U, + INT_DMA2_BTC4 = 76U, + INT_DMA2_BTC5 = 77U, + INT_DMA2_BTC6 = 78U, + INT_DMA2_BTC7 = 79U, + INT_DMA2_ERR = 80U, + /* MAU */ + INT_MAU_SQRT = 83U, + /* DVP */ + INT_DVP_FRAMSTA = 84U, + INT_DVP_LINESTA = 85U, + INT_DVP_LINEEND = 86U, + INT_DVP_FRAMEND = 87U, + INT_DVP_SQUERR = 88U, + INT_DVP_FIFOERR = 89U, + /* FMAC */ + INT_FMAC_1 = 91U, + INT_FMAC_2 = 92U, + INT_FMAC_3 = 93U, + INT_FMAC_4 = 94U, + /* TIMER0 */ + INT_TMR0_1_CMPA = 96U, + INT_TMR0_1_CMPB = 97U, + INT_TMR0_2_CMPA = 98U, + INT_TMR0_2_CMPB = 99U, + /* TIMER2 */ + INT_TMR2_1_CMPA = 100U, + INT_TMR2_1_CMPB = 101U, + INT_TMR2_1_OVFA = 102U, + INT_TMR2_1_OVFB = 103U, + INT_TMR2_2_CMPA = 104U, + INT_TMR2_2_CMPB = 105U, + INT_TMR2_2_OVFA = 106U, + INT_TMR2_2_OVFB = 107U, + INT_TMR2_3_CMPA = 108U, + INT_TMR2_3_CMPB = 109U, + INT_TMR2_3_OVFA = 110U, + INT_TMR2_3_OVFB = 111U, + INT_TMR2_4_CMPA = 112U, + INT_TMR2_4_CMPB = 113U, + INT_TMR2_4_OVFA = 114U, + INT_TMR2_4_OVFB = 115U, + /* RTC */ + INT_RTC_TP = 120U, + INT_RTC_ALM = 121U, + INT_RTC_PRD = 122U, + /* XTAL */ + INT_XTAL_STOP = 125U, + /* WKTM */ + INT_WKTM_PRD = 126U, + /* SWDT */ + INT_SWDT_REFUDF = 127U, + /* TIMER6_1 */ + INT_TMR6_1_GCMA = 128U, + INT_TMR6_1_GCMB = 129U, + INT_TMR6_1_GCMC = 130U, + INT_TMR6_1_GCMD = 131U, + INT_TMR6_1_GCME = 132U, + INT_TMR6_1_GCMF = 133U, + INT_TMR6_1_GOVF = 134U, + INT_TMR6_1_GUDF = 135U, + /* TIMER4_1 */ + INT_TMR4_1_GCMUH = 136U, + INT_TMR4_1_GCMUL = 137U, + INT_TMR4_1_GCMVH = 138U, + INT_TMR4_1_GCMVL = 139U, + INT_TMR4_1_GCMWH = 140U, + INT_TMR4_1_GCMWL = 141U, + INT_TMR4_1_GOVF = 142U, + INT_TMR4_1_GUDF = 143U, + /* TIMER6_2 */ + INT_TMR6_2_GCMA = 144U, + INT_TMR6_2_GCMB = 145U, + INT_TMR6_2_GCMC = 146U, + INT_TMR6_2_GCMD = 147U, + INT_TMR6_2_GCME = 148U, + INT_TMR6_2_GCMF = 149U, + INT_TMR6_2_GOVF = 150U, + INT_TMR6_2_GUDF = 151U, + /* TIMER4_2 */ + INT_TMR4_2_GCMUH = 152U, + INT_TMR4_2_GCMUL = 153U, + INT_TMR4_2_GCMVH = 154U, + INT_TMR4_2_GCMVL = 155U, + INT_TMR4_2_GCMWH = 156U, + INT_TMR4_2_GCMWL = 157U, + INT_TMR4_2_GOVF = 158U, + INT_TMR4_2_GUDF = 159U, + /* TIMER6_3 */ + INT_TMR6_3_GCMA = 160U, + INT_TMR6_3_GCMB = 161U, + INT_TMR6_3_GCMC = 162U, + INT_TMR6_3_GCMD = 163U, + INT_TMR6_3_GCME = 164U, + INT_TMR6_3_GCMF = 165U, + INT_TMR6_3_GOVF = 166U, + INT_TMR6_3_GUDF = 167U, + /* TIMER4_3 */ + INT_TMR4_3_GCMUH = 168U, + INT_TMR4_3_GCMUL = 169U, + INT_TMR4_3_GCMVH = 170U, + INT_TMR4_3_GCMVL = 171U, + INT_TMR4_3_GCMWH = 172U, + INT_TMR4_3_GCMWL = 173U, + INT_TMR4_3_GOVF = 174U, + INT_TMR4_3_GUDF = 175U, + /* TIMER6_1 */ + INT_TMR6_1_GDTE = 176U, + INT_TMR6_1_SCMA = 179U, + INT_TMR6_1_SCMB = 180U, + /* TIMER4_1 */ + INT_TMR4_1_RLOU = 181U, + INT_TMR4_1_RLOV = 182U, + INT_TMR4_1_RLOW = 183U, + /* TIMER6_2 */ + INT_TMR6_2_GDTE = 184U, + INT_TMR6_2_SCMA = 187U, + INT_TMR6_2_SCMB = 188U, + /* TIMER4_2 */ + INT_TMR4_2_RLOU = 189U, + INT_TMR4_2_RLOV = 190U, + INT_TMR4_2_RLOW = 191U, + /* TIMER6_3 */ + INT_TMR6_3_GDTE = 192U, + INT_TMR6_3_SCMA = 195U, + INT_TMR6_3_SCMB = 196U, + /* TIMER4_3 */ + INT_TMR4_3_RLOU = 197U, + INT_TMR4_3_RLOV = 198U, + INT_TMR4_3_RLOW = 199U, + /* TIMER6_4 TIMER6_5 */ + INT_TMR6_4_GCMA = 208U, + INT_TMR6_4_GCMB = 209U, + INT_TMR6_4_GCMC = 210U, + INT_TMR6_4_GCMD = 211U, + INT_TMR6_4_GCME = 212U, + INT_TMR6_4_GCMF = 213U, + INT_TMR6_4_GOVF = 214U, + INT_TMR6_4_GUDF = 215U, + INT_TMR6_4_GDTE = 216U, + INT_TMR6_4_SCMA = 219U, + INT_TMR6_4_SCMB = 220U, + INT_TMR6_5_GCMA = 224U, + INT_TMR6_5_GCMB = 225U, + INT_TMR6_5_GCMC = 226U, + INT_TMR6_5_GCMD = 227U, + INT_TMR6_5_GCME = 228U, + INT_TMR6_5_GCMF = 229U, + INT_TMR6_5_GOVF = 230U, + INT_TMR6_5_GUDF = 231U, + INT_TMR6_5_GDTE = 232U, + INT_TMR6_5_SCMA = 235U, + INT_TMR6_5_SCMB = 236U, + /* TIMERA_1 */ + INT_TMRA_1_OVF = 237U, + INT_TMRA_1_UDF = 238U, + INT_TMRA_1_CMP = 239U, + /* TIMER6_6 */ + INT_TMR6_6_GCMA = 240U, + INT_TMR6_6_GCMB = 241U, + INT_TMR6_6_GCMC = 242U, + INT_TMR6_6_GCMD = 243U, + INT_TMR6_6_GCME = 244U, + INT_TMR6_6_GCMF = 245U, + INT_TMR6_6_GOVF = 246U, + INT_TMR6_6_GUDF = 247U, + INT_TMR6_6_GDTE = 248U, + INT_TMR6_6_SCMA = 251U, + INT_TMR6_6_SCMB = 252U, + /* TIMERA_2 */ + INT_TMRA_2_OVF = 253U, + INT_TMRA_2_UDF = 254U, + INT_TMRA_2_CMP = 255U, + /* TIMER6_7 */ + INT_TMR6_7_GCMA = 256U, + INT_TMR6_7_GCMB = 257U, + INT_TMR6_7_GCMC = 258U, + INT_TMR6_7_GCMD = 259U, + INT_TMR6_7_GCME = 260U, + INT_TMR6_7_GCMF = 261U, + INT_TMR6_7_GOVF = 262U, + INT_TMR6_7_GUDF = 263U, + INT_TMR6_7_GDTE = 264U, + INT_TMR6_7_SCMA = 267U, + INT_TMR6_7_SCMB = 268U, + /* TIMERA_3 */ + INT_TMRA_3_OVF = 269U, + INT_TMRA_3_UDF = 270U, + INT_TMRA_3_CMP = 271U, + /* TIMER6_8 */ + INT_TMR6_8_GCMA = 272U, + INT_TMR6_8_GCMB = 273U, + INT_TMR6_8_GCMC = 274U, + INT_TMR6_8_GCMD = 275U, + INT_TMR6_8_GCME = 276U, + INT_TMR6_8_GCMF = 277U, + INT_TMR6_8_GOVF = 278U, + INT_TMR6_8_GUDF = 279U, + INT_TMR6_8_GDTE = 280U, + INT_TMR6_8_SCMA = 283U, + INT_TMR6_8_SCMB = 284U, + /* TIMERA_4 */ + INT_TMRA_4_OVF = 285U, + INT_TMRA_4_UDF = 286U, + INT_TMRA_4_CMP = 287U, + /* EMB */ + INT_EMB_GR0 = 288U, + INT_EMB_GR1 = 289U, + INT_EMB_GR2 = 290U, + INT_EMB_GR3 = 291U, + INT_EMB_GR4 = 292U, + INT_EMB_GR5 = 293U, + INT_EMB_GR6 = 294U, + /* USBHS */ + INT_USBHS_EP1_OUT = 295U, + INT_USBHS_EP1_IN = 296U, + INT_USBHS_GLB = 297U, + INT_USBHS_WKUP = 298U, + /* USART1 USART2 */ + INT_USART1_EI = 300U, + INT_USART1_RI = 301U, + INT_USART1_TI = 302U, + INT_USART1_TCI = 303U, + INT_USART1_RTO = 304U, + INT_USART2_EI = 305U, + INT_USART2_RI = 306U, + INT_USART2_TI = 307U, + INT_USART2_TCI = 308U, + INT_USART2_RTO = 309U, + /* SPI1 SPI2 */ + INT_SPI1_SPRI = 310U, + INT_SPI1_SPTI = 311U, + INT_SPI1_SPII = 312U, + INT_SPI1_SPEI = 313U, + INT_SPI2_SPRI = 315U, + INT_SPI2_SPTI = 316U, + INT_SPI2_SPII = 317U, + INT_SPI2_SPEI = 318U, + /* TIMERA_5 TIMERA_6 TIMERA_7 TIMERA_8 */ + INT_TMRA_5_OVF = 320U, + INT_TMRA_5_UDF = 321U, + INT_TMRA_5_CMP = 322U, + INT_TMRA_6_OVF = 323U, + INT_TMRA_6_UDF = 324U, + INT_TMRA_6_CMP = 325U, + INT_TMRA_7_OVF = 326U, + INT_TMRA_7_UDF = 327U, + INT_TMRA_7_CMP = 328U, + INT_TMRA_8_OVF = 329U, + INT_TMRA_8_UDF = 330U, + INT_TMRA_8_CMP = 331U, + /* USART3 USART4 */ + INT_USART3_EI = 332U, + INT_USART3_RI = 333U, + INT_USART3_TI = 334U, + INT_USART3_TCI = 335U, + INT_USART4_EI = 336U, + INT_USART4_RI = 337U, + INT_USART4_TI = 338U, + INT_USART4_TCI = 339U, + /* CAN1 CAN2 */ + INT_CAN1_HOST = 340U, + INT_CAN2_HOST = 341U, + /* SPI3 SPI4 */ + INT_SPI3_SPRI = 342U, + INT_SPI3_SPTI = 343U, + INT_SPI3_SPII = 344U, + INT_SPI3_SPEI = 345U, + INT_SPI4_SPRI = 347U, + INT_SPI4_SPTI = 348U, + INT_SPI4_SPII = 349U, + INT_SPI4_SPEI = 350U, + /* TIMERA_9 TIMERA_10 TIMER_11 TIMER_12 */ + INT_TMRA_9_OVF = 352U, + INT_TMRA_9_UDF = 353U, + INT_TMRA_9_CMP = 354U, + INT_TMRA_10_OVF = 355U, + INT_TMRA_10_UDF = 356U, + INT_TMRA_10_CMP = 357U, + INT_TMRA_11_OVF = 358U, + INT_TMRA_11_UDF = 359U, + INT_TMRA_11_CMP = 360U, + INT_TMRA_12_OVF = 361U, + INT_TMRA_12_UDF = 362U, + INT_TMRA_12_CMP = 363U, + /* USART5 USART6 */ + INT_USART5_BRKWKPI = 364U, + INT_USART5_EI = 365U, + INT_USART5_RI = 366U, + INT_USART5_TI = 367U, + INT_USART5_TCI = 368U, + INT_USART6_EI = 369U, + INT_USART6_RI = 370U, + INT_USART6_TI = 371U, + INT_USART6_TCI = 372U, + INT_USART6_RTO = 373U, + /* SPI5 SPI6 */ + INT_SPI5_SPRI = 374U, + INT_SPI5_SPTI = 375U, + INT_SPI5_SPII = 376U, + INT_SPI5_SPEI = 377U, + INT_SPI6_SPRI = 379U, + INT_SPI6_SPTI = 380U, + INT_SPI6_SPII = 381U, + INT_SPI6_SPEI = 382U, + /* I2S1 I2S2 */ + INT_I2S1_TXIRQOUT = 384U, + INT_I2S1_RXIRQOUT = 385U, + INT_I2S1_ERRIRQOUT = 386U, + INT_I2S2_TXIRQOUT = 387U, + INT_I2S2_RXIRQOUT = 388U, + INT_I2S2_ERRIRQOUT = 389U, + /* USART7 USART8 */ + INT_USART7_EI = 390U, + INT_USART7_RI = 391U, + INT_USART7_TI = 392U, + INT_USART7_TCI = 393U, + INT_USART7_RTO = 394U, + INT_USART8_EI = 395U, + INT_USART8_RI = 396U, + INT_USART8_TI = 397U, + INT_USART8_TCI = 398U, + /* USBFS */ + INT_USBFS_GLB = 399U, + INT_USBFS_WKUP = 400U, + /* HASH */ + INT_HASH = 401U, + /* SDIOC */ + INT_SDIOC1_SD = 404U, + INT_SDIOC2_SD = 407U, + /* EVENT PORT */ + INT_EVENT_PORT1 = 408U, + INT_EVENT_PORT2 = 409U, + INT_EVENT_PORT3 = 410U, + INT_EVENT_PORT4 = 411U, + /* ETHER */ + INT_ETH_GLB_INT = 412U, + INT_ETH_WKP_INT = 413U, + /* I2S3 I2S4 */ + INT_I2S3_TXIRQOUT = 416U, + INT_I2S3_RXIRQOUT = 417U, + INT_I2S3_ERRIRQOUT = 418U, + INT_I2S4_TXIRQOUT = 419U, + INT_I2S4_RXIRQOUT = 420U, + INT_I2S4_ERRIRQOUT = 421U, + /* USART9 USART10 */ + INT_USART9_EI = 422U, + INT_USART9_RI = 423U, + INT_USART9_TI = 424U, + INT_USART9_TCI = 425U, + INT_USART10_BRKWKPI = 426U, + INT_USART10_EI = 427U, + INT_USART10_RI = 428U, + INT_USART10_TI = 429U, + INT_USART10_TCI = 430U, + /* I2C1 I2C2 I2C3 */ + INT_I2C1_RXI = 432U, + INT_I2C1_TXI = 433U, + INT_I2C1_TEI = 434U, + INT_I2C1_EEI = 435U, + INT_I2C2_RXI = 436U, + INT_I2C2_TXI = 437U, + INT_I2C2_TEI = 438U, + INT_I2C2_EEI = 439U, + INT_I2C3_RXI = 440U, + INT_I2C3_TXI = 441U, + INT_I2C3_TEI = 442U, + INT_I2C3_EEI = 443U, + /* ACMP */ + INT_CMP1 = 444U, + INT_CMP2 = 445U, + INT_CMP3 = 446U, + INT_CMP4 = 447U, + /* I2C4 I2C5 I2C6 */ + INT_I2C4_RXI = 448U, + INT_I2C4_TXI = 449U, + INT_I2C4_TEI = 450U, + INT_I2C4_EEI = 451U, + INT_I2C5_RXI = 452U, + INT_I2C5_TXI = 453U, + INT_I2C5_TEI = 454U, + INT_I2C5_EEI = 455U, + INT_I2C6_RXI = 456U, + INT_I2C6_TXI = 457U, + INT_I2C6_TEI = 458U, + INT_I2C6_EEI = 459U, + /* USART1 */ + INT_USART1_WUPI = 460U, + /* PVD */ + INT_PVD_PVD1 = 461U, + INT_PVD_PVD2 = 462U, + /* OTS */ + INT_OTS = 463U, + /* FCM */ + INT_FCMFERRI = 464U, + INT_FCMMENDI = 465U, + INT_FCMCOVFI = 466U, + /* WDT */ + INT_WDT_REFUDF = 467U, + /* CTC */ + INT_CTC_ERR = 468U, + /* ADC */ + INT_ADC1_EOCA = 480U, + INT_ADC1_EOCB = 481U, + INT_ADC1_CMP0 = 482U, + INT_ADC1_CMP1 = 483U, + INT_ADC2_EOCA = 484U, + INT_ADC2_EOCB = 485U, + INT_ADC2_CMP0 = 486U, + INT_ADC2_CMP1 = 487U, + INT_ADC3_EOCA = 488U, + INT_ADC3_EOCB = 489U, + INT_ADC3_CMP0 = 490U, + INT_ADC3_CMP1 = 491U, + /* TRNG */ + INT_TRNG_END = 492U, + /* NFC */ + INT_NFC_INT = 496U, + INT_SRC_MAX = 511U, +} en_int_src_t; + +#if defined ( __CC_ARM ) +#pragma anon_unions +#endif + +/******************************************************************************/ +/* Device Specific Peripheral Registers structures */ +/******************************************************************************/ +/** + * @brief ADC + */ +typedef struct +{ + __IO uint8_t STR; + uint8_t RESERVED0[1]; + __IO uint16_t CR0; + __IO uint16_t CR1; + uint8_t RESERVED1[4]; + __IO uint16_t TRGSR; + __IO uint32_t CHSELRA; + __IO uint32_t CHSELRB; + __IO uint32_t AVCHSELR; + __IO uint8_t EXCHSELR; + uint8_t RESERVED2[1]; + __IO uint16_t SHCR; + uint8_t RESERVED3[4]; + __IO uint8_t SSTR0; + __IO uint8_t SSTR1; + __IO uint8_t SSTR2; + __IO uint8_t SSTR3; + __IO uint8_t SSTR4; + __IO uint8_t SSTR5; + __IO uint8_t SSTR6; + __IO uint8_t SSTR7; + __IO uint8_t SSTR8; + __IO uint8_t SSTR9; + __IO uint8_t SSTR10; + __IO uint8_t SSTR11; + __IO uint8_t SSTR12; + __IO uint8_t SSTR13; + __IO uint8_t SSTR14; + __IO uint8_t SSTR15; + __IO uint8_t SSTRL; + uint8_t RESERVED4[7]; + __IO uint16_t CHMUXR0; + __IO uint16_t CHMUXR1; + __IO uint16_t CHMUXR2; + __IO uint16_t CHMUXR3; + uint8_t RESERVED5[4]; + __IO uint8_t ISR; + __IO uint8_t ICR; + __IO uint8_t ISCLRR; + uint8_t RESERVED6[5]; + __IO uint16_t SYNCCR; + uint8_t RESERVED7[2]; + __IO uint16_t DR0; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t DR3; + __IO uint16_t DR4; + __IO uint16_t DR5; + __IO uint16_t DR6; + __IO uint16_t DR7; + __IO uint16_t DR8; + __IO uint16_t DR9; + __IO uint16_t DR10; + __IO uint16_t DR11; + __IO uint16_t DR12; + __IO uint16_t DR13; + __IO uint16_t DR14; + __IO uint16_t DR15; + __IO uint16_t DR16; + __IO uint16_t DR17; + __IO uint16_t DR18; + __IO uint16_t DR19; + uint8_t RESERVED8[40]; + __IO uint16_t AWDCR; + __IO uint8_t AWDSR; + __IO uint8_t AWDSCLRR; + __IO uint16_t AWD0DR0; + __IO uint16_t AWD0DR1; + __IO uint16_t AWD0CHSR; + uint8_t RESERVED9[2]; + __IO uint16_t AWD1DR0; + __IO uint16_t AWD1DR1; + __IO uint16_t AWD1CHSR; + uint8_t RESERVED10[14]; + __IO uint8_t PGACR1; + __IO uint8_t PGACR2; + __IO uint8_t PGACR3; + uint8_t RESERVED11[1]; + __IO uint8_t PGAVSSENR; +} M4_ADC_TypeDef; + +/** + * @brief AES + */ +typedef struct +{ + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t KR0; + __IO uint32_t KR1; + __IO uint32_t KR2; + __IO uint32_t KR3; + __IO uint32_t KR4; + __IO uint32_t KR5; + __IO uint32_t KR6; + __IO uint32_t KR7; +} M4_AES_TypeDef; + +/** + * @brief AOS + */ +typedef struct +{ + __IO uint32_t INT_SFTTRG; + __IO uint32_t DCU_1_TRGSEL; + __IO uint32_t DCU_2_TRGSEL; + __IO uint32_t DCU_3_TRGSEL; + __IO uint32_t DCU_4_TRGSEL; + __IO uint32_t DMA_1_TRGSEL0; + __IO uint32_t DMA_1_TRGSEL1; + __IO uint32_t DMA_1_TRGSEL2; + __IO uint32_t DMA_1_TRGSEL3; + __IO uint32_t DMA_1_TRGSEL4; + __IO uint32_t DMA_1_TRGSEL5; + __IO uint32_t DMA_1_TRGSEL6; + __IO uint32_t DMA_1_TRGSEL7; + __IO uint32_t DMA_2_TRGSEL0; + __IO uint32_t DMA_2_TRGSEL1; + __IO uint32_t DMA_2_TRGSEL2; + __IO uint32_t DMA_2_TRGSEL3; + __IO uint32_t DMA_2_TRGSEL4; + __IO uint32_t DMA_2_TRGSEL5; + __IO uint32_t DMA_2_TRGSEL6; + __IO uint32_t DMA_2_TRGSEL7; + __IO uint32_t DMA_TRGSELRC; + __IO uint32_t TMR6_HTSSR1; + __IO uint32_t TMR6_HTSSR2; + __IO uint32_t TMR6_HTSSR3; + __IO uint32_t TMR6_HTSSR4; + __IO uint32_t PORT_PEVNTTRGSR12; + __IO uint32_t PORT_PEVNTTRGSR34; + __IO uint32_t TMR0_HTSSR; + __IO uint32_t TMR2_HTSSR; + __IO uint32_t HASH_ITRGSELA; + __IO uint32_t HASH_ITRGSELB; + __IO uint32_t TMRA_HTSSR0; + __IO uint32_t TMRA_HTSSR1; + __IO uint32_t TMRA_HTSSR2; + __IO uint32_t TMRA_HTSSR3; + __IO uint32_t OTS_TRG; + __IO uint32_t ADC_1_ITRGSELR0; + __IO uint32_t ADC_1_ITRGSELR1; + __IO uint32_t ADC_2_ITRGSELR0; + __IO uint32_t ADC_2_ITRGSELR1; + __IO uint32_t ADC_3_ITRGSELR0; + __IO uint32_t ADC_3_ITRGSELR1; + __IO uint32_t COMTRG1; + __IO uint32_t COMTRG2; + uint8_t RESERVED0[76]; + __IO uint32_t GPIO_PEVNTDIRR1; + __IO uint32_t GPIO_PEVNTIDR1; + __IO uint32_t GPIO_PEVNTODR1; + __IO uint32_t GPIO_PEVNTORR1; + __IO uint32_t GPIO_PEVNTOSR1; + __IO uint32_t GPIO_PEVNTRISR1; + __IO uint32_t GPIO_PEVNTFAL1; + __IO uint32_t GPIO_PEVNTDIRR2; + __IO uint32_t GPIO_PEVNTIDR2; + __IO uint32_t GPIO_PEVNTODR2; + __IO uint32_t GPIO_PEVNTORR2; + __IO uint32_t GPIO_PEVNTOSR2; + __IO uint32_t GPIO_PEVNTRISR2; + __IO uint32_t GPIO_PEVNTFAL2; + __IO uint32_t GPIO_PEVNTDIRR3; + __IO uint32_t GPIO_PEVNTIDR3; + __IO uint32_t GPIO_PEVNTODR3; + __IO uint32_t GPIO_PEVNTORR3; + __IO uint32_t GPIO_PEVNTOSR3; + __IO uint32_t GPIO_PEVNTRISR3; + __IO uint32_t GPIO_PEVNTFAL3; + __IO uint32_t GPIO_PEVNTDIRR4; + __IO uint32_t GPIO_PEVNTIDR4; + __IO uint32_t GPIO_PEVNTODR4; + __IO uint32_t GPIO_PEVNTORR4; + __IO uint32_t GPIO_PEVNTOSR4; + __IO uint32_t GPIO_PEVNTRISR4; + __IO uint32_t GPIO_PEVNTFAL4; + __IO uint32_t GPIO_PEVNTNFCR; +} M4_AOS_TypeDef; + +/** + * @brief CAN + */ +typedef struct +{ + __IO uint32_t RBUF; + uint8_t RESERVED0[76]; + __IO uint32_t TBUF; + uint8_t RESERVED1[76]; + __IO uint8_t CFG_STAT; + __IO uint8_t TCMD; + __IO uint8_t TCTRL; + __IO uint8_t RCTRL; + __IO uint8_t RTIE; + __IO uint8_t RTIF; + __IO uint8_t ERRINT; + __IO uint8_t LIMIT; + __IO uint32_t SBT; + __IO uint32_t FBT; + __IO uint8_t EALCAP; + __IO uint8_t TDC; + __IO uint8_t RECNT; + __IO uint8_t TECNT; + __IO uint8_t ACFCTRL; + uint8_t RESERVED2[1]; + __IO uint16_t ACFEN; + __IO uint32_t ACF; + uint8_t RESERVED3[2]; + __IO uint8_t TBSLOT; + __IO uint8_t TTCFG; + __IO uint32_t REF_MSG; + __IO uint16_t TRG_CFG; + __IO uint16_t TT_TRIG; + __IO uint16_t TT_WTRIG; +} M4_CAN_TypeDef; + +/** + * @brief CMP + */ +typedef struct +{ + __IO uint8_t MDR; + __IO uint8_t FIR; + __IO uint8_t OCR; + __IO uint8_t PMSR; + __IO uint16_t TWSR; + __IO uint16_t TWPR; + __IO uint16_t VISR; +} M4_CMP_TypeDef; + +/** + * @brief CMU + */ +typedef struct +{ + __IO uint8_t XTAL32CR; + uint8_t RESERVED0[3]; + __IO uint8_t XTAL32CFGR; + uint8_t RESERVED1[15]; + __IO uint8_t XTAL32NFR; + uint8_t RESERVED2[7]; + __IO uint8_t LRCCR; + uint8_t RESERVED3[3]; + __IO uint8_t RTCLRCCR; + uint8_t RESERVED4[3]; + __IO uint8_t LRCTRM; + uint8_t RESERVED5[7]; + __IO uint8_t RTCLRCTRM; + uint8_t RESERVED6[2123]; + __IO uint8_t XTALCFGR; + uint8_t RESERVED7[29591]; + __IO uint16_t PERICKSEL; + __IO uint16_t I2SCKSEL; + uint8_t RESERVED8[4]; + __IO uint8_t CANCKCFGR; + uint8_t RESERVED9[7]; + __IO uint32_t SCFGR; + __IO uint8_t USBCKCFGR; + uint8_t RESERVED10[1]; + __IO uint8_t CKSWR; + uint8_t RESERVED11[3]; + __IO uint8_t PLLHCR; + uint8_t RESERVED12[3]; + __IO uint8_t PLLACR; + uint8_t RESERVED13[3]; + __IO uint8_t XTALCR; + uint8_t RESERVED14[3]; + __IO uint8_t HRCCR; + uint8_t RESERVED15[1]; + __IO uint8_t MRCCR; + uint8_t RESERVED16[3]; + __IO uint8_t OSCSTBSR; + __IO uint8_t MCO1CFGR; + __IO uint8_t MCO2CFGR; + __IO uint8_t TPIUCKCFGR; + __IO uint8_t XTALSTDCR; + __IO uint8_t XTALSTDSR; + uint8_t RESERVED17[31]; + __IO uint8_t MRCTRM; + __IO uint8_t HRCTRM; + uint8_t RESERVED18[63]; + __IO uint8_t XTALSTBCR; + uint8_t RESERVED19[93]; + __IO uint32_t PLLHCFGR; + __IO uint32_t PLLACFGR; +} M4_CMU_TypeDef; + +/** + * @brief CRC + */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t RESLT; + uint8_t RESERVED0[120]; + __IO uint32_t DAT0; + __IO uint32_t DAT1; + __IO uint32_t DAT2; + __IO uint32_t DAT3; + __IO uint32_t DAT4; + __IO uint32_t DAT5; + __IO uint32_t DAT6; + __IO uint32_t DAT7; + __IO uint32_t DAT8; + __IO uint32_t DAT9; + __IO uint32_t DAT10; + __IO uint32_t DAT11; + __IO uint32_t DAT12; + __IO uint32_t DAT13; + __IO uint32_t DAT14; + __IO uint32_t DAT15; + __IO uint32_t DAT16; + __IO uint32_t DAT17; + __IO uint32_t DAT18; + __IO uint32_t DAT19; + __IO uint32_t DAT20; + __IO uint32_t DAT21; + __IO uint32_t DAT22; + __IO uint32_t DAT23; + __IO uint32_t DAT24; + __IO uint32_t DAT25; + __IO uint32_t DAT26; + __IO uint32_t DAT27; + __IO uint32_t DAT28; + __IO uint32_t DAT29; + __IO uint32_t DAT30; + __IO uint32_t DAT31; +} M4_CRC_TypeDef; + +/** + * @brief CTC + */ +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t STR; +} M4_CTC_TypeDef; + +/** + * @brief DAC + */ +typedef struct +{ + __IO uint16_t DADR1; + __IO uint16_t DADR2; + __IO uint16_t DACR; + __IO uint16_t DAADPCR; + uint8_t RESERVED0[20]; + __IO uint16_t DAOCR; +} M4_DAC_TypeDef; + +/** + * @brief DBGC + */ +typedef struct +{ + __IO uint32_t AUTHID0; + __IO uint32_t AUTHID1; + __IO uint32_t AUTHID2; + __IO uint32_t RESV0; + __IO uint32_t MCUSTAT; + __IO uint32_t MCUCTL; + __IO uint32_t FMCCTL; + __IO uint32_t MCUDBGCSTAT; + __IO uint32_t MCUSTPCTL; + __IO uint32_t MCUTRACECTL; + __IO uint32_t MCUSTPCTL2; +} M4_DBGC_TypeDef; + +/** + * @brief DCU + */ +typedef struct +{ + __IO uint32_t CTL; + __IO uint32_t FLAG; + __IO uint32_t DATA0; + __IO uint32_t DATA1; + __IO uint32_t DATA2; + __IO uint32_t FLAGCLR; + __IO uint32_t INTEVTSEL; +} M4_DCU_TypeDef; + +/** + * @brief DMA + */ +typedef struct +{ + __IO uint32_t EN; + __IO uint32_t INTSTAT0; + __IO uint32_t INTSTAT1; + __IO uint32_t INTMASK0; + __IO uint32_t INTMASK1; + __IO uint32_t INTCLR0; + __IO uint32_t INTCLR1; + __IO uint32_t CHEN; + __IO uint32_t REQSTAT; + __IO uint32_t CHSTAT; + uint8_t RESERVED0[4]; + __IO uint32_t RCFGCTL; + uint8_t RESERVED1[4]; + __IO uint32_t CHENCLR; + uint8_t RESERVED2[8]; + __IO uint32_t SAR0; + __IO uint32_t DAR0; + __IO uint32_t DTCTL0; + union + { + __IO uint32_t RPT0; + __IO uint32_t RPTB0; + }; + union + { + __IO uint32_t SNSEQCTL0; + __IO uint32_t SNSEQCTLB0; + }; + union + { + __IO uint32_t DNSEQCTL0; + __IO uint32_t DNSEQCTLB0; + }; + __IO uint32_t LLP0; + __IO uint32_t CHCTL0; + __IO uint32_t MONSAR0; + __IO uint32_t MONDAR0; + __IO uint32_t MONDTCTL0; + __IO uint32_t MONRPT0; + __IO uint32_t MONSNSEQCTL0; + __IO uint32_t MONDNSEQCTL0; + uint8_t RESERVED3[8]; + __IO uint32_t SAR1; + __IO uint32_t DAR1; + __IO uint32_t DTCTL1; + union + { + __IO uint32_t RPT1; + __IO uint32_t RPTB1; + }; + union + { + __IO uint32_t SNSEQCTL1; + __IO uint32_t SNSEQCTLB1; + }; + union + { + __IO uint32_t DNSEQCTL1; + __IO uint32_t DNSEQCTLB1; + }; + __IO uint32_t LLP1; + __IO uint32_t CHCTL1; + __IO uint32_t MONSAR1; + __IO uint32_t MONDAR1; + __IO uint32_t MONDTCTL1; + __IO uint32_t MONRPT1; + __IO uint32_t MONSNSEQCTL1; + __IO uint32_t MONDNSEQCTL1; + uint8_t RESERVED4[8]; + __IO uint32_t SAR2; + __IO uint32_t DAR2; + __IO uint32_t DTCTL2; + union + { + __IO uint32_t RPT2; + __IO uint32_t RPTB2; + }; + union + { + __IO uint32_t SNSEQCTL2; + __IO uint32_t SNSEQCTLB2; + }; + union + { + __IO uint32_t DNSEQCTL2; + __IO uint32_t DNSEQCTLB2; + }; + __IO uint32_t LLP2; + __IO uint32_t CHCTL2; + __IO uint32_t MONSAR2; + __IO uint32_t MONDAR2; + __IO uint32_t MONDTCTL2; + __IO uint32_t MONRPT2; + __IO uint32_t MONSNSEQCTL2; + __IO uint32_t MONDNSEQCTL2; + uint8_t RESERVED5[8]; + __IO uint32_t SAR3; + __IO uint32_t DAR3; + __IO uint32_t DTCTL3; + union + { + __IO uint32_t RPT3; + __IO uint32_t RPTB3; + }; + union + { + __IO uint32_t SNSEQCTL3; + __IO uint32_t SNSEQCTLB3; + }; + union + { + __IO uint32_t DNSEQCTL3; + __IO uint32_t DNSEQCTLB3; + }; + __IO uint32_t LLP3; + __IO uint32_t CHCTL3; + __IO uint32_t MONSAR3; + __IO uint32_t MONDAR3; + __IO uint32_t MONDTCTL3; + __IO uint32_t MONRPT3; + __IO uint32_t MONSNSEQCTL3; + __IO uint32_t MONDNSEQCTL3; + uint8_t RESERVED6[8]; + __IO uint32_t SAR4; + __IO uint32_t DAR4; + __IO uint32_t DTCTL4; + union + { + __IO uint32_t RPT4; + __IO uint32_t RPTB4; + }; + union + { + __IO uint32_t SNSEQCTL4; + __IO uint32_t SNSEQCTLB4; + }; + union + { + __IO uint32_t DNSEQCTL4; + __IO uint32_t DNSEQCTLB4; + }; + __IO uint32_t LLP4; + __IO uint32_t CHCTL4; + __IO uint32_t MONSAR4; + __IO uint32_t MONDAR4; + __IO uint32_t MONDTCTL4; + __IO uint32_t MONRPT4; + __IO uint32_t MONSNSEQCTL4; + __IO uint32_t MONDNSEQCTL4; + uint8_t RESERVED7[8]; + __IO uint32_t SAR5; + __IO uint32_t DAR5; + __IO uint32_t DTCTL5; + union + { + __IO uint32_t RPT5; + __IO uint32_t RPTB5; + }; + union + { + __IO uint32_t SNSEQCTL5; + __IO uint32_t SNSEQCTLB5; + }; + union + { + __IO uint32_t DNSEQCTL5; + __IO uint32_t DNSEQCTLB5; + }; + __IO uint32_t LLP5; + __IO uint32_t CHCTL5; + __IO uint32_t MONSAR5; + __IO uint32_t MONDAR5; + __IO uint32_t MONDTCTL5; + __IO uint32_t MONRPT5; + __IO uint32_t MONSNSEQCTL5; + __IO uint32_t MONDNSEQCTL5; + uint8_t RESERVED8[8]; + __IO uint32_t SAR6; + __IO uint32_t DAR6; + __IO uint32_t DTCTL6; + union + { + __IO uint32_t RPT6; + __IO uint32_t RPTB6; + }; + union + { + __IO uint32_t SNSEQCTL6; + __IO uint32_t SNSEQCTLB6; + }; + union + { + __IO uint32_t DNSEQCTL6; + __IO uint32_t DNSEQCTLB6; + }; + __IO uint32_t LLP6; + __IO uint32_t CHCTL6; + __IO uint32_t MONSAR6; + __IO uint32_t MONDAR6; + __IO uint32_t MONDTCTL6; + __IO uint32_t MONRPT6; + __IO uint32_t MONSNSEQCTL6; + __IO uint32_t MONDNSEQCTL6; + uint8_t RESERVED9[8]; + __IO uint32_t SAR7; + __IO uint32_t DAR7; + __IO uint32_t DTCTL7; + union + { + __IO uint32_t RPT7; + __IO uint32_t RPTB7; + }; + union + { + __IO uint32_t SNSEQCTL7; + __IO uint32_t SNSEQCTLB7; + }; + union + { + __IO uint32_t DNSEQCTL7; + __IO uint32_t DNSEQCTLB7; + }; + __IO uint32_t LLP7; + __IO uint32_t CHCTL7; + __IO uint32_t MONSAR7; + __IO uint32_t MONDAR7; + __IO uint32_t MONDTCTL7; + __IO uint32_t MONRPT7; + __IO uint32_t MONSNSEQCTL7; + __IO uint32_t MONDNSEQCTL7; +} M4_DMA_TypeDef; + +/** + * @brief DMC + */ +typedef struct +{ + __IO uint32_t STSR; + __IO uint32_t STCR; + __IO uint32_t CMDR; + __IO uint32_t CPCR; + __IO uint32_t RFTR; + __IO uint32_t TMCR_T_CASL; + __IO uint32_t TMCR_T_DQSS; + __IO uint32_t TMCR_T_MRD; + __IO uint32_t TMCR_T_RAS; + __IO uint32_t TMCR_T_RC; + __IO uint32_t TMCR_T_RCD; + __IO uint32_t TMCR_T_RFC; + __IO uint32_t TMCR_T_RP; + __IO uint32_t TMCR_T_RRD; + __IO uint32_t TMCR_T_WR; + __IO uint32_t TMCR_T_WTR; + __IO uint32_t TMCR_T_XP; + __IO uint32_t TMCR_T_XSR; + __IO uint32_t TMCR_T_ESR; + uint8_t RESERVED0[436]; + __IO uint32_t CSCR0; + __IO uint32_t CSCR1; + __IO uint32_t CSCR2; + __IO uint32_t CSCR3; + uint8_t RESERVED1[240]; + __IO uint32_t BACR; +} M4_DMC_TypeDef; + +/** + * @brief DVP + */ +typedef struct +{ + __IO uint32_t CTR; + __IO uint32_t DTR; + __IO uint32_t STR; + __IO uint32_t IER; + __IO uint32_t DMR; + uint8_t RESERVED0[12]; + __IO uint32_t SSYNDR; + __IO uint32_t SSYNMR; + __IO uint32_t CPSFTR; + __IO uint32_t CPSZER; +} M4_DVP_TypeDef; + +/** + * @brief EFM + */ +typedef struct +{ + __IO uint32_t FAPRT; + __IO uint32_t KEY1; + __IO uint32_t KEY2; + uint8_t RESERVED0[8]; + __IO uint32_t FSTP; + __IO uint32_t FRMC; + __IO uint32_t FWMC; + __IO uint32_t FSR; + __IO uint32_t FSCLR; + __IO uint32_t FITE; + __IO uint32_t FSWP; + uint8_t RESERVED1[16]; + __IO uint32_t FHDFG; + uint8_t RESERVED2[12]; + __IO uint32_t UQID0; + __IO uint32_t UQID1; + __IO uint32_t UQID2; + uint8_t RESERVED3[164]; + __IO uint32_t REMPRT; + __IO uint32_t REMCR0; + __IO uint32_t REMCR1; + uint8_t RESERVED4[116]; + __IO uint32_t WLOCK; + uint8_t RESERVED5[12]; + __IO uint32_t F0NWPRT0; + __IO uint32_t F0NWPRT1; + __IO uint32_t F0NWPRT2; + __IO uint32_t F0NWPRT3; + __IO uint32_t F1NWPRT0; + __IO uint32_t F1NWPRT1; + __IO uint32_t F1NWPRT2; + __IO uint32_t F1NWPRT3; +} M4_EFM_TypeDef; + +/** + * @brief EMB + */ +typedef struct +{ + __IO uint32_t CTL1; + __IO uint32_t CTL2; + __IO uint32_t SOE; + __IO uint32_t STAT; + __IO uint32_t STATCLR; + __IO uint32_t INTEN; + __IO uint32_t RLSSEL; +} M4_EMB_TypeDef; + +/** + * @brief ETH + */ +typedef struct +{ + uint8_t RESERVED0[21520]; + __IO uint32_t MAC_IFCONFR; + uint8_t RESERVED1[44012]; + __IO uint32_t MAC_CONFIGR; + __IO uint32_t MAC_FLTCTLR; + __IO uint32_t MAC_HASHTHR; + __IO uint32_t MAC_HASHTLR; + __IO uint32_t MAC_SMIADDR; + __IO uint32_t MAC_SMIDATR; + __IO uint32_t MAC_FLOCTLR; + __IO uint32_t MAC_VTAFLTR; + uint8_t RESERVED2[4]; + __IO uint32_t MAC_MACSTSR; + __IO uint32_t MAC_RTWKFFR; + __IO uint32_t MAC_PMTCTLR; + uint8_t RESERVED3[8]; + __IO uint32_t MAC_INTSTSR; + __IO uint32_t MAC_INTMSKR; + __IO uint32_t MAC_MACADHR0; + __IO uint32_t MAC_MACADLR0; + __IO uint32_t MAC_MACADHR1; + __IO uint32_t MAC_MACADLR1; + __IO uint32_t MAC_MACADHR2; + __IO uint32_t MAC_MACADLR2; + __IO uint32_t MAC_MACADHR3; + __IO uint32_t MAC_MACADLR3; + __IO uint32_t MAC_MACADHR4; + __IO uint32_t MAC_MACADLR4; + uint8_t RESERVED4[152]; + __IO uint32_t MMC_MMCCTLR; + __IO uint32_t MMC_REVSTSR; + __IO uint32_t MMC_TRSSTSR; + __IO uint32_t MMC_RITCTLR; + __IO uint32_t MMC_TITCTLR; + uint8_t RESERVED5[8]; + __IO uint32_t MMC_TXBRGFR; + __IO uint32_t MMC_TXMUGFR; + uint8_t RESERVED6[48]; + __IO uint32_t MMC_TXDEEFR; + __IO uint32_t MMC_TXLCEFR; + __IO uint32_t MMC_TXECEFR; + __IO uint32_t MMC_TXCAEFR; + uint8_t RESERVED7[4]; + __IO uint32_t MMC_TXUNGFR; + __IO uint32_t MMC_TXEDEFR; + uint8_t RESERVED8[28]; + __IO uint32_t MMC_RXBRGFR; + __IO uint32_t MMC_RXMUGFR; + __IO uint32_t MMC_RXCREFR; + __IO uint32_t MMC_RXALEFR; + __IO uint32_t MMC_RXRUEFR; + uint8_t RESERVED9[36]; + __IO uint32_t MMC_RXUNGFR; + __IO uint32_t MMC_RXLEEFR; + __IO uint32_t MMC_RXOREFR; + uint8_t RESERVED10[560]; + __IO uint32_t MAC_L34CTLR; + __IO uint32_t MAC_L4PORTR; + uint8_t RESERVED11[8]; + __IO uint32_t MAC_L3ADDRR0; + __IO uint32_t MAC_L3ADDRR1; + __IO uint32_t MAC_L3ADDRR2; + __IO uint32_t MAC_L3ADDRR3; + uint8_t RESERVED12[356]; + __IO uint32_t MAC_VTACTLR; + __IO uint32_t MAC_VLAHTBR; + uint8_t RESERVED13[372]; + __IO uint32_t PTP_TSPCTLR; + __IO uint32_t PTP_TSPNSAR; + __IO uint32_t PTP_TMSSECR; + __IO uint32_t PTP_TMSNSER; + __IO uint32_t PTP_TMUSECR; + __IO uint32_t PTP_TMUNSER; + __IO uint32_t PTP_TSPADDR; + __IO uint32_t PTP_TMTSECR0; + __IO uint32_t PTP_TMTNSER0; + uint8_t RESERVED14[4]; + __IO uint32_t PTP_TSPSTSR; + __IO uint32_t PTP_PPSCTLR; + uint8_t RESERVED15[80]; + __IO uint32_t PTP_TMTSECR1; + __IO uint32_t PTP_TMTNSER1; + uint8_t RESERVED16[2168]; + __IO uint32_t DMA_BUSMODR; + __IO uint32_t DMA_TXPOLLR; + __IO uint32_t DMA_RXPOLLR; + __IO uint32_t DMA_RXDLADR; + __IO uint32_t DMA_TXDLADR; + __IO uint32_t DMA_DMASTSR; + __IO uint32_t DMA_OPRMODR; + __IO uint32_t DMA_INTENAR; + __IO uint32_t DMA_RFRCNTR; + __IO uint32_t DMA_REVWDTR; + uint8_t RESERVED17[32]; + __IO uint32_t DMA_CHTXDER; + __IO uint32_t DMA_CHRXDER; + __IO uint32_t DMA_CHTXBFR; + __IO uint32_t DMA_CHRXBFR; +} M4_ETH_TypeDef; + +/** + * @brief FCM + */ +typedef struct +{ + __IO uint32_t LVR; + __IO uint32_t UVR; + __IO uint32_t CNTR; + __IO uint32_t STR; + __IO uint32_t MCCR; + __IO uint32_t RCCR; + __IO uint32_t RIER; + __IO uint32_t SR; + __IO uint32_t CLR; +} M4_FCM_TypeDef; + +/** + * @brief FMAC + */ +typedef struct +{ + __IO uint32_t ENR; + __IO uint32_t CTR; + __IO uint32_t IER; + __IO uint32_t DTR; + __IO uint32_t RTR0; + __IO uint32_t RTR1; + __IO uint32_t STR; + uint8_t RESERVED0[4]; + __IO uint32_t COR0; + __IO uint32_t COR1; + __IO uint32_t COR2; + __IO uint32_t COR3; + __IO uint32_t COR4; + __IO uint32_t COR5; + __IO uint32_t COR6; + __IO uint32_t COR7; + __IO uint32_t COR8; + __IO uint32_t COR9; + __IO uint32_t COR10; + __IO uint32_t COR11; + __IO uint32_t COR12; + __IO uint32_t COR13; + __IO uint32_t COR14; + __IO uint32_t COR15; + __IO uint32_t COR16; +} M4_FMAC_TypeDef; + +/** + * @brief GPIO + */ +typedef struct +{ + __IO uint16_t PIDRA; + uint8_t RESERVED0[2]; + __IO uint16_t PODRA; + __IO uint16_t POERA; + __IO uint16_t POSRA; + __IO uint16_t PORRA; + __IO uint16_t POTRA; + uint8_t RESERVED1[2]; + __IO uint16_t PIDRB; + uint8_t RESERVED2[2]; + __IO uint16_t PODRB; + __IO uint16_t POERB; + __IO uint16_t POSRB; + __IO uint16_t PORRB; + __IO uint16_t POTRB; + uint8_t RESERVED3[2]; + __IO uint16_t PIDRC; + uint8_t RESERVED4[2]; + __IO uint16_t PODRC; + __IO uint16_t POERC; + __IO uint16_t POSRC; + __IO uint16_t PORRC; + __IO uint16_t POTRC; + uint8_t RESERVED5[2]; + __IO uint16_t PIDRD; + uint8_t RESERVED6[2]; + __IO uint16_t PODRD; + __IO uint16_t POERD; + __IO uint16_t POSRD; + __IO uint16_t PORRD; + __IO uint16_t POTRD; + uint8_t RESERVED7[2]; + __IO uint16_t PIDRE; + uint8_t RESERVED8[2]; + __IO uint16_t PODRE; + __IO uint16_t POERE; + __IO uint16_t POSRE; + __IO uint16_t PORRE; + __IO uint16_t POTRE; + uint8_t RESERVED9[2]; + __IO uint16_t PIDRF; + uint8_t RESERVED10[2]; + __IO uint16_t PODRF; + __IO uint16_t POERF; + __IO uint16_t POSRF; + __IO uint16_t PORRF; + __IO uint16_t POTRF; + uint8_t RESERVED11[2]; + __IO uint16_t PIDRG; + uint8_t RESERVED12[2]; + __IO uint16_t PODRG; + __IO uint16_t POERG; + __IO uint16_t POSRG; + __IO uint16_t PORRG; + __IO uint16_t POTRG; + uint8_t RESERVED13[2]; + __IO uint16_t PIDRH; + uint8_t RESERVED14[2]; + __IO uint16_t PODRH; + __IO uint16_t POERH; + __IO uint16_t POSRH; + __IO uint16_t PORRH; + __IO uint16_t POTRH; + uint8_t RESERVED15[2]; + __IO uint16_t PIDRI; + uint8_t RESERVED16[2]; + __IO uint16_t PODRI; + __IO uint16_t POERI; + __IO uint16_t POSRI; + __IO uint16_t PORRI; + __IO uint16_t POTRI; + uint8_t RESERVED17[870]; + __IO uint16_t PSPCR; + uint8_t RESERVED18[2]; + __IO uint16_t PCCR; + __IO uint16_t PINAER; + __IO uint16_t PWPR; + uint8_t RESERVED19[2]; + __IO uint16_t PCRA0; + __IO uint16_t PFSRA0; + __IO uint16_t PCRA1; + __IO uint16_t PFSRA1; + __IO uint16_t PCRA2; + __IO uint16_t PFSRA2; + __IO uint16_t PCRA3; + __IO uint16_t PFSRA3; + __IO uint16_t PCRA4; + __IO uint16_t PFSRA4; + __IO uint16_t PCRA5; + __IO uint16_t PFSRA5; + __IO uint16_t PCRA6; + __IO uint16_t PFSRA6; + __IO uint16_t PCRA7; + __IO uint16_t PFSRA7; + __IO uint16_t PCRA8; + __IO uint16_t PFSRA8; + __IO uint16_t PCRA9; + __IO uint16_t PFSRA9; + __IO uint16_t PCRA10; + __IO uint16_t PFSRA10; + __IO uint16_t PCRA11; + __IO uint16_t PFSRA11; + __IO uint16_t PCRA12; + __IO uint16_t PFSRA12; + __IO uint16_t PCRA13; + __IO uint16_t PFSRA13; + __IO uint16_t PCRA14; + __IO uint16_t PFSRA14; + __IO uint16_t PCRA15; + __IO uint16_t PFSRA15; + __IO uint16_t PCRB0; + __IO uint16_t PFSRB0; + __IO uint16_t PCRB1; + __IO uint16_t PFSRB1; + __IO uint16_t PCRB2; + __IO uint16_t PFSRB2; + __IO uint16_t PCRB3; + __IO uint16_t PFSRB3; + __IO uint16_t PCRB4; + __IO uint16_t PFSRB4; + __IO uint16_t PCRB5; + __IO uint16_t PFSRB5; + __IO uint16_t PCRB6; + __IO uint16_t PFSRB6; + __IO uint16_t PCRB7; + __IO uint16_t PFSRB7; + __IO uint16_t PCRB8; + __IO uint16_t PFSRB8; + __IO uint16_t PCRB9; + __IO uint16_t PFSRB9; + __IO uint16_t PCRB10; + __IO uint16_t PFSRB10; + __IO uint16_t PCRB11; + __IO uint16_t PFSRB11; + __IO uint16_t PCRB12; + __IO uint16_t PFSRB12; + __IO uint16_t PCRB13; + __IO uint16_t PFSRB13; + __IO uint16_t PCRB14; + __IO uint16_t PFSRB14; + __IO uint16_t PCRB15; + __IO uint16_t PFSRB15; + __IO uint16_t PCRC0; + __IO uint16_t PFSRC0; + __IO uint16_t PCRC1; + __IO uint16_t PFSRC1; + __IO uint16_t PCRC2; + __IO uint16_t PFSRC2; + __IO uint16_t PCRC3; + __IO uint16_t PFSRC3; + __IO uint16_t PCRC4; + __IO uint16_t PFSRC4; + __IO uint16_t PCRC5; + __IO uint16_t PFSRC5; + __IO uint16_t PCRC6; + __IO uint16_t PFSRC6; + __IO uint16_t PCRC7; + __IO uint16_t PFSRC7; + __IO uint16_t PCRC8; + __IO uint16_t PFSRC8; + __IO uint16_t PCRC9; + __IO uint16_t PFSRC9; + __IO uint16_t PCRC10; + __IO uint16_t PFSRC10; + __IO uint16_t PCRC11; + __IO uint16_t PFSRC11; + __IO uint16_t PCRC12; + __IO uint16_t PFSRC12; + __IO uint16_t PCRC13; + __IO uint16_t PFSRC13; + __IO uint16_t PCRC14; + __IO uint16_t PFSRC14; + __IO uint16_t PCRC15; + __IO uint16_t PFSRC15; + __IO uint16_t PCRD0; + __IO uint16_t PFSRD0; + __IO uint16_t PCRD1; + __IO uint16_t PFSRD1; + __IO uint16_t PCRD2; + __IO uint16_t PFSRD2; + __IO uint16_t PCRD3; + __IO uint16_t PFSRD3; + __IO uint16_t PCRD4; + __IO uint16_t PFSRD4; + __IO uint16_t PCRD5; + __IO uint16_t PFSRD5; + __IO uint16_t PCRD6; + __IO uint16_t PFSRD6; + __IO uint16_t PCRD7; + __IO uint16_t PFSRD7; + __IO uint16_t PCRD8; + __IO uint16_t PFSRD8; + __IO uint16_t PCRD9; + __IO uint16_t PFSRD9; + __IO uint16_t PCRD10; + __IO uint16_t PFSRD10; + __IO uint16_t PCRD11; + __IO uint16_t PFSRD11; + __IO uint16_t PCRD12; + __IO uint16_t PFSRD12; + __IO uint16_t PCRD13; + __IO uint16_t PFSRD13; + __IO uint16_t PCRD14; + __IO uint16_t PFSRD14; + __IO uint16_t PCRD15; + __IO uint16_t PFSRD15; + __IO uint16_t PCRE0; + __IO uint16_t PFSRE0; + __IO uint16_t PCRE1; + __IO uint16_t PFSRE1; + __IO uint16_t PCRE2; + __IO uint16_t PFSRE2; + __IO uint16_t PCRE3; + __IO uint16_t PFSRE3; + __IO uint16_t PCRE4; + __IO uint16_t PFSRE4; + __IO uint16_t PCRE5; + __IO uint16_t PFSRE5; + __IO uint16_t PCRE6; + __IO uint16_t PFSRE6; + __IO uint16_t PCRE7; + __IO uint16_t PFSRE7; + __IO uint16_t PCRE8; + __IO uint16_t PFSRE8; + __IO uint16_t PCRE9; + __IO uint16_t PFSRE9; + __IO uint16_t PCRE10; + __IO uint16_t PFSRE10; + __IO uint16_t PCRE11; + __IO uint16_t PFSRE11; + __IO uint16_t PCRE12; + __IO uint16_t PFSRE12; + __IO uint16_t PCRE13; + __IO uint16_t PFSRE13; + __IO uint16_t PCRE14; + __IO uint16_t PFSRE14; + __IO uint16_t PCRE15; + __IO uint16_t PFSRE15; + __IO uint16_t PCRF0; + __IO uint16_t PFSRF0; + __IO uint16_t PCRF1; + __IO uint16_t PFSRF1; + __IO uint16_t PCRF2; + __IO uint16_t PFSRF2; + __IO uint16_t PCRF3; + __IO uint16_t PFSRF3; + __IO uint16_t PCRF4; + __IO uint16_t PFSRF4; + __IO uint16_t PCRF5; + __IO uint16_t PFSRF5; + __IO uint16_t PCRF6; + __IO uint16_t PFSRF6; + __IO uint16_t PCRF7; + __IO uint16_t PFSRF7; + __IO uint16_t PCRF8; + __IO uint16_t PFSRF8; + __IO uint16_t PCRF9; + __IO uint16_t PFSRF9; + __IO uint16_t PCRF10; + __IO uint16_t PFSRF10; + __IO uint16_t PCRF11; + __IO uint16_t PFSRF11; + __IO uint16_t PCRF12; + __IO uint16_t PFSRF12; + __IO uint16_t PCRF13; + __IO uint16_t PFSRF13; + __IO uint16_t PCRF14; + __IO uint16_t PFSRF14; + __IO uint16_t PCRF15; + __IO uint16_t PFSRF15; + __IO uint16_t PCRG0; + __IO uint16_t PFSRG0; + __IO uint16_t PCRG1; + __IO uint16_t PFSRG1; + __IO uint16_t PCRG2; + __IO uint16_t PFSRG2; + __IO uint16_t PCRG3; + __IO uint16_t PFSRG3; + __IO uint16_t PCRG4; + __IO uint16_t PFSRG4; + __IO uint16_t PCRG5; + __IO uint16_t PFSRG5; + __IO uint16_t PCRG6; + __IO uint16_t PFSRG6; + __IO uint16_t PCRG7; + __IO uint16_t PFSRG7; + __IO uint16_t PCRG8; + __IO uint16_t PFSRG8; + __IO uint16_t PCRG9; + __IO uint16_t PFSRG9; + __IO uint16_t PCRG10; + __IO uint16_t PFSRG10; + __IO uint16_t PCRG11; + __IO uint16_t PFSRG11; + __IO uint16_t PCRG12; + __IO uint16_t PFSRG12; + __IO uint16_t PCRG13; + __IO uint16_t PFSRG13; + __IO uint16_t PCRG14; + __IO uint16_t PFSRG14; + __IO uint16_t PCRG15; + __IO uint16_t PFSRG15; + __IO uint16_t PCRH0; + __IO uint16_t PFSRH0; + __IO uint16_t PCRH1; + __IO uint16_t PFSRH1; + __IO uint16_t PCRH2; + __IO uint16_t PFSRH2; + __IO uint16_t PCRH3; + __IO uint16_t PFSRH3; + __IO uint16_t PCRH4; + __IO uint16_t PFSRH4; + __IO uint16_t PCRH5; + __IO uint16_t PFSRH5; + __IO uint16_t PCRH6; + __IO uint16_t PFSRH6; + __IO uint16_t PCRH7; + __IO uint16_t PFSRH7; + __IO uint16_t PCRH8; + __IO uint16_t PFSRH8; + __IO uint16_t PCRH9; + __IO uint16_t PFSRH9; + __IO uint16_t PCRH10; + __IO uint16_t PFSRH10; + __IO uint16_t PCRH11; + __IO uint16_t PFSRH11; + __IO uint16_t PCRH12; + __IO uint16_t PFSRH12; + __IO uint16_t PCRH13; + __IO uint16_t PFSRH13; + __IO uint16_t PCRH14; + __IO uint16_t PFSRH14; + __IO uint16_t PCRH15; + __IO uint16_t PFSRH15; + __IO uint16_t PCRI0; + __IO uint16_t PFSRI0; + __IO uint16_t PCRI1; + __IO uint16_t PFSRI1; + __IO uint16_t PCRI2; + __IO uint16_t PFSRI2; + __IO uint16_t PCRI3; + __IO uint16_t PFSRI3; + __IO uint16_t PCRI4; + __IO uint16_t PFSRI4; + __IO uint16_t PCRI5; + __IO uint16_t PFSRI5; + __IO uint16_t PCRI6; + __IO uint16_t PFSRI6; + __IO uint16_t PCRI7; + __IO uint16_t PFSRI7; + __IO uint16_t PCRI8; + __IO uint16_t PFSRI8; + __IO uint16_t PCRI9; + __IO uint16_t PFSRI9; + __IO uint16_t PCRI10; + __IO uint16_t PFSRI10; + __IO uint16_t PCRI11; + __IO uint16_t PFSRI11; + __IO uint16_t PCRI12; + __IO uint16_t PFSRI12; + __IO uint16_t PCRI13; + __IO uint16_t PFSRI13; +} M4_GPIO_TypeDef; + +/** + * @brief HASH + */ +typedef struct +{ + __IO uint32_t CR; + uint8_t RESERVED0[12]; + __IO uint32_t HR7; + __IO uint32_t HR6; + __IO uint32_t HR5; + __IO uint32_t HR4; + __IO uint32_t HR3; + __IO uint32_t HR2; + __IO uint32_t HR1; + __IO uint32_t HR0; + uint8_t RESERVED1[16]; + __IO uint32_t DR15; + __IO uint32_t DR14; + __IO uint32_t DR13; + __IO uint32_t DR12; + __IO uint32_t DR11; + __IO uint32_t DR10; + __IO uint32_t DR9; + __IO uint32_t DR8; + __IO uint32_t DR7; + __IO uint32_t DR6; + __IO uint32_t DR5; + __IO uint32_t DR4; + __IO uint32_t DR3; + __IO uint32_t DR2; + __IO uint32_t DR1; + __IO uint32_t DR0; +} M4_HASH_TypeDef; + +/** + * @brief HRPWM + */ +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t CR4; + __IO uint32_t CR5; + __IO uint32_t CR6; + __IO uint32_t CR7; + __IO uint32_t CR8; + __IO uint32_t CR9; + __IO uint32_t CR10; + __IO uint32_t CR11; + __IO uint32_t CR12; + __IO uint32_t CR13; + __IO uint32_t CR14; + __IO uint32_t CR15; + __IO uint32_t CR16; + uint8_t RESERVED0[16]; + __IO uint32_t CALCR0; + __IO uint32_t CALCR1; +} M4_HRPWM_TypeDef; + +/** + * @brief I2C + */ +typedef struct +{ + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + uint8_t RESERVED0[4]; + __IO uint32_t SLR0; + __IO uint32_t SLR1; + __IO uint32_t SLTR; + __IO uint32_t SR; + __IO uint32_t CLR; + __IO uint8_t DTR; + uint8_t RESERVED1[3]; + __IO uint8_t DRR; + uint8_t RESERVED2[3]; + __IO uint32_t CCR; + __IO uint32_t FLTR; +} M4_I2C_TypeDef; + +/** + * @brief I2S + */ +typedef struct +{ + __IO uint32_t CTRL; + __IO uint32_t SR; + __IO uint32_t ER; + __IO uint32_t CFGR; + __IO uint32_t TXBUF; + __IO uint32_t RXBUF; + __IO uint32_t PR; +} M4_I2S_TypeDef; + +/** + * @brief ICG + */ +typedef struct +{ + __IO uint32_t ICG0; + __IO uint32_t ICG1; + __IO uint32_t ICG2; + __IO uint32_t ICG3; +} M4_ICG_TypeDef; + +/** + * @brief INTC + */ +typedef struct +{ + __IO uint32_t NOCCR; + __IO uint32_t NMIENR; + __IO uint32_t NMIFR; + __IO uint32_t NMICFR; + __IO uint32_t EIRQCR0; + __IO uint32_t EIRQCR1; + __IO uint32_t EIRQCR2; + __IO uint32_t EIRQCR3; + __IO uint32_t EIRQCR4; + __IO uint32_t EIRQCR5; + __IO uint32_t EIRQCR6; + __IO uint32_t EIRQCR7; + __IO uint32_t EIRQCR8; + __IO uint32_t EIRQCR9; + __IO uint32_t EIRQCR10; + __IO uint32_t EIRQCR11; + __IO uint32_t EIRQCR12; + __IO uint32_t EIRQCR13; + __IO uint32_t EIRQCR14; + __IO uint32_t EIRQCR15; + __IO uint32_t WUPEN; + __IO uint32_t EIFR; + __IO uint32_t EICFR; + __IO uint32_t SEL0; + __IO uint32_t SEL1; + __IO uint32_t SEL2; + __IO uint32_t SEL3; + __IO uint32_t SEL4; + __IO uint32_t SEL5; + __IO uint32_t SEL6; + __IO uint32_t SEL7; + __IO uint32_t SEL8; + __IO uint32_t SEL9; + __IO uint32_t SEL10; + __IO uint32_t SEL11; + __IO uint32_t SEL12; + __IO uint32_t SEL13; + __IO uint32_t SEL14; + __IO uint32_t SEL15; + __IO uint32_t SEL16; + __IO uint32_t SEL17; + __IO uint32_t SEL18; + __IO uint32_t SEL19; + __IO uint32_t SEL20; + __IO uint32_t SEL21; + __IO uint32_t SEL22; + __IO uint32_t SEL23; + __IO uint32_t SEL24; + __IO uint32_t SEL25; + __IO uint32_t SEL26; + __IO uint32_t SEL27; + __IO uint32_t SEL28; + __IO uint32_t SEL29; + __IO uint32_t SEL30; + __IO uint32_t SEL31; + __IO uint32_t SEL32; + __IO uint32_t SEL33; + __IO uint32_t SEL34; + __IO uint32_t SEL35; + __IO uint32_t SEL36; + __IO uint32_t SEL37; + __IO uint32_t SEL38; + __IO uint32_t SEL39; + __IO uint32_t SEL40; + __IO uint32_t SEL41; + __IO uint32_t SEL42; + __IO uint32_t SEL43; + __IO uint32_t SEL44; + __IO uint32_t SEL45; + __IO uint32_t SEL46; + __IO uint32_t SEL47; + __IO uint32_t SEL48; + __IO uint32_t SEL49; + __IO uint32_t SEL50; + __IO uint32_t SEL51; + __IO uint32_t SEL52; + __IO uint32_t SEL53; + __IO uint32_t SEL54; + __IO uint32_t SEL55; + __IO uint32_t SEL56; + __IO uint32_t SEL57; + __IO uint32_t SEL58; + __IO uint32_t SEL59; + __IO uint32_t SEL60; + __IO uint32_t SEL61; + __IO uint32_t SEL62; + __IO uint32_t SEL63; + __IO uint32_t SEL64; + __IO uint32_t SEL65; + __IO uint32_t SEL66; + __IO uint32_t SEL67; + __IO uint32_t SEL68; + __IO uint32_t SEL69; + __IO uint32_t SEL70; + __IO uint32_t SEL71; + __IO uint32_t SEL72; + __IO uint32_t SEL73; + __IO uint32_t SEL74; + __IO uint32_t SEL75; + __IO uint32_t SEL76; + __IO uint32_t SEL77; + __IO uint32_t SEL78; + __IO uint32_t SEL79; + __IO uint32_t SEL80; + __IO uint32_t SEL81; + __IO uint32_t SEL82; + __IO uint32_t SEL83; + __IO uint32_t SEL84; + __IO uint32_t SEL85; + __IO uint32_t SEL86; + __IO uint32_t SEL87; + __IO uint32_t SEL88; + __IO uint32_t SEL89; + __IO uint32_t SEL90; + __IO uint32_t SEL91; + __IO uint32_t SEL92; + __IO uint32_t SEL93; + __IO uint32_t SEL94; + __IO uint32_t SEL95; + __IO uint32_t SEL96; + __IO uint32_t SEL97; + __IO uint32_t SEL98; + __IO uint32_t SEL99; + __IO uint32_t SEL100; + __IO uint32_t SEL101; + __IO uint32_t SEL102; + __IO uint32_t SEL103; + __IO uint32_t SEL104; + __IO uint32_t SEL105; + __IO uint32_t SEL106; + __IO uint32_t SEL107; + __IO uint32_t SEL108; + __IO uint32_t SEL109; + __IO uint32_t SEL110; + __IO uint32_t SEL111; + __IO uint32_t SEL112; + __IO uint32_t SEL113; + __IO uint32_t SEL114; + __IO uint32_t SEL115; + __IO uint32_t SEL116; + __IO uint32_t SEL117; + __IO uint32_t SEL118; + __IO uint32_t SEL119; + __IO uint32_t SEL120; + __IO uint32_t SEL121; + __IO uint32_t SEL122; + __IO uint32_t SEL123; + __IO uint32_t SEL124; + __IO uint32_t SEL125; + __IO uint32_t SEL126; + __IO uint32_t SEL127; + __IO uint32_t VSSEL128; + __IO uint32_t VSSEL129; + __IO uint32_t VSSEL130; + __IO uint32_t VSSEL131; + __IO uint32_t VSSEL132; + __IO uint32_t VSSEL133; + __IO uint32_t VSSEL134; + __IO uint32_t VSSEL135; + __IO uint32_t VSSEL136; + __IO uint32_t VSSEL137; + __IO uint32_t VSSEL138; + __IO uint32_t VSSEL139; + __IO uint32_t VSSEL140; + __IO uint32_t VSSEL141; + __IO uint32_t VSSEL142; + __IO uint32_t VSSEL143; + __IO uint32_t SWIER; + __IO uint32_t EVTER; + __IO uint32_t IER; +} M4_INTC_TypeDef; + +/** + * @brief KEYSCAN + */ +typedef struct +{ + __IO uint32_t SCR; + __IO uint32_t SER; + __IO uint32_t SSR; +} M4_KEYSCAN_TypeDef; + +/** + * @brief MAU + */ +typedef struct +{ + __IO uint32_t CSR; + __IO uint32_t DTR0; + uint8_t RESERVED0[4]; + __IO uint32_t RTR0; + __IO uint32_t DTR1; + __IO uint32_t RTR1; +} M4_MAU_TypeDef; + +/** + * @brief MPU + */ +typedef struct +{ + __IO uint32_t RGD0; + __IO uint32_t RGD1; + __IO uint32_t RGD2; + __IO uint32_t RGD3; + __IO uint32_t RGD4; + __IO uint32_t RGD5; + __IO uint32_t RGD6; + __IO uint32_t RGD7; + __IO uint32_t RGD8; + __IO uint32_t RGD9; + __IO uint32_t RGD10; + __IO uint32_t RGD11; + __IO uint32_t RGD12; + __IO uint32_t RGD13; + __IO uint32_t RGD14; + __IO uint32_t RGD15; + __IO uint32_t SR; + __IO uint32_t ECLR; + __IO uint32_t WP; + __IO uint32_t IPPR; + __IO uint32_t S1RGE; + __IO uint32_t S1RGWP; + __IO uint32_t S1RGRP; + __IO uint32_t S1CR; + __IO uint32_t S2RGE; + __IO uint32_t S2RGWP; + __IO uint32_t S2RGRP; + __IO uint32_t S2CR; + __IO uint32_t FRGE; + __IO uint32_t FRGWP; + __IO uint32_t FRGRP; + __IO uint32_t FCR; + __IO uint32_t HRGE; + __IO uint32_t HRGWP; + __IO uint32_t HRGRP; + __IO uint32_t HCR; + __IO uint32_t ERGE; + __IO uint32_t ERGWP; + __IO uint32_t ERGRP; + __IO uint32_t ECR; +} M4_MPU_TypeDef; + +/** + * @brief NFC + */ +typedef struct +{ + __IO uint32_t DATR_BASE; + uint8_t RESERVED0[32764]; + __IO uint32_t CMDR; + __IO uint32_t IDXR0; + uint8_t RESERVED1[40]; + __IO uint32_t IENR; + __IO uint32_t ISTR; + __IO uint32_t IRSR; + uint8_t RESERVED2[12]; + __IO uint32_t IDXR1; + __IO uint32_t TMCR0; + __IO uint32_t TMCR1; + __IO uint32_t BACR; + uint8_t RESERVED3[4]; + __IO uint32_t TMCR2; + __IO uint32_t ECCR0; + __IO uint32_t ECCR1; + __IO uint32_t ECCR2; + __IO uint32_t ECCR3; + __IO uint32_t ECCR4; + __IO uint32_t ECCR5; + __IO uint32_t ECCR6; + __IO uint32_t ECC_STAT; + __IO uint32_t ECC_SYND0_0; + __IO uint32_t ECC_SYND0_1; + __IO uint32_t ECC_SYND0_2; + __IO uint32_t ECC_SYND0_3; + __IO uint32_t ECC_SYND1_0; + __IO uint32_t ECC_SYND1_1; + __IO uint32_t ECC_SYND1_2; + __IO uint32_t ECC_SYND1_3; + __IO uint32_t ECC_SYND2_0; + __IO uint32_t ECC_SYND2_1; + __IO uint32_t ECC_SYND2_2; + __IO uint32_t ECC_SYND2_3; + __IO uint32_t ECC_SYND3_0; + __IO uint32_t ECC_SYND3_1; + __IO uint32_t ECC_SYND3_2; + __IO uint32_t ECC_SYND3_3; + __IO uint32_t ECC_SYND4_0; + __IO uint32_t ECC_SYND4_1; + __IO uint32_t ECC_SYND4_2; + __IO uint32_t ECC_SYND4_3; + __IO uint32_t ECC_SYND5_0; + __IO uint32_t ECC_SYND5_1; + __IO uint32_t ECC_SYND5_2; + __IO uint32_t ECC_SYND5_3; + __IO uint32_t ECC_SYND6_0; + __IO uint32_t ECC_SYND6_1; + __IO uint32_t ECC_SYND6_2; + __IO uint32_t ECC_SYND6_3; + __IO uint32_t ECC_SYND7_0; + __IO uint32_t ECC_SYND7_1; + __IO uint32_t ECC_SYND7_2; + __IO uint32_t ECC_SYND7_3; + __IO uint32_t ECC_SYND8_0; + __IO uint32_t ECC_SYND8_1; + __IO uint32_t ECC_SYND8_2; + __IO uint32_t ECC_SYND8_3; + __IO uint32_t ECC_SYND9_0; + __IO uint32_t ECC_SYND9_1; + __IO uint32_t ECC_SYND9_2; + __IO uint32_t ECC_SYND9_3; + __IO uint32_t ECC_SYND10_0; + __IO uint32_t ECC_SYND10_1; + __IO uint32_t ECC_SYND10_2; + __IO uint32_t ECC_SYND10_3; + __IO uint32_t ECC_SYND11_0; + __IO uint32_t ECC_SYND11_1; + __IO uint32_t ECC_SYND11_2; + __IO uint32_t ECC_SYND11_3; + __IO uint32_t ECC_SYND12_0; + __IO uint32_t ECC_SYND12_1; + __IO uint32_t ECC_SYND12_2; + __IO uint32_t ECC_SYND12_3; + __IO uint32_t ECC_SYND13_0; + __IO uint32_t ECC_SYND13_1; + __IO uint32_t ECC_SYND13_2; + __IO uint32_t ECC_SYND13_3; + __IO uint32_t ECC_SYND14_0; + __IO uint32_t ECC_SYND14_1; + __IO uint32_t ECC_SYND14_2; + __IO uint32_t ECC_SYND14_3; + __IO uint32_t ECC_SYND15_0; + __IO uint32_t ECC_SYND15_1; + __IO uint32_t ECC_SYND15_2; + __IO uint32_t ECC_SYND15_3; +} M4_NFC_TypeDef; + +/** + * @brief OTS + */ +typedef struct +{ + __IO uint16_t CTL; + __IO uint16_t DR1; + __IO uint16_t DR2; + __IO uint16_t ECR; + __IO uint32_t LPR; +} M4_OTS_TypeDef; + +/** + * @brief PERIC + */ +typedef struct +{ + __IO uint32_t USB_SYCTLREG; + __IO uint32_t SDIOC_SYCTLREG; + __IO uint32_t NFC_SYCTLREG; + __IO uint32_t EXMC_ENAR; + uint8_t RESERVED0[8]; + __IO uint32_t CAN_SYCTLREG; + __IO uint32_t USART1_NFC; + uint8_t RESERVED1[8]; + __IO uint32_t NFC_SYSTATREG; +} M4_PERIC_TypeDef; + +/** + * @brief PWC + */ +typedef struct +{ + __IO uint32_t FCG0; + __IO uint32_t FCG1; + __IO uint32_t FCG2; + __IO uint32_t FCG3; + __IO uint32_t FCG0PC; + uint8_t RESERVED0[17436]; + __IO uint8_t VBATRSTR; + uint8_t RESERVED1[15]; + __IO uint8_t VBATCR; + uint8_t RESERVED2[15]; + __IO uint8_t WKTC0; + uint8_t RESERVED3[3]; + __IO uint8_t WKTC1; + uint8_t RESERVED4[3]; + __IO uint8_t WKTC2; + uint8_t RESERVED5[423]; + __IO uint8_t BKR0; + uint8_t RESERVED6[3]; + __IO uint8_t BKR1; + uint8_t RESERVED7[3]; + __IO uint8_t BKR2; + uint8_t RESERVED8[3]; + __IO uint8_t BKR3; + uint8_t RESERVED9[3]; + __IO uint8_t BKR4; + uint8_t RESERVED10[3]; + __IO uint8_t BKR5; + uint8_t RESERVED11[3]; + __IO uint8_t BKR6; + uint8_t RESERVED12[3]; + __IO uint8_t BKR7; + uint8_t RESERVED13[3]; + __IO uint8_t BKR8; + uint8_t RESERVED14[3]; + __IO uint8_t BKR9; + uint8_t RESERVED15[3]; + __IO uint8_t BKR10; + uint8_t RESERVED16[3]; + __IO uint8_t BKR11; + uint8_t RESERVED17[3]; + __IO uint8_t BKR12; + uint8_t RESERVED18[3]; + __IO uint8_t BKR13; + uint8_t RESERVED19[3]; + __IO uint8_t BKR14; + uint8_t RESERVED20[3]; + __IO uint8_t BKR15; + uint8_t RESERVED21[3]; + __IO uint8_t BKR16; + uint8_t RESERVED22[3]; + __IO uint8_t BKR17; + uint8_t RESERVED23[3]; + __IO uint8_t BKR18; + uint8_t RESERVED24[3]; + __IO uint8_t BKR19; + uint8_t RESERVED25[3]; + __IO uint8_t BKR20; + uint8_t RESERVED26[3]; + __IO uint8_t BKR21; + uint8_t RESERVED27[3]; + __IO uint8_t BKR22; + uint8_t RESERVED28[3]; + __IO uint8_t BKR23; + uint8_t RESERVED29[3]; + __IO uint8_t BKR24; + uint8_t RESERVED30[3]; + __IO uint8_t BKR25; + uint8_t RESERVED31[3]; + __IO uint8_t BKR26; + uint8_t RESERVED32[3]; + __IO uint8_t BKR27; + uint8_t RESERVED33[3]; + __IO uint8_t BKR28; + uint8_t RESERVED34[3]; + __IO uint8_t BKR29; + uint8_t RESERVED35[3]; + __IO uint8_t BKR30; + uint8_t RESERVED36[3]; + __IO uint8_t BKR31; + uint8_t RESERVED37[3]; + __IO uint8_t BKR32; + uint8_t RESERVED38[3]; + __IO uint8_t BKR33; + uint8_t RESERVED39[3]; + __IO uint8_t BKR34; + uint8_t RESERVED40[3]; + __IO uint8_t BKR35; + uint8_t RESERVED41[3]; + __IO uint8_t BKR36; + uint8_t RESERVED42[3]; + __IO uint8_t BKR37; + uint8_t RESERVED43[3]; + __IO uint8_t BKR38; + uint8_t RESERVED44[3]; + __IO uint8_t BKR39; + uint8_t RESERVED45[3]; + __IO uint8_t BKR40; + uint8_t RESERVED46[3]; + __IO uint8_t BKR41; + uint8_t RESERVED47[3]; + __IO uint8_t BKR42; + uint8_t RESERVED48[3]; + __IO uint8_t BKR43; + uint8_t RESERVED49[3]; + __IO uint8_t BKR44; + uint8_t RESERVED50[3]; + __IO uint8_t BKR45; + uint8_t RESERVED51[3]; + __IO uint8_t BKR46; + uint8_t RESERVED52[3]; + __IO uint8_t BKR47; + uint8_t RESERVED53[3]; + __IO uint8_t BKR48; + uint8_t RESERVED54[3]; + __IO uint8_t BKR49; + uint8_t RESERVED55[3]; + __IO uint8_t BKR50; + uint8_t RESERVED56[3]; + __IO uint8_t BKR51; + uint8_t RESERVED57[3]; + __IO uint8_t BKR52; + uint8_t RESERVED58[3]; + __IO uint8_t BKR53; + uint8_t RESERVED59[3]; + __IO uint8_t BKR54; + uint8_t RESERVED60[3]; + __IO uint8_t BKR55; + uint8_t RESERVED61[3]; + __IO uint8_t BKR56; + uint8_t RESERVED62[3]; + __IO uint8_t BKR57; + uint8_t RESERVED63[3]; + __IO uint8_t BKR58; + uint8_t RESERVED64[3]; + __IO uint8_t BKR59; + uint8_t RESERVED65[3]; + __IO uint8_t BKR60; + uint8_t RESERVED66[3]; + __IO uint8_t BKR61; + uint8_t RESERVED67[3]; + __IO uint8_t BKR62; + uint8_t RESERVED68[3]; + __IO uint8_t BKR63; + uint8_t RESERVED69[3]; + __IO uint8_t BKR64; + uint8_t RESERVED70[3]; + __IO uint8_t BKR65; + uint8_t RESERVED71[3]; + __IO uint8_t BKR66; + uint8_t RESERVED72[3]; + __IO uint8_t BKR67; + uint8_t RESERVED73[3]; + __IO uint8_t BKR68; + uint8_t RESERVED74[3]; + __IO uint8_t BKR69; + uint8_t RESERVED75[3]; + __IO uint8_t BKR70; + uint8_t RESERVED76[3]; + __IO uint8_t BKR71; + uint8_t RESERVED77[3]; + __IO uint8_t BKR72; + uint8_t RESERVED78[3]; + __IO uint8_t BKR73; + uint8_t RESERVED79[3]; + __IO uint8_t BKR74; + uint8_t RESERVED80[3]; + __IO uint8_t BKR75; + uint8_t RESERVED81[3]; + __IO uint8_t BKR76; + uint8_t RESERVED82[3]; + __IO uint8_t BKR77; + uint8_t RESERVED83[3]; + __IO uint8_t BKR78; + uint8_t RESERVED84[3]; + __IO uint8_t BKR79; + uint8_t RESERVED85[3]; + __IO uint8_t BKR80; + uint8_t RESERVED86[3]; + __IO uint8_t BKR81; + uint8_t RESERVED87[3]; + __IO uint8_t BKR82; + uint8_t RESERVED88[3]; + __IO uint8_t BKR83; + uint8_t RESERVED89[3]; + __IO uint8_t BKR84; + uint8_t RESERVED90[3]; + __IO uint8_t BKR85; + uint8_t RESERVED91[3]; + __IO uint8_t BKR86; + uint8_t RESERVED92[3]; + __IO uint8_t BKR87; + uint8_t RESERVED93[3]; + __IO uint8_t BKR88; + uint8_t RESERVED94[3]; + __IO uint8_t BKR89; + uint8_t RESERVED95[3]; + __IO uint8_t BKR90; + uint8_t RESERVED96[3]; + __IO uint8_t BKR91; + uint8_t RESERVED97[3]; + __IO uint8_t BKR92; + uint8_t RESERVED98[3]; + __IO uint8_t BKR93; + uint8_t RESERVED99[3]; + __IO uint8_t BKR94; + uint8_t RESERVED100[3]; + __IO uint8_t BKR95; + uint8_t RESERVED101[3]; + __IO uint8_t BKR96; + uint8_t RESERVED102[3]; + __IO uint8_t BKR97; + uint8_t RESERVED103[3]; + __IO uint8_t BKR98; + uint8_t RESERVED104[3]; + __IO uint8_t BKR99; + uint8_t RESERVED105[3]; + __IO uint8_t BKR100; + uint8_t RESERVED106[3]; + __IO uint8_t BKR101; + uint8_t RESERVED107[3]; + __IO uint8_t BKR102; + uint8_t RESERVED108[3]; + __IO uint8_t BKR103; + uint8_t RESERVED109[3]; + __IO uint8_t BKR104; + uint8_t RESERVED110[3]; + __IO uint8_t BKR105; + uint8_t RESERVED111[3]; + __IO uint8_t BKR106; + uint8_t RESERVED112[3]; + __IO uint8_t BKR107; + uint8_t RESERVED113[3]; + __IO uint8_t BKR108; + uint8_t RESERVED114[3]; + __IO uint8_t BKR109; + uint8_t RESERVED115[3]; + __IO uint8_t BKR110; + uint8_t RESERVED116[3]; + __IO uint8_t BKR111; + uint8_t RESERVED117[3]; + __IO uint8_t BKR112; + uint8_t RESERVED118[3]; + __IO uint8_t BKR113; + uint8_t RESERVED119[3]; + __IO uint8_t BKR114; + uint8_t RESERVED120[3]; + __IO uint8_t BKR115; + uint8_t RESERVED121[3]; + __IO uint8_t BKR116; + uint8_t RESERVED122[3]; + __IO uint8_t BKR117; + uint8_t RESERVED123[3]; + __IO uint8_t BKR118; + uint8_t RESERVED124[3]; + __IO uint8_t BKR119; + uint8_t RESERVED125[3]; + __IO uint8_t BKR120; + uint8_t RESERVED126[3]; + __IO uint8_t BKR121; + uint8_t RESERVED127[3]; + __IO uint8_t BKR122; + uint8_t RESERVED128[3]; + __IO uint8_t BKR123; + uint8_t RESERVED129[3]; + __IO uint8_t BKR124; + uint8_t RESERVED130[3]; + __IO uint8_t BKR125; + uint8_t RESERVED131[3]; + __IO uint8_t BKR126; + uint8_t RESERVED132[3]; + __IO uint8_t BKR127; + uint8_t RESERVED133[1027]; + __IO uint8_t PWRC0; + uint8_t RESERVED134[3]; + __IO uint8_t PWRC1; + uint8_t RESERVED135[3]; + __IO uint8_t PWRC2; + uint8_t RESERVED136[3]; + __IO uint8_t PWRC3; + uint8_t RESERVED137[3]; + __IO uint8_t PWRC4; + uint8_t RESERVED138[3]; + __IO uint8_t PVDCR0; + uint8_t RESERVED139[3]; + __IO uint8_t PVDCR1; + uint8_t RESERVED140[3]; + __IO uint8_t PVDFCR; + uint8_t RESERVED141[3]; + __IO uint8_t PVDLCR; + uint8_t RESERVED142[7]; + __IO uint8_t PDWKE0; + uint8_t RESERVED143[3]; + __IO uint8_t PDWKE1; + uint8_t RESERVED144[3]; + __IO uint8_t PDWKE2; + uint8_t RESERVED145[3]; + __IO uint8_t PDWKES; + uint8_t RESERVED146[3]; + __IO uint8_t PDWKF0; + uint8_t RESERVED147[3]; + __IO uint8_t PDWKF1; + uint8_t RESERVED148[163]; + __IO uint32_t RAMPC0; + __IO uint32_t RAMOPM; + __IO uint32_t PRAMLPC; + uint8_t RESERVED149[4]; + __IO uint8_t PVDICR; + uint8_t RESERVED150[3]; + __IO uint8_t PVDDSR; + uint8_t RESERVED151[29463]; + __IO uint16_t STPMCR; + uint8_t RESERVED152[1008]; + __IO uint16_t FPRC; +} M4_PWC_TypeDef; + +/** + * @brief QSPI + */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t CSCR; + __IO uint32_t FCR; + __IO uint32_t SR; + __IO uint32_t DCOM; + __IO uint32_t CCMD; + __IO uint32_t XCMD; + uint8_t RESERVED0[8]; + __IO uint32_t SR2; + uint8_t RESERVED1[2012]; + __IO uint32_t EXAR; +} M4_QSPI_TypeDef; + +/** + * @brief RMU + */ +typedef struct +{ + uint8_t RESERVED0[248]; + __IO uint8_t PRSTCR0; + uint8_t RESERVED1[3]; + __IO uint32_t RSTF0; +} M4_RMU_TypeDef; + +/** + * @brief RTC + */ +typedef struct +{ + __IO uint8_t CR0; + uint8_t RESERVED0[3]; + __IO uint8_t CR1; + uint8_t RESERVED1[3]; + __IO uint8_t CR2; + uint8_t RESERVED2[3]; + __IO uint8_t CR3; + uint8_t RESERVED3[3]; + __IO uint8_t SEC; + uint8_t RESERVED4[3]; + __IO uint8_t MIN; + uint8_t RESERVED5[3]; + __IO uint8_t HOUR; + uint8_t RESERVED6[3]; + __IO uint8_t WEEK; + uint8_t RESERVED7[3]; + __IO uint8_t DAY; + uint8_t RESERVED8[3]; + __IO uint8_t MON; + uint8_t RESERVED9[3]; + __IO uint8_t YEAR; + uint8_t RESERVED10[3]; + __IO uint8_t ALMMIN; + uint8_t RESERVED11[3]; + __IO uint8_t ALMHOUR; + uint8_t RESERVED12[3]; + __IO uint8_t ALMWEEK; + uint8_t RESERVED13[3]; + __IO uint8_t ERRCRH; + uint8_t RESERVED14[3]; + __IO uint8_t ERRCRL; + uint8_t RESERVED15[3]; + __IO uint8_t TPCR0; + uint8_t RESERVED16[3]; + __IO uint8_t TPCR1; + uint8_t RESERVED17[3]; + __IO uint8_t TPSR; + uint8_t RESERVED18[3]; + __IO uint8_t SECTP; + uint8_t RESERVED19[3]; + __IO uint8_t MINTP; + uint8_t RESERVED20[3]; + __IO uint8_t HOURTP; + uint8_t RESERVED21[3]; + __IO uint8_t DAYTP; + uint8_t RESERVED22[3]; + __IO uint8_t MONTP; +} M4_RTC_TypeDef; + +/** + * @brief SDIOC + */ +typedef struct +{ + uint8_t RESERVED0[4]; + __IO uint16_t BLKSIZE; + __IO uint16_t BLKCNT; + __IO uint16_t ARG0; + __IO uint16_t ARG1; + __IO uint16_t TRANSMODE; + __IO uint16_t CMD; + __IO uint16_t RESP0; + __IO uint16_t RESP1; + __IO uint16_t RESP2; + __IO uint16_t RESP3; + __IO uint16_t RESP4; + __IO uint16_t RESP5; + __IO uint16_t RESP6; + __IO uint16_t RESP7; + __IO uint16_t BUF0; + __IO uint16_t BUF1; + __IO uint32_t PSTAT; + __IO uint8_t HOSTCON; + __IO uint8_t PWRCON; + __IO uint8_t BLKGPCON; + uint8_t RESERVED1[1]; + __IO uint16_t CLKCON; + __IO uint8_t TOUTCON; + __IO uint8_t SFTRST; + __IO uint16_t NORINTST; + __IO uint16_t ERRINTST; + __IO uint16_t NORINTSTEN; + __IO uint16_t ERRINTSTEN; + __IO uint16_t NORINTSGEN; + __IO uint16_t ERRINTSGEN; + __IO uint16_t ATCERRST; + uint8_t RESERVED2[18]; + __IO uint16_t FEA; + __IO uint16_t FEE; +} M4_SDIOC_TypeDef; + +/** + * @brief SMC + */ +typedef struct +{ + __IO uint32_t STSR; + uint8_t RESERVED0[4]; + __IO uint32_t STCR0; + __IO uint32_t STCR1; + __IO uint32_t CMDR; + __IO uint32_t TMCR; + __IO uint32_t CPCR; + uint8_t RESERVED1[4]; + __IO uint32_t RFTR; + uint8_t RESERVED2[220]; + __IO uint32_t TMSR0; + __IO uint32_t CPSR0; + uint8_t RESERVED3[24]; + __IO uint32_t TMSR1; + __IO uint32_t CPSR1; + uint8_t RESERVED4[24]; + __IO uint32_t TMSR2; + __IO uint32_t CPSR2; + uint8_t RESERVED5[24]; + __IO uint32_t TMSR3; + __IO uint32_t CPSR3; + uint8_t RESERVED6[152]; + __IO uint32_t BACR; + uint8_t RESERVED7[4]; + __IO uint32_t CSCR0; + __IO uint32_t CSCR1; +} M4_SMC_TypeDef; + +/** + * @brief SPI + */ +typedef struct +{ + __IO uint32_t DR; + __IO uint32_t CR1; + uint8_t RESERVED0[4]; + __IO uint32_t CFG1; + uint8_t RESERVED1[4]; + __IO uint32_t SR; + __IO uint32_t CFG2; +} M4_SPI_TypeDef; + +/** + * @brief SRAMC + */ +typedef struct +{ + __IO uint32_t WTCR; + __IO uint32_t WTPR; + __IO uint32_t CKCR; + __IO uint32_t CKPR; + __IO uint32_t CKSR; +} M4_SRAMC_TypeDef; + +/** + * @brief SWDT + */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} M4_SWDT_TypeDef; + +/** + * @brief TMR0 + */ +typedef struct +{ + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t STFLR; +} M4_TMR0_TypeDef; + +/** + * @brief TMR2 + */ +typedef struct +{ + __IO uint32_t CNTAR; + __IO uint32_t CNTBR; + __IO uint32_t CMPAR; + __IO uint32_t CMPBR; + __IO uint32_t BCONR; + __IO uint32_t ICONR; + __IO uint32_t PCONR; + __IO uint32_t HCONR; + __IO uint32_t STFLR; +} M4_TMR2_TypeDef; + +/** + * @brief TMR4 + */ +typedef struct +{ + uint8_t RESERVED0[2]; + __IO uint16_t OCCRUH; + uint8_t RESERVED1[2]; + __IO uint16_t OCCRUL; + uint8_t RESERVED2[2]; + __IO uint16_t OCCRVH; + uint8_t RESERVED3[2]; + __IO uint16_t OCCRVL; + uint8_t RESERVED4[2]; + __IO uint16_t OCCRWH; + uint8_t RESERVED5[2]; + __IO uint16_t OCCRWL; + __IO uint16_t OCSRU; + __IO uint16_t OCERU; + __IO uint16_t OCSRV; + __IO uint16_t OCERV; + __IO uint16_t OCSRW; + __IO uint16_t OCERW; + __IO uint16_t OCMRHUH; + uint8_t RESERVED6[2]; + __IO uint32_t OCMRLUL; + __IO uint16_t OCMRHVH; + uint8_t RESERVED7[2]; + __IO uint32_t OCMRLVL; + __IO uint16_t OCMRHWH; + uint8_t RESERVED8[2]; + __IO uint32_t OCMRLWL; + uint8_t RESERVED9[6]; + __IO uint16_t CPSR; + uint8_t RESERVED10[2]; + __IO uint16_t CNTR; + __IO uint16_t CCSR; + __IO uint16_t CVPR; + uint8_t RESERVED11[54]; + __IO uint16_t PFSRU; + __IO uint16_t PDARU; + __IO uint16_t PDBRU; + uint8_t RESERVED12[2]; + __IO uint16_t PFSRV; + __IO uint16_t PDARV; + __IO uint16_t PDBRV; + uint8_t RESERVED13[2]; + __IO uint16_t PFSRW; + __IO uint16_t PDARW; + __IO uint16_t PDBRW; + __IO uint16_t POCRU; + uint8_t RESERVED14[2]; + __IO uint16_t POCRV; + uint8_t RESERVED15[2]; + __IO uint16_t POCRW; + uint8_t RESERVED16[2]; + __IO uint16_t RCSR; + uint8_t RESERVED17[12]; + __IO uint16_t SCCRUH; + uint8_t RESERVED18[2]; + __IO uint16_t SCCRUL; + uint8_t RESERVED19[2]; + __IO uint16_t SCCRVH; + uint8_t RESERVED20[2]; + __IO uint16_t SCCRVL; + uint8_t RESERVED21[2]; + __IO uint16_t SCCRWH; + uint8_t RESERVED22[2]; + __IO uint16_t SCCRWL; + __IO uint16_t SCSRUH; + __IO uint16_t SCMRUH; + __IO uint16_t SCSRUL; + __IO uint16_t SCMRUL; + __IO uint16_t SCSRVH; + __IO uint16_t SCMRVH; + __IO uint16_t SCSRVL; + __IO uint16_t SCMRVL; + __IO uint16_t SCSRWH; + __IO uint16_t SCMRWH; + __IO uint16_t SCSRWL; + __IO uint16_t SCMRWL; + __IO uint32_t PSCR; + __IO uint16_t SCER; +} M4_TMR4_TypeDef; + +/** + * @brief TMR6 + */ +typedef struct +{ + __IO uint32_t CNTER; + __IO uint32_t UPDAR; + uint8_t RESERVED0[56]; + __IO uint32_t PERAR; + __IO uint32_t PERBR; + __IO uint32_t PERCR; + uint8_t RESERVED1[52]; + __IO uint32_t GCMAR; + __IO uint32_t GCMBR; + __IO uint32_t GCMCR; + __IO uint32_t GCMDR; + __IO uint32_t GCMER; + __IO uint32_t GCMFR; + uint8_t RESERVED2[40]; + __IO uint32_t SCMAR; + __IO uint32_t SCMBR; + __IO uint32_t SCMCR; + __IO uint32_t SCMDR; + __IO uint32_t SCMER; + __IO uint32_t SCMFR; + uint8_t RESERVED3[40]; + __IO uint32_t DTUAR; + __IO uint32_t DTDAR; + __IO uint32_t DTUBR; + __IO uint32_t DTDBR; + uint8_t RESERVED4[48]; + __IO uint32_t GCONR; + __IO uint32_t ICONR; + __IO uint32_t BCONR; + __IO uint32_t DCONR; + uint8_t RESERVED5[4]; + __IO uint32_t PCNAR; + __IO uint32_t PCNBR; + __IO uint32_t FCNGR; + __IO uint32_t VPERR; + __IO uint32_t STFLR; + uint8_t RESERVED6[24]; + __IO uint32_t HSTAR; + __IO uint32_t HSTPR; + __IO uint32_t HCLRR; + __IO uint32_t HUPDR; + __IO uint32_t HCPAR; + __IO uint32_t HCPBR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; + uint8_t RESERVED7[588]; + __IO uint32_t FCNTR; + __IO uint32_t SSTAR; + __IO uint32_t SSTPR; + __IO uint32_t SCLRR; + __IO uint32_t SUPDR; +} M4_TMR6_TypeDef; + +/** + * @brief TMRA + */ +typedef struct +{ + __IO uint32_t CNTER; + __IO uint32_t PERAR; + uint8_t RESERVED0[56]; + __IO uint32_t CMPAR1; + __IO uint32_t CMPAR2; + __IO uint32_t CMPAR3; + __IO uint32_t CMPAR4; + uint8_t RESERVED1[48]; + __IO uint32_t BCSTR; + __IO uint32_t HCONR; + __IO uint32_t HCUPR; + __IO uint32_t HCDOR; + __IO uint32_t ICONR; + __IO uint32_t ECONR; + __IO uint32_t FCONR; + __IO uint32_t STFLR; + uint8_t RESERVED2[32]; + __IO uint32_t BCONR1; + uint8_t RESERVED3[4]; + __IO uint32_t BCONR2; + uint8_t RESERVED4[52]; + __IO uint32_t CCONR1; + __IO uint32_t CCONR2; + __IO uint32_t CCONR3; + __IO uint32_t CCONR4; + uint8_t RESERVED5[48]; + __IO uint32_t PCONR1; + __IO uint32_t PCONR2; + __IO uint32_t PCONR3; + __IO uint32_t PCONR4; +} M4_TMRA_TypeDef; + +/** + * @brief TRNG + */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t MR; + uint8_t RESERVED0[4]; + __IO uint32_t DR0; + __IO uint32_t DR1; +} M4_TRNG_TypeDef; + +/** + * @brief USART + */ +typedef struct +{ + __IO uint32_t SR; + __IO uint32_t DR; + __IO uint32_t BRR; + __IO uint32_t CR1; + __IO uint32_t CR2; + __IO uint32_t CR3; + __IO uint32_t PR; + __IO uint32_t LBMC; +} M4_USART_TypeDef; + +/** + * @brief USBFS + */ +typedef struct +{ + __IO uint32_t GOTGCTL; + __IO uint32_t GOTGINT; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __IO uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __IO uint32_t GRXSTSR; + __IO uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t GNPTXFSIZ; + __IO uint32_t GNPTXSTS; + uint8_t RESERVED0[12]; + __IO uint32_t GUID; + uint8_t RESERVED1[20]; + __IO uint32_t GLPMCFG; + uint8_t RESERVED2[4]; + __IO uint32_t GDFIFOCFG; + uint8_t RESERVED3[160]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + __IO uint32_t DIEPTXF6; + __IO uint32_t DIEPTXF7; + __IO uint32_t DIEPTXF8; + __IO uint32_t DIEPTXF9; + __IO uint32_t DIEPTXF10; + __IO uint32_t DIEPTXF11; + __IO uint32_t DIEPTXF12; + __IO uint32_t DIEPTXF13; + __IO uint32_t DIEPTXF14; + __IO uint32_t DIEPTXF15; + uint8_t RESERVED4[704]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __IO uint32_t HFNUM; + uint8_t RESERVED5[4]; + __IO uint32_t HPTXSTS; + __IO uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED6[36]; + __IO uint32_t HPRT; + uint8_t RESERVED7[188]; + __IO uint32_t HCCHAR0; + __IO uint32_t HCSPLT0; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED8[8]; + __IO uint32_t HCCHAR1; + __IO uint32_t HCSPLT1; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED9[8]; + __IO uint32_t HCCHAR2; + __IO uint32_t HCSPLT2; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED10[8]; + __IO uint32_t HCCHAR3; + __IO uint32_t HCSPLT3; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED11[8]; + __IO uint32_t HCCHAR4; + __IO uint32_t HCSPLT4; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED12[8]; + __IO uint32_t HCCHAR5; + __IO uint32_t HCSPLT5; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED13[8]; + __IO uint32_t HCCHAR6; + __IO uint32_t HCSPLT6; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED14[8]; + __IO uint32_t HCCHAR7; + __IO uint32_t HCSPLT7; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED15[8]; + __IO uint32_t HCCHAR8; + __IO uint32_t HCSPLT8; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED16[8]; + __IO uint32_t HCCHAR9; + __IO uint32_t HCSPLT9; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED17[8]; + __IO uint32_t HCCHAR10; + __IO uint32_t HCSPLT10; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED18[8]; + __IO uint32_t HCCHAR11; + __IO uint32_t HCSPLT11; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED19[8]; + __IO uint32_t HCCHAR12; + __IO uint32_t HCSPLT12; + __IO uint32_t HCINT12; + __IO uint32_t HCINTMSK12; + __IO uint32_t HCTSIZ12; + __IO uint32_t HCDMA12; + uint8_t RESERVED20[8]; + __IO uint32_t HCCHAR13; + __IO uint32_t HCSPLT13; + __IO uint32_t HCINT13; + __IO uint32_t HCINTMSK13; + __IO uint32_t HCTSIZ13; + __IO uint32_t HCDMA13; + uint8_t RESERVED21[8]; + __IO uint32_t HCCHAR14; + __IO uint32_t HCSPLT14; + __IO uint32_t HCINT14; + __IO uint32_t HCINTMSK14; + __IO uint32_t HCTSIZ14; + __IO uint32_t HCDMA14; + uint8_t RESERVED22[8]; + __IO uint32_t HCCHAR15; + __IO uint32_t HCSPLT15; + __IO uint32_t HCINT15; + __IO uint32_t HCINTMSK15; + __IO uint32_t HCTSIZ15; + __IO uint32_t HCDMA15; + uint8_t RESERVED23[264]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __IO uint32_t DSTS; + uint8_t RESERVED24[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED25[20]; + __IO uint32_t DIEPEMPMSK; + uint8_t RESERVED26[200]; + __IO uint32_t DIEPCTL0; + uint8_t RESERVED27[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED28[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __IO uint32_t DTXFSTS0; + uint8_t RESERVED29[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED30[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED31[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __IO uint32_t DTXFSTS1; + uint8_t RESERVED32[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED33[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED34[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __IO uint32_t DTXFSTS2; + uint8_t RESERVED35[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED36[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED37[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __IO uint32_t DTXFSTS3; + uint8_t RESERVED38[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED39[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __IO uint32_t DTXFSTS4; + uint8_t RESERVED41[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED42[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __IO uint32_t DTXFSTS5; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPCTL6; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPINT6; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPTSIZ6; + __IO uint32_t DIEPDMA6; + __IO uint32_t DTXFSTS6; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPCTL7; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPINT7; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPTSIZ7; + __IO uint32_t DIEPDMA7; + __IO uint32_t DTXFSTS7; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPCTL8; + uint8_t RESERVED51[4]; + __IO uint32_t DIEPINT8; + uint8_t RESERVED52[4]; + __IO uint32_t DIEPTSIZ8; + __IO uint32_t DIEPDMA8; + __IO uint32_t DTXFSTS8; + uint8_t RESERVED53[4]; + __IO uint32_t DIEPCTL9; + uint8_t RESERVED54[4]; + __IO uint32_t DIEPINT9; + uint8_t RESERVED55[4]; + __IO uint32_t DIEPTSIZ9; + __IO uint32_t DIEPDMA9; + __IO uint32_t DTXFSTS9; + uint8_t RESERVED56[4]; + __IO uint32_t DIEPCTL10; + uint8_t RESERVED57[4]; + __IO uint32_t DIEPINT10; + uint8_t RESERVED58[4]; + __IO uint32_t DIEPTSIZ10; + __IO uint32_t DIEPDMA10; + __IO uint32_t DTXFSTS10; + uint8_t RESERVED59[4]; + __IO uint32_t DIEPCTL11; + uint8_t RESERVED60[4]; + __IO uint32_t DIEPINT11; + uint8_t RESERVED61[4]; + __IO uint32_t DIEPTSIZ11; + __IO uint32_t DIEPDMA11; + __IO uint32_t DTXFSTS11; + uint8_t RESERVED62[4]; + __IO uint32_t DIEPCTL12; + uint8_t RESERVED63[4]; + __IO uint32_t DIEPINT12; + uint8_t RESERVED64[4]; + __IO uint32_t DIEPTSIZ12; + __IO uint32_t DIEPDMA12; + __IO uint32_t DTXFSTS12; + uint8_t RESERVED65[4]; + __IO uint32_t DIEPCTL13; + uint8_t RESERVED66[4]; + __IO uint32_t DIEPINT13; + uint8_t RESERVED67[4]; + __IO uint32_t DIEPTSIZ13; + __IO uint32_t DIEPDMA13; + __IO uint32_t DTXFSTS13; + uint8_t RESERVED68[4]; + __IO uint32_t DIEPCTL14; + uint8_t RESERVED69[4]; + __IO uint32_t DIEPINT14; + uint8_t RESERVED70[4]; + __IO uint32_t DIEPTSIZ14; + __IO uint32_t DIEPDMA14; + __IO uint32_t DTXFSTS14; + uint8_t RESERVED71[4]; + __IO uint32_t DIEPCTL15; + uint8_t RESERVED72[4]; + __IO uint32_t DIEPINT15; + uint8_t RESERVED73[4]; + __IO uint32_t DIEPTSIZ15; + __IO uint32_t DIEPDMA15; + __IO uint32_t DTXFSTS15; + uint8_t RESERVED74[4]; + __IO uint32_t DOEPCTL0; + uint8_t RESERVED75[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED76[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED77[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED78[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED79[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED80[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED81[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED82[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED83[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED84[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED85[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED86[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED87[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED88[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED89[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED90[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED91[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED92[8]; + __IO uint32_t DOEPCTL6; + uint8_t RESERVED93[4]; + __IO uint32_t DOEPINT6; + uint8_t RESERVED94[4]; + __IO uint32_t DOEPTSIZ6; + __IO uint32_t DOEPDMA6; + uint8_t RESERVED95[8]; + __IO uint32_t DOEPCTL7; + uint8_t RESERVED96[4]; + __IO uint32_t DOEPINT7; + uint8_t RESERVED97[4]; + __IO uint32_t DOEPTSIZ7; + __IO uint32_t DOEPDMA7; + uint8_t RESERVED98[8]; + __IO uint32_t DOEPCTL8; + uint8_t RESERVED99[4]; + __IO uint32_t DOEPINT8; + uint8_t RESERVED100[4]; + __IO uint32_t DOEPTSIZ8; + __IO uint32_t DOEPDMA8; + uint8_t RESERVED101[8]; + __IO uint32_t DOEPCTL9; + uint8_t RESERVED102[4]; + __IO uint32_t DOEPINT9; + uint8_t RESERVED103[4]; + __IO uint32_t DOEPTSIZ9; + __IO uint32_t DOEPDMA9; + uint8_t RESERVED104[8]; + __IO uint32_t DOEPCTL10; + uint8_t RESERVED105[4]; + __IO uint32_t DOEPINT10; + uint8_t RESERVED106[4]; + __IO uint32_t DOEPTSIZ10; + __IO uint32_t DOEPDMA10; + uint8_t RESERVED107[8]; + __IO uint32_t DOEPCTL11; + uint8_t RESERVED108[4]; + __IO uint32_t DOEPINT11; + uint8_t RESERVED109[4]; + __IO uint32_t DOEPTSIZ11; + __IO uint32_t DOEPDMA11; + uint8_t RESERVED110[8]; + __IO uint32_t DOEPCTL12; + uint8_t RESERVED111[4]; + __IO uint32_t DOEPINT12; + uint8_t RESERVED112[4]; + __IO uint32_t DOEPTSIZ12; + __IO uint32_t DOEPDMA12; + uint8_t RESERVED113[8]; + __IO uint32_t DOEPCTL13; + uint8_t RESERVED114[4]; + __IO uint32_t DOEPINT13; + uint8_t RESERVED115[4]; + __IO uint32_t DOEPTSIZ13; + __IO uint32_t DOEPDMA13; + uint8_t RESERVED116[8]; + __IO uint32_t DOEPCTL14; + uint8_t RESERVED117[4]; + __IO uint32_t DOEPINT14; + uint8_t RESERVED118[4]; + __IO uint32_t DOEPTSIZ14; + __IO uint32_t DOEPDMA14; + uint8_t RESERVED119[8]; + __IO uint32_t DOEPCTL15; + uint8_t RESERVED120[4]; + __IO uint32_t DOEPINT15; + uint8_t RESERVED121[4]; + __IO uint32_t DOEPTSIZ15; + __IO uint32_t DOEPDMA15; + uint8_t RESERVED122[264]; + __IO uint32_t PCGCCTL; +} M4_USBFS_TypeDef; + +/** + * @brief USBHS + */ +typedef struct +{ + __IO uint32_t GOTGCTL; + __IO uint32_t GOTGINT; + __IO uint32_t GAHBCFG; + __IO uint32_t GUSBCFG; + __IO uint32_t GRSTCTL; + __IO uint32_t GINTSTS; + __IO uint32_t GINTMSK; + __IO uint32_t GRXSTSR; + __IO uint32_t GRXSTSP; + __IO uint32_t GRXFSIZ; + __IO uint32_t GNPTXFSIZ; + __IO uint32_t GNPTXSTS; + uint8_t RESERVED0[4]; + __IO uint32_t GPVNDCTL; + uint8_t RESERVED1[4]; + __IO uint32_t GUID; + uint8_t RESERVED2[20]; + __IO uint32_t GLPMCFG; + uint8_t RESERVED3[4]; + __IO uint32_t GDFIFOCFG; + uint8_t RESERVED4[160]; + __IO uint32_t HPTXFSIZ; + __IO uint32_t DIEPTXF1; + __IO uint32_t DIEPTXF2; + __IO uint32_t DIEPTXF3; + __IO uint32_t DIEPTXF4; + __IO uint32_t DIEPTXF5; + __IO uint32_t DIEPTXF6; + __IO uint32_t DIEPTXF7; + __IO uint32_t DIEPTXF8; + __IO uint32_t DIEPTXF9; + __IO uint32_t DIEPTXF10; + __IO uint32_t DIEPTXF11; + __IO uint32_t DIEPTXF12; + __IO uint32_t DIEPTXF13; + __IO uint32_t DIEPTXF14; + __IO uint32_t DIEPTXF15; + uint8_t RESERVED5[704]; + __IO uint32_t HCFG; + __IO uint32_t HFIR; + __IO uint32_t HFNUM; + uint8_t RESERVED6[4]; + __IO uint32_t HPTXSTS; + __IO uint32_t HAINT; + __IO uint32_t HAINTMSK; + uint8_t RESERVED7[36]; + __IO uint32_t HPRT; + uint8_t RESERVED8[188]; + __IO uint32_t HCCHAR0; + __IO uint32_t HCSPLT0; + __IO uint32_t HCINT0; + __IO uint32_t HCINTMSK0; + __IO uint32_t HCTSIZ0; + __IO uint32_t HCDMA0; + uint8_t RESERVED9[8]; + __IO uint32_t HCCHAR1; + __IO uint32_t HCSPLT1; + __IO uint32_t HCINT1; + __IO uint32_t HCINTMSK1; + __IO uint32_t HCTSIZ1; + __IO uint32_t HCDMA1; + uint8_t RESERVED10[8]; + __IO uint32_t HCCHAR2; + __IO uint32_t HCSPLT2; + __IO uint32_t HCINT2; + __IO uint32_t HCINTMSK2; + __IO uint32_t HCTSIZ2; + __IO uint32_t HCDMA2; + uint8_t RESERVED11[8]; + __IO uint32_t HCCHAR3; + __IO uint32_t HCSPLT3; + __IO uint32_t HCINT3; + __IO uint32_t HCINTMSK3; + __IO uint32_t HCTSIZ3; + __IO uint32_t HCDMA3; + uint8_t RESERVED12[8]; + __IO uint32_t HCCHAR4; + __IO uint32_t HCSPLT4; + __IO uint32_t HCINT4; + __IO uint32_t HCINTMSK4; + __IO uint32_t HCTSIZ4; + __IO uint32_t HCDMA4; + uint8_t RESERVED13[8]; + __IO uint32_t HCCHAR5; + __IO uint32_t HCSPLT5; + __IO uint32_t HCINT5; + __IO uint32_t HCINTMSK5; + __IO uint32_t HCTSIZ5; + __IO uint32_t HCDMA5; + uint8_t RESERVED14[8]; + __IO uint32_t HCCHAR6; + __IO uint32_t HCSPLT6; + __IO uint32_t HCINT6; + __IO uint32_t HCINTMSK6; + __IO uint32_t HCTSIZ6; + __IO uint32_t HCDMA6; + uint8_t RESERVED15[8]; + __IO uint32_t HCCHAR7; + __IO uint32_t HCSPLT7; + __IO uint32_t HCINT7; + __IO uint32_t HCINTMSK7; + __IO uint32_t HCTSIZ7; + __IO uint32_t HCDMA7; + uint8_t RESERVED16[8]; + __IO uint32_t HCCHAR8; + __IO uint32_t HCSPLT8; + __IO uint32_t HCINT8; + __IO uint32_t HCINTMSK8; + __IO uint32_t HCTSIZ8; + __IO uint32_t HCDMA8; + uint8_t RESERVED17[8]; + __IO uint32_t HCCHAR9; + __IO uint32_t HCSPLT9; + __IO uint32_t HCINT9; + __IO uint32_t HCINTMSK9; + __IO uint32_t HCTSIZ9; + __IO uint32_t HCDMA9; + uint8_t RESERVED18[8]; + __IO uint32_t HCCHAR10; + __IO uint32_t HCSPLT10; + __IO uint32_t HCINT10; + __IO uint32_t HCINTMSK10; + __IO uint32_t HCTSIZ10; + __IO uint32_t HCDMA10; + uint8_t RESERVED19[8]; + __IO uint32_t HCCHAR11; + __IO uint32_t HCSPLT11; + __IO uint32_t HCINT11; + __IO uint32_t HCINTMSK11; + __IO uint32_t HCTSIZ11; + __IO uint32_t HCDMA11; + uint8_t RESERVED20[8]; + __IO uint32_t HCCHAR12; + __IO uint32_t HCSPLT12; + __IO uint32_t HCINT12; + __IO uint32_t HCINTMSK12; + __IO uint32_t HCTSIZ12; + __IO uint32_t HCDMA12; + uint8_t RESERVED21[8]; + __IO uint32_t HCCHAR13; + __IO uint32_t HCSPLT13; + __IO uint32_t HCINT13; + __IO uint32_t HCINTMSK13; + __IO uint32_t HCTSIZ13; + __IO uint32_t HCDMA13; + uint8_t RESERVED22[8]; + __IO uint32_t HCCHAR14; + __IO uint32_t HCSPLT14; + __IO uint32_t HCINT14; + __IO uint32_t HCINTMSK14; + __IO uint32_t HCTSIZ14; + __IO uint32_t HCDMA14; + uint8_t RESERVED23[8]; + __IO uint32_t HCCHAR15; + __IO uint32_t HCSPLT15; + __IO uint32_t HCINT15; + __IO uint32_t HCINTMSK15; + __IO uint32_t HCTSIZ15; + __IO uint32_t HCDMA15; + uint8_t RESERVED24[264]; + __IO uint32_t DCFG; + __IO uint32_t DCTL; + __IO uint32_t DSTS; + uint8_t RESERVED25[4]; + __IO uint32_t DIEPMSK; + __IO uint32_t DOEPMSK; + __IO uint32_t DAINT; + __IO uint32_t DAINTMSK; + uint8_t RESERVED26[16]; + __IO uint32_t DTHRCTL; + __IO uint32_t DIEPEMPMSK; + __IO uint32_t DEACHINT; + __IO uint32_t DEACHINTMSK; + uint8_t RESERVED27[4]; + __IO uint32_t DIEPEACHMSK1; + uint8_t RESERVED28[60]; + __IO uint32_t DOEPEACHMSK1; + uint8_t RESERVED29[120]; + __IO uint32_t DIEPCTL0; + uint8_t RESERVED30[4]; + __IO uint32_t DIEPINT0; + uint8_t RESERVED31[4]; + __IO uint32_t DIEPTSIZ0; + __IO uint32_t DIEPDMA0; + __IO uint32_t DTXFSTS0; + uint8_t RESERVED32[4]; + __IO uint32_t DIEPCTL1; + uint8_t RESERVED33[4]; + __IO uint32_t DIEPINT1; + uint8_t RESERVED34[4]; + __IO uint32_t DIEPTSIZ1; + __IO uint32_t DIEPDMA1; + __IO uint32_t DTXFSTS1; + uint8_t RESERVED35[4]; + __IO uint32_t DIEPCTL2; + uint8_t RESERVED36[4]; + __IO uint32_t DIEPINT2; + uint8_t RESERVED37[4]; + __IO uint32_t DIEPTSIZ2; + __IO uint32_t DIEPDMA2; + __IO uint32_t DTXFSTS2; + uint8_t RESERVED38[4]; + __IO uint32_t DIEPCTL3; + uint8_t RESERVED39[4]; + __IO uint32_t DIEPINT3; + uint8_t RESERVED40[4]; + __IO uint32_t DIEPTSIZ3; + __IO uint32_t DIEPDMA3; + __IO uint32_t DTXFSTS3; + uint8_t RESERVED41[4]; + __IO uint32_t DIEPCTL4; + uint8_t RESERVED42[4]; + __IO uint32_t DIEPINT4; + uint8_t RESERVED43[4]; + __IO uint32_t DIEPTSIZ4; + __IO uint32_t DIEPDMA4; + __IO uint32_t DTXFSTS4; + uint8_t RESERVED44[4]; + __IO uint32_t DIEPCTL5; + uint8_t RESERVED45[4]; + __IO uint32_t DIEPINT5; + uint8_t RESERVED46[4]; + __IO uint32_t DIEPTSIZ5; + __IO uint32_t DIEPDMA5; + __IO uint32_t DTXFSTS5; + uint8_t RESERVED47[4]; + __IO uint32_t DIEPCTL6; + uint8_t RESERVED48[4]; + __IO uint32_t DIEPINT6; + uint8_t RESERVED49[4]; + __IO uint32_t DIEPTSIZ6; + __IO uint32_t DIEPDMA6; + __IO uint32_t DTXFSTS6; + uint8_t RESERVED50[4]; + __IO uint32_t DIEPCTL7; + uint8_t RESERVED51[4]; + __IO uint32_t DIEPINT7; + uint8_t RESERVED52[4]; + __IO uint32_t DIEPTSIZ7; + __IO uint32_t DIEPDMA7; + __IO uint32_t DTXFSTS7; + uint8_t RESERVED53[4]; + __IO uint32_t DIEPCTL8; + uint8_t RESERVED54[4]; + __IO uint32_t DIEPINT8; + uint8_t RESERVED55[4]; + __IO uint32_t DIEPTSIZ8; + __IO uint32_t DIEPDMA8; + __IO uint32_t DTXFSTS8; + uint8_t RESERVED56[4]; + __IO uint32_t DIEPCTL9; + uint8_t RESERVED57[4]; + __IO uint32_t DIEPINT9; + uint8_t RESERVED58[4]; + __IO uint32_t DIEPTSIZ9; + __IO uint32_t DIEPDMA9; + __IO uint32_t DTXFSTS9; + uint8_t RESERVED59[4]; + __IO uint32_t DIEPCTL10; + uint8_t RESERVED60[4]; + __IO uint32_t DIEPINT10; + uint8_t RESERVED61[4]; + __IO uint32_t DIEPTSIZ10; + __IO uint32_t DIEPDMA10; + __IO uint32_t DTXFSTS10; + uint8_t RESERVED62[4]; + __IO uint32_t DIEPCTL11; + uint8_t RESERVED63[4]; + __IO uint32_t DIEPINT11; + uint8_t RESERVED64[4]; + __IO uint32_t DIEPTSIZ11; + __IO uint32_t DIEPDMA11; + __IO uint32_t DTXFSTS11; + uint8_t RESERVED65[4]; + __IO uint32_t DIEPCTL12; + uint8_t RESERVED66[4]; + __IO uint32_t DIEPINT12; + uint8_t RESERVED67[4]; + __IO uint32_t DIEPTSIZ12; + __IO uint32_t DIEPDMA12; + __IO uint32_t DTXFSTS12; + uint8_t RESERVED68[4]; + __IO uint32_t DIEPCTL13; + uint8_t RESERVED69[4]; + __IO uint32_t DIEPINT13; + uint8_t RESERVED70[4]; + __IO uint32_t DIEPTSIZ13; + __IO uint32_t DIEPDMA13; + __IO uint32_t DTXFSTS13; + uint8_t RESERVED71[4]; + __IO uint32_t DIEPCTL14; + uint8_t RESERVED72[4]; + __IO uint32_t DIEPINT14; + uint8_t RESERVED73[4]; + __IO uint32_t DIEPTSIZ14; + __IO uint32_t DIEPDMA14; + __IO uint32_t DTXFSTS14; + uint8_t RESERVED74[4]; + __IO uint32_t DIEPCTL15; + uint8_t RESERVED75[4]; + __IO uint32_t DIEPINT15; + uint8_t RESERVED76[4]; + __IO uint32_t DIEPTSIZ15; + __IO uint32_t DIEPDMA15; + __IO uint32_t DTXFSTS15; + uint8_t RESERVED77[4]; + __IO uint32_t DOEPCTL0; + uint8_t RESERVED78[4]; + __IO uint32_t DOEPINT0; + uint8_t RESERVED79[4]; + __IO uint32_t DOEPTSIZ0; + __IO uint32_t DOEPDMA0; + uint8_t RESERVED80[8]; + __IO uint32_t DOEPCTL1; + uint8_t RESERVED81[4]; + __IO uint32_t DOEPINT1; + uint8_t RESERVED82[4]; + __IO uint32_t DOEPTSIZ1; + __IO uint32_t DOEPDMA1; + uint8_t RESERVED83[8]; + __IO uint32_t DOEPCTL2; + uint8_t RESERVED84[4]; + __IO uint32_t DOEPINT2; + uint8_t RESERVED85[4]; + __IO uint32_t DOEPTSIZ2; + __IO uint32_t DOEPDMA2; + uint8_t RESERVED86[8]; + __IO uint32_t DOEPCTL3; + uint8_t RESERVED87[4]; + __IO uint32_t DOEPINT3; + uint8_t RESERVED88[4]; + __IO uint32_t DOEPTSIZ3; + __IO uint32_t DOEPDMA3; + uint8_t RESERVED89[8]; + __IO uint32_t DOEPCTL4; + uint8_t RESERVED90[4]; + __IO uint32_t DOEPINT4; + uint8_t RESERVED91[4]; + __IO uint32_t DOEPTSIZ4; + __IO uint32_t DOEPDMA4; + uint8_t RESERVED92[8]; + __IO uint32_t DOEPCTL5; + uint8_t RESERVED93[4]; + __IO uint32_t DOEPINT5; + uint8_t RESERVED94[4]; + __IO uint32_t DOEPTSIZ5; + __IO uint32_t DOEPDMA5; + uint8_t RESERVED95[8]; + __IO uint32_t DOEPCTL6; + uint8_t RESERVED96[4]; + __IO uint32_t DOEPINT6; + uint8_t RESERVED97[4]; + __IO uint32_t DOEPTSIZ6; + __IO uint32_t DOEPDMA6; + uint8_t RESERVED98[8]; + __IO uint32_t DOEPCTL7; + uint8_t RESERVED99[4]; + __IO uint32_t DOEPINT7; + uint8_t RESERVED100[4]; + __IO uint32_t DOEPTSIZ7; + __IO uint32_t DOEPDMA7; + uint8_t RESERVED101[8]; + __IO uint32_t DOEPCTL8; + uint8_t RESERVED102[4]; + __IO uint32_t DOEPINT8; + uint8_t RESERVED103[4]; + __IO uint32_t DOEPTSIZ8; + __IO uint32_t DOEPDMA8; + uint8_t RESERVED104[8]; + __IO uint32_t DOEPCTL9; + uint8_t RESERVED105[4]; + __IO uint32_t DOEPINT9; + uint8_t RESERVED106[4]; + __IO uint32_t DOEPTSIZ9; + __IO uint32_t DOEPDMA9; + uint8_t RESERVED107[8]; + __IO uint32_t DOEPCTL10; + uint8_t RESERVED108[4]; + __IO uint32_t DOEPINT10; + uint8_t RESERVED109[4]; + __IO uint32_t DOEPTSIZ10; + __IO uint32_t DOEPDMA10; + uint8_t RESERVED110[8]; + __IO uint32_t DOEPCTL11; + uint8_t RESERVED111[4]; + __IO uint32_t DOEPINT11; + uint8_t RESERVED112[4]; + __IO uint32_t DOEPTSIZ11; + __IO uint32_t DOEPDMA11; + uint8_t RESERVED113[8]; + __IO uint32_t DOEPCTL12; + uint8_t RESERVED114[4]; + __IO uint32_t DOEPINT12; + uint8_t RESERVED115[4]; + __IO uint32_t DOEPTSIZ12; + __IO uint32_t DOEPDMA12; + uint8_t RESERVED116[8]; + __IO uint32_t DOEPCTL13; + uint8_t RESERVED117[4]; + __IO uint32_t DOEPINT13; + uint8_t RESERVED118[4]; + __IO uint32_t DOEPTSIZ13; + __IO uint32_t DOEPDMA13; + uint8_t RESERVED119[8]; + __IO uint32_t DOEPCTL14; + uint8_t RESERVED120[4]; + __IO uint32_t DOEPINT14; + uint8_t RESERVED121[4]; + __IO uint32_t DOEPTSIZ14; + __IO uint32_t DOEPDMA14; + uint8_t RESERVED122[8]; + __IO uint32_t DOEPCTL15; + uint8_t RESERVED123[4]; + __IO uint32_t DOEPINT15; + uint8_t RESERVED124[4]; + __IO uint32_t DOEPTSIZ15; + __IO uint32_t DOEPDMA15; + uint8_t RESERVED125[264]; + __IO uint32_t PCGCCTL; +} M4_USBHS_TypeDef; + +/** + * @brief WDT + */ +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t SR; + __IO uint32_t RR; +} M4_WDT_TypeDef; + + + +/******************************************************************************/ +/* Device Specific Peripheral declaration & memory map */ +/******************************************************************************/ + +#define M4_ADC1 ((M4_ADC_TypeDef *)0x40040000UL) +#define M4_ADC2 ((M4_ADC_TypeDef *)0x40040400UL) +#define M4_ADC3 ((M4_ADC_TypeDef *)0x40040800UL) +#define M4_AES ((M4_AES_TypeDef *)0x40008000UL) +#define M4_AOS ((M4_AOS_TypeDef *)0x40010800UL) +#define M4_CAN1 ((M4_CAN_TypeDef *)0x40009000UL) +#define M4_CAN2 ((M4_CAN_TypeDef *)0x40078000UL) +#define M4_CMP1 ((M4_CMP_TypeDef *)0x4004A000UL) +#define M4_CMP2 ((M4_CMP_TypeDef *)0x4004A010UL) +#define M4_CMP3 ((M4_CMP_TypeDef *)0x4004A400UL) +#define M4_CMP4 ((M4_CMP_TypeDef *)0x4004A410UL) +#define M4_CMU ((M4_CMU_TypeDef *)0x4004C400UL) +#define M4_CRC ((M4_CRC_TypeDef *)0x40008C00UL) +#define M4_CTC ((M4_CTC_TypeDef *)0x40049C00UL) +#define M4_DAC1 ((M4_DAC_TypeDef *)0x40041000UL) +#define M4_DAC2 ((M4_DAC_TypeDef *)0x40041400UL) +#define M4_DBGC ((M4_DBGC_TypeDef *)0xE0042000UL) +#define M4_DCU1 ((M4_DCU_TypeDef *)0x40056000UL) +#define M4_DCU2 ((M4_DCU_TypeDef *)0x40056400UL) +#define M4_DCU3 ((M4_DCU_TypeDef *)0x40056800UL) +#define M4_DCU4 ((M4_DCU_TypeDef *)0x40056C00UL) +#define M4_DCU5 ((M4_DCU_TypeDef *)0x40057000UL) +#define M4_DCU6 ((M4_DCU_TypeDef *)0x40057400UL) +#define M4_DCU7 ((M4_DCU_TypeDef *)0x40057800UL) +#define M4_DCU8 ((M4_DCU_TypeDef *)0x40057C00UL) +#define M4_DMA1 ((M4_DMA_TypeDef *)0x40053000UL) +#define M4_DMA2 ((M4_DMA_TypeDef *)0x40053400UL) +#define M4_DMC ((M4_DMC_TypeDef *)0x88000400UL) +#define M4_DVP ((M4_DVP_TypeDef *)0x40055800UL) +#define M4_EFM ((M4_EFM_TypeDef *)0x40010400UL) +#define M4_EMB0 ((M4_EMB_TypeDef *)0x40017C00UL) +#define M4_EMB1 ((M4_EMB_TypeDef *)0x40017C20UL) +#define M4_EMB2 ((M4_EMB_TypeDef *)0x40017C40UL) +#define M4_EMB3 ((M4_EMB_TypeDef *)0x40017C60UL) +#define M4_EMB4 ((M4_EMB_TypeDef *)0x40017C80UL) +#define M4_EMB5 ((M4_EMB_TypeDef *)0x40017CA0UL) +#define M4_EMB6 ((M4_EMB_TypeDef *)0x40017CC0UL) +#define M4_ETH ((M4_ETH_TypeDef *)0x40050000UL) +#define M4_FCM ((M4_FCM_TypeDef *)0x40048400UL) +#define M4_FMAC1 ((M4_FMAC_TypeDef *)0x40058000UL) +#define M4_FMAC2 ((M4_FMAC_TypeDef *)0x40058400UL) +#define M4_FMAC3 ((M4_FMAC_TypeDef *)0x40058800UL) +#define M4_FMAC4 ((M4_FMAC_TypeDef *)0x40058C00UL) +#define M4_GPIO ((M4_GPIO_TypeDef *)0x40053800UL) +#define M4_HASH ((M4_HASH_TypeDef *)0x40008400UL) +#define M4_HRPWM ((M4_HRPWM_TypeDef *)0x4003C000UL) +#define M4_I2C1 ((M4_I2C_TypeDef *)0x4004E000UL) +#define M4_I2C2 ((M4_I2C_TypeDef *)0x4004E400UL) +#define M4_I2C3 ((M4_I2C_TypeDef *)0x4004E800UL) +#define M4_I2C4 ((M4_I2C_TypeDef *)0x4004EC00UL) +#define M4_I2C5 ((M4_I2C_TypeDef *)0x4004F000UL) +#define M4_I2C6 ((M4_I2C_TypeDef *)0x4004F800UL) +#define M4_I2S1 ((M4_I2S_TypeDef *)0x4001E000UL) +#define M4_I2S2 ((M4_I2S_TypeDef *)0x4001E400UL) +#define M4_I2S3 ((M4_I2S_TypeDef *)0x40022000UL) +#define M4_I2S4 ((M4_I2S_TypeDef *)0x40022400UL) +#define M4_ICG ((M4_ICG_TypeDef *)0x00000400UL) +#define M4_INTC ((M4_INTC_TypeDef *)0x40051000UL) +#define M4_KEYSCAN ((M4_KEYSCAN_TypeDef *)0x40050C00UL) +#define M4_MAU ((M4_MAU_TypeDef *)0x40055000UL) +#define M4_MPU ((M4_MPU_TypeDef *)0x40050000UL) +#define M4_NFC ((M4_NFC_TypeDef *)0x88100000UL) +#define M4_OTS ((M4_OTS_TypeDef *)0x4004A800UL) +#define M4_PERIC ((M4_PERIC_TypeDef *)0x40055400UL) +#define M4_PWC ((M4_PWC_TypeDef *)0x40048000UL) +#define M4_QSPI ((M4_QSPI_TypeDef *)0x9C000000UL) +#define M4_RMU ((M4_RMU_TypeDef *)0x4004CC00UL) +#define M4_RTC ((M4_RTC_TypeDef *)0x4004C000UL) +#define M4_SDIOC1 ((M4_SDIOC_TypeDef *)0x40070000UL) +#define M4_SDIOC2 ((M4_SDIOC_TypeDef *)0x40078400UL) +#define M4_SMC ((M4_SMC_TypeDef *)0x88000000UL) +#define M4_SPI1 ((M4_SPI_TypeDef *)0x4001C000UL) +#define M4_SPI2 ((M4_SPI_TypeDef *)0x4001C400UL) +#define M4_SPI3 ((M4_SPI_TypeDef *)0x4001C800UL) +#define M4_SPI4 ((M4_SPI_TypeDef *)0x40020000UL) +#define M4_SPI5 ((M4_SPI_TypeDef *)0x40020400UL) +#define M4_SPI6 ((M4_SPI_TypeDef *)0x40020800UL) +#define M4_SRAMC ((M4_SRAMC_TypeDef *)0x40050800UL) +#define M4_SWDT ((M4_SWDT_TypeDef *)0x40049400UL) +#define M4_TMR0_1 ((M4_TMR0_TypeDef *)0x40024000UL) +#define M4_TMR0_2 ((M4_TMR0_TypeDef *)0x40024400UL) +#define M4_TMR2_1 ((M4_TMR2_TypeDef *)0x40024800UL) +#define M4_TMR2_2 ((M4_TMR2_TypeDef *)0x40024C00UL) +#define M4_TMR2_3 ((M4_TMR2_TypeDef *)0x40025000UL) +#define M4_TMR2_4 ((M4_TMR2_TypeDef *)0x40025400UL) +#define M4_TMR4_1 ((M4_TMR4_TypeDef *)0x40038000UL) +#define M4_TMR4_2 ((M4_TMR4_TypeDef *)0x40038400UL) +#define M4_TMR4_3 ((M4_TMR4_TypeDef *)0x40038800UL) +#define M4_TMR6_1 ((M4_TMR6_TypeDef *)0x40018000UL) +#define M4_TMR6_2 ((M4_TMR6_TypeDef *)0x40018400UL) +#define M4_TMR6_3 ((M4_TMR6_TypeDef *)0x40018800UL) +#define M4_TMR6_4 ((M4_TMR6_TypeDef *)0x40018C00UL) +#define M4_TMR6_5 ((M4_TMR6_TypeDef *)0x40019000UL) +#define M4_TMR6_6 ((M4_TMR6_TypeDef *)0x40019400UL) +#define M4_TMR6_7 ((M4_TMR6_TypeDef *)0x40019800UL) +#define M4_TMR6_8 ((M4_TMR6_TypeDef *)0x40019C00UL) +#define M4_TMRA_1 ((M4_TMRA_TypeDef *)0x4003A000UL) +#define M4_TMRA_10 ((M4_TMRA_TypeDef *)0x40027400UL) +#define M4_TMRA_11 ((M4_TMRA_TypeDef *)0x40027800UL) +#define M4_TMRA_12 ((M4_TMRA_TypeDef *)0x40027C00UL) +#define M4_TMRA_2 ((M4_TMRA_TypeDef *)0x4003A400UL) +#define M4_TMRA_3 ((M4_TMRA_TypeDef *)0x4003A800UL) +#define M4_TMRA_4 ((M4_TMRA_TypeDef *)0x4003AC00UL) +#define M4_TMRA_5 ((M4_TMRA_TypeDef *)0x40026000UL) +#define M4_TMRA_6 ((M4_TMRA_TypeDef *)0x40026400UL) +#define M4_TMRA_7 ((M4_TMRA_TypeDef *)0x40026800UL) +#define M4_TMRA_8 ((M4_TMRA_TypeDef *)0x40026C00UL) +#define M4_TMRA_9 ((M4_TMRA_TypeDef *)0x40027000UL) +#define M4_TRNG ((M4_TRNG_TypeDef *)0x40042000UL) +#define M4_USART1 ((M4_USART_TypeDef *)0x4001CC00UL) +#define M4_USART10 ((M4_USART_TypeDef *)0x40021C00UL) +#define M4_USART2 ((M4_USART_TypeDef *)0x4001D000UL) +#define M4_USART3 ((M4_USART_TypeDef *)0x4001D400UL) +#define M4_USART4 ((M4_USART_TypeDef *)0x4001D800UL) +#define M4_USART5 ((M4_USART_TypeDef *)0x4001DC00UL) +#define M4_USART6 ((M4_USART_TypeDef *)0x40020C00UL) +#define M4_USART7 ((M4_USART_TypeDef *)0x40021000UL) +#define M4_USART8 ((M4_USART_TypeDef *)0x40021400UL) +#define M4_USART9 ((M4_USART_TypeDef *)0x40021800UL) +#define M4_USBFS ((M4_USBFS_TypeDef *)0x40080000UL) +#define M4_USBHS ((M4_USBHS_TypeDef *)0x400C0000UL) +#define M4_WDT ((M4_WDT_TypeDef *)0x40049000UL) + + +/******************************************************************************/ +/* Peripheral Registers Bits Definition */ +/******************************************************************************/ + +/******************************************************************************* + Bit definition for Peripheral ADC +*******************************************************************************/ +/* Bit definition for ADC_STR register */ +#define ADC_STR_STRT (0x01U) + +/* Bit definition for ADC_CR0 register */ +#define ADC_CR0_MS_POS (0U) +#define ADC_CR0_MS (0x0003U) +#define ADC_CR0_MS_0 (0x0001U) +#define ADC_CR0_MS_1 (0x0002U) +#define ADC_CR0_ACCSEL_POS (4U) +#define ADC_CR0_ACCSEL (0x0030U) +#define ADC_CR0_ACCSEL_0 (0x0010U) +#define ADC_CR0_ACCSEL_1 (0x0020U) +#define ADC_CR0_CLREN_POS (6U) +#define ADC_CR0_CLREN (0x0040U) +#define ADC_CR0_DFMT_POS (7U) +#define ADC_CR0_DFMT (0x0080U) +#define ADC_CR0_AVCNT_POS (8U) +#define ADC_CR0_AVCNT (0x0700U) +#define ADC_CR0_AVCNT_0 (0x0100U) +#define ADC_CR0_AVCNT_1 (0x0200U) +#define ADC_CR0_AVCNT_2 (0x0400U) + +/* Bit definition for ADC_CR1 register */ +#define ADC_CR1_RSCHSEL_POS (2U) +#define ADC_CR1_RSCHSEL (0x0004U) + +/* Bit definition for ADC_TRGSR register */ +#define ADC_TRGSR_TRGSELA_POS (0U) +#define ADC_TRGSR_TRGSELA (0x0003U) +#define ADC_TRGSR_TRGSELA_0 (0x0001U) +#define ADC_TRGSR_TRGSELA_1 (0x0002U) +#define ADC_TRGSR_TRGENA_POS (7U) +#define ADC_TRGSR_TRGENA (0x0080U) +#define ADC_TRGSR_TRGSELB_POS (8U) +#define ADC_TRGSR_TRGSELB (0x0300U) +#define ADC_TRGSR_TRGSELB_0 (0x0100U) +#define ADC_TRGSR_TRGSELB_1 (0x0200U) +#define ADC_TRGSR_TRGENB_POS (15U) +#define ADC_TRGSR_TRGENB (0x8000U) + +/* Bit definition for ADC_CHSELRA register */ +#define ADC_CHSELRA_CHSELA (0x000FFFFFUL) + +/* Bit definition for ADC_CHSELRB register */ +#define ADC_CHSELRB_CHSELB (0x000FFFFFUL) + +/* Bit definition for ADC_AVCHSELR register */ +#define ADC_AVCHSELR_AVCHSEL (0x000FFFFFUL) + +/* Bit definition for ADC_EXCHSELR register */ +#define ADC_EXCHSELR_EXCHSEL (0x01U) + +/* Bit definition for ADC_SHCR register */ +#define ADC_SHCR_SHSST_POS (0U) +#define ADC_SHCR_SHSST (0x00FFU) +#define ADC_SHCR_SHSST_0 (0x0001U) +#define ADC_SHCR_SHSST_1 (0x0002U) +#define ADC_SHCR_SHSST_2 (0x0004U) +#define ADC_SHCR_SHSST_3 (0x0008U) +#define ADC_SHCR_SHSST_4 (0x0010U) +#define ADC_SHCR_SHSST_5 (0x0020U) +#define ADC_SHCR_SHSST_6 (0x0040U) +#define ADC_SHCR_SHSST_7 (0x0080U) +#define ADC_SHCR_SHSEL_POS (8U) +#define ADC_SHCR_SHSEL (0x0700U) +#define ADC_SHCR_SHSEL_0 (0x0100U) +#define ADC_SHCR_SHSEL_1 (0x0200U) +#define ADC_SHCR_SHSEL_2 (0x0400U) + +/* Bit definition for ADC_SSTR0 register */ +#define ADC_SSTR0 (0xFFU) + +/* Bit definition for ADC_SSTR1 register */ +#define ADC_SSTR1 (0xFFU) + +/* Bit definition for ADC_SSTR2 register */ +#define ADC_SSTR2 (0xFFU) + +/* Bit definition for ADC_SSTR3 register */ +#define ADC_SSTR3 (0xFFU) + +/* Bit definition for ADC_SSTR4 register */ +#define ADC_SSTR4 (0xFFU) + +/* Bit definition for ADC_SSTR5 register */ +#define ADC_SSTR5 (0xFFU) + +/* Bit definition for ADC_SSTR6 register */ +#define ADC_SSTR6 (0xFFU) + +/* Bit definition for ADC_SSTR7 register */ +#define ADC_SSTR7 (0xFFU) + +/* Bit definition for ADC_SSTR8 register */ +#define ADC_SSTR8 (0xFFU) + +/* Bit definition for ADC_SSTR9 register */ +#define ADC_SSTR9 (0xFFU) + +/* Bit definition for ADC_SSTR10 register */ +#define ADC_SSTR10 (0xFFU) + +/* Bit definition for ADC_SSTR11 register */ +#define ADC_SSTR11 (0xFFU) + +/* Bit definition for ADC_SSTR12 register */ +#define ADC_SSTR12 (0xFFU) + +/* Bit definition for ADC_SSTR13 register */ +#define ADC_SSTR13 (0xFFU) + +/* Bit definition for ADC_SSTR14 register */ +#define ADC_SSTR14 (0xFFU) + +/* Bit definition for ADC_SSTR15 register */ +#define ADC_SSTR15 (0xFFU) + +/* Bit definition for ADC_SSTRL register */ +#define ADC_SSTRL (0xFFU) + +/* Bit definition for ADC_CHMUXR0 register */ +#define ADC_CHMUXR0_CH00MUX_POS (0U) +#define ADC_CHMUXR0_CH00MUX (0x000FU) +#define ADC_CHMUXR0_CH00MUX_0 (0x0001U) +#define ADC_CHMUXR0_CH00MUX_1 (0x0002U) +#define ADC_CHMUXR0_CH00MUX_2 (0x0004U) +#define ADC_CHMUXR0_CH00MUX_3 (0x0008U) +#define ADC_CHMUXR0_CH01MUX_POS (4U) +#define ADC_CHMUXR0_CH01MUX (0x00F0U) +#define ADC_CHMUXR0_CH01MUX_0 (0x0010U) +#define ADC_CHMUXR0_CH01MUX_1 (0x0020U) +#define ADC_CHMUXR0_CH01MUX_2 (0x0040U) +#define ADC_CHMUXR0_CH01MUX_3 (0x0080U) +#define ADC_CHMUXR0_CH02MUX_POS (8U) +#define ADC_CHMUXR0_CH02MUX (0x0F00U) +#define ADC_CHMUXR0_CH02MUX_0 (0x0100U) +#define ADC_CHMUXR0_CH02MUX_1 (0x0200U) +#define ADC_CHMUXR0_CH02MUX_2 (0x0400U) +#define ADC_CHMUXR0_CH02MUX_3 (0x0800U) +#define ADC_CHMUXR0_CH03MUX_POS (12U) +#define ADC_CHMUXR0_CH03MUX (0xF000U) +#define ADC_CHMUXR0_CH03MUX_0 (0x1000U) +#define ADC_CHMUXR0_CH03MUX_1 (0x2000U) +#define ADC_CHMUXR0_CH03MUX_2 (0x4000U) +#define ADC_CHMUXR0_CH03MUX_3 (0x8000U) + +/* Bit definition for ADC_CHMUXR1 register */ +#define ADC_CHMUXR1_CH04MUX_POS (0U) +#define ADC_CHMUXR1_CH04MUX (0x000FU) +#define ADC_CHMUXR1_CH04MUX_0 (0x0001U) +#define ADC_CHMUXR1_CH04MUX_1 (0x0002U) +#define ADC_CHMUXR1_CH04MUX_2 (0x0004U) +#define ADC_CHMUXR1_CH04MUX_3 (0x0008U) +#define ADC_CHMUXR1_CH05MUX_POS (4U) +#define ADC_CHMUXR1_CH05MUX (0x00F0U) +#define ADC_CHMUXR1_CH05MUX_0 (0x0010U) +#define ADC_CHMUXR1_CH05MUX_1 (0x0020U) +#define ADC_CHMUXR1_CH05MUX_2 (0x0040U) +#define ADC_CHMUXR1_CH05MUX_3 (0x0080U) +#define ADC_CHMUXR1_CH06MUX_POS (8U) +#define ADC_CHMUXR1_CH06MUX (0x0F00U) +#define ADC_CHMUXR1_CH06MUX_0 (0x0100U) +#define ADC_CHMUXR1_CH06MUX_1 (0x0200U) +#define ADC_CHMUXR1_CH06MUX_2 (0x0400U) +#define ADC_CHMUXR1_CH06MUX_3 (0x0800U) +#define ADC_CHMUXR1_CH07MUX_POS (12U) +#define ADC_CHMUXR1_CH07MUX (0xF000U) +#define ADC_CHMUXR1_CH07MUX_0 (0x1000U) +#define ADC_CHMUXR1_CH07MUX_1 (0x2000U) +#define ADC_CHMUXR1_CH07MUX_2 (0x4000U) +#define ADC_CHMUXR1_CH07MUX_3 (0x8000U) + +/* Bit definition for ADC_CHMUXR2 register */ +#define ADC_CHMUXR2_CH08MUX_POS (0U) +#define ADC_CHMUXR2_CH08MUX (0x000FU) +#define ADC_CHMUXR2_CH08MUX_0 (0x0001U) +#define ADC_CHMUXR2_CH08MUX_1 (0x0002U) +#define ADC_CHMUXR2_CH08MUX_2 (0x0004U) +#define ADC_CHMUXR2_CH08MUX_3 (0x0008U) +#define ADC_CHMUXR2_CH09MUX_POS (4U) +#define ADC_CHMUXR2_CH09MUX (0x00F0U) +#define ADC_CHMUXR2_CH09MUX_0 (0x0010U) +#define ADC_CHMUXR2_CH09MUX_1 (0x0020U) +#define ADC_CHMUXR2_CH09MUX_2 (0x0040U) +#define ADC_CHMUXR2_CH09MUX_3 (0x0080U) +#define ADC_CHMUXR2_CH10MUX_POS (8U) +#define ADC_CHMUXR2_CH10MUX (0x0F00U) +#define ADC_CHMUXR2_CH10MUX_0 (0x0100U) +#define ADC_CHMUXR2_CH10MUX_1 (0x0200U) +#define ADC_CHMUXR2_CH10MUX_2 (0x0400U) +#define ADC_CHMUXR2_CH10MUX_3 (0x0800U) +#define ADC_CHMUXR2_CH11MUX_POS (12U) +#define ADC_CHMUXR2_CH11MUX (0xF000U) +#define ADC_CHMUXR2_CH11MUX_0 (0x1000U) +#define ADC_CHMUXR2_CH11MUX_1 (0x2000U) +#define ADC_CHMUXR2_CH11MUX_2 (0x4000U) +#define ADC_CHMUXR2_CH11MUX_3 (0x8000U) + +/* Bit definition for ADC_CHMUXR3 register */ +#define ADC_CHMUXR3_CH12MUX_POS (0U) +#define ADC_CHMUXR3_CH12MUX (0x000FU) +#define ADC_CHMUXR3_CH12MUX_0 (0x0001U) +#define ADC_CHMUXR3_CH12MUX_1 (0x0002U) +#define ADC_CHMUXR3_CH12MUX_2 (0x0004U) +#define ADC_CHMUXR3_CH12MUX_3 (0x0008U) +#define ADC_CHMUXR3_CH13MUX_POS (4U) +#define ADC_CHMUXR3_CH13MUX (0x00F0U) +#define ADC_CHMUXR3_CH13MUX_0 (0x0010U) +#define ADC_CHMUXR3_CH13MUX_1 (0x0020U) +#define ADC_CHMUXR3_CH13MUX_2 (0x0040U) +#define ADC_CHMUXR3_CH13MUX_3 (0x0080U) +#define ADC_CHMUXR3_CH14MUX_POS (8U) +#define ADC_CHMUXR3_CH14MUX (0x0F00U) +#define ADC_CHMUXR3_CH14MUX_0 (0x0100U) +#define ADC_CHMUXR3_CH14MUX_1 (0x0200U) +#define ADC_CHMUXR3_CH14MUX_2 (0x0400U) +#define ADC_CHMUXR3_CH14MUX_3 (0x0800U) +#define ADC_CHMUXR3_CH15MUX_POS (12U) +#define ADC_CHMUXR3_CH15MUX (0xF000U) +#define ADC_CHMUXR3_CH15MUX_0 (0x1000U) +#define ADC_CHMUXR3_CH15MUX_1 (0x2000U) +#define ADC_CHMUXR3_CH15MUX_2 (0x4000U) +#define ADC_CHMUXR3_CH15MUX_3 (0x8000U) + +/* Bit definition for ADC_ISR register */ +#define ADC_ISR_EOCAF_POS (0U) +#define ADC_ISR_EOCAF (0x01U) +#define ADC_ISR_EOCBF_POS (1U) +#define ADC_ISR_EOCBF (0x02U) +#define ADC_ISR_SASTPDF_POS (4U) +#define ADC_ISR_SASTPDF (0x10U) + +/* Bit definition for ADC_ICR register */ +#define ADC_ICR_EOCAIEN_POS (0U) +#define ADC_ICR_EOCAIEN (0x01U) +#define ADC_ICR_EOCBIEN_POS (1U) +#define ADC_ICR_EOCBIEN (0x02U) + +/* Bit definition for ADC_ISCLRR register */ +#define ADC_ISCLRR_CLREOCAF_POS (0U) +#define ADC_ISCLRR_CLREOCAF (0x01U) +#define ADC_ISCLRR_CLREOCBF_POS (1U) +#define ADC_ISCLRR_CLREOCBF (0x02U) +#define ADC_ISCLRR_CLRSASTPDF_POS (4U) +#define ADC_ISCLRR_CLRSASTPDF (0x10U) + +/* Bit definition for ADC_SYNCCR register */ +#define ADC_SYNCCR_SYNCEN_POS (0U) +#define ADC_SYNCCR_SYNCEN (0x0001U) +#define ADC_SYNCCR_SYNCMD_POS (4U) +#define ADC_SYNCCR_SYNCMD (0x0070U) +#define ADC_SYNCCR_SYNCMD_0 (0x0010U) +#define ADC_SYNCCR_SYNCMD_1 (0x0020U) +#define ADC_SYNCCR_SYNCMD_2 (0x0040U) +#define ADC_SYNCCR_SYNCDLY_POS (8U) +#define ADC_SYNCCR_SYNCDLY (0xFF00U) +#define ADC_SYNCCR_SYNCDLY_0 (0x0100U) +#define ADC_SYNCCR_SYNCDLY_1 (0x0200U) +#define ADC_SYNCCR_SYNCDLY_2 (0x0400U) +#define ADC_SYNCCR_SYNCDLY_3 (0x0800U) +#define ADC_SYNCCR_SYNCDLY_4 (0x1000U) +#define ADC_SYNCCR_SYNCDLY_5 (0x2000U) +#define ADC_SYNCCR_SYNCDLY_6 (0x4000U) +#define ADC_SYNCCR_SYNCDLY_7 (0x8000U) + +/* Bit definition for ADC_DR0 register */ +#define ADC_DR0 (0xFFFFU) + +/* Bit definition for ADC_DR1 register */ +#define ADC_DR1 (0xFFFFU) + +/* Bit definition for ADC_DR2 register */ +#define ADC_DR2 (0xFFFFU) + +/* Bit definition for ADC_DR3 register */ +#define ADC_DR3 (0xFFFFU) + +/* Bit definition for ADC_DR4 register */ +#define ADC_DR4 (0xFFFFU) + +/* Bit definition for ADC_DR5 register */ +#define ADC_DR5 (0xFFFFU) + +/* Bit definition for ADC_DR6 register */ +#define ADC_DR6 (0xFFFFU) + +/* Bit definition for ADC_DR7 register */ +#define ADC_DR7 (0xFFFFU) + +/* Bit definition for ADC_DR8 register */ +#define ADC_DR8 (0xFFFFU) + +/* Bit definition for ADC_DR9 register */ +#define ADC_DR9 (0xFFFFU) + +/* Bit definition for ADC_DR10 register */ +#define ADC_DR10 (0xFFFFU) + +/* Bit definition for ADC_DR11 register */ +#define ADC_DR11 (0xFFFFU) + +/* Bit definition for ADC_DR12 register */ +#define ADC_DR12 (0xFFFFU) + +/* Bit definition for ADC_DR13 register */ +#define ADC_DR13 (0xFFFFU) + +/* Bit definition for ADC_DR14 register */ +#define ADC_DR14 (0xFFFFU) + +/* Bit definition for ADC_DR15 register */ +#define ADC_DR15 (0xFFFFU) + +/* Bit definition for ADC_DR16 register */ +#define ADC_DR16 (0xFFFFU) + +/* Bit definition for ADC_DR17 register */ +#define ADC_DR17 (0xFFFFU) + +/* Bit definition for ADC_DR18 register */ +#define ADC_DR18 (0xFFFFU) + +/* Bit definition for ADC_DR19 register */ +#define ADC_DR19 (0xFFFFU) + +/* Bit definition for ADC_AWDCR register */ +#define ADC_AWDCR_AWD0EN_POS (0U) +#define ADC_AWDCR_AWD0EN (0x0001U) +#define ADC_AWDCR_AWD0IEN_POS (1U) +#define ADC_AWDCR_AWD0IEN (0x0002U) +#define ADC_AWDCR_AWD0MD_POS (2U) +#define ADC_AWDCR_AWD0MD (0x0004U) +#define ADC_AWDCR_AWD1EN_POS (4U) +#define ADC_AWDCR_AWD1EN (0x0010U) +#define ADC_AWDCR_AWD1IEN_POS (5U) +#define ADC_AWDCR_AWD1IEN (0x0020U) +#define ADC_AWDCR_AWD1MD_POS (6U) +#define ADC_AWDCR_AWD1MD (0x0040U) +#define ADC_AWDCR_AWDCM_POS (8U) +#define ADC_AWDCR_AWDCM (0x0300U) +#define ADC_AWDCR_AWDCM_0 (0x0100U) +#define ADC_AWDCR_AWDCM_1 (0x0200U) + +/* Bit definition for ADC_AWDSR register */ +#define ADC_AWDSR_AWD0F_POS (0U) +#define ADC_AWDSR_AWD0F (0x01U) +#define ADC_AWDSR_AWD1F_POS (1U) +#define ADC_AWDSR_AWD1F (0x02U) +#define ADC_AWDSR_AWDCMF_POS (4U) +#define ADC_AWDSR_AWDCMF (0x10U) + +/* Bit definition for ADC_AWDSCLRR register */ +#define ADC_AWDSCLRR_CLRAWD0F_POS (0U) +#define ADC_AWDSCLRR_CLRAWD0F (0x01U) +#define ADC_AWDSCLRR_CLRAWD1F_POS (1U) +#define ADC_AWDSCLRR_CLRAWD1F (0x02U) +#define ADC_AWDSCLRR_CLRAWDCMF_POS (4U) +#define ADC_AWDSCLRR_CLRAWDCMF (0x10U) + +/* Bit definition for ADC_AWD0DR0 register */ +#define ADC_AWD0DR0 (0xFFFFU) + +/* Bit definition for ADC_AWD0DR1 register */ +#define ADC_AWD0DR1 (0xFFFFU) + +/* Bit definition for ADC_AWD0CHSR register */ +#define ADC_AWD0CHSR_AWDCH (0x001FU) + +/* Bit definition for ADC_AWD1DR0 register */ +#define ADC_AWD1DR0 (0xFFFFU) + +/* Bit definition for ADC_AWD1DR1 register */ +#define ADC_AWD1DR1 (0xFFFFU) + +/* Bit definition for ADC_AWD1CHSR register */ +#define ADC_AWD1CHSR_AWDCH (0x001FU) + +/* Bit definition for ADC_PGACR1 register */ +#define ADC_PGACR1_PGACTL_POS (0U) +#define ADC_PGACR1_PGACTL (0x0FU) +#define ADC_PGACR1_PGACTL_0 (0x01U) +#define ADC_PGACR1_PGACTL_1 (0x02U) +#define ADC_PGACR1_PGACTL_2 (0x04U) +#define ADC_PGACR1_PGACTL_3 (0x08U) +#define ADC_PGACR1_PGAGAIN_POS (4U) +#define ADC_PGACR1_PGAGAIN (0xF0U) +#define ADC_PGACR1_PGAGAIN_0 (0x10U) +#define ADC_PGACR1_PGAGAIN_1 (0x20U) +#define ADC_PGACR1_PGAGAIN_2 (0x40U) +#define ADC_PGACR1_PGAGAIN_3 (0x80U) + +/* Bit definition for ADC_PGACR2 register */ +#define ADC_PGACR2_PGACTL_POS (0U) +#define ADC_PGACR2_PGACTL (0x0FU) +#define ADC_PGACR2_PGACTL_0 (0x01U) +#define ADC_PGACR2_PGACTL_1 (0x02U) +#define ADC_PGACR2_PGACTL_2 (0x04U) +#define ADC_PGACR2_PGACTL_3 (0x08U) +#define ADC_PGACR2_PGAGAIN_POS (4U) +#define ADC_PGACR2_PGAGAIN (0xF0U) +#define ADC_PGACR2_PGAGAIN_0 (0x10U) +#define ADC_PGACR2_PGAGAIN_1 (0x20U) +#define ADC_PGACR2_PGAGAIN_2 (0x40U) +#define ADC_PGACR2_PGAGAIN_3 (0x80U) + +/* Bit definition for ADC_PGACR3 register */ +#define ADC_PGACR3_PGACTL_POS (0U) +#define ADC_PGACR3_PGACTL (0x0FU) +#define ADC_PGACR3_PGACTL_0 (0x01U) +#define ADC_PGACR3_PGACTL_1 (0x02U) +#define ADC_PGACR3_PGACTL_2 (0x04U) +#define ADC_PGACR3_PGACTL_3 (0x08U) +#define ADC_PGACR3_PGAGAIN_POS (4U) +#define ADC_PGACR3_PGAGAIN (0xF0U) +#define ADC_PGACR3_PGAGAIN_0 (0x10U) +#define ADC_PGACR3_PGAGAIN_1 (0x20U) +#define ADC_PGACR3_PGAGAIN_2 (0x40U) +#define ADC_PGACR3_PGAGAIN_3 (0x80U) + +/* Bit definition for ADC_PGAVSSENR register */ +#define ADC_PGAVSSENR_PGAVSSEN (0x07U) + +/******************************************************************************* + Bit definition for Peripheral AES +*******************************************************************************/ +/* Bit definition for AES_CR register */ +#define AES_CR_START_POS (0U) +#define AES_CR_START (0x00000001UL) +#define AES_CR_MODE_POS (1U) +#define AES_CR_MODE (0x00000002UL) +#define AES_CR_KEYSIZE_POS (3U) +#define AES_CR_KEYSIZE (0x00000018UL) + +/* Bit definition for AES_DR0 register */ +#define AES_DR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR1 register */ +#define AES_DR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR2 register */ +#define AES_DR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_DR3 register */ +#define AES_DR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR0 register */ +#define AES_KR0 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR1 register */ +#define AES_KR1 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR2 register */ +#define AES_KR2 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR3 register */ +#define AES_KR3 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR4 register */ +#define AES_KR4 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR5 register */ +#define AES_KR5 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR6 register */ +#define AES_KR6 (0xFFFFFFFFUL) + +/* Bit definition for AES_KR7 register */ +#define AES_KR7 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral AOS +*******************************************************************************/ +/* Bit definition for AOS_INT_SFTTRG register */ +#define AOS_INT_SFTTRG_STRG (0x00000001UL) + +/* Bit definition for AOS_DCU_1_TRGSEL register */ +#define AOS_DCU_1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_1_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DCU_1_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DCU_1_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DCU_1_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DCU_2_TRGSEL register */ +#define AOS_DCU_2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_2_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DCU_2_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DCU_2_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DCU_2_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DCU_3_TRGSEL register */ +#define AOS_DCU_3_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_3_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_3_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DCU_3_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DCU_3_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DCU_3_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DCU_4_TRGSEL register */ +#define AOS_DCU_4_TRGSEL_TRGSEL_POS (0U) +#define AOS_DCU_4_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DCU_4_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DCU_4_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DCU_4_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DCU_4_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_1_TRGSEL register */ +#define AOS_DMA_1_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA_1_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA_1_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DMA_1_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DMA_1_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DMA_1_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_2_TRGSEL register */ +#define AOS_DMA_2_TRGSEL_TRGSEL_POS (0U) +#define AOS_DMA_2_TRGSEL_TRGSEL (0x000001FFUL) +#define AOS_DMA_2_TRGSEL_COMTRG_EN_POS (30U) +#define AOS_DMA_2_TRGSEL_COMTRG_EN (0xC0000000UL) +#define AOS_DMA_2_TRGSEL_COMTRG_EN_0 (0x40000000UL) +#define AOS_DMA_2_TRGSEL_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_DMA_TRGSELRC register */ +#define AOS_DMA_TRGSELRC_TRGSEL_POS (0U) +#define AOS_DMA_TRGSELRC_TRGSEL (0x000001FFUL) +#define AOS_DMA_TRGSELRC_COMTRG_EN_POS (30U) +#define AOS_DMA_TRGSELRC_COMTRG_EN (0xC0000000UL) +#define AOS_DMA_TRGSELRC_COMTRG_EN_0 (0x40000000UL) +#define AOS_DMA_TRGSELRC_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR6_HTSSR register */ +#define AOS_TMR6_HTSSR_TRGSEL_POS (0U) +#define AOS_TMR6_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMR6_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMR6_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMR6_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMR6_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_PORT_PEVNTTRGSR12 register */ +#define AOS_PORT_PEVNTTRGSR12_TRGSEL_POS (0U) +#define AOS_PORT_PEVNTTRGSR12_TRGSEL (0x000001FFUL) +#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN_POS (30U) +#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN (0xC0000000UL) +#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN_0 (0x40000000UL) +#define AOS_PORT_PEVNTTRGSR12_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_PORT_PEVNTTRGSR34 register */ +#define AOS_PORT_PEVNTTRGSR34_TRGSEL_POS (0U) +#define AOS_PORT_PEVNTTRGSR34_TRGSEL (0x000001FFUL) +#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN_POS (30U) +#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN (0xC0000000UL) +#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN_0 (0x40000000UL) +#define AOS_PORT_PEVNTTRGSR34_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR0_HTSSR register */ +#define AOS_TMR0_HTSSR_TRGSEL_POS (0U) +#define AOS_TMR0_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMR0_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMR0_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMR0_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMR0_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMR2_HTSSR register */ +#define AOS_TMR2_HTSSR_TRGSEL_POS (0U) +#define AOS_TMR2_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMR2_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMR2_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMR2_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMR2_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_HASH_ITRGSELA register */ +#define AOS_HASH_ITRGSELA_TRGSEL_POS (0U) +#define AOS_HASH_ITRGSELA_TRGSEL (0x000001FFUL) +#define AOS_HASH_ITRGSELA_COMTRG_EN_POS (30U) +#define AOS_HASH_ITRGSELA_COMTRG_EN (0xC0000000UL) +#define AOS_HASH_ITRGSELA_COMTRG_EN_0 (0x40000000UL) +#define AOS_HASH_ITRGSELA_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_HASH_ITRGSELB register */ +#define AOS_HASH_ITRGSELB_TRGSEL_POS (0U) +#define AOS_HASH_ITRGSELB_TRGSEL (0x000001FFUL) +#define AOS_HASH_ITRGSELB_COMTRG_EN_POS (30U) +#define AOS_HASH_ITRGSELB_COMTRG_EN (0xC0000000UL) +#define AOS_HASH_ITRGSELB_COMTRG_EN_0 (0x40000000UL) +#define AOS_HASH_ITRGSELB_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_TMRA_HTSSR register */ +#define AOS_TMRA_HTSSR_TRGSEL_POS (0U) +#define AOS_TMRA_HTSSR_TRGSEL (0x000001FFUL) +#define AOS_TMRA_HTSSR_COMTRG_EN_POS (30U) +#define AOS_TMRA_HTSSR_COMTRG_EN (0xC0000000UL) +#define AOS_TMRA_HTSSR_COMTRG_EN_0 (0x40000000UL) +#define AOS_TMRA_HTSSR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_OTS_TRG register */ +#define AOS_OTS_TRG_TRGSEL_POS (0U) +#define AOS_OTS_TRG_TRGSEL (0x000001FFUL) +#define AOS_OTS_TRG_COMTRG_EN_POS (30U) +#define AOS_OTS_TRG_COMTRG_EN (0xC0000000UL) +#define AOS_OTS_TRG_COMTRG_EN_0 (0x40000000UL) +#define AOS_OTS_TRG_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC_1_ITRGSELR register */ +#define AOS_ADC_1_ITRGSELR_TRGSEL_POS (0U) +#define AOS_ADC_1_ITRGSELR_TRGSEL (0x000001FFUL) +#define AOS_ADC_1_ITRGSELR_COMTRG_EN_POS (30U) +#define AOS_ADC_1_ITRGSELR_COMTRG_EN (0xC0000000UL) +#define AOS_ADC_1_ITRGSELR_COMTRG_EN_0 (0x40000000UL) +#define AOS_ADC_1_ITRGSELR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC_2_ITRGSELR register */ +#define AOS_ADC_2_ITRGSELR_TRGSEL_POS (0U) +#define AOS_ADC_2_ITRGSELR_TRGSEL (0x000001FFUL) +#define AOS_ADC_2_ITRGSELR_COMTRG_EN_POS (30U) +#define AOS_ADC_2_ITRGSELR_COMTRG_EN (0xC0000000UL) +#define AOS_ADC_2_ITRGSELR_COMTRG_EN_0 (0x40000000UL) +#define AOS_ADC_2_ITRGSELR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_ADC_3_ITRGSELR register */ +#define AOS_ADC_3_ITRGSELR_TRGSEL_POS (0U) +#define AOS_ADC_3_ITRGSELR_TRGSEL (0x000001FFUL) +#define AOS_ADC_3_ITRGSELR_COMTRG_EN_POS (30U) +#define AOS_ADC_3_ITRGSELR_COMTRG_EN (0xC0000000UL) +#define AOS_ADC_3_ITRGSELR_COMTRG_EN_0 (0x40000000UL) +#define AOS_ADC_3_ITRGSELR_COMTRG_EN_1 (0x80000000UL) + +/* Bit definition for AOS_COMTRG1 register */ +#define AOS_COMTRG1_TRGSEL (0x000001FFUL) + +/* Bit definition for AOS_COMTRG2 register */ +#define AOS_COMTRG2_TRGSEL (0x000001FFUL) + +/* Bit definition for AOS_GPIO_PEVNTDIRR register */ +#define AOS_GPIO_PEVNTDIRR_PDIR (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTIDR register */ +#define AOS_GPIO_PEVNTIDR_PIN (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTODR register */ +#define AOS_GPIO_PEVNTODR_POUT (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTORR register */ +#define AOS_GPIO_PEVNTORR_POR (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTOSR register */ +#define AOS_GPIO_PEVNTOSR_POS (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTRISR register */ +#define AOS_GPIO_PEVNTRISR_RIS (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTFAL register */ +#define AOS_GPIO_PEVNTFAL_FAL (0x0000FFFFUL) + +/* Bit definition for AOS_GPIO_PEVNTNFCR register */ +#define AOS_GPIO_PEVNTNFCR_NFEN1_POS (0U) +#define AOS_GPIO_PEVNTNFCR_NFEN1 (0x00000001UL) +#define AOS_GPIO_PEVNTNFCR_DIVS1_POS (1U) +#define AOS_GPIO_PEVNTNFCR_DIVS1 (0x00000006UL) +#define AOS_GPIO_PEVNTNFCR_NFEN2_POS (8U) +#define AOS_GPIO_PEVNTNFCR_NFEN2 (0x00000100UL) +#define AOS_GPIO_PEVNTNFCR_DIVS2_POS (9U) +#define AOS_GPIO_PEVNTNFCR_DIVS2 (0x00000600UL) +#define AOS_GPIO_PEVNTNFCR_NFEN3_POS (16U) +#define AOS_GPIO_PEVNTNFCR_NFEN3 (0x00010000UL) +#define AOS_GPIO_PEVNTNFCR_DIVS3_POS (17U) +#define AOS_GPIO_PEVNTNFCR_DIVS3 (0x00060000UL) +#define AOS_GPIO_PEVNTNFCR_NFEN4_POS (24U) +#define AOS_GPIO_PEVNTNFCR_NFEN4 (0x01000000UL) +#define AOS_GPIO_PEVNTNFCR_DIVS4_POS (25U) +#define AOS_GPIO_PEVNTNFCR_DIVS4 (0x06000000UL) + +/******************************************************************************* + Bit definition for Peripheral CAN +*******************************************************************************/ +/* Bit definition for CAN_RBUF register */ +#define CAN_RBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_TBUF register */ +#define CAN_TBUF (0xFFFFFFFFUL) + +/* Bit definition for CAN_CFG_STAT register */ +#define CAN_CFG_STAT_BUSOFF_POS (0U) +#define CAN_CFG_STAT_BUSOFF (0x01U) +#define CAN_CFG_STAT_TACTIVE_POS (1U) +#define CAN_CFG_STAT_TACTIVE (0x02U) +#define CAN_CFG_STAT_RACTIVE_POS (2U) +#define CAN_CFG_STAT_RACTIVE (0x04U) +#define CAN_CFG_STAT_TSSS_POS (3U) +#define CAN_CFG_STAT_TSSS (0x08U) +#define CAN_CFG_STAT_TPSS_POS (4U) +#define CAN_CFG_STAT_TPSS (0x10U) +#define CAN_CFG_STAT_LBMI_POS (5U) +#define CAN_CFG_STAT_LBMI (0x20U) +#define CAN_CFG_STAT_LBME_POS (6U) +#define CAN_CFG_STAT_LBME (0x40U) +#define CAN_CFG_STAT_RESET_POS (7U) +#define CAN_CFG_STAT_RESET (0x80U) + +/* Bit definition for CAN_TCMD register */ +#define CAN_TCMD_TSA_POS (0U) +#define CAN_TCMD_TSA (0x01U) +#define CAN_TCMD_TSALL_POS (1U) +#define CAN_TCMD_TSALL (0x02U) +#define CAN_TCMD_TSONE_POS (2U) +#define CAN_TCMD_TSONE (0x04U) +#define CAN_TCMD_TPA_POS (3U) +#define CAN_TCMD_TPA (0x08U) +#define CAN_TCMD_TPE_POS (4U) +#define CAN_TCMD_TPE (0x10U) +#define CAN_TCMD_LOM_POS (6U) +#define CAN_TCMD_LOM (0x40U) +#define CAN_TCMD_TBSEL_POS (7U) +#define CAN_TCMD_TBSEL (0x80U) + +/* Bit definition for CAN_TCTRL register */ +#define CAN_TCTRL_TSSTAT_POS (0U) +#define CAN_TCTRL_TSSTAT (0x03U) +#define CAN_TCTRL_TSSTAT_0 (0x01U) +#define CAN_TCTRL_TSSTAT_1 (0x02U) +#define CAN_TCTRL_TTTBM_POS (4U) +#define CAN_TCTRL_TTTBM (0x10U) +#define CAN_TCTRL_TSMODE_POS (5U) +#define CAN_TCTRL_TSMODE (0x20U) +#define CAN_TCTRL_TSNEXT_POS (6U) +#define CAN_TCTRL_TSNEXT (0x40U) +#define CAN_TCTRL_FD_ISO_POS (7U) +#define CAN_TCTRL_FD_ISO (0x80U) + +/* Bit definition for CAN_RCTRL register */ +#define CAN_RCTRL_RSTAT_POS (0U) +#define CAN_RCTRL_RSTAT (0x03U) +#define CAN_RCTRL_RSTAT_0 (0x01U) +#define CAN_RCTRL_RSTAT_1 (0x02U) +#define CAN_RCTRL_RBALL_POS (3U) +#define CAN_RCTRL_RBALL (0x08U) +#define CAN_RCTRL_RREL_POS (4U) +#define CAN_RCTRL_RREL (0x10U) +#define CAN_RCTRL_ROV_POS (5U) +#define CAN_RCTRL_ROV (0x20U) +#define CAN_RCTRL_ROM_POS (6U) +#define CAN_RCTRL_ROM (0x40U) +#define CAN_RCTRL_SACK_POS (7U) +#define CAN_RCTRL_SACK (0x80U) + +/* Bit definition for CAN_RTIE register */ +#define CAN_RTIE_TSFF_POS (0U) +#define CAN_RTIE_TSFF (0x01U) +#define CAN_RTIE_EIE_POS (1U) +#define CAN_RTIE_EIE (0x02U) +#define CAN_RTIE_TSIE_POS (2U) +#define CAN_RTIE_TSIE (0x04U) +#define CAN_RTIE_TPIE_POS (3U) +#define CAN_RTIE_TPIE (0x08U) +#define CAN_RTIE_RAFIE_POS (4U) +#define CAN_RTIE_RAFIE (0x10U) +#define CAN_RTIE_RFIE_POS (5U) +#define CAN_RTIE_RFIE (0x20U) +#define CAN_RTIE_ROIE_POS (6U) +#define CAN_RTIE_ROIE (0x40U) +#define CAN_RTIE_RIE_POS (7U) +#define CAN_RTIE_RIE (0x80U) + +/* Bit definition for CAN_RTIF register */ +#define CAN_RTIF_AIF_POS (0U) +#define CAN_RTIF_AIF (0x01U) +#define CAN_RTIF_EIF_POS (1U) +#define CAN_RTIF_EIF (0x02U) +#define CAN_RTIF_TSIF_POS (2U) +#define CAN_RTIF_TSIF (0x04U) +#define CAN_RTIF_TPIF_POS (3U) +#define CAN_RTIF_TPIF (0x08U) +#define CAN_RTIF_RAFIF_POS (4U) +#define CAN_RTIF_RAFIF (0x10U) +#define CAN_RTIF_RFIF_POS (5U) +#define CAN_RTIF_RFIF (0x20U) +#define CAN_RTIF_ROIF_POS (6U) +#define CAN_RTIF_ROIF (0x40U) +#define CAN_RTIF_RIF_POS (7U) +#define CAN_RTIF_RIF (0x80U) + +/* Bit definition for CAN_ERRINT register */ +#define CAN_ERRINT_BEIF_POS (0U) +#define CAN_ERRINT_BEIF (0x01U) +#define CAN_ERRINT_BEIE_POS (1U) +#define CAN_ERRINT_BEIE (0x02U) +#define CAN_ERRINT_ALIF_POS (2U) +#define CAN_ERRINT_ALIF (0x04U) +#define CAN_ERRINT_ALIE_POS (3U) +#define CAN_ERRINT_ALIE (0x08U) +#define CAN_ERRINT_EPIF_POS (4U) +#define CAN_ERRINT_EPIF (0x10U) +#define CAN_ERRINT_EPIE_POS (5U) +#define CAN_ERRINT_EPIE (0x20U) +#define CAN_ERRINT_EPASS_POS (6U) +#define CAN_ERRINT_EPASS (0x40U) +#define CAN_ERRINT_EWARN_POS (7U) +#define CAN_ERRINT_EWARN (0x80U) + +/* Bit definition for CAN_LIMIT register */ +#define CAN_LIMIT_EWL_POS (0U) +#define CAN_LIMIT_EWL (0x0FU) +#define CAN_LIMIT_EWL_0 (0x01U) +#define CAN_LIMIT_EWL_1 (0x02U) +#define CAN_LIMIT_EWL_2 (0x04U) +#define CAN_LIMIT_EWL_3 (0x08U) +#define CAN_LIMIT_AFWL_POS (4U) +#define CAN_LIMIT_AFWL (0xF0U) +#define CAN_LIMIT_AFWL_0 (0x10U) +#define CAN_LIMIT_AFWL_1 (0x20U) +#define CAN_LIMIT_AFWL_2 (0x40U) +#define CAN_LIMIT_AFWL_3 (0x80U) + +/* Bit definition for CAN_SBT register */ +#define CAN_SBT_S_SEG_1_POS (0U) +#define CAN_SBT_S_SEG_1 (0x000000FFUL) +#define CAN_SBT_S_SEG_1_0 (0x00000001UL) +#define CAN_SBT_S_SEG_1_1 (0x00000002UL) +#define CAN_SBT_S_SEG_1_2 (0x00000004UL) +#define CAN_SBT_S_SEG_1_3 (0x00000008UL) +#define CAN_SBT_S_SEG_1_4 (0x00000010UL) +#define CAN_SBT_S_SEG_1_5 (0x00000020UL) +#define CAN_SBT_S_SEG_1_6 (0x00000040UL) +#define CAN_SBT_S_SEG_1_7 (0x00000080UL) +#define CAN_SBT_S_SEG_2_POS (8U) +#define CAN_SBT_S_SEG_2 (0x00007F00UL) +#define CAN_SBT_S_SEG_2_0 (0x00000100UL) +#define CAN_SBT_S_SEG_2_1 (0x00000200UL) +#define CAN_SBT_S_SEG_2_2 (0x00000400UL) +#define CAN_SBT_S_SEG_2_3 (0x00000800UL) +#define CAN_SBT_S_SEG_2_4 (0x00001000UL) +#define CAN_SBT_S_SEG_2_5 (0x00002000UL) +#define CAN_SBT_S_SEG_2_6 (0x00004000UL) +#define CAN_SBT_S_SJW_POS (16U) +#define CAN_SBT_S_SJW (0x007F0000UL) +#define CAN_SBT_S_SJW_0 (0x00010000UL) +#define CAN_SBT_S_SJW_1 (0x00020000UL) +#define CAN_SBT_S_SJW_2 (0x00040000UL) +#define CAN_SBT_S_SJW_3 (0x00080000UL) +#define CAN_SBT_S_SJW_4 (0x00100000UL) +#define CAN_SBT_S_SJW_5 (0x00200000UL) +#define CAN_SBT_S_SJW_6 (0x00400000UL) +#define CAN_SBT_S_PRESC_POS (24U) +#define CAN_SBT_S_PRESC (0xFF000000UL) +#define CAN_SBT_S_PRESC_0 (0x01000000UL) +#define CAN_SBT_S_PRESC_1 (0x02000000UL) +#define CAN_SBT_S_PRESC_2 (0x04000000UL) +#define CAN_SBT_S_PRESC_3 (0x08000000UL) +#define CAN_SBT_S_PRESC_4 (0x10000000UL) +#define CAN_SBT_S_PRESC_5 (0x20000000UL) +#define CAN_SBT_S_PRESC_6 (0x40000000UL) +#define CAN_SBT_S_PRESC_7 (0x80000000UL) + +/* Bit definition for CAN_FBT register */ +#define CAN_FBT_F_SEG_1_POS (0U) +#define CAN_FBT_F_SEG_1 (0x0000001FUL) +#define CAN_FBT_F_SEG_1_0 (0x00000001UL) +#define CAN_FBT_F_SEG_1_1 (0x00000002UL) +#define CAN_FBT_F_SEG_1_2 (0x00000004UL) +#define CAN_FBT_F_SEG_1_3 (0x00000008UL) +#define CAN_FBT_F_SEG_1_4 (0x00000010UL) +#define CAN_FBT_F_SEG_2_POS (8U) +#define CAN_FBT_F_SEG_2 (0x00000F00UL) +#define CAN_FBT_F_SEG_2_0 (0x00000100UL) +#define CAN_FBT_F_SEG_2_1 (0x00000200UL) +#define CAN_FBT_F_SEG_2_2 (0x00000400UL) +#define CAN_FBT_F_SEG_2_3 (0x00000800UL) +#define CAN_FBT_F_SJW_POS (16U) +#define CAN_FBT_F_SJW (0x000F0000UL) +#define CAN_FBT_F_SJW_0 (0x00010000UL) +#define CAN_FBT_F_SJW_1 (0x00020000UL) +#define CAN_FBT_F_SJW_2 (0x00040000UL) +#define CAN_FBT_F_SJW_3 (0x00080000UL) +#define CAN_FBT_F_PRESC_POS (24U) +#define CAN_FBT_F_PRESC (0xFF000000UL) +#define CAN_FBT_F_PRESC_0 (0x01000000UL) +#define CAN_FBT_F_PRESC_1 (0x02000000UL) +#define CAN_FBT_F_PRESC_2 (0x04000000UL) +#define CAN_FBT_F_PRESC_3 (0x08000000UL) +#define CAN_FBT_F_PRESC_4 (0x10000000UL) +#define CAN_FBT_F_PRESC_5 (0x20000000UL) +#define CAN_FBT_F_PRESC_6 (0x40000000UL) +#define CAN_FBT_F_PRESC_7 (0x80000000UL) + +/* Bit definition for CAN_EALCAP register */ +#define CAN_EALCAP_ALC_POS (0U) +#define CAN_EALCAP_ALC (0x1FU) +#define CAN_EALCAP_ALC_0 (0x01U) +#define CAN_EALCAP_ALC_1 (0x02U) +#define CAN_EALCAP_ALC_2 (0x04U) +#define CAN_EALCAP_ALC_3 (0x08U) +#define CAN_EALCAP_ALC_4 (0x10U) +#define CAN_EALCAP_KOER_POS (5U) +#define CAN_EALCAP_KOER (0xE0U) +#define CAN_EALCAP_KOER_0 (0x20U) +#define CAN_EALCAP_KOER_1 (0x40U) +#define CAN_EALCAP_KOER_2 (0x80U) + +/* Bit definition for CAN_TDC register */ +#define CAN_TDC_SSPOFF_POS (0U) +#define CAN_TDC_SSPOFF (0x7FU) +#define CAN_TDC_SSPOFF_0 (0x01U) +#define CAN_TDC_SSPOFF_1 (0x02U) +#define CAN_TDC_SSPOFF_2 (0x04U) +#define CAN_TDC_SSPOFF_3 (0x08U) +#define CAN_TDC_SSPOFF_4 (0x10U) +#define CAN_TDC_SSPOFF_5 (0x20U) +#define CAN_TDC_SSPOFF_6 (0x40U) +#define CAN_TDC_TDCEN_POS (7U) +#define CAN_TDC_TDCEN (0x80U) + +/* Bit definition for CAN_RECNT register */ +#define CAN_RECNT (0xFFU) + +/* Bit definition for CAN_TECNT register */ +#define CAN_TECNT (0xFFU) + +/* Bit definition for CAN_ACFCTRL register */ +#define CAN_ACFCTRL_ACFADR_POS (0U) +#define CAN_ACFCTRL_ACFADR (0x0FU) +#define CAN_ACFCTRL_ACFADR_0 (0x01U) +#define CAN_ACFCTRL_ACFADR_1 (0x02U) +#define CAN_ACFCTRL_ACFADR_2 (0x04U) +#define CAN_ACFCTRL_ACFADR_3 (0x08U) +#define CAN_ACFCTRL_SELMASK_POS (5U) +#define CAN_ACFCTRL_SELMASK (0x20U) + +/* Bit definition for CAN_ACFEN register */ +#define CAN_ACFEN_AE_1_POS (0U) +#define CAN_ACFEN_AE_1 (0x0001U) +#define CAN_ACFEN_AE_2_POS (1U) +#define CAN_ACFEN_AE_2 (0x0002U) +#define CAN_ACFEN_AE_3_POS (2U) +#define CAN_ACFEN_AE_3 (0x0004U) +#define CAN_ACFEN_AE_4_POS (3U) +#define CAN_ACFEN_AE_4 (0x0008U) +#define CAN_ACFEN_AE_5_POS (4U) +#define CAN_ACFEN_AE_5 (0x0010U) +#define CAN_ACFEN_AE_6_POS (5U) +#define CAN_ACFEN_AE_6 (0x0020U) +#define CAN_ACFEN_AE_7_POS (6U) +#define CAN_ACFEN_AE_7 (0x0040U) +#define CAN_ACFEN_AE_8_POS (7U) +#define CAN_ACFEN_AE_8 (0x0080U) +#define CAN_ACFEN_AE_9_POS (8U) +#define CAN_ACFEN_AE_9 (0x0100U) +#define CAN_ACFEN_AE_10_POS (9U) +#define CAN_ACFEN_AE_10 (0x0200U) +#define CAN_ACFEN_AE_11_POS (10U) +#define CAN_ACFEN_AE_11 (0x0400U) +#define CAN_ACFEN_AE_12_POS (11U) +#define CAN_ACFEN_AE_12 (0x0800U) +#define CAN_ACFEN_AE_13_POS (12U) +#define CAN_ACFEN_AE_13 (0x1000U) +#define CAN_ACFEN_AE_14_POS (13U) +#define CAN_ACFEN_AE_14 (0x2000U) +#define CAN_ACFEN_AE_15_POS (14U) +#define CAN_ACFEN_AE_15 (0x4000U) +#define CAN_ACFEN_AE_16_POS (15U) +#define CAN_ACFEN_AE_16 (0x8000U) + +/* Bit definition for CAN_ACF register */ +#define CAN_ACF_ACODEORAMASK_POS (0U) +#define CAN_ACF_ACODEORAMASK (0x1FFFFFFFUL) +#define CAN_ACF_ACODEORAMASK_0 (0x00000001UL) +#define CAN_ACF_ACODEORAMASK_1 (0x00000002UL) +#define CAN_ACF_ACODEORAMASK_2 (0x00000004UL) +#define CAN_ACF_ACODEORAMASK_3 (0x00000008UL) +#define CAN_ACF_ACODEORAMASK_4 (0x00000010UL) +#define CAN_ACF_ACODEORAMASK_5 (0x00000020UL) +#define CAN_ACF_ACODEORAMASK_6 (0x00000040UL) +#define CAN_ACF_ACODEORAMASK_7 (0x00000080UL) +#define CAN_ACF_ACODEORAMASK_8 (0x00000100UL) +#define CAN_ACF_ACODEORAMASK_9 (0x00000200UL) +#define CAN_ACF_ACODEORAMASK_10 (0x00000400UL) +#define CAN_ACF_ACODEORAMASK_11 (0x00000800UL) +#define CAN_ACF_ACODEORAMASK_12 (0x00001000UL) +#define CAN_ACF_ACODEORAMASK_13 (0x00002000UL) +#define CAN_ACF_ACODEORAMASK_14 (0x00004000UL) +#define CAN_ACF_ACODEORAMASK_15 (0x00008000UL) +#define CAN_ACF_ACODEORAMASK_16 (0x00010000UL) +#define CAN_ACF_ACODEORAMASK_17 (0x00020000UL) +#define CAN_ACF_ACODEORAMASK_18 (0x00040000UL) +#define CAN_ACF_ACODEORAMASK_19 (0x00080000UL) +#define CAN_ACF_ACODEORAMASK_20 (0x00100000UL) +#define CAN_ACF_ACODEORAMASK_21 (0x00200000UL) +#define CAN_ACF_ACODEORAMASK_22 (0x00400000UL) +#define CAN_ACF_ACODEORAMASK_23 (0x00800000UL) +#define CAN_ACF_ACODEORAMASK_24 (0x01000000UL) +#define CAN_ACF_ACODEORAMASK_25 (0x02000000UL) +#define CAN_ACF_ACODEORAMASK_26 (0x04000000UL) +#define CAN_ACF_ACODEORAMASK_27 (0x08000000UL) +#define CAN_ACF_ACODEORAMASK_28 (0x10000000UL) +#define CAN_ACF_AIDE_POS (29U) +#define CAN_ACF_AIDE (0x20000000UL) +#define CAN_ACF_AIDEE_POS (30U) +#define CAN_ACF_AIDEE (0x40000000UL) + +/* Bit definition for CAN_TBSLOT register */ +#define CAN_TBSLOT_TBPTR_POS (0U) +#define CAN_TBSLOT_TBPTR (0x3FU) +#define CAN_TBSLOT_TBPTR_0 (0x01U) +#define CAN_TBSLOT_TBPTR_1 (0x02U) +#define CAN_TBSLOT_TBPTR_2 (0x04U) +#define CAN_TBSLOT_TBPTR_3 (0x08U) +#define CAN_TBSLOT_TBPTR_4 (0x10U) +#define CAN_TBSLOT_TBPTR_5 (0x20U) +#define CAN_TBSLOT_TBF_POS (6U) +#define CAN_TBSLOT_TBF (0x40U) +#define CAN_TBSLOT_TBE_POS (7U) +#define CAN_TBSLOT_TBE (0x80U) + +/* Bit definition for CAN_TTCFG register */ +#define CAN_TTCFG_TTEN_POS (0U) +#define CAN_TTCFG_TTEN (0x01U) +#define CAN_TTCFG_T_PRESC_POS (1U) +#define CAN_TTCFG_T_PRESC (0x06U) +#define CAN_TTCFG_T_PRESC_0 (0x02U) +#define CAN_TTCFG_T_PRESC_1 (0x04U) +#define CAN_TTCFG_TTIF_POS (3U) +#define CAN_TTCFG_TTIF (0x08U) +#define CAN_TTCFG_TTIE_POS (4U) +#define CAN_TTCFG_TTIE (0x10U) +#define CAN_TTCFG_TEIF_POS (5U) +#define CAN_TTCFG_TEIF (0x20U) +#define CAN_TTCFG_WTIF_POS (6U) +#define CAN_TTCFG_WTIF (0x40U) +#define CAN_TTCFG_WTIE_POS (7U) +#define CAN_TTCFG_WTIE (0x80U) + +/* Bit definition for CAN_REF_MSG register */ +#define CAN_REF_MSG_REF_ID_POS (0U) +#define CAN_REF_MSG_REF_ID (0x1FFFFFFFUL) +#define CAN_REF_MSG_REF_ID_0 (0x00000001UL) +#define CAN_REF_MSG_REF_ID_1 (0x00000002UL) +#define CAN_REF_MSG_REF_ID_2 (0x00000004UL) +#define CAN_REF_MSG_REF_ID_3 (0x00000008UL) +#define CAN_REF_MSG_REF_ID_4 (0x00000010UL) +#define CAN_REF_MSG_REF_ID_5 (0x00000020UL) +#define CAN_REF_MSG_REF_ID_6 (0x00000040UL) +#define CAN_REF_MSG_REF_ID_7 (0x00000080UL) +#define CAN_REF_MSG_REF_ID_8 (0x00000100UL) +#define CAN_REF_MSG_REF_ID_9 (0x00000200UL) +#define CAN_REF_MSG_REF_ID_10 (0x00000400UL) +#define CAN_REF_MSG_REF_ID_11 (0x00000800UL) +#define CAN_REF_MSG_REF_ID_12 (0x00001000UL) +#define CAN_REF_MSG_REF_ID_13 (0x00002000UL) +#define CAN_REF_MSG_REF_ID_14 (0x00004000UL) +#define CAN_REF_MSG_REF_ID_15 (0x00008000UL) +#define CAN_REF_MSG_REF_ID_16 (0x00010000UL) +#define CAN_REF_MSG_REF_ID_17 (0x00020000UL) +#define CAN_REF_MSG_REF_ID_18 (0x00040000UL) +#define CAN_REF_MSG_REF_ID_19 (0x00080000UL) +#define CAN_REF_MSG_REF_ID_20 (0x00100000UL) +#define CAN_REF_MSG_REF_ID_21 (0x00200000UL) +#define CAN_REF_MSG_REF_ID_22 (0x00400000UL) +#define CAN_REF_MSG_REF_ID_23 (0x00800000UL) +#define CAN_REF_MSG_REF_ID_24 (0x01000000UL) +#define CAN_REF_MSG_REF_ID_25 (0x02000000UL) +#define CAN_REF_MSG_REF_ID_26 (0x04000000UL) +#define CAN_REF_MSG_REF_ID_27 (0x08000000UL) +#define CAN_REF_MSG_REF_ID_28 (0x10000000UL) +#define CAN_REF_MSG_REF_IDE_POS (31U) +#define CAN_REF_MSG_REF_IDE (0x80000000UL) + +/* Bit definition for CAN_TRG_CFG register */ +#define CAN_TRG_CFG_TTPTR_POS (0U) +#define CAN_TRG_CFG_TTPTR (0x003FU) +#define CAN_TRG_CFG_TTPTR_0 (0x0001U) +#define CAN_TRG_CFG_TTPTR_1 (0x0002U) +#define CAN_TRG_CFG_TTPTR_2 (0x0004U) +#define CAN_TRG_CFG_TTPTR_3 (0x0008U) +#define CAN_TRG_CFG_TTPTR_4 (0x0010U) +#define CAN_TRG_CFG_TTPTR_5 (0x0020U) +#define CAN_TRG_CFG_TTYPE_POS (8U) +#define CAN_TRG_CFG_TTYPE (0x0700U) +#define CAN_TRG_CFG_TTYPE_0 (0x0100U) +#define CAN_TRG_CFG_TTYPE_1 (0x0200U) +#define CAN_TRG_CFG_TTYPE_2 (0x0400U) +#define CAN_TRG_CFG_TEW_POS (12U) +#define CAN_TRG_CFG_TEW (0xF000U) +#define CAN_TRG_CFG_TEW_0 (0x1000U) +#define CAN_TRG_CFG_TEW_1 (0x2000U) +#define CAN_TRG_CFG_TEW_2 (0x4000U) +#define CAN_TRG_CFG_TEW_3 (0x8000U) + +/* Bit definition for CAN_TT_TRIG register */ +#define CAN_TT_TRIG (0xFFFFU) + +/* Bit definition for CAN_TT_WTRIG register */ +#define CAN_TT_WTRIG (0xFFFFU) + +/******************************************************************************* + Bit definition for Peripheral CMP +*******************************************************************************/ +/* Bit definition for CMP_MDR register */ +#define CMP_MDR_CENB_POS (0U) +#define CMP_MDR_CENB (0x01U) +#define CMP_MDR_CWDE_POS (1U) +#define CMP_MDR_CWDE (0x02U) +#define CMP_MDR_CMON_POS (7U) +#define CMP_MDR_CMON (0x80U) + +/* Bit definition for CMP_FIR register */ +#define CMP_FIR_FCKS_POS (0U) +#define CMP_FIR_FCKS (0x03U) +#define CMP_FIR_FCKS_0 (0x01U) +#define CMP_FIR_FCKS_1 (0x02U) +#define CMP_FIR_EDGS_POS (4U) +#define CMP_FIR_EDGS (0x30U) +#define CMP_FIR_EDGS_0 (0x10U) +#define CMP_FIR_EDGS_1 (0x20U) +#define CMP_FIR_CIEN_POS (6U) +#define CMP_FIR_CIEN (0x40U) + +/* Bit definition for CMP_OCR register */ +#define CMP_OCR_COEN_POS (0U) +#define CMP_OCR_COEN (0x01U) +#define CMP_OCR_COPS_POS (1U) +#define CMP_OCR_COPS (0x02U) +#define CMP_OCR_CPOE_POS (2U) +#define CMP_OCR_CPOE (0x04U) +#define CMP_OCR_TWOE_POS (3U) +#define CMP_OCR_TWOE (0x08U) +#define CMP_OCR_TWOL_POS (4U) +#define CMP_OCR_TWOL (0x10U) + +/* Bit definition for CMP_PMSR register */ +#define CMP_PMSR_RVSL_POS (0U) +#define CMP_PMSR_RVSL (0x0FU) +#define CMP_PMSR_RVSL_0 (0x01U) +#define CMP_PMSR_RVSL_1 (0x02U) +#define CMP_PMSR_RVSL_2 (0x04U) +#define CMP_PMSR_RVSL_3 (0x08U) +#define CMP_PMSR_CVSL_POS (4U) +#define CMP_PMSR_CVSL (0xF0U) +#define CMP_PMSR_CVSL_0 (0x10U) +#define CMP_PMSR_CVSL_1 (0x20U) +#define CMP_PMSR_CVSL_2 (0x40U) +#define CMP_PMSR_CVSL_3 (0x80U) + +/* Bit definition for CMP_TWSR register */ +#define CMP_TWSR_CTWS0_POS (0U) +#define CMP_TWSR_CTWS0 (0x0001U) +#define CMP_TWSR_CTWS1_POS (1U) +#define CMP_TWSR_CTWS1 (0x0002U) +#define CMP_TWSR_CTWS2_POS (2U) +#define CMP_TWSR_CTWS2 (0x0004U) +#define CMP_TWSR_CTWS3_POS (3U) +#define CMP_TWSR_CTWS3 (0x0008U) +#define CMP_TWSR_CTWS4_POS (4U) +#define CMP_TWSR_CTWS4 (0x0010U) +#define CMP_TWSR_CTWS5_POS (5U) +#define CMP_TWSR_CTWS5 (0x0020U) +#define CMP_TWSR_CTWS6_POS (6U) +#define CMP_TWSR_CTWS6 (0x0040U) +#define CMP_TWSR_CTWS7_POS (7U) +#define CMP_TWSR_CTWS7 (0x0080U) +#define CMP_TWSR_CTWS8_POS (8U) +#define CMP_TWSR_CTWS8 (0x0100U) +#define CMP_TWSR_CTWS9_POS (9U) +#define CMP_TWSR_CTWS9 (0x0200U) +#define CMP_TWSR_CTWS10_POS (10U) +#define CMP_TWSR_CTWS10 (0x0400U) +#define CMP_TWSR_CTWS11_POS (11U) +#define CMP_TWSR_CTWS11 (0x0800U) +#define CMP_TWSR_CTWS12_POS (12U) +#define CMP_TWSR_CTWS12 (0x1000U) +#define CMP_TWSR_CTWS13_POS (13U) +#define CMP_TWSR_CTWS13 (0x2000U) +#define CMP_TWSR_CTWS14_POS (14U) +#define CMP_TWSR_CTWS14 (0x4000U) +#define CMP_TWSR_CTWS15_POS (15U) +#define CMP_TWSR_CTWS15 (0x8000U) + +/* Bit definition for CMP_TWPR register */ +#define CMP_TWPR_CTWP0_POS (0U) +#define CMP_TWPR_CTWP0 (0x0001U) +#define CMP_TWPR_CTWP1_POS (1U) +#define CMP_TWPR_CTWP1 (0x0002U) +#define CMP_TWPR_CTWP2_POS (2U) +#define CMP_TWPR_CTWP2 (0x0004U) +#define CMP_TWPR_CTWP3_POS (3U) +#define CMP_TWPR_CTWP3 (0x0008U) +#define CMP_TWPR_CTWP4_POS (4U) +#define CMP_TWPR_CTWP4 (0x0010U) +#define CMP_TWPR_CTWP5_POS (5U) +#define CMP_TWPR_CTWP5 (0x0020U) +#define CMP_TWPR_CTWP6_POS (6U) +#define CMP_TWPR_CTWP6 (0x0040U) +#define CMP_TWPR_CTWP7_POS (7U) +#define CMP_TWPR_CTWP7 (0x0080U) +#define CMP_TWPR_CTWP8_POS (8U) +#define CMP_TWPR_CTWP8 (0x0100U) +#define CMP_TWPR_CTWP9_POS (9U) +#define CMP_TWPR_CTWP9 (0x0200U) +#define CMP_TWPR_CTWP10_POS (10U) +#define CMP_TWPR_CTWP10 (0x0400U) +#define CMP_TWPR_CTWP11_POS (11U) +#define CMP_TWPR_CTWP11 (0x0800U) +#define CMP_TWPR_CTWP12_POS (12U) +#define CMP_TWPR_CTWP12 (0x1000U) +#define CMP_TWPR_CTWP13_POS (13U) +#define CMP_TWPR_CTWP13 (0x2000U) +#define CMP_TWPR_CTWP14_POS (14U) +#define CMP_TWPR_CTWP14 (0x4000U) +#define CMP_TWPR_CTWP15_POS (15U) +#define CMP_TWPR_CTWP15 (0x8000U) + +/* Bit definition for CMP_VISR register */ +#define CMP_VISR_P2SL_POS (0U) +#define CMP_VISR_P2SL (0x0007U) +#define CMP_VISR_P2SL_0 (0x0001U) +#define CMP_VISR_P2SL_1 (0x0002U) +#define CMP_VISR_P2SL_2 (0x0004U) +#define CMP_VISR_P3SL_POS (4U) +#define CMP_VISR_P3SL (0x0030U) +#define CMP_VISR_P3SL_0 (0x0010U) +#define CMP_VISR_P3SL_1 (0x0020U) + +/******************************************************************************* + Bit definition for Peripheral CMU +*******************************************************************************/ +/* Bit definition for CMU_XTAL32CR register */ +#define CMU_XTAL32CR_XTAL32STP (0x01U) + +/* Bit definition for CMU_XTAL32CFGR register */ +#define CMU_XTAL32CFGR_XTAL32DRV (0x07U) + +/* Bit definition for CMU_XTAL32NFR register */ +#define CMU_XTAL32NFR_XTAL32NF (0x03U) + +/* Bit definition for CMU_LRCCR register */ +#define CMU_LRCCR_LRCSTP (0x01U) + +/* Bit definition for CMU_RTCLRCCR register */ +#define CMU_RTCLRCCR_RTCLRCSTP (0x01U) + +/* Bit definition for CMU_LRCTRM register */ +#define CMU_LRCTRM (0xFFU) + +/* Bit definition for CMU_RTCLRCTRM register */ +#define CMU_RTCLRCTRM (0xFFU) + +/* Bit definition for CMU_XTALCFGR register */ +#define CMU_XTALCFGR_XTALDRV_POS (4U) +#define CMU_XTALCFGR_XTALDRV (0x30U) +#define CMU_XTALCFGR_XTALMS_POS (6U) +#define CMU_XTALCFGR_XTALMS (0x40U) + +/* Bit definition for CMU_PERICKSEL register */ +#define CMU_PERICKSEL_PERICKSEL (0x000FU) + +/* Bit definition for CMU_I2SCKSEL register */ +#define CMU_I2SCKSEL_I2S1CKSEL_POS (0U) +#define CMU_I2SCKSEL_I2S1CKSEL (0x000FU) +#define CMU_I2SCKSEL_I2S2CKSEL_POS (4U) +#define CMU_I2SCKSEL_I2S2CKSEL (0x00F0U) +#define CMU_I2SCKSEL_I2S3CKSEL_POS (8U) +#define CMU_I2SCKSEL_I2S3CKSEL (0x0F00U) +#define CMU_I2SCKSEL_I2S4CKSEL_POS (12U) +#define CMU_I2SCKSEL_I2S4CKSEL (0xF000U) + +/* Bit definition for CMU_CANCKCFGR register */ +#define CMU_CANCKCFGR_CAN1CKS_POS (0U) +#define CMU_CANCKCFGR_CAN1CKS (0x0FU) +#define CMU_CANCKCFGR_CAN2CKS_POS (4U) +#define CMU_CANCKCFGR_CAN2CKS (0xF0U) + +/* Bit definition for CMU_SCFGR register */ +#define CMU_SCFGR_PCLK0S_POS (0U) +#define CMU_SCFGR_PCLK0S (0x00000007UL) +#define CMU_SCFGR_PCLK1S_POS (4U) +#define CMU_SCFGR_PCLK1S (0x00000070UL) +#define CMU_SCFGR_PCLK2S_POS (8U) +#define CMU_SCFGR_PCLK2S (0x00000700UL) +#define CMU_SCFGR_PCLK3S_POS (12U) +#define CMU_SCFGR_PCLK3S (0x00007000UL) +#define CMU_SCFGR_PCLK4S_POS (16U) +#define CMU_SCFGR_PCLK4S (0x00070000UL) +#define CMU_SCFGR_EXCKS_POS (20U) +#define CMU_SCFGR_EXCKS (0x00700000UL) +#define CMU_SCFGR_HCLKS_POS (24U) +#define CMU_SCFGR_HCLKS (0x07000000UL) + +/* Bit definition for CMU_USBCKCFGR register */ +#define CMU_USBCKCFGR_USBCKS_POS (4U) +#define CMU_USBCKCFGR_USBCKS (0xF0U) + +/* Bit definition for CMU_CKSWR register */ +#define CMU_CKSWR_CKSW (0x07U) + +/* Bit definition for CMU_PLLHCR register */ +#define CMU_PLLHCR_PLLHOFF (0x01U) + +/* Bit definition for CMU_PLLACR register */ +#define CMU_PLLACR_PLLAOFF (0x01U) + +/* Bit definition for CMU_XTALCR register */ +#define CMU_XTALCR_XTALSTP (0x01U) + +/* Bit definition for CMU_HRCCR register */ +#define CMU_HRCCR_HRCSTP (0x01U) + +/* Bit definition for CMU_MRCCR register */ +#define CMU_MRCCR_MRCSTP (0x01U) + +/* Bit definition for CMU_OSCSTBSR register */ +#define CMU_OSCSTBSR_HRCSTBF_POS (0U) +#define CMU_OSCSTBSR_HRCSTBF (0x01U) +#define CMU_OSCSTBSR_XTALSTBF_POS (3U) +#define CMU_OSCSTBSR_XTALSTBF (0x08U) +#define CMU_OSCSTBSR_PLLHSTBF_POS (5U) +#define CMU_OSCSTBSR_PLLHSTBF (0x20U) +#define CMU_OSCSTBSR_PLLASTBF_POS (6U) +#define CMU_OSCSTBSR_PLLASTBF (0x40U) +#define CMU_OSCSTBSR_PLLBSTBF_POS (7U) +#define CMU_OSCSTBSR_PLLBSTBF (0x80U) + +/* Bit definition for CMU_MCO1CFGR register */ +#define CMU_MCO1CFGR_MCO1SEL_POS (0U) +#define CMU_MCO1CFGR_MCO1SEL (0x0FU) +#define CMU_MCO1CFGR_MCO1DIV_POS (4U) +#define CMU_MCO1CFGR_MCO1DIV (0x70U) +#define CMU_MCO1CFGR_MCO1EN_POS (7U) +#define CMU_MCO1CFGR_MCO1EN (0x80U) + +/* Bit definition for CMU_MCO2CFGR register */ +#define CMU_MCO2CFGR_MCO2SEL_POS (0U) +#define CMU_MCO2CFGR_MCO2SEL (0x0FU) +#define CMU_MCO2CFGR_MCO2DIV_POS (4U) +#define CMU_MCO2CFGR_MCO2DIV (0x70U) +#define CMU_MCO2CFGR_MCO2EN_POS (7U) +#define CMU_MCO2CFGR_MCO2EN (0x80U) + +/* Bit definition for CMU_TPIUCKCFGR register */ +#define CMU_TPIUCKCFGR_TPIUCKS_POS (0U) +#define CMU_TPIUCKCFGR_TPIUCKS (0x03U) +#define CMU_TPIUCKCFGR_TPIUCKOE_POS (7U) +#define CMU_TPIUCKCFGR_TPIUCKOE (0x80U) + +/* Bit definition for CMU_XTALSTDCR register */ +#define CMU_XTALSTDCR_XTALSTDIE_POS (0U) +#define CMU_XTALSTDCR_XTALSTDIE (0x01U) +#define CMU_XTALSTDCR_XTALSTDRE_POS (1U) +#define CMU_XTALSTDCR_XTALSTDRE (0x02U) +#define CMU_XTALSTDCR_XTALSTDRIS_POS (2U) +#define CMU_XTALSTDCR_XTALSTDRIS (0x04U) +#define CMU_XTALSTDCR_XTALSTDE_POS (7U) +#define CMU_XTALSTDCR_XTALSTDE (0x80U) + +/* Bit definition for CMU_XTALSTDSR register */ +#define CMU_XTALSTDSR_XTALSTDF (0x01U) + +/* Bit definition for CMU_MRCTRM register */ +#define CMU_MRCTRM (0xFFU) + +/* Bit definition for CMU_HRCTRM register */ +#define CMU_HRCTRM (0xFFU) + +/* Bit definition for CMU_XTALSTBCR register */ +#define CMU_XTALSTBCR_XTALSTB (0x0FU) + +/* Bit definition for CMU_PLLHCFGR register */ +#define CMU_PLLHCFGR_PLLHM_POS (0U) +#define CMU_PLLHCFGR_PLLHM (0x00000003UL) +#define CMU_PLLHCFGR_PLLSRC_POS (7U) +#define CMU_PLLHCFGR_PLLSRC (0x00000080UL) +#define CMU_PLLHCFGR_PLLHN_POS (8U) +#define CMU_PLLHCFGR_PLLHN (0x0001FF00UL) +#define CMU_PLLHCFGR_PLLHR_POS (20U) +#define CMU_PLLHCFGR_PLLHR (0x00F00000UL) +#define CMU_PLLHCFGR_PLLHQ_POS (24U) +#define CMU_PLLHCFGR_PLLHQ (0x0F000000UL) +#define CMU_PLLHCFGR_PLLHP_POS (28U) +#define CMU_PLLHCFGR_PLLHP (0xF0000000UL) + +/* Bit definition for CMU_PLLACFGR register */ +#define CMU_PLLACFGR_PLLAM_POS (0U) +#define CMU_PLLACFGR_PLLAM (0x0000001FUL) +#define CMU_PLLACFGR_PLLAN_POS (8U) +#define CMU_PLLACFGR_PLLAN (0x0001FF00UL) +#define CMU_PLLACFGR_PLLAR_POS (20U) +#define CMU_PLLACFGR_PLLAR (0x00F00000UL) +#define CMU_PLLACFGR_PLLAQ_POS (24U) +#define CMU_PLLACFGR_PLLAQ (0x0F000000UL) +#define CMU_PLLACFGR_PLLAP_POS (28U) +#define CMU_PLLACFGR_PLLAP (0xF0000000UL) + +/******************************************************************************* + Bit definition for Peripheral CRC +*******************************************************************************/ +/* Bit definition for CRC_CR register */ +#define CRC_CR_CR_POS (0U) +#define CRC_CR_CR (0x00000001UL) +#define CRC_CR_FLAG_POS (1U) +#define CRC_CR_FLAG (0x00000002UL) + +/* Bit definition for CRC_RESLT register */ +#define CRC_RESLT (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT0 register */ +#define CRC_DAT0 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT1 register */ +#define CRC_DAT1 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT2 register */ +#define CRC_DAT2 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT3 register */ +#define CRC_DAT3 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT4 register */ +#define CRC_DAT4 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT5 register */ +#define CRC_DAT5 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT6 register */ +#define CRC_DAT6 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT7 register */ +#define CRC_DAT7 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT8 register */ +#define CRC_DAT8 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT9 register */ +#define CRC_DAT9 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT10 register */ +#define CRC_DAT10 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT11 register */ +#define CRC_DAT11 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT12 register */ +#define CRC_DAT12 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT13 register */ +#define CRC_DAT13 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT14 register */ +#define CRC_DAT14 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT15 register */ +#define CRC_DAT15 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT16 register */ +#define CRC_DAT16 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT17 register */ +#define CRC_DAT17 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT18 register */ +#define CRC_DAT18 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT19 register */ +#define CRC_DAT19 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT20 register */ +#define CRC_DAT20 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT21 register */ +#define CRC_DAT21 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT22 register */ +#define CRC_DAT22 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT23 register */ +#define CRC_DAT23 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT24 register */ +#define CRC_DAT24 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT25 register */ +#define CRC_DAT25 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT26 register */ +#define CRC_DAT26 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT27 register */ +#define CRC_DAT27 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT28 register */ +#define CRC_DAT28 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT29 register */ +#define CRC_DAT29 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT30 register */ +#define CRC_DAT30 (0xFFFFFFFFUL) + +/* Bit definition for CRC_DAT31 register */ +#define CRC_DAT31 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral CTC +*******************************************************************************/ +/* Bit definition for CTC_CR1 register */ +#define CTC_CR1_REFPSC_POS (0U) +#define CTC_CR1_REFPSC (0x00000007UL) +#define CTC_CR1_REFPSC_0 (0x00000001UL) +#define CTC_CR1_REFPSC_1 (0x00000002UL) +#define CTC_CR1_REFPSC_2 (0x00000004UL) +#define CTC_CR1_REFCKS_POS (4U) +#define CTC_CR1_REFCKS (0x00000030UL) +#define CTC_CR1_REFCKS_0 (0x00000010UL) +#define CTC_CR1_REFCKS_1 (0x00000020UL) +#define CTC_CR1_ERRIE_POS (6U) +#define CTC_CR1_ERRIE (0x00000040UL) +#define CTC_CR1_CTCEN_POS (7U) +#define CTC_CR1_CTCEN (0x00000080UL) +#define CTC_CR1_TRMVAL_POS (16U) +#define CTC_CR1_TRMVAL (0x003F0000UL) + +/* Bit definition for CTC_CR2 register */ +#define CTC_CR2_OFSVAL_POS (0U) +#define CTC_CR2_OFSVAL (0x000000FFUL) +#define CTC_CR2_OFSVAL_0 (0x00000001UL) +#define CTC_CR2_OFSVAL_1 (0x00000002UL) +#define CTC_CR2_OFSVAL_2 (0x00000004UL) +#define CTC_CR2_OFSVAL_3 (0x00000008UL) +#define CTC_CR2_OFSVAL_4 (0x00000010UL) +#define CTC_CR2_OFSVAL_5 (0x00000020UL) +#define CTC_CR2_OFSVAL_6 (0x00000040UL) +#define CTC_CR2_OFSVAL_7 (0x00000080UL) +#define CTC_CR2_RLDVAL_POS (16U) +#define CTC_CR2_RLDVAL (0xFFFF0000UL) + +/* Bit definition for CTC_STR register */ +#define CTC_STR_TRIMOK_POS (0U) +#define CTC_STR_TRIMOK (0x00000001UL) +#define CTC_STR_TRMOVF_POS (1U) +#define CTC_STR_TRMOVF (0x00000002UL) +#define CTC_STR_TRMUDF_POS (2U) +#define CTC_STR_TRMUDF (0x00000004UL) +#define CTC_STR_CTCBSY_POS (3U) +#define CTC_STR_CTCBSY (0x00000008UL) + +/******************************************************************************* + Bit definition for Peripheral DAC +*******************************************************************************/ +/* Bit definition for DAC_DADR1 register */ +#define DAC_DADR1_DR0_POS (0U) +#define DAC_DADR1_DR0 (0x0001U) +#define DAC_DADR1_DR1_POS (1U) +#define DAC_DADR1_DR1 (0x0002U) +#define DAC_DADR1_DR2_POS (2U) +#define DAC_DADR1_DR2 (0x0004U) +#define DAC_DADR1_DR3_POS (3U) +#define DAC_DADR1_DR3 (0x0008U) +#define DAC_DADR1_DL0R4_POS (4U) +#define DAC_DADR1_DL0R4 (0x0010U) +#define DAC_DADR1_DL1R5_POS (5U) +#define DAC_DADR1_DL1R5 (0x0020U) +#define DAC_DADR1_DL2R6_POS (6U) +#define DAC_DADR1_DL2R6 (0x0040U) +#define DAC_DADR1_DL3R7_POS (7U) +#define DAC_DADR1_DL3R7 (0x0080U) +#define DAC_DADR1_DL4R8_POS (8U) +#define DAC_DADR1_DL4R8 (0x0100U) +#define DAC_DADR1_DL5R9_POS (9U) +#define DAC_DADR1_DL5R9 (0x0200U) +#define DAC_DADR1_DL6R10_POS (10U) +#define DAC_DADR1_DL6R10 (0x0400U) +#define DAC_DADR1_DL7R11_POS (11U) +#define DAC_DADR1_DL7R11 (0x0800U) +#define DAC_DADR1_DL8_POS (12U) +#define DAC_DADR1_DL8 (0x1000U) +#define DAC_DADR1_DL9_POS (13U) +#define DAC_DADR1_DL9 (0x2000U) +#define DAC_DADR1_DL10_POS (14U) +#define DAC_DADR1_DL10 (0x4000U) +#define DAC_DADR1_DL11_POS (15U) +#define DAC_DADR1_DL11 (0x8000U) + +/* Bit definition for DAC_DADR2 register */ +#define DAC_DADR2_DR0_POS (0U) +#define DAC_DADR2_DR0 (0x0001U) +#define DAC_DADR2_DR1_POS (1U) +#define DAC_DADR2_DR1 (0x0002U) +#define DAC_DADR2_DR2_POS (2U) +#define DAC_DADR2_DR2 (0x0004U) +#define DAC_DADR2_DR3_POS (3U) +#define DAC_DADR2_DR3 (0x0008U) +#define DAC_DADR2_DL0R4_POS (4U) +#define DAC_DADR2_DL0R4 (0x0010U) +#define DAC_DADR2_DL1R5_POS (5U) +#define DAC_DADR2_DL1R5 (0x0020U) +#define DAC_DADR2_DL2R6_POS (6U) +#define DAC_DADR2_DL2R6 (0x0040U) +#define DAC_DADR2_DL3R7_POS (7U) +#define DAC_DADR2_DL3R7 (0x0080U) +#define DAC_DADR2_DL4R8_POS (8U) +#define DAC_DADR2_DL4R8 (0x0100U) +#define DAC_DADR2_DL5R9_POS (9U) +#define DAC_DADR2_DL5R9 (0x0200U) +#define DAC_DADR2_DL6R10_POS (10U) +#define DAC_DADR2_DL6R10 (0x0400U) +#define DAC_DADR2_DL7R11_POS (11U) +#define DAC_DADR2_DL7R11 (0x0800U) +#define DAC_DADR2_DL8_POS (12U) +#define DAC_DADR2_DL8 (0x1000U) +#define DAC_DADR2_DL9_POS (13U) +#define DAC_DADR2_DL9 (0x2000U) +#define DAC_DADR2_DL10_POS (14U) +#define DAC_DADR2_DL10 (0x4000U) +#define DAC_DADR2_DL11_POS (15U) +#define DAC_DADR2_DL11 (0x8000U) + +/* Bit definition for DAC_DACR register */ +#define DAC_DACR_DAE_POS (0U) +#define DAC_DACR_DAE (0x0001U) +#define DAC_DACR_DA1E_POS (1U) +#define DAC_DACR_DA1E (0x0002U) +#define DAC_DACR_DA2E_POS (2U) +#define DAC_DACR_DA2E (0x0004U) +#define DAC_DACR_DPSEL_POS (8U) +#define DAC_DACR_DPSEL (0x0100U) +#define DAC_DACR_DAAMP1_POS (9U) +#define DAC_DACR_DAAMP1 (0x0200U) +#define DAC_DACR_DAAMP2_POS (10U) +#define DAC_DACR_DAAMP2 (0x0400U) +#define DAC_DACR_EXTDSL1_POS (11U) +#define DAC_DACR_EXTDSL1 (0x0800U) +#define DAC_DACR_EXTDSL2_POS (12U) +#define DAC_DACR_EXTDSL2 (0x1000U) + +/* Bit definition for DAC_DAADPCR register */ +#define DAC_DAADPCR_ADPSL1_POS (0U) +#define DAC_DAADPCR_ADPSL1 (0x0001U) +#define DAC_DAADPCR_ADPSL2_POS (1U) +#define DAC_DAADPCR_ADPSL2 (0x0002U) +#define DAC_DAADPCR_ADPSL3_POS (2U) +#define DAC_DAADPCR_ADPSL3 (0x0004U) +#define DAC_DAADPCR_DA1SF_POS (8U) +#define DAC_DAADPCR_DA1SF (0x0100U) +#define DAC_DAADPCR_DA2SF_POS (9U) +#define DAC_DAADPCR_DA2SF (0x0200U) +#define DAC_DAADPCR_ADPEN_POS (15U) +#define DAC_DAADPCR_ADPEN (0x8000U) + +/* Bit definition for DAC_DAOCR register */ +#define DAC_DAOCR_DAODIS1_POS (14U) +#define DAC_DAOCR_DAODIS1 (0x4000U) +#define DAC_DAOCR_DAODIS2_POS (15U) +#define DAC_DAOCR_DAODIS2 (0x8000U) + +/******************************************************************************* + Bit definition for Peripheral DBGC +*******************************************************************************/ +/* Bit definition for DBGC_AUTHID0 register */ +#define DBGC_AUTHID0 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID1 register */ +#define DBGC_AUTHID1 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_AUTHID2 register */ +#define DBGC_AUTHID2 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_RESV0 register */ +#define DBGC_RESV0 (0xFFFFFFFFUL) + +/* Bit definition for DBGC_MCUSTAT register */ +#define DBGC_MCUSTAT_AUTH_POS (0U) +#define DBGC_MCUSTAT_AUTH (0x00000001UL) +#define DBGC_MCUSTAT_REMVLOCK_POS (1U) +#define DBGC_MCUSTAT_REMVLOCK (0x00000002UL) +#define DBGC_MCUSTAT_SAFTYLOCK1_POS (2U) +#define DBGC_MCUSTAT_SAFTYLOCK1 (0x00000004UL) +#define DBGC_MCUSTAT_SAFTYLOCK2_POS (3U) +#define DBGC_MCUSTAT_SAFTYLOCK2 (0x00000008UL) +#define DBGC_MCUSTAT_CPUSTOP_POS (8U) +#define DBGC_MCUSTAT_CPUSTOP (0x00000100UL) +#define DBGC_MCUSTAT_CPUSLEEP_POS (9U) +#define DBGC_MCUSTAT_CPUSLEEP (0x00000200UL) + +/* Bit definition for DBGC_MCUCTL register */ +#define DBGC_MCUCTL_EDBGRQ_POS (0U) +#define DBGC_MCUCTL_EDBGRQ (0x00000001UL) +#define DBGC_MCUCTL_RESTART_POS (1U) +#define DBGC_MCUCTL_RESTART (0x00000002UL) +#define DBGC_MCUCTL_DIRQ_POS (8U) +#define DBGC_MCUCTL_DIRQ (0x00000100UL) + +/* Bit definition for DBGC_FMCCTL register */ +#define DBGC_FMCCTL_ERASEREQ_POS (0U) +#define DBGC_FMCCTL_ERASEREQ (0x00000001UL) +#define DBGC_FMCCTL_ERASEACK_POS (1U) +#define DBGC_FMCCTL_ERASEACK (0x00000002UL) +#define DBGC_FMCCTL_ERASEERR_POS (2U) +#define DBGC_FMCCTL_ERASEERR (0x00000004UL) + +/* Bit definition for DBGC_MCUDBGCSTAT register */ +#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ_POS (0U) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPREQ (0x00000001UL) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK_POS (1U) +#define DBGC_MCUDBGCSTAT_CDBGPWRUPACK (0x00000002UL) + +/* Bit definition for DBGC_MCUSTPCTL register */ +#define DBGC_MCUSTPCTL_SWDTSTP_POS (0U) +#define DBGC_MCUSTPCTL_SWDTSTP (0x00000001UL) +#define DBGC_MCUSTPCTL_WDTSTP_POS (1U) +#define DBGC_MCUSTPCTL_WDTSTP (0x00000002UL) +#define DBGC_MCUSTPCTL_RTCSTP_POS (2U) +#define DBGC_MCUSTPCTL_RTCSTP (0x00000004UL) +#define DBGC_MCUSTPCTL_PVD0STP_POS (3U) +#define DBGC_MCUSTPCTL_PVD0STP (0x00000008UL) +#define DBGC_MCUSTPCTL_PVD1STP_POS (4U) +#define DBGC_MCUSTPCTL_PVD1STP (0x00000010UL) +#define DBGC_MCUSTPCTL_PVD2STP_POS (5U) +#define DBGC_MCUSTPCTL_PVD2STP (0x00000020UL) +#define DBGC_MCUSTPCTL_M06STP_POS (6U) +#define DBGC_MCUSTPCTL_M06STP (0x00000040UL) +#define DBGC_MCUSTPCTL_M07STP_POS (7U) +#define DBGC_MCUSTPCTL_M07STP (0x00000080UL) +#define DBGC_MCUSTPCTL_M08STP_POS (8U) +#define DBGC_MCUSTPCTL_M08STP (0x00000100UL) +#define DBGC_MCUSTPCTL_M09STP_POS (9U) +#define DBGC_MCUSTPCTL_M09STP (0x00000200UL) +#define DBGC_MCUSTPCTL_M10STP_POS (10U) +#define DBGC_MCUSTPCTL_M10STP (0x00000400UL) +#define DBGC_MCUSTPCTL_M11STP_POS (11U) +#define DBGC_MCUSTPCTL_M11STP (0x00000800UL) +#define DBGC_MCUSTPCTL_M12STP_POS (12U) +#define DBGC_MCUSTPCTL_M12STP (0x00001000UL) +#define DBGC_MCUSTPCTL_M13STP_POS (13U) +#define DBGC_MCUSTPCTL_M13STP (0x00002000UL) +#define DBGC_MCUSTPCTL_M14STP_POS (14U) +#define DBGC_MCUSTPCTL_M14STP (0x00004000UL) +#define DBGC_MCUSTPCTL_M15STP_POS (15U) +#define DBGC_MCUSTPCTL_M15STP (0x00008000UL) +#define DBGC_MCUSTPCTL_M16STP_POS (16U) +#define DBGC_MCUSTPCTL_M16STP (0x00010000UL) +#define DBGC_MCUSTPCTL_M17STP_POS (17U) +#define DBGC_MCUSTPCTL_M17STP (0x00020000UL) +#define DBGC_MCUSTPCTL_M18STP_POS (18U) +#define DBGC_MCUSTPCTL_M18STP (0x00040000UL) +#define DBGC_MCUSTPCTL_M19STP_POS (19U) +#define DBGC_MCUSTPCTL_M19STP (0x00080000UL) +#define DBGC_MCUSTPCTL_M20STP_POS (20U) +#define DBGC_MCUSTPCTL_M20STP (0x00100000UL) +#define DBGC_MCUSTPCTL_M21STP_POS (21U) +#define DBGC_MCUSTPCTL_M21STP (0x00200000UL) +#define DBGC_MCUSTPCTL_M22STP_POS (22U) +#define DBGC_MCUSTPCTL_M22STP (0x00400000UL) +#define DBGC_MCUSTPCTL_M23STP_POS (23U) +#define DBGC_MCUSTPCTL_M23STP (0x00800000UL) +#define DBGC_MCUSTPCTL_M24STP_POS (24U) +#define DBGC_MCUSTPCTL_M24STP (0x01000000UL) +#define DBGC_MCUSTPCTL_M25STP_POS (25U) +#define DBGC_MCUSTPCTL_M25STP (0x02000000UL) +#define DBGC_MCUSTPCTL_M26STP_POS (26U) +#define DBGC_MCUSTPCTL_M26STP (0x04000000UL) +#define DBGC_MCUSTPCTL_M27STP_POS (27U) +#define DBGC_MCUSTPCTL_M27STP (0x08000000UL) +#define DBGC_MCUSTPCTL_M28STP_POS (28U) +#define DBGC_MCUSTPCTL_M28STP (0x10000000UL) +#define DBGC_MCUSTPCTL_M29STP_POS (29U) +#define DBGC_MCUSTPCTL_M29STP (0x20000000UL) +#define DBGC_MCUSTPCTL_M30STP_POS (30U) +#define DBGC_MCUSTPCTL_M30STP (0x40000000UL) +#define DBGC_MCUSTPCTL_M31STP_POS (31U) +#define DBGC_MCUSTPCTL_M31STP (0x80000000UL) + +/* Bit definition for DBGC_MCUTRACECTL register */ +#define DBGC_MCUTRACECTL_TRACEMODE_POS (0U) +#define DBGC_MCUTRACECTL_TRACEMODE (0x00000003UL) +#define DBGC_MCUTRACECTL_TRACEIOEN_POS (2U) +#define DBGC_MCUTRACECTL_TRACEIOEN (0x00000004UL) + +/* Bit definition for DBGC_MCUSTPCTL2 register */ +#define DBGC_MCUSTPCTL2_M32STP_POS (0U) +#define DBGC_MCUSTPCTL2_M32STP (0x00000001UL) +#define DBGC_MCUSTPCTL2_M33STP_POS (1U) +#define DBGC_MCUSTPCTL2_M33STP (0x00000002UL) +#define DBGC_MCUSTPCTL2_M34STP_POS (2U) +#define DBGC_MCUSTPCTL2_M34STP (0x00000004UL) +#define DBGC_MCUSTPCTL2_M35STP_POS (3U) +#define DBGC_MCUSTPCTL2_M35STP (0x00000008UL) +#define DBGC_MCUSTPCTL2_M36STP_POS (4U) +#define DBGC_MCUSTPCTL2_M36STP (0x00000010UL) +#define DBGC_MCUSTPCTL2_M37STP_POS (5U) +#define DBGC_MCUSTPCTL2_M37STP (0x00000020UL) +#define DBGC_MCUSTPCTL2_M38STP_POS (6U) +#define DBGC_MCUSTPCTL2_M38STP (0x00000040UL) +#define DBGC_MCUSTPCTL2_M39STP_POS (7U) +#define DBGC_MCUSTPCTL2_M39STP (0x00000080UL) +#define DBGC_MCUSTPCTL2_M40STP_POS (8U) +#define DBGC_MCUSTPCTL2_M40STP (0x00000100UL) +#define DBGC_MCUSTPCTL2_M41STP_POS (9U) +#define DBGC_MCUSTPCTL2_M41STP (0x00000200UL) +#define DBGC_MCUSTPCTL2_M42STP_POS (10U) +#define DBGC_MCUSTPCTL2_M42STP (0x00000400UL) +#define DBGC_MCUSTPCTL2_M43STP_POS (11U) +#define DBGC_MCUSTPCTL2_M43STP (0x00000800UL) +#define DBGC_MCUSTPCTL2_M44STP_POS (12U) +#define DBGC_MCUSTPCTL2_M44STP (0x00001000UL) +#define DBGC_MCUSTPCTL2_M45STP_POS (13U) +#define DBGC_MCUSTPCTL2_M45STP (0x00002000UL) +#define DBGC_MCUSTPCTL2_M46STP_POS (14U) +#define DBGC_MCUSTPCTL2_M46STP (0x00004000UL) +#define DBGC_MCUSTPCTL2_M47STP_POS (15U) +#define DBGC_MCUSTPCTL2_M47STP (0x00008000UL) +#define DBGC_MCUSTPCTL2_M48STP_POS (16U) +#define DBGC_MCUSTPCTL2_M48STP (0x00010000UL) +#define DBGC_MCUSTPCTL2_M49STP_POS (17U) +#define DBGC_MCUSTPCTL2_M49STP (0x00020000UL) +#define DBGC_MCUSTPCTL2_M50STP_POS (18U) +#define DBGC_MCUSTPCTL2_M50STP (0x00040000UL) +#define DBGC_MCUSTPCTL2_M51STP_POS (19U) +#define DBGC_MCUSTPCTL2_M51STP (0x00080000UL) +#define DBGC_MCUSTPCTL2_M52STP_POS (20U) +#define DBGC_MCUSTPCTL2_M52STP (0x00100000UL) +#define DBGC_MCUSTPCTL2_M53STP_POS (21U) +#define DBGC_MCUSTPCTL2_M53STP (0x00200000UL) +#define DBGC_MCUSTPCTL2_M54STP_POS (22U) +#define DBGC_MCUSTPCTL2_M54STP (0x00400000UL) +#define DBGC_MCUSTPCTL2_M55STP_POS (23U) +#define DBGC_MCUSTPCTL2_M55STP (0x00800000UL) +#define DBGC_MCUSTPCTL2_M56STP_POS (24U) +#define DBGC_MCUSTPCTL2_M56STP (0x01000000UL) +#define DBGC_MCUSTPCTL2_M57STP_POS (25U) +#define DBGC_MCUSTPCTL2_M57STP (0x02000000UL) +#define DBGC_MCUSTPCTL2_M58STP_POS (26U) +#define DBGC_MCUSTPCTL2_M58STP (0x04000000UL) +#define DBGC_MCUSTPCTL2_M59STP_POS (27U) +#define DBGC_MCUSTPCTL2_M59STP (0x08000000UL) +#define DBGC_MCUSTPCTL2_M60STP_POS (28U) +#define DBGC_MCUSTPCTL2_M60STP (0x10000000UL) +#define DBGC_MCUSTPCTL2_M61STP_POS (29U) +#define DBGC_MCUSTPCTL2_M61STP (0x20000000UL) +#define DBGC_MCUSTPCTL2_M62STP_POS (30U) +#define DBGC_MCUSTPCTL2_M62STP (0x40000000UL) +#define DBGC_MCUSTPCTL2_M63STP_POS (31U) +#define DBGC_MCUSTPCTL2_M63STP (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral DCU +*******************************************************************************/ +/* Bit definition for DCU_CTL register */ +#define DCU_CTL_MODE_POS (0U) +#define DCU_CTL_MODE (0x0000000FUL) +#define DCU_CTL_MODE_0 (0x00000001UL) +#define DCU_CTL_MODE_1 (0x00000002UL) +#define DCU_CTL_MODE_2 (0x00000004UL) +#define DCU_CTL_MODE_3 (0x00000008UL) +#define DCU_CTL_DATASIZE_POS (4U) +#define DCU_CTL_DATASIZE (0x00000030UL) +#define DCU_CTL_DATASIZE_0 (0x00000010UL) +#define DCU_CTL_DATASIZE_1 (0x00000020UL) +#define DCU_CTL_COMP_TRG_POS (8U) +#define DCU_CTL_COMP_TRG (0x00000100UL) +#define DCU_CTL_INTEN_POS (31U) +#define DCU_CTL_INTEN (0x80000000UL) + +/* Bit definition for DCU_FLAG register */ +#define DCU_FLAG_FLAG_OP_POS (0U) +#define DCU_FLAG_FLAG_OP (0x00000001UL) +#define DCU_FLAG_FLAG_LS2_POS (1U) +#define DCU_FLAG_FLAG_LS2 (0x00000002UL) +#define DCU_FLAG_FLAG_EQ2_POS (2U) +#define DCU_FLAG_FLAG_EQ2 (0x00000004UL) +#define DCU_FLAG_FLAG_GT2_POS (3U) +#define DCU_FLAG_FLAG_GT2 (0x00000008UL) +#define DCU_FLAG_FLAG_LS1_POS (4U) +#define DCU_FLAG_FLAG_LS1 (0x00000010UL) +#define DCU_FLAG_FLAG_EQ1_POS (5U) +#define DCU_FLAG_FLAG_EQ1 (0x00000020UL) +#define DCU_FLAG_FLAG_GT1_POS (6U) +#define DCU_FLAG_FLAG_GT1 (0x00000040UL) +#define DCU_FLAG_FLAG_RLD_POS (9U) +#define DCU_FLAG_FLAG_RLD (0x00000200UL) +#define DCU_FLAG_FLAG_BTM_POS (10U) +#define DCU_FLAG_FLAG_BTM (0x00000400UL) +#define DCU_FLAG_FLAG_TOP_POS (11U) +#define DCU_FLAG_FLAG_TOP (0x00000800UL) + +/* Bit definition for DCU_DATA0 register */ +#define DCU_DATA0 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA1 register */ +#define DCU_DATA1 (0xFFFFFFFFUL) + +/* Bit definition for DCU_DATA2 register */ +#define DCU_DATA2 (0xFFFFFFFFUL) + +/* Bit definition for DCU_FLAGCLR register */ +#define DCU_FLAGCLR_CLR_OP_POS (0U) +#define DCU_FLAGCLR_CLR_OP (0x00000001UL) +#define DCU_FLAGCLR_CLR_LS2_POS (1U) +#define DCU_FLAGCLR_CLR_LS2 (0x00000002UL) +#define DCU_FLAGCLR_CLR_EQ2_POS (2U) +#define DCU_FLAGCLR_CLR_EQ2 (0x00000004UL) +#define DCU_FLAGCLR_CLR_GT2_POS (3U) +#define DCU_FLAGCLR_CLR_GT2 (0x00000008UL) +#define DCU_FLAGCLR_CLR_LS1_POS (4U) +#define DCU_FLAGCLR_CLR_LS1 (0x00000010UL) +#define DCU_FLAGCLR_CLR_EQ1_POS (5U) +#define DCU_FLAGCLR_CLR_EQ1 (0x00000020UL) +#define DCU_FLAGCLR_CLR_GT1_POS (6U) +#define DCU_FLAGCLR_CLR_GT1 (0x00000040UL) +#define DCU_FLAGCLR_CLR_RLD_POS (9U) +#define DCU_FLAGCLR_CLR_RLD (0x00000200UL) +#define DCU_FLAGCLR_CLR_BTM_POS (10U) +#define DCU_FLAGCLR_CLR_BTM (0x00000400UL) +#define DCU_FLAGCLR_CLR_TOP_POS (11U) +#define DCU_FLAGCLR_CLR_TOP (0x00000800UL) + +/* Bit definition for DCU_INTEVTSEL register */ +#define DCU_INTEVTSEL_SEL_OP_POS (0U) +#define DCU_INTEVTSEL_SEL_OP (0x00000001UL) +#define DCU_INTEVTSEL_SEL_LS2_POS (1U) +#define DCU_INTEVTSEL_SEL_LS2 (0x00000002UL) +#define DCU_INTEVTSEL_SEL_EQ2_POS (2U) +#define DCU_INTEVTSEL_SEL_EQ2 (0x00000004UL) +#define DCU_INTEVTSEL_SEL_GT2_POS (3U) +#define DCU_INTEVTSEL_SEL_GT2 (0x00000008UL) +#define DCU_INTEVTSEL_SEL_LS1_POS (4U) +#define DCU_INTEVTSEL_SEL_LS1 (0x00000010UL) +#define DCU_INTEVTSEL_SEL_EQ1_POS (5U) +#define DCU_INTEVTSEL_SEL_EQ1 (0x00000020UL) +#define DCU_INTEVTSEL_SEL_GT1_POS (6U) +#define DCU_INTEVTSEL_SEL_GT1 (0x00000040UL) +#define DCU_INTEVTSEL_SEL_WIN_POS (7U) +#define DCU_INTEVTSEL_SEL_WIN (0x00000180UL) +#define DCU_INTEVTSEL_SEL_WIN_0 (0x00000080UL) +#define DCU_INTEVTSEL_SEL_WIN_1 (0x00000100UL) +#define DCU_INTEVTSEL_SEL_RLD_POS (9U) +#define DCU_INTEVTSEL_SEL_RLD (0x00000200UL) +#define DCU_INTEVTSEL_SEL_BTM_POS (10U) +#define DCU_INTEVTSEL_SEL_BTM (0x00000400UL) +#define DCU_INTEVTSEL_SEL_TOP_POS (11U) +#define DCU_INTEVTSEL_SEL_TOP (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral DMA +*******************************************************************************/ +/* Bit definition for DMA_EN register */ +#define DMA_EN_EN (0x00000001UL) + +/* Bit definition for DMA_INTSTAT0 register */ +#define DMA_INTSTAT0_TRNERR_POS (0U) +#define DMA_INTSTAT0_TRNERR (0x000000FFUL) +#define DMA_INTSTAT0_TRNERR_0 (0x00000001UL) +#define DMA_INTSTAT0_TRNERR_1 (0x00000002UL) +#define DMA_INTSTAT0_TRNERR_2 (0x00000004UL) +#define DMA_INTSTAT0_TRNERR_3 (0x00000008UL) +#define DMA_INTSTAT0_TRNERR_4 (0x00000010UL) +#define DMA_INTSTAT0_TRNERR_5 (0x00000020UL) +#define DMA_INTSTAT0_TRNERR_6 (0x00000040UL) +#define DMA_INTSTAT0_TRNERR_7 (0x00000080UL) +#define DMA_INTSTAT0_REQERR_POS (16U) +#define DMA_INTSTAT0_REQERR (0x00FF0000UL) +#define DMA_INTSTAT0_REQERR_0 (0x00010000UL) +#define DMA_INTSTAT0_REQERR_1 (0x00020000UL) +#define DMA_INTSTAT0_REQERR_2 (0x00040000UL) +#define DMA_INTSTAT0_REQERR_3 (0x00080000UL) +#define DMA_INTSTAT0_REQERR_4 (0x00100000UL) +#define DMA_INTSTAT0_REQERR_5 (0x00200000UL) +#define DMA_INTSTAT0_REQERR_6 (0x00400000UL) +#define DMA_INTSTAT0_REQERR_7 (0x00800000UL) + +/* Bit definition for DMA_INTSTAT1 register */ +#define DMA_INTSTAT1_TC_POS (0U) +#define DMA_INTSTAT1_TC (0x000000FFUL) +#define DMA_INTSTAT1_TC_0 (0x00000001UL) +#define DMA_INTSTAT1_TC_1 (0x00000002UL) +#define DMA_INTSTAT1_TC_2 (0x00000004UL) +#define DMA_INTSTAT1_TC_3 (0x00000008UL) +#define DMA_INTSTAT1_TC_4 (0x00000010UL) +#define DMA_INTSTAT1_TC_5 (0x00000020UL) +#define DMA_INTSTAT1_TC_6 (0x00000040UL) +#define DMA_INTSTAT1_TC_7 (0x00000080UL) +#define DMA_INTSTAT1_BTC_POS (16U) +#define DMA_INTSTAT1_BTC (0x00FF0000UL) +#define DMA_INTSTAT1_BTC_0 (0x00010000UL) +#define DMA_INTSTAT1_BTC_1 (0x00020000UL) +#define DMA_INTSTAT1_BTC_2 (0x00040000UL) +#define DMA_INTSTAT1_BTC_3 (0x00080000UL) +#define DMA_INTSTAT1_BTC_4 (0x00100000UL) +#define DMA_INTSTAT1_BTC_5 (0x00200000UL) +#define DMA_INTSTAT1_BTC_6 (0x00400000UL) +#define DMA_INTSTAT1_BTC_7 (0x00800000UL) + +/* Bit definition for DMA_INTMASK0 register */ +#define DMA_INTMASK0_MSKTRNERR_POS (0U) +#define DMA_INTMASK0_MSKTRNERR (0x000000FFUL) +#define DMA_INTMASK0_MSKTRNERR_0 (0x00000001UL) +#define DMA_INTMASK0_MSKTRNERR_1 (0x00000002UL) +#define DMA_INTMASK0_MSKTRNERR_2 (0x00000004UL) +#define DMA_INTMASK0_MSKTRNERR_3 (0x00000008UL) +#define DMA_INTMASK0_MSKTRNERR_4 (0x00000010UL) +#define DMA_INTMASK0_MSKTRNERR_5 (0x00000020UL) +#define DMA_INTMASK0_MSKTRNERR_6 (0x00000040UL) +#define DMA_INTMASK0_MSKTRNERR_7 (0x00000080UL) +#define DMA_INTMASK0_MSKREQERR_POS (16U) +#define DMA_INTMASK0_MSKREQERR (0x00FF0000UL) +#define DMA_INTMASK0_MSKREQERR_0 (0x00010000UL) +#define DMA_INTMASK0_MSKREQERR_1 (0x00020000UL) +#define DMA_INTMASK0_MSKREQERR_2 (0x00040000UL) +#define DMA_INTMASK0_MSKREQERR_3 (0x00080000UL) +#define DMA_INTMASK0_MSKREQERR_4 (0x00100000UL) +#define DMA_INTMASK0_MSKREQERR_5 (0x00200000UL) +#define DMA_INTMASK0_MSKREQERR_6 (0x00400000UL) +#define DMA_INTMASK0_MSKREQERR_7 (0x00800000UL) + +/* Bit definition for DMA_INTMASK1 register */ +#define DMA_INTMASK1_MSKTC_POS (0U) +#define DMA_INTMASK1_MSKTC (0x000000FFUL) +#define DMA_INTMASK1_MSKTC_0 (0x00000001UL) +#define DMA_INTMASK1_MSKTC_1 (0x00000002UL) +#define DMA_INTMASK1_MSKTC_2 (0x00000004UL) +#define DMA_INTMASK1_MSKTC_3 (0x00000008UL) +#define DMA_INTMASK1_MSKTC_4 (0x00000010UL) +#define DMA_INTMASK1_MSKTC_5 (0x00000020UL) +#define DMA_INTMASK1_MSKTC_6 (0x00000040UL) +#define DMA_INTMASK1_MSKTC_7 (0x00000080UL) +#define DMA_INTMASK1_MSKBTC_POS (16U) +#define DMA_INTMASK1_MSKBTC (0x00FF0000UL) +#define DMA_INTMASK1_MSKBTC_0 (0x00010000UL) +#define DMA_INTMASK1_MSKBTC_1 (0x00020000UL) +#define DMA_INTMASK1_MSKBTC_2 (0x00040000UL) +#define DMA_INTMASK1_MSKBTC_3 (0x00080000UL) +#define DMA_INTMASK1_MSKBTC_4 (0x00100000UL) +#define DMA_INTMASK1_MSKBTC_5 (0x00200000UL) +#define DMA_INTMASK1_MSKBTC_6 (0x00400000UL) +#define DMA_INTMASK1_MSKBTC_7 (0x00800000UL) + +/* Bit definition for DMA_INTCLR0 register */ +#define DMA_INTCLR0_CLRTRNERR_POS (0U) +#define DMA_INTCLR0_CLRTRNERR (0x000000FFUL) +#define DMA_INTCLR0_CLRTRNERR_0 (0x00000001UL) +#define DMA_INTCLR0_CLRTRNERR_1 (0x00000002UL) +#define DMA_INTCLR0_CLRTRNERR_2 (0x00000004UL) +#define DMA_INTCLR0_CLRTRNERR_3 (0x00000008UL) +#define DMA_INTCLR0_CLRTRNERR_4 (0x00000010UL) +#define DMA_INTCLR0_CLRTRNERR_5 (0x00000020UL) +#define DMA_INTCLR0_CLRTRNERR_6 (0x00000040UL) +#define DMA_INTCLR0_CLRTRNERR_7 (0x00000080UL) +#define DMA_INTCLR0_CLRREQERR_POS (16U) +#define DMA_INTCLR0_CLRREQERR (0x00FF0000UL) +#define DMA_INTCLR0_CLRREQERR_0 (0x00010000UL) +#define DMA_INTCLR0_CLRREQERR_1 (0x00020000UL) +#define DMA_INTCLR0_CLRREQERR_2 (0x00040000UL) +#define DMA_INTCLR0_CLRREQERR_3 (0x00080000UL) +#define DMA_INTCLR0_CLRREQERR_4 (0x00100000UL) +#define DMA_INTCLR0_CLRREQERR_5 (0x00200000UL) +#define DMA_INTCLR0_CLRREQERR_6 (0x00400000UL) +#define DMA_INTCLR0_CLRREQERR_7 (0x00800000UL) + +/* Bit definition for DMA_INTCLR1 register */ +#define DMA_INTCLR1_CLRTC_POS (0U) +#define DMA_INTCLR1_CLRTC (0x000000FFUL) +#define DMA_INTCLR1_CLRTC_0 (0x00000001UL) +#define DMA_INTCLR1_CLRTC_1 (0x00000002UL) +#define DMA_INTCLR1_CLRTC_2 (0x00000004UL) +#define DMA_INTCLR1_CLRTC_3 (0x00000008UL) +#define DMA_INTCLR1_CLRTC_4 (0x00000010UL) +#define DMA_INTCLR1_CLRTC_5 (0x00000020UL) +#define DMA_INTCLR1_CLRTC_6 (0x00000040UL) +#define DMA_INTCLR1_CLRTC_7 (0x00000080UL) +#define DMA_INTCLR1_CLRBTC_POS (16U) +#define DMA_INTCLR1_CLRBTC (0x00FF0000UL) +#define DMA_INTCLR1_CLRBTC_0 (0x00010000UL) +#define DMA_INTCLR1_CLRBTC_1 (0x00020000UL) +#define DMA_INTCLR1_CLRBTC_2 (0x00040000UL) +#define DMA_INTCLR1_CLRBTC_3 (0x00080000UL) +#define DMA_INTCLR1_CLRBTC_4 (0x00100000UL) +#define DMA_INTCLR1_CLRBTC_5 (0x00200000UL) +#define DMA_INTCLR1_CLRBTC_6 (0x00400000UL) +#define DMA_INTCLR1_CLRBTC_7 (0x00800000UL) + +/* Bit definition for DMA_CHEN register */ +#define DMA_CHEN_CHEN (0x000000FFUL) + +/* Bit definition for DMA_REQSTAT register */ +#define DMA_REQSTAT_CHREQ_POS (0U) +#define DMA_REQSTAT_CHREQ (0x000000FFUL) +#define DMA_REQSTAT_CHREQ_0 (0x00000001UL) +#define DMA_REQSTAT_CHREQ_1 (0x00000002UL) +#define DMA_REQSTAT_CHREQ_2 (0x00000004UL) +#define DMA_REQSTAT_CHREQ_3 (0x00000008UL) +#define DMA_REQSTAT_CHREQ_4 (0x00000010UL) +#define DMA_REQSTAT_CHREQ_5 (0x00000020UL) +#define DMA_REQSTAT_CHREQ_6 (0x00000040UL) +#define DMA_REQSTAT_CHREQ_7 (0x00000080UL) +#define DMA_REQSTAT_RCFGREQ_POS (15U) +#define DMA_REQSTAT_RCFGREQ (0x00008000UL) + +/* Bit definition for DMA_CHSTAT register */ +#define DMA_CHSTAT_DMAACT_POS (0U) +#define DMA_CHSTAT_DMAACT (0x00000001UL) +#define DMA_CHSTAT_RCFGACT_POS (1U) +#define DMA_CHSTAT_RCFGACT (0x00000002UL) +#define DMA_CHSTAT_CHACT_POS (16U) +#define DMA_CHSTAT_CHACT (0x00FF0000UL) +#define DMA_CHSTAT_CHACT_0 (0x00010000UL) +#define DMA_CHSTAT_CHACT_1 (0x00020000UL) +#define DMA_CHSTAT_CHACT_2 (0x00040000UL) +#define DMA_CHSTAT_CHACT_3 (0x00080000UL) +#define DMA_CHSTAT_CHACT_4 (0x00100000UL) +#define DMA_CHSTAT_CHACT_5 (0x00200000UL) +#define DMA_CHSTAT_CHACT_6 (0x00400000UL) +#define DMA_CHSTAT_CHACT_7 (0x00800000UL) + +/* Bit definition for DMA_RCFGCTL register */ +#define DMA_RCFGCTL_RCFGEN_POS (0U) +#define DMA_RCFGCTL_RCFGEN (0x00000001UL) +#define DMA_RCFGCTL_RCFGLLP_POS (1U) +#define DMA_RCFGCTL_RCFGLLP (0x00000002UL) +#define DMA_RCFGCTL_RCFGCHS_POS (8U) +#define DMA_RCFGCTL_RCFGCHS (0x00000F00UL) +#define DMA_RCFGCTL_SARMD_POS (16U) +#define DMA_RCFGCTL_SARMD (0x00030000UL) +#define DMA_RCFGCTL_SARMD_0 (0x00010000UL) +#define DMA_RCFGCTL_SARMD_1 (0x00020000UL) +#define DMA_RCFGCTL_DARMD_POS (18U) +#define DMA_RCFGCTL_DARMD (0x000C0000UL) +#define DMA_RCFGCTL_DARMD_0 (0x00040000UL) +#define DMA_RCFGCTL_DARMD_1 (0x00080000UL) +#define DMA_RCFGCTL_CNTMD_POS (20U) +#define DMA_RCFGCTL_CNTMD (0x00300000UL) +#define DMA_RCFGCTL_CNTMD_0 (0x00100000UL) +#define DMA_RCFGCTL_CNTMD_1 (0x00200000UL) + +/* Bit definition for DMA_CHENCLR register */ +#define DMA_CHENCLR_CHENCLR (0x000000FFUL) + +/* Bit definition for DMA_SAR register */ +#define DMA_SAR_SAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DAR register */ +#define DMA_DAR_DAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_DTCTL register */ +#define DMA_DTCTL_BLKSIZE_POS (0U) +#define DMA_DTCTL_BLKSIZE (0x000003FFUL) +#define DMA_DTCTL_CNT_POS (16U) +#define DMA_DTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_RPT register */ +#define DMA_RPT_SRPT_POS (0U) +#define DMA_RPT_SRPT (0x000003FFUL) +#define DMA_RPT_DRPT_POS (16U) +#define DMA_RPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_RPTB register */ +#define DMA_RPTB_SRPTB_POS (0U) +#define DMA_RPTB_SRPTB (0x000003FFUL) +#define DMA_RPTB_DRPTB_POS (16U) +#define DMA_RPTB_DRPTB (0x03FF0000UL) + +/* Bit definition for DMA_SNSEQCTL register */ +#define DMA_SNSEQCTL_SOFFSET_POS (0U) +#define DMA_SNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_SNSEQCTL_SNSCNT_POS (20U) +#define DMA_SNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_SNSEQCTLB register */ +#define DMA_SNSEQCTLB_SNSDIST_POS (0U) +#define DMA_SNSEQCTLB_SNSDIST (0x000FFFFFUL) +#define DMA_SNSEQCTLB_SNSCNTB_POS (20U) +#define DMA_SNSEQCTLB_SNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTL register */ +#define DMA_DNSEQCTL_DOFFSET_POS (0U) +#define DMA_DNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_DNSEQCTL_DNSCNT_POS (20U) +#define DMA_DNSEQCTL_DNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_DNSEQCTLB register */ +#define DMA_DNSEQCTLB_DNSDIST_POS (0U) +#define DMA_DNSEQCTLB_DNSDIST (0x000FFFFFUL) +#define DMA_DNSEQCTLB_DNSCNTB_POS (20U) +#define DMA_DNSEQCTLB_DNSCNTB (0xFFF00000UL) + +/* Bit definition for DMA_LLP register */ +#define DMA_LLP_LLP_POS (2U) +#define DMA_LLP_LLP (0xFFFFFFFCUL) + +/* Bit definition for DMA_CHCTL register */ +#define DMA_CHCTL_SINC_POS (0U) +#define DMA_CHCTL_SINC (0x00000003UL) +#define DMA_CHCTL_SINC_0 (0x00000001UL) +#define DMA_CHCTL_SINC_1 (0x00000002UL) +#define DMA_CHCTL_DINC_POS (2U) +#define DMA_CHCTL_DINC (0x0000000CUL) +#define DMA_CHCTL_DINC_0 (0x00000004UL) +#define DMA_CHCTL_DINC_1 (0x00000008UL) +#define DMA_CHCTL_SRTPEN_POS (4U) +#define DMA_CHCTL_SRTPEN (0x00000010UL) +#define DMA_CHCTL_DRPTEN_POS (5U) +#define DMA_CHCTL_DRPTEN (0x00000020UL) +#define DMA_CHCTL_SNSEQEN_POS (6U) +#define DMA_CHCTL_SNSEQEN (0x00000040UL) +#define DMA_CHCTL_DNSEQEN_POS (7U) +#define DMA_CHCTL_DNSEQEN (0x00000080UL) +#define DMA_CHCTL_HSIZE_POS (8U) +#define DMA_CHCTL_HSIZE (0x00000300UL) +#define DMA_CHCTL_HSIZE_0 (0x00000100UL) +#define DMA_CHCTL_HSIZE_1 (0x00000200UL) +#define DMA_CHCTL_LLPEN_POS (10U) +#define DMA_CHCTL_LLPEN (0x00000400UL) +#define DMA_CHCTL_LLPRUN_POS (11U) +#define DMA_CHCTL_LLPRUN (0x00000800UL) +#define DMA_CHCTL_IE_POS (12U) +#define DMA_CHCTL_IE (0x00001000UL) + +/* Bit definition for DMA_MONSAR register */ +#define DMA_MONSAR_MONSAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDAR register */ +#define DMA_MONDAR_MONDAR (0xFFFFFFFFUL) + +/* Bit definition for DMA_MONDTCTL register */ +#define DMA_MONDTCTL_BLKSIZE_POS (0U) +#define DMA_MONDTCTL_BLKSIZE (0x000003FFUL) +#define DMA_MONDTCTL_CNT_POS (16U) +#define DMA_MONDTCTL_CNT (0xFFFF0000UL) + +/* Bit definition for DMA_MONRPT register */ +#define DMA_MONRPT_SRPT_POS (0U) +#define DMA_MONRPT_SRPT (0x000003FFUL) +#define DMA_MONRPT_DRPT_POS (16U) +#define DMA_MONRPT_DRPT (0x03FF0000UL) + +/* Bit definition for DMA_MONSNSEQCTL register */ +#define DMA_MONSNSEQCTL_SOFFSET_POS (0U) +#define DMA_MONSNSEQCTL_SOFFSET (0x000FFFFFUL) +#define DMA_MONSNSEQCTL_SNSCNT_POS (20U) +#define DMA_MONSNSEQCTL_SNSCNT (0xFFF00000UL) + +/* Bit definition for DMA_MONDNSEQCTL register */ +#define DMA_MONDNSEQCTL_DOFFSET_POS (0U) +#define DMA_MONDNSEQCTL_DOFFSET (0x000FFFFFUL) +#define DMA_MONDNSEQCTL_DNSCNT_POS (20U) +#define DMA_MONDNSEQCTL_DNSCNT (0xFFF00000UL) + +/******************************************************************************* + Bit definition for Peripheral DMC +*******************************************************************************/ +/* Bit definition for DMC_STSR register */ +#define DMC_STSR_STATUS_POS (0U) +#define DMC_STSR_STATUS (0x00000003UL) +#define DMC_STSR_STATUS_0 (0x00000001UL) +#define DMC_STSR_STATUS_1 (0x00000002UL) +#define DMC_STSR_MEMMW_POS (2U) +#define DMC_STSR_MEMMW (0x0000000CUL) +#define DMC_STSR_MEMMW_0 (0x00000004UL) +#define DMC_STSR_MEMMW_1 (0x00000008UL) + +/* Bit definition for DMC_STCR register */ +#define DMC_STCR_STCTL (0x00000007UL) + +/* Bit definition for DMC_CMDR register */ +#define DMC_CMDR_CMDADD_POS (0U) +#define DMC_CMDR_CMDADD (0x00003FFFUL) +#define DMC_CMDR_CMDBA_POS (16U) +#define DMC_CMDR_CMDBA (0x00030000UL) +#define DMC_CMDR_CMDBA_0 (0x00010000UL) +#define DMC_CMDR_CMDBA_1 (0x00020000UL) +#define DMC_CMDR_CMD_POS (18U) +#define DMC_CMDR_CMD (0x000C0000UL) +#define DMC_CMDR_CMD_0 (0x00040000UL) +#define DMC_CMDR_CMD_1 (0x00080000UL) +#define DMC_CMDR_CMDCHIP_POS (20U) +#define DMC_CMDR_CMDCHIP (0x00300000UL) +#define DMC_CMDR_CMDCHIP_0 (0x00100000UL) +#define DMC_CMDR_CMDCHIP_1 (0x00200000UL) +#define DMC_CMDR_RESV5_POS (24U) +#define DMC_CMDR_RESV5 (0x01000000UL) + +/* Bit definition for DMC_CPCR register */ +#define DMC_CPCR_COLBS_POS (0U) +#define DMC_CPCR_COLBS (0x00000007UL) +#define DMC_CPCR_COLBS_0 (0x00000001UL) +#define DMC_CPCR_COLBS_1 (0x00000002UL) +#define DMC_CPCR_COLBS_2 (0x00000004UL) +#define DMC_CPCR_ROWBS_POS (4U) +#define DMC_CPCR_ROWBS (0x00000070UL) +#define DMC_CPCR_ROWBS_0 (0x00000010UL) +#define DMC_CPCR_ROWBS_1 (0x00000020UL) +#define DMC_CPCR_ROWBS_2 (0x00000040UL) +#define DMC_CPCR_APBS_POS (7U) +#define DMC_CPCR_APBS (0x00000080UL) +#define DMC_CPCR_CKEDIS_POS (8U) +#define DMC_CPCR_CKEDIS (0x00000100UL) +#define DMC_CPCR_CKSTOP_POS (9U) +#define DMC_CPCR_CKSTOP (0x00000200UL) +#define DMC_CPCR_CKEDISPRD_POS (10U) +#define DMC_CPCR_CKEDISPRD (0x0000FC00UL) +#define DMC_CPCR_BURST_POS (16U) +#define DMC_CPCR_BURST (0x00070000UL) +#define DMC_CPCR_BURST_0 (0x00010000UL) +#define DMC_CPCR_BURST_1 (0x00020000UL) +#define DMC_CPCR_BURST_2 (0x00040000UL) +#define DMC_CPCR_ACTCP_POS (24U) +#define DMC_CPCR_ACTCP (0x03000000UL) +#define DMC_CPCR_ACTCP_0 (0x01000000UL) +#define DMC_CPCR_ACTCP_1 (0x02000000UL) + +/* Bit definition for DMC_RFTR register */ +#define DMC_RFTR_REFPRD (0x00007FFFUL) + +/* Bit definition for DMC_TMCR_T_CASL register */ +#define DMC_TMCR_T_CASL_T_CASL (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_DQSS register */ +#define DMC_TMCR_T_DQSS_T_DQSS (0x00000003UL) + +/* Bit definition for DMC_TMCR_T_MRD register */ +#define DMC_TMCR_T_MRD_T_MRD (0x0000007FUL) + +/* Bit definition for DMC_TMCR_T_RAS register */ +#define DMC_TMCR_T_RAS_T_RAS (0x0000000FUL) + +/* Bit definition for DMC_TMCR_T_RC register */ +#define DMC_TMCR_T_RC_T_RC (0x0000000FUL) + +/* Bit definition for DMC_TMCR_T_RCD register */ +#define DMC_TMCR_T_RCD_T_RCD (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_RFC register */ +#define DMC_TMCR_T_RFC_T_RFC (0x0000001FUL) + +/* Bit definition for DMC_TMCR_T_RP register */ +#define DMC_TMCR_T_RP_T_RP (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_RRD register */ +#define DMC_TMCR_T_RRD_T_RRD (0x0000000FUL) + +/* Bit definition for DMC_TMCR_T_WR register */ +#define DMC_TMCR_T_WR_T_WR (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_WTR register */ +#define DMC_TMCR_T_WTR_T_WTR (0x00000007UL) + +/* Bit definition for DMC_TMCR_T_XP register */ +#define DMC_TMCR_T_XP_T_XP (0x000000FFUL) + +/* Bit definition for DMC_TMCR_T_XSR register */ +#define DMC_TMCR_T_XSR_T_XSR (0x000000FFUL) + +/* Bit definition for DMC_TMCR_T_ESR register */ +#define DMC_TMCR_T_ESR_T_ESR (0x000000FFUL) + +/* Bit definition for DMC_CSCR register */ +#define DMC_CSCR_ADDMSK_POS (0U) +#define DMC_CSCR_ADDMSK (0x000000FFUL) +#define DMC_CSCR_ADDMAT_POS (8U) +#define DMC_CSCR_ADDMAT (0x0000FF00UL) +#define DMC_CSCR_BRC_POS (16U) +#define DMC_CSCR_BRC (0x00010000UL) +#define DMC_CSCR_RESV8_POS (24U) +#define DMC_CSCR_RESV8 (0x01000000UL) + +/* Bit definition for DMC_BACR register */ +#define DMC_BACR_DMCMW_POS (0U) +#define DMC_BACR_DMCMW (0x00000003UL) +#define DMC_BACR_DMCMW_0 (0x00000001UL) +#define DMC_BACR_DMCMW_1 (0x00000002UL) +#define DMC_BACR_RESV11_POS (24U) +#define DMC_BACR_RESV11 (0x01000000UL) + +/******************************************************************************* + Bit definition for Peripheral DVP +*******************************************************************************/ +/* Bit definition for DVP_CTR register */ +#define DVP_CTR_CAPEN_POS (0U) +#define DVP_CTR_CAPEN (0x00000001UL) +#define DVP_CTR_CAPMD_POS (1U) +#define DVP_CTR_CAPMD (0x00000002UL) +#define DVP_CTR_CROPEN_POS (2U) +#define DVP_CTR_CROPEN (0x00000004UL) +#define DVP_CTR_JPEGEN_POS (3U) +#define DVP_CTR_JPEGEN (0x00000008UL) +#define DVP_CTR_SWSYNC_POS (4U) +#define DVP_CTR_SWSYNC (0x00000010UL) +#define DVP_CTR_PIXCKSEL_POS (5U) +#define DVP_CTR_PIXCKSEL (0x00000020UL) +#define DVP_CTR_HSYNCSEL_POS (6U) +#define DVP_CTR_HSYNCSEL (0x00000040UL) +#define DVP_CTR_VSYNCSEL_POS (7U) +#define DVP_CTR_VSYNCSEL (0x00000080UL) +#define DVP_CTR_CAPFRC_POS (8U) +#define DVP_CTR_CAPFRC (0x00000300UL) +#define DVP_CTR_CAPFRC_0 (0x00000100UL) +#define DVP_CTR_CAPFRC_1 (0x00000200UL) +#define DVP_CTR_BITSEL_POS (10U) +#define DVP_CTR_BITSEL (0x00000C00UL) +#define DVP_CTR_BITSEL_0 (0x00000400UL) +#define DVP_CTR_BITSEL_1 (0x00000800UL) +#define DVP_CTR_DVPEN_POS (14U) +#define DVP_CTR_DVPEN (0x00004000UL) + +/* Bit definition for DVP_DTR register */ +#define DVP_DTR (0xFFFFFFFFUL) + +/* Bit definition for DVP_STR register */ +#define DVP_STR_FSF_POS (0U) +#define DVP_STR_FSF (0x00000001UL) +#define DVP_STR_LSF_POS (1U) +#define DVP_STR_LSF (0x00000002UL) +#define DVP_STR_LEF_POS (2U) +#define DVP_STR_LEF (0x00000004UL) +#define DVP_STR_FEF_POS (3U) +#define DVP_STR_FEF (0x00000008UL) +#define DVP_STR_SQUERF_POS (4U) +#define DVP_STR_SQUERF (0x00000010UL) +#define DVP_STR_FIFOERF_POS (5U) +#define DVP_STR_FIFOERF (0x00000020UL) + +/* Bit definition for DVP_IER register */ +#define DVP_IER_FSIEN_POS (0U) +#define DVP_IER_FSIEN (0x00000001UL) +#define DVP_IER_LSIEN_POS (1U) +#define DVP_IER_LSIEN (0x00000002UL) +#define DVP_IER_LEIEN_POS (2U) +#define DVP_IER_LEIEN (0x00000004UL) +#define DVP_IER_FEIEN_POS (3U) +#define DVP_IER_FEIEN (0x00000008UL) +#define DVP_IER_SQUERIEN_POS (4U) +#define DVP_IER_SQUERIEN (0x00000010UL) +#define DVP_IER_FIFOERIEN_POS (5U) +#define DVP_IER_FIFOERIEN (0x00000020UL) + +/* Bit definition for DVP_DMR register */ +#define DVP_DMR (0xFFFFFFFFUL) + +/* Bit definition for DVP_SSYNDR register */ +#define DVP_SSYNDR_FSDAT_POS (0U) +#define DVP_SSYNDR_FSDAT (0x000000FFUL) +#define DVP_SSYNDR_LSDAT_POS (8U) +#define DVP_SSYNDR_LSDAT (0x0000FF00UL) +#define DVP_SSYNDR_LEDAT_POS (16U) +#define DVP_SSYNDR_LEDAT (0x00FF0000UL) +#define DVP_SSYNDR_FEDAT_POS (24U) +#define DVP_SSYNDR_FEDAT (0xFF000000UL) + +/* Bit definition for DVP_SSYNMR register */ +#define DVP_SSYNMR_FSMSK_POS (0U) +#define DVP_SSYNMR_FSMSK (0x000000FFUL) +#define DVP_SSYNMR_LSMSK_POS (8U) +#define DVP_SSYNMR_LSMSK (0x0000FF00UL) +#define DVP_SSYNMR_LEMSK_POS (16U) +#define DVP_SSYNMR_LEMSK (0x00FF0000UL) +#define DVP_SSYNMR_FEMSK_POS (24U) +#define DVP_SSYNMR_FEMSK (0xFF000000UL) + +/* Bit definition for DVP_CPSFTR register */ +#define DVP_CPSFTR_RSHIFT_POS (0U) +#define DVP_CPSFTR_RSHIFT (0x00003FFFUL) +#define DVP_CPSFTR_CSHIFT_POS (16U) +#define DVP_CPSFTR_CSHIFT (0x3FFF0000UL) + +/* Bit definition for DVP_CPSZER register */ +#define DVP_CPSZER_RSIZE_POS (0U) +#define DVP_CPSZER_RSIZE (0x00003FFFUL) +#define DVP_CPSZER_CSIZE_POS (16U) +#define DVP_CPSZER_CSIZE (0x3FFF0000UL) + +/******************************************************************************* + Bit definition for Peripheral EFM +*******************************************************************************/ +/* Bit definition for EFM_FAPRT register */ +#define EFM_FAPRT_FAPRT (0x0000FFFFUL) + +/* Bit definition for EFM_KEY1 register */ +#define EFM_KEY1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_KEY2 register */ +#define EFM_KEY2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_FSTP register */ +#define EFM_FSTP_F0STP_POS (0U) +#define EFM_FSTP_F0STP (0x00000001UL) +#define EFM_FSTP_F1STP_POS (1U) +#define EFM_FSTP_F1STP (0x00000002UL) + +/* Bit definition for EFM_FRMC register */ +#define EFM_FRMC_FLWT_POS (0U) +#define EFM_FRMC_FLWT (0x0000000FUL) +#define EFM_FRMC_FLWT_0 (0x00000001UL) +#define EFM_FRMC_FLWT_1 (0x00000002UL) +#define EFM_FRMC_FLWT_2 (0x00000004UL) +#define EFM_FRMC_FLWT_3 (0x00000008UL) +#define EFM_FRMC_LVM_POS (8U) +#define EFM_FRMC_LVM (0x00000100UL) +#define EFM_FRMC_ICACHE_POS (16U) +#define EFM_FRMC_ICACHE (0x00010000UL) +#define EFM_FRMC_DCACHE_POS (17U) +#define EFM_FRMC_DCACHE (0x00020000UL) +#define EFM_FRMC_PREFE_POS (18U) +#define EFM_FRMC_PREFE (0x00040000UL) +#define EFM_FRMC_CRST_POS (19U) +#define EFM_FRMC_CRST (0x00080000UL) + +/* Bit definition for EFM_FWMC register */ +#define EFM_FWMC_PEMOD_POS (0U) +#define EFM_FWMC_PEMOD (0x00000007UL) +#define EFM_FWMC_BUSHLDCTL_POS (8U) +#define EFM_FWMC_BUSHLDCTL (0x00000100UL) +#define EFM_FWMC_KEY1LOCK_POS (16U) +#define EFM_FWMC_KEY1LOCK (0x00010000UL) +#define EFM_FWMC_KEY2LOCK_POS (17U) +#define EFM_FWMC_KEY2LOCK (0x00020000UL) + +/* Bit definition for EFM_FSR register */ +#define EFM_FSR_OTPWERR0_POS (0U) +#define EFM_FSR_OTPWERR0 (0x00000001UL) +#define EFM_FSR_PRTWERR0_POS (1U) +#define EFM_FSR_PRTWERR0 (0x00000002UL) +#define EFM_FSR_PGSZERR0_POS (2U) +#define EFM_FSR_PGSZERR0 (0x00000004UL) +#define EFM_FSR_MISMTCH0_POS (3U) +#define EFM_FSR_MISMTCH0 (0x00000008UL) +#define EFM_FSR_OPTEND0_POS (4U) +#define EFM_FSR_OPTEND0 (0x00000010UL) +#define EFM_FSR_COLERR0_POS (5U) +#define EFM_FSR_COLERR0 (0x00000020UL) +#define EFM_FSR_RDY0_POS (8U) +#define EFM_FSR_RDY0 (0x00000100UL) +#define EFM_FSR_PRTWERR1_POS (17U) +#define EFM_FSR_PRTWERR1 (0x00020000UL) +#define EFM_FSR_PGSZERR1_POS (18U) +#define EFM_FSR_PGSZERR1 (0x00040000UL) +#define EFM_FSR_MISMTCH1_POS (19U) +#define EFM_FSR_MISMTCH1 (0x00080000UL) +#define EFM_FSR_OPTEND1_POS (20U) +#define EFM_FSR_OPTEND1 (0x00100000UL) +#define EFM_FSR_COLERR1_POS (21U) +#define EFM_FSR_COLERR1 (0x00200000UL) +#define EFM_FSR_RDY1_POS (24U) +#define EFM_FSR_RDY1 (0x01000000UL) + +/* Bit definition for EFM_FSCLR register */ +#define EFM_FSCLR_OTPWERRCLR0_POS (0U) +#define EFM_FSCLR_OTPWERRCLR0 (0x00000001UL) +#define EFM_FSCLR_PRTWERRCLR0_POS (1U) +#define EFM_FSCLR_PRTWERRCLR0 (0x00000002UL) +#define EFM_FSCLR_PGSZERRCLR0_POS (2U) +#define EFM_FSCLR_PGSZERRCLR0 (0x00000004UL) +#define EFM_FSCLR_MISMTCHCLR0_POS (3U) +#define EFM_FSCLR_MISMTCHCLR0 (0x00000008UL) +#define EFM_FSCLR_OPTENDCLR0_POS (4U) +#define EFM_FSCLR_OPTENDCLR0 (0x00000010UL) +#define EFM_FSCLR_COLERRCLR0_POS (5U) +#define EFM_FSCLR_COLERRCLR0 (0x00000020UL) +#define EFM_FSCLR_PRTWERRCLR1_POS (17U) +#define EFM_FSCLR_PRTWERRCLR1 (0x00020000UL) +#define EFM_FSCLR_PGSZERRCLR1_POS (18U) +#define EFM_FSCLR_PGSZERRCLR1 (0x00040000UL) +#define EFM_FSCLR_MISMTCHCLR1_POS (19U) +#define EFM_FSCLR_MISMTCHCLR1 (0x00080000UL) +#define EFM_FSCLR_OPTENDCLR1_POS (20U) +#define EFM_FSCLR_OPTENDCLR1 (0x00100000UL) +#define EFM_FSCLR_COLERRCLR1_POS (21U) +#define EFM_FSCLR_COLERRCLR1 (0x00200000UL) + +/* Bit definition for EFM_FITE register */ +#define EFM_FITE_PEERRITE_POS (0U) +#define EFM_FITE_PEERRITE (0x00000001UL) +#define EFM_FITE_OPTENDITE_POS (1U) +#define EFM_FITE_OPTENDITE (0x00000002UL) +#define EFM_FITE_COLERRITE_POS (2U) +#define EFM_FITE_COLERRITE (0x00000004UL) + +/* Bit definition for EFM_FSWP register */ +#define EFM_FSWP_FSWP (0x00000001UL) + +/* Bit definition for EFM_FHDFG register */ +#define EFM_FHDFG (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID0 register */ +#define EFM_UQID0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID1 register */ +#define EFM_UQID1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_UQID2 register */ +#define EFM_UQID2 (0xFFFFFFFFUL) + +/* Bit definition for MMF_REMPRT register */ +#define MMF_REMPRT_REMPRT (0x0000FFFFUL) + +/* Bit definition for MMF_REMCR0 register */ +#define MMF_REMCR0_RM0SIZE_POS (0U) +#define MMF_REMCR0_RM0SIZE (0x0000001FUL) +#define MMF_REMCR0_RM0TADDR_POS (12U) +#define MMF_REMCR0_RM0TADDR (0x1FFFF000UL) +#define MMF_REMCR0_EN0_POS (31U) +#define MMF_REMCR0_EN0 (0x80000000UL) + +/* Bit definition for MMF_REMCR1 register */ +#define MMF_REMCR1_RM1SIZE_POS (0U) +#define MMF_REMCR1_RM1SIZE (0x0000001FUL) +#define MMF_REMCR1_RM1TADDR_POS (12U) +#define MMF_REMCR1_RM1TADDR (0x1FFFF000UL) +#define MMF_REMCR1_EN1_POS (31U) +#define MMF_REMCR1_EN1 (0x80000000UL) + +/* Bit definition for EFM_WLOCK register */ +#define EFM_WLOCK_WLOCK0_POS (0U) +#define EFM_WLOCK_WLOCK0 (0x00000001UL) +#define EFM_WLOCK_WLOCK1_POS (1U) +#define EFM_WLOCK_WLOCK1 (0x00000002UL) +#define EFM_WLOCK_WLOCK2_POS (2U) +#define EFM_WLOCK_WLOCK2 (0x00000004UL) +#define EFM_WLOCK_WLOCK3_POS (3U) +#define EFM_WLOCK_WLOCK3 (0x00000008UL) +#define EFM_WLOCK_WLOCK4_POS (4U) +#define EFM_WLOCK_WLOCK4 (0x00000010UL) +#define EFM_WLOCK_WLOCK5_POS (5U) +#define EFM_WLOCK_WLOCK5 (0x00000020UL) +#define EFM_WLOCK_WLOCK6_POS (6U) +#define EFM_WLOCK_WLOCK6 (0x00000040UL) +#define EFM_WLOCK_WLOCK7_POS (7U) +#define EFM_WLOCK_WLOCK7 (0x00000080UL) + +/* Bit definition for EFM_F0NWPRT0 register */ +#define EFM_F0NWPRT0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F0NWPRT1 register */ +#define EFM_F0NWPRT1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F0NWPRT2 register */ +#define EFM_F0NWPRT2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F0NWPRT3 register */ +#define EFM_F0NWPRT3 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F1NWPRT0 register */ +#define EFM_F1NWPRT0 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F1NWPRT1 register */ +#define EFM_F1NWPRT1 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F1NWPRT2 register */ +#define EFM_F1NWPRT2 (0xFFFFFFFFUL) + +/* Bit definition for EFM_F1NWPRT3 register */ +#define EFM_F1NWPRT3 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral EMB +*******************************************************************************/ +/* Bit definition for EMB_CTL1 register */ +#define EMB_CTL1_CMPEN_POS (0U) +#define EMB_CTL1_CMPEN (0x0000000FUL) +#define EMB_CTL1_CMPEN_0 (0x00000001UL) +#define EMB_CTL1_CMPEN_1 (0x00000002UL) +#define EMB_CTL1_CMPEN_2 (0x00000004UL) +#define EMB_CTL1_CMPEN_3 (0x00000008UL) +#define EMB_CTL1_OSCSTPEN_POS (4U) +#define EMB_CTL1_OSCSTPEN (0x00000010UL) +#define EMB_CTL1_PWMSEN_POS (5U) +#define EMB_CTL1_PWMSEN (0x00001FE0UL) +#define EMB_CTL1_PWMSEN_0 (0x00000020UL) +#define EMB_CTL1_PWMSEN_1 (0x00000040UL) +#define EMB_CTL1_PWMSEN_2 (0x00000080UL) +#define EMB_CTL1_PWMSEN_3 (0x00000100UL) +#define EMB_CTL1_PWMSEN_4 (0x00000200UL) +#define EMB_CTL1_PWMSEN_5 (0x00000400UL) +#define EMB_CTL1_PWMSEN_6 (0x00000800UL) +#define EMB_CTL1_PWMSEN_7 (0x00001000UL) +#define EMB_CTL1_PORTINEN1_POS (16U) +#define EMB_CTL1_PORTINEN1 (0x00010000UL) +#define EMB_CTL1_PORTINEN2_POS (17U) +#define EMB_CTL1_PORTINEN2 (0x00020000UL) +#define EMB_CTL1_PORTINEN3_POS (18U) +#define EMB_CTL1_PORTINEN3 (0x00040000UL) +#define EMB_CTL1_PORTINEN4_POS (19U) +#define EMB_CTL1_PORTINEN4 (0x00080000UL) +#define EMB_CTL1_INVSEL1_POS (22U) +#define EMB_CTL1_INVSEL1 (0x00400000UL) +#define EMB_CTL1_INVSEL2_POS (23U) +#define EMB_CTL1_INVSEL2 (0x00800000UL) +#define EMB_CTL1_INVSEL3_POS (24U) +#define EMB_CTL1_INVSEL3 (0x01000000UL) +#define EMB_CTL1_INVSEL4_POS (25U) +#define EMB_CTL1_INVSEL4 (0x02000000UL) + +/* Bit definition for EMB_CTL2 register */ +#define EMB_CTL2_PWMLV_POS (0U) +#define EMB_CTL2_PWMLV (0x000000FFUL) +#define EMB_CTL2_PWMLV_0 (0x00000001UL) +#define EMB_CTL2_PWMLV_1 (0x00000002UL) +#define EMB_CTL2_PWMLV_2 (0x00000004UL) +#define EMB_CTL2_PWMLV_3 (0x00000008UL) +#define EMB_CTL2_PWMLV_4 (0x00000010UL) +#define EMB_CTL2_PWMLV_5 (0x00000020UL) +#define EMB_CTL2_PWMLV_6 (0x00000040UL) +#define EMB_CTL2_PWMLV_7 (0x00000080UL) +#define EMB_CTL2_NFSEL1_POS (16U) +#define EMB_CTL2_NFSEL1 (0x00030000UL) +#define EMB_CTL2_NFSEL1_0 (0x00010000UL) +#define EMB_CTL2_NFSEL1_1 (0x00020000UL) +#define EMB_CTL2_NFEN1_POS (18U) +#define EMB_CTL2_NFEN1 (0x00040000UL) +#define EMB_CTL2_NFSEL2_POS (19U) +#define EMB_CTL2_NFSEL2 (0x00180000UL) +#define EMB_CTL2_NFSEL2_0 (0x00080000UL) +#define EMB_CTL2_NFSEL2_1 (0x00100000UL) +#define EMB_CTL2_NFEN2_POS (21U) +#define EMB_CTL2_NFEN2 (0x00200000UL) +#define EMB_CTL2_NFSEL3_POS (22U) +#define EMB_CTL2_NFSEL3 (0x00C00000UL) +#define EMB_CTL2_NFSEL3_0 (0x00400000UL) +#define EMB_CTL2_NFSEL3_1 (0x00800000UL) +#define EMB_CTL2_NFEN3_POS (24U) +#define EMB_CTL2_NFEN3 (0x01000000UL) +#define EMB_CTL2_NFSEL4_POS (25U) +#define EMB_CTL2_NFSEL4 (0x06000000UL) +#define EMB_CTL2_NFSEL4_0 (0x02000000UL) +#define EMB_CTL2_NFSEL4_1 (0x04000000UL) +#define EMB_CTL2_NFEN4_POS (27U) +#define EMB_CTL2_NFEN4 (0x08000000UL) + +/* Bit definition for EMB_SOE register */ +#define EMB_SOE_SOE (0x00000001UL) + +/* Bit definition for EMB_STAT register */ +#define EMB_STAT_PWMSF_POS (1U) +#define EMB_STAT_PWMSF (0x00000002UL) +#define EMB_STAT_CMPF_POS (2U) +#define EMB_STAT_CMPF (0x00000004UL) +#define EMB_STAT_OSF_POS (3U) +#define EMB_STAT_OSF (0x00000008UL) +#define EMB_STAT_PWMST_POS (5U) +#define EMB_STAT_PWMST (0x00000020UL) +#define EMB_STAT_CMPST_POS (6U) +#define EMB_STAT_CMPST (0x00000040UL) +#define EMB_STAT_OSST_POS (7U) +#define EMB_STAT_OSST (0x00000080UL) +#define EMB_STAT_PORTINF1_POS (8U) +#define EMB_STAT_PORTINF1 (0x00000100UL) +#define EMB_STAT_PORTINF2_POS (9U) +#define EMB_STAT_PORTINF2 (0x00000200UL) +#define EMB_STAT_PORTINF3_POS (10U) +#define EMB_STAT_PORTINF3 (0x00000400UL) +#define EMB_STAT_PORTINF4_POS (11U) +#define EMB_STAT_PORTINF4 (0x00000800UL) +#define EMB_STAT_PORTINST1_POS (14U) +#define EMB_STAT_PORTINST1 (0x00004000UL) +#define EMB_STAT_PORTINST2_POS (15U) +#define EMB_STAT_PORTINST2 (0x00008000UL) +#define EMB_STAT_PORTINST3_POS (16U) +#define EMB_STAT_PORTINST3 (0x00010000UL) +#define EMB_STAT_PORTINST4_POS (17U) +#define EMB_STAT_PORTINST4 (0x00020000UL) + +/* Bit definition for EMB_STATCLR register */ +#define EMB_STATCLR_PWMSFCLR_POS (1U) +#define EMB_STATCLR_PWMSFCLR (0x00000002UL) +#define EMB_STATCLR_CMPFCLR_POS (2U) +#define EMB_STATCLR_CMPFCLR (0x00000004UL) +#define EMB_STATCLR_OSFCLR_POS (3U) +#define EMB_STATCLR_OSFCLR (0x00000008UL) +#define EMB_STATCLR_PORTINFCLR1_POS (8U) +#define EMB_STATCLR_PORTINFCLR1 (0x00000100UL) +#define EMB_STATCLR_PORTINFCLR2_POS (9U) +#define EMB_STATCLR_PORTINFCLR2 (0x00000200UL) +#define EMB_STATCLR_PORTINFCLR3_POS (10U) +#define EMB_STATCLR_PORTINFCLR3 (0x00000400UL) +#define EMB_STATCLR_PORTINFCLR4_POS (11U) +#define EMB_STATCLR_PORTINFCLR4 (0x00000800UL) + +/* Bit definition for EMB_INTEN register */ +#define EMB_INTEN_PWMSINTEN_POS (1U) +#define EMB_INTEN_PWMSINTEN (0x00000002UL) +#define EMB_INTEN_CMPINTEN_POS (2U) +#define EMB_INTEN_CMPINTEN (0x00000004UL) +#define EMB_INTEN_OSINTEN_POS (3U) +#define EMB_INTEN_OSINTEN (0x00000008UL) +#define EMB_INTEN_PORTINTEN1_POS (8U) +#define EMB_INTEN_PORTINTEN1 (0x00000100UL) +#define EMB_INTEN_PORTINTEN2_POS (9U) +#define EMB_INTEN_PORTINTEN2 (0x00000200UL) +#define EMB_INTEN_PORTINTEN3_POS (10U) +#define EMB_INTEN_PORTINTEN3 (0x00000400UL) +#define EMB_INTEN_PORTINTEN4_POS (11U) +#define EMB_INTEN_PORTINTEN4 (0x00000800UL) + +/* Bit definition for EMB_RLSSEL register */ +#define EMB_RLSSEL_PWMRSEL_POS (1U) +#define EMB_RLSSEL_PWMRSEL (0x00000002UL) +#define EMB_RLSSEL_CMPRSEL_POS (2U) +#define EMB_RLSSEL_CMPRSEL (0x00000004UL) +#define EMB_RLSSEL_OSRSEL_POS (3U) +#define EMB_RLSSEL_OSRSEL (0x00000008UL) +#define EMB_RLSSEL_PORTINRSEL1_POS (8U) +#define EMB_RLSSEL_PORTINRSEL1 (0x00000100UL) +#define EMB_RLSSEL_PORTINRSEL2_POS (9U) +#define EMB_RLSSEL_PORTINRSEL2 (0x00000200UL) +#define EMB_RLSSEL_PORTINRSEL3_POS (10U) +#define EMB_RLSSEL_PORTINRSEL3 (0x00000400UL) +#define EMB_RLSSEL_PORTINRSEL4_POS (11U) +#define EMB_RLSSEL_PORTINRSEL4 (0x00000800UL) + +/******************************************************************************* + Bit definition for Peripheral ETH +*******************************************************************************/ +/* Bit definition for ETH_MAC_IFCONFR register */ +#define ETH_MAC_IFCONFR_IFSEL_POS (0U) +#define ETH_MAC_IFCONFR_IFSEL (0x00000001UL) +#define ETH_MAC_IFCONFR_RCKINV_POS (4U) +#define ETH_MAC_IFCONFR_RCKINV (0x00000010UL) +#define ETH_MAC_IFCONFR_TCKINV_POS (5U) +#define ETH_MAC_IFCONFR_TCKINV (0x00000020UL) + +/* Bit definition for ETH_MAC_CONFIGR register */ +#define ETH_MAC_CONFIGR_RE_POS (2U) +#define ETH_MAC_CONFIGR_RE (0x00000004UL) +#define ETH_MAC_CONFIGR_TE_POS (3U) +#define ETH_MAC_CONFIGR_TE (0x00000008UL) +#define ETH_MAC_CONFIGR_DC_POS (4U) +#define ETH_MAC_CONFIGR_DC (0x00000010UL) +#define ETH_MAC_CONFIGR_BL_POS (5U) +#define ETH_MAC_CONFIGR_BL (0x00000060UL) +#define ETH_MAC_CONFIGR_BL_0 (0x00000020UL) +#define ETH_MAC_CONFIGR_BL_1 (0x00000040UL) +#define ETH_MAC_CONFIGR_ACS_POS (7U) +#define ETH_MAC_CONFIGR_ACS (0x00000080UL) +#define ETH_MAC_CONFIGR_DRTY_POS (9U) +#define ETH_MAC_CONFIGR_DRTY (0x00000200UL) +#define ETH_MAC_CONFIGR_IPCO_POS (10U) +#define ETH_MAC_CONFIGR_IPCO (0x00000400UL) +#define ETH_MAC_CONFIGR_DM_POS (11U) +#define ETH_MAC_CONFIGR_DM (0x00000800UL) +#define ETH_MAC_CONFIGR_LM_POS (12U) +#define ETH_MAC_CONFIGR_LM (0x00001000UL) +#define ETH_MAC_CONFIGR_DO_POS (13U) +#define ETH_MAC_CONFIGR_DO (0x00002000UL) +#define ETH_MAC_CONFIGR_FES_POS (14U) +#define ETH_MAC_CONFIGR_FES (0x00004000UL) +#define ETH_MAC_CONFIGR_DCRS_POS (16U) +#define ETH_MAC_CONFIGR_DCRS (0x00010000UL) +#define ETH_MAC_CONFIGR_IFG_POS (17U) +#define ETH_MAC_CONFIGR_IFG (0x000E0000UL) +#define ETH_MAC_CONFIGR_IFG_0 (0x00020000UL) +#define ETH_MAC_CONFIGR_IFG_1 (0x00040000UL) +#define ETH_MAC_CONFIGR_IFG_2 (0x00080000UL) +#define ETH_MAC_CONFIGR_MJB_POS (22U) +#define ETH_MAC_CONFIGR_MJB (0x00400000UL) +#define ETH_MAC_CONFIGR_MWD_POS (23U) +#define ETH_MAC_CONFIGR_MWD (0x00800000UL) +#define ETH_MAC_CONFIGR_CST_POS (25U) +#define ETH_MAC_CONFIGR_CST (0x02000000UL) +#define ETH_MAC_CONFIGR_SAIRC_POS (28U) +#define ETH_MAC_CONFIGR_SAIRC (0x70000000UL) +#define ETH_MAC_CONFIGR_SAIRC_0 (0x10000000UL) +#define ETH_MAC_CONFIGR_SAIRC_1 (0x20000000UL) +#define ETH_MAC_CONFIGR_SAIRC_2 (0x40000000UL) + +/* Bit definition for ETH_MAC_FLTCTLR register */ +#define ETH_MAC_FLTCTLR_PR_POS (0U) +#define ETH_MAC_FLTCTLR_PR (0x00000001UL) +#define ETH_MAC_FLTCTLR_HUC_POS (1U) +#define ETH_MAC_FLTCTLR_HUC (0x00000002UL) +#define ETH_MAC_FLTCTLR_HMC_POS (2U) +#define ETH_MAC_FLTCTLR_HMC (0x00000004UL) +#define ETH_MAC_FLTCTLR_DAIF_POS (3U) +#define ETH_MAC_FLTCTLR_DAIF (0x00000008UL) +#define ETH_MAC_FLTCTLR_PMF_POS (4U) +#define ETH_MAC_FLTCTLR_PMF (0x00000010UL) +#define ETH_MAC_FLTCTLR_DBF_POS (5U) +#define ETH_MAC_FLTCTLR_DBF (0x00000020UL) +#define ETH_MAC_FLTCTLR_PCF_POS (6U) +#define ETH_MAC_FLTCTLR_PCF (0x000000C0UL) +#define ETH_MAC_FLTCTLR_PCF_0 (0x00000040UL) +#define ETH_MAC_FLTCTLR_PCF_1 (0x00000080UL) +#define ETH_MAC_FLTCTLR_SAIF_POS (8U) +#define ETH_MAC_FLTCTLR_SAIF (0x00000100UL) +#define ETH_MAC_FLTCTLR_SAF_POS (9U) +#define ETH_MAC_FLTCTLR_SAF (0x00000200UL) +#define ETH_MAC_FLTCTLR_HPF_POS (10U) +#define ETH_MAC_FLTCTLR_HPF (0x00000400UL) +#define ETH_MAC_FLTCTLR_VTFE_POS (16U) +#define ETH_MAC_FLTCTLR_VTFE (0x00010000UL) +#define ETH_MAC_FLTCTLR_IPFE_POS (20U) +#define ETH_MAC_FLTCTLR_IPFE (0x00100000UL) +#define ETH_MAC_FLTCTLR_DNTU_POS (21U) +#define ETH_MAC_FLTCTLR_DNTU (0x00200000UL) +#define ETH_MAC_FLTCTLR_RA_POS (31U) +#define ETH_MAC_FLTCTLR_RA (0x80000000UL) + +/* Bit definition for ETH_MAC_HASHTHR register */ +#define ETH_MAC_HASHTHR_HTH (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_HASHTLR register */ +#define ETH_MAC_HASHTLR_HTL (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_SMIADDR register */ +#define ETH_MAC_SMIADDR_SMIB_POS (0U) +#define ETH_MAC_SMIADDR_SMIB (0x00000001UL) +#define ETH_MAC_SMIADDR_SMIW_POS (1U) +#define ETH_MAC_SMIADDR_SMIW (0x00000002UL) +#define ETH_MAC_SMIADDR_SMIC_POS (2U) +#define ETH_MAC_SMIADDR_SMIC (0x0000003CUL) +#define ETH_MAC_SMIADDR_SMIC_0 (0x00000004UL) +#define ETH_MAC_SMIADDR_SMIC_1 (0x00000008UL) +#define ETH_MAC_SMIADDR_SMIC_2 (0x00000010UL) +#define ETH_MAC_SMIADDR_SMIC_3 (0x00000020UL) +#define ETH_MAC_SMIADDR_SMIR_POS (6U) +#define ETH_MAC_SMIADDR_SMIR (0x000007C0UL) +#define ETH_MAC_SMIADDR_SMIR_0 (0x00000040UL) +#define ETH_MAC_SMIADDR_SMIR_1 (0x00000080UL) +#define ETH_MAC_SMIADDR_SMIR_2 (0x00000100UL) +#define ETH_MAC_SMIADDR_SMIR_3 (0x00000200UL) +#define ETH_MAC_SMIADDR_SMIR_4 (0x00000400UL) +#define ETH_MAC_SMIADDR_SMIA_POS (11U) +#define ETH_MAC_SMIADDR_SMIA (0x0000F800UL) +#define ETH_MAC_SMIADDR_SMIA_0 (0x00000800UL) +#define ETH_MAC_SMIADDR_SMIA_1 (0x00001000UL) +#define ETH_MAC_SMIADDR_SMIA_2 (0x00002000UL) +#define ETH_MAC_SMIADDR_SMIA_3 (0x00004000UL) +#define ETH_MAC_SMIADDR_SMIA_4 (0x00008000UL) + +/* Bit definition for ETH_MAC_SMIDATR register */ +#define ETH_MAC_SMIDATR_SMID (0x0000FFFFUL) + +/* Bit definition for ETH_MAC_FLOCTLR register */ +#define ETH_MAC_FLOCTLR_FCA_BPA_POS (0U) +#define ETH_MAC_FLOCTLR_FCA_BPA (0x00000001UL) +#define ETH_MAC_FLOCTLR_TFE_POS (1U) +#define ETH_MAC_FLOCTLR_TFE (0x00000002UL) +#define ETH_MAC_FLOCTLR_RFE_POS (2U) +#define ETH_MAC_FLOCTLR_RFE (0x00000004UL) +#define ETH_MAC_FLOCTLR_UNP_POS (3U) +#define ETH_MAC_FLOCTLR_UNP (0x00000008UL) +#define ETH_MAC_FLOCTLR_PLT_POS (4U) +#define ETH_MAC_FLOCTLR_PLT (0x00000030UL) +#define ETH_MAC_FLOCTLR_PLT_0 (0x00000010UL) +#define ETH_MAC_FLOCTLR_PLT_1 (0x00000020UL) +#define ETH_MAC_FLOCTLR_DZPQ_POS (7U) +#define ETH_MAC_FLOCTLR_DZPQ (0x00000080UL) +#define ETH_MAC_FLOCTLR_PAUSET_POS (16U) +#define ETH_MAC_FLOCTLR_PAUSET (0xFFFF0000UL) + +/* Bit definition for ETH_MAC_VTAFLTR register */ +#define ETH_MAC_VTAFLTR_VLFLT_POS (0U) +#define ETH_MAC_VTAFLTR_VLFLT (0x0000FFFFUL) +#define ETH_MAC_VTAFLTR_VTAL_POS (16U) +#define ETH_MAC_VTAFLTR_VTAL (0x00010000UL) +#define ETH_MAC_VTAFLTR_VTIM_POS (17U) +#define ETH_MAC_VTAFLTR_VTIM (0x00020000UL) +#define ETH_MAC_VTAFLTR_VTHM_POS (19U) +#define ETH_MAC_VTAFLTR_VTHM (0x00080000UL) + +/* Bit definition for ETH_MAC_MACSTSR register */ +#define ETH_MAC_MACSTSR_MREA_POS (0U) +#define ETH_MAC_MACSTSR_MREA (0x00000001UL) +#define ETH_MAC_MACSTSR_MRS_POS (1U) +#define ETH_MAC_MACSTSR_MRS (0x00000006UL) +#define ETH_MAC_MACSTSR_MRS_0 (0x00000002UL) +#define ETH_MAC_MACSTSR_MRS_1 (0x00000004UL) +#define ETH_MAC_MACSTSR_RFWA_POS (4U) +#define ETH_MAC_MACSTSR_RFWA (0x00000010UL) +#define ETH_MAC_MACSTSR_RFRS_POS (5U) +#define ETH_MAC_MACSTSR_RFRS (0x00000060UL) +#define ETH_MAC_MACSTSR_RFRS_0 (0x00000020UL) +#define ETH_MAC_MACSTSR_RFRS_1 (0x00000040UL) +#define ETH_MAC_MACSTSR_RFFL_POS (8U) +#define ETH_MAC_MACSTSR_RFFL (0x00000300UL) +#define ETH_MAC_MACSTSR_RFFL_0 (0x00000100UL) +#define ETH_MAC_MACSTSR_RFFL_1 (0x00000200UL) +#define ETH_MAC_MACSTSR_MTEA_POS (16U) +#define ETH_MAC_MACSTSR_MTEA (0x00010000UL) +#define ETH_MAC_MACSTSR_MTS_POS (17U) +#define ETH_MAC_MACSTSR_MTS (0x00060000UL) +#define ETH_MAC_MACSTSR_MTS_0 (0x00020000UL) +#define ETH_MAC_MACSTSR_MTS_1 (0x00040000UL) +#define ETH_MAC_MACSTSR_MTP_POS (19U) +#define ETH_MAC_MACSTSR_MTP (0x00080000UL) +#define ETH_MAC_MACSTSR_TFRS_POS (20U) +#define ETH_MAC_MACSTSR_TFRS (0x00300000UL) +#define ETH_MAC_MACSTSR_TFRS_0 (0x00100000UL) +#define ETH_MAC_MACSTSR_TFRS_1 (0x00200000UL) +#define ETH_MAC_MACSTSR_TFWA_POS (22U) +#define ETH_MAC_MACSTSR_TFWA (0x00400000UL) +#define ETH_MAC_MACSTSR_TFNE_POS (24U) +#define ETH_MAC_MACSTSR_TFNE (0x01000000UL) +#define ETH_MAC_MACSTSR_TFF_POS (25U) +#define ETH_MAC_MACSTSR_TFF (0x02000000UL) + +/* Bit definition for ETH_MAC_RTWKFFR register */ +#define ETH_MAC_RTWKFFR_WKUPFRMFT (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_PMTCTLR register */ +#define ETH_MAC_PMTCTLR_PWDN_POS (0U) +#define ETH_MAC_PMTCTLR_PWDN (0x00000001UL) +#define ETH_MAC_PMTCTLR_MPEN_POS (1U) +#define ETH_MAC_PMTCTLR_MPEN (0x00000002UL) +#define ETH_MAC_PMTCTLR_WKEN_POS (2U) +#define ETH_MAC_PMTCTLR_WKEN (0x00000004UL) +#define ETH_MAC_PMTCTLR_MPFR_POS (5U) +#define ETH_MAC_PMTCTLR_MPFR (0x00000020UL) +#define ETH_MAC_PMTCTLR_WKFR_POS (6U) +#define ETH_MAC_PMTCTLR_WKFR (0x00000040UL) +#define ETH_MAC_PMTCTLR_GLUB_POS (9U) +#define ETH_MAC_PMTCTLR_GLUB (0x00000200UL) +#define ETH_MAC_PMTCTLR_RTWKTR_POS (10U) +#define ETH_MAC_PMTCTLR_RTWKTR (0x00000400UL) +#define ETH_MAC_PMTCTLR_RTWKPT_POS (24U) +#define ETH_MAC_PMTCTLR_RTWKPT (0x07000000UL) +#define ETH_MAC_PMTCTLR_RTWKPT_0 (0x01000000UL) +#define ETH_MAC_PMTCTLR_RTWKPT_1 (0x02000000UL) +#define ETH_MAC_PMTCTLR_RTWKPT_2 (0x04000000UL) +#define ETH_MAC_PMTCTLR_RTWKFR_POS (31U) +#define ETH_MAC_PMTCTLR_RTWKFR (0x80000000UL) + +/* Bit definition for ETH_MAC_INTSTSR register */ +#define ETH_MAC_INTSTSR_PMTIS_POS (3U) +#define ETH_MAC_INTSTSR_PMTIS (0x00000008UL) +#define ETH_MAC_INTSTSR_MMCIS_POS (4U) +#define ETH_MAC_INTSTSR_MMCIS (0x00000010UL) +#define ETH_MAC_INTSTSR_MMCRXIS_POS (5U) +#define ETH_MAC_INTSTSR_MMCRXIS (0x00000020UL) +#define ETH_MAC_INTSTSR_MMCTXIS_POS (6U) +#define ETH_MAC_INTSTSR_MMCTXIS (0x00000040UL) +#define ETH_MAC_INTSTSR_TSPIS_POS (9U) +#define ETH_MAC_INTSTSR_TSPIS (0x00000200UL) + +/* Bit definition for ETH_MAC_INTMSKR register */ +#define ETH_MAC_INTMSKR_PMTIM_POS (3U) +#define ETH_MAC_INTMSKR_PMTIM (0x00000008UL) +#define ETH_MAC_INTMSKR_TSPIM_POS (9U) +#define ETH_MAC_INTMSKR_TSPIM (0x00000200UL) + +/* Bit definition for ETH_MAC_MACADHR0 register */ +#define ETH_MAC_MACADHR0_ADDRH0_POS (0U) +#define ETH_MAC_MACADHR0_ADDRH0 (0x0000FFFFUL) +#define ETH_MAC_MACADHR0_AE0_POS (31U) +#define ETH_MAC_MACADHR0_AE0 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR0 register */ +#define ETH_MAC_MACADLR0_ADDRL0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR1 register */ +#define ETH_MAC_MACADHR1_ADDRH1_POS (0U) +#define ETH_MAC_MACADHR1_ADDRH1 (0x0000FFFFUL) +#define ETH_MAC_MACADHR1_MBC1_POS (24U) +#define ETH_MAC_MACADHR1_MBC1 (0x3F000000UL) +#define ETH_MAC_MACADHR1_MBC1_0 (0x01000000UL) +#define ETH_MAC_MACADHR1_MBC1_1 (0x02000000UL) +#define ETH_MAC_MACADHR1_MBC1_2 (0x04000000UL) +#define ETH_MAC_MACADHR1_MBC1_3 (0x08000000UL) +#define ETH_MAC_MACADHR1_MBC1_4 (0x10000000UL) +#define ETH_MAC_MACADHR1_MBC1_5 (0x20000000UL) +#define ETH_MAC_MACADHR1_SA1_POS (30U) +#define ETH_MAC_MACADHR1_SA1 (0x40000000UL) +#define ETH_MAC_MACADHR1_AE1_POS (31U) +#define ETH_MAC_MACADHR1_AE1 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR1 register */ +#define ETH_MAC_MACADLR1_ADDRL1 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR2 register */ +#define ETH_MAC_MACADHR2_ADDRH2_POS (0U) +#define ETH_MAC_MACADHR2_ADDRH2 (0x0000FFFFUL) +#define ETH_MAC_MACADHR2_MBC2_POS (24U) +#define ETH_MAC_MACADHR2_MBC2 (0x3F000000UL) +#define ETH_MAC_MACADHR2_MBC2_0 (0x01000000UL) +#define ETH_MAC_MACADHR2_MBC2_1 (0x02000000UL) +#define ETH_MAC_MACADHR2_MBC2_2 (0x04000000UL) +#define ETH_MAC_MACADHR2_MBC2_3 (0x08000000UL) +#define ETH_MAC_MACADHR2_MBC2_4 (0x10000000UL) +#define ETH_MAC_MACADHR2_MBC2_5 (0x20000000UL) +#define ETH_MAC_MACADHR2_SA2_POS (30U) +#define ETH_MAC_MACADHR2_SA2 (0x40000000UL) +#define ETH_MAC_MACADHR2_AE2_POS (31U) +#define ETH_MAC_MACADHR2_AE2 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR2 register */ +#define ETH_MAC_MACADLR2_ADDRL2 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR3 register */ +#define ETH_MAC_MACADHR3_ADDRH3_POS (0U) +#define ETH_MAC_MACADHR3_ADDRH3 (0x0000FFFFUL) +#define ETH_MAC_MACADHR3_MBC3_POS (24U) +#define ETH_MAC_MACADHR3_MBC3 (0x3F000000UL) +#define ETH_MAC_MACADHR3_MBC3_0 (0x01000000UL) +#define ETH_MAC_MACADHR3_MBC3_1 (0x02000000UL) +#define ETH_MAC_MACADHR3_MBC3_2 (0x04000000UL) +#define ETH_MAC_MACADHR3_MBC3_3 (0x08000000UL) +#define ETH_MAC_MACADHR3_MBC3_4 (0x10000000UL) +#define ETH_MAC_MACADHR3_MBC3_5 (0x20000000UL) +#define ETH_MAC_MACADHR3_SA3_POS (30U) +#define ETH_MAC_MACADHR3_SA3 (0x40000000UL) +#define ETH_MAC_MACADHR3_AE3_POS (31U) +#define ETH_MAC_MACADHR3_AE3 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR3 register */ +#define ETH_MAC_MACADLR3_ADDRL3 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_MACADHR4 register */ +#define ETH_MAC_MACADHR4_ADDRH4_POS (0U) +#define ETH_MAC_MACADHR4_ADDRH4 (0x0000FFFFUL) +#define ETH_MAC_MACADHR4_MBC4_POS (24U) +#define ETH_MAC_MACADHR4_MBC4 (0x3F000000UL) +#define ETH_MAC_MACADHR4_MBC4_0 (0x01000000UL) +#define ETH_MAC_MACADHR4_MBC4_1 (0x02000000UL) +#define ETH_MAC_MACADHR4_MBC4_2 (0x04000000UL) +#define ETH_MAC_MACADHR4_MBC4_3 (0x08000000UL) +#define ETH_MAC_MACADHR4_MBC4_4 (0x10000000UL) +#define ETH_MAC_MACADHR4_MBC4_5 (0x20000000UL) +#define ETH_MAC_MACADHR4_SA4_POS (30U) +#define ETH_MAC_MACADHR4_SA4 (0x40000000UL) +#define ETH_MAC_MACADHR4_AE4_POS (31U) +#define ETH_MAC_MACADHR4_AE4 (0x80000000UL) + +/* Bit definition for ETH_MAC_MACADLR4 register */ +#define ETH_MAC_MACADLR4_ADDRL4 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MMC_MMCCTLR register */ +#define ETH_MMC_MMCCTLR_CRST_POS (0U) +#define ETH_MMC_MMCCTLR_CRST (0x00000001UL) +#define ETH_MMC_MMCCTLR_COS_POS (1U) +#define ETH_MMC_MMCCTLR_COS (0x00000002UL) +#define ETH_MMC_MMCCTLR_ROR_POS (2U) +#define ETH_MMC_MMCCTLR_ROR (0x00000004UL) +#define ETH_MMC_MMCCTLR_MCF_POS (3U) +#define ETH_MMC_MMCCTLR_MCF (0x00000008UL) +#define ETH_MMC_MMCCTLR_MCPSET_POS (4U) +#define ETH_MMC_MMCCTLR_MCPSET (0x00000010UL) +#define ETH_MMC_MMCCTLR_MCPSEL_POS (5U) +#define ETH_MMC_MMCCTLR_MCPSEL (0x00000020UL) + +/* Bit definition for ETH_MMC_REVSTSR register */ +#define ETH_MMC_REVSTSR_RXBGIS_POS (3U) +#define ETH_MMC_REVSTSR_RXBGIS (0x00000008UL) +#define ETH_MMC_REVSTSR_RXMGIS_POS (4U) +#define ETH_MMC_REVSTSR_RXMGIS (0x00000010UL) +#define ETH_MMC_REVSTSR_RXCEIS_POS (5U) +#define ETH_MMC_REVSTSR_RXCEIS (0x00000020UL) +#define ETH_MMC_REVSTSR_RXAEIS_POS (6U) +#define ETH_MMC_REVSTSR_RXAEIS (0x00000040UL) +#define ETH_MMC_REVSTSR_RXREIS_POS (7U) +#define ETH_MMC_REVSTSR_RXREIS (0x00000080UL) +#define ETH_MMC_REVSTSR_RXUGIS_POS (17U) +#define ETH_MMC_REVSTSR_RXUGIS (0x00020000UL) +#define ETH_MMC_REVSTSR_RXLEIS_POS (18U) +#define ETH_MMC_REVSTSR_RXLEIS (0x00040000UL) +#define ETH_MMC_REVSTSR_RXOEIS_POS (19U) +#define ETH_MMC_REVSTSR_RXOEIS (0x00080000UL) + +/* Bit definition for ETH_MMC_TRSSTSR register */ +#define ETH_MMC_TRSSTSR_TXBGIS_POS (2U) +#define ETH_MMC_TRSSTSR_TXBGIS (0x00000004UL) +#define ETH_MMC_TRSSTSR_TXMGIS_POS (3U) +#define ETH_MMC_TRSSTSR_TXMGIS (0x00000008UL) +#define ETH_MMC_TRSSTSR_TXDEEIS_POS (16U) +#define ETH_MMC_TRSSTSR_TXDEEIS (0x00010000UL) +#define ETH_MMC_TRSSTSR_TXLCEIS_POS (17U) +#define ETH_MMC_TRSSTSR_TXLCEIS (0x00020000UL) +#define ETH_MMC_TRSSTSR_TXECEIS_POS (18U) +#define ETH_MMC_TRSSTSR_TXECEIS (0x00040000UL) +#define ETH_MMC_TRSSTSR_TXCAEIS_POS (19U) +#define ETH_MMC_TRSSTSR_TXCAEIS (0x00080000UL) +#define ETH_MMC_TRSSTSR_TXUGIS_POS (21U) +#define ETH_MMC_TRSSTSR_TXUGIS (0x00200000UL) +#define ETH_MMC_TRSSTSR_TXEDEIS_POS (22U) +#define ETH_MMC_TRSSTSR_TXEDEIS (0x00400000UL) + +/* Bit definition for ETH_MMC_RITCTLR register */ +#define ETH_MMC_RITCTLR_RXBGIM_POS (3U) +#define ETH_MMC_RITCTLR_RXBGIM (0x00000008UL) +#define ETH_MMC_RITCTLR_RXMGIM_POS (4U) +#define ETH_MMC_RITCTLR_RXMGIM (0x00000010UL) +#define ETH_MMC_RITCTLR_RXCEIM_POS (5U) +#define ETH_MMC_RITCTLR_RXCEIM (0x00000020UL) +#define ETH_MMC_RITCTLR_RXAEIM_POS (6U) +#define ETH_MMC_RITCTLR_RXAEIM (0x00000040UL) +#define ETH_MMC_RITCTLR_RXREIM_POS (7U) +#define ETH_MMC_RITCTLR_RXREIM (0x00000080UL) +#define ETH_MMC_RITCTLR_RXUGIM_POS (17U) +#define ETH_MMC_RITCTLR_RXUGIM (0x00020000UL) +#define ETH_MMC_RITCTLR_RXLEIM_POS (18U) +#define ETH_MMC_RITCTLR_RXLEIM (0x00040000UL) +#define ETH_MMC_RITCTLR_RXOEIM_POS (19U) +#define ETH_MMC_RITCTLR_RXOEIM (0x00080000UL) + +/* Bit definition for ETH_MMC_TITCTLR register */ +#define ETH_MMC_TITCTLR_TXBGIM_POS (2U) +#define ETH_MMC_TITCTLR_TXBGIM (0x00000004UL) +#define ETH_MMC_TITCTLR_TXMGIM_POS (3U) +#define ETH_MMC_TITCTLR_TXMGIM (0x00000008UL) +#define ETH_MMC_TITCTLR_TXDEEIM_POS (16U) +#define ETH_MMC_TITCTLR_TXDEEIM (0x00010000UL) +#define ETH_MMC_TITCTLR_TXLCEIM_POS (17U) +#define ETH_MMC_TITCTLR_TXLCEIM (0x00020000UL) +#define ETH_MMC_TITCTLR_TXECEIM_POS (18U) +#define ETH_MMC_TITCTLR_TXECEIM (0x00040000UL) +#define ETH_MMC_TITCTLR_TXCAEIM_POS (19U) +#define ETH_MMC_TITCTLR_TXCAEIM (0x00080000UL) +#define ETH_MMC_TITCTLR_TXUGIM_POS (21U) +#define ETH_MMC_TITCTLR_TXUGIM (0x00200000UL) +#define ETH_MMC_TITCTLR_TXEDEIM_POS (22U) +#define ETH_MMC_TITCTLR_TXEDEIM (0x00400000UL) + +/* Bit definition for ETH_MMC_TXBRGFR register */ +#define ETH_MMC_TXBRGFR_TXBRGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXMUGFR register */ +#define ETH_MMC_TXMUGFR_TXMUGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXDEEFR register */ +#define ETH_MMC_TXDEEFR_TXDEECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXLCEFR register */ +#define ETH_MMC_TXLCEFR_TXLCECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXECEFR register */ +#define ETH_MMC_TXECEFR_TXECECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXCAEFR register */ +#define ETH_MMC_TXCAEFR_TXCAECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXUNGFR register */ +#define ETH_MMC_TXUNGFR_TXUNGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_TXEDEFR register */ +#define ETH_MMC_TXEDEFR_TXEDECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXBRGFR register */ +#define ETH_MMC_RXBRGFR_RXBRGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXMUGFR register */ +#define ETH_MMC_RXMUGFR_RXMUGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXCREFR register */ +#define ETH_MMC_RXCREFR_RXCRECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXALEFR register */ +#define ETH_MMC_RXALEFR_RXALECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXRUEFR register */ +#define ETH_MMC_RXRUEFR_RXRUECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXUNGFR register */ +#define ETH_MMC_RXUNGFR_RXUNGCNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXLEEFR register */ +#define ETH_MMC_RXLEEFR_RXLEECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MMC_RXOREFR register */ +#define ETH_MMC_RXOREFR_RXORECNT (0x0000FFFFUL) + +/* Bit definition for ETH_MAC_L34CTLR register */ +#define ETH_MAC_L34CTLR_L3PEN_POS (0U) +#define ETH_MAC_L34CTLR_L3PEN (0x00000001UL) +#define ETH_MAC_L34CTLR_L3SAM_POS (2U) +#define ETH_MAC_L34CTLR_L3SAM (0x00000004UL) +#define ETH_MAC_L34CTLR_L3SAIM_POS (3U) +#define ETH_MAC_L34CTLR_L3SAIM (0x00000008UL) +#define ETH_MAC_L34CTLR_L3DAM_POS (4U) +#define ETH_MAC_L34CTLR_L3DAM (0x00000010UL) +#define ETH_MAC_L34CTLR_L3DAIM_POS (5U) +#define ETH_MAC_L34CTLR_L3DAIM (0x00000020UL) +#define ETH_MAC_L34CTLR_L3HSBM_POS (6U) +#define ETH_MAC_L34CTLR_L3HSBM (0x000007C0UL) +#define ETH_MAC_L34CTLR_L3HSBM_0 (0x00000040UL) +#define ETH_MAC_L34CTLR_L3HSBM_1 (0x00000080UL) +#define ETH_MAC_L34CTLR_L3HSBM_2 (0x00000100UL) +#define ETH_MAC_L34CTLR_L3HSBM_3 (0x00000200UL) +#define ETH_MAC_L34CTLR_L3HSBM_4 (0x00000400UL) +#define ETH_MAC_L34CTLR_L3HDBM_POS (11U) +#define ETH_MAC_L34CTLR_L3HDBM (0x0000F800UL) +#define ETH_MAC_L34CTLR_L3HDBM_0 (0x00000800UL) +#define ETH_MAC_L34CTLR_L3HDBM_1 (0x00001000UL) +#define ETH_MAC_L34CTLR_L3HDBM_2 (0x00002000UL) +#define ETH_MAC_L34CTLR_L3HDBM_3 (0x00004000UL) +#define ETH_MAC_L34CTLR_L3HDBM_4 (0x00008000UL) +#define ETH_MAC_L34CTLR_L4PEN_POS (16U) +#define ETH_MAC_L34CTLR_L4PEN (0x00010000UL) +#define ETH_MAC_L34CTLR_L4SPM_POS (18U) +#define ETH_MAC_L34CTLR_L4SPM (0x00040000UL) +#define ETH_MAC_L34CTLR_L4SPIM_POS (19U) +#define ETH_MAC_L34CTLR_L4SPIM (0x00080000UL) +#define ETH_MAC_L34CTLR_L4DPM_POS (20U) +#define ETH_MAC_L34CTLR_L4DPM (0x00100000UL) +#define ETH_MAC_L34CTLR_L4DPIM_POS (21U) +#define ETH_MAC_L34CTLR_L4DPIM (0x00200000UL) + +/* Bit definition for ETH_MAC_L4PORTR register */ +#define ETH_MAC_L4PORTR_L4SPVAL_POS (0U) +#define ETH_MAC_L4PORTR_L4SPVAL (0x0000FFFFUL) +#define ETH_MAC_L4PORTR_L4DPVAL_POS (16U) +#define ETH_MAC_L4PORTR_L4DPVAL (0xFFFF0000UL) + +/* Bit definition for ETH_MAC_L3ADDRR0 register */ +#define ETH_MAC_L3ADDRR0_L3ADDR0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_L3ADDRR1 register */ +#define ETH_MAC_L3ADDRR1_L3ADDR2 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_L3ADDRR2 register */ +#define ETH_MAC_L3ADDRR2_L3ADDR2 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_L3ADDRR3 register */ +#define ETH_MAC_L3ADDRR3_L3ADDR3 (0xFFFFFFFFUL) + +/* Bit definition for ETH_MAC_VTACTLR register */ +#define ETH_MAC_VTACTLR_VLANV_POS (0U) +#define ETH_MAC_VTACTLR_VLANV (0x0000FFFFUL) +#define ETH_MAC_VTACTLR_VLANC_POS (16U) +#define ETH_MAC_VTACTLR_VLANC (0x00030000UL) +#define ETH_MAC_VTACTLR_VLANC_0 (0x00010000UL) +#define ETH_MAC_VTACTLR_VLANC_1 (0x00020000UL) +#define ETH_MAC_VTACTLR_VLANS_POS (18U) +#define ETH_MAC_VTACTLR_VLANS (0x00040000UL) + +/* Bit definition for ETH_MAC_VLAHTBR register */ +#define ETH_MAC_VLAHTBR_VLHT (0x0000FFFFUL) + +/* Bit definition for ETH_PTP_TSPCTLR register */ +#define ETH_PTP_TSPCTLR_TSPEN_POS (0U) +#define ETH_PTP_TSPCTLR_TSPEN (0x00000001UL) +#define ETH_PTP_TSPCTLR_TSPUPSEL_POS (1U) +#define ETH_PTP_TSPCTLR_TSPUPSEL (0x00000002UL) +#define ETH_PTP_TSPCTLR_TSPINI_POS (2U) +#define ETH_PTP_TSPCTLR_TSPINI (0x00000004UL) +#define ETH_PTP_TSPCTLR_TSPUP_POS (3U) +#define ETH_PTP_TSPCTLR_TSPUP (0x00000008UL) +#define ETH_PTP_TSPCTLR_TSPINT_POS (4U) +#define ETH_PTP_TSPCTLR_TSPINT (0x00000010UL) +#define ETH_PTP_TSPCTLR_TSPADUP_POS (5U) +#define ETH_PTP_TSPCTLR_TSPADUP (0x00000020UL) +#define ETH_PTP_TSPCTLR_TSPEALL_POS (8U) +#define ETH_PTP_TSPCTLR_TSPEALL (0x00000100UL) +#define ETH_PTP_TSPCTLR_TSPSSR_POS (9U) +#define ETH_PTP_TSPCTLR_TSPSSR (0x00000200UL) +#define ETH_PTP_TSPCTLR_TSPVER_POS (10U) +#define ETH_PTP_TSPCTLR_TSPVER (0x00000400UL) +#define ETH_PTP_TSPCTLR_TSPOVETH_POS (11U) +#define ETH_PTP_TSPCTLR_TSPOVETH (0x00000800UL) +#define ETH_PTP_TSPCTLR_TSPOVIPV6_POS (12U) +#define ETH_PTP_TSPCTLR_TSPOVIPV6 (0x00001000UL) +#define ETH_PTP_TSPCTLR_TSPOVIPV4_POS (13U) +#define ETH_PTP_TSPCTLR_TSPOVIPV4 (0x00002000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_POS (14U) +#define ETH_PTP_TSPCTLR_TSPMTSEL (0x0003C000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_0 (0x00004000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_1 (0x00008000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_2 (0x00010000UL) +#define ETH_PTP_TSPCTLR_TSPMTSEL_3 (0x00020000UL) +#define ETH_PTP_TSPCTLR_TSPADF_POS (18U) +#define ETH_PTP_TSPCTLR_TSPADF (0x00040000UL) + +/* Bit definition for ETH_PTP_TSPNSAR register */ +#define ETH_PTP_TSPNSAR_TSPNSEADD (0x000000FFUL) + +/* Bit definition for ETH_PTP_TMSSECR register */ +#define ETH_PTP_TMSSECR_TSPSYSSEC (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMSNSER register */ +#define ETH_PTP_TMSNSER_TSPSYSNSEC (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMUSECR register */ +#define ETH_PTP_TMUSECR_TSPUPSEC (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMUNSER register */ +#define ETH_PTP_TMUNSER_TSPUPNSE_POS (0U) +#define ETH_PTP_TMUNSER_TSPUPNSE (0x7FFFFFFFUL) +#define ETH_PTP_TMUNSER_TSPUPNS_POS (31U) +#define ETH_PTP_TMUNSER_TSPUPNS (0x80000000UL) + +/* Bit definition for ETH_PTP_TSPADDR register */ +#define ETH_PTP_TSPADDR_TSPADD (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMTSECR0 register */ +#define ETH_PTP_TMTSECR0_TSPTAGSEC0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMTNSER0 register */ +#define ETH_PTP_TMTNSER0_TSPTAGNSEC0 (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TSPSTSR register */ +#define ETH_PTP_TSPSTSR_TSOVF_POS (0U) +#define ETH_PTP_TSPSTSR_TSOVF (0x00000001UL) +#define ETH_PTP_TSPSTSR_TSTAR0_POS (1U) +#define ETH_PTP_TSPSTSR_TSTAR0 (0x00000002UL) +#define ETH_PTP_TSPSTSR_TSERR0_POS (3U) +#define ETH_PTP_TSPSTSR_TSERR0 (0x00000008UL) +#define ETH_PTP_TSPSTSR_TSTAR1_POS (4U) +#define ETH_PTP_TSPSTSR_TSTAR1 (0x00000010UL) +#define ETH_PTP_TSPSTSR_TSERR1_POS (5U) +#define ETH_PTP_TSPSTSR_TSERR1 (0x00000020UL) + +/* Bit definition for ETH_PTP_PPSCTLR register */ +#define ETH_PTP_PPSCTLR_PPSFRE0_POS (0U) +#define ETH_PTP_PPSCTLR_PPSFRE0 (0x0000000FUL) +#define ETH_PTP_PPSCTLR_PPSFRE0_0 (0x00000001UL) +#define ETH_PTP_PPSCTLR_PPSFRE0_1 (0x00000002UL) +#define ETH_PTP_PPSCTLR_PPSFRE0_2 (0x00000004UL) +#define ETH_PTP_PPSCTLR_PPSFRE0_3 (0x00000008UL) +#define ETH_PTP_PPSCTLR_PPSOMD_POS (4U) +#define ETH_PTP_PPSCTLR_PPSOMD (0x00000010UL) +#define ETH_PTP_PPSCTLR_TT0SEL_POS (5U) +#define ETH_PTP_PPSCTLR_TT0SEL (0x00000060UL) +#define ETH_PTP_PPSCTLR_TT0SEL_0 (0x00000020UL) +#define ETH_PTP_PPSCTLR_TT0SEL_1 (0x00000040UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_POS (8U) +#define ETH_PTP_PPSCTLR_PPSFRE1 (0x00000700UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_0 (0x00000100UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_1 (0x00000200UL) +#define ETH_PTP_PPSCTLR_PPSFRE1_2 (0x00000400UL) +#define ETH_PTP_PPSCTLR_TT1SEL_POS (13U) +#define ETH_PTP_PPSCTLR_TT1SEL (0x00006000UL) +#define ETH_PTP_PPSCTLR_TT1SEL_0 (0x00002000UL) +#define ETH_PTP_PPSCTLR_TT1SEL_1 (0x00004000UL) + +/* Bit definition for ETH_PTP_TMTSECR1 register */ +#define ETH_PTP_TMTSECR1_TSPTAGSEC1 (0xFFFFFFFFUL) + +/* Bit definition for ETH_PTP_TMTNSER1 register */ +#define ETH_PTP_TMTNSER1_TSPTAGNSEC1 (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_BUSMODR register */ +#define ETH_DMA_BUSMODR_SWR_POS (0U) +#define ETH_DMA_BUSMODR_SWR (0x00000001UL) +#define ETH_DMA_BUSMODR_DMAA_POS (1U) +#define ETH_DMA_BUSMODR_DMAA (0x00000002UL) +#define ETH_DMA_BUSMODR_DSL_POS (2U) +#define ETH_DMA_BUSMODR_DSL (0x0000007CUL) +#define ETH_DMA_BUSMODR_DSL_0 (0x00000004UL) +#define ETH_DMA_BUSMODR_DSL_1 (0x00000008UL) +#define ETH_DMA_BUSMODR_DSL_2 (0x00000010UL) +#define ETH_DMA_BUSMODR_DSL_3 (0x00000020UL) +#define ETH_DMA_BUSMODR_DSL_4 (0x00000040UL) +#define ETH_DMA_BUSMODR_DSEN_POS (7U) +#define ETH_DMA_BUSMODR_DSEN (0x00000080UL) +#define ETH_DMA_BUSMODR_TPBL_POS (8U) +#define ETH_DMA_BUSMODR_TPBL (0x00003F00UL) +#define ETH_DMA_BUSMODR_TPBL_0 (0x00000100UL) +#define ETH_DMA_BUSMODR_TPBL_1 (0x00000200UL) +#define ETH_DMA_BUSMODR_TPBL_2 (0x00000400UL) +#define ETH_DMA_BUSMODR_TPBL_3 (0x00000800UL) +#define ETH_DMA_BUSMODR_TPBL_4 (0x00001000UL) +#define ETH_DMA_BUSMODR_TPBL_5 (0x00002000UL) +#define ETH_DMA_BUSMODR_PRAT_POS (14U) +#define ETH_DMA_BUSMODR_PRAT (0x0000C000UL) +#define ETH_DMA_BUSMODR_PRAT_0 (0x00004000UL) +#define ETH_DMA_BUSMODR_PRAT_1 (0x00008000UL) +#define ETH_DMA_BUSMODR_FBST_POS (16U) +#define ETH_DMA_BUSMODR_FBST (0x00010000UL) +#define ETH_DMA_BUSMODR_RPBL_POS (17U) +#define ETH_DMA_BUSMODR_RPBL (0x007E0000UL) +#define ETH_DMA_BUSMODR_RPBL_0 (0x00020000UL) +#define ETH_DMA_BUSMODR_RPBL_1 (0x00040000UL) +#define ETH_DMA_BUSMODR_RPBL_2 (0x00080000UL) +#define ETH_DMA_BUSMODR_RPBL_3 (0x00100000UL) +#define ETH_DMA_BUSMODR_RPBL_4 (0x00200000UL) +#define ETH_DMA_BUSMODR_RPBL_5 (0x00400000UL) +#define ETH_DMA_BUSMODR_SPBL_POS (23U) +#define ETH_DMA_BUSMODR_SPBL (0x00800000UL) +#define ETH_DMA_BUSMODR_M8PBL_POS (24U) +#define ETH_DMA_BUSMODR_M8PBL (0x01000000UL) +#define ETH_DMA_BUSMODR_AAL_POS (25U) +#define ETH_DMA_BUSMODR_AAL (0x02000000UL) +#define ETH_DMA_BUSMODR_MBST_POS (26U) +#define ETH_DMA_BUSMODR_MBST (0x04000000UL) +#define ETH_DMA_BUSMODR_TXPR_POS (27U) +#define ETH_DMA_BUSMODR_TXPR (0x08000000UL) + +/* Bit definition for ETH_DMA_TXPOLLR register */ +#define ETH_DMA_TXPOLLR_TXPOLL (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_RXPOLLR register */ +#define ETH_DMA_RXPOLLR_RXPOLL (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_RXDLADR register */ +#define ETH_DMA_RXDLADR_RXDLAD (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_TXDLADR register */ +#define ETH_DMA_TXDLADR_TXDLAD (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_DMASTSR register */ +#define ETH_DMA_DMASTSR_TIS_POS (0U) +#define ETH_DMA_DMASTSR_TIS (0x00000001UL) +#define ETH_DMA_DMASTSR_TSS_POS (1U) +#define ETH_DMA_DMASTSR_TSS (0x00000002UL) +#define ETH_DMA_DMASTSR_TUS_POS (2U) +#define ETH_DMA_DMASTSR_TUS (0x00000004UL) +#define ETH_DMA_DMASTSR_TJS_POS (3U) +#define ETH_DMA_DMASTSR_TJS (0x00000008UL) +#define ETH_DMA_DMASTSR_OVS_POS (4U) +#define ETH_DMA_DMASTSR_OVS (0x00000010UL) +#define ETH_DMA_DMASTSR_UNS_POS (5U) +#define ETH_DMA_DMASTSR_UNS (0x00000020UL) +#define ETH_DMA_DMASTSR_RIS_POS (6U) +#define ETH_DMA_DMASTSR_RIS (0x00000040UL) +#define ETH_DMA_DMASTSR_RUS_POS (7U) +#define ETH_DMA_DMASTSR_RUS (0x00000080UL) +#define ETH_DMA_DMASTSR_RSS_POS (8U) +#define ETH_DMA_DMASTSR_RSS (0x00000100UL) +#define ETH_DMA_DMASTSR_RWS_POS (9U) +#define ETH_DMA_DMASTSR_RWS (0x00000200UL) +#define ETH_DMA_DMASTSR_ETS_POS (10U) +#define ETH_DMA_DMASTSR_ETS (0x00000400UL) +#define ETH_DMA_DMASTSR_FBS_POS (13U) +#define ETH_DMA_DMASTSR_FBS (0x00002000UL) +#define ETH_DMA_DMASTSR_ERS_POS (14U) +#define ETH_DMA_DMASTSR_ERS (0x00004000UL) +#define ETH_DMA_DMASTSR_AIS_POS (15U) +#define ETH_DMA_DMASTSR_AIS (0x00008000UL) +#define ETH_DMA_DMASTSR_NIS_POS (16U) +#define ETH_DMA_DMASTSR_NIS (0x00010000UL) +#define ETH_DMA_DMASTSR_RSTS_POS (17U) +#define ETH_DMA_DMASTSR_RSTS (0x000E0000UL) +#define ETH_DMA_DMASTSR_RSTS_0 (0x00020000UL) +#define ETH_DMA_DMASTSR_RSTS_1 (0x00040000UL) +#define ETH_DMA_DMASTSR_RSTS_2 (0x00080000UL) +#define ETH_DMA_DMASTSR_TSTS_POS (20U) +#define ETH_DMA_DMASTSR_TSTS (0x00700000UL) +#define ETH_DMA_DMASTSR_TSTS_0 (0x00100000UL) +#define ETH_DMA_DMASTSR_TSTS_1 (0x00200000UL) +#define ETH_DMA_DMASTSR_TSTS_2 (0x00400000UL) +#define ETH_DMA_DMASTSR_EBUS_POS (23U) +#define ETH_DMA_DMASTSR_EBUS (0x03800000UL) +#define ETH_DMA_DMASTSR_EBUS_0 (0x00800000UL) +#define ETH_DMA_DMASTSR_EBUS_1 (0x01000000UL) +#define ETH_DMA_DMASTSR_EBUS_2 (0x02000000UL) +#define ETH_DMA_DMASTSR_MMCS_POS (27U) +#define ETH_DMA_DMASTSR_MMCS (0x08000000UL) +#define ETH_DMA_DMASTSR_PMTS_POS (28U) +#define ETH_DMA_DMASTSR_PMTS (0x10000000UL) +#define ETH_DMA_DMASTSR_PTPS_POS (29U) +#define ETH_DMA_DMASTSR_PTPS (0x20000000UL) + +/* Bit definition for ETH_DMA_OPRMODR register */ +#define ETH_DMA_OPRMODR_STR_POS (1U) +#define ETH_DMA_OPRMODR_STR (0x00000002UL) +#define ETH_DMA_OPRMODR_OSF_POS (2U) +#define ETH_DMA_OPRMODR_OSF (0x00000004UL) +#define ETH_DMA_OPRMODR_RTC_POS (3U) +#define ETH_DMA_OPRMODR_RTC (0x00000018UL) +#define ETH_DMA_OPRMODR_RTC_0 (0x00000008UL) +#define ETH_DMA_OPRMODR_RTC_1 (0x00000010UL) +#define ETH_DMA_OPRMODR_DGF_POS (5U) +#define ETH_DMA_OPRMODR_DGF (0x00000020UL) +#define ETH_DMA_OPRMODR_FUF_POS (6U) +#define ETH_DMA_OPRMODR_FUF (0x00000040UL) +#define ETH_DMA_OPRMODR_FEF_POS (7U) +#define ETH_DMA_OPRMODR_FEF (0x00000080UL) +#define ETH_DMA_OPRMODR_STT_POS (13U) +#define ETH_DMA_OPRMODR_STT (0x00002000UL) +#define ETH_DMA_OPRMODR_TTC_POS (14U) +#define ETH_DMA_OPRMODR_TTC (0x0001C000UL) +#define ETH_DMA_OPRMODR_TTC_0 (0x00004000UL) +#define ETH_DMA_OPRMODR_TTC_1 (0x00008000UL) +#define ETH_DMA_OPRMODR_TTC_2 (0x00010000UL) +#define ETH_DMA_OPRMODR_FTF_POS (20U) +#define ETH_DMA_OPRMODR_FTF (0x00100000UL) +#define ETH_DMA_OPRMODR_TSF_POS (21U) +#define ETH_DMA_OPRMODR_TSF (0x00200000UL) +#define ETH_DMA_OPRMODR_DFRF_POS (24U) +#define ETH_DMA_OPRMODR_DFRF (0x01000000UL) +#define ETH_DMA_OPRMODR_RSF_POS (25U) +#define ETH_DMA_OPRMODR_RSF (0x02000000UL) +#define ETH_DMA_OPRMODR_DTCOE_POS (26U) +#define ETH_DMA_OPRMODR_DTCOE (0x04000000UL) + +/* Bit definition for ETH_DMA_INTENAR register */ +#define ETH_DMA_INTENAR_TIE_POS (0U) +#define ETH_DMA_INTENAR_TIE (0x00000001UL) +#define ETH_DMA_INTENAR_TSE_POS (1U) +#define ETH_DMA_INTENAR_TSE (0x00000002UL) +#define ETH_DMA_INTENAR_TUE_POS (2U) +#define ETH_DMA_INTENAR_TUE (0x00000004UL) +#define ETH_DMA_INTENAR_TJE_POS (3U) +#define ETH_DMA_INTENAR_TJE (0x00000008UL) +#define ETH_DMA_INTENAR_OVE_POS (4U) +#define ETH_DMA_INTENAR_OVE (0x00000010UL) +#define ETH_DMA_INTENAR_UNE_POS (5U) +#define ETH_DMA_INTENAR_UNE (0x00000020UL) +#define ETH_DMA_INTENAR_RIE_POS (6U) +#define ETH_DMA_INTENAR_RIE (0x00000040UL) +#define ETH_DMA_INTENAR_RUE_POS (7U) +#define ETH_DMA_INTENAR_RUE (0x00000080UL) +#define ETH_DMA_INTENAR_RSE_POS (8U) +#define ETH_DMA_INTENAR_RSE (0x00000100UL) +#define ETH_DMA_INTENAR_RWE_POS (9U) +#define ETH_DMA_INTENAR_RWE (0x00000200UL) +#define ETH_DMA_INTENAR_ETE_POS (10U) +#define ETH_DMA_INTENAR_ETE (0x00000400UL) +#define ETH_DMA_INTENAR_FBE_POS (13U) +#define ETH_DMA_INTENAR_FBE (0x00002000UL) +#define ETH_DMA_INTENAR_ERE_POS (14U) +#define ETH_DMA_INTENAR_ERE (0x00004000UL) +#define ETH_DMA_INTENAR_AIE_POS (15U) +#define ETH_DMA_INTENAR_AIE (0x00008000UL) +#define ETH_DMA_INTENAR_NIE_POS (16U) +#define ETH_DMA_INTENAR_NIE (0x00010000UL) + +/* Bit definition for ETH_DMA_RFRCNTR register */ +#define ETH_DMA_RFRCNTR_UNACNT_POS (0U) +#define ETH_DMA_RFRCNTR_UNACNT (0x0000FFFFUL) +#define ETH_DMA_RFRCNTR_UNAOVF_POS (16U) +#define ETH_DMA_RFRCNTR_UNAOVF (0x00010000UL) +#define ETH_DMA_RFRCNTR_OVFCNT_POS (17U) +#define ETH_DMA_RFRCNTR_OVFCNT (0x0FFE0000UL) +#define ETH_DMA_RFRCNTR_OVFOVF_POS (28U) +#define ETH_DMA_RFRCNTR_OVFOVF (0x10000000UL) + +/* Bit definition for ETH_DMA_REVWDTR register */ +#define ETH_DMA_REVWDTR_RIWT (0x000000FFUL) + +/* Bit definition for ETH_DMA_CHTXDER register */ +#define ETH_DMA_CHTXDER_CHTXDE (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_CHRXDER register */ +#define ETH_DMA_CHRXDER_CHRXDE (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_CHTXBFR register */ +#define ETH_DMA_CHTXBFR_CHTXBF (0xFFFFFFFFUL) + +/* Bit definition for ETH_DMA_CHRXBFR register */ +#define ETH_DMA_CHRXBFR_CHRXBF (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral FCM +*******************************************************************************/ +/* Bit definition for FCM_LVR register */ +#define FCM_LVR_LVR (0x0000FFFFUL) + +/* Bit definition for FCM_UVR register */ +#define FCM_UVR_UVR (0x0000FFFFUL) + +/* Bit definition for FCM_CNTR register */ +#define FCM_CNTR_CNTR (0x0000FFFFUL) + +/* Bit definition for FCM_STR register */ +#define FCM_STR_START (0x00000001UL) + +/* Bit definition for FCM_MCCR register */ +#define FCM_MCCR_MDIVS_POS (0U) +#define FCM_MCCR_MDIVS (0x00000003UL) +#define FCM_MCCR_MCKS_POS (4U) +#define FCM_MCCR_MCKS (0x000000F0UL) + +/* Bit definition for FCM_RCCR register */ +#define FCM_RCCR_RDIVS_POS (0U) +#define FCM_RCCR_RDIVS (0x00000003UL) +#define FCM_RCCR_RCKS_POS (3U) +#define FCM_RCCR_RCKS (0x00000078UL) +#define FCM_RCCR_INEXS_POS (7U) +#define FCM_RCCR_INEXS (0x00000080UL) +#define FCM_RCCR_DNFS_POS (8U) +#define FCM_RCCR_DNFS (0x00000300UL) +#define FCM_RCCR_DNFS_0 (0x00000100UL) +#define FCM_RCCR_DNFS_1 (0x00000200UL) +#define FCM_RCCR_EDGES_POS (12U) +#define FCM_RCCR_EDGES (0x00003000UL) +#define FCM_RCCR_EDGES_0 (0x00001000UL) +#define FCM_RCCR_EDGES_1 (0x00002000UL) +#define FCM_RCCR_EXREFE_POS (15U) +#define FCM_RCCR_EXREFE (0x00008000UL) + +/* Bit definition for FCM_RIER register */ +#define FCM_RIER_ERRIE_POS (0U) +#define FCM_RIER_ERRIE (0x00000001UL) +#define FCM_RIER_MENDIE_POS (1U) +#define FCM_RIER_MENDIE (0x00000002UL) +#define FCM_RIER_OVFIE_POS (2U) +#define FCM_RIER_OVFIE (0x00000004UL) +#define FCM_RIER_ERRINTRS_POS (4U) +#define FCM_RIER_ERRINTRS (0x00000010UL) +#define FCM_RIER_ERRE_POS (7U) +#define FCM_RIER_ERRE (0x00000080UL) + +/* Bit definition for FCM_SR register */ +#define FCM_SR_ERRF_POS (0U) +#define FCM_SR_ERRF (0x00000001UL) +#define FCM_SR_MENDF_POS (1U) +#define FCM_SR_MENDF (0x00000002UL) +#define FCM_SR_OVF_POS (2U) +#define FCM_SR_OVF (0x00000004UL) + +/* Bit definition for FCM_CLR register */ +#define FCM_CLR_ERRFCLR_POS (0U) +#define FCM_CLR_ERRFCLR (0x00000001UL) +#define FCM_CLR_MENDFCLR_POS (1U) +#define FCM_CLR_MENDFCLR (0x00000002UL) +#define FCM_CLR_OVFCLR_POS (2U) +#define FCM_CLR_OVFCLR (0x00000004UL) + +/******************************************************************************* + Bit definition for Peripheral FMAC +*******************************************************************************/ +/* Bit definition for FMAC_ENR register */ +#define FMAC_ENR_FMACEN (0x00000001UL) + +/* Bit definition for FMAC_CTR register */ +#define FMAC_CTR_STAGE_NUM_POS (0U) +#define FMAC_CTR_STAGE_NUM (0x0000001FUL) +#define FMAC_CTR_SHIFT_POS (8U) +#define FMAC_CTR_SHIFT (0x00001F00UL) + +/* Bit definition for FMAC_IER register */ +#define FMAC_IER_INTEN (0x00000001UL) + +/* Bit definition for FMAC_DTR register */ +#define FMAC_DTR_DIN (0x0000FFFFUL) + +/* Bit definition for FMAC_RTR0 register */ +#define FMAC_RTR0 (0xFFFFFFFFUL) + +/* Bit definition for FMAC_RTR1 register */ +#define FMAC_RTR1 (0xFFFFFFFFUL) + +/* Bit definition for FMAC_STR register */ +#define FMAC_STR_READY_POS (31U) +#define FMAC_STR_READY (0x80000000UL) + +/* Bit definition for FMAC_COR0 register */ +#define FMAC_COR0_CIN0 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR1 register */ +#define FMAC_COR1_CIN1 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR2 register */ +#define FMAC_COR2_CIN2 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR3 register */ +#define FMAC_COR3_CIN3 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR4 register */ +#define FMAC_COR4_CIN4 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR5 register */ +#define FMAC_COR5_CIN5 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR6 register */ +#define FMAC_COR6_CIN6 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR7 register */ +#define FMAC_COR7_CIN7 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR8 register */ +#define FMAC_COR8_CIN8 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR9 register */ +#define FMAC_COR9_CIN9 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR10 register */ +#define FMAC_COR10_CIN10 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR11 register */ +#define FMAC_COR11_CIN11 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR12 register */ +#define FMAC_COR12_CIN12 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR13 register */ +#define FMAC_COR13_CIN13 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR14 register */ +#define FMAC_COR14_CIN14 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR15 register */ +#define FMAC_COR15_CIN15 (0x0000FFFFUL) + +/* Bit definition for FMAC_COR16 register */ +#define FMAC_COR16_CIN16 (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral GPIO +*******************************************************************************/ +/* Bit definition for GPIO_PIDRA register */ +#define GPIO_PIDRA_PIN00_POS (0U) +#define GPIO_PIDRA_PIN00 (0x0001U) +#define GPIO_PIDRA_PIN01_POS (1U) +#define GPIO_PIDRA_PIN01 (0x0002U) +#define GPIO_PIDRA_PIN02_POS (2U) +#define GPIO_PIDRA_PIN02 (0x0004U) +#define GPIO_PIDRA_PIN03_POS (3U) +#define GPIO_PIDRA_PIN03 (0x0008U) +#define GPIO_PIDRA_PIN04_POS (4U) +#define GPIO_PIDRA_PIN04 (0x0010U) +#define GPIO_PIDRA_PIN05_POS (5U) +#define GPIO_PIDRA_PIN05 (0x0020U) +#define GPIO_PIDRA_PIN06_POS (6U) +#define GPIO_PIDRA_PIN06 (0x0040U) +#define GPIO_PIDRA_PIN07_POS (7U) +#define GPIO_PIDRA_PIN07 (0x0080U) +#define GPIO_PIDRA_PIN08_POS (8U) +#define GPIO_PIDRA_PIN08 (0x0100U) +#define GPIO_PIDRA_PIN09_POS (9U) +#define GPIO_PIDRA_PIN09 (0x0200U) +#define GPIO_PIDRA_PIN10_POS (10U) +#define GPIO_PIDRA_PIN10 (0x0400U) +#define GPIO_PIDRA_PIN11_POS (11U) +#define GPIO_PIDRA_PIN11 (0x0800U) +#define GPIO_PIDRA_PIN12_POS (12U) +#define GPIO_PIDRA_PIN12 (0x1000U) +#define GPIO_PIDRA_PIN13_POS (13U) +#define GPIO_PIDRA_PIN13 (0x2000U) +#define GPIO_PIDRA_PIN14_POS (14U) +#define GPIO_PIDRA_PIN14 (0x4000U) +#define GPIO_PIDRA_PIN15_POS (15U) +#define GPIO_PIDRA_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRA register */ +#define GPIO_PODRA_POUT00_POS (0U) +#define GPIO_PODRA_POUT00 (0x0001U) +#define GPIO_PODRA_POUT01_POS (1U) +#define GPIO_PODRA_POUT01 (0x0002U) +#define GPIO_PODRA_POUT02_POS (2U) +#define GPIO_PODRA_POUT02 (0x0004U) +#define GPIO_PODRA_POUT03_POS (3U) +#define GPIO_PODRA_POUT03 (0x0008U) +#define GPIO_PODRA_POUT04_POS (4U) +#define GPIO_PODRA_POUT04 (0x0010U) +#define GPIO_PODRA_POUT05_POS (5U) +#define GPIO_PODRA_POUT05 (0x0020U) +#define GPIO_PODRA_POUT06_POS (6U) +#define GPIO_PODRA_POUT06 (0x0040U) +#define GPIO_PODRA_POUT07_POS (7U) +#define GPIO_PODRA_POUT07 (0x0080U) +#define GPIO_PODRA_POUT08_POS (8U) +#define GPIO_PODRA_POUT08 (0x0100U) +#define GPIO_PODRA_POUT09_POS (9U) +#define GPIO_PODRA_POUT09 (0x0200U) +#define GPIO_PODRA_POUT10_POS (10U) +#define GPIO_PODRA_POUT10 (0x0400U) +#define GPIO_PODRA_POUT11_POS (11U) +#define GPIO_PODRA_POUT11 (0x0800U) +#define GPIO_PODRA_POUT12_POS (12U) +#define GPIO_PODRA_POUT12 (0x1000U) +#define GPIO_PODRA_POUT13_POS (13U) +#define GPIO_PODRA_POUT13 (0x2000U) +#define GPIO_PODRA_POUT14_POS (14U) +#define GPIO_PODRA_POUT14 (0x4000U) +#define GPIO_PODRA_POUT15_POS (15U) +#define GPIO_PODRA_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERA register */ +#define GPIO_POERA_POUTE00_POS (0U) +#define GPIO_POERA_POUTE00 (0x0001U) +#define GPIO_POERA_POUTE01_POS (1U) +#define GPIO_POERA_POUTE01 (0x0002U) +#define GPIO_POERA_POUTE02_POS (2U) +#define GPIO_POERA_POUTE02 (0x0004U) +#define GPIO_POERA_POUTE03_POS (3U) +#define GPIO_POERA_POUTE03 (0x0008U) +#define GPIO_POERA_POUTE04_POS (4U) +#define GPIO_POERA_POUTE04 (0x0010U) +#define GPIO_POERA_POUTE05_POS (5U) +#define GPIO_POERA_POUTE05 (0x0020U) +#define GPIO_POERA_POUTE06_POS (6U) +#define GPIO_POERA_POUTE06 (0x0040U) +#define GPIO_POERA_POUTE07_POS (7U) +#define GPIO_POERA_POUTE07 (0x0080U) +#define GPIO_POERA_POUTE08_POS (8U) +#define GPIO_POERA_POUTE08 (0x0100U) +#define GPIO_POERA_POUTE09_POS (9U) +#define GPIO_POERA_POUTE09 (0x0200U) +#define GPIO_POERA_POUTE10_POS (10U) +#define GPIO_POERA_POUTE10 (0x0400U) +#define GPIO_POERA_POUTE11_POS (11U) +#define GPIO_POERA_POUTE11 (0x0800U) +#define GPIO_POERA_POUTE12_POS (12U) +#define GPIO_POERA_POUTE12 (0x1000U) +#define GPIO_POERA_POUTE13_POS (13U) +#define GPIO_POERA_POUTE13 (0x2000U) +#define GPIO_POERA_POUTE14_POS (14U) +#define GPIO_POERA_POUTE14 (0x4000U) +#define GPIO_POERA_POUTE15_POS (15U) +#define GPIO_POERA_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRA register */ +#define GPIO_POSRA_POS00_POS (0U) +#define GPIO_POSRA_POS00 (0x0001U) +#define GPIO_POSRA_POS01_POS (1U) +#define GPIO_POSRA_POS01 (0x0002U) +#define GPIO_POSRA_POS02_POS (2U) +#define GPIO_POSRA_POS02 (0x0004U) +#define GPIO_POSRA_POS03_POS (3U) +#define GPIO_POSRA_POS03 (0x0008U) +#define GPIO_POSRA_POS04_POS (4U) +#define GPIO_POSRA_POS04 (0x0010U) +#define GPIO_POSRA_POS05_POS (5U) +#define GPIO_POSRA_POS05 (0x0020U) +#define GPIO_POSRA_POS06_POS (6U) +#define GPIO_POSRA_POS06 (0x0040U) +#define GPIO_POSRA_POS07_POS (7U) +#define GPIO_POSRA_POS07 (0x0080U) +#define GPIO_POSRA_POS08_POS (8U) +#define GPIO_POSRA_POS08 (0x0100U) +#define GPIO_POSRA_POS09_POS (9U) +#define GPIO_POSRA_POS09 (0x0200U) +#define GPIO_POSRA_POS10_POS (10U) +#define GPIO_POSRA_POS10 (0x0400U) +#define GPIO_POSRA_POS11_POS (11U) +#define GPIO_POSRA_POS11 (0x0800U) +#define GPIO_POSRA_POS12_POS (12U) +#define GPIO_POSRA_POS12 (0x1000U) +#define GPIO_POSRA_POS13_POS (13U) +#define GPIO_POSRA_POS13 (0x2000U) +#define GPIO_POSRA_POS14_POS (14U) +#define GPIO_POSRA_POS14 (0x4000U) +#define GPIO_POSRA_POS15_POS (15U) +#define GPIO_POSRA_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRA register */ +#define GPIO_PORRA_POR00_POS (0U) +#define GPIO_PORRA_POR00 (0x0001U) +#define GPIO_PORRA_POR01_POS (1U) +#define GPIO_PORRA_POR01 (0x0002U) +#define GPIO_PORRA_POR02_POS (2U) +#define GPIO_PORRA_POR02 (0x0004U) +#define GPIO_PORRA_POR03_POS (3U) +#define GPIO_PORRA_POR03 (0x0008U) +#define GPIO_PORRA_POR04_POS (4U) +#define GPIO_PORRA_POR04 (0x0010U) +#define GPIO_PORRA_POR05_POS (5U) +#define GPIO_PORRA_POR05 (0x0020U) +#define GPIO_PORRA_POR06_POS (6U) +#define GPIO_PORRA_POR06 (0x0040U) +#define GPIO_PORRA_POR07_POS (7U) +#define GPIO_PORRA_POR07 (0x0080U) +#define GPIO_PORRA_POR08_POS (8U) +#define GPIO_PORRA_POR08 (0x0100U) +#define GPIO_PORRA_POR09_POS (9U) +#define GPIO_PORRA_POR09 (0x0200U) +#define GPIO_PORRA_POR10_POS (10U) +#define GPIO_PORRA_POR10 (0x0400U) +#define GPIO_PORRA_POR11_POS (11U) +#define GPIO_PORRA_POR11 (0x0800U) +#define GPIO_PORRA_POR12_POS (12U) +#define GPIO_PORRA_POR12 (0x1000U) +#define GPIO_PORRA_POR13_POS (13U) +#define GPIO_PORRA_POR13 (0x2000U) +#define GPIO_PORRA_POR14_POS (14U) +#define GPIO_PORRA_POR14 (0x4000U) +#define GPIO_PORRA_POR15_POS (15U) +#define GPIO_PORRA_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRA register */ +#define GPIO_POTRA_POT00_POS (0U) +#define GPIO_POTRA_POT00 (0x0001U) +#define GPIO_POTRA_POT01_POS (1U) +#define GPIO_POTRA_POT01 (0x0002U) +#define GPIO_POTRA_POT02_POS (2U) +#define GPIO_POTRA_POT02 (0x0004U) +#define GPIO_POTRA_POT03_POS (3U) +#define GPIO_POTRA_POT03 (0x0008U) +#define GPIO_POTRA_POT04_POS (4U) +#define GPIO_POTRA_POT04 (0x0010U) +#define GPIO_POTRA_POT05_POS (5U) +#define GPIO_POTRA_POT05 (0x0020U) +#define GPIO_POTRA_POT06_POS (6U) +#define GPIO_POTRA_POT06 (0x0040U) +#define GPIO_POTRA_POT07_POS (7U) +#define GPIO_POTRA_POT07 (0x0080U) +#define GPIO_POTRA_POT08_POS (8U) +#define GPIO_POTRA_POT08 (0x0100U) +#define GPIO_POTRA_POT09_POS (9U) +#define GPIO_POTRA_POT09 (0x0200U) +#define GPIO_POTRA_POT10_POS (10U) +#define GPIO_POTRA_POT10 (0x0400U) +#define GPIO_POTRA_POT11_POS (11U) +#define GPIO_POTRA_POT11 (0x0800U) +#define GPIO_POTRA_POT12_POS (12U) +#define GPIO_POTRA_POT12 (0x1000U) +#define GPIO_POTRA_POT13_POS (13U) +#define GPIO_POTRA_POT13 (0x2000U) +#define GPIO_POTRA_POT14_POS (14U) +#define GPIO_POTRA_POT14 (0x4000U) +#define GPIO_POTRA_POT15_POS (15U) +#define GPIO_POTRA_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRB register */ +#define GPIO_PIDRB_PIN00_POS (0U) +#define GPIO_PIDRB_PIN00 (0x0001U) +#define GPIO_PIDRB_PIN01_POS (1U) +#define GPIO_PIDRB_PIN01 (0x0002U) +#define GPIO_PIDRB_PIN02_POS (2U) +#define GPIO_PIDRB_PIN02 (0x0004U) +#define GPIO_PIDRB_PIN03_POS (3U) +#define GPIO_PIDRB_PIN03 (0x0008U) +#define GPIO_PIDRB_PIN04_POS (4U) +#define GPIO_PIDRB_PIN04 (0x0010U) +#define GPIO_PIDRB_PIN05_POS (5U) +#define GPIO_PIDRB_PIN05 (0x0020U) +#define GPIO_PIDRB_PIN06_POS (6U) +#define GPIO_PIDRB_PIN06 (0x0040U) +#define GPIO_PIDRB_PIN07_POS (7U) +#define GPIO_PIDRB_PIN07 (0x0080U) +#define GPIO_PIDRB_PIN08_POS (8U) +#define GPIO_PIDRB_PIN08 (0x0100U) +#define GPIO_PIDRB_PIN09_POS (9U) +#define GPIO_PIDRB_PIN09 (0x0200U) +#define GPIO_PIDRB_PIN10_POS (10U) +#define GPIO_PIDRB_PIN10 (0x0400U) +#define GPIO_PIDRB_PIN11_POS (11U) +#define GPIO_PIDRB_PIN11 (0x0800U) +#define GPIO_PIDRB_PIN12_POS (12U) +#define GPIO_PIDRB_PIN12 (0x1000U) +#define GPIO_PIDRB_PIN13_POS (13U) +#define GPIO_PIDRB_PIN13 (0x2000U) +#define GPIO_PIDRB_PIN14_POS (14U) +#define GPIO_PIDRB_PIN14 (0x4000U) +#define GPIO_PIDRB_PIN15_POS (15U) +#define GPIO_PIDRB_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRB register */ +#define GPIO_PODRB_POUT00_POS (0U) +#define GPIO_PODRB_POUT00 (0x0001U) +#define GPIO_PODRB_POUT01_POS (1U) +#define GPIO_PODRB_POUT01 (0x0002U) +#define GPIO_PODRB_POUT02_POS (2U) +#define GPIO_PODRB_POUT02 (0x0004U) +#define GPIO_PODRB_POUT03_POS (3U) +#define GPIO_PODRB_POUT03 (0x0008U) +#define GPIO_PODRB_POUT04_POS (4U) +#define GPIO_PODRB_POUT04 (0x0010U) +#define GPIO_PODRB_POUT05_POS (5U) +#define GPIO_PODRB_POUT05 (0x0020U) +#define GPIO_PODRB_POUT06_POS (6U) +#define GPIO_PODRB_POUT06 (0x0040U) +#define GPIO_PODRB_POUT07_POS (7U) +#define GPIO_PODRB_POUT07 (0x0080U) +#define GPIO_PODRB_POUT08_POS (8U) +#define GPIO_PODRB_POUT08 (0x0100U) +#define GPIO_PODRB_POUT09_POS (9U) +#define GPIO_PODRB_POUT09 (0x0200U) +#define GPIO_PODRB_POUT10_POS (10U) +#define GPIO_PODRB_POUT10 (0x0400U) +#define GPIO_PODRB_POUT11_POS (11U) +#define GPIO_PODRB_POUT11 (0x0800U) +#define GPIO_PODRB_POUT12_POS (12U) +#define GPIO_PODRB_POUT12 (0x1000U) +#define GPIO_PODRB_POUT13_POS (13U) +#define GPIO_PODRB_POUT13 (0x2000U) +#define GPIO_PODRB_POUT14_POS (14U) +#define GPIO_PODRB_POUT14 (0x4000U) +#define GPIO_PODRB_POUT15_POS (15U) +#define GPIO_PODRB_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERB register */ +#define GPIO_POERB_POUTE00_POS (0U) +#define GPIO_POERB_POUTE00 (0x0001U) +#define GPIO_POERB_POUTE01_POS (1U) +#define GPIO_POERB_POUTE01 (0x0002U) +#define GPIO_POERB_POUTE02_POS (2U) +#define GPIO_POERB_POUTE02 (0x0004U) +#define GPIO_POERB_POUTE03_POS (3U) +#define GPIO_POERB_POUTE03 (0x0008U) +#define GPIO_POERB_POUTE04_POS (4U) +#define GPIO_POERB_POUTE04 (0x0010U) +#define GPIO_POERB_POUTE05_POS (5U) +#define GPIO_POERB_POUTE05 (0x0020U) +#define GPIO_POERB_POUTE06_POS (6U) +#define GPIO_POERB_POUTE06 (0x0040U) +#define GPIO_POERB_POUTE07_POS (7U) +#define GPIO_POERB_POUTE07 (0x0080U) +#define GPIO_POERB_POUTE08_POS (8U) +#define GPIO_POERB_POUTE08 (0x0100U) +#define GPIO_POERB_POUTE09_POS (9U) +#define GPIO_POERB_POUTE09 (0x0200U) +#define GPIO_POERB_POUTE10_POS (10U) +#define GPIO_POERB_POUTE10 (0x0400U) +#define GPIO_POERB_POUTE11_POS (11U) +#define GPIO_POERB_POUTE11 (0x0800U) +#define GPIO_POERB_POUTE12_POS (12U) +#define GPIO_POERB_POUTE12 (0x1000U) +#define GPIO_POERB_POUTE13_POS (13U) +#define GPIO_POERB_POUTE13 (0x2000U) +#define GPIO_POERB_POUTE14_POS (14U) +#define GPIO_POERB_POUTE14 (0x4000U) +#define GPIO_POERB_POUTE15_POS (15U) +#define GPIO_POERB_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRB register */ +#define GPIO_POSRB_POS00_POS (0U) +#define GPIO_POSRB_POS00 (0x0001U) +#define GPIO_POSRB_POS01_POS (1U) +#define GPIO_POSRB_POS01 (0x0002U) +#define GPIO_POSRB_POS02_POS (2U) +#define GPIO_POSRB_POS02 (0x0004U) +#define GPIO_POSRB_POS03_POS (3U) +#define GPIO_POSRB_POS03 (0x0008U) +#define GPIO_POSRB_POS04_POS (4U) +#define GPIO_POSRB_POS04 (0x0010U) +#define GPIO_POSRB_POS05_POS (5U) +#define GPIO_POSRB_POS05 (0x0020U) +#define GPIO_POSRB_POS06_POS (6U) +#define GPIO_POSRB_POS06 (0x0040U) +#define GPIO_POSRB_POS07_POS (7U) +#define GPIO_POSRB_POS07 (0x0080U) +#define GPIO_POSRB_POS08_POS (8U) +#define GPIO_POSRB_POS08 (0x0100U) +#define GPIO_POSRB_POS09_POS (9U) +#define GPIO_POSRB_POS09 (0x0200U) +#define GPIO_POSRB_POS10_POS (10U) +#define GPIO_POSRB_POS10 (0x0400U) +#define GPIO_POSRB_POS11_POS (11U) +#define GPIO_POSRB_POS11 (0x0800U) +#define GPIO_POSRB_POS12_POS (12U) +#define GPIO_POSRB_POS12 (0x1000U) +#define GPIO_POSRB_POS13_POS (13U) +#define GPIO_POSRB_POS13 (0x2000U) +#define GPIO_POSRB_POS14_POS (14U) +#define GPIO_POSRB_POS14 (0x4000U) +#define GPIO_POSRB_POS15_POS (15U) +#define GPIO_POSRB_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRB register */ +#define GPIO_PORRB_POR00_POS (0U) +#define GPIO_PORRB_POR00 (0x0001U) +#define GPIO_PORRB_POR01_POS (1U) +#define GPIO_PORRB_POR01 (0x0002U) +#define GPIO_PORRB_POR02_POS (2U) +#define GPIO_PORRB_POR02 (0x0004U) +#define GPIO_PORRB_POR03_POS (3U) +#define GPIO_PORRB_POR03 (0x0008U) +#define GPIO_PORRB_POR04_POS (4U) +#define GPIO_PORRB_POR04 (0x0010U) +#define GPIO_PORRB_POR05_POS (5U) +#define GPIO_PORRB_POR05 (0x0020U) +#define GPIO_PORRB_POR06_POS (6U) +#define GPIO_PORRB_POR06 (0x0040U) +#define GPIO_PORRB_POR07_POS (7U) +#define GPIO_PORRB_POR07 (0x0080U) +#define GPIO_PORRB_POR08_POS (8U) +#define GPIO_PORRB_POR08 (0x0100U) +#define GPIO_PORRB_POR09_POS (9U) +#define GPIO_PORRB_POR09 (0x0200U) +#define GPIO_PORRB_POR10_POS (10U) +#define GPIO_PORRB_POR10 (0x0400U) +#define GPIO_PORRB_POR11_POS (11U) +#define GPIO_PORRB_POR11 (0x0800U) +#define GPIO_PORRB_POR12_POS (12U) +#define GPIO_PORRB_POR12 (0x1000U) +#define GPIO_PORRB_POR13_POS (13U) +#define GPIO_PORRB_POR13 (0x2000U) +#define GPIO_PORRB_POR14_POS (14U) +#define GPIO_PORRB_POR14 (0x4000U) +#define GPIO_PORRB_POR15_POS (15U) +#define GPIO_PORRB_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRB register */ +#define GPIO_POTRB_POT00_POS (0U) +#define GPIO_POTRB_POT00 (0x0001U) +#define GPIO_POTRB_POT01_POS (1U) +#define GPIO_POTRB_POT01 (0x0002U) +#define GPIO_POTRB_POT02_POS (2U) +#define GPIO_POTRB_POT02 (0x0004U) +#define GPIO_POTRB_POT03_POS (3U) +#define GPIO_POTRB_POT03 (0x0008U) +#define GPIO_POTRB_POT04_POS (4U) +#define GPIO_POTRB_POT04 (0x0010U) +#define GPIO_POTRB_POT05_POS (5U) +#define GPIO_POTRB_POT05 (0x0020U) +#define GPIO_POTRB_POT06_POS (6U) +#define GPIO_POTRB_POT06 (0x0040U) +#define GPIO_POTRB_POT07_POS (7U) +#define GPIO_POTRB_POT07 (0x0080U) +#define GPIO_POTRB_POT08_POS (8U) +#define GPIO_POTRB_POT08 (0x0100U) +#define GPIO_POTRB_POT09_POS (9U) +#define GPIO_POTRB_POT09 (0x0200U) +#define GPIO_POTRB_POT10_POS (10U) +#define GPIO_POTRB_POT10 (0x0400U) +#define GPIO_POTRB_POT11_POS (11U) +#define GPIO_POTRB_POT11 (0x0800U) +#define GPIO_POTRB_POT12_POS (12U) +#define GPIO_POTRB_POT12 (0x1000U) +#define GPIO_POTRB_POT13_POS (13U) +#define GPIO_POTRB_POT13 (0x2000U) +#define GPIO_POTRB_POT14_POS (14U) +#define GPIO_POTRB_POT14 (0x4000U) +#define GPIO_POTRB_POT15_POS (15U) +#define GPIO_POTRB_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRC register */ +#define GPIO_PIDRC_PIN00_POS (0U) +#define GPIO_PIDRC_PIN00 (0x0001U) +#define GPIO_PIDRC_PIN01_POS (1U) +#define GPIO_PIDRC_PIN01 (0x0002U) +#define GPIO_PIDRC_PIN02_POS (2U) +#define GPIO_PIDRC_PIN02 (0x0004U) +#define GPIO_PIDRC_PIN03_POS (3U) +#define GPIO_PIDRC_PIN03 (0x0008U) +#define GPIO_PIDRC_PIN04_POS (4U) +#define GPIO_PIDRC_PIN04 (0x0010U) +#define GPIO_PIDRC_PIN05_POS (5U) +#define GPIO_PIDRC_PIN05 (0x0020U) +#define GPIO_PIDRC_PIN06_POS (6U) +#define GPIO_PIDRC_PIN06 (0x0040U) +#define GPIO_PIDRC_PIN07_POS (7U) +#define GPIO_PIDRC_PIN07 (0x0080U) +#define GPIO_PIDRC_PIN08_POS (8U) +#define GPIO_PIDRC_PIN08 (0x0100U) +#define GPIO_PIDRC_PIN09_POS (9U) +#define GPIO_PIDRC_PIN09 (0x0200U) +#define GPIO_PIDRC_PIN10_POS (10U) +#define GPIO_PIDRC_PIN10 (0x0400U) +#define GPIO_PIDRC_PIN11_POS (11U) +#define GPIO_PIDRC_PIN11 (0x0800U) +#define GPIO_PIDRC_PIN12_POS (12U) +#define GPIO_PIDRC_PIN12 (0x1000U) +#define GPIO_PIDRC_PIN13_POS (13U) +#define GPIO_PIDRC_PIN13 (0x2000U) +#define GPIO_PIDRC_PIN14_POS (14U) +#define GPIO_PIDRC_PIN14 (0x4000U) +#define GPIO_PIDRC_PIN15_POS (15U) +#define GPIO_PIDRC_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRC register */ +#define GPIO_PODRC_POUT00_POS (0U) +#define GPIO_PODRC_POUT00 (0x0001U) +#define GPIO_PODRC_POUT01_POS (1U) +#define GPIO_PODRC_POUT01 (0x0002U) +#define GPIO_PODRC_POUT02_POS (2U) +#define GPIO_PODRC_POUT02 (0x0004U) +#define GPIO_PODRC_POUT03_POS (3U) +#define GPIO_PODRC_POUT03 (0x0008U) +#define GPIO_PODRC_POUT04_POS (4U) +#define GPIO_PODRC_POUT04 (0x0010U) +#define GPIO_PODRC_POUT05_POS (5U) +#define GPIO_PODRC_POUT05 (0x0020U) +#define GPIO_PODRC_POUT06_POS (6U) +#define GPIO_PODRC_POUT06 (0x0040U) +#define GPIO_PODRC_POUT07_POS (7U) +#define GPIO_PODRC_POUT07 (0x0080U) +#define GPIO_PODRC_POUT08_POS (8U) +#define GPIO_PODRC_POUT08 (0x0100U) +#define GPIO_PODRC_POUT09_POS (9U) +#define GPIO_PODRC_POUT09 (0x0200U) +#define GPIO_PODRC_POUT10_POS (10U) +#define GPIO_PODRC_POUT10 (0x0400U) +#define GPIO_PODRC_POUT11_POS (11U) +#define GPIO_PODRC_POUT11 (0x0800U) +#define GPIO_PODRC_POUT12_POS (12U) +#define GPIO_PODRC_POUT12 (0x1000U) +#define GPIO_PODRC_POUT13_POS (13U) +#define GPIO_PODRC_POUT13 (0x2000U) +#define GPIO_PODRC_POUT14_POS (14U) +#define GPIO_PODRC_POUT14 (0x4000U) +#define GPIO_PODRC_POUT15_POS (15U) +#define GPIO_PODRC_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERC register */ +#define GPIO_POERC_POUTE00_POS (0U) +#define GPIO_POERC_POUTE00 (0x0001U) +#define GPIO_POERC_POUTE01_POS (1U) +#define GPIO_POERC_POUTE01 (0x0002U) +#define GPIO_POERC_POUTE02_POS (2U) +#define GPIO_POERC_POUTE02 (0x0004U) +#define GPIO_POERC_POUTE03_POS (3U) +#define GPIO_POERC_POUTE03 (0x0008U) +#define GPIO_POERC_POUTE04_POS (4U) +#define GPIO_POERC_POUTE04 (0x0010U) +#define GPIO_POERC_POUTE05_POS (5U) +#define GPIO_POERC_POUTE05 (0x0020U) +#define GPIO_POERC_POUTE06_POS (6U) +#define GPIO_POERC_POUTE06 (0x0040U) +#define GPIO_POERC_POUTE07_POS (7U) +#define GPIO_POERC_POUTE07 (0x0080U) +#define GPIO_POERC_POUTE08_POS (8U) +#define GPIO_POERC_POUTE08 (0x0100U) +#define GPIO_POERC_POUTE09_POS (9U) +#define GPIO_POERC_POUTE09 (0x0200U) +#define GPIO_POERC_POUTE10_POS (10U) +#define GPIO_POERC_POUTE10 (0x0400U) +#define GPIO_POERC_POUTE11_POS (11U) +#define GPIO_POERC_POUTE11 (0x0800U) +#define GPIO_POERC_POUTE12_POS (12U) +#define GPIO_POERC_POUTE12 (0x1000U) +#define GPIO_POERC_POUTE13_POS (13U) +#define GPIO_POERC_POUTE13 (0x2000U) +#define GPIO_POERC_POUTE14_POS (14U) +#define GPIO_POERC_POUTE14 (0x4000U) +#define GPIO_POERC_POUTE15_POS (15U) +#define GPIO_POERC_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRC register */ +#define GPIO_POSRC_POS00_POS (0U) +#define GPIO_POSRC_POS00 (0x0001U) +#define GPIO_POSRC_POS01_POS (1U) +#define GPIO_POSRC_POS01 (0x0002U) +#define GPIO_POSRC_POS02_POS (2U) +#define GPIO_POSRC_POS02 (0x0004U) +#define GPIO_POSRC_POS03_POS (3U) +#define GPIO_POSRC_POS03 (0x0008U) +#define GPIO_POSRC_POS04_POS (4U) +#define GPIO_POSRC_POS04 (0x0010U) +#define GPIO_POSRC_POS05_POS (5U) +#define GPIO_POSRC_POS05 (0x0020U) +#define GPIO_POSRC_POS06_POS (6U) +#define GPIO_POSRC_POS06 (0x0040U) +#define GPIO_POSRC_POS07_POS (7U) +#define GPIO_POSRC_POS07 (0x0080U) +#define GPIO_POSRC_POS08_POS (8U) +#define GPIO_POSRC_POS08 (0x0100U) +#define GPIO_POSRC_POS09_POS (9U) +#define GPIO_POSRC_POS09 (0x0200U) +#define GPIO_POSRC_POS10_POS (10U) +#define GPIO_POSRC_POS10 (0x0400U) +#define GPIO_POSRC_POS11_POS (11U) +#define GPIO_POSRC_POS11 (0x0800U) +#define GPIO_POSRC_POS12_POS (12U) +#define GPIO_POSRC_POS12 (0x1000U) +#define GPIO_POSRC_POS13_POS (13U) +#define GPIO_POSRC_POS13 (0x2000U) +#define GPIO_POSRC_POS14_POS (14U) +#define GPIO_POSRC_POS14 (0x4000U) +#define GPIO_POSRC_POS15_POS (15U) +#define GPIO_POSRC_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRC register */ +#define GPIO_PORRC_POR00_POS (0U) +#define GPIO_PORRC_POR00 (0x0001U) +#define GPIO_PORRC_POR01_POS (1U) +#define GPIO_PORRC_POR01 (0x0002U) +#define GPIO_PORRC_POR02_POS (2U) +#define GPIO_PORRC_POR02 (0x0004U) +#define GPIO_PORRC_POR03_POS (3U) +#define GPIO_PORRC_POR03 (0x0008U) +#define GPIO_PORRC_POR04_POS (4U) +#define GPIO_PORRC_POR04 (0x0010U) +#define GPIO_PORRC_POR05_POS (5U) +#define GPIO_PORRC_POR05 (0x0020U) +#define GPIO_PORRC_POR06_POS (6U) +#define GPIO_PORRC_POR06 (0x0040U) +#define GPIO_PORRC_POR07_POS (7U) +#define GPIO_PORRC_POR07 (0x0080U) +#define GPIO_PORRC_POR08_POS (8U) +#define GPIO_PORRC_POR08 (0x0100U) +#define GPIO_PORRC_POR09_POS (9U) +#define GPIO_PORRC_POR09 (0x0200U) +#define GPIO_PORRC_POR10_POS (10U) +#define GPIO_PORRC_POR10 (0x0400U) +#define GPIO_PORRC_POR11_POS (11U) +#define GPIO_PORRC_POR11 (0x0800U) +#define GPIO_PORRC_POR12_POS (12U) +#define GPIO_PORRC_POR12 (0x1000U) +#define GPIO_PORRC_POR13_POS (13U) +#define GPIO_PORRC_POR13 (0x2000U) +#define GPIO_PORRC_POR14_POS (14U) +#define GPIO_PORRC_POR14 (0x4000U) +#define GPIO_PORRC_POR15_POS (15U) +#define GPIO_PORRC_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRC register */ +#define GPIO_POTRC_POT00_POS (0U) +#define GPIO_POTRC_POT00 (0x0001U) +#define GPIO_POTRC_POT01_POS (1U) +#define GPIO_POTRC_POT01 (0x0002U) +#define GPIO_POTRC_POT02_POS (2U) +#define GPIO_POTRC_POT02 (0x0004U) +#define GPIO_POTRC_POT03_POS (3U) +#define GPIO_POTRC_POT03 (0x0008U) +#define GPIO_POTRC_POT04_POS (4U) +#define GPIO_POTRC_POT04 (0x0010U) +#define GPIO_POTRC_POT05_POS (5U) +#define GPIO_POTRC_POT05 (0x0020U) +#define GPIO_POTRC_POT06_POS (6U) +#define GPIO_POTRC_POT06 (0x0040U) +#define GPIO_POTRC_POT07_POS (7U) +#define GPIO_POTRC_POT07 (0x0080U) +#define GPIO_POTRC_POT08_POS (8U) +#define GPIO_POTRC_POT08 (0x0100U) +#define GPIO_POTRC_POT09_POS (9U) +#define GPIO_POTRC_POT09 (0x0200U) +#define GPIO_POTRC_POT10_POS (10U) +#define GPIO_POTRC_POT10 (0x0400U) +#define GPIO_POTRC_POT11_POS (11U) +#define GPIO_POTRC_POT11 (0x0800U) +#define GPIO_POTRC_POT12_POS (12U) +#define GPIO_POTRC_POT12 (0x1000U) +#define GPIO_POTRC_POT13_POS (13U) +#define GPIO_POTRC_POT13 (0x2000U) +#define GPIO_POTRC_POT14_POS (14U) +#define GPIO_POTRC_POT14 (0x4000U) +#define GPIO_POTRC_POT15_POS (15U) +#define GPIO_POTRC_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRD register */ +#define GPIO_PIDRD_PIN00_POS (0U) +#define GPIO_PIDRD_PIN00 (0x0001U) +#define GPIO_PIDRD_PIN01_POS (1U) +#define GPIO_PIDRD_PIN01 (0x0002U) +#define GPIO_PIDRD_PIN02_POS (2U) +#define GPIO_PIDRD_PIN02 (0x0004U) +#define GPIO_PIDRD_PIN03_POS (3U) +#define GPIO_PIDRD_PIN03 (0x0008U) +#define GPIO_PIDRD_PIN04_POS (4U) +#define GPIO_PIDRD_PIN04 (0x0010U) +#define GPIO_PIDRD_PIN05_POS (5U) +#define GPIO_PIDRD_PIN05 (0x0020U) +#define GPIO_PIDRD_PIN06_POS (6U) +#define GPIO_PIDRD_PIN06 (0x0040U) +#define GPIO_PIDRD_PIN07_POS (7U) +#define GPIO_PIDRD_PIN07 (0x0080U) +#define GPIO_PIDRD_PIN08_POS (8U) +#define GPIO_PIDRD_PIN08 (0x0100U) +#define GPIO_PIDRD_PIN09_POS (9U) +#define GPIO_PIDRD_PIN09 (0x0200U) +#define GPIO_PIDRD_PIN10_POS (10U) +#define GPIO_PIDRD_PIN10 (0x0400U) +#define GPIO_PIDRD_PIN11_POS (11U) +#define GPIO_PIDRD_PIN11 (0x0800U) +#define GPIO_PIDRD_PIN12_POS (12U) +#define GPIO_PIDRD_PIN12 (0x1000U) +#define GPIO_PIDRD_PIN13_POS (13U) +#define GPIO_PIDRD_PIN13 (0x2000U) +#define GPIO_PIDRD_PIN14_POS (14U) +#define GPIO_PIDRD_PIN14 (0x4000U) +#define GPIO_PIDRD_PIN15_POS (15U) +#define GPIO_PIDRD_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRD register */ +#define GPIO_PODRD_POUT00_POS (0U) +#define GPIO_PODRD_POUT00 (0x0001U) +#define GPIO_PODRD_POUT01_POS (1U) +#define GPIO_PODRD_POUT01 (0x0002U) +#define GPIO_PODRD_POUT02_POS (2U) +#define GPIO_PODRD_POUT02 (0x0004U) +#define GPIO_PODRD_POUT03_POS (3U) +#define GPIO_PODRD_POUT03 (0x0008U) +#define GPIO_PODRD_POUT04_POS (4U) +#define GPIO_PODRD_POUT04 (0x0010U) +#define GPIO_PODRD_POUT05_POS (5U) +#define GPIO_PODRD_POUT05 (0x0020U) +#define GPIO_PODRD_POUT06_POS (6U) +#define GPIO_PODRD_POUT06 (0x0040U) +#define GPIO_PODRD_POUT07_POS (7U) +#define GPIO_PODRD_POUT07 (0x0080U) +#define GPIO_PODRD_POUT08_POS (8U) +#define GPIO_PODRD_POUT08 (0x0100U) +#define GPIO_PODRD_POUT09_POS (9U) +#define GPIO_PODRD_POUT09 (0x0200U) +#define GPIO_PODRD_POUT10_POS (10U) +#define GPIO_PODRD_POUT10 (0x0400U) +#define GPIO_PODRD_POUT11_POS (11U) +#define GPIO_PODRD_POUT11 (0x0800U) +#define GPIO_PODRD_POUT12_POS (12U) +#define GPIO_PODRD_POUT12 (0x1000U) +#define GPIO_PODRD_POUT13_POS (13U) +#define GPIO_PODRD_POUT13 (0x2000U) +#define GPIO_PODRD_POUT14_POS (14U) +#define GPIO_PODRD_POUT14 (0x4000U) +#define GPIO_PODRD_POUT15_POS (15U) +#define GPIO_PODRD_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERD register */ +#define GPIO_POERD_POUTE00_POS (0U) +#define GPIO_POERD_POUTE00 (0x0001U) +#define GPIO_POERD_POUTE01_POS (1U) +#define GPIO_POERD_POUTE01 (0x0002U) +#define GPIO_POERD_POUTE02_POS (2U) +#define GPIO_POERD_POUTE02 (0x0004U) +#define GPIO_POERD_POUTE03_POS (3U) +#define GPIO_POERD_POUTE03 (0x0008U) +#define GPIO_POERD_POUTE04_POS (4U) +#define GPIO_POERD_POUTE04 (0x0010U) +#define GPIO_POERD_POUTE05_POS (5U) +#define GPIO_POERD_POUTE05 (0x0020U) +#define GPIO_POERD_POUTE06_POS (6U) +#define GPIO_POERD_POUTE06 (0x0040U) +#define GPIO_POERD_POUTE07_POS (7U) +#define GPIO_POERD_POUTE07 (0x0080U) +#define GPIO_POERD_POUTE08_POS (8U) +#define GPIO_POERD_POUTE08 (0x0100U) +#define GPIO_POERD_POUTE09_POS (9U) +#define GPIO_POERD_POUTE09 (0x0200U) +#define GPIO_POERD_POUTE10_POS (10U) +#define GPIO_POERD_POUTE10 (0x0400U) +#define GPIO_POERD_POUTE11_POS (11U) +#define GPIO_POERD_POUTE11 (0x0800U) +#define GPIO_POERD_POUTE12_POS (12U) +#define GPIO_POERD_POUTE12 (0x1000U) +#define GPIO_POERD_POUTE13_POS (13U) +#define GPIO_POERD_POUTE13 (0x2000U) +#define GPIO_POERD_POUTE14_POS (14U) +#define GPIO_POERD_POUTE14 (0x4000U) +#define GPIO_POERD_POUTE15_POS (15U) +#define GPIO_POERD_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRD register */ +#define GPIO_POSRD_POS00_POS (0U) +#define GPIO_POSRD_POS00 (0x0001U) +#define GPIO_POSRD_POS01_POS (1U) +#define GPIO_POSRD_POS01 (0x0002U) +#define GPIO_POSRD_POS02_POS (2U) +#define GPIO_POSRD_POS02 (0x0004U) +#define GPIO_POSRD_POS03_POS (3U) +#define GPIO_POSRD_POS03 (0x0008U) +#define GPIO_POSRD_POS04_POS (4U) +#define GPIO_POSRD_POS04 (0x0010U) +#define GPIO_POSRD_POS05_POS (5U) +#define GPIO_POSRD_POS05 (0x0020U) +#define GPIO_POSRD_POS06_POS (6U) +#define GPIO_POSRD_POS06 (0x0040U) +#define GPIO_POSRD_POS07_POS (7U) +#define GPIO_POSRD_POS07 (0x0080U) +#define GPIO_POSRD_POS08_POS (8U) +#define GPIO_POSRD_POS08 (0x0100U) +#define GPIO_POSRD_POS09_POS (9U) +#define GPIO_POSRD_POS09 (0x0200U) +#define GPIO_POSRD_POS10_POS (10U) +#define GPIO_POSRD_POS10 (0x0400U) +#define GPIO_POSRD_POS11_POS (11U) +#define GPIO_POSRD_POS11 (0x0800U) +#define GPIO_POSRD_POS12_POS (12U) +#define GPIO_POSRD_POS12 (0x1000U) +#define GPIO_POSRD_POS13_POS (13U) +#define GPIO_POSRD_POS13 (0x2000U) +#define GPIO_POSRD_POS14_POS (14U) +#define GPIO_POSRD_POS14 (0x4000U) +#define GPIO_POSRD_POS15_POS (15U) +#define GPIO_POSRD_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRD register */ +#define GPIO_PORRD_POR00_POS (0U) +#define GPIO_PORRD_POR00 (0x0001U) +#define GPIO_PORRD_POR01_POS (1U) +#define GPIO_PORRD_POR01 (0x0002U) +#define GPIO_PORRD_POR02_POS (2U) +#define GPIO_PORRD_POR02 (0x0004U) +#define GPIO_PORRD_POR03_POS (3U) +#define GPIO_PORRD_POR03 (0x0008U) +#define GPIO_PORRD_POR04_POS (4U) +#define GPIO_PORRD_POR04 (0x0010U) +#define GPIO_PORRD_POR05_POS (5U) +#define GPIO_PORRD_POR05 (0x0020U) +#define GPIO_PORRD_POR06_POS (6U) +#define GPIO_PORRD_POR06 (0x0040U) +#define GPIO_PORRD_POR07_POS (7U) +#define GPIO_PORRD_POR07 (0x0080U) +#define GPIO_PORRD_POR08_POS (8U) +#define GPIO_PORRD_POR08 (0x0100U) +#define GPIO_PORRD_POR09_POS (9U) +#define GPIO_PORRD_POR09 (0x0200U) +#define GPIO_PORRD_POR10_POS (10U) +#define GPIO_PORRD_POR10 (0x0400U) +#define GPIO_PORRD_POR11_POS (11U) +#define GPIO_PORRD_POR11 (0x0800U) +#define GPIO_PORRD_POR12_POS (12U) +#define GPIO_PORRD_POR12 (0x1000U) +#define GPIO_PORRD_POR13_POS (13U) +#define GPIO_PORRD_POR13 (0x2000U) +#define GPIO_PORRD_POR14_POS (14U) +#define GPIO_PORRD_POR14 (0x4000U) +#define GPIO_PORRD_POR15_POS (15U) +#define GPIO_PORRD_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRD register */ +#define GPIO_POTRD_POT00_POS (0U) +#define GPIO_POTRD_POT00 (0x0001U) +#define GPIO_POTRD_POT01_POS (1U) +#define GPIO_POTRD_POT01 (0x0002U) +#define GPIO_POTRD_POT02_POS (2U) +#define GPIO_POTRD_POT02 (0x0004U) +#define GPIO_POTRD_POT03_POS (3U) +#define GPIO_POTRD_POT03 (0x0008U) +#define GPIO_POTRD_POT04_POS (4U) +#define GPIO_POTRD_POT04 (0x0010U) +#define GPIO_POTRD_POT05_POS (5U) +#define GPIO_POTRD_POT05 (0x0020U) +#define GPIO_POTRD_POT06_POS (6U) +#define GPIO_POTRD_POT06 (0x0040U) +#define GPIO_POTRD_POT07_POS (7U) +#define GPIO_POTRD_POT07 (0x0080U) +#define GPIO_POTRD_POT08_POS (8U) +#define GPIO_POTRD_POT08 (0x0100U) +#define GPIO_POTRD_POT09_POS (9U) +#define GPIO_POTRD_POT09 (0x0200U) +#define GPIO_POTRD_POT10_POS (10U) +#define GPIO_POTRD_POT10 (0x0400U) +#define GPIO_POTRD_POT11_POS (11U) +#define GPIO_POTRD_POT11 (0x0800U) +#define GPIO_POTRD_POT12_POS (12U) +#define GPIO_POTRD_POT12 (0x1000U) +#define GPIO_POTRD_POT13_POS (13U) +#define GPIO_POTRD_POT13 (0x2000U) +#define GPIO_POTRD_POT14_POS (14U) +#define GPIO_POTRD_POT14 (0x4000U) +#define GPIO_POTRD_POT15_POS (15U) +#define GPIO_POTRD_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRE register */ +#define GPIO_PIDRE_PIN00_POS (0U) +#define GPIO_PIDRE_PIN00 (0x0001U) +#define GPIO_PIDRE_PIN01_POS (1U) +#define GPIO_PIDRE_PIN01 (0x0002U) +#define GPIO_PIDRE_PIN02_POS (2U) +#define GPIO_PIDRE_PIN02 (0x0004U) +#define GPIO_PIDRE_PIN03_POS (3U) +#define GPIO_PIDRE_PIN03 (0x0008U) +#define GPIO_PIDRE_PIN04_POS (4U) +#define GPIO_PIDRE_PIN04 (0x0010U) +#define GPIO_PIDRE_PIN05_POS (5U) +#define GPIO_PIDRE_PIN05 (0x0020U) +#define GPIO_PIDRE_PIN06_POS (6U) +#define GPIO_PIDRE_PIN06 (0x0040U) +#define GPIO_PIDRE_PIN07_POS (7U) +#define GPIO_PIDRE_PIN07 (0x0080U) +#define GPIO_PIDRE_PIN08_POS (8U) +#define GPIO_PIDRE_PIN08 (0x0100U) +#define GPIO_PIDRE_PIN09_POS (9U) +#define GPIO_PIDRE_PIN09 (0x0200U) +#define GPIO_PIDRE_PIN10_POS (10U) +#define GPIO_PIDRE_PIN10 (0x0400U) +#define GPIO_PIDRE_PIN11_POS (11U) +#define GPIO_PIDRE_PIN11 (0x0800U) +#define GPIO_PIDRE_PIN12_POS (12U) +#define GPIO_PIDRE_PIN12 (0x1000U) +#define GPIO_PIDRE_PIN13_POS (13U) +#define GPIO_PIDRE_PIN13 (0x2000U) +#define GPIO_PIDRE_PIN14_POS (14U) +#define GPIO_PIDRE_PIN14 (0x4000U) +#define GPIO_PIDRE_PIN15_POS (15U) +#define GPIO_PIDRE_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRE register */ +#define GPIO_PODRE_POUT00_POS (0U) +#define GPIO_PODRE_POUT00 (0x0001U) +#define GPIO_PODRE_POUT01_POS (1U) +#define GPIO_PODRE_POUT01 (0x0002U) +#define GPIO_PODRE_POUT02_POS (2U) +#define GPIO_PODRE_POUT02 (0x0004U) +#define GPIO_PODRE_POUT03_POS (3U) +#define GPIO_PODRE_POUT03 (0x0008U) +#define GPIO_PODRE_POUT04_POS (4U) +#define GPIO_PODRE_POUT04 (0x0010U) +#define GPIO_PODRE_POUT05_POS (5U) +#define GPIO_PODRE_POUT05 (0x0020U) +#define GPIO_PODRE_POUT06_POS (6U) +#define GPIO_PODRE_POUT06 (0x0040U) +#define GPIO_PODRE_POUT07_POS (7U) +#define GPIO_PODRE_POUT07 (0x0080U) +#define GPIO_PODRE_POUT08_POS (8U) +#define GPIO_PODRE_POUT08 (0x0100U) +#define GPIO_PODRE_POUT09_POS (9U) +#define GPIO_PODRE_POUT09 (0x0200U) +#define GPIO_PODRE_POUT10_POS (10U) +#define GPIO_PODRE_POUT10 (0x0400U) +#define GPIO_PODRE_POUT11_POS (11U) +#define GPIO_PODRE_POUT11 (0x0800U) +#define GPIO_PODRE_POUT12_POS (12U) +#define GPIO_PODRE_POUT12 (0x1000U) +#define GPIO_PODRE_POUT13_POS (13U) +#define GPIO_PODRE_POUT13 (0x2000U) +#define GPIO_PODRE_POUT14_POS (14U) +#define GPIO_PODRE_POUT14 (0x4000U) +#define GPIO_PODRE_POUT15_POS (15U) +#define GPIO_PODRE_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERE register */ +#define GPIO_POERE_POUTE00_POS (0U) +#define GPIO_POERE_POUTE00 (0x0001U) +#define GPIO_POERE_POUTE01_POS (1U) +#define GPIO_POERE_POUTE01 (0x0002U) +#define GPIO_POERE_POUTE02_POS (2U) +#define GPIO_POERE_POUTE02 (0x0004U) +#define GPIO_POERE_POUTE03_POS (3U) +#define GPIO_POERE_POUTE03 (0x0008U) +#define GPIO_POERE_POUTE04_POS (4U) +#define GPIO_POERE_POUTE04 (0x0010U) +#define GPIO_POERE_POUTE05_POS (5U) +#define GPIO_POERE_POUTE05 (0x0020U) +#define GPIO_POERE_POUTE06_POS (6U) +#define GPIO_POERE_POUTE06 (0x0040U) +#define GPIO_POERE_POUTE07_POS (7U) +#define GPIO_POERE_POUTE07 (0x0080U) +#define GPIO_POERE_POUTE08_POS (8U) +#define GPIO_POERE_POUTE08 (0x0100U) +#define GPIO_POERE_POUTE09_POS (9U) +#define GPIO_POERE_POUTE09 (0x0200U) +#define GPIO_POERE_POUTE10_POS (10U) +#define GPIO_POERE_POUTE10 (0x0400U) +#define GPIO_POERE_POUTE11_POS (11U) +#define GPIO_POERE_POUTE11 (0x0800U) +#define GPIO_POERE_POUTE12_POS (12U) +#define GPIO_POERE_POUTE12 (0x1000U) +#define GPIO_POERE_POUTE13_POS (13U) +#define GPIO_POERE_POUTE13 (0x2000U) +#define GPIO_POERE_POUTE14_POS (14U) +#define GPIO_POERE_POUTE14 (0x4000U) +#define GPIO_POERE_POUTE15_POS (15U) +#define GPIO_POERE_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRE register */ +#define GPIO_POSRE_POS00_POS (0U) +#define GPIO_POSRE_POS00 (0x0001U) +#define GPIO_POSRE_POS01_POS (1U) +#define GPIO_POSRE_POS01 (0x0002U) +#define GPIO_POSRE_POS02_POS (2U) +#define GPIO_POSRE_POS02 (0x0004U) +#define GPIO_POSRE_POS03_POS (3U) +#define GPIO_POSRE_POS03 (0x0008U) +#define GPIO_POSRE_POS04_POS (4U) +#define GPIO_POSRE_POS04 (0x0010U) +#define GPIO_POSRE_POS05_POS (5U) +#define GPIO_POSRE_POS05 (0x0020U) +#define GPIO_POSRE_POS06_POS (6U) +#define GPIO_POSRE_POS06 (0x0040U) +#define GPIO_POSRE_POS07_POS (7U) +#define GPIO_POSRE_POS07 (0x0080U) +#define GPIO_POSRE_POS08_POS (8U) +#define GPIO_POSRE_POS08 (0x0100U) +#define GPIO_POSRE_POS09_POS (9U) +#define GPIO_POSRE_POS09 (0x0200U) +#define GPIO_POSRE_POS10_POS (10U) +#define GPIO_POSRE_POS10 (0x0400U) +#define GPIO_POSRE_POS11_POS (11U) +#define GPIO_POSRE_POS11 (0x0800U) +#define GPIO_POSRE_POS12_POS (12U) +#define GPIO_POSRE_POS12 (0x1000U) +#define GPIO_POSRE_POS13_POS (13U) +#define GPIO_POSRE_POS13 (0x2000U) +#define GPIO_POSRE_POS14_POS (14U) +#define GPIO_POSRE_POS14 (0x4000U) +#define GPIO_POSRE_POS15_POS (15U) +#define GPIO_POSRE_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRE register */ +#define GPIO_PORRE_POR00_POS (0U) +#define GPIO_PORRE_POR00 (0x0001U) +#define GPIO_PORRE_POR01_POS (1U) +#define GPIO_PORRE_POR01 (0x0002U) +#define GPIO_PORRE_POR02_POS (2U) +#define GPIO_PORRE_POR02 (0x0004U) +#define GPIO_PORRE_POR03_POS (3U) +#define GPIO_PORRE_POR03 (0x0008U) +#define GPIO_PORRE_POR04_POS (4U) +#define GPIO_PORRE_POR04 (0x0010U) +#define GPIO_PORRE_POR05_POS (5U) +#define GPIO_PORRE_POR05 (0x0020U) +#define GPIO_PORRE_POR06_POS (6U) +#define GPIO_PORRE_POR06 (0x0040U) +#define GPIO_PORRE_POR07_POS (7U) +#define GPIO_PORRE_POR07 (0x0080U) +#define GPIO_PORRE_POR08_POS (8U) +#define GPIO_PORRE_POR08 (0x0100U) +#define GPIO_PORRE_POR09_POS (9U) +#define GPIO_PORRE_POR09 (0x0200U) +#define GPIO_PORRE_POR10_POS (10U) +#define GPIO_PORRE_POR10 (0x0400U) +#define GPIO_PORRE_POR11_POS (11U) +#define GPIO_PORRE_POR11 (0x0800U) +#define GPIO_PORRE_POR12_POS (12U) +#define GPIO_PORRE_POR12 (0x1000U) +#define GPIO_PORRE_POR13_POS (13U) +#define GPIO_PORRE_POR13 (0x2000U) +#define GPIO_PORRE_POR14_POS (14U) +#define GPIO_PORRE_POR14 (0x4000U) +#define GPIO_PORRE_POR15_POS (15U) +#define GPIO_PORRE_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRE register */ +#define GPIO_POTRE_POT00_POS (0U) +#define GPIO_POTRE_POT00 (0x0001U) +#define GPIO_POTRE_POT01_POS (1U) +#define GPIO_POTRE_POT01 (0x0002U) +#define GPIO_POTRE_POT02_POS (2U) +#define GPIO_POTRE_POT02 (0x0004U) +#define GPIO_POTRE_POT03_POS (3U) +#define GPIO_POTRE_POT03 (0x0008U) +#define GPIO_POTRE_POT04_POS (4U) +#define GPIO_POTRE_POT04 (0x0010U) +#define GPIO_POTRE_POT05_POS (5U) +#define GPIO_POTRE_POT05 (0x0020U) +#define GPIO_POTRE_POT06_POS (6U) +#define GPIO_POTRE_POT06 (0x0040U) +#define GPIO_POTRE_POT07_POS (7U) +#define GPIO_POTRE_POT07 (0x0080U) +#define GPIO_POTRE_POT08_POS (8U) +#define GPIO_POTRE_POT08 (0x0100U) +#define GPIO_POTRE_POT09_POS (9U) +#define GPIO_POTRE_POT09 (0x0200U) +#define GPIO_POTRE_POT10_POS (10U) +#define GPIO_POTRE_POT10 (0x0400U) +#define GPIO_POTRE_POT11_POS (11U) +#define GPIO_POTRE_POT11 (0x0800U) +#define GPIO_POTRE_POT12_POS (12U) +#define GPIO_POTRE_POT12 (0x1000U) +#define GPIO_POTRE_POT13_POS (13U) +#define GPIO_POTRE_POT13 (0x2000U) +#define GPIO_POTRE_POT14_POS (14U) +#define GPIO_POTRE_POT14 (0x4000U) +#define GPIO_POTRE_POT15_POS (15U) +#define GPIO_POTRE_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRF register */ +#define GPIO_PIDRF_PIN00_POS (0U) +#define GPIO_PIDRF_PIN00 (0x0001U) +#define GPIO_PIDRF_PIN01_POS (1U) +#define GPIO_PIDRF_PIN01 (0x0002U) +#define GPIO_PIDRF_PIN02_POS (2U) +#define GPIO_PIDRF_PIN02 (0x0004U) +#define GPIO_PIDRF_PIN03_POS (3U) +#define GPIO_PIDRF_PIN03 (0x0008U) +#define GPIO_PIDRF_PIN04_POS (4U) +#define GPIO_PIDRF_PIN04 (0x0010U) +#define GPIO_PIDRF_PIN05_POS (5U) +#define GPIO_PIDRF_PIN05 (0x0020U) +#define GPIO_PIDRF_PIN06_POS (6U) +#define GPIO_PIDRF_PIN06 (0x0040U) +#define GPIO_PIDRF_PIN07_POS (7U) +#define GPIO_PIDRF_PIN07 (0x0080U) +#define GPIO_PIDRF_PIN08_POS (8U) +#define GPIO_PIDRF_PIN08 (0x0100U) +#define GPIO_PIDRF_PIN09_POS (9U) +#define GPIO_PIDRF_PIN09 (0x0200U) +#define GPIO_PIDRF_PIN10_POS (10U) +#define GPIO_PIDRF_PIN10 (0x0400U) +#define GPIO_PIDRF_PIN11_POS (11U) +#define GPIO_PIDRF_PIN11 (0x0800U) +#define GPIO_PIDRF_PIN12_POS (12U) +#define GPIO_PIDRF_PIN12 (0x1000U) +#define GPIO_PIDRF_PIN13_POS (13U) +#define GPIO_PIDRF_PIN13 (0x2000U) +#define GPIO_PIDRF_PIN14_POS (14U) +#define GPIO_PIDRF_PIN14 (0x4000U) +#define GPIO_PIDRF_PIN15_POS (15U) +#define GPIO_PIDRF_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRF register */ +#define GPIO_PODRF_POUT00_POS (0U) +#define GPIO_PODRF_POUT00 (0x0001U) +#define GPIO_PODRF_POUT01_POS (1U) +#define GPIO_PODRF_POUT01 (0x0002U) +#define GPIO_PODRF_POUT02_POS (2U) +#define GPIO_PODRF_POUT02 (0x0004U) +#define GPIO_PODRF_POUT03_POS (3U) +#define GPIO_PODRF_POUT03 (0x0008U) +#define GPIO_PODRF_POUT04_POS (4U) +#define GPIO_PODRF_POUT04 (0x0010U) +#define GPIO_PODRF_POUT05_POS (5U) +#define GPIO_PODRF_POUT05 (0x0020U) +#define GPIO_PODRF_POUT06_POS (6U) +#define GPIO_PODRF_POUT06 (0x0040U) +#define GPIO_PODRF_POUT07_POS (7U) +#define GPIO_PODRF_POUT07 (0x0080U) +#define GPIO_PODRF_POUT08_POS (8U) +#define GPIO_PODRF_POUT08 (0x0100U) +#define GPIO_PODRF_POUT09_POS (9U) +#define GPIO_PODRF_POUT09 (0x0200U) +#define GPIO_PODRF_POUT10_POS (10U) +#define GPIO_PODRF_POUT10 (0x0400U) +#define GPIO_PODRF_POUT11_POS (11U) +#define GPIO_PODRF_POUT11 (0x0800U) +#define GPIO_PODRF_POUT12_POS (12U) +#define GPIO_PODRF_POUT12 (0x1000U) +#define GPIO_PODRF_POUT13_POS (13U) +#define GPIO_PODRF_POUT13 (0x2000U) +#define GPIO_PODRF_POUT14_POS (14U) +#define GPIO_PODRF_POUT14 (0x4000U) +#define GPIO_PODRF_POUT15_POS (15U) +#define GPIO_PODRF_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERF register */ +#define GPIO_POERF_POUTE00_POS (0U) +#define GPIO_POERF_POUTE00 (0x0001U) +#define GPIO_POERF_POUTE01_POS (1U) +#define GPIO_POERF_POUTE01 (0x0002U) +#define GPIO_POERF_POUTE02_POS (2U) +#define GPIO_POERF_POUTE02 (0x0004U) +#define GPIO_POERF_POUTE03_POS (3U) +#define GPIO_POERF_POUTE03 (0x0008U) +#define GPIO_POERF_POUTE04_POS (4U) +#define GPIO_POERF_POUTE04 (0x0010U) +#define GPIO_POERF_POUTE05_POS (5U) +#define GPIO_POERF_POUTE05 (0x0020U) +#define GPIO_POERF_POUTE06_POS (6U) +#define GPIO_POERF_POUTE06 (0x0040U) +#define GPIO_POERF_POUTE07_POS (7U) +#define GPIO_POERF_POUTE07 (0x0080U) +#define GPIO_POERF_POUTE08_POS (8U) +#define GPIO_POERF_POUTE08 (0x0100U) +#define GPIO_POERF_POUTE09_POS (9U) +#define GPIO_POERF_POUTE09 (0x0200U) +#define GPIO_POERF_POUTE10_POS (10U) +#define GPIO_POERF_POUTE10 (0x0400U) +#define GPIO_POERF_POUTE11_POS (11U) +#define GPIO_POERF_POUTE11 (0x0800U) +#define GPIO_POERF_POUTE12_POS (12U) +#define GPIO_POERF_POUTE12 (0x1000U) +#define GPIO_POERF_POUTE13_POS (13U) +#define GPIO_POERF_POUTE13 (0x2000U) +#define GPIO_POERF_POUTE14_POS (14U) +#define GPIO_POERF_POUTE14 (0x4000U) +#define GPIO_POERF_POUTE15_POS (15U) +#define GPIO_POERF_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRF register */ +#define GPIO_POSRF_POS00_POS (0U) +#define GPIO_POSRF_POS00 (0x0001U) +#define GPIO_POSRF_POS01_POS (1U) +#define GPIO_POSRF_POS01 (0x0002U) +#define GPIO_POSRF_POS02_POS (2U) +#define GPIO_POSRF_POS02 (0x0004U) +#define GPIO_POSRF_POS03_POS (3U) +#define GPIO_POSRF_POS03 (0x0008U) +#define GPIO_POSRF_POS04_POS (4U) +#define GPIO_POSRF_POS04 (0x0010U) +#define GPIO_POSRF_POS05_POS (5U) +#define GPIO_POSRF_POS05 (0x0020U) +#define GPIO_POSRF_POS06_POS (6U) +#define GPIO_POSRF_POS06 (0x0040U) +#define GPIO_POSRF_POS07_POS (7U) +#define GPIO_POSRF_POS07 (0x0080U) +#define GPIO_POSRF_POS08_POS (8U) +#define GPIO_POSRF_POS08 (0x0100U) +#define GPIO_POSRF_POS09_POS (9U) +#define GPIO_POSRF_POS09 (0x0200U) +#define GPIO_POSRF_POS10_POS (10U) +#define GPIO_POSRF_POS10 (0x0400U) +#define GPIO_POSRF_POS11_POS (11U) +#define GPIO_POSRF_POS11 (0x0800U) +#define GPIO_POSRF_POS12_POS (12U) +#define GPIO_POSRF_POS12 (0x1000U) +#define GPIO_POSRF_POS13_POS (13U) +#define GPIO_POSRF_POS13 (0x2000U) +#define GPIO_POSRF_POS14_POS (14U) +#define GPIO_POSRF_POS14 (0x4000U) +#define GPIO_POSRF_POS15_POS (15U) +#define GPIO_POSRF_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRF register */ +#define GPIO_PORRF_POR00_POS (0U) +#define GPIO_PORRF_POR00 (0x0001U) +#define GPIO_PORRF_POR01_POS (1U) +#define GPIO_PORRF_POR01 (0x0002U) +#define GPIO_PORRF_POR02_POS (2U) +#define GPIO_PORRF_POR02 (0x0004U) +#define GPIO_PORRF_POR03_POS (3U) +#define GPIO_PORRF_POR03 (0x0008U) +#define GPIO_PORRF_POR04_POS (4U) +#define GPIO_PORRF_POR04 (0x0010U) +#define GPIO_PORRF_POR05_POS (5U) +#define GPIO_PORRF_POR05 (0x0020U) +#define GPIO_PORRF_POR06_POS (6U) +#define GPIO_PORRF_POR06 (0x0040U) +#define GPIO_PORRF_POR07_POS (7U) +#define GPIO_PORRF_POR07 (0x0080U) +#define GPIO_PORRF_POR08_POS (8U) +#define GPIO_PORRF_POR08 (0x0100U) +#define GPIO_PORRF_POR09_POS (9U) +#define GPIO_PORRF_POR09 (0x0200U) +#define GPIO_PORRF_POR10_POS (10U) +#define GPIO_PORRF_POR10 (0x0400U) +#define GPIO_PORRF_POR11_POS (11U) +#define GPIO_PORRF_POR11 (0x0800U) +#define GPIO_PORRF_POR12_POS (12U) +#define GPIO_PORRF_POR12 (0x1000U) +#define GPIO_PORRF_POR13_POS (13U) +#define GPIO_PORRF_POR13 (0x2000U) +#define GPIO_PORRF_POR14_POS (14U) +#define GPIO_PORRF_POR14 (0x4000U) +#define GPIO_PORRF_POR15_POS (15U) +#define GPIO_PORRF_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRF register */ +#define GPIO_POTRF_POT00_POS (0U) +#define GPIO_POTRF_POT00 (0x0001U) +#define GPIO_POTRF_POT01_POS (1U) +#define GPIO_POTRF_POT01 (0x0002U) +#define GPIO_POTRF_POT02_POS (2U) +#define GPIO_POTRF_POT02 (0x0004U) +#define GPIO_POTRF_POT03_POS (3U) +#define GPIO_POTRF_POT03 (0x0008U) +#define GPIO_POTRF_POT04_POS (4U) +#define GPIO_POTRF_POT04 (0x0010U) +#define GPIO_POTRF_POT05_POS (5U) +#define GPIO_POTRF_POT05 (0x0020U) +#define GPIO_POTRF_POT06_POS (6U) +#define GPIO_POTRF_POT06 (0x0040U) +#define GPIO_POTRF_POT07_POS (7U) +#define GPIO_POTRF_POT07 (0x0080U) +#define GPIO_POTRF_POT08_POS (8U) +#define GPIO_POTRF_POT08 (0x0100U) +#define GPIO_POTRF_POT09_POS (9U) +#define GPIO_POTRF_POT09 (0x0200U) +#define GPIO_POTRF_POT10_POS (10U) +#define GPIO_POTRF_POT10 (0x0400U) +#define GPIO_POTRF_POT11_POS (11U) +#define GPIO_POTRF_POT11 (0x0800U) +#define GPIO_POTRF_POT12_POS (12U) +#define GPIO_POTRF_POT12 (0x1000U) +#define GPIO_POTRF_POT13_POS (13U) +#define GPIO_POTRF_POT13 (0x2000U) +#define GPIO_POTRF_POT14_POS (14U) +#define GPIO_POTRF_POT14 (0x4000U) +#define GPIO_POTRF_POT15_POS (15U) +#define GPIO_POTRF_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRG register */ +#define GPIO_PIDRG_PIN00_POS (0U) +#define GPIO_PIDRG_PIN00 (0x0001U) +#define GPIO_PIDRG_PIN01_POS (1U) +#define GPIO_PIDRG_PIN01 (0x0002U) +#define GPIO_PIDRG_PIN02_POS (2U) +#define GPIO_PIDRG_PIN02 (0x0004U) +#define GPIO_PIDRG_PIN03_POS (3U) +#define GPIO_PIDRG_PIN03 (0x0008U) +#define GPIO_PIDRG_PIN04_POS (4U) +#define GPIO_PIDRG_PIN04 (0x0010U) +#define GPIO_PIDRG_PIN05_POS (5U) +#define GPIO_PIDRG_PIN05 (0x0020U) +#define GPIO_PIDRG_PIN06_POS (6U) +#define GPIO_PIDRG_PIN06 (0x0040U) +#define GPIO_PIDRG_PIN07_POS (7U) +#define GPIO_PIDRG_PIN07 (0x0080U) +#define GPIO_PIDRG_PIN08_POS (8U) +#define GPIO_PIDRG_PIN08 (0x0100U) +#define GPIO_PIDRG_PIN09_POS (9U) +#define GPIO_PIDRG_PIN09 (0x0200U) +#define GPIO_PIDRG_PIN10_POS (10U) +#define GPIO_PIDRG_PIN10 (0x0400U) +#define GPIO_PIDRG_PIN11_POS (11U) +#define GPIO_PIDRG_PIN11 (0x0800U) +#define GPIO_PIDRG_PIN12_POS (12U) +#define GPIO_PIDRG_PIN12 (0x1000U) +#define GPIO_PIDRG_PIN13_POS (13U) +#define GPIO_PIDRG_PIN13 (0x2000U) +#define GPIO_PIDRG_PIN14_POS (14U) +#define GPIO_PIDRG_PIN14 (0x4000U) +#define GPIO_PIDRG_PIN15_POS (15U) +#define GPIO_PIDRG_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRG register */ +#define GPIO_PODRG_POUT00_POS (0U) +#define GPIO_PODRG_POUT00 (0x0001U) +#define GPIO_PODRG_POUT01_POS (1U) +#define GPIO_PODRG_POUT01 (0x0002U) +#define GPIO_PODRG_POUT02_POS (2U) +#define GPIO_PODRG_POUT02 (0x0004U) +#define GPIO_PODRG_POUT03_POS (3U) +#define GPIO_PODRG_POUT03 (0x0008U) +#define GPIO_PODRG_POUT04_POS (4U) +#define GPIO_PODRG_POUT04 (0x0010U) +#define GPIO_PODRG_POUT05_POS (5U) +#define GPIO_PODRG_POUT05 (0x0020U) +#define GPIO_PODRG_POUT06_POS (6U) +#define GPIO_PODRG_POUT06 (0x0040U) +#define GPIO_PODRG_POUT07_POS (7U) +#define GPIO_PODRG_POUT07 (0x0080U) +#define GPIO_PODRG_POUT08_POS (8U) +#define GPIO_PODRG_POUT08 (0x0100U) +#define GPIO_PODRG_POUT09_POS (9U) +#define GPIO_PODRG_POUT09 (0x0200U) +#define GPIO_PODRG_POUT10_POS (10U) +#define GPIO_PODRG_POUT10 (0x0400U) +#define GPIO_PODRG_POUT11_POS (11U) +#define GPIO_PODRG_POUT11 (0x0800U) +#define GPIO_PODRG_POUT12_POS (12U) +#define GPIO_PODRG_POUT12 (0x1000U) +#define GPIO_PODRG_POUT13_POS (13U) +#define GPIO_PODRG_POUT13 (0x2000U) +#define GPIO_PODRG_POUT14_POS (14U) +#define GPIO_PODRG_POUT14 (0x4000U) +#define GPIO_PODRG_POUT15_POS (15U) +#define GPIO_PODRG_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERG register */ +#define GPIO_POERG_POUTE00_POS (0U) +#define GPIO_POERG_POUTE00 (0x0001U) +#define GPIO_POERG_POUTE01_POS (1U) +#define GPIO_POERG_POUTE01 (0x0002U) +#define GPIO_POERG_POUTE02_POS (2U) +#define GPIO_POERG_POUTE02 (0x0004U) +#define GPIO_POERG_POUTE03_POS (3U) +#define GPIO_POERG_POUTE03 (0x0008U) +#define GPIO_POERG_POUTE04_POS (4U) +#define GPIO_POERG_POUTE04 (0x0010U) +#define GPIO_POERG_POUTE05_POS (5U) +#define GPIO_POERG_POUTE05 (0x0020U) +#define GPIO_POERG_POUTE06_POS (6U) +#define GPIO_POERG_POUTE06 (0x0040U) +#define GPIO_POERG_POUTE07_POS (7U) +#define GPIO_POERG_POUTE07 (0x0080U) +#define GPIO_POERG_POUTE08_POS (8U) +#define GPIO_POERG_POUTE08 (0x0100U) +#define GPIO_POERG_POUTE09_POS (9U) +#define GPIO_POERG_POUTE09 (0x0200U) +#define GPIO_POERG_POUTE10_POS (10U) +#define GPIO_POERG_POUTE10 (0x0400U) +#define GPIO_POERG_POUTE11_POS (11U) +#define GPIO_POERG_POUTE11 (0x0800U) +#define GPIO_POERG_POUTE12_POS (12U) +#define GPIO_POERG_POUTE12 (0x1000U) +#define GPIO_POERG_POUTE13_POS (13U) +#define GPIO_POERG_POUTE13 (0x2000U) +#define GPIO_POERG_POUTE14_POS (14U) +#define GPIO_POERG_POUTE14 (0x4000U) +#define GPIO_POERG_POUTE15_POS (15U) +#define GPIO_POERG_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRG register */ +#define GPIO_POSRG_POS00_POS (0U) +#define GPIO_POSRG_POS00 (0x0001U) +#define GPIO_POSRG_POS01_POS (1U) +#define GPIO_POSRG_POS01 (0x0002U) +#define GPIO_POSRG_POS02_POS (2U) +#define GPIO_POSRG_POS02 (0x0004U) +#define GPIO_POSRG_POS03_POS (3U) +#define GPIO_POSRG_POS03 (0x0008U) +#define GPIO_POSRG_POS04_POS (4U) +#define GPIO_POSRG_POS04 (0x0010U) +#define GPIO_POSRG_POS05_POS (5U) +#define GPIO_POSRG_POS05 (0x0020U) +#define GPIO_POSRG_POS06_POS (6U) +#define GPIO_POSRG_POS06 (0x0040U) +#define GPIO_POSRG_POS07_POS (7U) +#define GPIO_POSRG_POS07 (0x0080U) +#define GPIO_POSRG_POS08_POS (8U) +#define GPIO_POSRG_POS08 (0x0100U) +#define GPIO_POSRG_POS09_POS (9U) +#define GPIO_POSRG_POS09 (0x0200U) +#define GPIO_POSRG_POS10_POS (10U) +#define GPIO_POSRG_POS10 (0x0400U) +#define GPIO_POSRG_POS11_POS (11U) +#define GPIO_POSRG_POS11 (0x0800U) +#define GPIO_POSRG_POS12_POS (12U) +#define GPIO_POSRG_POS12 (0x1000U) +#define GPIO_POSRG_POS13_POS (13U) +#define GPIO_POSRG_POS13 (0x2000U) +#define GPIO_POSRG_POS14_POS (14U) +#define GPIO_POSRG_POS14 (0x4000U) +#define GPIO_POSRG_POS15_POS (15U) +#define GPIO_POSRG_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRG register */ +#define GPIO_PORRG_POR00_POS (0U) +#define GPIO_PORRG_POR00 (0x0001U) +#define GPIO_PORRG_POR01_POS (1U) +#define GPIO_PORRG_POR01 (0x0002U) +#define GPIO_PORRG_POR02_POS (2U) +#define GPIO_PORRG_POR02 (0x0004U) +#define GPIO_PORRG_POR03_POS (3U) +#define GPIO_PORRG_POR03 (0x0008U) +#define GPIO_PORRG_POR04_POS (4U) +#define GPIO_PORRG_POR04 (0x0010U) +#define GPIO_PORRG_POR05_POS (5U) +#define GPIO_PORRG_POR05 (0x0020U) +#define GPIO_PORRG_POR06_POS (6U) +#define GPIO_PORRG_POR06 (0x0040U) +#define GPIO_PORRG_POR07_POS (7U) +#define GPIO_PORRG_POR07 (0x0080U) +#define GPIO_PORRG_POR08_POS (8U) +#define GPIO_PORRG_POR08 (0x0100U) +#define GPIO_PORRG_POR09_POS (9U) +#define GPIO_PORRG_POR09 (0x0200U) +#define GPIO_PORRG_POR10_POS (10U) +#define GPIO_PORRG_POR10 (0x0400U) +#define GPIO_PORRG_POR11_POS (11U) +#define GPIO_PORRG_POR11 (0x0800U) +#define GPIO_PORRG_POR12_POS (12U) +#define GPIO_PORRG_POR12 (0x1000U) +#define GPIO_PORRG_POR13_POS (13U) +#define GPIO_PORRG_POR13 (0x2000U) +#define GPIO_PORRG_POR14_POS (14U) +#define GPIO_PORRG_POR14 (0x4000U) +#define GPIO_PORRG_POR15_POS (15U) +#define GPIO_PORRG_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRG register */ +#define GPIO_POTRG_POT00_POS (0U) +#define GPIO_POTRG_POT00 (0x0001U) +#define GPIO_POTRG_POT01_POS (1U) +#define GPIO_POTRG_POT01 (0x0002U) +#define GPIO_POTRG_POT02_POS (2U) +#define GPIO_POTRG_POT02 (0x0004U) +#define GPIO_POTRG_POT03_POS (3U) +#define GPIO_POTRG_POT03 (0x0008U) +#define GPIO_POTRG_POT04_POS (4U) +#define GPIO_POTRG_POT04 (0x0010U) +#define GPIO_POTRG_POT05_POS (5U) +#define GPIO_POTRG_POT05 (0x0020U) +#define GPIO_POTRG_POT06_POS (6U) +#define GPIO_POTRG_POT06 (0x0040U) +#define GPIO_POTRG_POT07_POS (7U) +#define GPIO_POTRG_POT07 (0x0080U) +#define GPIO_POTRG_POT08_POS (8U) +#define GPIO_POTRG_POT08 (0x0100U) +#define GPIO_POTRG_POT09_POS (9U) +#define GPIO_POTRG_POT09 (0x0200U) +#define GPIO_POTRG_POT10_POS (10U) +#define GPIO_POTRG_POT10 (0x0400U) +#define GPIO_POTRG_POT11_POS (11U) +#define GPIO_POTRG_POT11 (0x0800U) +#define GPIO_POTRG_POT12_POS (12U) +#define GPIO_POTRG_POT12 (0x1000U) +#define GPIO_POTRG_POT13_POS (13U) +#define GPIO_POTRG_POT13 (0x2000U) +#define GPIO_POTRG_POT14_POS (14U) +#define GPIO_POTRG_POT14 (0x4000U) +#define GPIO_POTRG_POT15_POS (15U) +#define GPIO_POTRG_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRH register */ +#define GPIO_PIDRH_PIN00_POS (0U) +#define GPIO_PIDRH_PIN00 (0x0001U) +#define GPIO_PIDRH_PIN01_POS (1U) +#define GPIO_PIDRH_PIN01 (0x0002U) +#define GPIO_PIDRH_PIN02_POS (2U) +#define GPIO_PIDRH_PIN02 (0x0004U) +#define GPIO_PIDRH_PIN03_POS (3U) +#define GPIO_PIDRH_PIN03 (0x0008U) +#define GPIO_PIDRH_PIN04_POS (4U) +#define GPIO_PIDRH_PIN04 (0x0010U) +#define GPIO_PIDRH_PIN05_POS (5U) +#define GPIO_PIDRH_PIN05 (0x0020U) +#define GPIO_PIDRH_PIN06_POS (6U) +#define GPIO_PIDRH_PIN06 (0x0040U) +#define GPIO_PIDRH_PIN07_POS (7U) +#define GPIO_PIDRH_PIN07 (0x0080U) +#define GPIO_PIDRH_PIN08_POS (8U) +#define GPIO_PIDRH_PIN08 (0x0100U) +#define GPIO_PIDRH_PIN09_POS (9U) +#define GPIO_PIDRH_PIN09 (0x0200U) +#define GPIO_PIDRH_PIN10_POS (10U) +#define GPIO_PIDRH_PIN10 (0x0400U) +#define GPIO_PIDRH_PIN11_POS (11U) +#define GPIO_PIDRH_PIN11 (0x0800U) +#define GPIO_PIDRH_PIN12_POS (12U) +#define GPIO_PIDRH_PIN12 (0x1000U) +#define GPIO_PIDRH_PIN13_POS (13U) +#define GPIO_PIDRH_PIN13 (0x2000U) +#define GPIO_PIDRH_PIN14_POS (14U) +#define GPIO_PIDRH_PIN14 (0x4000U) +#define GPIO_PIDRH_PIN15_POS (15U) +#define GPIO_PIDRH_PIN15 (0x8000U) + +/* Bit definition for GPIO_PODRH register */ +#define GPIO_PODRH_POUT00_POS (0U) +#define GPIO_PODRH_POUT00 (0x0001U) +#define GPIO_PODRH_POUT01_POS (1U) +#define GPIO_PODRH_POUT01 (0x0002U) +#define GPIO_PODRH_POUT02_POS (2U) +#define GPIO_PODRH_POUT02 (0x0004U) +#define GPIO_PODRH_POUT03_POS (3U) +#define GPIO_PODRH_POUT03 (0x0008U) +#define GPIO_PODRH_POUT04_POS (4U) +#define GPIO_PODRH_POUT04 (0x0010U) +#define GPIO_PODRH_POUT05_POS (5U) +#define GPIO_PODRH_POUT05 (0x0020U) +#define GPIO_PODRH_POUT06_POS (6U) +#define GPIO_PODRH_POUT06 (0x0040U) +#define GPIO_PODRH_POUT07_POS (7U) +#define GPIO_PODRH_POUT07 (0x0080U) +#define GPIO_PODRH_POUT08_POS (8U) +#define GPIO_PODRH_POUT08 (0x0100U) +#define GPIO_PODRH_POUT09_POS (9U) +#define GPIO_PODRH_POUT09 (0x0200U) +#define GPIO_PODRH_POUT10_POS (10U) +#define GPIO_PODRH_POUT10 (0x0400U) +#define GPIO_PODRH_POUT11_POS (11U) +#define GPIO_PODRH_POUT11 (0x0800U) +#define GPIO_PODRH_POUT12_POS (12U) +#define GPIO_PODRH_POUT12 (0x1000U) +#define GPIO_PODRH_POUT13_POS (13U) +#define GPIO_PODRH_POUT13 (0x2000U) +#define GPIO_PODRH_POUT14_POS (14U) +#define GPIO_PODRH_POUT14 (0x4000U) +#define GPIO_PODRH_POUT15_POS (15U) +#define GPIO_PODRH_POUT15 (0x8000U) + +/* Bit definition for GPIO_POERH register */ +#define GPIO_POERH_POUTE00_POS (0U) +#define GPIO_POERH_POUTE00 (0x0001U) +#define GPIO_POERH_POUTE01_POS (1U) +#define GPIO_POERH_POUTE01 (0x0002U) +#define GPIO_POERH_POUTE02_POS (2U) +#define GPIO_POERH_POUTE02 (0x0004U) +#define GPIO_POERH_POUTE03_POS (3U) +#define GPIO_POERH_POUTE03 (0x0008U) +#define GPIO_POERH_POUTE04_POS (4U) +#define GPIO_POERH_POUTE04 (0x0010U) +#define GPIO_POERH_POUTE05_POS (5U) +#define GPIO_POERH_POUTE05 (0x0020U) +#define GPIO_POERH_POUTE06_POS (6U) +#define GPIO_POERH_POUTE06 (0x0040U) +#define GPIO_POERH_POUTE07_POS (7U) +#define GPIO_POERH_POUTE07 (0x0080U) +#define GPIO_POERH_POUTE08_POS (8U) +#define GPIO_POERH_POUTE08 (0x0100U) +#define GPIO_POERH_POUTE09_POS (9U) +#define GPIO_POERH_POUTE09 (0x0200U) +#define GPIO_POERH_POUTE10_POS (10U) +#define GPIO_POERH_POUTE10 (0x0400U) +#define GPIO_POERH_POUTE11_POS (11U) +#define GPIO_POERH_POUTE11 (0x0800U) +#define GPIO_POERH_POUTE12_POS (12U) +#define GPIO_POERH_POUTE12 (0x1000U) +#define GPIO_POERH_POUTE13_POS (13U) +#define GPIO_POERH_POUTE13 (0x2000U) +#define GPIO_POERH_POUTE14_POS (14U) +#define GPIO_POERH_POUTE14 (0x4000U) +#define GPIO_POERH_POUTE15_POS (15U) +#define GPIO_POERH_POUTE15 (0x8000U) + +/* Bit definition for GPIO_POSRH register */ +#define GPIO_POSRH_POS00_POS (0U) +#define GPIO_POSRH_POS00 (0x0001U) +#define GPIO_POSRH_POS01_POS (1U) +#define GPIO_POSRH_POS01 (0x0002U) +#define GPIO_POSRH_POS02_POS (2U) +#define GPIO_POSRH_POS02 (0x0004U) +#define GPIO_POSRH_POS03_POS (3U) +#define GPIO_POSRH_POS03 (0x0008U) +#define GPIO_POSRH_POS04_POS (4U) +#define GPIO_POSRH_POS04 (0x0010U) +#define GPIO_POSRH_POS05_POS (5U) +#define GPIO_POSRH_POS05 (0x0020U) +#define GPIO_POSRH_POS06_POS (6U) +#define GPIO_POSRH_POS06 (0x0040U) +#define GPIO_POSRH_POS07_POS (7U) +#define GPIO_POSRH_POS07 (0x0080U) +#define GPIO_POSRH_POS08_POS (8U) +#define GPIO_POSRH_POS08 (0x0100U) +#define GPIO_POSRH_POS09_POS (9U) +#define GPIO_POSRH_POS09 (0x0200U) +#define GPIO_POSRH_POS10_POS (10U) +#define GPIO_POSRH_POS10 (0x0400U) +#define GPIO_POSRH_POS11_POS (11U) +#define GPIO_POSRH_POS11 (0x0800U) +#define GPIO_POSRH_POS12_POS (12U) +#define GPIO_POSRH_POS12 (0x1000U) +#define GPIO_POSRH_POS13_POS (13U) +#define GPIO_POSRH_POS13 (0x2000U) +#define GPIO_POSRH_POS14_POS (14U) +#define GPIO_POSRH_POS14 (0x4000U) +#define GPIO_POSRH_POS15_POS (15U) +#define GPIO_POSRH_POS15 (0x8000U) + +/* Bit definition for GPIO_PORRH register */ +#define GPIO_PORRH_POR00_POS (0U) +#define GPIO_PORRH_POR00 (0x0001U) +#define GPIO_PORRH_POR01_POS (1U) +#define GPIO_PORRH_POR01 (0x0002U) +#define GPIO_PORRH_POR02_POS (2U) +#define GPIO_PORRH_POR02 (0x0004U) +#define GPIO_PORRH_POR03_POS (3U) +#define GPIO_PORRH_POR03 (0x0008U) +#define GPIO_PORRH_POR04_POS (4U) +#define GPIO_PORRH_POR04 (0x0010U) +#define GPIO_PORRH_POR05_POS (5U) +#define GPIO_PORRH_POR05 (0x0020U) +#define GPIO_PORRH_POR06_POS (6U) +#define GPIO_PORRH_POR06 (0x0040U) +#define GPIO_PORRH_POR07_POS (7U) +#define GPIO_PORRH_POR07 (0x0080U) +#define GPIO_PORRH_POR08_POS (8U) +#define GPIO_PORRH_POR08 (0x0100U) +#define GPIO_PORRH_POR09_POS (9U) +#define GPIO_PORRH_POR09 (0x0200U) +#define GPIO_PORRH_POR10_POS (10U) +#define GPIO_PORRH_POR10 (0x0400U) +#define GPIO_PORRH_POR11_POS (11U) +#define GPIO_PORRH_POR11 (0x0800U) +#define GPIO_PORRH_POR12_POS (12U) +#define GPIO_PORRH_POR12 (0x1000U) +#define GPIO_PORRH_POR13_POS (13U) +#define GPIO_PORRH_POR13 (0x2000U) +#define GPIO_PORRH_POR14_POS (14U) +#define GPIO_PORRH_POR14 (0x4000U) +#define GPIO_PORRH_POR15_POS (15U) +#define GPIO_PORRH_POR15 (0x8000U) + +/* Bit definition for GPIO_POTRH register */ +#define GPIO_POTRH_POT00_POS (0U) +#define GPIO_POTRH_POT00 (0x0001U) +#define GPIO_POTRH_POT01_POS (1U) +#define GPIO_POTRH_POT01 (0x0002U) +#define GPIO_POTRH_POT02_POS (2U) +#define GPIO_POTRH_POT02 (0x0004U) +#define GPIO_POTRH_POT03_POS (3U) +#define GPIO_POTRH_POT03 (0x0008U) +#define GPIO_POTRH_POT04_POS (4U) +#define GPIO_POTRH_POT04 (0x0010U) +#define GPIO_POTRH_POT05_POS (5U) +#define GPIO_POTRH_POT05 (0x0020U) +#define GPIO_POTRH_POT06_POS (6U) +#define GPIO_POTRH_POT06 (0x0040U) +#define GPIO_POTRH_POT07_POS (7U) +#define GPIO_POTRH_POT07 (0x0080U) +#define GPIO_POTRH_POT08_POS (8U) +#define GPIO_POTRH_POT08 (0x0100U) +#define GPIO_POTRH_POT09_POS (9U) +#define GPIO_POTRH_POT09 (0x0200U) +#define GPIO_POTRH_POT10_POS (10U) +#define GPIO_POTRH_POT10 (0x0400U) +#define GPIO_POTRH_POT11_POS (11U) +#define GPIO_POTRH_POT11 (0x0800U) +#define GPIO_POTRH_POT12_POS (12U) +#define GPIO_POTRH_POT12 (0x1000U) +#define GPIO_POTRH_POT13_POS (13U) +#define GPIO_POTRH_POT13 (0x2000U) +#define GPIO_POTRH_POT14_POS (14U) +#define GPIO_POTRH_POT14 (0x4000U) +#define GPIO_POTRH_POT15_POS (15U) +#define GPIO_POTRH_POT15 (0x8000U) + +/* Bit definition for GPIO_PIDRI register */ +#define GPIO_PIDRI_PIN00_POS (0U) +#define GPIO_PIDRI_PIN00 (0x0001U) +#define GPIO_PIDRI_PIN01_POS (1U) +#define GPIO_PIDRI_PIN01 (0x0002U) +#define GPIO_PIDRI_PIN02_POS (2U) +#define GPIO_PIDRI_PIN02 (0x0004U) +#define GPIO_PIDRI_PIN03_POS (3U) +#define GPIO_PIDRI_PIN03 (0x0008U) +#define GPIO_PIDRI_PIN04_POS (4U) +#define GPIO_PIDRI_PIN04 (0x0010U) +#define GPIO_PIDRI_PIN05_POS (5U) +#define GPIO_PIDRI_PIN05 (0x0020U) +#define GPIO_PIDRI_PIN06_POS (6U) +#define GPIO_PIDRI_PIN06 (0x0040U) +#define GPIO_PIDRI_PIN07_POS (7U) +#define GPIO_PIDRI_PIN07 (0x0080U) +#define GPIO_PIDRI_PIN08_POS (8U) +#define GPIO_PIDRI_PIN08 (0x0100U) +#define GPIO_PIDRI_PIN09_POS (9U) +#define GPIO_PIDRI_PIN09 (0x0200U) +#define GPIO_PIDRI_PIN10_POS (10U) +#define GPIO_PIDRI_PIN10 (0x0400U) +#define GPIO_PIDRI_PIN11_POS (11U) +#define GPIO_PIDRI_PIN11 (0x0800U) +#define GPIO_PIDRI_PIN12_POS (12U) +#define GPIO_PIDRI_PIN12 (0x1000U) +#define GPIO_PIDRI_PIN13_POS (13U) +#define GPIO_PIDRI_PIN13 (0x2000U) + +/* Bit definition for GPIO_PODRI register */ +#define GPIO_PODRI_POUT00_POS (0U) +#define GPIO_PODRI_POUT00 (0x0001U) +#define GPIO_PODRI_POUT01_POS (1U) +#define GPIO_PODRI_POUT01 (0x0002U) +#define GPIO_PODRI_POUT02_POS (2U) +#define GPIO_PODRI_POUT02 (0x0004U) +#define GPIO_PODRI_POUT03_POS (3U) +#define GPIO_PODRI_POUT03 (0x0008U) +#define GPIO_PODRI_POUT04_POS (4U) +#define GPIO_PODRI_POUT04 (0x0010U) +#define GPIO_PODRI_POUT05_POS (5U) +#define GPIO_PODRI_POUT05 (0x0020U) +#define GPIO_PODRI_POUT06_POS (6U) +#define GPIO_PODRI_POUT06 (0x0040U) +#define GPIO_PODRI_POUT07_POS (7U) +#define GPIO_PODRI_POUT07 (0x0080U) +#define GPIO_PODRI_POUT08_POS (8U) +#define GPIO_PODRI_POUT08 (0x0100U) +#define GPIO_PODRI_POUT09_POS (9U) +#define GPIO_PODRI_POUT09 (0x0200U) +#define GPIO_PODRI_POUT10_POS (10U) +#define GPIO_PODRI_POUT10 (0x0400U) +#define GPIO_PODRI_POUT11_POS (11U) +#define GPIO_PODRI_POUT11 (0x0800U) +#define GPIO_PODRI_POUT12_POS (12U) +#define GPIO_PODRI_POUT12 (0x1000U) +#define GPIO_PODRI_POUT13_POS (13U) +#define GPIO_PODRI_POUT13 (0x2000U) + +/* Bit definition for GPIO_POERI register */ +#define GPIO_POERI_POUTE00_POS (0U) +#define GPIO_POERI_POUTE00 (0x0001U) +#define GPIO_POERI_POUTE01_POS (1U) +#define GPIO_POERI_POUTE01 (0x0002U) +#define GPIO_POERI_POUTE02_POS (2U) +#define GPIO_POERI_POUTE02 (0x0004U) +#define GPIO_POERI_POUTE03_POS (3U) +#define GPIO_POERI_POUTE03 (0x0008U) +#define GPIO_POERI_POUTE04_POS (4U) +#define GPIO_POERI_POUTE04 (0x0010U) +#define GPIO_POERI_POUTE05_POS (5U) +#define GPIO_POERI_POUTE05 (0x0020U) +#define GPIO_POERI_POUTE06_POS (6U) +#define GPIO_POERI_POUTE06 (0x0040U) +#define GPIO_POERI_POUTE07_POS (7U) +#define GPIO_POERI_POUTE07 (0x0080U) +#define GPIO_POERI_POUTE08_POS (8U) +#define GPIO_POERI_POUTE08 (0x0100U) +#define GPIO_POERI_POUTE09_POS (9U) +#define GPIO_POERI_POUTE09 (0x0200U) +#define GPIO_POERI_POUTE10_POS (10U) +#define GPIO_POERI_POUTE10 (0x0400U) +#define GPIO_POERI_POUTE11_POS (11U) +#define GPIO_POERI_POUTE11 (0x0800U) +#define GPIO_POERI_POUTE12_POS (12U) +#define GPIO_POERI_POUTE12 (0x1000U) +#define GPIO_POERI_POUTE13_POS (13U) +#define GPIO_POERI_POUTE13 (0x2000U) + +/* Bit definition for GPIO_POSRI register */ +#define GPIO_POSRI_POS00_POS (0U) +#define GPIO_POSRI_POS00 (0x0001U) +#define GPIO_POSRI_POS01_POS (1U) +#define GPIO_POSRI_POS01 (0x0002U) +#define GPIO_POSRI_POS02_POS (2U) +#define GPIO_POSRI_POS02 (0x0004U) +#define GPIO_POSRI_POS03_POS (3U) +#define GPIO_POSRI_POS03 (0x0008U) +#define GPIO_POSRI_POS04_POS (4U) +#define GPIO_POSRI_POS04 (0x0010U) +#define GPIO_POSRI_POS05_POS (5U) +#define GPIO_POSRI_POS05 (0x0020U) +#define GPIO_POSRI_POS06_POS (6U) +#define GPIO_POSRI_POS06 (0x0040U) +#define GPIO_POSRI_POS07_POS (7U) +#define GPIO_POSRI_POS07 (0x0080U) +#define GPIO_POSRI_POS08_POS (8U) +#define GPIO_POSRI_POS08 (0x0100U) +#define GPIO_POSRI_POS09_POS (9U) +#define GPIO_POSRI_POS09 (0x0200U) +#define GPIO_POSRI_POS10_POS (10U) +#define GPIO_POSRI_POS10 (0x0400U) +#define GPIO_POSRI_POS11_POS (11U) +#define GPIO_POSRI_POS11 (0x0800U) +#define GPIO_POSRI_POS12_POS (12U) +#define GPIO_POSRI_POS12 (0x1000U) +#define GPIO_POSRI_POS13_POS (13U) +#define GPIO_POSRI_POS13 (0x2000U) + +/* Bit definition for GPIO_PORRI register */ +#define GPIO_PORRI_POR00_POS (0U) +#define GPIO_PORRI_POR00 (0x0001U) +#define GPIO_PORRI_POR01_POS (1U) +#define GPIO_PORRI_POR01 (0x0002U) +#define GPIO_PORRI_POR02_POS (2U) +#define GPIO_PORRI_POR02 (0x0004U) +#define GPIO_PORRI_POR03_POS (3U) +#define GPIO_PORRI_POR03 (0x0008U) +#define GPIO_PORRI_POR04_POS (4U) +#define GPIO_PORRI_POR04 (0x0010U) +#define GPIO_PORRI_POR05_POS (5U) +#define GPIO_PORRI_POR05 (0x0020U) +#define GPIO_PORRI_POR06_POS (6U) +#define GPIO_PORRI_POR06 (0x0040U) +#define GPIO_PORRI_POR07_POS (7U) +#define GPIO_PORRI_POR07 (0x0080U) +#define GPIO_PORRI_POR08_POS (8U) +#define GPIO_PORRI_POR08 (0x0100U) +#define GPIO_PORRI_POR09_POS (9U) +#define GPIO_PORRI_POR09 (0x0200U) +#define GPIO_PORRI_POR10_POS (10U) +#define GPIO_PORRI_POR10 (0x0400U) +#define GPIO_PORRI_POR11_POS (11U) +#define GPIO_PORRI_POR11 (0x0800U) +#define GPIO_PORRI_POR12_POS (12U) +#define GPIO_PORRI_POR12 (0x1000U) +#define GPIO_PORRI_POR13_POS (13U) +#define GPIO_PORRI_POR13 (0x2000U) + +/* Bit definition for GPIO_POTRI register */ +#define GPIO_POTRI_POT00_POS (0U) +#define GPIO_POTRI_POT00 (0x0001U) +#define GPIO_POTRI_POT01_POS (1U) +#define GPIO_POTRI_POT01 (0x0002U) +#define GPIO_POTRI_POT02_POS (2U) +#define GPIO_POTRI_POT02 (0x0004U) +#define GPIO_POTRI_POT03_POS (3U) +#define GPIO_POTRI_POT03 (0x0008U) +#define GPIO_POTRI_POT04_POS (4U) +#define GPIO_POTRI_POT04 (0x0010U) +#define GPIO_POTRI_POT05_POS (5U) +#define GPIO_POTRI_POT05 (0x0020U) +#define GPIO_POTRI_POT06_POS (6U) +#define GPIO_POTRI_POT06 (0x0040U) +#define GPIO_POTRI_POT07_POS (7U) +#define GPIO_POTRI_POT07 (0x0080U) +#define GPIO_POTRI_POT08_POS (8U) +#define GPIO_POTRI_POT08 (0x0100U) +#define GPIO_POTRI_POT09_POS (9U) +#define GPIO_POTRI_POT09 (0x0200U) +#define GPIO_POTRI_POT10_POS (10U) +#define GPIO_POTRI_POT10 (0x0400U) +#define GPIO_POTRI_POT11_POS (11U) +#define GPIO_POTRI_POT11 (0x0800U) +#define GPIO_POTRI_POT12_POS (12U) +#define GPIO_POTRI_POT12 (0x1000U) +#define GPIO_POTRI_POT13_POS (13U) +#define GPIO_POTRI_POT13 (0x2000U) + +/* Bit definition for GPIO_PSPCR register */ +#define GPIO_PSPCR_SPFE (0x001FU) + +/* Bit definition for GPIO_PCCR register */ +#define GPIO_PCCR_BFSEL_POS (0U) +#define GPIO_PCCR_BFSEL (0x003FU) +#define GPIO_PCCR_RDWT_POS (12U) +#define GPIO_PCCR_RDWT (0x7000U) + +/* Bit definition for GPIO_PINAER register */ +#define GPIO_PINAER_PINAE (0x01FFU) + +/* Bit definition for GPIO_PWPR register */ +#define GPIO_PWPR_WE_POS (0U) +#define GPIO_PWPR_WE (0x0001U) +#define GPIO_PWPR_WP_POS (8U) +#define GPIO_PWPR_WP (0xFF00U) + +/* Bit definition for GPIO_PCR register */ +#define GPIO_PCR_POUT_POS (0U) +#define GPIO_PCR_POUT (0x0001U) +#define GPIO_PCR_POUTE_POS (1U) +#define GPIO_PCR_POUTE (0x0002U) +#define GPIO_PCR_NOD_POS (2U) +#define GPIO_PCR_NOD (0x0004U) +#define GPIO_PCR_DRV_POS (4U) +#define GPIO_PCR_DRV (0x0030U) +#define GPIO_PCR_DRV_0 (0x0010U) +#define GPIO_PCR_DRV_1 (0x0020U) +#define GPIO_PCR_PUU_POS (6U) +#define GPIO_PCR_PUU (0x0040U) +#define GPIO_PCR_PIN_POS (8U) +#define GPIO_PCR_PIN (0x0100U) +#define GPIO_PCR_INVE_POS (9U) +#define GPIO_PCR_INVE (0x0200U) +#define GPIO_PCR_CINSEL_POS (10U) +#define GPIO_PCR_CINSEL (0x0400U) +#define GPIO_PCR_INTE_POS (12U) +#define GPIO_PCR_INTE (0x1000U) +#define GPIO_PCR_LTE_POS (14U) +#define GPIO_PCR_LTE (0x4000U) +#define GPIO_PCR_DDIS_POS (15U) +#define GPIO_PCR_DDIS (0x8000U) + +/* Bit definition for GPIO_PFSR register */ +#define GPIO_PFSR_FSEL_POS (0U) +#define GPIO_PFSR_FSEL (0x003FU) +#define GPIO_PFSR_BFE_POS (8U) +#define GPIO_PFSR_BFE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral HASH +*******************************************************************************/ +/* Bit definition for HASH_CR register */ +#define HASH_CR_START_POS (0U) +#define HASH_CR_START (0x00000001UL) +#define HASH_CR_FST_GRP_POS (1U) +#define HASH_CR_FST_GRP (0x00000002UL) +#define HASH_CR_KMSG_END_POS (2U) +#define HASH_CR_KMSG_END (0x00000004UL) +#define HASH_CR_MODE_POS (4U) +#define HASH_CR_MODE (0x00000030UL) +#define HASH_CR_MODE_0 (0x00000010UL) +#define HASH_CR_MODE_1 (0x00000020UL) +#define HASH_CR_LKEY_POS (6U) +#define HASH_CR_LKEY (0x00000040UL) +#define HASH_CR_BUSY_POS (8U) +#define HASH_CR_BUSY (0x00000100UL) +#define HASH_CR_CYC_END_POS (9U) +#define HASH_CR_CYC_END (0x00000200UL) +#define HASH_CR_HMAC_END_POS (10U) +#define HASH_CR_HMAC_END (0x00000400UL) +#define HASH_CR_HCIE_POS (14U) +#define HASH_CR_HCIE (0x00004000UL) +#define HASH_CR_HEIE_POS (15U) +#define HASH_CR_HEIE (0x00008000UL) + +/* Bit definition for HASH_HR7 register */ +#define HASH_HR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR6 register */ +#define HASH_HR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR5 register */ +#define HASH_HR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR4 register */ +#define HASH_HR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR3 register */ +#define HASH_HR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR2 register */ +#define HASH_HR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR1 register */ +#define HASH_HR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_HR0 register */ +#define HASH_HR0 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR15 register */ +#define HASH_DR15 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR14 register */ +#define HASH_DR14 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR13 register */ +#define HASH_DR13 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR12 register */ +#define HASH_DR12 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR11 register */ +#define HASH_DR11 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR10 register */ +#define HASH_DR10 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR9 register */ +#define HASH_DR9 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR8 register */ +#define HASH_DR8 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR7 register */ +#define HASH_DR7 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR6 register */ +#define HASH_DR6 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR5 register */ +#define HASH_DR5 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR4 register */ +#define HASH_DR4 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR3 register */ +#define HASH_DR3 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR2 register */ +#define HASH_DR2 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR1 register */ +#define HASH_DR1 (0xFFFFFFFFUL) + +/* Bit definition for HASH_DR0 register */ +#define HASH_DR0 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral HRPWM +*******************************************************************************/ +/* Bit definition for HRPWM_CR register */ +#define HRPWM_CR_NSEL_POS (0U) +#define HRPWM_CR_NSEL (0x000000FFUL) +#define HRPWM_CR_PSEL_POS (8U) +#define HRPWM_CR_PSEL (0x0000FF00UL) +#define HRPWM_CR_NE_POS (29U) +#define HRPWM_CR_NE (0x20000000UL) +#define HRPWM_CR_PE_POS (30U) +#define HRPWM_CR_PE (0x40000000UL) +#define HRPWM_CR_EN_POS (31U) +#define HRPWM_CR_EN (0x80000000UL) + +/* Bit definition for HRPWM_CALCR register */ +#define HRPWM_CALCR_CALCODE_POS (0U) +#define HRPWM_CALCR_CALCODE (0x000000FFUL) +#define HRPWM_CALCR_ENDF_POS (12U) +#define HRPWM_CALCR_ENDF (0x00001000UL) +#define HRPWM_CALCR_CALEN_POS (15U) +#define HRPWM_CALCR_CALEN (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral I2C +*******************************************************************************/ +/* Bit definition for I2C_CR1 register */ +#define I2C_CR1_PE_POS (0U) +#define I2C_CR1_PE (0x00000001UL) +#define I2C_CR1_SMBUS_POS (1U) +#define I2C_CR1_SMBUS (0x00000002UL) +#define I2C_CR1_SMBALRTEN_POS (2U) +#define I2C_CR1_SMBALRTEN (0x00000004UL) +#define I2C_CR1_SMBDEFAULTEN_POS (3U) +#define I2C_CR1_SMBDEFAULTEN (0x00000008UL) +#define I2C_CR1_SMBHOSTEN_POS (4U) +#define I2C_CR1_SMBHOSTEN (0x00000010UL) +#define I2C_CR1_ENGC_POS (6U) +#define I2C_CR1_ENGC (0x00000040UL) +#define I2C_CR1_RESTART_POS (7U) +#define I2C_CR1_RESTART (0x00000080UL) +#define I2C_CR1_START_POS (8U) +#define I2C_CR1_START (0x00000100UL) +#define I2C_CR1_STOP_POS (9U) +#define I2C_CR1_STOP (0x00000200UL) +#define I2C_CR1_ACK_POS (10U) +#define I2C_CR1_ACK (0x00000400UL) +#define I2C_CR1_SWRST_POS (15U) +#define I2C_CR1_SWRST (0x00008000UL) + +/* Bit definition for I2C_CR2 register */ +#define I2C_CR2_STARTIE_POS (0U) +#define I2C_CR2_STARTIE (0x00000001UL) +#define I2C_CR2_SLADDR0IE_POS (1U) +#define I2C_CR2_SLADDR0IE (0x00000002UL) +#define I2C_CR2_SLADDR1IE_POS (2U) +#define I2C_CR2_SLADDR1IE (0x00000004UL) +#define I2C_CR2_TENDIE_POS (3U) +#define I2C_CR2_TENDIE (0x00000008UL) +#define I2C_CR2_STOPIE_POS (4U) +#define I2C_CR2_STOPIE (0x00000010UL) +#define I2C_CR2_RFULLIE_POS (6U) +#define I2C_CR2_RFULLIE (0x00000040UL) +#define I2C_CR2_TEMPTYIE_POS (7U) +#define I2C_CR2_TEMPTYIE (0x00000080UL) +#define I2C_CR2_ARLOIE_POS (9U) +#define I2C_CR2_ARLOIE (0x00000200UL) +#define I2C_CR2_NACKIE_POS (12U) +#define I2C_CR2_NACKIE (0x00001000UL) +#define I2C_CR2_TMOUTIE_POS (14U) +#define I2C_CR2_TMOUTIE (0x00004000UL) +#define I2C_CR2_GENCALLIE_POS (20U) +#define I2C_CR2_GENCALLIE (0x00100000UL) +#define I2C_CR2_SMBDEFAULTIE_POS (21U) +#define I2C_CR2_SMBDEFAULTIE (0x00200000UL) +#define I2C_CR2_SMHOSTIE_POS (22U) +#define I2C_CR2_SMHOSTIE (0x00400000UL) +#define I2C_CR2_SMBALRTIE_POS (23U) +#define I2C_CR2_SMBALRTIE (0x00800000UL) + +/* Bit definition for I2C_CR3 register */ +#define I2C_CR3_TMOUTEN_POS (0U) +#define I2C_CR3_TMOUTEN (0x00000001UL) +#define I2C_CR3_LTMOUT_POS (1U) +#define I2C_CR3_LTMOUT (0x00000002UL) +#define I2C_CR3_HTMOUT_POS (2U) +#define I2C_CR3_HTMOUT (0x00000004UL) +#define I2C_CR3_FACKEN_POS (7U) +#define I2C_CR3_FACKEN (0x00000080UL) + +/* Bit definition for I2C_SLR0 register */ +#define I2C_SLR0_SLADDR0_POS (0U) +#define I2C_SLR0_SLADDR0 (0x000003FFUL) +#define I2C_SLR0_SLADDR0EN_POS (12U) +#define I2C_SLR0_SLADDR0EN (0x00001000UL) +#define I2C_SLR0_ADDRMOD0_POS (15U) +#define I2C_SLR0_ADDRMOD0 (0x00008000UL) + +/* Bit definition for I2C_SLR1 register */ +#define I2C_SLR1_SLADDR1_POS (0U) +#define I2C_SLR1_SLADDR1 (0x000003FFUL) +#define I2C_SLR1_SLADDR1EN_POS (12U) +#define I2C_SLR1_SLADDR1EN (0x00001000UL) +#define I2C_SLR1_ADDRMOD1_POS (15U) +#define I2C_SLR1_ADDRMOD1 (0x00008000UL) + +/* Bit definition for I2C_SLTR register */ +#define I2C_SLTR_TOUTLOW_POS (0U) +#define I2C_SLTR_TOUTLOW (0x0000FFFFUL) +#define I2C_SLTR_TOUTHIGH_POS (16U) +#define I2C_SLTR_TOUTHIGH (0xFFFF0000UL) + +/* Bit definition for I2C_SR register */ +#define I2C_SR_STARTF_POS (0U) +#define I2C_SR_STARTF (0x00000001UL) +#define I2C_SR_SLADDR0F_POS (1U) +#define I2C_SR_SLADDR0F (0x00000002UL) +#define I2C_SR_SLADDR1F_POS (2U) +#define I2C_SR_SLADDR1F (0x00000004UL) +#define I2C_SR_TENDF_POS (3U) +#define I2C_SR_TENDF (0x00000008UL) +#define I2C_SR_STOPF_POS (4U) +#define I2C_SR_STOPF (0x00000010UL) +#define I2C_SR_RFULLF_POS (6U) +#define I2C_SR_RFULLF (0x00000040UL) +#define I2C_SR_TEMPTYF_POS (7U) +#define I2C_SR_TEMPTYF (0x00000080UL) +#define I2C_SR_ARLOF_POS (9U) +#define I2C_SR_ARLOF (0x00000200UL) +#define I2C_SR_ACKRF_POS (10U) +#define I2C_SR_ACKRF (0x00000400UL) +#define I2C_SR_NACKF_POS (12U) +#define I2C_SR_NACKF (0x00001000UL) +#define I2C_SR_TMOUTF_POS (14U) +#define I2C_SR_TMOUTF (0x00004000UL) +#define I2C_SR_MSL_POS (16U) +#define I2C_SR_MSL (0x00010000UL) +#define I2C_SR_BUSY_POS (17U) +#define I2C_SR_BUSY (0x00020000UL) +#define I2C_SR_TRA_POS (18U) +#define I2C_SR_TRA (0x00040000UL) +#define I2C_SR_GENCALLF_POS (20U) +#define I2C_SR_GENCALLF (0x00100000UL) +#define I2C_SR_SMBDEFAULTF_POS (21U) +#define I2C_SR_SMBDEFAULTF (0x00200000UL) +#define I2C_SR_SMBHOSTF_POS (22U) +#define I2C_SR_SMBHOSTF (0x00400000UL) +#define I2C_SR_SMBALRTF_POS (23U) +#define I2C_SR_SMBALRTF (0x00800000UL) + +/* Bit definition for I2C_CLR register */ +#define I2C_CLR_STARTFCLR_POS (0U) +#define I2C_CLR_STARTFCLR (0x00000001UL) +#define I2C_CLR_SLADDR0FCLR_POS (1U) +#define I2C_CLR_SLADDR0FCLR (0x00000002UL) +#define I2C_CLR_SLADDR1FCLR_POS (2U) +#define I2C_CLR_SLADDR1FCLR (0x00000004UL) +#define I2C_CLR_TENDFCLR_POS (3U) +#define I2C_CLR_TENDFCLR (0x00000008UL) +#define I2C_CLR_STOPFCLR_POS (4U) +#define I2C_CLR_STOPFCLR (0x00000010UL) +#define I2C_CLR_RFULLFCLR_POS (6U) +#define I2C_CLR_RFULLFCLR (0x00000040UL) +#define I2C_CLR_TEMPTYFCLR_POS (7U) +#define I2C_CLR_TEMPTYFCLR (0x00000080UL) +#define I2C_CLR_ARLOFCLR_POS (9U) +#define I2C_CLR_ARLOFCLR (0x00000200UL) +#define I2C_CLR_NACKFCLR_POS (12U) +#define I2C_CLR_NACKFCLR (0x00001000UL) +#define I2C_CLR_TMOUTFCLR_POS (14U) +#define I2C_CLR_TMOUTFCLR (0x00004000UL) +#define I2C_CLR_GENCALLFCLR_POS (20U) +#define I2C_CLR_GENCALLFCLR (0x00100000UL) +#define I2C_CLR_SMBDEFAULTFCLR_POS (21U) +#define I2C_CLR_SMBDEFAULTFCLR (0x00200000UL) +#define I2C_CLR_SMBHOSTFCLR_POS (22U) +#define I2C_CLR_SMBHOSTFCLR (0x00400000UL) +#define I2C_CLR_SMBALRTFCLR_POS (23U) +#define I2C_CLR_SMBALRTFCLR (0x00800000UL) + +/* Bit definition for I2C_DTR register */ +#define I2C_DTR_DT (0xFFU) + +/* Bit definition for I2C_DRR register */ +#define I2C_DRR_DR (0xFFU) + +/* Bit definition for I2C_CCR register */ +#define I2C_CCR_SLOWW_POS (0U) +#define I2C_CCR_SLOWW (0x0000001FUL) +#define I2C_CCR_SHIGHW_POS (8U) +#define I2C_CCR_SHIGHW (0x00001F00UL) +#define I2C_CCR_FREQ_POS (16U) +#define I2C_CCR_FREQ (0x00070000UL) + +/* Bit definition for I2C_FLTR register */ +#define I2C_FLTR_DNF_POS (0U) +#define I2C_FLTR_DNF (0x00000003UL) +#define I2C_FLTR_DNFEN_POS (4U) +#define I2C_FLTR_DNFEN (0x00000010UL) +#define I2C_FLTR_ANFEN_POS (5U) +#define I2C_FLTR_ANFEN (0x00000020UL) + +/******************************************************************************* + Bit definition for Peripheral I2S +*******************************************************************************/ +/* Bit definition for I2S_CTRL register */ +#define I2S_CTRL_TXE_POS (0U) +#define I2S_CTRL_TXE (0x00000001UL) +#define I2S_CTRL_TXIE_POS (1U) +#define I2S_CTRL_TXIE (0x00000002UL) +#define I2S_CTRL_RXE_POS (2U) +#define I2S_CTRL_RXE (0x00000004UL) +#define I2S_CTRL_RXIE_POS (3U) +#define I2S_CTRL_RXIE (0x00000008UL) +#define I2S_CTRL_EIE_POS (4U) +#define I2S_CTRL_EIE (0x00000010UL) +#define I2S_CTRL_WMS_POS (5U) +#define I2S_CTRL_WMS (0x00000020UL) +#define I2S_CTRL_ODD_POS (6U) +#define I2S_CTRL_ODD (0x00000040UL) +#define I2S_CTRL_MCKOE_POS (7U) +#define I2S_CTRL_MCKOE (0x00000080UL) +#define I2S_CTRL_TXBIRQWL_POS (8U) +#define I2S_CTRL_TXBIRQWL (0x00000700UL) +#define I2S_CTRL_TXBIRQWL_0 (0x00000100UL) +#define I2S_CTRL_TXBIRQWL_1 (0x00000200UL) +#define I2S_CTRL_TXBIRQWL_2 (0x00000400UL) +#define I2S_CTRL_RXBIRQWL_POS (12U) +#define I2S_CTRL_RXBIRQWL (0x00007000UL) +#define I2S_CTRL_RXBIRQWL_0 (0x00001000UL) +#define I2S_CTRL_RXBIRQWL_1 (0x00002000UL) +#define I2S_CTRL_RXBIRQWL_2 (0x00004000UL) +#define I2S_CTRL_FIFOR_POS (16U) +#define I2S_CTRL_FIFOR (0x00010000UL) +#define I2S_CTRL_CODECRC_POS (17U) +#define I2S_CTRL_CODECRC (0x00020000UL) +#define I2S_CTRL_I2SPLLSEL_POS (18U) +#define I2S_CTRL_I2SPLLSEL (0x00040000UL) +#define I2S_CTRL_SDOE_POS (19U) +#define I2S_CTRL_SDOE (0x00080000UL) +#define I2S_CTRL_LRCKOE_POS (20U) +#define I2S_CTRL_LRCKOE (0x00100000UL) +#define I2S_CTRL_CKOE_POS (21U) +#define I2S_CTRL_CKOE (0x00200000UL) +#define I2S_CTRL_DUPLEX_POS (22U) +#define I2S_CTRL_DUPLEX (0x00400000UL) +#define I2S_CTRL_CLKSEL_POS (23U) +#define I2S_CTRL_CLKSEL (0x00800000UL) +#define I2S_CTRL_SRST_POS (24U) +#define I2S_CTRL_SRST (0x01000000UL) + +/* Bit definition for I2S_SR register */ +#define I2S_SR_TXBA_POS (0U) +#define I2S_SR_TXBA (0x00000001UL) +#define I2S_SR_RXBA_POS (1U) +#define I2S_SR_RXBA (0x00000002UL) +#define I2S_SR_TXBE_POS (2U) +#define I2S_SR_TXBE (0x00000004UL) +#define I2S_SR_TXBF_POS (3U) +#define I2S_SR_TXBF (0x00000008UL) +#define I2S_SR_RXBE_POS (4U) +#define I2S_SR_RXBE (0x00000010UL) +#define I2S_SR_RXBF_POS (5U) +#define I2S_SR_RXBF (0x00000020UL) + +/* Bit definition for I2S_ER register */ +#define I2S_ER_TXERR_POS (0U) +#define I2S_ER_TXERR (0x00000001UL) +#define I2S_ER_RXERR_POS (1U) +#define I2S_ER_RXERR (0x00000002UL) + +/* Bit definition for I2S_CFGR register */ +#define I2S_CFGR_I2SSTD_POS (0U) +#define I2S_CFGR_I2SSTD (0x00000003UL) +#define I2S_CFGR_I2SSTD_0 (0x00000001UL) +#define I2S_CFGR_I2SSTD_1 (0x00000002UL) +#define I2S_CFGR_DATLEN_POS (2U) +#define I2S_CFGR_DATLEN (0x0000000CUL) +#define I2S_CFGR_DATLEN_0 (0x00000004UL) +#define I2S_CFGR_DATLEN_1 (0x00000008UL) +#define I2S_CFGR_CHLEN_POS (4U) +#define I2S_CFGR_CHLEN (0x00000010UL) +#define I2S_CFGR_PCMSYNC_POS (5U) +#define I2S_CFGR_PCMSYNC (0x00000020UL) + +/* Bit definition for I2S_TXBUF register */ +#define I2S_TXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_RXBUF register */ +#define I2S_RXBUF (0xFFFFFFFFUL) + +/* Bit definition for I2S_PR register */ +#define I2S_PR_I2SDIV (0x000000FFUL) + +/******************************************************************************* + Bit definition for Peripheral ICG +*******************************************************************************/ +/* Bit definition for ICG_ICG0 register */ +#define ICG_ICG0_SWDTAUTS_POS (0U) +#define ICG_ICG0_SWDTAUTS (0x00000001UL) +#define ICG_ICG0_SWDTITS_POS (1U) +#define ICG_ICG0_SWDTITS (0x00000002UL) +#define ICG_ICG0_SWDTPERI_POS (2U) +#define ICG_ICG0_SWDTPERI (0x0000000CUL) +#define ICG_ICG0_SWDTPERI_0 (0x00000004UL) +#define ICG_ICG0_SWDTPERI_1 (0x00000008UL) +#define ICG_ICG0_SWDTCKS_POS (4U) +#define ICG_ICG0_SWDTCKS (0x000000F0UL) +#define ICG_ICG0_SWDTCKS_0 (0x00000010UL) +#define ICG_ICG0_SWDTCKS_1 (0x00000020UL) +#define ICG_ICG0_SWDTCKS_2 (0x00000040UL) +#define ICG_ICG0_SWDTCKS_3 (0x00000080UL) +#define ICG_ICG0_SWDTWDPT_POS (8U) +#define ICG_ICG0_SWDTWDPT (0x00000F00UL) +#define ICG_ICG0_SWDTWDPT_0 (0x00000100UL) +#define ICG_ICG0_SWDTWDPT_1 (0x00000200UL) +#define ICG_ICG0_SWDTWDPT_2 (0x00000400UL) +#define ICG_ICG0_SWDTWDPT_3 (0x00000800UL) +#define ICG_ICG0_SWDTSLPOFF_POS (12U) +#define ICG_ICG0_SWDTSLPOFF (0x00001000UL) +#define ICG_ICG0_WDTAUTS_POS (16U) +#define ICG_ICG0_WDTAUTS (0x00010000UL) +#define ICG_ICG0_WDTITS_POS (17U) +#define ICG_ICG0_WDTITS (0x00020000UL) +#define ICG_ICG0_WDTPERI_POS (18U) +#define ICG_ICG0_WDTPERI (0x000C0000UL) +#define ICG_ICG0_WDTPERI_0 (0x00040000UL) +#define ICG_ICG0_WDTPERI_1 (0x00080000UL) +#define ICG_ICG0_WDTCKS_POS (20U) +#define ICG_ICG0_WDTCKS (0x00F00000UL) +#define ICG_ICG0_WDTCKS_0 (0x00100000UL) +#define ICG_ICG0_WDTCKS_1 (0x00200000UL) +#define ICG_ICG0_WDTCKS_2 (0x00400000UL) +#define ICG_ICG0_WDTCKS_3 (0x00800000UL) +#define ICG_ICG0_WDTWDPT_POS (24U) +#define ICG_ICG0_WDTWDPT (0x0F000000UL) +#define ICG_ICG0_WDTWDPT_0 (0x01000000UL) +#define ICG_ICG0_WDTWDPT_1 (0x02000000UL) +#define ICG_ICG0_WDTWDPT_2 (0x04000000UL) +#define ICG_ICG0_WDTWDPT_3 (0x08000000UL) +#define ICG_ICG0_WDTSLPOFF_POS (28U) +#define ICG_ICG0_WDTSLPOFF (0x10000000UL) + +/* Bit definition for ICG_ICG1 register */ +#define ICG_ICG1_HRCFREQSEL_POS (0U) +#define ICG_ICG1_HRCFREQSEL (0x00000001UL) +#define ICG_ICG1_HRCSTOP_POS (8U) +#define ICG_ICG1_HRCSTOP (0x00000100UL) +#define ICG_ICG1_BOR_LEV_POS (16U) +#define ICG_ICG1_BOR_LEV (0x00030000UL) +#define ICG_ICG1_BOR_LEV_0 (0x00010000UL) +#define ICG_ICG1_BOR_LEV_1 (0x00020000UL) +#define ICG_ICG1_BORDIS_POS (18U) +#define ICG_ICG1_BORDIS (0x00040000UL) + +/* Bit definition for ICG_ICG2 register */ +#define ICG_ICG2_BGO1M (0x00FFFFFFUL) + +/* Bit definition for ICG_ICG3 register */ +#define ICG_ICG3_DBUSPRT (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral INTC +*******************************************************************************/ +/* Bit definition for INTC_NOCCR register */ +#define INTC_NOCCR_NOCSEL_POS (12U) +#define INTC_NOCCR_NOCSEL (0x00003000UL) + +/* Bit definition for INTC_NMIENR register */ +#define INTC_NMIENR_SWDTENR_POS (1U) +#define INTC_NMIENR_SWDTENR (0x00000002UL) +#define INTC_NMIENR_PVD1ENR_POS (2U) +#define INTC_NMIENR_PVD1ENR (0x00000004UL) +#define INTC_NMIENR_PVD2ENR_POS (3U) +#define INTC_NMIENR_PVD2ENR (0x00000008UL) +#define INTC_NMIENR_XTAL32STPENR_POS (4U) +#define INTC_NMIENR_XTAL32STPENR (0x00000010UL) +#define INTC_NMIENR_XTALSTPENR_POS (5U) +#define INTC_NMIENR_XTALSTPENR (0x00000020UL) +#define INTC_NMIENR_REPENR_POS (8U) +#define INTC_NMIENR_REPENR (0x00000100UL) +#define INTC_NMIENR_RECCENR_POS (9U) +#define INTC_NMIENR_RECCENR (0x00000200UL) +#define INTC_NMIENR_BUSMENR_POS (10U) +#define INTC_NMIENR_BUSMENR (0x00000400UL) +#define INTC_NMIENR_WDTENR_POS (11U) +#define INTC_NMIENR_WDTENR (0x00000800UL) + +/* Bit definition for INTC_NMIFR register */ +#define INTC_NMIFR_SWDTFR_POS (1U) +#define INTC_NMIFR_SWDTFR (0x00000002UL) +#define INTC_NMIFR_PVD1FR_POS (2U) +#define INTC_NMIFR_PVD1FR (0x00000004UL) +#define INTC_NMIFR_PVD2FR_POS (3U) +#define INTC_NMIFR_PVD2FR (0x00000008UL) +#define INTC_NMIFR_XTAL32STPFR_POS (4U) +#define INTC_NMIFR_XTAL32STPFR (0x00000010UL) +#define INTC_NMIFR_XTALSTPFR_POS (5U) +#define INTC_NMIFR_XTALSTPFR (0x00000020UL) +#define INTC_NMIFR_REPFR_POS (8U) +#define INTC_NMIFR_REPFR (0x00000100UL) +#define INTC_NMIFR_RECCFR_POS (9U) +#define INTC_NMIFR_RECCFR (0x00000200UL) +#define INTC_NMIFR_BUSMFR_POS (10U) +#define INTC_NMIFR_BUSMFR (0x00000400UL) +#define INTC_NMIFR_WDTFR_POS (11U) +#define INTC_NMIFR_WDTFR (0x00000800UL) + +/* Bit definition for INTC_NMICFR register */ +#define INTC_NMICFR_SWDTCFR_POS (1U) +#define INTC_NMICFR_SWDTCFR (0x00000002UL) +#define INTC_NMICFR_PVD1CFR_POS (2U) +#define INTC_NMICFR_PVD1CFR (0x00000004UL) +#define INTC_NMICFR_PVD2CFR_POS (3U) +#define INTC_NMICFR_PVD2CFR (0x00000008UL) +#define INTC_NMICFR_XTAL32STPCFR_POS (4U) +#define INTC_NMICFR_XTAL32STPCFR (0x00000010UL) +#define INTC_NMICFR_XTALSTPCFR_POS (5U) +#define INTC_NMICFR_XTALSTPCFR (0x00000020UL) +#define INTC_NMICFR_REPCFR_POS (8U) +#define INTC_NMICFR_REPCFR (0x00000100UL) +#define INTC_NMICFR_RECCCFR_POS (9U) +#define INTC_NMICFR_RECCCFR (0x00000200UL) +#define INTC_NMICFR_BUSMCFR_POS (10U) +#define INTC_NMICFR_BUSMCFR (0x00000400UL) +#define INTC_NMICFR_WDTCFR_POS (11U) +#define INTC_NMICFR_WDTCFR (0x00000800UL) + +/* Bit definition for INTC_EIRQCR register */ +#define INTC_EIRQCR_EIRQTRG_POS (0U) +#define INTC_EIRQCR_EIRQTRG (0x00000003UL) +#define INTC_EIRQCR_EIRQTRG_0 (0x00000001UL) +#define INTC_EIRQCR_EIRQTRG_1 (0x00000002UL) +#define INTC_EIRQCR_EISMPCLK_POS (4U) +#define INTC_EIRQCR_EISMPCLK (0x00000030UL) +#define INTC_EIRQCR_EISMPCLK_0 (0x00000010UL) +#define INTC_EIRQCR_EISMPCLK_1 (0x00000020UL) +#define INTC_EIRQCR_EFEN_POS (7U) +#define INTC_EIRQCR_EFEN (0x00000080UL) +#define INTC_EIRQCR_NOCEN_POS (15U) +#define INTC_EIRQCR_NOCEN (0x00008000UL) + +/* Bit definition for INTC_WUPEN register */ +#define INTC_WUPEN_EIRQWUEN_POS (0U) +#define INTC_WUPEN_EIRQWUEN (0x0000FFFFUL) +#define INTC_WUPEN_EIRQWUEN_0 (0x00000001UL) +#define INTC_WUPEN_EIRQWUEN_1 (0x00000002UL) +#define INTC_WUPEN_EIRQWUEN_2 (0x00000004UL) +#define INTC_WUPEN_EIRQWUEN_3 (0x00000008UL) +#define INTC_WUPEN_EIRQWUEN_4 (0x00000010UL) +#define INTC_WUPEN_EIRQWUEN_5 (0x00000020UL) +#define INTC_WUPEN_EIRQWUEN_6 (0x00000040UL) +#define INTC_WUPEN_EIRQWUEN_7 (0x00000080UL) +#define INTC_WUPEN_EIRQWUEN_8 (0x00000100UL) +#define INTC_WUPEN_EIRQWUEN_9 (0x00000200UL) +#define INTC_WUPEN_EIRQWUEN_10 (0x00000400UL) +#define INTC_WUPEN_EIRQWUEN_11 (0x00000800UL) +#define INTC_WUPEN_EIRQWUEN_12 (0x00001000UL) +#define INTC_WUPEN_EIRQWUEN_13 (0x00002000UL) +#define INTC_WUPEN_EIRQWUEN_14 (0x00004000UL) +#define INTC_WUPEN_EIRQWUEN_15 (0x00008000UL) +#define INTC_WUPEN_SWDTWUEN_POS (16U) +#define INTC_WUPEN_SWDTWUEN (0x00010000UL) +#define INTC_WUPEN_PVD1WUEN_POS (17U) +#define INTC_WUPEN_PVD1WUEN (0x00020000UL) +#define INTC_WUPEN_PVD2WUEN_POS (18U) +#define INTC_WUPEN_PVD2WUEN (0x00040000UL) +#define INTC_WUPEN_CMPWUEN_POS (19U) +#define INTC_WUPEN_CMPWUEN (0x00080000UL) +#define INTC_WUPEN_WKTMWUEN_POS (20U) +#define INTC_WUPEN_WKTMWUEN (0x00100000UL) +#define INTC_WUPEN_RTCALMWUEN_POS (21U) +#define INTC_WUPEN_RTCALMWUEN (0x00200000UL) +#define INTC_WUPEN_RTCPRDWUEN_POS (22U) +#define INTC_WUPEN_RTCPRDWUEN (0x00400000UL) +#define INTC_WUPEN_TMR0GCMWUEN_POS (23U) +#define INTC_WUPEN_TMR0GCMWUEN (0x00800000UL) +#define INTC_WUPEN_TMR2GCMWUEN_POS (24U) +#define INTC_WUPEN_TMR2GCMWUEN (0x01000000UL) +#define INTC_WUPEN_TMR2OVFWUEN_POS (25U) +#define INTC_WUPEN_TMR2OVFWUEN (0x02000000UL) +#define INTC_WUPEN_RXWUEN_POS (26U) +#define INTC_WUPEN_RXWUEN (0x04000000UL) +#define INTC_WUPEN_USHWUEN_POS (27U) +#define INTC_WUPEN_USHWUEN (0x08000000UL) +#define INTC_WUPEN_USFWUEN_POS (28U) +#define INTC_WUPEN_USFWUEN (0x10000000UL) +#define INTC_WUPEN_ETHWUEN_POS (29U) +#define INTC_WUPEN_ETHWUEN (0x20000000UL) + +/* Bit definition for INTC_EIFR register */ +#define INTC_EIFR_EIFR0_POS (0U) +#define INTC_EIFR_EIFR0 (0x00000001UL) +#define INTC_EIFR_EIFR1_POS (1U) +#define INTC_EIFR_EIFR1 (0x00000002UL) +#define INTC_EIFR_EIFR2_POS (2U) +#define INTC_EIFR_EIFR2 (0x00000004UL) +#define INTC_EIFR_EIFR3_POS (3U) +#define INTC_EIFR_EIFR3 (0x00000008UL) +#define INTC_EIFR_EIFR4_POS (4U) +#define INTC_EIFR_EIFR4 (0x00000010UL) +#define INTC_EIFR_EIFR5_POS (5U) +#define INTC_EIFR_EIFR5 (0x00000020UL) +#define INTC_EIFR_EIFR6_POS (6U) +#define INTC_EIFR_EIFR6 (0x00000040UL) +#define INTC_EIFR_EIFR7_POS (7U) +#define INTC_EIFR_EIFR7 (0x00000080UL) +#define INTC_EIFR_EIFR8_POS (8U) +#define INTC_EIFR_EIFR8 (0x00000100UL) +#define INTC_EIFR_EIFR9_POS (9U) +#define INTC_EIFR_EIFR9 (0x00000200UL) +#define INTC_EIFR_EIFR10_POS (10U) +#define INTC_EIFR_EIFR10 (0x00000400UL) +#define INTC_EIFR_EIFR11_POS (11U) +#define INTC_EIFR_EIFR11 (0x00000800UL) +#define INTC_EIFR_EIFR12_POS (12U) +#define INTC_EIFR_EIFR12 (0x00001000UL) +#define INTC_EIFR_EIFR13_POS (13U) +#define INTC_EIFR_EIFR13 (0x00002000UL) +#define INTC_EIFR_EIFR14_POS (14U) +#define INTC_EIFR_EIFR14 (0x00004000UL) +#define INTC_EIFR_EIFR15_POS (15U) +#define INTC_EIFR_EIFR15 (0x00008000UL) + +/* Bit definition for INTC_EICFR register */ +#define INTC_EICFR_EICFR0_POS (0U) +#define INTC_EICFR_EICFR0 (0x00000001UL) +#define INTC_EICFR_EICFR1_POS (1U) +#define INTC_EICFR_EICFR1 (0x00000002UL) +#define INTC_EICFR_EICFR2_POS (2U) +#define INTC_EICFR_EICFR2 (0x00000004UL) +#define INTC_EICFR_EICFR3_POS (3U) +#define INTC_EICFR_EICFR3 (0x00000008UL) +#define INTC_EICFR_EICFR4_POS (4U) +#define INTC_EICFR_EICFR4 (0x00000010UL) +#define INTC_EICFR_EICFR5_POS (5U) +#define INTC_EICFR_EICFR5 (0x00000020UL) +#define INTC_EICFR_EICFR6_POS (6U) +#define INTC_EICFR_EICFR6 (0x00000040UL) +#define INTC_EICFR_EICFR7_POS (7U) +#define INTC_EICFR_EICFR7 (0x00000080UL) +#define INTC_EICFR_EICFR8_POS (8U) +#define INTC_EICFR_EICFR8 (0x00000100UL) +#define INTC_EICFR_EICFR9_POS (9U) +#define INTC_EICFR_EICFR9 (0x00000200UL) +#define INTC_EICFR_EICFR10_POS (10U) +#define INTC_EICFR_EICFR10 (0x00000400UL) +#define INTC_EICFR_EICFR11_POS (11U) +#define INTC_EICFR_EICFR11 (0x00000800UL) +#define INTC_EICFR_EICFR12_POS (12U) +#define INTC_EICFR_EICFR12 (0x00001000UL) +#define INTC_EICFR_EICFR13_POS (13U) +#define INTC_EICFR_EICFR13 (0x00002000UL) +#define INTC_EICFR_EICFR14_POS (14U) +#define INTC_EICFR_EICFR14 (0x00004000UL) +#define INTC_EICFR_EICFR15_POS (15U) +#define INTC_EICFR_EICFR15 (0x00008000UL) + +/* Bit definition for INTC_SEL0 register */ +#define INTC_SEL0_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL1 register */ +#define INTC_SEL1_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL2 register */ +#define INTC_SEL2_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL3 register */ +#define INTC_SEL3_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL4 register */ +#define INTC_SEL4_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL5 register */ +#define INTC_SEL5_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL6 register */ +#define INTC_SEL6_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL7 register */ +#define INTC_SEL7_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL8 register */ +#define INTC_SEL8_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL9 register */ +#define INTC_SEL9_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL10 register */ +#define INTC_SEL10_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL11 register */ +#define INTC_SEL11_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL12 register */ +#define INTC_SEL12_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL13 register */ +#define INTC_SEL13_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL14 register */ +#define INTC_SEL14_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL15 register */ +#define INTC_SEL15_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL16 register */ +#define INTC_SEL16_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL17 register */ +#define INTC_SEL17_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL18 register */ +#define INTC_SEL18_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL19 register */ +#define INTC_SEL19_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL20 register */ +#define INTC_SEL20_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL21 register */ +#define INTC_SEL21_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL22 register */ +#define INTC_SEL22_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL23 register */ +#define INTC_SEL23_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL24 register */ +#define INTC_SEL24_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL25 register */ +#define INTC_SEL25_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL26 register */ +#define INTC_SEL26_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL27 register */ +#define INTC_SEL27_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL28 register */ +#define INTC_SEL28_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL29 register */ +#define INTC_SEL29_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL30 register */ +#define INTC_SEL30_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL31 register */ +#define INTC_SEL31_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL32 register */ +#define INTC_SEL32_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL33 register */ +#define INTC_SEL33_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL34 register */ +#define INTC_SEL34_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL35 register */ +#define INTC_SEL35_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL36 register */ +#define INTC_SEL36_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL37 register */ +#define INTC_SEL37_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL38 register */ +#define INTC_SEL38_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL39 register */ +#define INTC_SEL39_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL40 register */ +#define INTC_SEL40_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL41 register */ +#define INTC_SEL41_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL42 register */ +#define INTC_SEL42_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL43 register */ +#define INTC_SEL43_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL44 register */ +#define INTC_SEL44_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL45 register */ +#define INTC_SEL45_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL46 register */ +#define INTC_SEL46_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL47 register */ +#define INTC_SEL47_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL48 register */ +#define INTC_SEL48_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL49 register */ +#define INTC_SEL49_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL50 register */ +#define INTC_SEL50_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL51 register */ +#define INTC_SEL51_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL52 register */ +#define INTC_SEL52_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL53 register */ +#define INTC_SEL53_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL54 register */ +#define INTC_SEL54_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL55 register */ +#define INTC_SEL55_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL56 register */ +#define INTC_SEL56_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL57 register */ +#define INTC_SEL57_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL58 register */ +#define INTC_SEL58_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL59 register */ +#define INTC_SEL59_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL60 register */ +#define INTC_SEL60_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL61 register */ +#define INTC_SEL61_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL62 register */ +#define INTC_SEL62_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL63 register */ +#define INTC_SEL63_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL64 register */ +#define INTC_SEL64_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL65 register */ +#define INTC_SEL65_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL66 register */ +#define INTC_SEL66_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL67 register */ +#define INTC_SEL67_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL68 register */ +#define INTC_SEL68_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL69 register */ +#define INTC_SEL69_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL70 register */ +#define INTC_SEL70_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL71 register */ +#define INTC_SEL71_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL72 register */ +#define INTC_SEL72_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL73 register */ +#define INTC_SEL73_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL74 register */ +#define INTC_SEL74_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL75 register */ +#define INTC_SEL75_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL76 register */ +#define INTC_SEL76_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL77 register */ +#define INTC_SEL77_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL78 register */ +#define INTC_SEL78_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL79 register */ +#define INTC_SEL79_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL80 register */ +#define INTC_SEL80_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL81 register */ +#define INTC_SEL81_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL82 register */ +#define INTC_SEL82_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL83 register */ +#define INTC_SEL83_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL84 register */ +#define INTC_SEL84_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL85 register */ +#define INTC_SEL85_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL86 register */ +#define INTC_SEL86_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL87 register */ +#define INTC_SEL87_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL88 register */ +#define INTC_SEL88_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL89 register */ +#define INTC_SEL89_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL90 register */ +#define INTC_SEL90_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL91 register */ +#define INTC_SEL91_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL92 register */ +#define INTC_SEL92_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL93 register */ +#define INTC_SEL93_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL94 register */ +#define INTC_SEL94_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL95 register */ +#define INTC_SEL95_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL96 register */ +#define INTC_SEL96_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL97 register */ +#define INTC_SEL97_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL98 register */ +#define INTC_SEL98_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL99 register */ +#define INTC_SEL99_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL100 register */ +#define INTC_SEL100_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL101 register */ +#define INTC_SEL101_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL102 register */ +#define INTC_SEL102_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL103 register */ +#define INTC_SEL103_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL104 register */ +#define INTC_SEL104_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL105 register */ +#define INTC_SEL105_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL106 register */ +#define INTC_SEL106_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL107 register */ +#define INTC_SEL107_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL108 register */ +#define INTC_SEL108_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL109 register */ +#define INTC_SEL109_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL110 register */ +#define INTC_SEL110_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL111 register */ +#define INTC_SEL111_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL112 register */ +#define INTC_SEL112_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL113 register */ +#define INTC_SEL113_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL114 register */ +#define INTC_SEL114_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL115 register */ +#define INTC_SEL115_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL116 register */ +#define INTC_SEL116_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL117 register */ +#define INTC_SEL117_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL118 register */ +#define INTC_SEL118_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL119 register */ +#define INTC_SEL119_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL120 register */ +#define INTC_SEL120_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL121 register */ +#define INTC_SEL121_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL122 register */ +#define INTC_SEL122_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL123 register */ +#define INTC_SEL123_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL124 register */ +#define INTC_SEL124_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL125 register */ +#define INTC_SEL125_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL126 register */ +#define INTC_SEL126_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_SEL127 register */ +#define INTC_SEL127_INTSEL (0x000001FFUL) + +/* Bit definition for INTC_VSSEL register */ +#define INTC_VSSEL_VSEL0_POS (0U) +#define INTC_VSSEL_VSEL0 (0x00000001UL) +#define INTC_VSSEL_VSEL1_POS (1U) +#define INTC_VSSEL_VSEL1 (0x00000002UL) +#define INTC_VSSEL_VSEL2_POS (2U) +#define INTC_VSSEL_VSEL2 (0x00000004UL) +#define INTC_VSSEL_VSEL3_POS (3U) +#define INTC_VSSEL_VSEL3 (0x00000008UL) +#define INTC_VSSEL_VSEL4_POS (4U) +#define INTC_VSSEL_VSEL4 (0x00000010UL) +#define INTC_VSSEL_VSEL5_POS (5U) +#define INTC_VSSEL_VSEL5 (0x00000020UL) +#define INTC_VSSEL_VSEL6_POS (6U) +#define INTC_VSSEL_VSEL6 (0x00000040UL) +#define INTC_VSSEL_VSEL7_POS (7U) +#define INTC_VSSEL_VSEL7 (0x00000080UL) +#define INTC_VSSEL_VSEL8_POS (8U) +#define INTC_VSSEL_VSEL8 (0x00000100UL) +#define INTC_VSSEL_VSEL9_POS (9U) +#define INTC_VSSEL_VSEL9 (0x00000200UL) +#define INTC_VSSEL_VSEL10_POS (10U) +#define INTC_VSSEL_VSEL10 (0x00000400UL) +#define INTC_VSSEL_VSEL11_POS (11U) +#define INTC_VSSEL_VSEL11 (0x00000800UL) +#define INTC_VSSEL_VSEL12_POS (12U) +#define INTC_VSSEL_VSEL12 (0x00001000UL) +#define INTC_VSSEL_VSEL13_POS (13U) +#define INTC_VSSEL_VSEL13 (0x00002000UL) +#define INTC_VSSEL_VSEL14_POS (14U) +#define INTC_VSSEL_VSEL14 (0x00004000UL) +#define INTC_VSSEL_VSEL15_POS (15U) +#define INTC_VSSEL_VSEL15 (0x00008000UL) +#define INTC_VSSEL_VSEL16_POS (16U) +#define INTC_VSSEL_VSEL16 (0x00010000UL) +#define INTC_VSSEL_VSEL17_POS (17U) +#define INTC_VSSEL_VSEL17 (0x00020000UL) +#define INTC_VSSEL_VSEL18_POS (18U) +#define INTC_VSSEL_VSEL18 (0x00040000UL) +#define INTC_VSSEL_VSEL19_POS (19U) +#define INTC_VSSEL_VSEL19 (0x00080000UL) +#define INTC_VSSEL_VSEL20_POS (20U) +#define INTC_VSSEL_VSEL20 (0x00100000UL) +#define INTC_VSSEL_VSEL21_POS (21U) +#define INTC_VSSEL_VSEL21 (0x00200000UL) +#define INTC_VSSEL_VSEL22_POS (22U) +#define INTC_VSSEL_VSEL22 (0x00400000UL) +#define INTC_VSSEL_VSEL23_POS (23U) +#define INTC_VSSEL_VSEL23 (0x00800000UL) +#define INTC_VSSEL_VSEL24_POS (24U) +#define INTC_VSSEL_VSEL24 (0x01000000UL) +#define INTC_VSSEL_VSEL25_POS (25U) +#define INTC_VSSEL_VSEL25 (0x02000000UL) +#define INTC_VSSEL_VSEL26_POS (26U) +#define INTC_VSSEL_VSEL26 (0x04000000UL) +#define INTC_VSSEL_VSEL27_POS (27U) +#define INTC_VSSEL_VSEL27 (0x08000000UL) +#define INTC_VSSEL_VSEL28_POS (28U) +#define INTC_VSSEL_VSEL28 (0x10000000UL) +#define INTC_VSSEL_VSEL29_POS (29U) +#define INTC_VSSEL_VSEL29 (0x20000000UL) +#define INTC_VSSEL_VSEL30_POS (30U) +#define INTC_VSSEL_VSEL30 (0x40000000UL) +#define INTC_VSSEL_VSEL31_POS (31U) +#define INTC_VSSEL_VSEL31 (0x80000000UL) + +/* Bit definition for INTC_SWIER register */ +#define INTC_SWIER_SWIE0_POS (0U) +#define INTC_SWIER_SWIE0 (0x00000001UL) +#define INTC_SWIER_SWIE1_POS (1U) +#define INTC_SWIER_SWIE1 (0x00000002UL) +#define INTC_SWIER_SWIE2_POS (2U) +#define INTC_SWIER_SWIE2 (0x00000004UL) +#define INTC_SWIER_SWIE3_POS (3U) +#define INTC_SWIER_SWIE3 (0x00000008UL) +#define INTC_SWIER_SWIE4_POS (4U) +#define INTC_SWIER_SWIE4 (0x00000010UL) +#define INTC_SWIER_SWIE5_POS (5U) +#define INTC_SWIER_SWIE5 (0x00000020UL) +#define INTC_SWIER_SWIE6_POS (6U) +#define INTC_SWIER_SWIE6 (0x00000040UL) +#define INTC_SWIER_SWIE7_POS (7U) +#define INTC_SWIER_SWIE7 (0x00000080UL) +#define INTC_SWIER_SWIE8_POS (8U) +#define INTC_SWIER_SWIE8 (0x00000100UL) +#define INTC_SWIER_SWIE9_POS (9U) +#define INTC_SWIER_SWIE9 (0x00000200UL) +#define INTC_SWIER_SWIE10_POS (10U) +#define INTC_SWIER_SWIE10 (0x00000400UL) +#define INTC_SWIER_SWIE11_POS (11U) +#define INTC_SWIER_SWIE11 (0x00000800UL) +#define INTC_SWIER_SWIE12_POS (12U) +#define INTC_SWIER_SWIE12 (0x00001000UL) +#define INTC_SWIER_SWIE13_POS (13U) +#define INTC_SWIER_SWIE13 (0x00002000UL) +#define INTC_SWIER_SWIE14_POS (14U) +#define INTC_SWIER_SWIE14 (0x00004000UL) +#define INTC_SWIER_SWIE15_POS (15U) +#define INTC_SWIER_SWIE15 (0x00008000UL) +#define INTC_SWIER_SWIE16_POS (16U) +#define INTC_SWIER_SWIE16 (0x00010000UL) +#define INTC_SWIER_SWIE17_POS (17U) +#define INTC_SWIER_SWIE17 (0x00020000UL) +#define INTC_SWIER_SWIE18_POS (18U) +#define INTC_SWIER_SWIE18 (0x00040000UL) +#define INTC_SWIER_SWIE19_POS (19U) +#define INTC_SWIER_SWIE19 (0x00080000UL) +#define INTC_SWIER_SWIE20_POS (20U) +#define INTC_SWIER_SWIE20 (0x00100000UL) +#define INTC_SWIER_SWIE21_POS (21U) +#define INTC_SWIER_SWIE21 (0x00200000UL) +#define INTC_SWIER_SWIE22_POS (22U) +#define INTC_SWIER_SWIE22 (0x00400000UL) +#define INTC_SWIER_SWIE23_POS (23U) +#define INTC_SWIER_SWIE23 (0x00800000UL) +#define INTC_SWIER_SWIE24_POS (24U) +#define INTC_SWIER_SWIE24 (0x01000000UL) +#define INTC_SWIER_SWIE25_POS (25U) +#define INTC_SWIER_SWIE25 (0x02000000UL) +#define INTC_SWIER_SWIE26_POS (26U) +#define INTC_SWIER_SWIE26 (0x04000000UL) +#define INTC_SWIER_SWIE27_POS (27U) +#define INTC_SWIER_SWIE27 (0x08000000UL) +#define INTC_SWIER_SWIE28_POS (28U) +#define INTC_SWIER_SWIE28 (0x10000000UL) +#define INTC_SWIER_SWIE29_POS (29U) +#define INTC_SWIER_SWIE29 (0x20000000UL) +#define INTC_SWIER_SWIE30_POS (30U) +#define INTC_SWIER_SWIE30 (0x40000000UL) +#define INTC_SWIER_SWIE31_POS (31U) +#define INTC_SWIER_SWIE31 (0x80000000UL) + +/* Bit definition for INTC_EVTER register */ +#define INTC_EVTER_EVTE0_POS (0U) +#define INTC_EVTER_EVTE0 (0x00000001UL) +#define INTC_EVTER_EVTE1_POS (1U) +#define INTC_EVTER_EVTE1 (0x00000002UL) +#define INTC_EVTER_EVTE2_POS (2U) +#define INTC_EVTER_EVTE2 (0x00000004UL) +#define INTC_EVTER_EVTE3_POS (3U) +#define INTC_EVTER_EVTE3 (0x00000008UL) +#define INTC_EVTER_EVTE4_POS (4U) +#define INTC_EVTER_EVTE4 (0x00000010UL) +#define INTC_EVTER_EVTE5_POS (5U) +#define INTC_EVTER_EVTE5 (0x00000020UL) +#define INTC_EVTER_EVTE6_POS (6U) +#define INTC_EVTER_EVTE6 (0x00000040UL) +#define INTC_EVTER_EVTE7_POS (7U) +#define INTC_EVTER_EVTE7 (0x00000080UL) +#define INTC_EVTER_EVTE8_POS (8U) +#define INTC_EVTER_EVTE8 (0x00000100UL) +#define INTC_EVTER_EVTE9_POS (9U) +#define INTC_EVTER_EVTE9 (0x00000200UL) +#define INTC_EVTER_EVTE10_POS (10U) +#define INTC_EVTER_EVTE10 (0x00000400UL) +#define INTC_EVTER_EVTE11_POS (11U) +#define INTC_EVTER_EVTE11 (0x00000800UL) +#define INTC_EVTER_EVTE12_POS (12U) +#define INTC_EVTER_EVTE12 (0x00001000UL) +#define INTC_EVTER_EVTE13_POS (13U) +#define INTC_EVTER_EVTE13 (0x00002000UL) +#define INTC_EVTER_EVTE14_POS (14U) +#define INTC_EVTER_EVTE14 (0x00004000UL) +#define INTC_EVTER_EVTE15_POS (15U) +#define INTC_EVTER_EVTE15 (0x00008000UL) +#define INTC_EVTER_EVTE16_POS (16U) +#define INTC_EVTER_EVTE16 (0x00010000UL) +#define INTC_EVTER_EVTE17_POS (17U) +#define INTC_EVTER_EVTE17 (0x00020000UL) +#define INTC_EVTER_EVTE18_POS (18U) +#define INTC_EVTER_EVTE18 (0x00040000UL) +#define INTC_EVTER_EVTE19_POS (19U) +#define INTC_EVTER_EVTE19 (0x00080000UL) +#define INTC_EVTER_EVTE20_POS (20U) +#define INTC_EVTER_EVTE20 (0x00100000UL) +#define INTC_EVTER_EVTE21_POS (21U) +#define INTC_EVTER_EVTE21 (0x00200000UL) +#define INTC_EVTER_EVTE22_POS (22U) +#define INTC_EVTER_EVTE22 (0x00400000UL) +#define INTC_EVTER_EVTE23_POS (23U) +#define INTC_EVTER_EVTE23 (0x00800000UL) +#define INTC_EVTER_EVTE24_POS (24U) +#define INTC_EVTER_EVTE24 (0x01000000UL) +#define INTC_EVTER_EVTE25_POS (25U) +#define INTC_EVTER_EVTE25 (0x02000000UL) +#define INTC_EVTER_EVTE26_POS (26U) +#define INTC_EVTER_EVTE26 (0x04000000UL) +#define INTC_EVTER_EVTE27_POS (27U) +#define INTC_EVTER_EVTE27 (0x08000000UL) +#define INTC_EVTER_EVTE28_POS (28U) +#define INTC_EVTER_EVTE28 (0x10000000UL) +#define INTC_EVTER_EVTE29_POS (29U) +#define INTC_EVTER_EVTE29 (0x20000000UL) +#define INTC_EVTER_EVTE30_POS (30U) +#define INTC_EVTER_EVTE30 (0x40000000UL) +#define INTC_EVTER_EVTE31_POS (31U) +#define INTC_EVTER_EVTE31 (0x80000000UL) + +/* Bit definition for INTC_IER register */ +#define INTC_IER_IER0_POS (0U) +#define INTC_IER_IER0 (0x00000001UL) +#define INTC_IER_IER1_POS (1U) +#define INTC_IER_IER1 (0x00000002UL) +#define INTC_IER_IER2_POS (2U) +#define INTC_IER_IER2 (0x00000004UL) +#define INTC_IER_IER3_POS (3U) +#define INTC_IER_IER3 (0x00000008UL) +#define INTC_IER_IER4_POS (4U) +#define INTC_IER_IER4 (0x00000010UL) +#define INTC_IER_IER5_POS (5U) +#define INTC_IER_IER5 (0x00000020UL) +#define INTC_IER_IER6_POS (6U) +#define INTC_IER_IER6 (0x00000040UL) +#define INTC_IER_IER7_POS (7U) +#define INTC_IER_IER7 (0x00000080UL) +#define INTC_IER_IER8_POS (8U) +#define INTC_IER_IER8 (0x00000100UL) +#define INTC_IER_IER9_POS (9U) +#define INTC_IER_IER9 (0x00000200UL) +#define INTC_IER_IER10_POS (10U) +#define INTC_IER_IER10 (0x00000400UL) +#define INTC_IER_IER11_POS (11U) +#define INTC_IER_IER11 (0x00000800UL) +#define INTC_IER_IER12_POS (12U) +#define INTC_IER_IER12 (0x00001000UL) +#define INTC_IER_IER13_POS (13U) +#define INTC_IER_IER13 (0x00002000UL) +#define INTC_IER_IER14_POS (14U) +#define INTC_IER_IER14 (0x00004000UL) +#define INTC_IER_IER15_POS (15U) +#define INTC_IER_IER15 (0x00008000UL) +#define INTC_IER_IER16_POS (16U) +#define INTC_IER_IER16 (0x00010000UL) +#define INTC_IER_IER17_POS (17U) +#define INTC_IER_IER17 (0x00020000UL) +#define INTC_IER_IER18_POS (18U) +#define INTC_IER_IER18 (0x00040000UL) +#define INTC_IER_IER19_POS (19U) +#define INTC_IER_IER19 (0x00080000UL) +#define INTC_IER_IER20_POS (20U) +#define INTC_IER_IER20 (0x00100000UL) +#define INTC_IER_IER21_POS (21U) +#define INTC_IER_IER21 (0x00200000UL) +#define INTC_IER_IER22_POS (22U) +#define INTC_IER_IER22 (0x00400000UL) +#define INTC_IER_IER23_POS (23U) +#define INTC_IER_IER23 (0x00800000UL) +#define INTC_IER_IER24_POS (24U) +#define INTC_IER_IER24 (0x01000000UL) +#define INTC_IER_IER25_POS (25U) +#define INTC_IER_IER25 (0x02000000UL) +#define INTC_IER_IER26_POS (26U) +#define INTC_IER_IER26 (0x04000000UL) +#define INTC_IER_IER27_POS (27U) +#define INTC_IER_IER27 (0x08000000UL) +#define INTC_IER_IER28_POS (28U) +#define INTC_IER_IER28 (0x10000000UL) +#define INTC_IER_IER29_POS (29U) +#define INTC_IER_IER29 (0x20000000UL) +#define INTC_IER_IER30_POS (30U) +#define INTC_IER_IER30 (0x40000000UL) +#define INTC_IER_IER31_POS (31U) +#define INTC_IER_IER31 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral KEYSCAN +*******************************************************************************/ +/* Bit definition for KEYSCAN_SCR register */ +#define KEYSCAN_SCR_KEYINSEL_POS (0U) +#define KEYSCAN_SCR_KEYINSEL (0x0000FFFFUL) +#define KEYSCAN_SCR_KEYINSEL_0 (0x00000001UL) +#define KEYSCAN_SCR_KEYINSEL_1 (0x00000002UL) +#define KEYSCAN_SCR_KEYINSEL_2 (0x00000004UL) +#define KEYSCAN_SCR_KEYINSEL_3 (0x00000008UL) +#define KEYSCAN_SCR_KEYINSEL_4 (0x00000010UL) +#define KEYSCAN_SCR_KEYINSEL_5 (0x00000020UL) +#define KEYSCAN_SCR_KEYINSEL_6 (0x00000040UL) +#define KEYSCAN_SCR_KEYINSEL_7 (0x00000080UL) +#define KEYSCAN_SCR_KEYINSEL_8 (0x00000100UL) +#define KEYSCAN_SCR_KEYINSEL_9 (0x00000200UL) +#define KEYSCAN_SCR_KEYINSEL_10 (0x00000400UL) +#define KEYSCAN_SCR_KEYINSEL_11 (0x00000800UL) +#define KEYSCAN_SCR_KEYINSEL_12 (0x00001000UL) +#define KEYSCAN_SCR_KEYINSEL_13 (0x00002000UL) +#define KEYSCAN_SCR_KEYINSEL_14 (0x00004000UL) +#define KEYSCAN_SCR_KEYINSEL_15 (0x00008000UL) +#define KEYSCAN_SCR_KEYOUTSEL_POS (16U) +#define KEYSCAN_SCR_KEYOUTSEL (0x00070000UL) +#define KEYSCAN_SCR_CKSEL_POS (20U) +#define KEYSCAN_SCR_CKSEL (0x00300000UL) +#define KEYSCAN_SCR_CKSEL_0 (0x00100000UL) +#define KEYSCAN_SCR_CKSEL_1 (0x00200000UL) +#define KEYSCAN_SCR_T_LLEVEL_POS (24U) +#define KEYSCAN_SCR_T_LLEVEL (0x1F000000UL) +#define KEYSCAN_SCR_T_HIZ_POS (29U) +#define KEYSCAN_SCR_T_HIZ (0xE0000000UL) + +/* Bit definition for KEYSCAN_SER register */ +#define KEYSCAN_SER_SEN (0x00000001UL) + +/* Bit definition for KEYSCAN_SSR register */ +#define KEYSCAN_SSR_INDEX (0x00000007UL) + +/******************************************************************************* + Bit definition for Peripheral MAU +*******************************************************************************/ +/* Bit definition for MAU_CSR register */ +#define MAU_CSR_START_POS (0U) +#define MAU_CSR_START (0x00000001UL) +#define MAU_CSR_INTEN_POS (1U) +#define MAU_CSR_INTEN (0x00000002UL) +#define MAU_CSR_BUSY_POS (3U) +#define MAU_CSR_BUSY (0x00000008UL) +#define MAU_CSR_SHIFT_POS (8U) +#define MAU_CSR_SHIFT (0x00001F00UL) + +/* Bit definition for MAU_DTR0 register */ +#define MAU_DTR0 (0xFFFFFFFFUL) + +/* Bit definition for MAU_RTR0 register */ +#define MAU_RTR0_SQRT_DOUT (0x0001FFFFUL) + +/* Bit definition for MAU_DTR1 register */ +#define MAU_DTR1_SIN_DIN (0x00000FFFUL) + +/* Bit definition for MAU_RTR1 register */ +#define MAU_RTR1_SIN_DOUT (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral MPU +*******************************************************************************/ +/* Bit definition for MPU_RGD register */ +#define MPU_RGD_MPURGSIZE_POS (0U) +#define MPU_RGD_MPURGSIZE (0x0000001FUL) +#define MPU_RGD_MPURGSIZE_0 (0x00000001UL) +#define MPU_RGD_MPURGSIZE_1 (0x00000002UL) +#define MPU_RGD_MPURGSIZE_2 (0x00000004UL) +#define MPU_RGD_MPURGSIZE_3 (0x00000008UL) +#define MPU_RGD_MPURGSIZE_4 (0x00000010UL) +#define MPU_RGD_MPURGADDR_POS (5U) +#define MPU_RGD_MPURGADDR (0xFFFFFFE0UL) + +/* Bit definition for MPU_SR register */ +#define MPU_SR_SMPU1EAF_POS (0U) +#define MPU_SR_SMPU1EAF (0x00000001UL) +#define MPU_SR_SMPU2EAF_POS (1U) +#define MPU_SR_SMPU2EAF (0x00000002UL) +#define MPU_SR_FMPUEAF_POS (2U) +#define MPU_SR_FMPUEAF (0x00000004UL) +#define MPU_SR_HMPUEAF_POS (3U) +#define MPU_SR_HMPUEAF (0x00000008UL) +#define MPU_SR_EMPUEAF_POS (4U) +#define MPU_SR_EMPUEAF (0x00000010UL) + +/* Bit definition for MPU_ECLR register */ +#define MPU_ECLR_SMPU1ECLR_POS (0U) +#define MPU_ECLR_SMPU1ECLR (0x00000001UL) +#define MPU_ECLR_SMPU2ECLR_POS (1U) +#define MPU_ECLR_SMPU2ECLR (0x00000002UL) +#define MPU_ECLR_FMPUECLR_POS (2U) +#define MPU_ECLR_FMPUECLR (0x00000004UL) +#define MPU_ECLR_HMPUECLR_POS (3U) +#define MPU_ECLR_HMPUECLR (0x00000008UL) +#define MPU_ECLR_EMPUECLR_POS (4U) +#define MPU_ECLR_EMPUECLR (0x00000010UL) + +/* Bit definition for MPU_WP register */ +#define MPU_WP_MPUWE_POS (0U) +#define MPU_WP_MPUWE (0x00000001UL) +#define MPU_WP_WKEY_POS (1U) +#define MPU_WP_WKEY (0x0000FFFEUL) + +/* Bit definition for MPU_IPPR register */ +#define MPU_IPPR_AESRDP_POS (0U) +#define MPU_IPPR_AESRDP (0x00000001UL) +#define MPU_IPPR_AESWRP_POS (1U) +#define MPU_IPPR_AESWRP (0x00000002UL) +#define MPU_IPPR_HASHRDP_POS (2U) +#define MPU_IPPR_HASHRDP (0x00000004UL) +#define MPU_IPPR_HASHWRP_POS (3U) +#define MPU_IPPR_HASHWRP (0x00000008UL) +#define MPU_IPPR_TRNGRDP_POS (4U) +#define MPU_IPPR_TRNGRDP (0x00000010UL) +#define MPU_IPPR_TRNGWRP_POS (5U) +#define MPU_IPPR_TRNGWRP (0x00000020UL) +#define MPU_IPPR_CRCRDP_POS (6U) +#define MPU_IPPR_CRCRDP (0x00000040UL) +#define MPU_IPPR_CRCWRP_POS (7U) +#define MPU_IPPR_CRCWRP (0x00000080UL) +#define MPU_IPPR_FMCRDP_POS (8U) +#define MPU_IPPR_FMCRDP (0x00000100UL) +#define MPU_IPPR_FMCWRP_POS (9U) +#define MPU_IPPR_FMCWRP (0x00000200UL) +#define MPU_IPPR_WDTRDP_POS (12U) +#define MPU_IPPR_WDTRDP (0x00001000UL) +#define MPU_IPPR_WDTWRP_POS (13U) +#define MPU_IPPR_WDTWRP (0x00002000UL) +#define MPU_IPPR_SWDTRDP_POS (14U) +#define MPU_IPPR_SWDTRDP (0x00004000UL) +#define MPU_IPPR_SWDTWRP_POS (15U) +#define MPU_IPPR_SWDTWRP (0x00008000UL) +#define MPU_IPPR_BKSRAMRDP_POS (16U) +#define MPU_IPPR_BKSRAMRDP (0x00010000UL) +#define MPU_IPPR_BKSRAMWRP_POS (17U) +#define MPU_IPPR_BKSRAMWRP (0x00020000UL) +#define MPU_IPPR_RTCRDP_POS (18U) +#define MPU_IPPR_RTCRDP (0x00040000UL) +#define MPU_IPPR_RTCWRP_POS (19U) +#define MPU_IPPR_RTCWRP (0x00080000UL) +#define MPU_IPPR_DMPURDP_POS (20U) +#define MPU_IPPR_DMPURDP (0x00100000UL) +#define MPU_IPPR_DMPUWRP_POS (21U) +#define MPU_IPPR_DMPUWRP (0x00200000UL) +#define MPU_IPPR_SRAMCRDP_POS (22U) +#define MPU_IPPR_SRAMCRDP (0x00400000UL) +#define MPU_IPPR_SRAMCWRP_POS (23U) +#define MPU_IPPR_SRAMCWRP (0x00800000UL) +#define MPU_IPPR_INTCRDP_POS (24U) +#define MPU_IPPR_INTCRDP (0x01000000UL) +#define MPU_IPPR_INTCWRP_POS (25U) +#define MPU_IPPR_INTCWRP (0x02000000UL) +#define MPU_IPPR_SYSCRDP_POS (26U) +#define MPU_IPPR_SYSCRDP (0x04000000UL) +#define MPU_IPPR_SYSCWRP_POS (27U) +#define MPU_IPPR_SYSCWRP (0x08000000UL) +#define MPU_IPPR_MSTPRDP_POS (28U) +#define MPU_IPPR_MSTPRDP (0x10000000UL) +#define MPU_IPPR_MSPTWRP_POS (29U) +#define MPU_IPPR_MSPTWRP (0x20000000UL) +#define MPU_IPPR_BUSERRE_POS (31U) +#define MPU_IPPR_BUSERRE (0x80000000UL) + +/* Bit definition for MPU_S1RGE register */ +#define MPU_S1RGE_S1RG0E_POS (0U) +#define MPU_S1RGE_S1RG0E (0x00000001UL) +#define MPU_S1RGE_S1RG1E_POS (1U) +#define MPU_S1RGE_S1RG1E (0x00000002UL) +#define MPU_S1RGE_S1RG2E_POS (2U) +#define MPU_S1RGE_S1RG2E (0x00000004UL) +#define MPU_S1RGE_S1RG3E_POS (3U) +#define MPU_S1RGE_S1RG3E (0x00000008UL) +#define MPU_S1RGE_S1RG4E_POS (4U) +#define MPU_S1RGE_S1RG4E (0x00000010UL) +#define MPU_S1RGE_S1RG5E_POS (5U) +#define MPU_S1RGE_S1RG5E (0x00000020UL) +#define MPU_S1RGE_S1RG6E_POS (6U) +#define MPU_S1RGE_S1RG6E (0x00000040UL) +#define MPU_S1RGE_S1RG7E_POS (7U) +#define MPU_S1RGE_S1RG7E (0x00000080UL) +#define MPU_S1RGE_S1RG8E_POS (8U) +#define MPU_S1RGE_S1RG8E (0x00000100UL) +#define MPU_S1RGE_S1RG9E_POS (9U) +#define MPU_S1RGE_S1RG9E (0x00000200UL) +#define MPU_S1RGE_S1RG10E_POS (10U) +#define MPU_S1RGE_S1RG10E (0x00000400UL) +#define MPU_S1RGE_S1RG11E_POS (11U) +#define MPU_S1RGE_S1RG11E (0x00000800UL) +#define MPU_S1RGE_S1RG12E_POS (12U) +#define MPU_S1RGE_S1RG12E (0x00001000UL) +#define MPU_S1RGE_S1RG13E_POS (13U) +#define MPU_S1RGE_S1RG13E (0x00002000UL) +#define MPU_S1RGE_S1RG14E_POS (14U) +#define MPU_S1RGE_S1RG14E (0x00004000UL) +#define MPU_S1RGE_S1RG15E_POS (15U) +#define MPU_S1RGE_S1RG15E (0x00008000UL) + +/* Bit definition for MPU_S1RGWP register */ +#define MPU_S1RGWP_S1RG0WP_POS (0U) +#define MPU_S1RGWP_S1RG0WP (0x00000001UL) +#define MPU_S1RGWP_S1RG1WP_POS (1U) +#define MPU_S1RGWP_S1RG1WP (0x00000002UL) +#define MPU_S1RGWP_S1RG2WP_POS (2U) +#define MPU_S1RGWP_S1RG2WP (0x00000004UL) +#define MPU_S1RGWP_S1RG3WP_POS (3U) +#define MPU_S1RGWP_S1RG3WP (0x00000008UL) +#define MPU_S1RGWP_S1RG4WP_POS (4U) +#define MPU_S1RGWP_S1RG4WP (0x00000010UL) +#define MPU_S1RGWP_S1RG5WP_POS (5U) +#define MPU_S1RGWP_S1RG5WP (0x00000020UL) +#define MPU_S1RGWP_S1RG6WP_POS (6U) +#define MPU_S1RGWP_S1RG6WP (0x00000040UL) +#define MPU_S1RGWP_S1RG7WP_POS (7U) +#define MPU_S1RGWP_S1RG7WP (0x00000080UL) +#define MPU_S1RGWP_S1RG8WP_POS (8U) +#define MPU_S1RGWP_S1RG8WP (0x00000100UL) +#define MPU_S1RGWP_S1RG9WP_POS (9U) +#define MPU_S1RGWP_S1RG9WP (0x00000200UL) +#define MPU_S1RGWP_S1RG10WP_POS (10U) +#define MPU_S1RGWP_S1RG10WP (0x00000400UL) +#define MPU_S1RGWP_S1RG11WP_POS (11U) +#define MPU_S1RGWP_S1RG11WP (0x00000800UL) +#define MPU_S1RGWP_S1RG12WP_POS (12U) +#define MPU_S1RGWP_S1RG12WP (0x00001000UL) +#define MPU_S1RGWP_S1RG13WP_POS (13U) +#define MPU_S1RGWP_S1RG13WP (0x00002000UL) +#define MPU_S1RGWP_S1RG14WP_POS (14U) +#define MPU_S1RGWP_S1RG14WP (0x00004000UL) +#define MPU_S1RGWP_S1RG15WP_POS (15U) +#define MPU_S1RGWP_S1RG15WP (0x00008000UL) + +/* Bit definition for MPU_S1RGRP register */ +#define MPU_S1RGRP_S1RG0RP_POS (0U) +#define MPU_S1RGRP_S1RG0RP (0x00000001UL) +#define MPU_S1RGRP_S1RG1RP_POS (1U) +#define MPU_S1RGRP_S1RG1RP (0x00000002UL) +#define MPU_S1RGRP_S1RG2RP_POS (2U) +#define MPU_S1RGRP_S1RG2RP (0x00000004UL) +#define MPU_S1RGRP_S1RG3RP_POS (3U) +#define MPU_S1RGRP_S1RG3RP (0x00000008UL) +#define MPU_S1RGRP_S1RG4RP_POS (4U) +#define MPU_S1RGRP_S1RG4RP (0x00000010UL) +#define MPU_S1RGRP_S1RG5RP_POS (5U) +#define MPU_S1RGRP_S1RG5RP (0x00000020UL) +#define MPU_S1RGRP_S1RG6RP_POS (6U) +#define MPU_S1RGRP_S1RG6RP (0x00000040UL) +#define MPU_S1RGRP_S1RG7RP_POS (7U) +#define MPU_S1RGRP_S1RG7RP (0x00000080UL) +#define MPU_S1RGRP_S1RG8RP_POS (8U) +#define MPU_S1RGRP_S1RG8RP (0x00000100UL) +#define MPU_S1RGRP_S1RG9RP_POS (9U) +#define MPU_S1RGRP_S1RG9RP (0x00000200UL) +#define MPU_S1RGRP_S1RG10RP_POS (10U) +#define MPU_S1RGRP_S1RG10RP (0x00000400UL) +#define MPU_S1RGRP_S1RG11RP_POS (11U) +#define MPU_S1RGRP_S1RG11RP (0x00000800UL) +#define MPU_S1RGRP_S1RG12RP_POS (12U) +#define MPU_S1RGRP_S1RG12RP (0x00001000UL) +#define MPU_S1RGRP_S1RG13RP_POS (13U) +#define MPU_S1RGRP_S1RG13RP (0x00002000UL) +#define MPU_S1RGRP_S1RG14RP_POS (14U) +#define MPU_S1RGRP_S1RG14RP (0x00004000UL) +#define MPU_S1RGRP_S1RG15RP_POS (15U) +#define MPU_S1RGRP_S1RG15RP (0x00008000UL) + +/* Bit definition for MPU_S1CR register */ +#define MPU_S1CR_SMPU1BRP_POS (0U) +#define MPU_S1CR_SMPU1BRP (0x00000001UL) +#define MPU_S1CR_SMPU1BWP_POS (1U) +#define MPU_S1CR_SMPU1BWP (0x00000002UL) +#define MPU_S1CR_SMPU1ACT_POS (2U) +#define MPU_S1CR_SMPU1ACT (0x0000000CUL) +#define MPU_S1CR_SMPU1ACT_0 (0x00000004UL) +#define MPU_S1CR_SMPU1ACT_1 (0x00000008UL) +#define MPU_S1CR_SMPU1E_POS (7U) +#define MPU_S1CR_SMPU1E (0x00000080UL) + +/* Bit definition for MPU_S2RGE register */ +#define MPU_S2RGE_S2RG0E_POS (0U) +#define MPU_S2RGE_S2RG0E (0x00000001UL) +#define MPU_S2RGE_S2RG1E_POS (1U) +#define MPU_S2RGE_S2RG1E (0x00000002UL) +#define MPU_S2RGE_S2RG2E_POS (2U) +#define MPU_S2RGE_S2RG2E (0x00000004UL) +#define MPU_S2RGE_S2RG3E_POS (3U) +#define MPU_S2RGE_S2RG3E (0x00000008UL) +#define MPU_S2RGE_S2RG4E_POS (4U) +#define MPU_S2RGE_S2RG4E (0x00000010UL) +#define MPU_S2RGE_S2RG5E_POS (5U) +#define MPU_S2RGE_S2RG5E (0x00000020UL) +#define MPU_S2RGE_S2RG6E_POS (6U) +#define MPU_S2RGE_S2RG6E (0x00000040UL) +#define MPU_S2RGE_S2RG7E_POS (7U) +#define MPU_S2RGE_S2RG7E (0x00000080UL) +#define MPU_S2RGE_S2RG8E_POS (8U) +#define MPU_S2RGE_S2RG8E (0x00000100UL) +#define MPU_S2RGE_S2RG9E_POS (9U) +#define MPU_S2RGE_S2RG9E (0x00000200UL) +#define MPU_S2RGE_S2RG10E_POS (10U) +#define MPU_S2RGE_S2RG10E (0x00000400UL) +#define MPU_S2RGE_S2RG11E_POS (11U) +#define MPU_S2RGE_S2RG11E (0x00000800UL) +#define MPU_S2RGE_S2RG12E_POS (12U) +#define MPU_S2RGE_S2RG12E (0x00001000UL) +#define MPU_S2RGE_S2RG13E_POS (13U) +#define MPU_S2RGE_S2RG13E (0x00002000UL) +#define MPU_S2RGE_S2RG14E_POS (14U) +#define MPU_S2RGE_S2RG14E (0x00004000UL) +#define MPU_S2RGE_S2RG15E_POS (15U) +#define MPU_S2RGE_S2RG15E (0x00008000UL) + +/* Bit definition for MPU_S2RGWP register */ +#define MPU_S2RGWP_S2RG0WP_POS (0U) +#define MPU_S2RGWP_S2RG0WP (0x00000001UL) +#define MPU_S2RGWP_S2RG1WP_POS (1U) +#define MPU_S2RGWP_S2RG1WP (0x00000002UL) +#define MPU_S2RGWP_S2RG2WP_POS (2U) +#define MPU_S2RGWP_S2RG2WP (0x00000004UL) +#define MPU_S2RGWP_S2RG3WP_POS (3U) +#define MPU_S2RGWP_S2RG3WP (0x00000008UL) +#define MPU_S2RGWP_S2RG4WP_POS (4U) +#define MPU_S2RGWP_S2RG4WP (0x00000010UL) +#define MPU_S2RGWP_S2RG5WP_POS (5U) +#define MPU_S2RGWP_S2RG5WP (0x00000020UL) +#define MPU_S2RGWP_S2RG6WP_POS (6U) +#define MPU_S2RGWP_S2RG6WP (0x00000040UL) +#define MPU_S2RGWP_S2RG7WP_POS (7U) +#define MPU_S2RGWP_S2RG7WP (0x00000080UL) +#define MPU_S2RGWP_S2RG8WP_POS (8U) +#define MPU_S2RGWP_S2RG8WP (0x00000100UL) +#define MPU_S2RGWP_S2RG9WP_POS (9U) +#define MPU_S2RGWP_S2RG9WP (0x00000200UL) +#define MPU_S2RGWP_S2RG10WP_POS (10U) +#define MPU_S2RGWP_S2RG10WP (0x00000400UL) +#define MPU_S2RGWP_S2RG11WP_POS (11U) +#define MPU_S2RGWP_S2RG11WP (0x00000800UL) +#define MPU_S2RGWP_S2RG12WP_POS (12U) +#define MPU_S2RGWP_S2RG12WP (0x00001000UL) +#define MPU_S2RGWP_S2RG13WP_POS (13U) +#define MPU_S2RGWP_S2RG13WP (0x00002000UL) +#define MPU_S2RGWP_S2RG14WP_POS (14U) +#define MPU_S2RGWP_S2RG14WP (0x00004000UL) +#define MPU_S2RGWP_S2RG15WP_POS (15U) +#define MPU_S2RGWP_S2RG15WP (0x00008000UL) + +/* Bit definition for MPU_S2RGRP register */ +#define MPU_S2RGRP_S2RG0RP_POS (0U) +#define MPU_S2RGRP_S2RG0RP (0x00000001UL) +#define MPU_S2RGRP_S2RG1RP_POS (1U) +#define MPU_S2RGRP_S2RG1RP (0x00000002UL) +#define MPU_S2RGRP_S2RG2RP_POS (2U) +#define MPU_S2RGRP_S2RG2RP (0x00000004UL) +#define MPU_S2RGRP_S2RG3RP_POS (3U) +#define MPU_S2RGRP_S2RG3RP (0x00000008UL) +#define MPU_S2RGRP_S2RG4RP_POS (4U) +#define MPU_S2RGRP_S2RG4RP (0x00000010UL) +#define MPU_S2RGRP_S2RG5RP_POS (5U) +#define MPU_S2RGRP_S2RG5RP (0x00000020UL) +#define MPU_S2RGRP_S2RG6RP_POS (6U) +#define MPU_S2RGRP_S2RG6RP (0x00000040UL) +#define MPU_S2RGRP_S2RG7RP_POS (7U) +#define MPU_S2RGRP_S2RG7RP (0x00000080UL) +#define MPU_S2RGRP_S2RG8RP_POS (8U) +#define MPU_S2RGRP_S2RG8RP (0x00000100UL) +#define MPU_S2RGRP_S2RG9RP_POS (9U) +#define MPU_S2RGRP_S2RG9RP (0x00000200UL) +#define MPU_S2RGRP_S2RG10RP_POS (10U) +#define MPU_S2RGRP_S2RG10RP (0x00000400UL) +#define MPU_S2RGRP_S2RG11RP_POS (11U) +#define MPU_S2RGRP_S2RG11RP (0x00000800UL) +#define MPU_S2RGRP_S2RG12RP_POS (12U) +#define MPU_S2RGRP_S2RG12RP (0x00001000UL) +#define MPU_S2RGRP_S2RG13RP_POS (13U) +#define MPU_S2RGRP_S2RG13RP (0x00002000UL) +#define MPU_S2RGRP_S2RG14RP_POS (14U) +#define MPU_S2RGRP_S2RG14RP (0x00004000UL) +#define MPU_S2RGRP_S2RG15RP_POS (15U) +#define MPU_S2RGRP_S2RG15RP (0x00008000UL) + +/* Bit definition for MPU_S2CR register */ +#define MPU_S2CR_SMPU2BRP_POS (0U) +#define MPU_S2CR_SMPU2BRP (0x00000001UL) +#define MPU_S2CR_SMPU2BWP_POS (1U) +#define MPU_S2CR_SMPU2BWP (0x00000002UL) +#define MPU_S2CR_SMPU2ACT_POS (2U) +#define MPU_S2CR_SMPU2ACT (0x0000000CUL) +#define MPU_S2CR_SMPU2ACT_0 (0x00000004UL) +#define MPU_S2CR_SMPU2ACT_1 (0x00000008UL) +#define MPU_S2CR_SMPU2E_POS (7U) +#define MPU_S2CR_SMPU2E (0x00000080UL) + +/* Bit definition for MPU_FRGE register */ +#define MPU_FRGE_FMPU0E_POS (0U) +#define MPU_FRGE_FMPU0E (0x00000001UL) +#define MPU_FRGE_FMPU1E_POS (1U) +#define MPU_FRGE_FMPU1E (0x00000002UL) +#define MPU_FRGE_FMPU2E_POS (2U) +#define MPU_FRGE_FMPU2E (0x00000004UL) +#define MPU_FRGE_FMPU3E_POS (3U) +#define MPU_FRGE_FMPU3E (0x00000008UL) +#define MPU_FRGE_FMPU4E_POS (4U) +#define MPU_FRGE_FMPU4E (0x00000010UL) +#define MPU_FRGE_FMPU5E_POS (5U) +#define MPU_FRGE_FMPU5E (0x00000020UL) +#define MPU_FRGE_FMPU6E_POS (6U) +#define MPU_FRGE_FMPU6E (0x00000040UL) +#define MPU_FRGE_FMPU7E_POS (7U) +#define MPU_FRGE_FMPU7E (0x00000080UL) + +/* Bit definition for MPU_FRGWP register */ +#define MPU_FRGWP_FMPU0WP_POS (0U) +#define MPU_FRGWP_FMPU0WP (0x00000001UL) +#define MPU_FRGWP_FMPU1WP_POS (1U) +#define MPU_FRGWP_FMPU1WP (0x00000002UL) +#define MPU_FRGWP_FMPU2WP_POS (2U) +#define MPU_FRGWP_FMPU2WP (0x00000004UL) +#define MPU_FRGWP_FMPU3WP_POS (3U) +#define MPU_FRGWP_FMPU3WP (0x00000008UL) +#define MPU_FRGWP_FMPU4WP_POS (4U) +#define MPU_FRGWP_FMPU4WP (0x00000010UL) +#define MPU_FRGWP_FMPU5WP_POS (5U) +#define MPU_FRGWP_FMPU5WP (0x00000020UL) +#define MPU_FRGWP_FMPU6WP_POS (6U) +#define MPU_FRGWP_FMPU6WP (0x00000040UL) +#define MPU_FRGWP_FMPU7WP_POS (7U) +#define MPU_FRGWP_FMPU7WP (0x00000080UL) + +/* Bit definition for MPU_FRGRP register */ +#define MPU_FRGRP_FMPU0RP_POS (0U) +#define MPU_FRGRP_FMPU0RP (0x00000001UL) +#define MPU_FRGRP_FMPU1RP_POS (1U) +#define MPU_FRGRP_FMPU1RP (0x00000002UL) +#define MPU_FRGRP_FMPU2RP_POS (2U) +#define MPU_FRGRP_FMPU2RP (0x00000004UL) +#define MPU_FRGRP_FMPU3RP_POS (3U) +#define MPU_FRGRP_FMPU3RP (0x00000008UL) +#define MPU_FRGRP_FMPU4RP_POS (4U) +#define MPU_FRGRP_FMPU4RP (0x00000010UL) +#define MPU_FRGRP_FMPU5RP_POS (5U) +#define MPU_FRGRP_FMPU5RP (0x00000020UL) +#define MPU_FRGRP_FMPU6RP_POS (6U) +#define MPU_FRGRP_FMPU6RP (0x00000040UL) +#define MPU_FRGRP_FMPU7RP_POS (7U) +#define MPU_FRGRP_FMPU7RP (0x00000080UL) + +/* Bit definition for MPU_FCR register */ +#define MPU_FCR_FMPUBRP_POS (0U) +#define MPU_FCR_FMPUBRP (0x00000001UL) +#define MPU_FCR_FMPUBWP_POS (1U) +#define MPU_FCR_FMPUBWP (0x00000002UL) +#define MPU_FCR_FMPUACT_POS (2U) +#define MPU_FCR_FMPUACT (0x0000000CUL) +#define MPU_FCR_FMPUACT_0 (0x00000004UL) +#define MPU_FCR_FMPUACT_1 (0x00000008UL) +#define MPU_FCR_FMPUE_POS (7U) +#define MPU_FCR_FMPUE (0x00000080UL) + +/* Bit definition for MPU_HRGE register */ +#define MPU_HRGE_HMPU0E_POS (0U) +#define MPU_HRGE_HMPU0E (0x00000001UL) +#define MPU_HRGE_HMPU1E_POS (1U) +#define MPU_HRGE_HMPU1E (0x00000002UL) +#define MPU_HRGE_HMPU2E_POS (2U) +#define MPU_HRGE_HMPU2E (0x00000004UL) +#define MPU_HRGE_HMPU3E_POS (3U) +#define MPU_HRGE_HMPU3E (0x00000008UL) +#define MPU_HRGE_HMPU4E_POS (4U) +#define MPU_HRGE_HMPU4E (0x00000010UL) +#define MPU_HRGE_HMPU5E_POS (5U) +#define MPU_HRGE_HMPU5E (0x00000020UL) +#define MPU_HRGE_HMPU6E_POS (6U) +#define MPU_HRGE_HMPU6E (0x00000040UL) +#define MPU_HRGE_HMPU7E_POS (7U) +#define MPU_HRGE_HMPU7E (0x00000080UL) + +/* Bit definition for MPU_HRGWP register */ +#define MPU_HRGWP_HMPU0WP_POS (0U) +#define MPU_HRGWP_HMPU0WP (0x00000001UL) +#define MPU_HRGWP_HMPU1WP_POS (1U) +#define MPU_HRGWP_HMPU1WP (0x00000002UL) +#define MPU_HRGWP_HMPU2WP_POS (2U) +#define MPU_HRGWP_HMPU2WP (0x00000004UL) +#define MPU_HRGWP_HMPU3WP_POS (3U) +#define MPU_HRGWP_HMPU3WP (0x00000008UL) +#define MPU_HRGWP_HMPU4WP_POS (4U) +#define MPU_HRGWP_HMPU4WP (0x00000010UL) +#define MPU_HRGWP_HMPU5WP_POS (5U) +#define MPU_HRGWP_HMPU5WP (0x00000020UL) +#define MPU_HRGWP_HMPU6WP_POS (6U) +#define MPU_HRGWP_HMPU6WP (0x00000040UL) +#define MPU_HRGWP_HMPU7WP_POS (7U) +#define MPU_HRGWP_HMPU7WP (0x00000080UL) + +/* Bit definition for MPU_HRGRP register */ +#define MPU_HRGRP_HMPU0RP_POS (0U) +#define MPU_HRGRP_HMPU0RP (0x00000001UL) +#define MPU_HRGRP_HMPU1RP_POS (1U) +#define MPU_HRGRP_HMPU1RP (0x00000002UL) +#define MPU_HRGRP_HMPU2RP_POS (2U) +#define MPU_HRGRP_HMPU2RP (0x00000004UL) +#define MPU_HRGRP_HMPU3RP_POS (3U) +#define MPU_HRGRP_HMPU3RP (0x00000008UL) +#define MPU_HRGRP_HMPU4RP_POS (4U) +#define MPU_HRGRP_HMPU4RP (0x00000010UL) +#define MPU_HRGRP_HMPU5RP_POS (5U) +#define MPU_HRGRP_HMPU5RP (0x00000020UL) +#define MPU_HRGRP_HMPU6RP_POS (6U) +#define MPU_HRGRP_HMPU6RP (0x00000040UL) +#define MPU_HRGRP_HMPU7RP_POS (7U) +#define MPU_HRGRP_HMPU7RP (0x00000080UL) + +/* Bit definition for MPU_HCR register */ +#define MPU_HCR_HMPUBRP_POS (0U) +#define MPU_HCR_HMPUBRP (0x00000001UL) +#define MPU_HCR_HMPUBWP_POS (1U) +#define MPU_HCR_HMPUBWP (0x00000002UL) +#define MPU_HCR_HMPUACT_POS (2U) +#define MPU_HCR_HMPUACT (0x0000000CUL) +#define MPU_HCR_HMPUACT_0 (0x00000004UL) +#define MPU_HCR_HMPUACT_1 (0x00000008UL) +#define MPU_HCR_HMPUE_POS (7U) +#define MPU_HCR_HMPUE (0x00000080UL) + +/* Bit definition for MPU_ERGE register */ +#define MPU_ERGE_EMPU0E_POS (0U) +#define MPU_ERGE_EMPU0E (0x00000001UL) +#define MPU_ERGE_EMPU1E_POS (1U) +#define MPU_ERGE_EMPU1E (0x00000002UL) +#define MPU_ERGE_EMPU2E_POS (2U) +#define MPU_ERGE_EMPU2E (0x00000004UL) +#define MPU_ERGE_EMPU3E_POS (3U) +#define MPU_ERGE_EMPU3E (0x00000008UL) +#define MPU_ERGE_EMPU4E_POS (4U) +#define MPU_ERGE_EMPU4E (0x00000010UL) +#define MPU_ERGE_EMPU5E_POS (5U) +#define MPU_ERGE_EMPU5E (0x00000020UL) +#define MPU_ERGE_EMPU6E_POS (6U) +#define MPU_ERGE_EMPU6E (0x00000040UL) +#define MPU_ERGE_EMPU7E_POS (7U) +#define MPU_ERGE_EMPU7E (0x00000080UL) + +/* Bit definition for MPU_ERGWP register */ +#define MPU_ERGWP_EMPU0WP_POS (0U) +#define MPU_ERGWP_EMPU0WP (0x00000001UL) +#define MPU_ERGWP_EMPU1WP_POS (1U) +#define MPU_ERGWP_EMPU1WP (0x00000002UL) +#define MPU_ERGWP_EMPU2WP_POS (2U) +#define MPU_ERGWP_EMPU2WP (0x00000004UL) +#define MPU_ERGWP_EMPU3WP_POS (3U) +#define MPU_ERGWP_EMPU3WP (0x00000008UL) +#define MPU_ERGWP_EMPU4WP_POS (4U) +#define MPU_ERGWP_EMPU4WP (0x00000010UL) +#define MPU_ERGWP_EMPU5WP_POS (5U) +#define MPU_ERGWP_EMPU5WP (0x00000020UL) +#define MPU_ERGWP_EMPU6WP_POS (6U) +#define MPU_ERGWP_EMPU6WP (0x00000040UL) +#define MPU_ERGWP_EMPU7WP_POS (7U) +#define MPU_ERGWP_EMPU7WP (0x00000080UL) + +/* Bit definition for MPU_ERGRP register */ +#define MPU_ERGRP_EMPU0RP_POS (0U) +#define MPU_ERGRP_EMPU0RP (0x00000001UL) +#define MPU_ERGRP_EMPU1RP_POS (1U) +#define MPU_ERGRP_EMPU1RP (0x00000002UL) +#define MPU_ERGRP_EMPU2RP_POS (2U) +#define MPU_ERGRP_EMPU2RP (0x00000004UL) +#define MPU_ERGRP_EMPU3RP_POS (3U) +#define MPU_ERGRP_EMPU3RP (0x00000008UL) +#define MPU_ERGRP_EMPU4RP_POS (4U) +#define MPU_ERGRP_EMPU4RP (0x00000010UL) +#define MPU_ERGRP_EMPU5RP_POS (5U) +#define MPU_ERGRP_EMPU5RP (0x00000020UL) +#define MPU_ERGRP_EMPU6RP_POS (6U) +#define MPU_ERGRP_EMPU6RP (0x00000040UL) +#define MPU_ERGRP_EMPU7RP_POS (7U) +#define MPU_ERGRP_EMPU7RP (0x00000080UL) + +/* Bit definition for MPU_ECR register */ +#define MPU_ECR_EMPUBRP_POS (0U) +#define MPU_ECR_EMPUBRP (0x00000001UL) +#define MPU_ECR_EMPUBWP_POS (1U) +#define MPU_ECR_EMPUBWP (0x00000002UL) +#define MPU_ECR_EMPUACT_POS (2U) +#define MPU_ECR_EMPUACT (0x0000000CUL) +#define MPU_ECR_EMPUACT_0 (0x00000004UL) +#define MPU_ECR_EMPUACT_1 (0x00000008UL) +#define MPU_ECR_EMPUE_POS (7U) +#define MPU_ECR_EMPUE (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral NFC +*******************************************************************************/ +/* Bit definition for NFC_DATR_BASE register */ +#define NFC_DATR_BASE (0xFFFFFFFFUL) + +/* Bit definition for NFC_CMDR register */ +#define NFC_CMDR_CMD_POS (0U) +#define NFC_CMDR_CMD (0x000000FFUL) +#define NFC_CMDR_ARG_POS (8U) +#define NFC_CMDR_ARG (0xFFFFFF00UL) + +/* Bit definition for NFC_IDXR0 register */ +#define NFC_IDXR0 (0xFFFFFFFFUL) + +/* Bit definition for NFC_IENR register */ +#define NFC_IENR_ECCEUEN_POS (0U) +#define NFC_IENR_ECCEUEN (0x00000001UL) +#define NFC_IENR_ECCECEN_POS (1U) +#define NFC_IENR_ECCECEN (0x00000002UL) +#define NFC_IENR_ECCCEN_POS (4U) +#define NFC_IENR_ECCCEN (0x00000010UL) +#define NFC_IENR_ECCEEN_POS (6U) +#define NFC_IENR_ECCEEN (0x00000040UL) +#define NFC_IENR_ECCDIS_POS (7U) +#define NFC_IENR_ECCDIS (0x00000080UL) +#define NFC_IENR_RBEN_POS (8U) +#define NFC_IENR_RBEN (0x0000FF00UL) +#define NFC_IENR_RBEN_0 (0x00000100UL) +#define NFC_IENR_RBEN_1 (0x00000200UL) +#define NFC_IENR_RBEN_2 (0x00000400UL) +#define NFC_IENR_RBEN_3 (0x00000800UL) +#define NFC_IENR_RBEN_4 (0x00001000UL) +#define NFC_IENR_RBEN_5 (0x00002000UL) +#define NFC_IENR_RBEN_6 (0x00004000UL) +#define NFC_IENR_RBEN_7 (0x00008000UL) +#define NFC_IENR_RESV_POS (31U) +#define NFC_IENR_RESV (0x80000000UL) + +/* Bit definition for NFC_ISTR register */ +#define NFC_ISTR_ECCEUST_POS (0U) +#define NFC_ISTR_ECCEUST (0x00000001UL) +#define NFC_ISTR_ECCECST_POS (1U) +#define NFC_ISTR_ECCECST (0x00000002UL) +#define NFC_ISTR_ECCCST_POS (4U) +#define NFC_ISTR_ECCCST (0x00000010UL) +#define NFC_ISTR_ECCEST_POS (6U) +#define NFC_ISTR_ECCEST (0x00000040UL) +#define NFC_ISTR_RBST_POS (8U) +#define NFC_ISTR_RBST (0x0000FF00UL) +#define NFC_ISTR_RBST_0 (0x00000100UL) +#define NFC_ISTR_RBST_1 (0x00000200UL) +#define NFC_ISTR_RBST_2 (0x00000400UL) +#define NFC_ISTR_RBST_3 (0x00000800UL) +#define NFC_ISTR_RBST_4 (0x00001000UL) +#define NFC_ISTR_RBST_5 (0x00002000UL) +#define NFC_ISTR_RBST_6 (0x00004000UL) +#define NFC_ISTR_RBST_7 (0x00008000UL) +#define NFC_ISTR_RESV_POS (31U) +#define NFC_ISTR_RESV (0x80000000UL) + +/* Bit definition for NFC_IRSR register */ +#define NFC_IRSR_ECCEURS_POS (0U) +#define NFC_IRSR_ECCEURS (0x00000001UL) +#define NFC_IRSR_ECCECRS_POS (1U) +#define NFC_IRSR_ECCECRS (0x00000002UL) +#define NFC_IRSR_ECCCRS_POS (4U) +#define NFC_IRSR_ECCCRS (0x00000010UL) +#define NFC_IRSR_ECCERS_POS (6U) +#define NFC_IRSR_ECCERS (0x00000040UL) +#define NFC_IRSR_RBRS_POS (8U) +#define NFC_IRSR_RBRS (0x0000FF00UL) +#define NFC_IRSR_RBRS_0 (0x00000100UL) +#define NFC_IRSR_RBRS_1 (0x00000200UL) +#define NFC_IRSR_RBRS_2 (0x00000400UL) +#define NFC_IRSR_RBRS_3 (0x00000800UL) +#define NFC_IRSR_RBRS_4 (0x00001000UL) +#define NFC_IRSR_RBRS_5 (0x00002000UL) +#define NFC_IRSR_RBRS_6 (0x00004000UL) +#define NFC_IRSR_RBRS_7 (0x00008000UL) +#define NFC_IRSR_RESV_POS (31U) +#define NFC_IRSR_RESV (0x80000000UL) + +/* Bit definition for NFC_IDXR1 register */ +#define NFC_IDXR1_IDX1_POS (0U) +#define NFC_IDXR1_IDX1 (0x000000FFUL) +#define NFC_IDXR1_RESV_POS (8U) +#define NFC_IDXR1_RESV (0xFFFFFF00UL) + +/* Bit definition for NFC_TMCR0 register */ +#define NFC_TMCR0_TS_POS (0U) +#define NFC_TMCR0_TS (0x000000FFUL) +#define NFC_TMCR0_TS_0 (0x00000001UL) +#define NFC_TMCR0_TS_1 (0x00000002UL) +#define NFC_TMCR0_TS_2 (0x00000004UL) +#define NFC_TMCR0_TS_3 (0x00000008UL) +#define NFC_TMCR0_TS_4 (0x00000010UL) +#define NFC_TMCR0_TS_5 (0x00000020UL) +#define NFC_TMCR0_TS_6 (0x00000040UL) +#define NFC_TMCR0_TS_7 (0x00000080UL) +#define NFC_TMCR0_TWP_POS (8U) +#define NFC_TMCR0_TWP (0x0000FF00UL) +#define NFC_TMCR0_TWP_0 (0x00000100UL) +#define NFC_TMCR0_TWP_1 (0x00000200UL) +#define NFC_TMCR0_TWP_2 (0x00000400UL) +#define NFC_TMCR0_TWP_3 (0x00000800UL) +#define NFC_TMCR0_TWP_4 (0x00001000UL) +#define NFC_TMCR0_TWP_5 (0x00002000UL) +#define NFC_TMCR0_TWP_6 (0x00004000UL) +#define NFC_TMCR0_TWP_7 (0x00008000UL) +#define NFC_TMCR0_TRP_POS (16U) +#define NFC_TMCR0_TRP (0x00FF0000UL) +#define NFC_TMCR0_TRP_0 (0x00010000UL) +#define NFC_TMCR0_TRP_1 (0x00020000UL) +#define NFC_TMCR0_TRP_2 (0x00040000UL) +#define NFC_TMCR0_TRP_3 (0x00080000UL) +#define NFC_TMCR0_TRP_4 (0x00100000UL) +#define NFC_TMCR0_TRP_5 (0x00200000UL) +#define NFC_TMCR0_TRP_6 (0x00400000UL) +#define NFC_TMCR0_TRP_7 (0x00800000UL) +#define NFC_TMCR0_TH_POS (24U) +#define NFC_TMCR0_TH (0xFF000000UL) +#define NFC_TMCR0_TH_0 (0x01000000UL) +#define NFC_TMCR0_TH_1 (0x02000000UL) +#define NFC_TMCR0_TH_2 (0x04000000UL) +#define NFC_TMCR0_TH_3 (0x08000000UL) +#define NFC_TMCR0_TH_4 (0x10000000UL) +#define NFC_TMCR0_TH_5 (0x20000000UL) +#define NFC_TMCR0_TH_6 (0x40000000UL) +#define NFC_TMCR0_TH_7 (0x80000000UL) + +/* Bit definition for NFC_TMCR1 register */ +#define NFC_TMCR1_TWH_POS (0U) +#define NFC_TMCR1_TWH (0x000000FFUL) +#define NFC_TMCR1_TRH_POS (8U) +#define NFC_TMCR1_TRH (0x0000FF00UL) +#define NFC_TMCR1_TRR_POS (16U) +#define NFC_TMCR1_TRR (0x00FF0000UL) +#define NFC_TMCR1_TWB_POS (24U) +#define NFC_TMCR1_TWB (0xFF000000UL) + +/* Bit definition for NFC_BACR register */ +#define NFC_BACR_SIZE_POS (0U) +#define NFC_BACR_SIZE (0x00000007UL) +#define NFC_BACR_SIZE_0 (0x00000001UL) +#define NFC_BACR_SIZE_1 (0x00000002UL) +#define NFC_BACR_SIZE_2 (0x00000004UL) +#define NFC_BACR_B16BIT_POS (3U) +#define NFC_BACR_B16BIT (0x00000008UL) +#define NFC_BACR_BANK_POS (6U) +#define NFC_BACR_BANK (0x000000C0UL) +#define NFC_BACR_BANK_0 (0x00000040UL) +#define NFC_BACR_BANK_1 (0x00000080UL) +#define NFC_BACR_PAGE_POS (8U) +#define NFC_BACR_PAGE (0x00000300UL) +#define NFC_BACR_PAGE_0 (0x00000100UL) +#define NFC_BACR_PAGE_1 (0x00000200UL) +#define NFC_BACR_WP_POS (10U) +#define NFC_BACR_WP (0x00000400UL) +#define NFC_BACR_ECCM_POS (11U) +#define NFC_BACR_ECCM (0x00001800UL) +#define NFC_BACR_ECCM_0 (0x00000800UL) +#define NFC_BACR_ECCM_1 (0x00001000UL) +#define NFC_BACR_RAC_POS (13U) +#define NFC_BACR_RAC (0x00002000UL) +#define NFC_BACR_SCS_POS (16U) +#define NFC_BACR_SCS (0x00FF0000UL) +#define NFC_BACR_SCS_0 (0x00010000UL) +#define NFC_BACR_SCS_1 (0x00020000UL) +#define NFC_BACR_SCS_2 (0x00040000UL) +#define NFC_BACR_SCS_3 (0x00080000UL) +#define NFC_BACR_SCS_4 (0x00100000UL) +#define NFC_BACR_SCS_5 (0x00200000UL) +#define NFC_BACR_SCS_6 (0x00400000UL) +#define NFC_BACR_SCS_7 (0x00800000UL) + +/* Bit definition for NFC_TMCR2 register */ +#define NFC_TMCR2_TCCS_POS (0U) +#define NFC_TMCR2_TCCS (0x000000FFUL) +#define NFC_TMCR2_TWTR_POS (8U) +#define NFC_TMCR2_TWTR (0x0000FF00UL) +#define NFC_TMCR2_TRTW_POS (16U) +#define NFC_TMCR2_TRTW (0x00FF0000UL) +#define NFC_TMCR2_TADL_POS (24U) +#define NFC_TMCR2_TADL (0xFF000000UL) + +/* Bit definition for NFC_ECCR register */ +#define NFC_ECCR_ERRLOC_POS (0U) +#define NFC_ECCR_ERRLOC (0x00000FFFUL) +#define NFC_ECCR_SE_POS (12U) +#define NFC_ECCR_SE (0x00001000UL) +#define NFC_ECCR_ME_POS (13U) +#define NFC_ECCR_ME (0x00002000UL) + +/* Bit definition for NFC_ECC_STAT register */ +#define NFC_ECC_STAT_ERRSEC_POS (0U) +#define NFC_ECC_STAT_ERRSEC (0x0000FFFFUL) +#define NFC_ECC_STAT_ERRSEC_0 (0x00000001UL) +#define NFC_ECC_STAT_ERRSEC_1 (0x00000002UL) +#define NFC_ECC_STAT_ERRSEC_2 (0x00000004UL) +#define NFC_ECC_STAT_ERRSEC_3 (0x00000008UL) +#define NFC_ECC_STAT_ERRSEC_4 (0x00000010UL) +#define NFC_ECC_STAT_ERRSEC_5 (0x00000020UL) +#define NFC_ECC_STAT_ERRSEC_6 (0x00000040UL) +#define NFC_ECC_STAT_ERRSEC_7 (0x00000080UL) +#define NFC_ECC_STAT_ERRSEC_8 (0x00000100UL) +#define NFC_ECC_STAT_ERRSEC_9 (0x00000200UL) +#define NFC_ECC_STAT_ERRSEC_10 (0x00000400UL) +#define NFC_ECC_STAT_ERRSEC_11 (0x00000800UL) +#define NFC_ECC_STAT_ERRSEC_12 (0x00001000UL) +#define NFC_ECC_STAT_ERRSEC_13 (0x00002000UL) +#define NFC_ECC_STAT_ERRSEC_14 (0x00004000UL) +#define NFC_ECC_STAT_ERRSEC_15 (0x00008000UL) +#define NFC_ECC_STAT_RESV_POS (16U) +#define NFC_ECC_STAT_RESV (0xFFFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_0 register */ +#define NFC_ECC_SYND0_0_S1_POS (0U) +#define NFC_ECC_SYND0_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND0_0_S2_POS (16U) +#define NFC_ECC_SYND0_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_1 register */ +#define NFC_ECC_SYND0_1_S3_POS (0U) +#define NFC_ECC_SYND0_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND0_1_S4_POS (16U) +#define NFC_ECC_SYND0_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_2 register */ +#define NFC_ECC_SYND0_2_S5_POS (0U) +#define NFC_ECC_SYND0_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND0_2_S6_POS (16U) +#define NFC_ECC_SYND0_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND0_3 register */ +#define NFC_ECC_SYND0_3_S7_POS (0U) +#define NFC_ECC_SYND0_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND0_3_S8_POS (16U) +#define NFC_ECC_SYND0_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_0 register */ +#define NFC_ECC_SYND1_0_S1_POS (0U) +#define NFC_ECC_SYND1_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND1_0_S2_POS (16U) +#define NFC_ECC_SYND1_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_1 register */ +#define NFC_ECC_SYND1_1_S3_POS (0U) +#define NFC_ECC_SYND1_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND1_1_S4_POS (16U) +#define NFC_ECC_SYND1_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_2 register */ +#define NFC_ECC_SYND1_2_S5_POS (0U) +#define NFC_ECC_SYND1_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND1_2_S6_POS (16U) +#define NFC_ECC_SYND1_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND1_3 register */ +#define NFC_ECC_SYND1_3_S7_POS (0U) +#define NFC_ECC_SYND1_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND1_3_S8_POS (16U) +#define NFC_ECC_SYND1_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_0 register */ +#define NFC_ECC_SYND2_0_S1_POS (0U) +#define NFC_ECC_SYND2_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND2_0_S2_POS (16U) +#define NFC_ECC_SYND2_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_1 register */ +#define NFC_ECC_SYND2_1_S3_POS (0U) +#define NFC_ECC_SYND2_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND2_1_S4_POS (16U) +#define NFC_ECC_SYND2_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_2 register */ +#define NFC_ECC_SYND2_2_S5_POS (0U) +#define NFC_ECC_SYND2_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND2_2_S6_POS (16U) +#define NFC_ECC_SYND2_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND2_3 register */ +#define NFC_ECC_SYND2_3_S7_POS (0U) +#define NFC_ECC_SYND2_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND2_3_S8_POS (16U) +#define NFC_ECC_SYND2_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_0 register */ +#define NFC_ECC_SYND3_0_S1_POS (0U) +#define NFC_ECC_SYND3_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND3_0_S2_POS (16U) +#define NFC_ECC_SYND3_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_1 register */ +#define NFC_ECC_SYND3_1_S3_POS (0U) +#define NFC_ECC_SYND3_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND3_1_S4_POS (16U) +#define NFC_ECC_SYND3_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_2 register */ +#define NFC_ECC_SYND3_2_S5_POS (0U) +#define NFC_ECC_SYND3_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND3_2_S6_POS (16U) +#define NFC_ECC_SYND3_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND3_3 register */ +#define NFC_ECC_SYND3_3_S7_POS (0U) +#define NFC_ECC_SYND3_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND3_3_S8_POS (16U) +#define NFC_ECC_SYND3_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_0 register */ +#define NFC_ECC_SYND4_0_S1_POS (0U) +#define NFC_ECC_SYND4_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND4_0_S2_POS (16U) +#define NFC_ECC_SYND4_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_1 register */ +#define NFC_ECC_SYND4_1_S3_POS (0U) +#define NFC_ECC_SYND4_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND4_1_S4_POS (16U) +#define NFC_ECC_SYND4_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_2 register */ +#define NFC_ECC_SYND4_2_S5_POS (0U) +#define NFC_ECC_SYND4_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND4_2_S6_POS (16U) +#define NFC_ECC_SYND4_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND4_3 register */ +#define NFC_ECC_SYND4_3_S7_POS (0U) +#define NFC_ECC_SYND4_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND4_3_S8_POS (16U) +#define NFC_ECC_SYND4_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_0 register */ +#define NFC_ECC_SYND5_0_S1_POS (0U) +#define NFC_ECC_SYND5_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND5_0_S2_POS (16U) +#define NFC_ECC_SYND5_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_1 register */ +#define NFC_ECC_SYND5_1_S3_POS (0U) +#define NFC_ECC_SYND5_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND5_1_S4_POS (16U) +#define NFC_ECC_SYND5_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_2 register */ +#define NFC_ECC_SYND5_2_S5_POS (0U) +#define NFC_ECC_SYND5_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND5_2_S6_POS (16U) +#define NFC_ECC_SYND5_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND5_3 register */ +#define NFC_ECC_SYND5_3_S7_POS (0U) +#define NFC_ECC_SYND5_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND5_3_S8_POS (16U) +#define NFC_ECC_SYND5_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND6_0 register */ +#define NFC_ECC_SYND6_0_S1_POS (0U) +#define NFC_ECC_SYND6_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND6_0_S2_POS (16U) +#define NFC_ECC_SYND6_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND6_1 register */ +#define NFC_ECC_SYND6_1_S3_POS (0U) +#define NFC_ECC_SYND6_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND6_1_S3_0 (0x00000001UL) +#define NFC_ECC_SYND6_1_S3_1 (0x00000002UL) +#define NFC_ECC_SYND6_1_S3_2 (0x00000004UL) +#define NFC_ECC_SYND6_1_S3_3 (0x00000008UL) +#define NFC_ECC_SYND6_1_S3_4 (0x00000010UL) +#define NFC_ECC_SYND6_1_S3_5 (0x00000020UL) +#define NFC_ECC_SYND6_1_S3_6 (0x00000040UL) +#define NFC_ECC_SYND6_1_S3_7 (0x00000080UL) +#define NFC_ECC_SYND6_1_S3_8 (0x00000100UL) +#define NFC_ECC_SYND6_1_S3_9 (0x00000200UL) +#define NFC_ECC_SYND6_1_S3_10 (0x00000400UL) +#define NFC_ECC_SYND6_1_S3_11 (0x00000800UL) +#define NFC_ECC_SYND6_1_S3_12 (0x00001000UL) +#define NFC_ECC_SYND6_1_S4_POS (16U) +#define NFC_ECC_SYND6_1_S4 (0x1FFF0000UL) +#define NFC_ECC_SYND6_1_S4_0 (0x00010000UL) +#define NFC_ECC_SYND6_1_S4_1 (0x00020000UL) +#define NFC_ECC_SYND6_1_S4_2 (0x00040000UL) +#define NFC_ECC_SYND6_1_S4_3 (0x00080000UL) +#define NFC_ECC_SYND6_1_S4_4 (0x00100000UL) +#define NFC_ECC_SYND6_1_S4_5 (0x00200000UL) +#define NFC_ECC_SYND6_1_S4_6 (0x00400000UL) +#define NFC_ECC_SYND6_1_S4_7 (0x00800000UL) +#define NFC_ECC_SYND6_1_S4_8 (0x01000000UL) +#define NFC_ECC_SYND6_1_S4_9 (0x02000000UL) +#define NFC_ECC_SYND6_1_S4_10 (0x04000000UL) +#define NFC_ECC_SYND6_1_S4_11 (0x08000000UL) +#define NFC_ECC_SYND6_1_S4_12 (0x10000000UL) +#define NFC_ECC_SYND6_1_RESV_POS (31U) +#define NFC_ECC_SYND6_1_RESV (0x80000000UL) + +/* Bit definition for NFC_ECC_SYND6_2 register */ +#define NFC_ECC_SYND6_2_S5_POS (0U) +#define NFC_ECC_SYND6_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND6_2_S6_POS (16U) +#define NFC_ECC_SYND6_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND6_3 register */ +#define NFC_ECC_SYND6_3_S7_POS (0U) +#define NFC_ECC_SYND6_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND6_3_S8_POS (16U) +#define NFC_ECC_SYND6_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_0 register */ +#define NFC_ECC_SYND7_0_S1_POS (0U) +#define NFC_ECC_SYND7_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND7_0_S2_POS (16U) +#define NFC_ECC_SYND7_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_1 register */ +#define NFC_ECC_SYND7_1_S3_POS (0U) +#define NFC_ECC_SYND7_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND7_1_S4_POS (16U) +#define NFC_ECC_SYND7_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_2 register */ +#define NFC_ECC_SYND7_2_S5_POS (0U) +#define NFC_ECC_SYND7_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND7_2_S6_POS (16U) +#define NFC_ECC_SYND7_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND7_3 register */ +#define NFC_ECC_SYND7_3_S7_POS (0U) +#define NFC_ECC_SYND7_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND7_3_S8_POS (16U) +#define NFC_ECC_SYND7_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_0 register */ +#define NFC_ECC_SYND8_0_S1_POS (0U) +#define NFC_ECC_SYND8_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND8_0_S2_POS (16U) +#define NFC_ECC_SYND8_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_1 register */ +#define NFC_ECC_SYND8_1_S3_POS (0U) +#define NFC_ECC_SYND8_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND8_1_S4_POS (16U) +#define NFC_ECC_SYND8_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_2 register */ +#define NFC_ECC_SYND8_2_S5_POS (0U) +#define NFC_ECC_SYND8_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND8_2_S6_POS (16U) +#define NFC_ECC_SYND8_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND8_3 register */ +#define NFC_ECC_SYND8_3_S7_POS (0U) +#define NFC_ECC_SYND8_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND8_3_S8_POS (16U) +#define NFC_ECC_SYND8_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_0 register */ +#define NFC_ECC_SYND9_0_S1_POS (0U) +#define NFC_ECC_SYND9_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND9_0_S2_POS (16U) +#define NFC_ECC_SYND9_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_1 register */ +#define NFC_ECC_SYND9_1_S3_POS (0U) +#define NFC_ECC_SYND9_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND9_1_S4_POS (16U) +#define NFC_ECC_SYND9_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_2 register */ +#define NFC_ECC_SYND9_2_S5_POS (0U) +#define NFC_ECC_SYND9_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND9_2_S6_POS (16U) +#define NFC_ECC_SYND9_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND9_3 register */ +#define NFC_ECC_SYND9_3_S7_POS (0U) +#define NFC_ECC_SYND9_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND9_3_S8_POS (16U) +#define NFC_ECC_SYND9_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_0 register */ +#define NFC_ECC_SYND10_0_S1_POS (0U) +#define NFC_ECC_SYND10_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND10_0_S2_POS (16U) +#define NFC_ECC_SYND10_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_1 register */ +#define NFC_ECC_SYND10_1_S3_POS (0U) +#define NFC_ECC_SYND10_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND10_1_S4_POS (16U) +#define NFC_ECC_SYND10_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_2 register */ +#define NFC_ECC_SYND10_2_S5_POS (0U) +#define NFC_ECC_SYND10_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND10_2_S6_POS (16U) +#define NFC_ECC_SYND10_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND10_3 register */ +#define NFC_ECC_SYND10_3_S7_POS (0U) +#define NFC_ECC_SYND10_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND10_3_S8_POS (16U) +#define NFC_ECC_SYND10_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_0 register */ +#define NFC_ECC_SYND11_0_S1_POS (0U) +#define NFC_ECC_SYND11_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND11_0_S2_POS (16U) +#define NFC_ECC_SYND11_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_1 register */ +#define NFC_ECC_SYND11_1_S3_POS (0U) +#define NFC_ECC_SYND11_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND11_1_S4_POS (16U) +#define NFC_ECC_SYND11_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_2 register */ +#define NFC_ECC_SYND11_2_S5_POS (0U) +#define NFC_ECC_SYND11_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND11_2_S6_POS (16U) +#define NFC_ECC_SYND11_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND11_3 register */ +#define NFC_ECC_SYND11_3_S7_POS (0U) +#define NFC_ECC_SYND11_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND11_3_S8_POS (16U) +#define NFC_ECC_SYND11_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_0 register */ +#define NFC_ECC_SYND12_0_S1_POS (0U) +#define NFC_ECC_SYND12_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND12_0_S2_POS (16U) +#define NFC_ECC_SYND12_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_1 register */ +#define NFC_ECC_SYND12_1_S3_POS (0U) +#define NFC_ECC_SYND12_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND12_1_S4_POS (16U) +#define NFC_ECC_SYND12_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_2 register */ +#define NFC_ECC_SYND12_2_S5_POS (0U) +#define NFC_ECC_SYND12_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND12_2_S6_POS (16U) +#define NFC_ECC_SYND12_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND12_3 register */ +#define NFC_ECC_SYND12_3_S7_POS (0U) +#define NFC_ECC_SYND12_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND12_3_S8_POS (16U) +#define NFC_ECC_SYND12_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_0 register */ +#define NFC_ECC_SYND13_0_S1_POS (0U) +#define NFC_ECC_SYND13_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND13_0_S2_POS (16U) +#define NFC_ECC_SYND13_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_1 register */ +#define NFC_ECC_SYND13_1_S3_POS (0U) +#define NFC_ECC_SYND13_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND13_1_S4_POS (16U) +#define NFC_ECC_SYND13_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_2 register */ +#define NFC_ECC_SYND13_2_S5_POS (0U) +#define NFC_ECC_SYND13_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND13_2_S6_POS (16U) +#define NFC_ECC_SYND13_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND13_3 register */ +#define NFC_ECC_SYND13_3_S7_POS (0U) +#define NFC_ECC_SYND13_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND13_3_S8_POS (16U) +#define NFC_ECC_SYND13_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_0 register */ +#define NFC_ECC_SYND14_0_S1_POS (0U) +#define NFC_ECC_SYND14_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND14_0_S2_POS (16U) +#define NFC_ECC_SYND14_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_1 register */ +#define NFC_ECC_SYND14_1_S3_POS (0U) +#define NFC_ECC_SYND14_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND14_1_S4_POS (16U) +#define NFC_ECC_SYND14_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_2 register */ +#define NFC_ECC_SYND14_2_S5_POS (0U) +#define NFC_ECC_SYND14_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND14_2_S6_POS (16U) +#define NFC_ECC_SYND14_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND14_3 register */ +#define NFC_ECC_SYND14_3_S7_POS (0U) +#define NFC_ECC_SYND14_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND14_3_S8_POS (16U) +#define NFC_ECC_SYND14_3_S8 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_0 register */ +#define NFC_ECC_SYND15_0_S1_POS (0U) +#define NFC_ECC_SYND15_0_S1 (0x00001FFFUL) +#define NFC_ECC_SYND15_0_S2_POS (16U) +#define NFC_ECC_SYND15_0_S2 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_1 register */ +#define NFC_ECC_SYND15_1_S3_POS (0U) +#define NFC_ECC_SYND15_1_S3 (0x00001FFFUL) +#define NFC_ECC_SYND15_1_S4_POS (16U) +#define NFC_ECC_SYND15_1_S4 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_2 register */ +#define NFC_ECC_SYND15_2_S5_POS (0U) +#define NFC_ECC_SYND15_2_S5 (0x00001FFFUL) +#define NFC_ECC_SYND15_2_S6_POS (16U) +#define NFC_ECC_SYND15_2_S6 (0x1FFF0000UL) + +/* Bit definition for NFC_ECC_SYND15_3 register */ +#define NFC_ECC_SYND15_3_S7_POS (0U) +#define NFC_ECC_SYND15_3_S7 (0x00001FFFUL) +#define NFC_ECC_SYND15_3_S8_POS (16U) +#define NFC_ECC_SYND15_3_S8 (0x1FFF0000UL) + +/******************************************************************************* + Bit definition for Peripheral OTS +*******************************************************************************/ +/* Bit definition for OTS_CTL register */ +#define OTS_CTL_OTSST_POS (0U) +#define OTS_CTL_OTSST (0x0001U) +#define OTS_CTL_OTSCK_POS (1U) +#define OTS_CTL_OTSCK (0x0002U) +#define OTS_CTL_OTSIE_POS (2U) +#define OTS_CTL_OTSIE (0x0004U) +#define OTS_CTL_TSSTP_POS (3U) +#define OTS_CTL_TSSTP (0x0008U) + +/* Bit definition for OTS_DR1 register */ +#define OTS_DR1 (0xFFFFU) + +/* Bit definition for OTS_DR2 register */ +#define OTS_DR2 (0xFFFFU) + +/* Bit definition for OTS_ECR register */ +#define OTS_ECR (0xFFFFU) + +/* Bit definition for OTS_LPR register */ +#define OTS_LPR_TSOFS_POS (0U) +#define OTS_LPR_TSOFS (0x000000FFUL) +#define OTS_LPR_TSOFS_0 (0x00000001UL) +#define OTS_LPR_TSOFS_1 (0x00000002UL) +#define OTS_LPR_TSOFS_2 (0x00000004UL) +#define OTS_LPR_TSOFS_3 (0x00000008UL) +#define OTS_LPR_TSOFS_4 (0x00000010UL) +#define OTS_LPR_TSOFS_5 (0x00000020UL) +#define OTS_LPR_TSOFS_6 (0x00000040UL) +#define OTS_LPR_TSOFS_7 (0x00000080UL) +#define OTS_LPR_TSSLP_POS (8U) +#define OTS_LPR_TSSLP (0xFFFFFF00UL) +#define OTS_LPR_TSSLP_0 (0x00000100UL) +#define OTS_LPR_TSSLP_1 (0x00000200UL) +#define OTS_LPR_TSSLP_2 (0x00000400UL) +#define OTS_LPR_TSSLP_3 (0x00000800UL) +#define OTS_LPR_TSSLP_4 (0x00001000UL) +#define OTS_LPR_TSSLP_5 (0x00002000UL) +#define OTS_LPR_TSSLP_6 (0x00004000UL) +#define OTS_LPR_TSSLP_7 (0x00008000UL) +#define OTS_LPR_TSSLP_8 (0x00010000UL) +#define OTS_LPR_TSSLP_9 (0x00020000UL) +#define OTS_LPR_TSSLP_10 (0x00040000UL) +#define OTS_LPR_TSSLP_11 (0x00080000UL) +#define OTS_LPR_TSSLP_12 (0x00100000UL) +#define OTS_LPR_TSSLP_13 (0x00200000UL) +#define OTS_LPR_TSSLP_14 (0x00400000UL) +#define OTS_LPR_TSSLP_15 (0x00800000UL) +#define OTS_LPR_TSSLP_16 (0x01000000UL) +#define OTS_LPR_TSSLP_17 (0x02000000UL) +#define OTS_LPR_TSSLP_18 (0x04000000UL) +#define OTS_LPR_TSSLP_19 (0x08000000UL) +#define OTS_LPR_TSSLP_20 (0x10000000UL) +#define OTS_LPR_TSSLP_21 (0x20000000UL) +#define OTS_LPR_TSSLP_22 (0x40000000UL) +#define OTS_LPR_TSSLP_23 (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral PERIC +*******************************************************************************/ +/* Bit definition for PERIC_USB_SYCTLREG register */ +#define PERIC_USB_SYCTLREG_USBFS_DFB_POS (0U) +#define PERIC_USB_SYCTLREG_USBFS_DFB (0x00000001UL) +#define PERIC_USB_SYCTLREG_USBFS_SOFEN_POS (1U) +#define PERIC_USB_SYCTLREG_USBFS_SOFEN (0x00000002UL) +#define PERIC_USB_SYCTLREG_USBHS_DFB_POS (8U) +#define PERIC_USB_SYCTLREG_USBHS_DFB (0x00000100UL) +#define PERIC_USB_SYCTLREG_USBHS_SOFEN_POS (9U) +#define PERIC_USB_SYCTLREG_USBHS_SOFEN (0x00000200UL) +#define PERIC_USB_SYCTLREG_USBHS_FSPHYE_POS (10U) +#define PERIC_USB_SYCTLREG_USBHS_FSPHYE (0x00000400UL) +#define PERIC_USB_SYCTLREG_USBFS_NFS_POS (16U) +#define PERIC_USB_SYCTLREG_USBFS_NFS (0x00030000UL) +#define PERIC_USB_SYCTLREG_USBFS_NFS_0 (0x00010000UL) +#define PERIC_USB_SYCTLREG_USBFS_NFS_1 (0x00020000UL) +#define PERIC_USB_SYCTLREG_USBFS_NFE_POS (18U) +#define PERIC_USB_SYCTLREG_USBFS_NFE (0x00040000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFS_POS (24U) +#define PERIC_USB_SYCTLREG_USBHS_NFS (0x03000000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFS_0 (0x01000000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFS_1 (0x02000000UL) +#define PERIC_USB_SYCTLREG_USBHS_NFE_POS (26U) +#define PERIC_USB_SYCTLREG_USBHS_NFE (0x04000000UL) + +/* Bit definition for PERIC_SDIOC_SYCTLREG register */ +#define PERIC_SDIOC_SYCTLREG_SELMMC1_POS (1U) +#define PERIC_SDIOC_SYCTLREG_SELMMC1 (0x00000002UL) +#define PERIC_SDIOC_SYCTLREG_SELMMC2_POS (3U) +#define PERIC_SDIOC_SYCTLREG_SELMMC2 (0x00000008UL) + +/* Bit definition for PERIC_NFC_SYCTLREG register */ +#define PERIC_NFC_SYCTLREG_OPO (0x00000001UL) + +/* Bit definition for PERIC_EXMC_ENAR register */ +#define PERIC_EXMC_ENAR_DMCEN_POS (0U) +#define PERIC_EXMC_ENAR_DMCEN (0x00000001UL) +#define PERIC_EXMC_ENAR_SMCEN_POS (1U) +#define PERIC_EXMC_ENAR_SMCEN (0x00000002UL) +#define PERIC_EXMC_ENAR_NFCEN_POS (2U) +#define PERIC_EXMC_ENAR_NFCEN (0x00000004UL) + +/* Bit definition for PERIC_CAN_SYCTLREG register */ +#define PERIC_CAN_SYCTLREG_CAN1FDE_POS (0U) +#define PERIC_CAN_SYCTLREG_CAN1FDE (0x00000001UL) +#define PERIC_CAN_SYCTLREG_CAN2FDE_POS (1U) +#define PERIC_CAN_SYCTLREG_CAN2FDE (0x00000002UL) + +/* Bit definition for PERIC_USART1_NFC register */ +#define PERIC_USART1_NFC_NFS_POS (0U) +#define PERIC_USART1_NFC_NFS (0x00000003UL) +#define PERIC_USART1_NFC_NFS_0 (0x00000001UL) +#define PERIC_USART1_NFC_NFS_1 (0x00000002UL) +#define PERIC_USART1_NFC_NFE_POS (2U) +#define PERIC_USART1_NFC_NFE (0x00000004UL) + +/* Bit definition for PERIC_NFC_SYSTATREG register */ +#define PERIC_NFC_SYSTATREG_CHIPBUSY_POS (0U) +#define PERIC_NFC_SYSTATREG_CHIPBUSY (0x000000FFUL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_0 (0x00000001UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_1 (0x00000002UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_2 (0x00000004UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_3 (0x00000008UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_4 (0x00000010UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_5 (0x00000020UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_6 (0x00000040UL) +#define PERIC_NFC_SYSTATREG_CHIPBUSY_7 (0x00000080UL) +#define PERIC_NFC_SYSTATREG_PECC_POS (8U) +#define PERIC_NFC_SYSTATREG_PECC (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral PWC +*******************************************************************************/ +/* Bit definition for PWC_FCG0 register */ +#define PWC_FCG0_SRAMH_POS (0U) +#define PWC_FCG0_SRAMH (0x00000001UL) +#define PWC_FCG0_SRAM1_POS (4U) +#define PWC_FCG0_SRAM1 (0x00000010UL) +#define PWC_FCG0_SRAM2_POS (5U) +#define PWC_FCG0_SRAM2 (0x00000020UL) +#define PWC_FCG0_SRAM3_POS (6U) +#define PWC_FCG0_SRAM3 (0x00000040UL) +#define PWC_FCG0_SRAM4_POS (7U) +#define PWC_FCG0_SRAM4 (0x00000080UL) +#define PWC_FCG0_SRAMB_POS (10U) +#define PWC_FCG0_SRAMB (0x00000400UL) +#define PWC_FCG0_KEY_POS (13U) +#define PWC_FCG0_KEY (0x00002000UL) +#define PWC_FCG0_DMA1_POS (14U) +#define PWC_FCG0_DMA1 (0x00004000UL) +#define PWC_FCG0_DMA2_POS (15U) +#define PWC_FCG0_DMA2 (0x00008000UL) +#define PWC_FCG0_FCM_POS (16U) +#define PWC_FCG0_FCM (0x00010000UL) +#define PWC_FCG0_AOS_POS (17U) +#define PWC_FCG0_AOS (0x00020000UL) +#define PWC_FCG0_CTC_POS (18U) +#define PWC_FCG0_CTC (0x00040000UL) +#define PWC_FCG0_CORDIC_POS (19U) +#define PWC_FCG0_CORDIC (0x00080000UL) +#define PWC_FCG0_AES_POS (20U) +#define PWC_FCG0_AES (0x00100000UL) +#define PWC_FCG0_HASH_POS (21U) +#define PWC_FCG0_HASH (0x00200000UL) +#define PWC_FCG0_TRNG_POS (22U) +#define PWC_FCG0_TRNG (0x00400000UL) +#define PWC_FCG0_CRC_POS (23U) +#define PWC_FCG0_CRC (0x00800000UL) +#define PWC_FCG0_DCU1_POS (24U) +#define PWC_FCG0_DCU1 (0x01000000UL) +#define PWC_FCG0_DCU2_POS (25U) +#define PWC_FCG0_DCU2 (0x02000000UL) +#define PWC_FCG0_DCU3_POS (26U) +#define PWC_FCG0_DCU3 (0x04000000UL) +#define PWC_FCG0_DCU4_POS (27U) +#define PWC_FCG0_DCU4 (0x08000000UL) +#define PWC_FCG0_DCU5_POS (28U) +#define PWC_FCG0_DCU5 (0x10000000UL) +#define PWC_FCG0_DCU6_POS (29U) +#define PWC_FCG0_DCU6 (0x20000000UL) +#define PWC_FCG0_DCU7_POS (30U) +#define PWC_FCG0_DCU7 (0x40000000UL) +#define PWC_FCG0_DCU8_POS (31U) +#define PWC_FCG0_DCU8 (0x80000000UL) + +/* Bit definition for PWC_FCG1 register */ +#define PWC_FCG1_CAN1_POS (0U) +#define PWC_FCG1_CAN1 (0x00000001UL) +#define PWC_FCG1_CAN2_POS (1U) +#define PWC_FCG1_CAN2 (0x00000002UL) +#define PWC_FCG1_ETHER_POS (2U) +#define PWC_FCG1_ETHER (0x00000004UL) +#define PWC_FCG1_QSPI_POS (3U) +#define PWC_FCG1_QSPI (0x00000008UL) +#define PWC_FCG1_IIC1_POS (4U) +#define PWC_FCG1_IIC1 (0x00000010UL) +#define PWC_FCG1_IIC2_POS (5U) +#define PWC_FCG1_IIC2 (0x00000020UL) +#define PWC_FCG1_IIC3_POS (6U) +#define PWC_FCG1_IIC3 (0x00000040UL) +#define PWC_FCG1_IIC4_POS (7U) +#define PWC_FCG1_IIC4 (0x00000080UL) +#define PWC_FCG1_IIC5_POS (8U) +#define PWC_FCG1_IIC5 (0x00000100UL) +#define PWC_FCG1_IIC6_POS (9U) +#define PWC_FCG1_IIC6 (0x00000200UL) +#define PWC_FCG1_SDIOC1_POS (10U) +#define PWC_FCG1_SDIOC1 (0x00000400UL) +#define PWC_FCG1_SDIOC2_POS (11U) +#define PWC_FCG1_SDIOC2 (0x00000800UL) +#define PWC_FCG1_I2S1_POS (12U) +#define PWC_FCG1_I2S1 (0x00001000UL) +#define PWC_FCG1_I2S2_POS (13U) +#define PWC_FCG1_I2S2 (0x00002000UL) +#define PWC_FCG1_I2S3_POS (14U) +#define PWC_FCG1_I2S3 (0x00004000UL) +#define PWC_FCG1_I2S4_POS (15U) +#define PWC_FCG1_I2S4 (0x00008000UL) +#define PWC_FCG1_SPI1_POS (16U) +#define PWC_FCG1_SPI1 (0x00010000UL) +#define PWC_FCG1_SPI2_POS (17U) +#define PWC_FCG1_SPI2 (0x00020000UL) +#define PWC_FCG1_SPI3_POS (18U) +#define PWC_FCG1_SPI3 (0x00040000UL) +#define PWC_FCG1_SPI4_POS (19U) +#define PWC_FCG1_SPI4 (0x00080000UL) +#define PWC_FCG1_SPI5_POS (20U) +#define PWC_FCG1_SPI5 (0x00100000UL) +#define PWC_FCG1_SPI6_POS (21U) +#define PWC_FCG1_SPI6 (0x00200000UL) +#define PWC_FCG1_USBFS_POS (22U) +#define PWC_FCG1_USBFS (0x00400000UL) +#define PWC_FCG1_USBHS_POS (23U) +#define PWC_FCG1_USBHS (0x00800000UL) +#define PWC_FCG1_FMAC1_POS (24U) +#define PWC_FCG1_FMAC1 (0x01000000UL) +#define PWC_FCG1_FMAC2_POS (25U) +#define PWC_FCG1_FMAC2 (0x02000000UL) +#define PWC_FCG1_FMAC3_POS (26U) +#define PWC_FCG1_FMAC3 (0x04000000UL) +#define PWC_FCG1_FMAC4_POS (27U) +#define PWC_FCG1_FMAC4 (0x08000000UL) + +/* Bit definition for PWC_FCG2 register */ +#define PWC_FCG2_TMR6_1_POS (0U) +#define PWC_FCG2_TMR6_1 (0x00000001UL) +#define PWC_FCG2_TMR6_2_POS (1U) +#define PWC_FCG2_TMR6_2 (0x00000002UL) +#define PWC_FCG2_TMR6_3_POS (2U) +#define PWC_FCG2_TMR6_3 (0x00000004UL) +#define PWC_FCG2_TMR6_4_POS (3U) +#define PWC_FCG2_TMR6_4 (0x00000008UL) +#define PWC_FCG2_TMR6_5_POS (4U) +#define PWC_FCG2_TMR6_5 (0x00000010UL) +#define PWC_FCG2_TMR6_6_POS (5U) +#define PWC_FCG2_TMR6_6 (0x00000020UL) +#define PWC_FCG2_TMR6_7_POS (6U) +#define PWC_FCG2_TMR6_7 (0x00000040UL) +#define PWC_FCG2_TMR6_8_POS (7U) +#define PWC_FCG2_TMR6_8 (0x00000080UL) +#define PWC_FCG2_TMR4_1_POS (8U) +#define PWC_FCG2_TMR4_1 (0x00000100UL) +#define PWC_FCG2_TMR4_2_POS (9U) +#define PWC_FCG2_TMR4_2 (0x00000200UL) +#define PWC_FCG2_TMR4_3_POS (10U) +#define PWC_FCG2_TMR4_3 (0x00000400UL) +#define PWC_FCG2_HRPWM_POS (11U) +#define PWC_FCG2_HRPWM (0x00000800UL) +#define PWC_FCG2_TMR0_1_POS (12U) +#define PWC_FCG2_TMR0_1 (0x00001000UL) +#define PWC_FCG2_TMR0_2_POS (13U) +#define PWC_FCG2_TMR0_2 (0x00002000UL) +#define PWC_FCG2_EMB_POS (15U) +#define PWC_FCG2_EMB (0x00008000UL) +#define PWC_FCG2_TMR2_1_POS (16U) +#define PWC_FCG2_TMR2_1 (0x00010000UL) +#define PWC_FCG2_TMR2_2_POS (17U) +#define PWC_FCG2_TMR2_2 (0x00020000UL) +#define PWC_FCG2_TMR2_3_POS (18U) +#define PWC_FCG2_TMR2_3 (0x00040000UL) +#define PWC_FCG2_TMR2_4_POS (19U) +#define PWC_FCG2_TMR2_4 (0x00080000UL) +#define PWC_FCG2_TMRA_1_POS (20U) +#define PWC_FCG2_TMRA_1 (0x00100000UL) +#define PWC_FCG2_TMRA_2_POS (21U) +#define PWC_FCG2_TMRA_2 (0x00200000UL) +#define PWC_FCG2_TMRA_3_POS (22U) +#define PWC_FCG2_TMRA_3 (0x00400000UL) +#define PWC_FCG2_TMRA_4_POS (23U) +#define PWC_FCG2_TMRA_4 (0x00800000UL) +#define PWC_FCG2_TMRA_5_POS (24U) +#define PWC_FCG2_TMRA_5 (0x01000000UL) +#define PWC_FCG2_TMRA_6_POS (25U) +#define PWC_FCG2_TMRA_6 (0x02000000UL) +#define PWC_FCG2_TMRA_7_POS (26U) +#define PWC_FCG2_TMRA_7 (0x04000000UL) +#define PWC_FCG2_TMRA_8_POS (27U) +#define PWC_FCG2_TMRA_8 (0x08000000UL) +#define PWC_FCG2_TMRA_9_POS (28U) +#define PWC_FCG2_TMRA_9 (0x10000000UL) +#define PWC_FCG2_TMRA_10_POS (29U) +#define PWC_FCG2_TMRA_10 (0x20000000UL) +#define PWC_FCG2_TMRA_11_POS (30U) +#define PWC_FCG2_TMRA_11 (0x40000000UL) +#define PWC_FCG2_TMRA_12_POS (31U) +#define PWC_FCG2_TMRA_12 (0x80000000UL) + +/* Bit definition for PWC_FCG3 register */ +#define PWC_FCG3_ADC1_POS (0U) +#define PWC_FCG3_ADC1 (0x00000001UL) +#define PWC_FCG3_ADC2_POS (1U) +#define PWC_FCG3_ADC2 (0x00000002UL) +#define PWC_FCG3_ADC3_POS (2U) +#define PWC_FCG3_ADC3 (0x00000004UL) +#define PWC_FCG3_CMBIAS_POS (3U) +#define PWC_FCG3_CMBIAS (0x00000008UL) +#define PWC_FCG3_DAC1_POS (4U) +#define PWC_FCG3_DAC1 (0x00000010UL) +#define PWC_FCG3_DAC2_POS (5U) +#define PWC_FCG3_DAC2 (0x00000020UL) +#define PWC_FCG3_CMP1_POS (8U) +#define PWC_FCG3_CMP1 (0x00000100UL) +#define PWC_FCG3_CMP2_POS (9U) +#define PWC_FCG3_CMP2 (0x00000200UL) +#define PWC_FCG3_OTS_POS (12U) +#define PWC_FCG3_OTS (0x00001000UL) +#define PWC_FCG3_DVP_POS (15U) +#define PWC_FCG3_DVP (0x00008000UL) +#define PWC_FCG3_SMC_POS (16U) +#define PWC_FCG3_SMC (0x00010000UL) +#define PWC_FCG3_DMC_POS (17U) +#define PWC_FCG3_DMC (0x00020000UL) +#define PWC_FCG3_NFC_POS (18U) +#define PWC_FCG3_NFC (0x00040000UL) +#define PWC_FCG3_USART1_POS (20U) +#define PWC_FCG3_USART1 (0x00100000UL) +#define PWC_FCG3_USART2_POS (21U) +#define PWC_FCG3_USART2 (0x00200000UL) +#define PWC_FCG3_USART3_POS (22U) +#define PWC_FCG3_USART3 (0x00400000UL) +#define PWC_FCG3_USART4_POS (23U) +#define PWC_FCG3_USART4 (0x00800000UL) +#define PWC_FCG3_USART5_POS (24U) +#define PWC_FCG3_USART5 (0x01000000UL) +#define PWC_FCG3_USART6_POS (25U) +#define PWC_FCG3_USART6 (0x02000000UL) +#define PWC_FCG3_USART7_POS (26U) +#define PWC_FCG3_USART7 (0x04000000UL) +#define PWC_FCG3_USART8_POS (27U) +#define PWC_FCG3_USART8 (0x08000000UL) +#define PWC_FCG3_USART9_POS (28U) +#define PWC_FCG3_USART9 (0x10000000UL) +#define PWC_FCG3_USART10_POS (29U) +#define PWC_FCG3_USART10 (0x20000000UL) + +/* Bit definition for PWC_FCG0PC register */ +#define PWC_FCG0PC_PRT0_POS (0U) +#define PWC_FCG0PC_PRT0 (0x00000001UL) +#define PWC_FCG0PC_FCG0PCWE_POS (16U) +#define PWC_FCG0PC_FCG0PCWE (0xFFFF0000UL) + +/* Bit definition for PWC_VBATRSTR register */ +#define PWC_VBATRSTR (0xFFU) + +/* Bit definition for PWC_VBATCR register */ +#define PWC_VBATCR_VBTRSD_POS (0U) +#define PWC_VBATCR_VBTRSD (0x01U) +#define PWC_VBATCR_RAMVALID_POS (1U) +#define PWC_VBATCR_RAMVALID (0x02U) +#define PWC_VBATCR_RAMPDF_POS (2U) +#define PWC_VBATCR_RAMPDF (0x04U) +#define PWC_VBATCR_VBATDIVMONE_POS (3U) +#define PWC_VBATCR_VBATDIVMONE (0x08U) +#define PWC_VBATCR_CSDIS_POS (7U) +#define PWC_VBATCR_CSDIS (0x80U) + +/* Bit definition for PWC_WKTC0 register */ +#define PWC_WKTC0_WKTMCMP (0xFFU) + +/* Bit definition for PWC_WKTC1 register */ +#define PWC_WKTC1_WKTMCMP (0x0FU) + +/* Bit definition for PWC_WKTC2 register */ +#define PWC_WKTC2_WKOVF_POS (4U) +#define PWC_WKTC2_WKOVF (0x10U) +#define PWC_WKTC2_WKCKS_POS (5U) +#define PWC_WKTC2_WKCKS (0x60U) +#define PWC_WKTC2_WKCKS_0 (0x20U) +#define PWC_WKTC2_WKCKS_1 (0x40U) +#define PWC_WKTC2_WKTCE_POS (7U) +#define PWC_WKTC2_WKTCE (0x80U) + +/* Bit definition for PWC_BKR0 register */ +#define PWC_BKR0 (0xFFU) + +/* Bit definition for PWC_BKR1 register */ +#define PWC_BKR1 (0xFFU) + +/* Bit definition for PWC_BKR2 register */ +#define PWC_BKR2 (0xFFU) + +/* Bit definition for PWC_BKR3 register */ +#define PWC_BKR3 (0xFFU) + +/* Bit definition for PWC_BKR4 register */ +#define PWC_BKR4 (0xFFU) + +/* Bit definition for PWC_BKR5 register */ +#define PWC_BKR5 (0xFFU) + +/* Bit definition for PWC_BKR6 register */ +#define PWC_BKR6 (0xFFU) + +/* Bit definition for PWC_BKR7 register */ +#define PWC_BKR7 (0xFFU) + +/* Bit definition for PWC_BKR8 register */ +#define PWC_BKR8 (0xFFU) + +/* Bit definition for PWC_BKR9 register */ +#define PWC_BKR9 (0xFFU) + +/* Bit definition for PWC_BKR10 register */ +#define PWC_BKR10 (0xFFU) + +/* Bit definition for PWC_BKR11 register */ +#define PWC_BKR11 (0xFFU) + +/* Bit definition for PWC_BKR12 register */ +#define PWC_BKR12 (0xFFU) + +/* Bit definition for PWC_BKR13 register */ +#define PWC_BKR13 (0xFFU) + +/* Bit definition for PWC_BKR14 register */ +#define PWC_BKR14 (0xFFU) + +/* Bit definition for PWC_BKR15 register */ +#define PWC_BKR15 (0xFFU) + +/* Bit definition for PWC_BKR16 register */ +#define PWC_BKR16 (0xFFU) + +/* Bit definition for PWC_BKR17 register */ +#define PWC_BKR17 (0xFFU) + +/* Bit definition for PWC_BKR18 register */ +#define PWC_BKR18 (0xFFU) + +/* Bit definition for PWC_BKR19 register */ +#define PWC_BKR19 (0xFFU) + +/* Bit definition for PWC_BKR20 register */ +#define PWC_BKR20 (0xFFU) + +/* Bit definition for PWC_BKR21 register */ +#define PWC_BKR21 (0xFFU) + +/* Bit definition for PWC_BKR22 register */ +#define PWC_BKR22 (0xFFU) + +/* Bit definition for PWC_BKR23 register */ +#define PWC_BKR23 (0xFFU) + +/* Bit definition for PWC_BKR24 register */ +#define PWC_BKR24 (0xFFU) + +/* Bit definition for PWC_BKR25 register */ +#define PWC_BKR25 (0xFFU) + +/* Bit definition for PWC_BKR26 register */ +#define PWC_BKR26 (0xFFU) + +/* Bit definition for PWC_BKR27 register */ +#define PWC_BKR27 (0xFFU) + +/* Bit definition for PWC_BKR28 register */ +#define PWC_BKR28 (0xFFU) + +/* Bit definition for PWC_BKR29 register */ +#define PWC_BKR29 (0xFFU) + +/* Bit definition for PWC_BKR30 register */ +#define PWC_BKR30 (0xFFU) + +/* Bit definition for PWC_BKR31 register */ +#define PWC_BKR31 (0xFFU) + +/* Bit definition for PWC_BKR32 register */ +#define PWC_BKR32 (0xFFU) + +/* Bit definition for PWC_BKR33 register */ +#define PWC_BKR33 (0xFFU) + +/* Bit definition for PWC_BKR34 register */ +#define PWC_BKR34 (0xFFU) + +/* Bit definition for PWC_BKR35 register */ +#define PWC_BKR35 (0xFFU) + +/* Bit definition for PWC_BKR36 register */ +#define PWC_BKR36 (0xFFU) + +/* Bit definition for PWC_BKR37 register */ +#define PWC_BKR37 (0xFFU) + +/* Bit definition for PWC_BKR38 register */ +#define PWC_BKR38 (0xFFU) + +/* Bit definition for PWC_BKR39 register */ +#define PWC_BKR39 (0xFFU) + +/* Bit definition for PWC_BKR40 register */ +#define PWC_BKR40 (0xFFU) + +/* Bit definition for PWC_BKR41 register */ +#define PWC_BKR41 (0xFFU) + +/* Bit definition for PWC_BKR42 register */ +#define PWC_BKR42 (0xFFU) + +/* Bit definition for PWC_BKR43 register */ +#define PWC_BKR43 (0xFFU) + +/* Bit definition for PWC_BKR44 register */ +#define PWC_BKR44 (0xFFU) + +/* Bit definition for PWC_BKR45 register */ +#define PWC_BKR45 (0xFFU) + +/* Bit definition for PWC_BKR46 register */ +#define PWC_BKR46 (0xFFU) + +/* Bit definition for PWC_BKR47 register */ +#define PWC_BKR47 (0xFFU) + +/* Bit definition for PWC_BKR48 register */ +#define PWC_BKR48 (0xFFU) + +/* Bit definition for PWC_BKR49 register */ +#define PWC_BKR49 (0xFFU) + +/* Bit definition for PWC_BKR50 register */ +#define PWC_BKR50 (0xFFU) + +/* Bit definition for PWC_BKR51 register */ +#define PWC_BKR51 (0xFFU) + +/* Bit definition for PWC_BKR52 register */ +#define PWC_BKR52 (0xFFU) + +/* Bit definition for PWC_BKR53 register */ +#define PWC_BKR53 (0xFFU) + +/* Bit definition for PWC_BKR54 register */ +#define PWC_BKR54 (0xFFU) + +/* Bit definition for PWC_BKR55 register */ +#define PWC_BKR55 (0xFFU) + +/* Bit definition for PWC_BKR56 register */ +#define PWC_BKR56 (0xFFU) + +/* Bit definition for PWC_BKR57 register */ +#define PWC_BKR57 (0xFFU) + +/* Bit definition for PWC_BKR58 register */ +#define PWC_BKR58 (0xFFU) + +/* Bit definition for PWC_BKR59 register */ +#define PWC_BKR59 (0xFFU) + +/* Bit definition for PWC_BKR60 register */ +#define PWC_BKR60 (0xFFU) + +/* Bit definition for PWC_BKR61 register */ +#define PWC_BKR61 (0xFFU) + +/* Bit definition for PWC_BKR62 register */ +#define PWC_BKR62 (0xFFU) + +/* Bit definition for PWC_BKR63 register */ +#define PWC_BKR63 (0xFFU) + +/* Bit definition for PWC_BKR64 register */ +#define PWC_BKR64 (0xFFU) + +/* Bit definition for PWC_BKR65 register */ +#define PWC_BKR65 (0xFFU) + +/* Bit definition for PWC_BKR66 register */ +#define PWC_BKR66 (0xFFU) + +/* Bit definition for PWC_BKR67 register */ +#define PWC_BKR67 (0xFFU) + +/* Bit definition for PWC_BKR68 register */ +#define PWC_BKR68 (0xFFU) + +/* Bit definition for PWC_BKR69 register */ +#define PWC_BKR69 (0xFFU) + +/* Bit definition for PWC_BKR70 register */ +#define PWC_BKR70 (0xFFU) + +/* Bit definition for PWC_BKR71 register */ +#define PWC_BKR71 (0xFFU) + +/* Bit definition for PWC_BKR72 register */ +#define PWC_BKR72 (0xFFU) + +/* Bit definition for PWC_BKR73 register */ +#define PWC_BKR73 (0xFFU) + +/* Bit definition for PWC_BKR74 register */ +#define PWC_BKR74 (0xFFU) + +/* Bit definition for PWC_BKR75 register */ +#define PWC_BKR75 (0xFFU) + +/* Bit definition for PWC_BKR76 register */ +#define PWC_BKR76 (0xFFU) + +/* Bit definition for PWC_BKR77 register */ +#define PWC_BKR77 (0xFFU) + +/* Bit definition for PWC_BKR78 register */ +#define PWC_BKR78 (0xFFU) + +/* Bit definition for PWC_BKR79 register */ +#define PWC_BKR79 (0xFFU) + +/* Bit definition for PWC_BKR80 register */ +#define PWC_BKR80 (0xFFU) + +/* Bit definition for PWC_BKR81 register */ +#define PWC_BKR81 (0xFFU) + +/* Bit definition for PWC_BKR82 register */ +#define PWC_BKR82 (0xFFU) + +/* Bit definition for PWC_BKR83 register */ +#define PWC_BKR83 (0xFFU) + +/* Bit definition for PWC_BKR84 register */ +#define PWC_BKR84 (0xFFU) + +/* Bit definition for PWC_BKR85 register */ +#define PWC_BKR85 (0xFFU) + +/* Bit definition for PWC_BKR86 register */ +#define PWC_BKR86 (0xFFU) + +/* Bit definition for PWC_BKR87 register */ +#define PWC_BKR87 (0xFFU) + +/* Bit definition for PWC_BKR88 register */ +#define PWC_BKR88 (0xFFU) + +/* Bit definition for PWC_BKR89 register */ +#define PWC_BKR89 (0xFFU) + +/* Bit definition for PWC_BKR90 register */ +#define PWC_BKR90 (0xFFU) + +/* Bit definition for PWC_BKR91 register */ +#define PWC_BKR91 (0xFFU) + +/* Bit definition for PWC_BKR92 register */ +#define PWC_BKR92 (0xFFU) + +/* Bit definition for PWC_BKR93 register */ +#define PWC_BKR93 (0xFFU) + +/* Bit definition for PWC_BKR94 register */ +#define PWC_BKR94 (0xFFU) + +/* Bit definition for PWC_BKR95 register */ +#define PWC_BKR95 (0xFFU) + +/* Bit definition for PWC_BKR96 register */ +#define PWC_BKR96 (0xFFU) + +/* Bit definition for PWC_BKR97 register */ +#define PWC_BKR97 (0xFFU) + +/* Bit definition for PWC_BKR98 register */ +#define PWC_BKR98 (0xFFU) + +/* Bit definition for PWC_BKR99 register */ +#define PWC_BKR99 (0xFFU) + +/* Bit definition for PWC_BKR100 register */ +#define PWC_BKR100 (0xFFU) + +/* Bit definition for PWC_BKR101 register */ +#define PWC_BKR101 (0xFFU) + +/* Bit definition for PWC_BKR102 register */ +#define PWC_BKR102 (0xFFU) + +/* Bit definition for PWC_BKR103 register */ +#define PWC_BKR103 (0xFFU) + +/* Bit definition for PWC_BKR104 register */ +#define PWC_BKR104 (0xFFU) + +/* Bit definition for PWC_BKR105 register */ +#define PWC_BKR105 (0xFFU) + +/* Bit definition for PWC_BKR106 register */ +#define PWC_BKR106 (0xFFU) + +/* Bit definition for PWC_BKR107 register */ +#define PWC_BKR107 (0xFFU) + +/* Bit definition for PWC_BKR108 register */ +#define PWC_BKR108 (0xFFU) + +/* Bit definition for PWC_BKR109 register */ +#define PWC_BKR109 (0xFFU) + +/* Bit definition for PWC_BKR110 register */ +#define PWC_BKR110 (0xFFU) + +/* Bit definition for PWC_BKR111 register */ +#define PWC_BKR111 (0xFFU) + +/* Bit definition for PWC_BKR112 register */ +#define PWC_BKR112 (0xFFU) + +/* Bit definition for PWC_BKR113 register */ +#define PWC_BKR113 (0xFFU) + +/* Bit definition for PWC_BKR114 register */ +#define PWC_BKR114 (0xFFU) + +/* Bit definition for PWC_BKR115 register */ +#define PWC_BKR115 (0xFFU) + +/* Bit definition for PWC_BKR116 register */ +#define PWC_BKR116 (0xFFU) + +/* Bit definition for PWC_BKR117 register */ +#define PWC_BKR117 (0xFFU) + +/* Bit definition for PWC_BKR118 register */ +#define PWC_BKR118 (0xFFU) + +/* Bit definition for PWC_BKR119 register */ +#define PWC_BKR119 (0xFFU) + +/* Bit definition for PWC_BKR120 register */ +#define PWC_BKR120 (0xFFU) + +/* Bit definition for PWC_BKR121 register */ +#define PWC_BKR121 (0xFFU) + +/* Bit definition for PWC_BKR122 register */ +#define PWC_BKR122 (0xFFU) + +/* Bit definition for PWC_BKR123 register */ +#define PWC_BKR123 (0xFFU) + +/* Bit definition for PWC_BKR124 register */ +#define PWC_BKR124 (0xFFU) + +/* Bit definition for PWC_BKR125 register */ +#define PWC_BKR125 (0xFFU) + +/* Bit definition for PWC_BKR126 register */ +#define PWC_BKR126 (0xFFU) + +/* Bit definition for PWC_BKR127 register */ +#define PWC_BKR127 (0xFFU) + +/* Bit definition for PWC_PWRC0 register */ +#define PWC_PWRC0_PDMDS_POS (0U) +#define PWC_PWRC0_PDMDS (0x03U) +#define PWC_PWRC0_PDMDS_0 (0x01U) +#define PWC_PWRC0_PDMDS_1 (0x02U) +#define PWC_PWRC0_IORTN_POS (4U) +#define PWC_PWRC0_IORTN (0x30U) +#define PWC_PWRC0_IORTN_0 (0x10U) +#define PWC_PWRC0_IORTN_1 (0x20U) +#define PWC_PWRC0_PWDN_POS (7U) +#define PWC_PWRC0_PWDN (0x80U) + +/* Bit definition for PWC_PWRC1 register */ +#define PWC_PWRC1_VPLLSD_POS (0U) +#define PWC_PWRC1_VPLLSD (0x03U) +#define PWC_PWRC1_VPLLSD_0 (0x01U) +#define PWC_PWRC1_VPLLSD_1 (0x02U) +#define PWC_PWRC1_VHRCSD_POS (2U) +#define PWC_PWRC1_VHRCSD (0x04U) +#define PWC_PWRC1_PDTS_POS (3U) +#define PWC_PWRC1_PDTS (0x08U) +#define PWC_PWRC1_STPDAS_POS (6U) +#define PWC_PWRC1_STPDAS (0xC0U) +#define PWC_PWRC1_STPDAS_0 (0x40U) +#define PWC_PWRC1_STPDAS_1 (0x80U) + +/* Bit definition for PWC_PWRC2 register */ +#define PWC_PWRC2_DDAS_POS (0U) +#define PWC_PWRC2_DDAS (0x0FU) +#define PWC_PWRC2_DVS_POS (4U) +#define PWC_PWRC2_DVS (0x30U) +#define PWC_PWRC2_DVS_0 (0x10U) +#define PWC_PWRC2_DVS_1 (0x20U) + +/* Bit definition for PWC_PWRC3 register */ +#define PWC_PWRC3_DDAS (0xFFU) + +/* Bit definition for PWC_PWRC4 register */ +#define PWC_PWRC4_VBATREFSEL_POS (0U) +#define PWC_PWRC4_VBATREFSEL (0x01U) +#define PWC_PWRC4_VBATME_POS (1U) +#define PWC_PWRC4_VBATME (0x02U) +#define PWC_PWRC4_VBATMON_POS (4U) +#define PWC_PWRC4_VBATMON (0x10U) +#define PWC_PWRC4_ADBUFS_POS (6U) +#define PWC_PWRC4_ADBUFS (0x40U) +#define PWC_PWRC4_ADBUFE_POS (7U) +#define PWC_PWRC4_ADBUFE (0x80U) + +/* Bit definition for PWC_PVDCR0 register */ +#define PWC_PVDCR0_EXVCCINEN_POS (0U) +#define PWC_PVDCR0_EXVCCINEN (0x01U) +#define PWC_PVDCR0_PVD1EN_POS (5U) +#define PWC_PVDCR0_PVD1EN (0x20U) +#define PWC_PVDCR0_PVD2EN_POS (6U) +#define PWC_PVDCR0_PVD2EN (0x40U) + +/* Bit definition for PWC_PVDCR1 register */ +#define PWC_PVDCR1_PVD1IRE_POS (0U) +#define PWC_PVDCR1_PVD1IRE (0x01U) +#define PWC_PVDCR1_PVD1IRS_POS (1U) +#define PWC_PVDCR1_PVD1IRS (0x02U) +#define PWC_PVDCR1_PVD1CMPOE_POS (2U) +#define PWC_PVDCR1_PVD1CMPOE (0x04U) +#define PWC_PVDCR1_PVD2IRE_POS (4U) +#define PWC_PVDCR1_PVD2IRE (0x10U) +#define PWC_PVDCR1_PVD2IRS_POS (5U) +#define PWC_PVDCR1_PVD2IRS (0x20U) +#define PWC_PVDCR1_PVD2CMPOE_POS (6U) +#define PWC_PVDCR1_PVD2CMPOE (0x40U) + +/* Bit definition for PWC_PVDFCR register */ +#define PWC_PVDFCR_PVD1NFDIS_POS (0U) +#define PWC_PVDFCR_PVD1NFDIS (0x01U) +#define PWC_PVDFCR_PVD1NFCKS_POS (1U) +#define PWC_PVDFCR_PVD1NFCKS (0x06U) +#define PWC_PVDFCR_PVD1NFCKS_0 (0x02U) +#define PWC_PVDFCR_PVD1NFCKS_1 (0x04U) +#define PWC_PVDFCR_PVD2NFDIS_POS (4U) +#define PWC_PVDFCR_PVD2NFDIS (0x10U) +#define PWC_PVDFCR_PVD2NFCKS_POS (5U) +#define PWC_PVDFCR_PVD2NFCKS (0x60U) +#define PWC_PVDFCR_PVD2NFCKS_0 (0x20U) +#define PWC_PVDFCR_PVD2NFCKS_1 (0x40U) + +/* Bit definition for PWC_PVDLCR register */ +#define PWC_PVDLCR_PVD1LVL_POS (0U) +#define PWC_PVDLCR_PVD1LVL (0x07U) +#define PWC_PVDLCR_PVD1LVL_0 (0x01U) +#define PWC_PVDLCR_PVD1LVL_1 (0x02U) +#define PWC_PVDLCR_PVD1LVL_2 (0x04U) +#define PWC_PVDLCR_PVD2LVL_POS (4U) +#define PWC_PVDLCR_PVD2LVL (0x70U) +#define PWC_PVDLCR_PVD2LVL_0 (0x10U) +#define PWC_PVDLCR_PVD2LVL_1 (0x20U) +#define PWC_PVDLCR_PVD2LVL_2 (0x40U) + +/* Bit definition for PWC_PDWKE0 register */ +#define PWC_PDWKE0_WKE0_0_POS (0U) +#define PWC_PDWKE0_WKE0_0 (0x01U) +#define PWC_PDWKE0_WKE0_1_POS (1U) +#define PWC_PDWKE0_WKE0_1 (0x02U) +#define PWC_PDWKE0_WKE0_2_POS (2U) +#define PWC_PDWKE0_WKE0_2 (0x04U) +#define PWC_PDWKE0_WKE0_3_POS (3U) +#define PWC_PDWKE0_WKE0_3 (0x08U) +#define PWC_PDWKE0_WKE1_0_POS (4U) +#define PWC_PDWKE0_WKE1_0 (0x10U) +#define PWC_PDWKE0_WKE1_1_POS (5U) +#define PWC_PDWKE0_WKE1_1 (0x20U) +#define PWC_PDWKE0_WKE1_2_POS (6U) +#define PWC_PDWKE0_WKE1_2 (0x40U) +#define PWC_PDWKE0_WKE1_3_POS (7U) +#define PWC_PDWKE0_WKE1_3 (0x80U) + +/* Bit definition for PWC_PDWKE1 register */ +#define PWC_PDWKE1_WKE2_0_POS (0U) +#define PWC_PDWKE1_WKE2_0 (0x01U) +#define PWC_PDWKE1_WKE2_1_POS (1U) +#define PWC_PDWKE1_WKE2_1 (0x02U) +#define PWC_PDWKE1_WKE2_2_POS (2U) +#define PWC_PDWKE1_WKE2_2 (0x04U) +#define PWC_PDWKE1_WKE2_3_POS (3U) +#define PWC_PDWKE1_WKE2_3 (0x08U) +#define PWC_PDWKE1_WKE3_0_POS (4U) +#define PWC_PDWKE1_WKE3_0 (0x10U) +#define PWC_PDWKE1_WKE3_1_POS (5U) +#define PWC_PDWKE1_WKE3_1 (0x20U) +#define PWC_PDWKE1_WKE3_2_POS (6U) +#define PWC_PDWKE1_WKE3_2 (0x40U) +#define PWC_PDWKE1_WKE3_3_POS (7U) +#define PWC_PDWKE1_WKE3_3 (0x80U) + +/* Bit definition for PWC_PDWKE2 register */ +#define PWC_PDWKE2_VD1WKE_POS (0U) +#define PWC_PDWKE2_VD1WKE (0x01U) +#define PWC_PDWKE2_VD2WKE_POS (1U) +#define PWC_PDWKE2_VD2WKE (0x02U) +#define PWC_PDWKE2_RTCPRDWKE_POS (4U) +#define PWC_PDWKE2_RTCPRDWKE (0x10U) +#define PWC_PDWKE2_RTCALMWKE_POS (5U) +#define PWC_PDWKE2_RTCALMWKE (0x20U) +#define PWC_PDWKE2_XTAL32ERWKE_POS (6U) +#define PWC_PDWKE2_XTAL32ERWKE (0x40U) +#define PWC_PDWKE2_WKTMWKE_POS (7U) +#define PWC_PDWKE2_WKTMWKE (0x80U) + +/* Bit definition for PWC_PDWKES register */ +#define PWC_PDWKES_WK0EGS_POS (0U) +#define PWC_PDWKES_WK0EGS (0x01U) +#define PWC_PDWKES_WK1EGS_POS (1U) +#define PWC_PDWKES_WK1EGS (0x02U) +#define PWC_PDWKES_WK2EGS_POS (2U) +#define PWC_PDWKES_WK2EGS (0x04U) +#define PWC_PDWKES_WK3EGS_POS (3U) +#define PWC_PDWKES_WK3EGS (0x08U) +#define PWC_PDWKES_VD1EGS_POS (4U) +#define PWC_PDWKES_VD1EGS (0x10U) +#define PWC_PDWKES_VD2EGS_POS (5U) +#define PWC_PDWKES_VD2EGS (0x20U) + +/* Bit definition for PWC_PDWKF0 register */ +#define PWC_PDWKF0_PTWK0F_POS (0U) +#define PWC_PDWKF0_PTWK0F (0x01U) +#define PWC_PDWKF0_PTWK1F_POS (1U) +#define PWC_PDWKF0_PTWK1F (0x02U) +#define PWC_PDWKF0_PTWK2F_POS (2U) +#define PWC_PDWKF0_PTWK2F (0x04U) +#define PWC_PDWKF0_PTWK3F_POS (3U) +#define PWC_PDWKF0_PTWK3F (0x08U) +#define PWC_PDWKF0_VD1WKF_POS (4U) +#define PWC_PDWKF0_VD1WKF (0x10U) +#define PWC_PDWKF0_VD2WKF_POS (5U) +#define PWC_PDWKF0_VD2WKF (0x20U) + +/* Bit definition for PWC_PDWKF1 register */ +#define PWC_PDWKF1_RXD0WKF_POS (3U) +#define PWC_PDWKF1_RXD0WKF (0x08U) +#define PWC_PDWKF1_RTCPRDWKF_POS (4U) +#define PWC_PDWKF1_RTCPRDWKF (0x10U) +#define PWC_PDWKF1_RTCALMWKF_POS (5U) +#define PWC_PDWKF1_RTCALMWKF (0x20U) +#define PWC_PDWKF1_XTAL32ERWKF_POS (6U) +#define PWC_PDWKF1_XTAL32ERWKF (0x40U) +#define PWC_PDWKF1_WKTMWKF_POS (7U) +#define PWC_PDWKF1_WKTMWKF (0x80U) + +/* Bit definition for PWC_RAMPC0 register */ +#define PWC_RAMPC0_RAMPDC0_POS (0U) +#define PWC_RAMPC0_RAMPDC0 (0x00000001UL) +#define PWC_RAMPC0_RAMPDC1_POS (1U) +#define PWC_RAMPC0_RAMPDC1 (0x00000002UL) +#define PWC_RAMPC0_RAMPDC2_POS (2U) +#define PWC_RAMPC0_RAMPDC2 (0x00000004UL) +#define PWC_RAMPC0_RAMPDC3_POS (3U) +#define PWC_RAMPC0_RAMPDC3 (0x00000008UL) +#define PWC_RAMPC0_RAMPDC4_POS (4U) +#define PWC_RAMPC0_RAMPDC4 (0x00000010UL) +#define PWC_RAMPC0_RAMPDC5_POS (5U) +#define PWC_RAMPC0_RAMPDC5 (0x00000020UL) +#define PWC_RAMPC0_RAMPDC6_POS (6U) +#define PWC_RAMPC0_RAMPDC6 (0x00000040UL) +#define PWC_RAMPC0_RAMPDC7_POS (7U) +#define PWC_RAMPC0_RAMPDC7 (0x00000080UL) +#define PWC_RAMPC0_RAMPDC8_POS (8U) +#define PWC_RAMPC0_RAMPDC8 (0x00000100UL) +#define PWC_RAMPC0_RAMPDC9_POS (9U) +#define PWC_RAMPC0_RAMPDC9 (0x00000200UL) +#define PWC_RAMPC0_RAMPDC10_POS (10U) +#define PWC_RAMPC0_RAMPDC10 (0x00000400UL) + +/* Bit definition for PWC_RAMOPM register */ +#define PWC_RAMOPM_RAMOPM (0x0000FFFFUL) + +/* Bit definition for PWC_PRAMLPC register */ +#define PWC_PRAMLPC_PRAMPDC0_POS (0U) +#define PWC_PRAMLPC_PRAMPDC0 (0x00000001UL) +#define PWC_PRAMLPC_PRAMPDC1_POS (1U) +#define PWC_PRAMLPC_PRAMPDC1 (0x00000002UL) +#define PWC_PRAMLPC_PRAMPDC2_POS (2U) +#define PWC_PRAMLPC_PRAMPDC2 (0x00000004UL) +#define PWC_PRAMLPC_PRAMPDC3_POS (3U) +#define PWC_PRAMLPC_PRAMPDC3 (0x00000008UL) +#define PWC_PRAMLPC_PRAMPDC4_POS (4U) +#define PWC_PRAMLPC_PRAMPDC4 (0x00000010UL) +#define PWC_PRAMLPC_PRAMPDC5_POS (5U) +#define PWC_PRAMLPC_PRAMPDC5 (0x00000020UL) +#define PWC_PRAMLPC_PRAMPDC6_POS (6U) +#define PWC_PRAMLPC_PRAMPDC6 (0x00000040UL) +#define PWC_PRAMLPC_PRAMPDC7_POS (7U) +#define PWC_PRAMLPC_PRAMPDC7 (0x00000080UL) +#define PWC_PRAMLPC_PRAMPDC8_POS (8U) +#define PWC_PRAMLPC_PRAMPDC8 (0x00000100UL) +#define PWC_PRAMLPC_PRAMPDC9_POS (9U) +#define PWC_PRAMLPC_PRAMPDC9 (0x00000200UL) + +/* Bit definition for PWC_PVDICR register */ +#define PWC_PVDICR_PVD1NMIS_POS (0U) +#define PWC_PVDICR_PVD1NMIS (0x01U) +#define PWC_PVDICR_PVD1EDGS_POS (1U) +#define PWC_PVDICR_PVD1EDGS (0x06U) +#define PWC_PVDICR_PVD1EDGS_0 (0x02U) +#define PWC_PVDICR_PVD1EDGS_1 (0x04U) +#define PWC_PVDICR_PVD2NMIS_POS (4U) +#define PWC_PVDICR_PVD2NMIS (0x10U) +#define PWC_PVDICR_PVD2EDGS_POS (5U) +#define PWC_PVDICR_PVD2EDGS (0x60U) +#define PWC_PVDICR_PVD2EDGS_0 (0x20U) +#define PWC_PVDICR_PVD2EDGS_1 (0x40U) + +/* Bit definition for PWC_PVDDSR register */ +#define PWC_PVDDSR_PVD1MON_POS (0U) +#define PWC_PVDDSR_PVD1MON (0x01U) +#define PWC_PVDDSR_PVD1DETFLG_POS (1U) +#define PWC_PVDDSR_PVD1DETFLG (0x02U) +#define PWC_PVDDSR_PVD2MON_POS (4U) +#define PWC_PVDDSR_PVD2MON (0x10U) +#define PWC_PVDDSR_PVD2DETFLG_POS (5U) +#define PWC_PVDDSR_PVD2DETFLG (0x20U) + +/* Bit definition for PWC_STPMCR register */ +#define PWC_STPMCR_FLNWT_POS (0U) +#define PWC_STPMCR_FLNWT (0x0001U) +#define PWC_STPMCR_CKSMRC_POS (1U) +#define PWC_STPMCR_CKSMRC (0x0002U) +#define PWC_STPMCR_EXBUSOE_POS (14U) +#define PWC_STPMCR_EXBUSOE (0x4000U) +#define PWC_STPMCR_STOP_POS (15U) +#define PWC_STPMCR_STOP (0x8000U) + +/* Bit definition for PWC_FPRC register */ +#define PWC_FPRC_FPRCB0_POS (0U) +#define PWC_FPRC_FPRCB0 (0x0001U) +#define PWC_FPRC_FPRCB1_POS (1U) +#define PWC_FPRC_FPRCB1 (0x0002U) +#define PWC_FPRC_FPRCB2_POS (2U) +#define PWC_FPRC_FPRCB2 (0x0004U) +#define PWC_FPRC_FPRCB3_POS (3U) +#define PWC_FPRC_FPRCB3 (0x0008U) +#define PWC_FPRC_FPRCWE_POS (8U) +#define PWC_FPRC_FPRCWE (0xFF00U) + +/******************************************************************************* + Bit definition for Peripheral QSPI +*******************************************************************************/ +/* Bit definition for QSPI_CR register */ +#define QSPI_CR_MDSEL_POS (0U) +#define QSPI_CR_MDSEL (0x00000007UL) +#define QSPI_CR_MDSEL_0 (0x00000001UL) +#define QSPI_CR_MDSEL_1 (0x00000002UL) +#define QSPI_CR_MDSEL_2 (0x00000004UL) +#define QSPI_CR_PFE_POS (3U) +#define QSPI_CR_PFE (0x00000008UL) +#define QSPI_CR_PFSAE_POS (4U) +#define QSPI_CR_PFSAE (0x00000010UL) +#define QSPI_CR_DCOME_POS (5U) +#define QSPI_CR_DCOME (0x00000020UL) +#define QSPI_CR_XIPE_POS (6U) +#define QSPI_CR_XIPE (0x00000040UL) +#define QSPI_CR_SPIMD3_POS (7U) +#define QSPI_CR_SPIMD3 (0x00000080UL) +#define QSPI_CR_IPRSL_POS (8U) +#define QSPI_CR_IPRSL (0x00000300UL) +#define QSPI_CR_IPRSL_0 (0x00000100UL) +#define QSPI_CR_IPRSL_1 (0x00000200UL) +#define QSPI_CR_APRSL_POS (10U) +#define QSPI_CR_APRSL (0x00000C00UL) +#define QSPI_CR_APRSL_0 (0x00000400UL) +#define QSPI_CR_APRSL_1 (0x00000800UL) +#define QSPI_CR_DPRSL_POS (12U) +#define QSPI_CR_DPRSL (0x00003000UL) +#define QSPI_CR_DPRSL_0 (0x00001000UL) +#define QSPI_CR_DPRSL_1 (0x00002000UL) +#define QSPI_CR_DIV_POS (16U) +#define QSPI_CR_DIV (0x003F0000UL) +#define QSPI_CR_DIV_0 (0x00010000UL) +#define QSPI_CR_DIV_1 (0x00020000UL) +#define QSPI_CR_DIV_2 (0x00040000UL) +#define QSPI_CR_DIV_3 (0x00080000UL) +#define QSPI_CR_DIV_4 (0x00100000UL) +#define QSPI_CR_DIV_5 (0x00200000UL) + +/* Bit definition for QSPI_CSCR register */ +#define QSPI_CSCR_SSHW_POS (0U) +#define QSPI_CSCR_SSHW (0x0000000FUL) +#define QSPI_CSCR_SSHW_0 (0x00000001UL) +#define QSPI_CSCR_SSHW_1 (0x00000002UL) +#define QSPI_CSCR_SSHW_2 (0x00000004UL) +#define QSPI_CSCR_SSHW_3 (0x00000008UL) +#define QSPI_CSCR_SSNW_POS (4U) +#define QSPI_CSCR_SSNW (0x00000030UL) +#define QSPI_CSCR_SSNW_0 (0x00000010UL) +#define QSPI_CSCR_SSNW_1 (0x00000020UL) + +/* Bit definition for QSPI_FCR register */ +#define QSPI_FCR_AWSL_POS (0U) +#define QSPI_FCR_AWSL (0x00000003UL) +#define QSPI_FCR_AWSL_0 (0x00000001UL) +#define QSPI_FCR_AWSL_1 (0x00000002UL) +#define QSPI_FCR_FOUR_BIC_POS (2U) +#define QSPI_FCR_FOUR_BIC (0x00000004UL) +#define QSPI_FCR_SSNHD_POS (4U) +#define QSPI_FCR_SSNHD (0x00000010UL) +#define QSPI_FCR_SSNLD_POS (5U) +#define QSPI_FCR_SSNLD (0x00000020UL) +#define QSPI_FCR_WPOL_POS (6U) +#define QSPI_FCR_WPOL (0x00000040UL) +#define QSPI_FCR_DMCYCN_POS (8U) +#define QSPI_FCR_DMCYCN (0x00000F00UL) +#define QSPI_FCR_DMCYCN_0 (0x00000100UL) +#define QSPI_FCR_DMCYCN_1 (0x00000200UL) +#define QSPI_FCR_DMCYCN_2 (0x00000400UL) +#define QSPI_FCR_DMCYCN_3 (0x00000800UL) +#define QSPI_FCR_DUTY_POS (15U) +#define QSPI_FCR_DUTY (0x00008000UL) + +/* Bit definition for QSPI_SR register */ +#define QSPI_SR_BUSY_POS (0U) +#define QSPI_SR_BUSY (0x00000001UL) +#define QSPI_SR_XIPF_POS (6U) +#define QSPI_SR_XIPF (0x00000040UL) +#define QSPI_SR_RAER_POS (7U) +#define QSPI_SR_RAER (0x00000080UL) +#define QSPI_SR_PFNUM_POS (8U) +#define QSPI_SR_PFNUM (0x00001F00UL) +#define QSPI_SR_PFNUM_0 (0x00000100UL) +#define QSPI_SR_PFNUM_1 (0x00000200UL) +#define QSPI_SR_PFNUM_2 (0x00000400UL) +#define QSPI_SR_PFNUM_3 (0x00000800UL) +#define QSPI_SR_PFNUM_4 (0x00001000UL) +#define QSPI_SR_PFFUL_POS (14U) +#define QSPI_SR_PFFUL (0x00004000UL) +#define QSPI_SR_PFAN_POS (15U) +#define QSPI_SR_PFAN (0x00008000UL) + +/* Bit definition for QSPI_DCOM register */ +#define QSPI_DCOM_DCOM (0x000000FFUL) + +/* Bit definition for QSPI_CCMD register */ +#define QSPI_CCMD_RIC (0x000000FFUL) + +/* Bit definition for QSPI_XCMD register */ +#define QSPI_XCMD_XIPMC (0x000000FFUL) + +/* Bit definition for QSPI_SR2 register */ +#define QSPI_SR2_RAERCLR_POS (7U) +#define QSPI_SR2_RAERCLR (0x00000080UL) + +/* Bit definition for QSPI_EXAR register */ +#define QSPI_EXAR_EXADR_POS (26U) +#define QSPI_EXAR_EXADR (0xFC000000UL) + +/******************************************************************************* + Bit definition for Peripheral RMU +*******************************************************************************/ +/* Bit definition for RMU_PRSTCR0 register */ +#define RMU_PRSTCR0_LKUPREN_POS (5U) +#define RMU_PRSTCR0_LKUPREN (0x60U) + +/* Bit definition for RMU_RSTF0 register */ +#define RMU_RSTF0_PORF_POS (0U) +#define RMU_RSTF0_PORF (0x00000001UL) +#define RMU_RSTF0_PINRF_POS (1U) +#define RMU_RSTF0_PINRF (0x00000002UL) +#define RMU_RSTF0_BORF_POS (2U) +#define RMU_RSTF0_BORF (0x00000004UL) +#define RMU_RSTF0_PVD1RF_POS (3U) +#define RMU_RSTF0_PVD1RF (0x00000008UL) +#define RMU_RSTF0_PVD2RF_POS (4U) +#define RMU_RSTF0_PVD2RF (0x00000010UL) +#define RMU_RSTF0_WDRF_POS (5U) +#define RMU_RSTF0_WDRF (0x00000020UL) +#define RMU_RSTF0_SWDRF_POS (6U) +#define RMU_RSTF0_SWDRF (0x00000040UL) +#define RMU_RSTF0_PDRF_POS (7U) +#define RMU_RSTF0_PDRF (0x00000080UL) +#define RMU_RSTF0_SWRF_POS (8U) +#define RMU_RSTF0_SWRF (0x00000100UL) +#define RMU_RSTF0_MPUERF_POS (9U) +#define RMU_RSTF0_MPUERF (0x00000200UL) +#define RMU_RSTF0_RAPERF_POS (10U) +#define RMU_RSTF0_RAPERF (0x00000400UL) +#define RMU_RSTF0_RAECRF_POS (11U) +#define RMU_RSTF0_RAECRF (0x00000800UL) +#define RMU_RSTF0_CKFERF_POS (12U) +#define RMU_RSTF0_CKFERF (0x00001000UL) +#define RMU_RSTF0_XTALERF_POS (13U) +#define RMU_RSTF0_XTALERF (0x00002000UL) +#define RMU_RSTF0_LKUPRF_POS (14U) +#define RMU_RSTF0_LKUPRF (0x00004000UL) +#define RMU_RSTF0_MULTIRF_POS (30U) +#define RMU_RSTF0_MULTIRF (0x40000000UL) +#define RMU_RSTF0_CLRF_POS (31U) +#define RMU_RSTF0_CLRF (0x80000000UL) + +/******************************************************************************* + Bit definition for Peripheral RTC +*******************************************************************************/ +/* Bit definition for RTC_CR0 register */ +#define RTC_CR0_RESET (0x01U) + +/* Bit definition for RTC_CR1 register */ +#define RTC_CR1_PRDS_POS (0U) +#define RTC_CR1_PRDS (0x07U) +#define RTC_CR1_PRDS_0 (0x01U) +#define RTC_CR1_PRDS_1 (0x02U) +#define RTC_CR1_PRDS_2 (0x04U) +#define RTC_CR1_AMPM_POS (3U) +#define RTC_CR1_AMPM (0x08U) +#define RTC_CR1_ONEHZOE_POS (5U) +#define RTC_CR1_ONEHZOE (0x20U) +#define RTC_CR1_ONEHZSEL_POS (6U) +#define RTC_CR1_ONEHZSEL (0x40U) +#define RTC_CR1_START_POS (7U) +#define RTC_CR1_START (0x80U) + +/* Bit definition for RTC_CR2 register */ +#define RTC_CR2_RWREQ_POS (0U) +#define RTC_CR2_RWREQ (0x01U) +#define RTC_CR2_RWEN_POS (1U) +#define RTC_CR2_RWEN (0x02U) +#define RTC_CR2_PRDF_POS (2U) +#define RTC_CR2_PRDF (0x04U) +#define RTC_CR2_ALMF_POS (3U) +#define RTC_CR2_ALMF (0x08U) +#define RTC_CR2_PRDIE_POS (5U) +#define RTC_CR2_PRDIE (0x20U) +#define RTC_CR2_ALMIE_POS (6U) +#define RTC_CR2_ALMIE (0x40U) +#define RTC_CR2_ALME_POS (7U) +#define RTC_CR2_ALME (0x80U) + +/* Bit definition for RTC_CR3 register */ +#define RTC_CR3_LRCEN_POS (4U) +#define RTC_CR3_LRCEN (0x10U) +#define RTC_CR3_RCKSEL_POS (7U) +#define RTC_CR3_RCKSEL (0x80U) + +/* Bit definition for RTC_SEC register */ +#define RTC_SEC_SECU_POS (0U) +#define RTC_SEC_SECU (0x0FU) +#define RTC_SEC_SECD_POS (4U) +#define RTC_SEC_SECD (0x70U) + +/* Bit definition for RTC_MIN register */ +#define RTC_MIN_MINU_POS (0U) +#define RTC_MIN_MINU (0x0FU) +#define RTC_MIN_MIND_POS (4U) +#define RTC_MIN_MIND (0x70U) + +/* Bit definition for RTC_HOUR register */ +#define RTC_HOUR_HOURU_POS (0U) +#define RTC_HOUR_HOURU (0x0FU) +#define RTC_HOUR_HOURU_0 (0x01U) +#define RTC_HOUR_HOURU_1 (0x02U) +#define RTC_HOUR_HOURU_2 (0x04U) +#define RTC_HOUR_HOURU_3 (0x08U) +#define RTC_HOUR_HOURD_POS (4U) +#define RTC_HOUR_HOURD (0x30U) +#define RTC_HOUR_HOURD_0 (0x10U) +#define RTC_HOUR_HOURD_1 (0x20U) + +/* Bit definition for RTC_WEEK register */ +#define RTC_WEEK_WEEK (0x07U) + +/* Bit definition for RTC_DAY register */ +#define RTC_DAY_DAYU_POS (0U) +#define RTC_DAY_DAYU (0x0FU) +#define RTC_DAY_DAYD_POS (4U) +#define RTC_DAY_DAYD (0x30U) + +/* Bit definition for RTC_MON register */ +#define RTC_MON_MON (0x1FU) + +/* Bit definition for RTC_YEAR register */ +#define RTC_YEAR_YEARU_POS (0U) +#define RTC_YEAR_YEARU (0x0FU) +#define RTC_YEAR_YEARD_POS (4U) +#define RTC_YEAR_YEARD (0xF0U) + +/* Bit definition for RTC_ALMMIN register */ +#define RTC_ALMMIN_ALMMINU_POS (0U) +#define RTC_ALMMIN_ALMMINU (0x0FU) +#define RTC_ALMMIN_ALMMIND_POS (4U) +#define RTC_ALMMIN_ALMMIND (0x70U) + +/* Bit definition for RTC_ALMHOUR register */ +#define RTC_ALMHOUR_ALMHOURU_POS (0U) +#define RTC_ALMHOUR_ALMHOURU (0x0FU) +#define RTC_ALMHOUR_ALMHOURU_0 (0x01U) +#define RTC_ALMHOUR_ALMHOURU_1 (0x02U) +#define RTC_ALMHOUR_ALMHOURU_2 (0x04U) +#define RTC_ALMHOUR_ALMHOURU_3 (0x08U) +#define RTC_ALMHOUR_ALMHOURD_POS (4U) +#define RTC_ALMHOUR_ALMHOURD (0x30U) +#define RTC_ALMHOUR_ALMHOURD_0 (0x10U) +#define RTC_ALMHOUR_ALMHOURD_1 (0x20U) + +/* Bit definition for RTC_ALMWEEK register */ +#define RTC_ALMWEEK_ALMWEEK (0x7FU) + +/* Bit definition for RTC_ERRCRH register */ +#define RTC_ERRCRH_COMP8_POS (0U) +#define RTC_ERRCRH_COMP8 (0x01U) +#define RTC_ERRCRH_COMPEN_POS (7U) +#define RTC_ERRCRH_COMPEN (0x80U) + +/* Bit definition for RTC_ERRCRL register */ +#define RTC_ERRCRL_COMP (0xFFU) + +/* Bit definition for RTC_TPCR0 register */ +#define RTC_TPCR0_TPCT0_POS (0U) +#define RTC_TPCR0_TPCT0 (0x03U) +#define RTC_TPCR0_TPCT0_0 (0x01U) +#define RTC_TPCR0_TPCT0_1 (0x02U) +#define RTC_TPCR0_TPNF0_POS (2U) +#define RTC_TPCR0_TPNF0 (0x0CU) +#define RTC_TPCR0_TPNF0_0 (0x04U) +#define RTC_TPCR0_TPNF0_1 (0x08U) +#define RTC_TPCR0_TPRSTE0_POS (4U) +#define RTC_TPCR0_TPRSTE0 (0x10U) +#define RTC_TPCR0_TPIE0_POS (5U) +#define RTC_TPCR0_TPIE0 (0x20U) +#define RTC_TPCR0_TSTPE0_POS (6U) +#define RTC_TPCR0_TSTPE0 (0x40U) +#define RTC_TPCR0_TPEN0_POS (7U) +#define RTC_TPCR0_TPEN0 (0x80U) + +/* Bit definition for RTC_TPCR1 register */ +#define RTC_TPCR1_TPCT1_POS (0U) +#define RTC_TPCR1_TPCT1 (0x03U) +#define RTC_TPCR1_TPCT1_0 (0x01U) +#define RTC_TPCR1_TPCT1_1 (0x02U) +#define RTC_TPCR1_TPNF1_POS (2U) +#define RTC_TPCR1_TPNF1 (0x0CU) +#define RTC_TPCR1_TPNF1_0 (0x04U) +#define RTC_TPCR1_TPNF1_1 (0x08U) +#define RTC_TPCR1_TPRSTE1_POS (4U) +#define RTC_TPCR1_TPRSTE1 (0x10U) +#define RTC_TPCR1_TPIE1_POS (5U) +#define RTC_TPCR1_TPIE1 (0x20U) +#define RTC_TPCR1_TSTPE1_POS (6U) +#define RTC_TPCR1_TSTPE1 (0x40U) +#define RTC_TPCR1_TPEN1_POS (7U) +#define RTC_TPCR1_TPEN1 (0x80U) + +/* Bit definition for RTC_TPSR register */ +#define RTC_TPSR_TPF0_POS (0U) +#define RTC_TPSR_TPF0 (0x01U) +#define RTC_TPSR_TPF1_POS (1U) +#define RTC_TPSR_TPF1 (0x02U) +#define RTC_TPSR_TPOVF_POS (2U) +#define RTC_TPSR_TPOVF (0x04U) + +/* Bit definition for RTC_SECTP register */ +#define RTC_SECTP_SECTPU_POS (0U) +#define RTC_SECTP_SECTPU (0x0FU) +#define RTC_SECTP_SECTPD_POS (4U) +#define RTC_SECTP_SECTPD (0x70U) + +/* Bit definition for RTC_MINTP register */ +#define RTC_MINTP_MINTPU_POS (0U) +#define RTC_MINTP_MINTPU (0x0FU) +#define RTC_MINTP_MINTPD_POS (4U) +#define RTC_MINTP_MINTPD (0x70U) + +/* Bit definition for RTC_HOURTP register */ +#define RTC_HOURTP_HOURTPU_POS (0U) +#define RTC_HOURTP_HOURTPU (0x0FU) +#define RTC_HOURTP_HOURTPU_0 (0x01U) +#define RTC_HOURTP_HOURTPU_1 (0x02U) +#define RTC_HOURTP_HOURTPU_2 (0x04U) +#define RTC_HOURTP_HOURTPU_3 (0x08U) +#define RTC_HOURTP_HOURTPD_POS (4U) +#define RTC_HOURTP_HOURTPD (0x30U) +#define RTC_HOURTP_HOURTPD_0 (0x10U) +#define RTC_HOURTP_HOURTPD_1 (0x20U) + +/* Bit definition for RTC_DAYTP register */ +#define RTC_DAYTP_DAYTPU_POS (0U) +#define RTC_DAYTP_DAYTPU (0x0FU) +#define RTC_DAYTP_DAYTPD_POS (4U) +#define RTC_DAYTP_DAYTPD (0x30U) + +/* Bit definition for RTC_MONTP register */ +#define RTC_MONTP_MONTP (0x1FU) + +/******************************************************************************* + Bit definition for Peripheral SDIOC +*******************************************************************************/ +/* Bit definition for SDIOC_BLKSIZE register */ +#define SDIOC_BLKSIZE_TBS (0x0FFFU) + +/* Bit definition for SDIOC_BLKCNT register */ +#define SDIOC_BLKCNT (0xFFFFU) + +/* Bit definition for SDIOC_ARG0 register */ +#define SDIOC_ARG0 (0xFFFFU) + +/* Bit definition for SDIOC_ARG1 register */ +#define SDIOC_ARG1 (0xFFFFU) + +/* Bit definition for SDIOC_TRANSMODE register */ +#define SDIOC_TRANSMODE_BCE_POS (1U) +#define SDIOC_TRANSMODE_BCE (0x0002U) +#define SDIOC_TRANSMODE_ATCEN_POS (2U) +#define SDIOC_TRANSMODE_ATCEN (0x000CU) +#define SDIOC_TRANSMODE_ATCEN_0 (0x0004U) +#define SDIOC_TRANSMODE_ATCEN_1 (0x0008U) +#define SDIOC_TRANSMODE_DDIR_POS (4U) +#define SDIOC_TRANSMODE_DDIR (0x0010U) +#define SDIOC_TRANSMODE_MULB_POS (5U) +#define SDIOC_TRANSMODE_MULB (0x0020U) + +/* Bit definition for SDIOC_CMD register */ +#define SDIOC_CMD_RESTYP_POS (0U) +#define SDIOC_CMD_RESTYP (0x0003U) +#define SDIOC_CMD_RESTYP_0 (0x0001U) +#define SDIOC_CMD_RESTYP_1 (0x0002U) +#define SDIOC_CMD_CCE_POS (3U) +#define SDIOC_CMD_CCE (0x0008U) +#define SDIOC_CMD_ICE_POS (4U) +#define SDIOC_CMD_ICE (0x0010U) +#define SDIOC_CMD_DAT_POS (5U) +#define SDIOC_CMD_DAT (0x0020U) +#define SDIOC_CMD_TYP_POS (6U) +#define SDIOC_CMD_TYP (0x00C0U) +#define SDIOC_CMD_TYP_0 (0x0040U) +#define SDIOC_CMD_TYP_1 (0x0080U) +#define SDIOC_CMD_IDX_POS (8U) +#define SDIOC_CMD_IDX (0x3F00U) +#define SDIOC_CMD_IDX_0 (0x0100U) +#define SDIOC_CMD_IDX_1 (0x0200U) +#define SDIOC_CMD_IDX_2 (0x0400U) +#define SDIOC_CMD_IDX_3 (0x0800U) +#define SDIOC_CMD_IDX_4 (0x1000U) +#define SDIOC_CMD_IDX_5 (0x2000U) + +/* Bit definition for SDIOC_RESP0 register */ +#define SDIOC_RESP0 (0xFFFFU) + +/* Bit definition for SDIOC_RESP1 register */ +#define SDIOC_RESP1 (0xFFFFU) + +/* Bit definition for SDIOC_RESP2 register */ +#define SDIOC_RESP2 (0xFFFFU) + +/* Bit definition for SDIOC_RESP3 register */ +#define SDIOC_RESP3 (0xFFFFU) + +/* Bit definition for SDIOC_RESP4 register */ +#define SDIOC_RESP4 (0xFFFFU) + +/* Bit definition for SDIOC_RESP5 register */ +#define SDIOC_RESP5 (0xFFFFU) + +/* Bit definition for SDIOC_RESP6 register */ +#define SDIOC_RESP6 (0xFFFFU) + +/* Bit definition for SDIOC_RESP7 register */ +#define SDIOC_RESP7 (0xFFFFU) + +/* Bit definition for SDIOC_BUF0 register */ +#define SDIOC_BUF0 (0xFFFFU) + +/* Bit definition for SDIOC_BUF1 register */ +#define SDIOC_BUF1 (0xFFFFU) + +/* Bit definition for SDIOC_PSTAT register */ +#define SDIOC_PSTAT_CIC_POS (0U) +#define SDIOC_PSTAT_CIC (0x00000001UL) +#define SDIOC_PSTAT_CID_POS (1U) +#define SDIOC_PSTAT_CID (0x00000002UL) +#define SDIOC_PSTAT_DA_POS (2U) +#define SDIOC_PSTAT_DA (0x00000004UL) +#define SDIOC_PSTAT_WTA_POS (8U) +#define SDIOC_PSTAT_WTA (0x00000100UL) +#define SDIOC_PSTAT_RTA_POS (9U) +#define SDIOC_PSTAT_RTA (0x00000200UL) +#define SDIOC_PSTAT_BWE_POS (10U) +#define SDIOC_PSTAT_BWE (0x00000400UL) +#define SDIOC_PSTAT_BRE_POS (11U) +#define SDIOC_PSTAT_BRE (0x00000800UL) +#define SDIOC_PSTAT_CIN_POS (16U) +#define SDIOC_PSTAT_CIN (0x00010000UL) +#define SDIOC_PSTAT_CSS_POS (17U) +#define SDIOC_PSTAT_CSS (0x00020000UL) +#define SDIOC_PSTAT_CDL_POS (18U) +#define SDIOC_PSTAT_CDL (0x00040000UL) +#define SDIOC_PSTAT_WPL_POS (19U) +#define SDIOC_PSTAT_WPL (0x00080000UL) +#define SDIOC_PSTAT_DATL_POS (20U) +#define SDIOC_PSTAT_DATL (0x00F00000UL) +#define SDIOC_PSTAT_DATL_0 (0x00100000UL) +#define SDIOC_PSTAT_DATL_1 (0x00200000UL) +#define SDIOC_PSTAT_DATL_2 (0x00400000UL) +#define SDIOC_PSTAT_DATL_3 (0x00800000UL) +#define SDIOC_PSTAT_CMDL_POS (24U) +#define SDIOC_PSTAT_CMDL (0x01000000UL) + +/* Bit definition for SDIOC_HOSTCON register */ +#define SDIOC_HOSTCON_DW_POS (1U) +#define SDIOC_HOSTCON_DW (0x02U) +#define SDIOC_HOSTCON_HSEN_POS (2U) +#define SDIOC_HOSTCON_HSEN (0x04U) +#define SDIOC_HOSTCON_EXDW_POS (5U) +#define SDIOC_HOSTCON_EXDW (0x20U) +#define SDIOC_HOSTCON_CDTL_POS (6U) +#define SDIOC_HOSTCON_CDTL (0x40U) +#define SDIOC_HOSTCON_CDSS_POS (7U) +#define SDIOC_HOSTCON_CDSS (0x80U) + +/* Bit definition for SDIOC_PWRCON register */ +#define SDIOC_PWRCON_PWON (0x01U) + +/* Bit definition for SDIOC_BLKGPCON register */ +#define SDIOC_BLKGPCON_SABGR_POS (0U) +#define SDIOC_BLKGPCON_SABGR (0x01U) +#define SDIOC_BLKGPCON_CR_POS (1U) +#define SDIOC_BLKGPCON_CR (0x02U) +#define SDIOC_BLKGPCON_RWC_POS (2U) +#define SDIOC_BLKGPCON_RWC (0x04U) +#define SDIOC_BLKGPCON_IABG_POS (3U) +#define SDIOC_BLKGPCON_IABG (0x08U) + +/* Bit definition for SDIOC_CLKCON register */ +#define SDIOC_CLKCON_ICE_POS (0U) +#define SDIOC_CLKCON_ICE (0x0001U) +#define SDIOC_CLKCON_CE_POS (2U) +#define SDIOC_CLKCON_CE (0x0004U) +#define SDIOC_CLKCON_FS_POS (8U) +#define SDIOC_CLKCON_FS (0xFF00U) +#define SDIOC_CLKCON_FS_0 (0x0100U) +#define SDIOC_CLKCON_FS_1 (0x0200U) +#define SDIOC_CLKCON_FS_2 (0x0400U) +#define SDIOC_CLKCON_FS_3 (0x0800U) +#define SDIOC_CLKCON_FS_4 (0x1000U) +#define SDIOC_CLKCON_FS_5 (0x2000U) +#define SDIOC_CLKCON_FS_6 (0x4000U) +#define SDIOC_CLKCON_FS_7 (0x8000U) + +/* Bit definition for SDIOC_TOUTCON register */ +#define SDIOC_TOUTCON_DTO (0x0FU) + +/* Bit definition for SDIOC_SFTRST register */ +#define SDIOC_SFTRST_RSTA_POS (0U) +#define SDIOC_SFTRST_RSTA (0x01U) +#define SDIOC_SFTRST_RSTC_POS (1U) +#define SDIOC_SFTRST_RSTC (0x02U) +#define SDIOC_SFTRST_RSTD_POS (2U) +#define SDIOC_SFTRST_RSTD (0x04U) + +/* Bit definition for SDIOC_NORINTST register */ +#define SDIOC_NORINTST_CC_POS (0U) +#define SDIOC_NORINTST_CC (0x0001U) +#define SDIOC_NORINTST_TC_POS (1U) +#define SDIOC_NORINTST_TC (0x0002U) +#define SDIOC_NORINTST_BGE_POS (2U) +#define SDIOC_NORINTST_BGE (0x0004U) +#define SDIOC_NORINTST_BWR_POS (4U) +#define SDIOC_NORINTST_BWR (0x0010U) +#define SDIOC_NORINTST_BRR_POS (5U) +#define SDIOC_NORINTST_BRR (0x0020U) +#define SDIOC_NORINTST_CIST_POS (6U) +#define SDIOC_NORINTST_CIST (0x0040U) +#define SDIOC_NORINTST_CRM_POS (7U) +#define SDIOC_NORINTST_CRM (0x0080U) +#define SDIOC_NORINTST_CINT_POS (8U) +#define SDIOC_NORINTST_CINT (0x0100U) +#define SDIOC_NORINTST_EI_POS (15U) +#define SDIOC_NORINTST_EI (0x8000U) + +/* Bit definition for SDIOC_ERRINTST register */ +#define SDIOC_ERRINTST_CTOE_POS (0U) +#define SDIOC_ERRINTST_CTOE (0x0001U) +#define SDIOC_ERRINTST_CCE_POS (1U) +#define SDIOC_ERRINTST_CCE (0x0002U) +#define SDIOC_ERRINTST_CEBE_POS (2U) +#define SDIOC_ERRINTST_CEBE (0x0004U) +#define SDIOC_ERRINTST_CIE_POS (3U) +#define SDIOC_ERRINTST_CIE (0x0008U) +#define SDIOC_ERRINTST_DTOE_POS (4U) +#define SDIOC_ERRINTST_DTOE (0x0010U) +#define SDIOC_ERRINTST_DCE_POS (5U) +#define SDIOC_ERRINTST_DCE (0x0020U) +#define SDIOC_ERRINTST_DEBE_POS (6U) +#define SDIOC_ERRINTST_DEBE (0x0040U) +#define SDIOC_ERRINTST_ACE_POS (8U) +#define SDIOC_ERRINTST_ACE (0x0100U) + +/* Bit definition for SDIOC_NORINTSTEN register */ +#define SDIOC_NORINTSTEN_CCEN_POS (0U) +#define SDIOC_NORINTSTEN_CCEN (0x0001U) +#define SDIOC_NORINTSTEN_TCEN_POS (1U) +#define SDIOC_NORINTSTEN_TCEN (0x0002U) +#define SDIOC_NORINTSTEN_BGEEN_POS (2U) +#define SDIOC_NORINTSTEN_BGEEN (0x0004U) +#define SDIOC_NORINTSTEN_BWREN_POS (4U) +#define SDIOC_NORINTSTEN_BWREN (0x0010U) +#define SDIOC_NORINTSTEN_BRREN_POS (5U) +#define SDIOC_NORINTSTEN_BRREN (0x0020U) +#define SDIOC_NORINTSTEN_CISTEN_POS (6U) +#define SDIOC_NORINTSTEN_CISTEN (0x0040U) +#define SDIOC_NORINTSTEN_CRMEN_POS (7U) +#define SDIOC_NORINTSTEN_CRMEN (0x0080U) +#define SDIOC_NORINTSTEN_CINTEN_POS (8U) +#define SDIOC_NORINTSTEN_CINTEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSTEN register */ +#define SDIOC_ERRINTSTEN_CTOEEN_POS (0U) +#define SDIOC_ERRINTSTEN_CTOEEN (0x0001U) +#define SDIOC_ERRINTSTEN_CCEEN_POS (1U) +#define SDIOC_ERRINTSTEN_CCEEN (0x0002U) +#define SDIOC_ERRINTSTEN_CEBEEN_POS (2U) +#define SDIOC_ERRINTSTEN_CEBEEN (0x0004U) +#define SDIOC_ERRINTSTEN_CIEEN_POS (3U) +#define SDIOC_ERRINTSTEN_CIEEN (0x0008U) +#define SDIOC_ERRINTSTEN_DTOEEN_POS (4U) +#define SDIOC_ERRINTSTEN_DTOEEN (0x0010U) +#define SDIOC_ERRINTSTEN_DCEEN_POS (5U) +#define SDIOC_ERRINTSTEN_DCEEN (0x0020U) +#define SDIOC_ERRINTSTEN_DEBEEN_POS (6U) +#define SDIOC_ERRINTSTEN_DEBEEN (0x0040U) +#define SDIOC_ERRINTSTEN_ACEEN_POS (8U) +#define SDIOC_ERRINTSTEN_ACEEN (0x0100U) + +/* Bit definition for SDIOC_NORINTSGEN register */ +#define SDIOC_NORINTSGEN_CCSEN_POS (0U) +#define SDIOC_NORINTSGEN_CCSEN (0x0001U) +#define SDIOC_NORINTSGEN_TCSEN_POS (1U) +#define SDIOC_NORINTSGEN_TCSEN (0x0002U) +#define SDIOC_NORINTSGEN_BGESEN_POS (2U) +#define SDIOC_NORINTSGEN_BGESEN (0x0004U) +#define SDIOC_NORINTSGEN_BWRSEN_POS (4U) +#define SDIOC_NORINTSGEN_BWRSEN (0x0010U) +#define SDIOC_NORINTSGEN_BRRSEN_POS (5U) +#define SDIOC_NORINTSGEN_BRRSEN (0x0020U) +#define SDIOC_NORINTSGEN_CISTSEN_POS (6U) +#define SDIOC_NORINTSGEN_CISTSEN (0x0040U) +#define SDIOC_NORINTSGEN_CRMSEN_POS (7U) +#define SDIOC_NORINTSGEN_CRMSEN (0x0080U) +#define SDIOC_NORINTSGEN_CINTSEN_POS (8U) +#define SDIOC_NORINTSGEN_CINTSEN (0x0100U) + +/* Bit definition for SDIOC_ERRINTSGEN register */ +#define SDIOC_ERRINTSGEN_CTOESEN_POS (0U) +#define SDIOC_ERRINTSGEN_CTOESEN (0x0001U) +#define SDIOC_ERRINTSGEN_CCESEN_POS (1U) +#define SDIOC_ERRINTSGEN_CCESEN (0x0002U) +#define SDIOC_ERRINTSGEN_CEBESEN_POS (2U) +#define SDIOC_ERRINTSGEN_CEBESEN (0x0004U) +#define SDIOC_ERRINTSGEN_CIESEN_POS (3U) +#define SDIOC_ERRINTSGEN_CIESEN (0x0008U) +#define SDIOC_ERRINTSGEN_DTOESEN_POS (4U) +#define SDIOC_ERRINTSGEN_DTOESEN (0x0010U) +#define SDIOC_ERRINTSGEN_DCESEN_POS (5U) +#define SDIOC_ERRINTSGEN_DCESEN (0x0020U) +#define SDIOC_ERRINTSGEN_DEBESEN_POS (6U) +#define SDIOC_ERRINTSGEN_DEBESEN (0x0040U) +#define SDIOC_ERRINTSGEN_ACESEN_POS (8U) +#define SDIOC_ERRINTSGEN_ACESEN (0x0100U) + +/* Bit definition for SDIOC_ATCERRST register */ +#define SDIOC_ATCERRST_NE_POS (0U) +#define SDIOC_ATCERRST_NE (0x0001U) +#define SDIOC_ATCERRST_TOE_POS (1U) +#define SDIOC_ATCERRST_TOE (0x0002U) +#define SDIOC_ATCERRST_CE_POS (2U) +#define SDIOC_ATCERRST_CE (0x0004U) +#define SDIOC_ATCERRST_EBE_POS (3U) +#define SDIOC_ATCERRST_EBE (0x0008U) +#define SDIOC_ATCERRST_IE_POS (4U) +#define SDIOC_ATCERRST_IE (0x0010U) +#define SDIOC_ATCERRST_CMDE_POS (7U) +#define SDIOC_ATCERRST_CMDE (0x0080U) + +/* Bit definition for SDIOC_FEA register */ +#define SDIOC_FEA_FNE_POS (0U) +#define SDIOC_FEA_FNE (0x0001U) +#define SDIOC_FEA_FTOE_POS (1U) +#define SDIOC_FEA_FTOE (0x0002U) +#define SDIOC_FEA_FCE_POS (2U) +#define SDIOC_FEA_FCE (0x0004U) +#define SDIOC_FEA_FEBE_POS (3U) +#define SDIOC_FEA_FEBE (0x0008U) +#define SDIOC_FEA_FIE_POS (4U) +#define SDIOC_FEA_FIE (0x0010U) +#define SDIOC_FEA_FCMDE_POS (7U) +#define SDIOC_FEA_FCMDE (0x0080U) + +/* Bit definition for SDIOC_FEE register */ +#define SDIOC_FEE_FCTOE_POS (0U) +#define SDIOC_FEE_FCTOE (0x0001U) +#define SDIOC_FEE_FCCE_POS (1U) +#define SDIOC_FEE_FCCE (0x0002U) +#define SDIOC_FEE_FCEBE_POS (2U) +#define SDIOC_FEE_FCEBE (0x0004U) +#define SDIOC_FEE_FCIE_POS (3U) +#define SDIOC_FEE_FCIE (0x0008U) +#define SDIOC_FEE_FDTOE_POS (4U) +#define SDIOC_FEE_FDTOE (0x0010U) +#define SDIOC_FEE_FDCE_POS (5U) +#define SDIOC_FEE_FDCE (0x0020U) +#define SDIOC_FEE_FDEBE_POS (6U) +#define SDIOC_FEE_FDEBE (0x0040U) +#define SDIOC_FEE_FACE_POS (8U) +#define SDIOC_FEE_FACE (0x0100U) + +/******************************************************************************* + Bit definition for Peripheral SMC +*******************************************************************************/ +/* Bit definition for SMC_STSR register */ +#define SMC_STSR_STATUS (0x00000001UL) + +/* Bit definition for SMC_STCR0 register */ +#define SMC_STCR0_LPWIR_POS (2U) +#define SMC_STCR0_LPWIR (0x00000004UL) + +/* Bit definition for SMC_STCR1 register */ +#define SMC_STCR1_LPWOR_POS (2U) +#define SMC_STCR1_LPWOR (0x00000004UL) + +/* Bit definition for SMC_CMDR register */ +#define SMC_CMDR_CMDADD_POS (0U) +#define SMC_CMDR_CMDADD (0x000FFFFFUL) +#define SMC_CMDR_CRES_POS (20U) +#define SMC_CMDR_CRES (0x00100000UL) +#define SMC_CMDR_CMD_POS (21U) +#define SMC_CMDR_CMD (0x00600000UL) +#define SMC_CMDR_CMD_0 (0x00200000UL) +#define SMC_CMDR_CMD_1 (0x00400000UL) +#define SMC_CMDR_CMDCHIP_POS (23U) +#define SMC_CMDR_CMDCHIP (0x03800000UL) +#define SMC_CMDR_CMDCHIP_0 (0x00800000UL) +#define SMC_CMDR_CMDCHIP_1 (0x01000000UL) +#define SMC_CMDR_CMDCHIP_2 (0x02000000UL) + +/* Bit definition for SMC_TMCR register */ +#define SMC_TMCR_T_RC_POS (0U) +#define SMC_TMCR_T_RC (0x0000000FUL) +#define SMC_TMCR_T_WC_POS (4U) +#define SMC_TMCR_T_WC (0x000000F0UL) +#define SMC_TMCR_T_CEOE_POS (8U) +#define SMC_TMCR_T_CEOE (0x00000700UL) +#define SMC_TMCR_T_WP_POS (12U) +#define SMC_TMCR_T_WP (0x00007000UL) +#define SMC_TMCR_T_PC_POS (16U) +#define SMC_TMCR_T_PC (0x00070000UL) +#define SMC_TMCR_T_TR_POS (20U) +#define SMC_TMCR_T_TR (0x00700000UL) + +/* Bit definition for SMC_CPCR register */ +#define SMC_CPCR_RSYN_POS (0U) +#define SMC_CPCR_RSYN (0x00000001UL) +#define SMC_CPCR_RBL_POS (1U) +#define SMC_CPCR_RBL (0x0000000EUL) +#define SMC_CPCR_RBL_0 (0x00000002UL) +#define SMC_CPCR_RBL_1 (0x00000004UL) +#define SMC_CPCR_RBL_2 (0x00000008UL) +#define SMC_CPCR_WSYN_POS (4U) +#define SMC_CPCR_WSYN (0x00000010UL) +#define SMC_CPCR_WBL_POS (5U) +#define SMC_CPCR_WBL (0x000000E0UL) +#define SMC_CPCR_WBL_0 (0x00000020UL) +#define SMC_CPCR_WBL_1 (0x00000040UL) +#define SMC_CPCR_WBL_2 (0x00000080UL) +#define SMC_CPCR_MW_POS (8U) +#define SMC_CPCR_MW (0x00000300UL) +#define SMC_CPCR_MW_0 (0x00000100UL) +#define SMC_CPCR_MW_1 (0x00000200UL) +#define SMC_CPCR_BAAS_POS (10U) +#define SMC_CPCR_BAAS (0x00000400UL) +#define SMC_CPCR_ADVS_POS (11U) +#define SMC_CPCR_ADVS (0x00000800UL) +#define SMC_CPCR_BLSS_POS (12U) +#define SMC_CPCR_BLSS (0x00001000UL) + +/* Bit definition for SMC_RFTR register */ +#define SMC_RFTR_REFPRD (0x0000000FUL) + +/* Bit definition for SMC_TMSR register */ +#define SMC_TMSR_T_RC_POS (0U) +#define SMC_TMSR_T_RC (0x0000000FUL) +#define SMC_TMSR_T_WC_POS (4U) +#define SMC_TMSR_T_WC (0x000000F0UL) +#define SMC_TMSR_T_CEOE_POS (8U) +#define SMC_TMSR_T_CEOE (0x00000700UL) +#define SMC_TMSR_T_WP_POS (12U) +#define SMC_TMSR_T_WP (0x00007000UL) +#define SMC_TMSR_T_PC_POS (16U) +#define SMC_TMSR_T_PC (0x00070000UL) +#define SMC_TMSR_T_TR_POS (20U) +#define SMC_TMSR_T_TR (0x00700000UL) + +/* Bit definition for SMC_CPSR register */ +#define SMC_CPSR_RSYN_POS (0U) +#define SMC_CPSR_RSYN (0x00000001UL) +#define SMC_CPSR_RBL_POS (1U) +#define SMC_CPSR_RBL (0x0000000EUL) +#define SMC_CPSR_RBL_0 (0x00000002UL) +#define SMC_CPSR_RBL_1 (0x00000004UL) +#define SMC_CPSR_RBL_2 (0x00000008UL) +#define SMC_CPSR_WSYN_POS (4U) +#define SMC_CPSR_WSYN (0x00000010UL) +#define SMC_CPSR_WBL_POS (5U) +#define SMC_CPSR_WBL (0x000000E0UL) +#define SMC_CPSR_WBL_0 (0x00000020UL) +#define SMC_CPSR_WBL_1 (0x00000040UL) +#define SMC_CPSR_WBL_2 (0x00000080UL) +#define SMC_CPSR_MW_POS (8U) +#define SMC_CPSR_MW (0x00000300UL) +#define SMC_CPSR_MW_0 (0x00000100UL) +#define SMC_CPSR_MW_1 (0x00000200UL) +#define SMC_CPSR_BAAS_POS (10U) +#define SMC_CPSR_BAAS (0x00000400UL) +#define SMC_CPSR_ADVS_POS (11U) +#define SMC_CPSR_ADVS (0x00000800UL) +#define SMC_CPSR_BLSS_POS (12U) +#define SMC_CPSR_BLSS (0x00001000UL) +#define SMC_CPSR_ADDMSK_POS (16U) +#define SMC_CPSR_ADDMSK (0x00FF0000UL) +#define SMC_CPSR_ADDMAT_POS (24U) +#define SMC_CPSR_ADDMAT (0xFF000000UL) + +/* Bit definition for SMC_BACR register */ +#define SMC_BACR_MUXMD_POS (4U) +#define SMC_BACR_MUXMD (0x00000010UL) + +/* Bit definition for SMC_CSCR0 register */ +#define SMC_CSCR0_ADDMSK0_POS (0U) +#define SMC_CSCR0_ADDMSK0 (0x000000FFUL) +#define SMC_CSCR0_ADDMSK1_POS (8U) +#define SMC_CSCR0_ADDMSK1 (0x0000FF00UL) +#define SMC_CSCR0_ADDMSK2_POS (16U) +#define SMC_CSCR0_ADDMSK2 (0x00FF0000UL) +#define SMC_CSCR0_ADDMSK3_POS (24U) +#define SMC_CSCR0_ADDMSK3 (0xFF000000UL) + +/* Bit definition for SMC_CSCR1 register */ +#define SMC_CSCR1_ADDMAT0_POS (0U) +#define SMC_CSCR1_ADDMAT0 (0x000000FFUL) +#define SMC_CSCR1_ADDMAT1_POS (8U) +#define SMC_CSCR1_ADDMAT1 (0x0000FF00UL) +#define SMC_CSCR1_ADDMAT2_POS (16U) +#define SMC_CSCR1_ADDMAT2 (0x00FF0000UL) +#define SMC_CSCR1_ADDMAT3_POS (24U) +#define SMC_CSCR1_ADDMAT3 (0xFF000000UL) + +/******************************************************************************* + Bit definition for Peripheral SPI +*******************************************************************************/ +/* Bit definition for SPI_DR register */ +#define SPI_DR (0xFFFFFFFFUL) + +/* Bit definition for SPI_CR1 register */ +#define SPI_CR1_SPIMDS_POS (0U) +#define SPI_CR1_SPIMDS (0x00000001UL) +#define SPI_CR1_TXMDS_POS (1U) +#define SPI_CR1_TXMDS (0x00000002UL) +#define SPI_CR1_MSTR_POS (3U) +#define SPI_CR1_MSTR (0x00000008UL) +#define SPI_CR1_SPLPBK_POS (4U) +#define SPI_CR1_SPLPBK (0x00000010UL) +#define SPI_CR1_SPLPBK2_POS (5U) +#define SPI_CR1_SPLPBK2 (0x00000020UL) +#define SPI_CR1_SPE_POS (6U) +#define SPI_CR1_SPE (0x00000040UL) +#define SPI_CR1_CSUSPE_POS (7U) +#define SPI_CR1_CSUSPE (0x00000080UL) +#define SPI_CR1_EIE_POS (8U) +#define SPI_CR1_EIE (0x00000100UL) +#define SPI_CR1_TXIE_POS (9U) +#define SPI_CR1_TXIE (0x00000200UL) +#define SPI_CR1_RXIE_POS (10U) +#define SPI_CR1_RXIE (0x00000400UL) +#define SPI_CR1_IDIE_POS (11U) +#define SPI_CR1_IDIE (0x00000800UL) +#define SPI_CR1_MODFE_POS (12U) +#define SPI_CR1_MODFE (0x00001000UL) +#define SPI_CR1_PATE_POS (13U) +#define SPI_CR1_PATE (0x00002000UL) +#define SPI_CR1_PAOE_POS (14U) +#define SPI_CR1_PAOE (0x00004000UL) +#define SPI_CR1_PAE_POS (15U) +#define SPI_CR1_PAE (0x00008000UL) + +/* Bit definition for SPI_CFG1 register */ +#define SPI_CFG1_FTHLV_POS (0U) +#define SPI_CFG1_FTHLV (0x00000003UL) +#define SPI_CFG1_FTHLV_0 (0x00000001UL) +#define SPI_CFG1_FTHLV_1 (0x00000002UL) +#define SPI_CFG1_SPRDTD_POS (6U) +#define SPI_CFG1_SPRDTD (0x00000040UL) +#define SPI_CFG1_SS0PV_POS (8U) +#define SPI_CFG1_SS0PV (0x00000100UL) +#define SPI_CFG1_SS1PV_POS (9U) +#define SPI_CFG1_SS1PV (0x00000200UL) +#define SPI_CFG1_SS2PV_POS (10U) +#define SPI_CFG1_SS2PV (0x00000400UL) +#define SPI_CFG1_SS3PV_POS (11U) +#define SPI_CFG1_SS3PV (0x00000800UL) +#define SPI_CFG1_MSSI_POS (20U) +#define SPI_CFG1_MSSI (0x00700000UL) +#define SPI_CFG1_MSSI_0 (0x00100000UL) +#define SPI_CFG1_MSSI_1 (0x00200000UL) +#define SPI_CFG1_MSSI_2 (0x00400000UL) +#define SPI_CFG1_MSSDL_POS (24U) +#define SPI_CFG1_MSSDL (0x07000000UL) +#define SPI_CFG1_MSSDL_0 (0x01000000UL) +#define SPI_CFG1_MSSDL_1 (0x02000000UL) +#define SPI_CFG1_MSSDL_2 (0x04000000UL) +#define SPI_CFG1_MIDI_POS (28U) +#define SPI_CFG1_MIDI (0x70000000UL) +#define SPI_CFG1_MIDI_0 (0x10000000UL) +#define SPI_CFG1_MIDI_1 (0x20000000UL) +#define SPI_CFG1_MIDI_2 (0x40000000UL) + +/* Bit definition for SPI_SR register */ +#define SPI_SR_OVRERF_POS (0U) +#define SPI_SR_OVRERF (0x00000001UL) +#define SPI_SR_IDLNF_POS (1U) +#define SPI_SR_IDLNF (0x00000002UL) +#define SPI_SR_MODFERF_POS (2U) +#define SPI_SR_MODFERF (0x00000004UL) +#define SPI_SR_PERF_POS (3U) +#define SPI_SR_PERF (0x00000008UL) +#define SPI_SR_UDRERF_POS (4U) +#define SPI_SR_UDRERF (0x00000010UL) +#define SPI_SR_TDEF_POS (5U) +#define SPI_SR_TDEF (0x00000020UL) +#define SPI_SR_RDFF_POS (7U) +#define SPI_SR_RDFF (0x00000080UL) + +/* Bit definition for SPI_CFG2 register */ +#define SPI_CFG2_CPHA_POS (0U) +#define SPI_CFG2_CPHA (0x00000001UL) +#define SPI_CFG2_CPOL_POS (1U) +#define SPI_CFG2_CPOL (0x00000002UL) +#define SPI_CFG2_MBR_POS (2U) +#define SPI_CFG2_MBR (0x0000001CUL) +#define SPI_CFG2_MBR_0 (0x00000004UL) +#define SPI_CFG2_MBR_1 (0x00000008UL) +#define SPI_CFG2_MBR_2 (0x00000010UL) +#define SPI_CFG2_SSA_POS (5U) +#define SPI_CFG2_SSA (0x000000E0UL) +#define SPI_CFG2_SSA_0 (0x00000020UL) +#define SPI_CFG2_SSA_1 (0x00000040UL) +#define SPI_CFG2_SSA_2 (0x00000080UL) +#define SPI_CFG2_DSIZE_POS (8U) +#define SPI_CFG2_DSIZE (0x00000F00UL) +#define SPI_CFG2_DSIZE_0 (0x00000100UL) +#define SPI_CFG2_DSIZE_1 (0x00000200UL) +#define SPI_CFG2_DSIZE_2 (0x00000400UL) +#define SPI_CFG2_DSIZE_3 (0x00000800UL) +#define SPI_CFG2_LSBF_POS (12U) +#define SPI_CFG2_LSBF (0x00001000UL) +#define SPI_CFG2_MIDIE_POS (13U) +#define SPI_CFG2_MIDIE (0x00002000UL) +#define SPI_CFG2_MSSDLE_POS (14U) +#define SPI_CFG2_MSSDLE (0x00004000UL) +#define SPI_CFG2_MSSIE_POS (15U) +#define SPI_CFG2_MSSIE (0x00008000UL) + +/******************************************************************************* + Bit definition for Peripheral SRAMC +*******************************************************************************/ +/* Bit definition for SRAMC_WTCR register */ +#define SRAMC_WTCR_SRAM123RWT_POS (0U) +#define SRAMC_WTCR_SRAM123RWT (0x00000007UL) +#define SRAMC_WTCR_SRAM123RWT_0 (0x00000001UL) +#define SRAMC_WTCR_SRAM123RWT_1 (0x00000002UL) +#define SRAMC_WTCR_SRAM123RWT_2 (0x00000004UL) +#define SRAMC_WTCR_SRAM123WWT_POS (4U) +#define SRAMC_WTCR_SRAM123WWT (0x00000070UL) +#define SRAMC_WTCR_SRAM123WWT_0 (0x00000010UL) +#define SRAMC_WTCR_SRAM123WWT_1 (0x00000020UL) +#define SRAMC_WTCR_SRAM123WWT_2 (0x00000040UL) +#define SRAMC_WTCR_SRAM4RWT_POS (8U) +#define SRAMC_WTCR_SRAM4RWT (0x00000700UL) +#define SRAMC_WTCR_SRAM4RWT_0 (0x00000100UL) +#define SRAMC_WTCR_SRAM4RWT_1 (0x00000200UL) +#define SRAMC_WTCR_SRAM4RWT_2 (0x00000400UL) +#define SRAMC_WTCR_SRAM4WWT_POS (12U) +#define SRAMC_WTCR_SRAM4WWT (0x00007000UL) +#define SRAMC_WTCR_SRAM4WWT_0 (0x00001000UL) +#define SRAMC_WTCR_SRAM4WWT_1 (0x00002000UL) +#define SRAMC_WTCR_SRAM4WWT_2 (0x00004000UL) +#define SRAMC_WTCR_SRAMHRWT_POS (16U) +#define SRAMC_WTCR_SRAMHRWT (0x00070000UL) +#define SRAMC_WTCR_SRAMHRWT_0 (0x00010000UL) +#define SRAMC_WTCR_SRAMHRWT_1 (0x00020000UL) +#define SRAMC_WTCR_SRAMHRWT_2 (0x00040000UL) +#define SRAMC_WTCR_SRAMHWWT_POS (20U) +#define SRAMC_WTCR_SRAMHWWT (0x00700000UL) +#define SRAMC_WTCR_SRAMHWWT_0 (0x00100000UL) +#define SRAMC_WTCR_SRAMHWWT_1 (0x00200000UL) +#define SRAMC_WTCR_SRAMHWWT_2 (0x00400000UL) +#define SRAMC_WTCR_SRAMBRWT_POS (24U) +#define SRAMC_WTCR_SRAMBRWT (0x07000000UL) +#define SRAMC_WTCR_SRAMBRWT_0 (0x01000000UL) +#define SRAMC_WTCR_SRAMBRWT_1 (0x02000000UL) +#define SRAMC_WTCR_SRAMBRWT_2 (0x04000000UL) +#define SRAMC_WTCR_SRAMBWWT_POS (28U) +#define SRAMC_WTCR_SRAMBWWT (0x70000000UL) +#define SRAMC_WTCR_SRAMBWWT_0 (0x10000000UL) +#define SRAMC_WTCR_SRAMBWWT_1 (0x20000000UL) +#define SRAMC_WTCR_SRAMBWWT_2 (0x40000000UL) + +/* Bit definition for SRAMC_WTPR register */ +#define SRAMC_WTPR_WTPRC_POS (0U) +#define SRAMC_WTPR_WTPRC (0x00000001UL) +#define SRAMC_WTPR_WTPRKW_POS (1U) +#define SRAMC_WTPR_WTPRKW (0x000000FEUL) +#define SRAMC_WTPR_WTPRKW_0 (0x00000002UL) +#define SRAMC_WTPR_WTPRKW_1 (0x00000004UL) +#define SRAMC_WTPR_WTPRKW_2 (0x00000008UL) +#define SRAMC_WTPR_WTPRKW_3 (0x00000010UL) +#define SRAMC_WTPR_WTPRKW_4 (0x00000020UL) +#define SRAMC_WTPR_WTPRKW_5 (0x00000040UL) +#define SRAMC_WTPR_WTPRKW_6 (0x00000080UL) + +/* Bit definition for SRAMC_CKCR register */ +#define SRAMC_CKCR_PYOAD_POS (0U) +#define SRAMC_CKCR_PYOAD (0x00000001UL) +#define SRAMC_CKCR_ECCOAD_POS (16U) +#define SRAMC_CKCR_ECCOAD (0x00010000UL) +#define SRAMC_CKCR_BECCOAD_POS (17U) +#define SRAMC_CKCR_BECCOAD (0x00020000UL) +#define SRAMC_CKCR_ECCMOD_POS (24U) +#define SRAMC_CKCR_ECCMOD (0x03000000UL) +#define SRAMC_CKCR_ECCMOD_0 (0x01000000UL) +#define SRAMC_CKCR_ECCMOD_1 (0x02000000UL) +#define SRAMC_CKCR_BECCMOD_POS (26U) +#define SRAMC_CKCR_BECCMOD (0x0C000000UL) +#define SRAMC_CKCR_BECCMOD_0 (0x04000000UL) +#define SRAMC_CKCR_BECCMOD_1 (0x08000000UL) + +/* Bit definition for SRAMC_CKPR register */ +#define SRAMC_CKPR_CKPRC_POS (0U) +#define SRAMC_CKPR_CKPRC (0x00000001UL) +#define SRAMC_CKPR_CKPRKW_POS (1U) +#define SRAMC_CKPR_CKPRKW (0x000000FEUL) +#define SRAMC_CKPR_CKPRKW_0 (0x00000002UL) +#define SRAMC_CKPR_CKPRKW_1 (0x00000004UL) +#define SRAMC_CKPR_CKPRKW_2 (0x00000008UL) +#define SRAMC_CKPR_CKPRKW_3 (0x00000010UL) +#define SRAMC_CKPR_CKPRKW_4 (0x00000020UL) +#define SRAMC_CKPR_CKPRKW_5 (0x00000040UL) +#define SRAMC_CKPR_CKPRKW_6 (0x00000080UL) + +/* Bit definition for SRAMC_CKSR register */ +#define SRAMC_CKSR_SRAM1_PYERR_POS (0U) +#define SRAMC_CKSR_SRAM1_PYERR (0x00000001UL) +#define SRAMC_CKSR_SRAM2_PYERR_POS (1U) +#define SRAMC_CKSR_SRAM2_PYERR (0x00000002UL) +#define SRAMC_CKSR_SRAM3_PYERR_POS (2U) +#define SRAMC_CKSR_SRAM3_PYERR (0x00000004UL) +#define SRAMC_CKSR_SRAMH_PYERR_POS (3U) +#define SRAMC_CKSR_SRAMH_PYERR (0x00000008UL) +#define SRAMC_CKSR_SRAM4_1ERR_POS (4U) +#define SRAMC_CKSR_SRAM4_1ERR (0x00000010UL) +#define SRAMC_CKSR_SRAM4_2ERR_POS (5U) +#define SRAMC_CKSR_SRAM4_2ERR (0x00000020UL) +#define SRAMC_CKSR_SRAMB_1ERR_POS (6U) +#define SRAMC_CKSR_SRAMB_1ERR (0x00000040UL) +#define SRAMC_CKSR_SRAMB_2ERR_POS (7U) +#define SRAMC_CKSR_SRAMB_2ERR (0x00000080UL) +#define SRAMC_CKSR_CACHE_PYERR_POS (8U) +#define SRAMC_CKSR_CACHE_PYERR (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral SWDT +*******************************************************************************/ +/* Bit definition for SWDT_CR register */ +#define SWDT_CR_PERI_POS (0U) +#define SWDT_CR_PERI (0x00000003UL) +#define SWDT_CR_PERI_0 (0x00000001UL) +#define SWDT_CR_PERI_1 (0x00000002UL) +#define SWDT_CR_CKS_POS (4U) +#define SWDT_CR_CKS (0x000000F0UL) +#define SWDT_CR_CKS_0 (0x00000010UL) +#define SWDT_CR_CKS_1 (0x00000020UL) +#define SWDT_CR_CKS_2 (0x00000040UL) +#define SWDT_CR_CKS_3 (0x00000080UL) +#define SWDT_CR_WDPT_POS (8U) +#define SWDT_CR_WDPT (0x00000F00UL) +#define SWDT_CR_WDPT_0 (0x00000100UL) +#define SWDT_CR_WDPT_1 (0x00000200UL) +#define SWDT_CR_WDPT_2 (0x00000400UL) +#define SWDT_CR_WDPT_3 (0x00000800UL) +#define SWDT_CR_SLPOFF_POS (16U) +#define SWDT_CR_SLPOFF (0x00010000UL) +#define SWDT_CR_ITS_POS (31U) +#define SWDT_CR_ITS (0x80000000UL) + +/* Bit definition for SWDT_SR register */ +#define SWDT_SR_CNT_POS (0U) +#define SWDT_SR_CNT (0x0000FFFFUL) +#define SWDT_SR_UDF_POS (16U) +#define SWDT_SR_UDF (0x00010000UL) +#define SWDT_SR_REF_POS (17U) +#define SWDT_SR_REF (0x00020000UL) + +/* Bit definition for SWDT_RR register */ +#define SWDT_RR_RF (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral TMR0 +*******************************************************************************/ +/* Bit definition for TMR0_CNTAR register */ +#define TMR0_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR0_CNTBR register */ +#define TMR0_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPAR register */ +#define TMR0_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR0_CMPBR register */ +#define TMR0_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR0_BCONR register */ +#define TMR0_BCONR_CSTA_POS (0U) +#define TMR0_BCONR_CSTA (0x00000001UL) +#define TMR0_BCONR_CAPMDA_POS (1U) +#define TMR0_BCONR_CAPMDA (0x00000002UL) +#define TMR0_BCONR_INTENA_POS (2U) +#define TMR0_BCONR_INTENA (0x00000004UL) +#define TMR0_BCONR_CKDIVA_POS (4U) +#define TMR0_BCONR_CKDIVA (0x000000F0UL) +#define TMR0_BCONR_SYNSA_POS (8U) +#define TMR0_BCONR_SYNSA (0x00000100UL) +#define TMR0_BCONR_SYNCLKA_POS (9U) +#define TMR0_BCONR_SYNCLKA (0x00000200UL) +#define TMR0_BCONR_ASYNCLKA_POS (10U) +#define TMR0_BCONR_ASYNCLKA (0x00000400UL) +#define TMR0_BCONR_HSTAA_POS (12U) +#define TMR0_BCONR_HSTAA (0x00001000UL) +#define TMR0_BCONR_HSTPA_POS (13U) +#define TMR0_BCONR_HSTPA (0x00002000UL) +#define TMR0_BCONR_HCLEA_POS (14U) +#define TMR0_BCONR_HCLEA (0x00004000UL) +#define TMR0_BCONR_HICPA_POS (15U) +#define TMR0_BCONR_HICPA (0x00008000UL) +#define TMR0_BCONR_CSTB_POS (16U) +#define TMR0_BCONR_CSTB (0x00010000UL) +#define TMR0_BCONR_CAPMDB_POS (17U) +#define TMR0_BCONR_CAPMDB (0x00020000UL) +#define TMR0_BCONR_INTENB_POS (18U) +#define TMR0_BCONR_INTENB (0x00040000UL) +#define TMR0_BCONR_CKDIVB_POS (20U) +#define TMR0_BCONR_CKDIVB (0x00F00000UL) +#define TMR0_BCONR_SYNSB_POS (24U) +#define TMR0_BCONR_SYNSB (0x01000000UL) +#define TMR0_BCONR_SYNCLKB_POS (25U) +#define TMR0_BCONR_SYNCLKB (0x02000000UL) +#define TMR0_BCONR_ASYNCLKB_POS (26U) +#define TMR0_BCONR_ASYNCLKB (0x04000000UL) +#define TMR0_BCONR_HSTAB_POS (28U) +#define TMR0_BCONR_HSTAB (0x10000000UL) +#define TMR0_BCONR_HSTPB_POS (29U) +#define TMR0_BCONR_HSTPB (0x20000000UL) +#define TMR0_BCONR_HCLEB_POS (30U) +#define TMR0_BCONR_HCLEB (0x40000000UL) +#define TMR0_BCONR_HICPB_POS (31U) +#define TMR0_BCONR_HICPB (0x80000000UL) + +/* Bit definition for TMR0_STFLR register */ +#define TMR0_STFLR_CMFA_POS (0U) +#define TMR0_STFLR_CMFA (0x00000001UL) +#define TMR0_STFLR_CMFB_POS (16U) +#define TMR0_STFLR_CMFB (0x00010000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR2 +*******************************************************************************/ +/* Bit definition for TMR2_CNTAR register */ +#define TMR2_CNTAR_CNTA (0x0000FFFFUL) + +/* Bit definition for TMR2_CNTBR register */ +#define TMR2_CNTBR_CNTB (0x0000FFFFUL) + +/* Bit definition for TMR2_CMPAR register */ +#define TMR2_CMPAR_CMPA (0x0000FFFFUL) + +/* Bit definition for TMR2_CMPBR register */ +#define TMR2_CMPBR_CMPB (0x0000FFFFUL) + +/* Bit definition for TMR2_BCONR register */ +#define TMR2_BCONR_CSTA_POS (0U) +#define TMR2_BCONR_CSTA (0x00000001UL) +#define TMR2_BCONR_CAPMDA_POS (1U) +#define TMR2_BCONR_CAPMDA (0x00000002UL) +#define TMR2_BCONR_SYNSA_POS (3U) +#define TMR2_BCONR_SYNSA (0x00000008UL) +#define TMR2_BCONR_CKDIVA_POS (4U) +#define TMR2_BCONR_CKDIVA (0x000000F0UL) +#define TMR2_BCONR_CKDIVA_0 (0x00000010UL) +#define TMR2_BCONR_CKDIVA_1 (0x00000020UL) +#define TMR2_BCONR_CKDIVA_2 (0x00000040UL) +#define TMR2_BCONR_CKDIVA_3 (0x00000080UL) +#define TMR2_BCONR_SYNCLKA_POS (8U) +#define TMR2_BCONR_SYNCLKA (0x00000300UL) +#define TMR2_BCONR_SYNCLKA_0 (0x00000100UL) +#define TMR2_BCONR_SYNCLKA_1 (0x00000200UL) +#define TMR2_BCONR_ASYNCLKA_POS (10U) +#define TMR2_BCONR_ASYNCLKA (0x00000C00UL) +#define TMR2_BCONR_ASYNCLKA_0 (0x00000400UL) +#define TMR2_BCONR_ASYNCLKA_1 (0x00000800UL) +#define TMR2_BCONR_SYNCLKAT_POS (12U) +#define TMR2_BCONR_SYNCLKAT (0x00003000UL) +#define TMR2_BCONR_SYNCLKAT_0 (0x00001000UL) +#define TMR2_BCONR_SYNCLKAT_1 (0x00002000UL) +#define TMR2_BCONR_CSTB_POS (16U) +#define TMR2_BCONR_CSTB (0x00010000UL) +#define TMR2_BCONR_CAPMDB_POS (17U) +#define TMR2_BCONR_CAPMDB (0x00020000UL) +#define TMR2_BCONR_SYNSB_POS (19U) +#define TMR2_BCONR_SYNSB (0x00080000UL) +#define TMR2_BCONR_CKDIVB_POS (20U) +#define TMR2_BCONR_CKDIVB (0x00F00000UL) +#define TMR2_BCONR_CKDIVB_0 (0x00100000UL) +#define TMR2_BCONR_CKDIVB_1 (0x00200000UL) +#define TMR2_BCONR_CKDIVB_2 (0x00400000UL) +#define TMR2_BCONR_CKDIVB_3 (0x00800000UL) +#define TMR2_BCONR_SYNCLKB_POS (24U) +#define TMR2_BCONR_SYNCLKB (0x03000000UL) +#define TMR2_BCONR_SYNCLKB_0 (0x01000000UL) +#define TMR2_BCONR_SYNCLKB_1 (0x02000000UL) +#define TMR2_BCONR_ASYNCLKB_POS (26U) +#define TMR2_BCONR_ASYNCLKB (0x0C000000UL) +#define TMR2_BCONR_ASYNCLKB_0 (0x04000000UL) +#define TMR2_BCONR_ASYNCLKB_1 (0x08000000UL) +#define TMR2_BCONR_SYNCLKBT_POS (28U) +#define TMR2_BCONR_SYNCLKBT (0x30000000UL) +#define TMR2_BCONR_SYNCLKBT_0 (0x10000000UL) +#define TMR2_BCONR_SYNCLKBT_1 (0x20000000UL) + +/* Bit definition for TMR2_ICONR register */ +#define TMR2_ICONR_CMENA_POS (0U) +#define TMR2_ICONR_CMENA (0x00000001UL) +#define TMR2_ICONR_OVENA_POS (1U) +#define TMR2_ICONR_OVENA (0x00000002UL) +#define TMR2_ICONR_CMENB_POS (16U) +#define TMR2_ICONR_CMENB (0x00010000UL) +#define TMR2_ICONR_OVENB_POS (17U) +#define TMR2_ICONR_OVENB (0x00020000UL) +#define TMR2_ICONR_RESV_POS (24U) +#define TMR2_ICONR_RESV (0x01000000UL) + +/* Bit definition for TMR2_PCONR register */ +#define TMR2_PCONR_STACA_POS (0U) +#define TMR2_PCONR_STACA (0x00000003UL) +#define TMR2_PCONR_STACA_0 (0x00000001UL) +#define TMR2_PCONR_STACA_1 (0x00000002UL) +#define TMR2_PCONR_STPCA_POS (2U) +#define TMR2_PCONR_STPCA (0x0000000CUL) +#define TMR2_PCONR_STPCA_0 (0x00000004UL) +#define TMR2_PCONR_STPCA_1 (0x00000008UL) +#define TMR2_PCONR_CMPCA_POS (4U) +#define TMR2_PCONR_CMPCA (0x00000030UL) +#define TMR2_PCONR_CMPCA_0 (0x00000010UL) +#define TMR2_PCONR_CMPCA_1 (0x00000020UL) +#define TMR2_PCONR_OUTENA_POS (8U) +#define TMR2_PCONR_OUTENA (0x00000100UL) +#define TMR2_PCONR_NOFIENA_POS (12U) +#define TMR2_PCONR_NOFIENA (0x00001000UL) +#define TMR2_PCONR_NOFICKA_POS (13U) +#define TMR2_PCONR_NOFICKA (0x00006000UL) +#define TMR2_PCONR_NOFICKA_0 (0x00002000UL) +#define TMR2_PCONR_NOFICKA_1 (0x00004000UL) +#define TMR2_PCONR_STACB_POS (16U) +#define TMR2_PCONR_STACB (0x00030000UL) +#define TMR2_PCONR_STACB_0 (0x00010000UL) +#define TMR2_PCONR_STACB_1 (0x00020000UL) +#define TMR2_PCONR_STPCB_POS (18U) +#define TMR2_PCONR_STPCB (0x000C0000UL) +#define TMR2_PCONR_STPCB_0 (0x00040000UL) +#define TMR2_PCONR_STPCB_1 (0x00080000UL) +#define TMR2_PCONR_CMPCB_POS (20U) +#define TMR2_PCONR_CMPCB (0x00300000UL) +#define TMR2_PCONR_CMPCB_0 (0x00100000UL) +#define TMR2_PCONR_CMPCB_1 (0x00200000UL) +#define TMR2_PCONR_OUTENB_POS (24U) +#define TMR2_PCONR_OUTENB (0x01000000UL) +#define TMR2_PCONR_NOFIENB_POS (28U) +#define TMR2_PCONR_NOFIENB (0x10000000UL) +#define TMR2_PCONR_NOFICKB_POS (29U) +#define TMR2_PCONR_NOFICKB (0x60000000UL) +#define TMR2_PCONR_NOFICKB_0 (0x20000000UL) +#define TMR2_PCONR_NOFICKB_1 (0x40000000UL) + +/* Bit definition for TMR2_HCONR register */ +#define TMR2_HCONR_HSTAA0_POS (0U) +#define TMR2_HCONR_HSTAA0 (0x00000001UL) +#define TMR2_HCONR_HSTAA1_POS (1U) +#define TMR2_HCONR_HSTAA1 (0x00000002UL) +#define TMR2_HCONR_HSTAA2_POS (2U) +#define TMR2_HCONR_HSTAA2 (0x00000004UL) +#define TMR2_HCONR_HSTPA0_POS (4U) +#define TMR2_HCONR_HSTPA0 (0x00000010UL) +#define TMR2_HCONR_HSTPA1_POS (5U) +#define TMR2_HCONR_HSTPA1 (0x00000020UL) +#define TMR2_HCONR_HSTPA2_POS (6U) +#define TMR2_HCONR_HSTPA2 (0x00000040UL) +#define TMR2_HCONR_HCLEA0_POS (8U) +#define TMR2_HCONR_HCLEA0 (0x00000100UL) +#define TMR2_HCONR_HCLEA1_POS (9U) +#define TMR2_HCONR_HCLEA1 (0x00000200UL) +#define TMR2_HCONR_HCLEA2_POS (10U) +#define TMR2_HCONR_HCLEA2 (0x00000400UL) +#define TMR2_HCONR_HICPA0_POS (12U) +#define TMR2_HCONR_HICPA0 (0x00001000UL) +#define TMR2_HCONR_HICPA1_POS (13U) +#define TMR2_HCONR_HICPA1 (0x00002000UL) +#define TMR2_HCONR_HICPA2_POS (14U) +#define TMR2_HCONR_HICPA2 (0x00004000UL) +#define TMR2_HCONR_HSTAB0_POS (16U) +#define TMR2_HCONR_HSTAB0 (0x00010000UL) +#define TMR2_HCONR_HSTAB1_POS (17U) +#define TMR2_HCONR_HSTAB1 (0x00020000UL) +#define TMR2_HCONR_HSTAB2_POS (18U) +#define TMR2_HCONR_HSTAB2 (0x00040000UL) +#define TMR2_HCONR_HSTPB0_POS (20U) +#define TMR2_HCONR_HSTPB0 (0x00100000UL) +#define TMR2_HCONR_HSTPB1_POS (21U) +#define TMR2_HCONR_HSTPB1 (0x00200000UL) +#define TMR2_HCONR_HSTPB2_POS (22U) +#define TMR2_HCONR_HSTPB2 (0x00400000UL) +#define TMR2_HCONR_HCLEB0_POS (24U) +#define TMR2_HCONR_HCLEB0 (0x01000000UL) +#define TMR2_HCONR_HCLEB1_POS (25U) +#define TMR2_HCONR_HCLEB1 (0x02000000UL) +#define TMR2_HCONR_HCLEB2_POS (26U) +#define TMR2_HCONR_HCLEB2 (0x04000000UL) +#define TMR2_HCONR_HICPB0_POS (28U) +#define TMR2_HCONR_HICPB0 (0x10000000UL) +#define TMR2_HCONR_HICPB1_POS (29U) +#define TMR2_HCONR_HICPB1 (0x20000000UL) +#define TMR2_HCONR_HICPB2_POS (30U) +#define TMR2_HCONR_HICPB2 (0x40000000UL) + +/* Bit definition for TMR2_STFLR register */ +#define TMR2_STFLR_CMFA_POS (0U) +#define TMR2_STFLR_CMFA (0x00000001UL) +#define TMR2_STFLR_OVFA_POS (1U) +#define TMR2_STFLR_OVFA (0x00000002UL) +#define TMR2_STFLR_CMFB_POS (16U) +#define TMR2_STFLR_CMFB (0x00010000UL) +#define TMR2_STFLR_OVFB_POS (17U) +#define TMR2_STFLR_OVFB (0x00020000UL) +#define TMR2_STFLR_RESV_POS (24U) +#define TMR2_STFLR_RESV (0x01000000UL) + +/******************************************************************************* + Bit definition for Peripheral TMR4 +*******************************************************************************/ +/* Bit definition for TMR4_OCCRUH register */ +#define TMR4_OCCRUH (0xFFFFU) + +/* Bit definition for TMR4_OCCRUL register */ +#define TMR4_OCCRUL (0xFFFFU) + +/* Bit definition for TMR4_OCCRVH register */ +#define TMR4_OCCRVH (0xFFFFU) + +/* Bit definition for TMR4_OCCRVL register */ +#define TMR4_OCCRVL (0xFFFFU) + +/* Bit definition for TMR4_OCCRWH register */ +#define TMR4_OCCRWH (0xFFFFU) + +/* Bit definition for TMR4_OCCRWL register */ +#define TMR4_OCCRWL (0xFFFFU) + +/* Bit definition for TMR4_OCSR register */ +#define TMR4_OCSR_OCEH_POS (0U) +#define TMR4_OCSR_OCEH (0x0001U) +#define TMR4_OCSR_OCEL_POS (1U) +#define TMR4_OCSR_OCEL (0x0002U) +#define TMR4_OCSR_OCPH_POS (2U) +#define TMR4_OCSR_OCPH (0x0004U) +#define TMR4_OCSR_OCPL_POS (3U) +#define TMR4_OCSR_OCPL (0x0008U) +#define TMR4_OCSR_OCIEH_POS (4U) +#define TMR4_OCSR_OCIEH (0x0010U) +#define TMR4_OCSR_OCIEL_POS (5U) +#define TMR4_OCSR_OCIEL (0x0020U) +#define TMR4_OCSR_OCFH_POS (6U) +#define TMR4_OCSR_OCFH (0x0040U) +#define TMR4_OCSR_OCFL_POS (7U) +#define TMR4_OCSR_OCFL (0x0080U) + +/* Bit definition for TMR4_OCER register */ +#define TMR4_OCER_CHBUFEN_POS (0U) +#define TMR4_OCER_CHBUFEN (0x0003U) +#define TMR4_OCER_CHBUFEN_0 (0x0001U) +#define TMR4_OCER_CHBUFEN_1 (0x0002U) +#define TMR4_OCER_CLBUFEN_POS (2U) +#define TMR4_OCER_CLBUFEN (0x000CU) +#define TMR4_OCER_CLBUFEN_0 (0x0004U) +#define TMR4_OCER_CLBUFEN_1 (0x0008U) +#define TMR4_OCER_MHBUFEN_POS (4U) +#define TMR4_OCER_MHBUFEN (0x0030U) +#define TMR4_OCER_MHBUFEN_0 (0x0010U) +#define TMR4_OCER_MHBUFEN_1 (0x0020U) +#define TMR4_OCER_MLBUFEN_POS (6U) +#define TMR4_OCER_MLBUFEN (0x00C0U) +#define TMR4_OCER_MLBUFEN_0 (0x0040U) +#define TMR4_OCER_MLBUFEN_1 (0x0080U) +#define TMR4_OCER_LMCH_POS (8U) +#define TMR4_OCER_LMCH (0x0100U) +#define TMR4_OCER_LMCL_POS (9U) +#define TMR4_OCER_LMCL (0x0200U) +#define TMR4_OCER_LMMH_POS (10U) +#define TMR4_OCER_LMMH (0x0400U) +#define TMR4_OCER_LMML_POS (11U) +#define TMR4_OCER_LMML (0x0800U) +#define TMR4_OCER_MCECH_POS (12U) +#define TMR4_OCER_MCECH (0x1000U) +#define TMR4_OCER_MCECL_POS (13U) +#define TMR4_OCER_MCECL (0x2000U) + +/* Bit definition for TMR4_OCMRH register */ +#define TMR4_OCMRH_OCFDCH_POS (0U) +#define TMR4_OCMRH_OCFDCH (0x0001U) +#define TMR4_OCMRH_OCFPKH_POS (1U) +#define TMR4_OCMRH_OCFPKH (0x0002U) +#define TMR4_OCMRH_OCFUCH_POS (2U) +#define TMR4_OCMRH_OCFUCH (0x0004U) +#define TMR4_OCMRH_OCFZRH_POS (3U) +#define TMR4_OCMRH_OCFZRH (0x0008U) +#define TMR4_OCMRH_OPDCH_POS (4U) +#define TMR4_OCMRH_OPDCH (0x0030U) +#define TMR4_OCMRH_OPDCH_0 (0x0010U) +#define TMR4_OCMRH_OPDCH_1 (0x0020U) +#define TMR4_OCMRH_OPPKH_POS (6U) +#define TMR4_OCMRH_OPPKH (0x00C0U) +#define TMR4_OCMRH_OPPKH_0 (0x0040U) +#define TMR4_OCMRH_OPPKH_1 (0x0080U) +#define TMR4_OCMRH_OPUCH_POS (8U) +#define TMR4_OCMRH_OPUCH (0x0300U) +#define TMR4_OCMRH_OPUCH_0 (0x0100U) +#define TMR4_OCMRH_OPUCH_1 (0x0200U) +#define TMR4_OCMRH_OPZRH_POS (10U) +#define TMR4_OCMRH_OPZRH (0x0C00U) +#define TMR4_OCMRH_OPZRH_0 (0x0400U) +#define TMR4_OCMRH_OPZRH_1 (0x0800U) +#define TMR4_OCMRH_OPNPKH_POS (12U) +#define TMR4_OCMRH_OPNPKH (0x3000U) +#define TMR4_OCMRH_OPNPKH_0 (0x1000U) +#define TMR4_OCMRH_OPNPKH_1 (0x2000U) +#define TMR4_OCMRH_OPNZRH_POS (14U) +#define TMR4_OCMRH_OPNZRH (0xC000U) +#define TMR4_OCMRH_OPNZRH_0 (0x4000U) +#define TMR4_OCMRH_OPNZRH_1 (0x8000U) + +/* Bit definition for TMR4_OCMRL register */ +#define TMR4_OCMRL_OCFDCL_POS (0U) +#define TMR4_OCMRL_OCFDCL (0x00000001UL) +#define TMR4_OCMRL_OCFPKL_POS (1U) +#define TMR4_OCMRL_OCFPKL (0x00000002UL) +#define TMR4_OCMRL_OCFUCL_POS (2U) +#define TMR4_OCMRL_OCFUCL (0x00000004UL) +#define TMR4_OCMRL_OCFZRL_POS (3U) +#define TMR4_OCMRL_OCFZRL (0x00000008UL) +#define TMR4_OCMRL_OPDCL_POS (4U) +#define TMR4_OCMRL_OPDCL (0x00000030UL) +#define TMR4_OCMRL_OPDCL_0 (0x00000010UL) +#define TMR4_OCMRL_OPDCL_1 (0x00000020UL) +#define TMR4_OCMRL_OPPKL_POS (6U) +#define TMR4_OCMRL_OPPKL (0x000000C0UL) +#define TMR4_OCMRL_OPPKL_0 (0x00000040UL) +#define TMR4_OCMRL_OPPKL_1 (0x00000080UL) +#define TMR4_OCMRL_OPUCL_POS (8U) +#define TMR4_OCMRL_OPUCL (0x00000300UL) +#define TMR4_OCMRL_OPUCL_0 (0x00000100UL) +#define TMR4_OCMRL_OPUCL_1 (0x00000200UL) +#define TMR4_OCMRL_OPZRL_POS (10U) +#define TMR4_OCMRL_OPZRL (0x00000C00UL) +#define TMR4_OCMRL_OPZRL_0 (0x00000400UL) +#define TMR4_OCMRL_OPZRL_1 (0x00000800UL) +#define TMR4_OCMRL_OPNPKL_POS (12U) +#define TMR4_OCMRL_OPNPKL (0x00003000UL) +#define TMR4_OCMRL_OPNPKL_0 (0x00001000UL) +#define TMR4_OCMRL_OPNPKL_1 (0x00002000UL) +#define TMR4_OCMRL_OPNZRL_POS (14U) +#define TMR4_OCMRL_OPNZRL (0x0000C000UL) +#define TMR4_OCMRL_OPNZRL_0 (0x00004000UL) +#define TMR4_OCMRL_OPNZRL_1 (0x00008000UL) +#define TMR4_OCMRL_EOPNDCL_POS (16U) +#define TMR4_OCMRL_EOPNDCL (0x00030000UL) +#define TMR4_OCMRL_EOPNDCL_0 (0x00010000UL) +#define TMR4_OCMRL_EOPNDCL_1 (0x00020000UL) +#define TMR4_OCMRL_EOPNUCL_POS (18U) +#define TMR4_OCMRL_EOPNUCL (0x000C0000UL) +#define TMR4_OCMRL_EOPNUCL_0 (0x00040000UL) +#define TMR4_OCMRL_EOPNUCL_1 (0x00080000UL) +#define TMR4_OCMRL_EOPDCL_POS (20U) +#define TMR4_OCMRL_EOPDCL (0x00300000UL) +#define TMR4_OCMRL_EOPDCL_0 (0x00100000UL) +#define TMR4_OCMRL_EOPDCL_1 (0x00200000UL) +#define TMR4_OCMRL_EOPPKL_POS (22U) +#define TMR4_OCMRL_EOPPKL (0x00C00000UL) +#define TMR4_OCMRL_EOPPKL_0 (0x00400000UL) +#define TMR4_OCMRL_EOPPKL_1 (0x00800000UL) +#define TMR4_OCMRL_EOPUCL_POS (24U) +#define TMR4_OCMRL_EOPUCL (0x03000000UL) +#define TMR4_OCMRL_EOPUCL_0 (0x01000000UL) +#define TMR4_OCMRL_EOPUCL_1 (0x02000000UL) +#define TMR4_OCMRL_EOPZRL_POS (26U) +#define TMR4_OCMRL_EOPZRL (0x0C000000UL) +#define TMR4_OCMRL_EOPZRL_0 (0x04000000UL) +#define TMR4_OCMRL_EOPZRL_1 (0x08000000UL) +#define TMR4_OCMRL_EOPNPKL_POS (28U) +#define TMR4_OCMRL_EOPNPKL (0x30000000UL) +#define TMR4_OCMRL_EOPNPKL_0 (0x10000000UL) +#define TMR4_OCMRL_EOPNPKL_1 (0x20000000UL) +#define TMR4_OCMRL_EOPNZRL_POS (30U) +#define TMR4_OCMRL_EOPNZRL (0xC0000000UL) +#define TMR4_OCMRL_EOPNZRL_0 (0x40000000UL) +#define TMR4_OCMRL_EOPNZRL_1 (0x80000000UL) + +/* Bit definition for TMR4_CPSR register */ +#define TMR4_CPSR (0xFFFFU) + +/* Bit definition for TMR4_CNTR register */ +#define TMR4_CNTR (0xFFFFU) + +/* Bit definition for TMR4_CCSR register */ +#define TMR4_CCSR_CKDIV_POS (0U) +#define TMR4_CCSR_CKDIV (0x000FU) +#define TMR4_CCSR_CKDIV_0 (0x0001U) +#define TMR4_CCSR_CKDIV_1 (0x0002U) +#define TMR4_CCSR_CKDIV_2 (0x0004U) +#define TMR4_CCSR_CKDIV_3 (0x0008U) +#define TMR4_CCSR_CLEAR_POS (4U) +#define TMR4_CCSR_CLEAR (0x0010U) +#define TMR4_CCSR_MODE_POS (5U) +#define TMR4_CCSR_MODE (0x0020U) +#define TMR4_CCSR_STOP_POS (6U) +#define TMR4_CCSR_STOP (0x0040U) +#define TMR4_CCSR_BUFEN_POS (7U) +#define TMR4_CCSR_BUFEN (0x0080U) +#define TMR4_CCSR_IRQPEN_POS (8U) +#define TMR4_CCSR_IRQPEN (0x0100U) +#define TMR4_CCSR_IRQPF_POS (9U) +#define TMR4_CCSR_IRQPF (0x0200U) +#define TMR4_CCSR_IRQZEN_POS (13U) +#define TMR4_CCSR_IRQZEN (0x2000U) +#define TMR4_CCSR_IRQZF_POS (14U) +#define TMR4_CCSR_IRQZF (0x4000U) +#define TMR4_CCSR_ECKEN_POS (15U) +#define TMR4_CCSR_ECKEN (0x8000U) + +/* Bit definition for TMR4_CVPR register */ +#define TMR4_CVPR_ZIM_POS (0U) +#define TMR4_CVPR_ZIM (0x000FU) +#define TMR4_CVPR_PIM_POS (4U) +#define TMR4_CVPR_PIM (0x00F0U) +#define TMR4_CVPR_ZIC_POS (8U) +#define TMR4_CVPR_ZIC (0x0F00U) +#define TMR4_CVPR_PIC_POS (12U) +#define TMR4_CVPR_PIC (0xF000U) + +/* Bit definition for TMR4_PFSRU register */ +#define TMR4_PFSRU (0xFFFFU) + +/* Bit definition for TMR4_PDARU register */ +#define TMR4_PDARU (0xFFFFU) + +/* Bit definition for TMR4_PDBRU register */ +#define TMR4_PDBRU (0xFFFFU) + +/* Bit definition for TMR4_PFSRV register */ +#define TMR4_PFSRV (0xFFFFU) + +/* Bit definition for TMR4_PDARV register */ +#define TMR4_PDARV (0xFFFFU) + +/* Bit definition for TMR4_PDBRV register */ +#define TMR4_PDBRV (0xFFFFU) + +/* Bit definition for TMR4_PFSRW register */ +#define TMR4_PFSRW (0xFFFFU) + +/* Bit definition for TMR4_PDARW register */ +#define TMR4_PDARW (0xFFFFU) + +/* Bit definition for TMR4_PDBRW register */ +#define TMR4_PDBRW (0xFFFFU) + +/* Bit definition for TMR4_POCR register */ +#define TMR4_POCR_DIVCK_POS (0U) +#define TMR4_POCR_DIVCK (0x0007U) +#define TMR4_POCR_DIVCK_0 (0x0001U) +#define TMR4_POCR_DIVCK_1 (0x0002U) +#define TMR4_POCR_DIVCK_2 (0x0004U) +#define TMR4_POCR_PWMMD_POS (4U) +#define TMR4_POCR_PWMMD (0x0030U) +#define TMR4_POCR_PWMMD_0 (0x0010U) +#define TMR4_POCR_PWMMD_1 (0x0020U) +#define TMR4_POCR_LVLS_POS (6U) +#define TMR4_POCR_LVLS (0x00C0U) +#define TMR4_POCR_LVLS_0 (0x0040U) +#define TMR4_POCR_LVLS_1 (0x0080U) + +/* Bit definition for TMR4_RCSR register */ +#define TMR4_RCSR_RTIDU_POS (0U) +#define TMR4_RCSR_RTIDU (0x0001U) +#define TMR4_RCSR_RTIDV_POS (1U) +#define TMR4_RCSR_RTIDV (0x0002U) +#define TMR4_RCSR_RTIDW_POS (2U) +#define TMR4_RCSR_RTIDW (0x0004U) +#define TMR4_RCSR_RTIFU_POS (4U) +#define TMR4_RCSR_RTIFU (0x0010U) +#define TMR4_RCSR_RTICU_POS (5U) +#define TMR4_RCSR_RTICU (0x0020U) +#define TMR4_RCSR_RTEU_POS (6U) +#define TMR4_RCSR_RTEU (0x0040U) +#define TMR4_RCSR_RTSU_POS (7U) +#define TMR4_RCSR_RTSU (0x0080U) +#define TMR4_RCSR_RTIFV_POS (8U) +#define TMR4_RCSR_RTIFV (0x0100U) +#define TMR4_RCSR_RTICV_POS (9U) +#define TMR4_RCSR_RTICV (0x0200U) +#define TMR4_RCSR_RTEV_POS (10U) +#define TMR4_RCSR_RTEV (0x0400U) +#define TMR4_RCSR_RTSV_POS (11U) +#define TMR4_RCSR_RTSV (0x0800U) +#define TMR4_RCSR_RTIFW_POS (12U) +#define TMR4_RCSR_RTIFW (0x1000U) +#define TMR4_RCSR_RTICW_POS (13U) +#define TMR4_RCSR_RTICW (0x2000U) +#define TMR4_RCSR_RTEW_POS (14U) +#define TMR4_RCSR_RTEW (0x4000U) +#define TMR4_RCSR_RTSW_POS (15U) +#define TMR4_RCSR_RTSW (0x8000U) + +/* Bit definition for TMR4_SCCRUH register */ +#define TMR4_SCCRUH (0xFFFFU) + +/* Bit definition for TMR4_SCCRUL register */ +#define TMR4_SCCRUL (0xFFFFU) + +/* Bit definition for TMR4_SCCRVH register */ +#define TMR4_SCCRVH (0xFFFFU) + +/* Bit definition for TMR4_SCCRVL register */ +#define TMR4_SCCRVL (0xFFFFU) + +/* Bit definition for TMR4_SCCRWH register */ +#define TMR4_SCCRWH (0xFFFFU) + +/* Bit definition for TMR4_SCCRWL register */ +#define TMR4_SCCRWL (0xFFFFU) + +/* Bit definition for TMR4_SCSR register */ +#define TMR4_SCSR_BUFEN_POS (0U) +#define TMR4_SCSR_BUFEN (0x0003U) +#define TMR4_SCSR_BUFEN_0 (0x0001U) +#define TMR4_SCSR_BUFEN_1 (0x0002U) +#define TMR4_SCSR_EVTOS_POS (2U) +#define TMR4_SCSR_EVTOS (0x001CU) +#define TMR4_SCSR_EVTOS_0 (0x0004U) +#define TMR4_SCSR_EVTOS_1 (0x0008U) +#define TMR4_SCSR_EVTOS_2 (0x0010U) +#define TMR4_SCSR_LMC_POS (5U) +#define TMR4_SCSR_LMC (0x0020U) +#define TMR4_SCSR_EVTMS_POS (8U) +#define TMR4_SCSR_EVTMS (0x0100U) +#define TMR4_SCSR_EVTDS_POS (9U) +#define TMR4_SCSR_EVTDS (0x0200U) +#define TMR4_SCSR_DEN_POS (12U) +#define TMR4_SCSR_DEN (0x1000U) +#define TMR4_SCSR_PEN_POS (13U) +#define TMR4_SCSR_PEN (0x2000U) +#define TMR4_SCSR_UEN_POS (14U) +#define TMR4_SCSR_UEN (0x4000U) +#define TMR4_SCSR_ZEN_POS (15U) +#define TMR4_SCSR_ZEN (0x8000U) + +/* Bit definition for TMR4_SCMR register */ +#define TMR4_SCMR_AMC_POS (0U) +#define TMR4_SCMR_AMC (0x000FU) +#define TMR4_SCMR_MZCE_POS (6U) +#define TMR4_SCMR_MZCE (0x0040U) +#define TMR4_SCMR_MPCE_POS (7U) +#define TMR4_SCMR_MPCE (0x0080U) + +/* Bit definition for TMR4_PSCR register */ +#define TMR4_PSCR_OEUH_POS (0U) +#define TMR4_PSCR_OEUH (0x00000001UL) +#define TMR4_PSCR_OEUL_POS (1U) +#define TMR4_PSCR_OEUL (0x00000002UL) +#define TMR4_PSCR_OEVH_POS (2U) +#define TMR4_PSCR_OEVH (0x00000004UL) +#define TMR4_PSCR_OEVL_POS (3U) +#define TMR4_PSCR_OEVL (0x00000008UL) +#define TMR4_PSCR_OEWH_POS (4U) +#define TMR4_PSCR_OEWH (0x00000010UL) +#define TMR4_PSCR_OEWL_POS (5U) +#define TMR4_PSCR_OEWL (0x00000020UL) +#define TMR4_PSCR_ODT_POS (6U) +#define TMR4_PSCR_ODT (0x000000C0UL) +#define TMR4_PSCR_ODT_0 (0x00000040UL) +#define TMR4_PSCR_ODT_1 (0x00000080UL) +#define TMR4_PSCR_MOE_POS (8U) +#define TMR4_PSCR_MOE (0x00000100UL) +#define TMR4_PSCR_AOE_POS (9U) +#define TMR4_PSCR_AOE (0x00000200UL) +#define TMR4_PSCR_OSUH_POS (16U) +#define TMR4_PSCR_OSUH (0x00030000UL) +#define TMR4_PSCR_OSUH_0 (0x00010000UL) +#define TMR4_PSCR_OSUH_1 (0x00020000UL) +#define TMR4_PSCR_OSUL_POS (18U) +#define TMR4_PSCR_OSUL (0x000C0000UL) +#define TMR4_PSCR_OSUL_0 (0x00040000UL) +#define TMR4_PSCR_OSUL_1 (0x00080000UL) +#define TMR4_PSCR_OSVH_POS (20U) +#define TMR4_PSCR_OSVH (0x00300000UL) +#define TMR4_PSCR_OSVH_0 (0x00100000UL) +#define TMR4_PSCR_OSVH_1 (0x00200000UL) +#define TMR4_PSCR_OSVL_POS (22U) +#define TMR4_PSCR_OSVL (0x00C00000UL) +#define TMR4_PSCR_OSVL_0 (0x00400000UL) +#define TMR4_PSCR_OSVL_1 (0x00800000UL) +#define TMR4_PSCR_OSWH_POS (24U) +#define TMR4_PSCR_OSWH (0x03000000UL) +#define TMR4_PSCR_OSWH_0 (0x01000000UL) +#define TMR4_PSCR_OSWH_1 (0x02000000UL) +#define TMR4_PSCR_OSWL_POS (26U) +#define TMR4_PSCR_OSWL (0x0C000000UL) +#define TMR4_PSCR_OSWL_0 (0x04000000UL) +#define TMR4_PSCR_OSWL_1 (0x08000000UL) + +/* Bit definition for TMR4_SCER register */ +#define TMR4_SCER_EVTRS_POS (0U) +#define TMR4_SCER_EVTRS (0x0007U) +#define TMR4_SCER_EVTRS_0 (0x0001U) +#define TMR4_SCER_EVTRS_1 (0x0002U) +#define TMR4_SCER_EVTRS_2 (0x0004U) +#define TMR4_SCER_PCTS_POS (3U) +#define TMR4_SCER_PCTS (0x0008U) + +/******************************************************************************* + Bit definition for Peripheral TMR6 +*******************************************************************************/ +/* Bit definition for TMR6_CNTER register */ +#define TMR6_CNTER (0xFFFFFFFFUL) + +/* Bit definition for TMR6_UPDAR register */ +#define TMR6_UPDAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_PERAR register */ +#define TMR6_PERAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_PERBR register */ +#define TMR6_PERBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_PERCR register */ +#define TMR6_PERCR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMAR register */ +#define TMR6_GCMAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMBR register */ +#define TMR6_GCMBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMCR register */ +#define TMR6_GCMCR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMDR register */ +#define TMR6_GCMDR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMER register */ +#define TMR6_GCMER (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCMFR register */ +#define TMR6_GCMFR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMAR register */ +#define TMR6_SCMAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMBR register */ +#define TMR6_SCMBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMCR register */ +#define TMR6_SCMCR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMDR register */ +#define TMR6_SCMDR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMER register */ +#define TMR6_SCMER (0xFFFFFFFFUL) + +/* Bit definition for TMR6_SCMFR register */ +#define TMR6_SCMFR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTUAR register */ +#define TMR6_DTUAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTDAR register */ +#define TMR6_DTDAR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTUBR register */ +#define TMR6_DTUBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_DTDBR register */ +#define TMR6_DTDBR (0xFFFFFFFFUL) + +/* Bit definition for TMR6_GCONR register */ +#define TMR6_GCONR_START_POS (0U) +#define TMR6_GCONR_START (0x00000001UL) +#define TMR6_GCONR_DIR_POS (1U) +#define TMR6_GCONR_DIR (0x00000002UL) +#define TMR6_GCONR_MODE_POS (2U) +#define TMR6_GCONR_MODE (0x00000004UL) +#define TMR6_GCONR_CKDIV_POS (4U) +#define TMR6_GCONR_CKDIV (0x000000F0UL) +#define TMR6_GCONR_CKDIV_0 (0x00000010UL) +#define TMR6_GCONR_CKDIV_1 (0x00000020UL) +#define TMR6_GCONR_CKDIV_2 (0x00000040UL) +#define TMR6_GCONR_CKDIV_3 (0x00000080UL) +#define TMR6_GCONR_OVSTP_POS (8U) +#define TMR6_GCONR_OVSTP (0x00000100UL) +#define TMR6_GCONR_ZMSKREV_POS (16U) +#define TMR6_GCONR_ZMSKREV (0x00010000UL) +#define TMR6_GCONR_ZMSKPOS_POS (17U) +#define TMR6_GCONR_ZMSKPOS (0x00020000UL) +#define TMR6_GCONR_ZMSKVAL_POS (18U) +#define TMR6_GCONR_ZMSKVAL (0x000C0000UL) +#define TMR6_GCONR_ZMSKVAL_0 (0x00040000UL) +#define TMR6_GCONR_ZMSKVAL_1 (0x00080000UL) + +/* Bit definition for TMR6_ICONR register */ +#define TMR6_ICONR_INTENA_POS (0U) +#define TMR6_ICONR_INTENA (0x00000001UL) +#define TMR6_ICONR_INTENB_POS (1U) +#define TMR6_ICONR_INTENB (0x00000002UL) +#define TMR6_ICONR_INTENC_POS (2U) +#define TMR6_ICONR_INTENC (0x00000004UL) +#define TMR6_ICONR_INTEND_POS (3U) +#define TMR6_ICONR_INTEND (0x00000008UL) +#define TMR6_ICONR_INTENE_POS (4U) +#define TMR6_ICONR_INTENE (0x00000010UL) +#define TMR6_ICONR_INTENF_POS (5U) +#define TMR6_ICONR_INTENF (0x00000020UL) +#define TMR6_ICONR_INTENOVF_POS (6U) +#define TMR6_ICONR_INTENOVF (0x00000040UL) +#define TMR6_ICONR_INTENUDF_POS (7U) +#define TMR6_ICONR_INTENUDF (0x00000080UL) +#define TMR6_ICONR_INTENDTE_POS (8U) +#define TMR6_ICONR_INTENDTE (0x00000100UL) +#define TMR6_ICONR_INTENSAU_POS (16U) +#define TMR6_ICONR_INTENSAU (0x00010000UL) +#define TMR6_ICONR_INTENSAD_POS (17U) +#define TMR6_ICONR_INTENSAD (0x00020000UL) +#define TMR6_ICONR_INTENSBU_POS (18U) +#define TMR6_ICONR_INTENSBU (0x00040000UL) +#define TMR6_ICONR_INTENSBD_POS (19U) +#define TMR6_ICONR_INTENSBD (0x00080000UL) + +/* Bit definition for TMR6_BCONR register */ +#define TMR6_BCONR_BENA_POS (0U) +#define TMR6_BCONR_BENA (0x00000001UL) +#define TMR6_BCONR_BSEA_POS (1U) +#define TMR6_BCONR_BSEA (0x00000002UL) +#define TMR6_BCONR_BTRUA_POS (2U) +#define TMR6_BCONR_BTRUA (0x00000004UL) +#define TMR6_BCONR_BTRDA_POS (3U) +#define TMR6_BCONR_BTRDA (0x00000008UL) +#define TMR6_BCONR_BENB_POS (4U) +#define TMR6_BCONR_BENB (0x00000010UL) +#define TMR6_BCONR_BSEB_POS (5U) +#define TMR6_BCONR_BSEB (0x00000020UL) +#define TMR6_BCONR_BTRUB_POS (6U) +#define TMR6_BCONR_BTRUB (0x00000040UL) +#define TMR6_BCONR_BTRDB_POS (7U) +#define TMR6_BCONR_BTRDB (0x00000080UL) +#define TMR6_BCONR_BENP_POS (8U) +#define TMR6_BCONR_BENP (0x00000100UL) +#define TMR6_BCONR_BSEP_POS (9U) +#define TMR6_BCONR_BSEP (0x00000200UL) +#define TMR6_BCONR_BTRUP_POS (10U) +#define TMR6_BCONR_BTRUP (0x00000400UL) +#define TMR6_BCONR_BTRDP_POS (11U) +#define TMR6_BCONR_BTRDP (0x00000800UL) +#define TMR6_BCONR_BENSPA_POS (16U) +#define TMR6_BCONR_BENSPA (0x00010000UL) +#define TMR6_BCONR_BSESPA_POS (17U) +#define TMR6_BCONR_BSESPA (0x00020000UL) +#define TMR6_BCONR_BTRUSPA_POS (18U) +#define TMR6_BCONR_BTRUSPA (0x00040000UL) +#define TMR6_BCONR_BTRDSPA_POS (19U) +#define TMR6_BCONR_BTRDSPA (0x00080000UL) +#define TMR6_BCONR_BENSPB_POS (20U) +#define TMR6_BCONR_BENSPB (0x00100000UL) +#define TMR6_BCONR_BSESPB_POS (21U) +#define TMR6_BCONR_BSESPB (0x00200000UL) +#define TMR6_BCONR_BTRUSPB_POS (22U) +#define TMR6_BCONR_BTRUSPB (0x00400000UL) +#define TMR6_BCONR_BTRDSPB_POS (23U) +#define TMR6_BCONR_BTRDSPB (0x00800000UL) + +/* Bit definition for TMR6_DCONR register */ +#define TMR6_DCONR_DTCEN_POS (0U) +#define TMR6_DCONR_DTCEN (0x00000001UL) +#define TMR6_DCONR_SEPA_POS (1U) +#define TMR6_DCONR_SEPA (0x00000002UL) +#define TMR6_DCONR_DTBENU_POS (4U) +#define TMR6_DCONR_DTBENU (0x00000010UL) +#define TMR6_DCONR_DTBEND_POS (5U) +#define TMR6_DCONR_DTBEND (0x00000020UL) +#define TMR6_DCONR_DTBTRU_POS (6U) +#define TMR6_DCONR_DTBTRU (0x00000040UL) +#define TMR6_DCONR_DTBTRD_POS (7U) +#define TMR6_DCONR_DTBTRD (0x00000080UL) + +/* Bit definition for TMR6_PCNAR register */ +#define TMR6_PCNAR_STACA_POS (0U) +#define TMR6_PCNAR_STACA (0x00000003UL) +#define TMR6_PCNAR_STACA_0 (0x00000001UL) +#define TMR6_PCNAR_STACA_1 (0x00000002UL) +#define TMR6_PCNAR_STPCA_POS (2U) +#define TMR6_PCNAR_STPCA (0x0000000CUL) +#define TMR6_PCNAR_STPCA_0 (0x00000004UL) +#define TMR6_PCNAR_STPCA_1 (0x00000008UL) +#define TMR6_PCNAR_OVFCA_POS (4U) +#define TMR6_PCNAR_OVFCA (0x00000030UL) +#define TMR6_PCNAR_OVFCA_0 (0x00000010UL) +#define TMR6_PCNAR_OVFCA_1 (0x00000020UL) +#define TMR6_PCNAR_UDFCA_POS (6U) +#define TMR6_PCNAR_UDFCA (0x000000C0UL) +#define TMR6_PCNAR_UDFCA_0 (0x00000040UL) +#define TMR6_PCNAR_UDFCA_1 (0x00000080UL) +#define TMR6_PCNAR_CMAUCA_POS (8U) +#define TMR6_PCNAR_CMAUCA (0x00000300UL) +#define TMR6_PCNAR_CMAUCA_0 (0x00000100UL) +#define TMR6_PCNAR_CMAUCA_1 (0x00000200UL) +#define TMR6_PCNAR_CMADCA_POS (10U) +#define TMR6_PCNAR_CMADCA (0x00000C00UL) +#define TMR6_PCNAR_CMADCA_0 (0x00000400UL) +#define TMR6_PCNAR_CMADCA_1 (0x00000800UL) +#define TMR6_PCNAR_CMBUCA_POS (12U) +#define TMR6_PCNAR_CMBUCA (0x00003000UL) +#define TMR6_PCNAR_CMBUCA_0 (0x00001000UL) +#define TMR6_PCNAR_CMBUCA_1 (0x00002000UL) +#define TMR6_PCNAR_CMBDCA_POS (14U) +#define TMR6_PCNAR_CMBDCA (0x0000C000UL) +#define TMR6_PCNAR_CMBDCA_0 (0x00004000UL) +#define TMR6_PCNAR_CMBDCA_1 (0x00008000UL) +#define TMR6_PCNAR_FORCA_POS (16U) +#define TMR6_PCNAR_FORCA (0x00030000UL) +#define TMR6_PCNAR_FORCA_0 (0x00010000UL) +#define TMR6_PCNAR_FORCA_1 (0x00020000UL) +#define TMR6_PCNAR_EMBCA_POS (20U) +#define TMR6_PCNAR_EMBCA (0x00300000UL) +#define TMR6_PCNAR_EMBCA_0 (0x00100000UL) +#define TMR6_PCNAR_EMBCA_1 (0x00200000UL) +#define TMR6_PCNAR_EMBRA_POS (22U) +#define TMR6_PCNAR_EMBRA (0x00C00000UL) +#define TMR6_PCNAR_EMBRA_0 (0x00400000UL) +#define TMR6_PCNAR_EMBRA_1 (0x00800000UL) +#define TMR6_PCNAR_EMBSA_POS (24U) +#define TMR6_PCNAR_EMBSA (0x03000000UL) +#define TMR6_PCNAR_EMBSA_0 (0x01000000UL) +#define TMR6_PCNAR_EMBSA_1 (0x02000000UL) +#define TMR6_PCNAR_OUTENA_POS (28U) +#define TMR6_PCNAR_OUTENA (0x10000000UL) +#define TMR6_PCNAR_CAPMDA_POS (31U) +#define TMR6_PCNAR_CAPMDA (0x80000000UL) + +/* Bit definition for TMR6_PCNBR register */ +#define TMR6_PCNBR_STACB_POS (0U) +#define TMR6_PCNBR_STACB (0x00000003UL) +#define TMR6_PCNBR_STACB_0 (0x00000001UL) +#define TMR6_PCNBR_STACB_1 (0x00000002UL) +#define TMR6_PCNBR_STPCB_POS (2U) +#define TMR6_PCNBR_STPCB (0x0000000CUL) +#define TMR6_PCNBR_STPCB_0 (0x00000004UL) +#define TMR6_PCNBR_STPCB_1 (0x00000008UL) +#define TMR6_PCNBR_OVFCB_POS (4U) +#define TMR6_PCNBR_OVFCB (0x00000030UL) +#define TMR6_PCNBR_OVFCB_0 (0x00000010UL) +#define TMR6_PCNBR_OVFCB_1 (0x00000020UL) +#define TMR6_PCNBR_UDFCB_POS (6U) +#define TMR6_PCNBR_UDFCB (0x000000C0UL) +#define TMR6_PCNBR_UDFCB_0 (0x00000040UL) +#define TMR6_PCNBR_UDFCB_1 (0x00000080UL) +#define TMR6_PCNBR_CMAUCB_POS (8U) +#define TMR6_PCNBR_CMAUCB (0x00000300UL) +#define TMR6_PCNBR_CMAUCB_0 (0x00000100UL) +#define TMR6_PCNBR_CMAUCB_1 (0x00000200UL) +#define TMR6_PCNBR_CMADCB_POS (10U) +#define TMR6_PCNBR_CMADCB (0x00000C00UL) +#define TMR6_PCNBR_CMADCB_0 (0x00000400UL) +#define TMR6_PCNBR_CMADCB_1 (0x00000800UL) +#define TMR6_PCNBR_CMBUCB_POS (12U) +#define TMR6_PCNBR_CMBUCB (0x00003000UL) +#define TMR6_PCNBR_CMBUCB_0 (0x00001000UL) +#define TMR6_PCNBR_CMBUCB_1 (0x00002000UL) +#define TMR6_PCNBR_CMBDCB_POS (14U) +#define TMR6_PCNBR_CMBDCB (0x0000C000UL) +#define TMR6_PCNBR_CMBDCB_0 (0x00004000UL) +#define TMR6_PCNBR_CMBDCB_1 (0x00008000UL) +#define TMR6_PCNBR_FORCB_POS (16U) +#define TMR6_PCNBR_FORCB (0x00030000UL) +#define TMR6_PCNBR_FORCB_0 (0x00010000UL) +#define TMR6_PCNBR_FORCB_1 (0x00020000UL) +#define TMR6_PCNBR_EMBCB_POS (20U) +#define TMR6_PCNBR_EMBCB (0x00300000UL) +#define TMR6_PCNBR_EMBCB_0 (0x00100000UL) +#define TMR6_PCNBR_EMBCB_1 (0x00200000UL) +#define TMR6_PCNBR_EMBRB_POS (22U) +#define TMR6_PCNBR_EMBRB (0x00C00000UL) +#define TMR6_PCNBR_EMBRB_0 (0x00400000UL) +#define TMR6_PCNBR_EMBRB_1 (0x00800000UL) +#define TMR6_PCNBR_EMBSB_POS (24U) +#define TMR6_PCNBR_EMBSB (0x03000000UL) +#define TMR6_PCNBR_EMBSB_0 (0x01000000UL) +#define TMR6_PCNBR_EMBSB_1 (0x02000000UL) +#define TMR6_PCNBR_OUTENB_POS (28U) +#define TMR6_PCNBR_OUTENB (0x10000000UL) +#define TMR6_PCNBR_CAPMDB_POS (31U) +#define TMR6_PCNBR_CAPMDB (0x80000000UL) + +/* Bit definition for TMR6_FCNGR register */ +#define TMR6_FCNGR_NOFIENGA_POS (0U) +#define TMR6_FCNGR_NOFIENGA (0x00000001UL) +#define TMR6_FCNGR_NOFICKGA_POS (1U) +#define TMR6_FCNGR_NOFICKGA (0x00000006UL) +#define TMR6_FCNGR_NOFICKGA_0 (0x00000002UL) +#define TMR6_FCNGR_NOFICKGA_1 (0x00000004UL) +#define TMR6_FCNGR_NOFIENGB_POS (4U) +#define TMR6_FCNGR_NOFIENGB (0x00000010UL) +#define TMR6_FCNGR_NOFICKGB_POS (5U) +#define TMR6_FCNGR_NOFICKGB (0x00000060UL) +#define TMR6_FCNGR_NOFICKGB_0 (0x00000020UL) +#define TMR6_FCNGR_NOFICKGB_1 (0x00000040UL) + +/* Bit definition for TMR6_VPERR register */ +#define TMR6_VPERR_SPPERIA_POS (8U) +#define TMR6_VPERR_SPPERIA (0x00000100UL) +#define TMR6_VPERR_SPPERIB_POS (9U) +#define TMR6_VPERR_SPPERIB (0x00000200UL) +#define TMR6_VPERR_PCNTE_POS (16U) +#define TMR6_VPERR_PCNTE (0x00030000UL) +#define TMR6_VPERR_PCNTE_0 (0x00010000UL) +#define TMR6_VPERR_PCNTE_1 (0x00020000UL) +#define TMR6_VPERR_PCNTS_POS (18U) +#define TMR6_VPERR_PCNTS (0x001C0000UL) +#define TMR6_VPERR_PCNTS_0 (0x00040000UL) +#define TMR6_VPERR_PCNTS_1 (0x00080000UL) +#define TMR6_VPERR_PCNTS_2 (0x00100000UL) + +/* Bit definition for TMR6_STFLR register */ +#define TMR6_STFLR_CMAF_POS (0U) +#define TMR6_STFLR_CMAF (0x00000001UL) +#define TMR6_STFLR_CMBF_POS (1U) +#define TMR6_STFLR_CMBF (0x00000002UL) +#define TMR6_STFLR_CMCF_POS (2U) +#define TMR6_STFLR_CMCF (0x00000004UL) +#define TMR6_STFLR_CMDF_POS (3U) +#define TMR6_STFLR_CMDF (0x00000008UL) +#define TMR6_STFLR_CMEF_POS (4U) +#define TMR6_STFLR_CMEF (0x00000010UL) +#define TMR6_STFLR_CMFF_POS (5U) +#define TMR6_STFLR_CMFF (0x00000020UL) +#define TMR6_STFLR_OVFF_POS (6U) +#define TMR6_STFLR_OVFF (0x00000040UL) +#define TMR6_STFLR_UDFF_POS (7U) +#define TMR6_STFLR_UDFF (0x00000080UL) +#define TMR6_STFLR_DTEF_POS (8U) +#define TMR6_STFLR_DTEF (0x00000100UL) +#define TMR6_STFLR_CMSAUF_POS (9U) +#define TMR6_STFLR_CMSAUF (0x00000200UL) +#define TMR6_STFLR_CMSADF_POS (10U) +#define TMR6_STFLR_CMSADF (0x00000400UL) +#define TMR6_STFLR_CMSBUF_POS (11U) +#define TMR6_STFLR_CMSBUF (0x00000800UL) +#define TMR6_STFLR_CMSBDF_POS (12U) +#define TMR6_STFLR_CMSBDF (0x00001000UL) +#define TMR6_STFLR_VPERNUM_POS (21U) +#define TMR6_STFLR_VPERNUM (0x00E00000UL) +#define TMR6_STFLR_VPERNUM_0 (0x00200000UL) +#define TMR6_STFLR_VPERNUM_1 (0x00400000UL) +#define TMR6_STFLR_VPERNUM_2 (0x00800000UL) +#define TMR6_STFLR_DIRF_POS (31U) +#define TMR6_STFLR_DIRF (0x80000000UL) + +/* Bit definition for TMR6_HSTAR register */ +#define TMR6_HSTAR_HSTA0_POS (0U) +#define TMR6_HSTAR_HSTA0 (0x00000001UL) +#define TMR6_HSTAR_HSTA1_POS (1U) +#define TMR6_HSTAR_HSTA1 (0x00000002UL) +#define TMR6_HSTAR_HSTA2_POS (2U) +#define TMR6_HSTAR_HSTA2 (0x00000004UL) +#define TMR6_HSTAR_HSTA3_POS (3U) +#define TMR6_HSTAR_HSTA3 (0x00000008UL) +#define TMR6_HSTAR_STAS_POS (7U) +#define TMR6_HSTAR_STAS (0x00000080UL) +#define TMR6_HSTAR_HSTA8_POS (8U) +#define TMR6_HSTAR_HSTA8 (0x00000100UL) +#define TMR6_HSTAR_HSTA9_POS (9U) +#define TMR6_HSTAR_HSTA9 (0x00000200UL) +#define TMR6_HSTAR_HSTA10_POS (10U) +#define TMR6_HSTAR_HSTA10 (0x00000400UL) +#define TMR6_HSTAR_HSTA11_POS (11U) +#define TMR6_HSTAR_HSTA11 (0x00000800UL) +#define TMR6_HSTAR_HSTA16_POS (16U) +#define TMR6_HSTAR_HSTA16 (0x00010000UL) +#define TMR6_HSTAR_HSTA17_POS (17U) +#define TMR6_HSTAR_HSTA17 (0x00020000UL) +#define TMR6_HSTAR_HSTA18_POS (18U) +#define TMR6_HSTAR_HSTA18 (0x00040000UL) +#define TMR6_HSTAR_HSTA19_POS (19U) +#define TMR6_HSTAR_HSTA19 (0x00080000UL) +#define TMR6_HSTAR_HSTA20_POS (20U) +#define TMR6_HSTAR_HSTA20 (0x00100000UL) +#define TMR6_HSTAR_HSTA21_POS (21U) +#define TMR6_HSTAR_HSTA21 (0x00200000UL) +#define TMR6_HSTAR_HSTA22_POS (22U) +#define TMR6_HSTAR_HSTA22 (0x00400000UL) +#define TMR6_HSTAR_HSTA23_POS (23U) +#define TMR6_HSTAR_HSTA23 (0x00800000UL) + +/* Bit definition for TMR6_HSTPR register */ +#define TMR6_HSTPR_HSTP0_POS (0U) +#define TMR6_HSTPR_HSTP0 (0x00000001UL) +#define TMR6_HSTPR_HSTP1_POS (1U) +#define TMR6_HSTPR_HSTP1 (0x00000002UL) +#define TMR6_HSTPR_HSTP2_POS (2U) +#define TMR6_HSTPR_HSTP2 (0x00000004UL) +#define TMR6_HSTPR_HSTP3_POS (3U) +#define TMR6_HSTPR_HSTP3 (0x00000008UL) +#define TMR6_HSTPR_STPS_POS (7U) +#define TMR6_HSTPR_STPS (0x00000080UL) +#define TMR6_HSTPR_HSTP8_POS (8U) +#define TMR6_HSTPR_HSTP8 (0x00000100UL) +#define TMR6_HSTPR_HSTP9_POS (9U) +#define TMR6_HSTPR_HSTP9 (0x00000200UL) +#define TMR6_HSTPR_HSTP10_POS (10U) +#define TMR6_HSTPR_HSTP10 (0x00000400UL) +#define TMR6_HSTPR_HSTP11_POS (11U) +#define TMR6_HSTPR_HSTP11 (0x00000800UL) +#define TMR6_HSTPR_HSTP16_POS (16U) +#define TMR6_HSTPR_HSTP16 (0x00010000UL) +#define TMR6_HSTPR_HSTP17_POS (17U) +#define TMR6_HSTPR_HSTP17 (0x00020000UL) +#define TMR6_HSTPR_HSTP18_POS (18U) +#define TMR6_HSTPR_HSTP18 (0x00040000UL) +#define TMR6_HSTPR_HSTP19_POS (19U) +#define TMR6_HSTPR_HSTP19 (0x00080000UL) +#define TMR6_HSTPR_HSTP20_POS (20U) +#define TMR6_HSTPR_HSTP20 (0x00100000UL) +#define TMR6_HSTPR_HSTP21_POS (21U) +#define TMR6_HSTPR_HSTP21 (0x00200000UL) +#define TMR6_HSTPR_HSTP22_POS (22U) +#define TMR6_HSTPR_HSTP22 (0x00400000UL) +#define TMR6_HSTPR_HSTP23_POS (23U) +#define TMR6_HSTPR_HSTP23 (0x00800000UL) + +/* Bit definition for TMR6_HCLRR register */ +#define TMR6_HCLRR_HCLE0_POS (0U) +#define TMR6_HCLRR_HCLE0 (0x00000001UL) +#define TMR6_HCLRR_HCLE1_POS (1U) +#define TMR6_HCLRR_HCLE1 (0x00000002UL) +#define TMR6_HCLRR_HCLE2_POS (2U) +#define TMR6_HCLRR_HCLE2 (0x00000004UL) +#define TMR6_HCLRR_HCLE3_POS (3U) +#define TMR6_HCLRR_HCLE3 (0x00000008UL) +#define TMR6_HCLRR_CLES_POS (7U) +#define TMR6_HCLRR_CLES (0x00000080UL) +#define TMR6_HCLRR_HCLE8_POS (8U) +#define TMR6_HCLRR_HCLE8 (0x00000100UL) +#define TMR6_HCLRR_HCLE9_POS (9U) +#define TMR6_HCLRR_HCLE9 (0x00000200UL) +#define TMR6_HCLRR_HCLE10_POS (10U) +#define TMR6_HCLRR_HCLE10 (0x00000400UL) +#define TMR6_HCLRR_HCLE11_POS (11U) +#define TMR6_HCLRR_HCLE11 (0x00000800UL) +#define TMR6_HCLRR_HCLE16_POS (16U) +#define TMR6_HCLRR_HCLE16 (0x00010000UL) +#define TMR6_HCLRR_HCLE17_POS (17U) +#define TMR6_HCLRR_HCLE17 (0x00020000UL) +#define TMR6_HCLRR_HCLE18_POS (18U) +#define TMR6_HCLRR_HCLE18 (0x00040000UL) +#define TMR6_HCLRR_HCLE19_POS (19U) +#define TMR6_HCLRR_HCLE19 (0x00080000UL) +#define TMR6_HCLRR_HCLE20_POS (20U) +#define TMR6_HCLRR_HCLE20 (0x00100000UL) +#define TMR6_HCLRR_HCLE21_POS (21U) +#define TMR6_HCLRR_HCLE21 (0x00200000UL) +#define TMR6_HCLRR_HCLE22_POS (22U) +#define TMR6_HCLRR_HCLE22 (0x00400000UL) +#define TMR6_HCLRR_HCLE23_POS (23U) +#define TMR6_HCLRR_HCLE23 (0x00800000UL) + +/* Bit definition for TMR6_HUPDR register */ +#define TMR6_HUPDR_HUPD0_POS (0U) +#define TMR6_HUPDR_HUPD0 (0x00000001UL) +#define TMR6_HUPDR_HUPD1_POS (1U) +#define TMR6_HUPDR_HUPD1 (0x00000002UL) +#define TMR6_HUPDR_HUPD2_POS (2U) +#define TMR6_HUPDR_HUPD2 (0x00000004UL) +#define TMR6_HUPDR_HUPD3_POS (3U) +#define TMR6_HUPDR_HUPD3 (0x00000008UL) +#define TMR6_HUPDR_UPDS_POS (7U) +#define TMR6_HUPDR_UPDS (0x00000080UL) +#define TMR6_HUPDR_HUPD8_POS (8U) +#define TMR6_HUPDR_HUPD8 (0x00000100UL) +#define TMR6_HUPDR_HUPD9_POS (9U) +#define TMR6_HUPDR_HUPD9 (0x00000200UL) +#define TMR6_HUPDR_HUPD10_POS (10U) +#define TMR6_HUPDR_HUPD10 (0x00000400UL) +#define TMR6_HUPDR_HUPD11_POS (11U) +#define TMR6_HUPDR_HUPD11 (0x00000800UL) +#define TMR6_HUPDR_HUPD16_POS (16U) +#define TMR6_HUPDR_HUPD16 (0x00010000UL) +#define TMR6_HUPDR_HUPD17_POS (17U) +#define TMR6_HUPDR_HUPD17 (0x00020000UL) +#define TMR6_HUPDR_HUPD18_POS (18U) +#define TMR6_HUPDR_HUPD18 (0x00040000UL) +#define TMR6_HUPDR_HUPD19_POS (19U) +#define TMR6_HUPDR_HUPD19 (0x00080000UL) +#define TMR6_HUPDR_HUPD20_POS (20U) +#define TMR6_HUPDR_HUPD20 (0x00100000UL) +#define TMR6_HUPDR_HUPD21_POS (21U) +#define TMR6_HUPDR_HUPD21 (0x00200000UL) +#define TMR6_HUPDR_HUPD22_POS (22U) +#define TMR6_HUPDR_HUPD22 (0x00400000UL) +#define TMR6_HUPDR_HUPD23_POS (23U) +#define TMR6_HUPDR_HUPD23 (0x00800000UL) + +/* Bit definition for TMR6_HCPAR register */ +#define TMR6_HCPAR_HCPA0_POS (0U) +#define TMR6_HCPAR_HCPA0 (0x00000001UL) +#define TMR6_HCPAR_HCPA1_POS (1U) +#define TMR6_HCPAR_HCPA1 (0x00000002UL) +#define TMR6_HCPAR_HCPA2_POS (2U) +#define TMR6_HCPAR_HCPA2 (0x00000004UL) +#define TMR6_HCPAR_HCPA3_POS (3U) +#define TMR6_HCPAR_HCPA3 (0x00000008UL) +#define TMR6_HCPAR_HCPA8_POS (8U) +#define TMR6_HCPAR_HCPA8 (0x00000100UL) +#define TMR6_HCPAR_HCPA9_POS (9U) +#define TMR6_HCPAR_HCPA9 (0x00000200UL) +#define TMR6_HCPAR_HCPA10_POS (10U) +#define TMR6_HCPAR_HCPA10 (0x00000400UL) +#define TMR6_HCPAR_HCPA11_POS (11U) +#define TMR6_HCPAR_HCPA11 (0x00000800UL) +#define TMR6_HCPAR_HCPA16_POS (16U) +#define TMR6_HCPAR_HCPA16 (0x00010000UL) +#define TMR6_HCPAR_HCPA17_POS (17U) +#define TMR6_HCPAR_HCPA17 (0x00020000UL) +#define TMR6_HCPAR_HCPA18_POS (18U) +#define TMR6_HCPAR_HCPA18 (0x00040000UL) +#define TMR6_HCPAR_HCPA19_POS (19U) +#define TMR6_HCPAR_HCPA19 (0x00080000UL) +#define TMR6_HCPAR_HCPA20_POS (20U) +#define TMR6_HCPAR_HCPA20 (0x00100000UL) +#define TMR6_HCPAR_HCPA21_POS (21U) +#define TMR6_HCPAR_HCPA21 (0x00200000UL) +#define TMR6_HCPAR_HCPA22_POS (22U) +#define TMR6_HCPAR_HCPA22 (0x00400000UL) +#define TMR6_HCPAR_HCPA23_POS (23U) +#define TMR6_HCPAR_HCPA23 (0x00800000UL) + +/* Bit definition for TMR6_HCPBR register */ +#define TMR6_HCPBR_HCPB0_POS (0U) +#define TMR6_HCPBR_HCPB0 (0x00000001UL) +#define TMR6_HCPBR_HCPB1_POS (1U) +#define TMR6_HCPBR_HCPB1 (0x00000002UL) +#define TMR6_HCPBR_HCPB2_POS (2U) +#define TMR6_HCPBR_HCPB2 (0x00000004UL) +#define TMR6_HCPBR_HCPB3_POS (3U) +#define TMR6_HCPBR_HCPB3 (0x00000008UL) +#define TMR6_HCPBR_HCPB8_POS (8U) +#define TMR6_HCPBR_HCPB8 (0x00000100UL) +#define TMR6_HCPBR_HCPB9_POS (9U) +#define TMR6_HCPBR_HCPB9 (0x00000200UL) +#define TMR6_HCPBR_HCPB10_POS (10U) +#define TMR6_HCPBR_HCPB10 (0x00000400UL) +#define TMR6_HCPBR_HCPB11_POS (11U) +#define TMR6_HCPBR_HCPB11 (0x00000800UL) +#define TMR6_HCPBR_HCPB16_POS (16U) +#define TMR6_HCPBR_HCPB16 (0x00010000UL) +#define TMR6_HCPBR_HCPB17_POS (17U) +#define TMR6_HCPBR_HCPB17 (0x00020000UL) +#define TMR6_HCPBR_HCPB18_POS (18U) +#define TMR6_HCPBR_HCPB18 (0x00040000UL) +#define TMR6_HCPBR_HCPB19_POS (19U) +#define TMR6_HCPBR_HCPB19 (0x00080000UL) +#define TMR6_HCPBR_HCPB20_POS (20U) +#define TMR6_HCPBR_HCPB20 (0x00100000UL) +#define TMR6_HCPBR_HCPB21_POS (21U) +#define TMR6_HCPBR_HCPB21 (0x00200000UL) +#define TMR6_HCPBR_HCPB22_POS (22U) +#define TMR6_HCPBR_HCPB22 (0x00400000UL) +#define TMR6_HCPBR_HCPB23_POS (23U) +#define TMR6_HCPBR_HCPB23 (0x00800000UL) + +/* Bit definition for TMR6_HCUPR register */ +#define TMR6_HCUPR_HCUP0_POS (0U) +#define TMR6_HCUPR_HCUP0 (0x00000001UL) +#define TMR6_HCUPR_HCUP1_POS (1U) +#define TMR6_HCUPR_HCUP1 (0x00000002UL) +#define TMR6_HCUPR_HCUP2_POS (2U) +#define TMR6_HCUPR_HCUP2 (0x00000004UL) +#define TMR6_HCUPR_HCUP3_POS (3U) +#define TMR6_HCUPR_HCUP3 (0x00000008UL) +#define TMR6_HCUPR_HCUP4_POS (4U) +#define TMR6_HCUPR_HCUP4 (0x00000010UL) +#define TMR6_HCUPR_HCUP5_POS (5U) +#define TMR6_HCUPR_HCUP5 (0x00000020UL) +#define TMR6_HCUPR_HCUP6_POS (6U) +#define TMR6_HCUPR_HCUP6 (0x00000040UL) +#define TMR6_HCUPR_HCUP7_POS (7U) +#define TMR6_HCUPR_HCUP7 (0x00000080UL) +#define TMR6_HCUPR_HCUP8_POS (8U) +#define TMR6_HCUPR_HCUP8 (0x00000100UL) +#define TMR6_HCUPR_HCUP9_POS (9U) +#define TMR6_HCUPR_HCUP9 (0x00000200UL) +#define TMR6_HCUPR_HCUP10_POS (10U) +#define TMR6_HCUPR_HCUP10 (0x00000400UL) +#define TMR6_HCUPR_HCUP11_POS (11U) +#define TMR6_HCUPR_HCUP11 (0x00000800UL) +#define TMR6_HCUPR_HCUP16_POS (16U) +#define TMR6_HCUPR_HCUP16 (0x00010000UL) +#define TMR6_HCUPR_HCUP17_POS (17U) +#define TMR6_HCUPR_HCUP17 (0x00020000UL) +#define TMR6_HCUPR_HCUP18_POS (18U) +#define TMR6_HCUPR_HCUP18 (0x00040000UL) +#define TMR6_HCUPR_HCUP19_POS (19U) +#define TMR6_HCUPR_HCUP19 (0x00080000UL) +#define TMR6_HCUPR_HCUP20_POS (20U) +#define TMR6_HCUPR_HCUP20 (0x00100000UL) +#define TMR6_HCUPR_HCUP21_POS (21U) +#define TMR6_HCUPR_HCUP21 (0x00200000UL) +#define TMR6_HCUPR_HCUP22_POS (22U) +#define TMR6_HCUPR_HCUP22 (0x00400000UL) +#define TMR6_HCUPR_HCUP23_POS (23U) +#define TMR6_HCUPR_HCUP23 (0x00800000UL) + +/* Bit definition for TMR6_HCDOR register */ +#define TMR6_HCDOR_HCDO0_POS (0U) +#define TMR6_HCDOR_HCDO0 (0x00000001UL) +#define TMR6_HCDOR_HCDO1_POS (1U) +#define TMR6_HCDOR_HCDO1 (0x00000002UL) +#define TMR6_HCDOR_HCDO2_POS (2U) +#define TMR6_HCDOR_HCDO2 (0x00000004UL) +#define TMR6_HCDOR_HCDO3_POS (3U) +#define TMR6_HCDOR_HCDO3 (0x00000008UL) +#define TMR6_HCDOR_HCDO4_POS (4U) +#define TMR6_HCDOR_HCDO4 (0x00000010UL) +#define TMR6_HCDOR_HCDO5_POS (5U) +#define TMR6_HCDOR_HCDO5 (0x00000020UL) +#define TMR6_HCDOR_HCDO6_POS (6U) +#define TMR6_HCDOR_HCDO6 (0x00000040UL) +#define TMR6_HCDOR_HCDO7_POS (7U) +#define TMR6_HCDOR_HCDO7 (0x00000080UL) +#define TMR6_HCDOR_HCDO8_POS (8U) +#define TMR6_HCDOR_HCDO8 (0x00000100UL) +#define TMR6_HCDOR_HCDO9_POS (9U) +#define TMR6_HCDOR_HCDO9 (0x00000200UL) +#define TMR6_HCDOR_HCDO10_POS (10U) +#define TMR6_HCDOR_HCDO10 (0x00000400UL) +#define TMR6_HCDOR_HCDO11_POS (11U) +#define TMR6_HCDOR_HCDO11 (0x00000800UL) +#define TMR6_HCDOR_HCDO16_POS (16U) +#define TMR6_HCDOR_HCDO16 (0x00010000UL) +#define TMR6_HCDOR_HCDO17_POS (17U) +#define TMR6_HCDOR_HCDO17 (0x00020000UL) +#define TMR6_HCDOR_HCDO18_POS (18U) +#define TMR6_HCDOR_HCDO18 (0x00040000UL) +#define TMR6_HCDOR_HCDO19_POS (19U) +#define TMR6_HCDOR_HCDO19 (0x00080000UL) +#define TMR6_HCDOR_HCDO20_POS (20U) +#define TMR6_HCDOR_HCDO20 (0x00100000UL) +#define TMR6_HCDOR_HCDO21_POS (21U) +#define TMR6_HCDOR_HCDO21 (0x00200000UL) +#define TMR6_HCDOR_HCDO22_POS (22U) +#define TMR6_HCDOR_HCDO22 (0x00400000UL) +#define TMR6_HCDOR_HCDO23_POS (23U) +#define TMR6_HCDOR_HCDO23 (0x00800000UL) + +/* Bit definition for TMR6_FCNTR register */ +#define TMR6_FCNTR_NOFIENTA_POS (0U) +#define TMR6_FCNTR_NOFIENTA (0x00000001UL) +#define TMR6_FCNTR_NOFICKTA_POS (1U) +#define TMR6_FCNTR_NOFICKTA (0x00000006UL) +#define TMR6_FCNTR_NOFICKTA_0 (0x00000002UL) +#define TMR6_FCNTR_NOFICKTA_1 (0x00000004UL) +#define TMR6_FCNTR_NOFIENTB_POS (4U) +#define TMR6_FCNTR_NOFIENTB (0x00000010UL) +#define TMR6_FCNTR_NOFICKTB_POS (5U) +#define TMR6_FCNTR_NOFICKTB (0x00000060UL) +#define TMR6_FCNTR_NOFICKTB_0 (0x00000020UL) +#define TMR6_FCNTR_NOFICKTB_1 (0x00000040UL) +#define TMR6_FCNTR_NOFIENTC_POS (8U) +#define TMR6_FCNTR_NOFIENTC (0x00000100UL) +#define TMR6_FCNTR_NOFICKTC_POS (9U) +#define TMR6_FCNTR_NOFICKTC (0x00000600UL) +#define TMR6_FCNTR_NOFICKTC_0 (0x00000200UL) +#define TMR6_FCNTR_NOFICKTC_1 (0x00000400UL) +#define TMR6_FCNTR_NOFIENTD_POS (12U) +#define TMR6_FCNTR_NOFIENTD (0x00001000UL) +#define TMR6_FCNTR_NOFICKTD_POS (13U) +#define TMR6_FCNTR_NOFICKTD (0x00006000UL) +#define TMR6_FCNTR_NOFICKTD_0 (0x00002000UL) +#define TMR6_FCNTR_NOFICKTD_1 (0x00004000UL) + +/* Bit definition for TMR6_SSTAR register */ +#define TMR6_SSTAR_SSTA1_POS (0U) +#define TMR6_SSTAR_SSTA1 (0x00000001UL) +#define TMR6_SSTAR_SSTA2_POS (1U) +#define TMR6_SSTAR_SSTA2 (0x00000002UL) +#define TMR6_SSTAR_SSTA3_POS (2U) +#define TMR6_SSTAR_SSTA3 (0x00000004UL) +#define TMR6_SSTAR_SSTA4_POS (3U) +#define TMR6_SSTAR_SSTA4 (0x00000008UL) +#define TMR6_SSTAR_SSTA5_POS (4U) +#define TMR6_SSTAR_SSTA5 (0x00000010UL) +#define TMR6_SSTAR_SSTA6_POS (5U) +#define TMR6_SSTAR_SSTA6 (0x00000020UL) +#define TMR6_SSTAR_SSTA7_POS (6U) +#define TMR6_SSTAR_SSTA7 (0x00000040UL) +#define TMR6_SSTAR_SSTA8_POS (7U) +#define TMR6_SSTAR_SSTA8 (0x00000080UL) + +/* Bit definition for TMR6_SSTPR register */ +#define TMR6_SSTPR_SSTP1_POS (0U) +#define TMR6_SSTPR_SSTP1 (0x00000001UL) +#define TMR6_SSTPR_SSTP2_POS (1U) +#define TMR6_SSTPR_SSTP2 (0x00000002UL) +#define TMR6_SSTPR_SSTP3_POS (2U) +#define TMR6_SSTPR_SSTP3 (0x00000004UL) +#define TMR6_SSTPR_SSTP4_POS (3U) +#define TMR6_SSTPR_SSTP4 (0x00000008UL) +#define TMR6_SSTPR_SSTP5_POS (4U) +#define TMR6_SSTPR_SSTP5 (0x00000010UL) +#define TMR6_SSTPR_SSTP6_POS (5U) +#define TMR6_SSTPR_SSTP6 (0x00000020UL) +#define TMR6_SSTPR_SSTP7_POS (6U) +#define TMR6_SSTPR_SSTP7 (0x00000040UL) +#define TMR6_SSTPR_SSTP8_POS (7U) +#define TMR6_SSTPR_SSTP8 (0x00000080UL) + +/* Bit definition for TMR6_SCLRR register */ +#define TMR6_SCLRR_SCLE1_POS (0U) +#define TMR6_SCLRR_SCLE1 (0x00000001UL) +#define TMR6_SCLRR_SCLE2_POS (1U) +#define TMR6_SCLRR_SCLE2 (0x00000002UL) +#define TMR6_SCLRR_SCLE3_POS (2U) +#define TMR6_SCLRR_SCLE3 (0x00000004UL) +#define TMR6_SCLRR_SCLE4_POS (3U) +#define TMR6_SCLRR_SCLE4 (0x00000008UL) +#define TMR6_SCLRR_SCLE5_POS (4U) +#define TMR6_SCLRR_SCLE5 (0x00000010UL) +#define TMR6_SCLRR_SCLE6_POS (5U) +#define TMR6_SCLRR_SCLE6 (0x00000020UL) +#define TMR6_SCLRR_SCLE7_POS (6U) +#define TMR6_SCLRR_SCLE7 (0x00000040UL) +#define TMR6_SCLRR_SCLE8_POS (7U) +#define TMR6_SCLRR_SCLE8 (0x00000080UL) + +/* Bit definition for TMR6_SUPDR register */ +#define TMR6_SUPDR_SUPD1_POS (0U) +#define TMR6_SUPDR_SUPD1 (0x00000001UL) +#define TMR6_SUPDR_SUPD2_POS (1U) +#define TMR6_SUPDR_SUPD2 (0x00000002UL) +#define TMR6_SUPDR_SUPD3_POS (2U) +#define TMR6_SUPDR_SUPD3 (0x00000004UL) +#define TMR6_SUPDR_SUPD4_POS (3U) +#define TMR6_SUPDR_SUPD4 (0x00000008UL) +#define TMR6_SUPDR_SUPD5_POS (4U) +#define TMR6_SUPDR_SUPD5 (0x00000010UL) +#define TMR6_SUPDR_SUPD6_POS (5U) +#define TMR6_SUPDR_SUPD6 (0x00000020UL) +#define TMR6_SUPDR_SUPD7_POS (6U) +#define TMR6_SUPDR_SUPD7 (0x00000040UL) +#define TMR6_SUPDR_SUPD8_POS (7U) +#define TMR6_SUPDR_SUPD8 (0x00000080UL) + +/******************************************************************************* + Bit definition for Peripheral TMRA +*******************************************************************************/ +/* Bit definition for TMRA_CNTER register */ +#define TMRA_CNTER_CNT (0x0000FFFFUL) + +/* Bit definition for TMRA_PERAR register */ +#define TMRA_PERAR_PER (0x0000FFFFUL) + +/* Bit definition for TMRA_CMPAR1 register */ +#define TMRA_CMPAR1_CMP (0x0000FFFFUL) + +/* Bit definition for TMRA_CMPAR2 register */ +#define TMRA_CMPAR2_CMP (0x0000FFFFUL) + +/* Bit definition for TMRA_CMPAR3 register */ +#define TMRA_CMPAR3_CMP (0x0000FFFFUL) + +/* Bit definition for TMRA_CMPAR4 register */ +#define TMRA_CMPAR4_CMP (0x0000FFFFUL) + +/* Bit definition for TMRA_BCSTR register */ +#define TMRA_BCSTR_START_POS (0U) +#define TMRA_BCSTR_START (0x00000001UL) +#define TMRA_BCSTR_DIR_POS (1U) +#define TMRA_BCSTR_DIR (0x00000002UL) +#define TMRA_BCSTR_MODE_POS (2U) +#define TMRA_BCSTR_MODE (0x00000004UL) +#define TMRA_BCSTR_SYNST_POS (3U) +#define TMRA_BCSTR_SYNST (0x00000008UL) +#define TMRA_BCSTR_CKDIV_POS (4U) +#define TMRA_BCSTR_CKDIV (0x000000F0UL) +#define TMRA_BCSTR_CKDIV_0 (0x00000010UL) +#define TMRA_BCSTR_CKDIV_1 (0x00000020UL) +#define TMRA_BCSTR_CKDIV_2 (0x00000040UL) +#define TMRA_BCSTR_CKDIV_3 (0x00000080UL) +#define TMRA_BCSTR_OVSTP_POS (8U) +#define TMRA_BCSTR_OVSTP (0x00000100UL) +#define TMRA_BCSTR_ITENOVF_POS (12U) +#define TMRA_BCSTR_ITENOVF (0x00001000UL) +#define TMRA_BCSTR_ITENUDF_POS (13U) +#define TMRA_BCSTR_ITENUDF (0x00002000UL) +#define TMRA_BCSTR_OVFF_POS (14U) +#define TMRA_BCSTR_OVFF (0x00004000UL) +#define TMRA_BCSTR_UDFF_POS (15U) +#define TMRA_BCSTR_UDFF (0x00008000UL) + +/* Bit definition for TMRA_HCONR register */ +#define TMRA_HCONR_HSTA0_POS (0U) +#define TMRA_HCONR_HSTA0 (0x00000001UL) +#define TMRA_HCONR_HSTA1_POS (1U) +#define TMRA_HCONR_HSTA1 (0x00000002UL) +#define TMRA_HCONR_HSTA2_POS (2U) +#define TMRA_HCONR_HSTA2 (0x00000004UL) +#define TMRA_HCONR_HSTP0_POS (4U) +#define TMRA_HCONR_HSTP0 (0x00000010UL) +#define TMRA_HCONR_HSTP1_POS (5U) +#define TMRA_HCONR_HSTP1 (0x00000020UL) +#define TMRA_HCONR_HSTP2_POS (6U) +#define TMRA_HCONR_HSTP2 (0x00000040UL) +#define TMRA_HCONR_HCLE0_POS (8U) +#define TMRA_HCONR_HCLE0 (0x00000100UL) +#define TMRA_HCONR_HCLE1_POS (9U) +#define TMRA_HCONR_HCLE1 (0x00000200UL) +#define TMRA_HCONR_HCLE2_POS (10U) +#define TMRA_HCONR_HCLE2 (0x00000400UL) +#define TMRA_HCONR_HCLE3_POS (12U) +#define TMRA_HCONR_HCLE3 (0x00001000UL) +#define TMRA_HCONR_HCLE4_POS (13U) +#define TMRA_HCONR_HCLE4 (0x00002000UL) +#define TMRA_HCONR_HCLE5_POS (14U) +#define TMRA_HCONR_HCLE5 (0x00004000UL) +#define TMRA_HCONR_HCLE6_POS (15U) +#define TMRA_HCONR_HCLE6 (0x00008000UL) + +/* Bit definition for TMRA_HCUPR register */ +#define TMRA_HCUPR_HCUP0_POS (0U) +#define TMRA_HCUPR_HCUP0 (0x00000001UL) +#define TMRA_HCUPR_HCUP1_POS (1U) +#define TMRA_HCUPR_HCUP1 (0x00000002UL) +#define TMRA_HCUPR_HCUP2_POS (2U) +#define TMRA_HCUPR_HCUP2 (0x00000004UL) +#define TMRA_HCUPR_HCUP3_POS (3U) +#define TMRA_HCUPR_HCUP3 (0x00000008UL) +#define TMRA_HCUPR_HCUP4_POS (4U) +#define TMRA_HCUPR_HCUP4 (0x00000010UL) +#define TMRA_HCUPR_HCUP5_POS (5U) +#define TMRA_HCUPR_HCUP5 (0x00000020UL) +#define TMRA_HCUPR_HCUP6_POS (6U) +#define TMRA_HCUPR_HCUP6 (0x00000040UL) +#define TMRA_HCUPR_HCUP7_POS (7U) +#define TMRA_HCUPR_HCUP7 (0x00000080UL) +#define TMRA_HCUPR_HCUP8_POS (8U) +#define TMRA_HCUPR_HCUP8 (0x00000100UL) +#define TMRA_HCUPR_HCUP9_POS (9U) +#define TMRA_HCUPR_HCUP9 (0x00000200UL) +#define TMRA_HCUPR_HCUP10_POS (10U) +#define TMRA_HCUPR_HCUP10 (0x00000400UL) +#define TMRA_HCUPR_HCUP11_POS (11U) +#define TMRA_HCUPR_HCUP11 (0x00000800UL) +#define TMRA_HCUPR_HCUP12_POS (12U) +#define TMRA_HCUPR_HCUP12 (0x00001000UL) + +/* Bit definition for TMRA_HCDOR register */ +#define TMRA_HCDOR_HCDO0_POS (0U) +#define TMRA_HCDOR_HCDO0 (0x00000001UL) +#define TMRA_HCDOR_HCDO1_POS (1U) +#define TMRA_HCDOR_HCDO1 (0x00000002UL) +#define TMRA_HCDOR_HCDO2_POS (2U) +#define TMRA_HCDOR_HCDO2 (0x00000004UL) +#define TMRA_HCDOR_HCDO3_POS (3U) +#define TMRA_HCDOR_HCDO3 (0x00000008UL) +#define TMRA_HCDOR_HCDO4_POS (4U) +#define TMRA_HCDOR_HCDO4 (0x00000010UL) +#define TMRA_HCDOR_HCDO5_POS (5U) +#define TMRA_HCDOR_HCDO5 (0x00000020UL) +#define TMRA_HCDOR_HCDO6_POS (6U) +#define TMRA_HCDOR_HCDO6 (0x00000040UL) +#define TMRA_HCDOR_HCDO7_POS (7U) +#define TMRA_HCDOR_HCDO7 (0x00000080UL) +#define TMRA_HCDOR_HCDO8_POS (8U) +#define TMRA_HCDOR_HCDO8 (0x00000100UL) +#define TMRA_HCDOR_HCDO9_POS (9U) +#define TMRA_HCDOR_HCDO9 (0x00000200UL) +#define TMRA_HCDOR_HCDO10_POS (10U) +#define TMRA_HCDOR_HCDO10 (0x00000400UL) +#define TMRA_HCDOR_HCDO11_POS (11U) +#define TMRA_HCDOR_HCDO11 (0x00000800UL) +#define TMRA_HCDOR_HCDO12_POS (12U) +#define TMRA_HCDOR_HCDO12 (0x00001000UL) + +/* Bit definition for TMRA_ICONR register */ +#define TMRA_ICONR_ITEN1_POS (0U) +#define TMRA_ICONR_ITEN1 (0x00000001UL) +#define TMRA_ICONR_ITEN2_POS (1U) +#define TMRA_ICONR_ITEN2 (0x00000002UL) +#define TMRA_ICONR_ITEN3_POS (2U) +#define TMRA_ICONR_ITEN3 (0x00000004UL) +#define TMRA_ICONR_ITEN4_POS (3U) +#define TMRA_ICONR_ITEN4 (0x00000008UL) + +/* Bit definition for TMRA_ECONR register */ +#define TMRA_ECONR_ETEN1_POS (0U) +#define TMRA_ECONR_ETEN1 (0x00000001UL) +#define TMRA_ECONR_ETEN2_POS (1U) +#define TMRA_ECONR_ETEN2 (0x00000002UL) +#define TMRA_ECONR_ETEN3_POS (2U) +#define TMRA_ECONR_ETEN3 (0x00000004UL) +#define TMRA_ECONR_ETEN4_POS (3U) +#define TMRA_ECONR_ETEN4 (0x00000008UL) + +/* Bit definition for TMRA_FCONR register */ +#define TMRA_FCONR_NOFIENTG_POS (0U) +#define TMRA_FCONR_NOFIENTG (0x00000001UL) +#define TMRA_FCONR_NOFICKTG_POS (1U) +#define TMRA_FCONR_NOFICKTG (0x00000006UL) +#define TMRA_FCONR_NOFICKTG_0 (0x00000002UL) +#define TMRA_FCONR_NOFICKTG_1 (0x00000004UL) +#define TMRA_FCONR_NOFIENCA_POS (8U) +#define TMRA_FCONR_NOFIENCA (0x00000100UL) +#define TMRA_FCONR_NOFICKCA_POS (9U) +#define TMRA_FCONR_NOFICKCA (0x00000600UL) +#define TMRA_FCONR_NOFICKCA_0 (0x00000200UL) +#define TMRA_FCONR_NOFICKCA_1 (0x00000400UL) +#define TMRA_FCONR_NOFIENCB_POS (12U) +#define TMRA_FCONR_NOFIENCB (0x00001000UL) +#define TMRA_FCONR_NOFICKCB_POS (13U) +#define TMRA_FCONR_NOFICKCB (0x00006000UL) +#define TMRA_FCONR_NOFICKCB_0 (0x00002000UL) +#define TMRA_FCONR_NOFICKCB_1 (0x00004000UL) + +/* Bit definition for TMRA_STFLR register */ +#define TMRA_STFLR_CMPF1_POS (0U) +#define TMRA_STFLR_CMPF1 (0x00000001UL) +#define TMRA_STFLR_CMPF2_POS (1U) +#define TMRA_STFLR_CMPF2 (0x00000002UL) +#define TMRA_STFLR_CMPF3_POS (2U) +#define TMRA_STFLR_CMPF3 (0x00000004UL) +#define TMRA_STFLR_CMPF4_POS (3U) +#define TMRA_STFLR_CMPF4 (0x00000008UL) + +/* Bit definition for TMRA_BCONR register */ +#define TMRA_BCONR_BEN_POS (0U) +#define TMRA_BCONR_BEN (0x00000001UL) +#define TMRA_BCONR_BSE0_POS (1U) +#define TMRA_BCONR_BSE0 (0x00000002UL) +#define TMRA_BCONR_BSE1_POS (2U) +#define TMRA_BCONR_BSE1 (0x00000004UL) + +/* Bit definition for TMRA_CCONR register */ +#define TMRA_CCONR_CAPMD_POS (0U) +#define TMRA_CCONR_CAPMD (0x00000001UL) +#define TMRA_CCONR_HICP0_POS (4U) +#define TMRA_CCONR_HICP0 (0x00000010UL) +#define TMRA_CCONR_HICP1_POS (5U) +#define TMRA_CCONR_HICP1 (0x00000020UL) +#define TMRA_CCONR_HICP2_POS (6U) +#define TMRA_CCONR_HICP2 (0x00000040UL) +#define TMRA_CCONR_HICP3_POS (8U) +#define TMRA_CCONR_HICP3 (0x00000100UL) +#define TMRA_CCONR_HICP4_POS (9U) +#define TMRA_CCONR_HICP4 (0x00000200UL) +#define TMRA_CCONR_NOFIENCP_POS (12U) +#define TMRA_CCONR_NOFIENCP (0x00001000UL) +#define TMRA_CCONR_NOFICKCP_POS (13U) +#define TMRA_CCONR_NOFICKCP (0x00006000UL) +#define TMRA_CCONR_NOFICKCP_0 (0x00002000UL) +#define TMRA_CCONR_NOFICKCP_1 (0x00004000UL) + +/* Bit definition for TMRA_PCONR register */ +#define TMRA_PCONR_STAC_POS (0U) +#define TMRA_PCONR_STAC (0x00000003UL) +#define TMRA_PCONR_STAC_0 (0x00000001UL) +#define TMRA_PCONR_STAC_1 (0x00000002UL) +#define TMRA_PCONR_STPC_POS (2U) +#define TMRA_PCONR_STPC (0x0000000CUL) +#define TMRA_PCONR_STPC_0 (0x00000004UL) +#define TMRA_PCONR_STPC_1 (0x00000008UL) +#define TMRA_PCONR_CMPC_POS (4U) +#define TMRA_PCONR_CMPC (0x00000030UL) +#define TMRA_PCONR_CMPC_0 (0x00000010UL) +#define TMRA_PCONR_CMPC_1 (0x00000020UL) +#define TMRA_PCONR_PERC_POS (6U) +#define TMRA_PCONR_PERC (0x000000C0UL) +#define TMRA_PCONR_PERC_0 (0x00000040UL) +#define TMRA_PCONR_PERC_1 (0x00000080UL) +#define TMRA_PCONR_FORC_POS (8U) +#define TMRA_PCONR_FORC (0x00000300UL) +#define TMRA_PCONR_FORC_0 (0x00000100UL) +#define TMRA_PCONR_FORC_1 (0x00000200UL) +#define TMRA_PCONR_OUTEN_POS (12U) +#define TMRA_PCONR_OUTEN (0x00001000UL) + +/******************************************************************************* + Bit definition for Peripheral TRNG +*******************************************************************************/ +/* Bit definition for TRNG_CR register */ +#define TRNG_CR_EN_POS (0U) +#define TRNG_CR_EN (0x00000001UL) +#define TRNG_CR_RUN_POS (1U) +#define TRNG_CR_RUN (0x00000002UL) + +/* Bit definition for TRNG_MR register */ +#define TRNG_MR_LOAD_POS (0U) +#define TRNG_MR_LOAD (0x00000001UL) +#define TRNG_MR_CNT_POS (2U) +#define TRNG_MR_CNT (0x0000001CUL) + +/* Bit definition for TRNG_DR0 register */ +#define TRNG_DR0 (0xFFFFFFFFUL) + +/* Bit definition for TRNG_DR1 register */ +#define TRNG_DR1 (0xFFFFFFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USART +*******************************************************************************/ +/* Bit definition for USART_SR register */ +#define USART_SR_PE_POS (0U) +#define USART_SR_PE (0x00000001UL) +#define USART_SR_FE_POS (1U) +#define USART_SR_FE (0x00000002UL) +#define USART_SR_ORE_POS (3U) +#define USART_SR_ORE (0x00000008UL) +#define USART_SR_BE_POS (4U) +#define USART_SR_BE (0x00000010UL) +#define USART_SR_RXNE_POS (5U) +#define USART_SR_RXNE (0x00000020UL) +#define USART_SR_TC_POS (6U) +#define USART_SR_TC (0x00000040UL) +#define USART_SR_TXE_POS (7U) +#define USART_SR_TXE (0x00000080UL) +#define USART_SR_RTOF_POS (8U) +#define USART_SR_RTOF (0x00000100UL) +#define USART_SR_WKUP_POS (9U) +#define USART_SR_WKUP (0x00000200UL) +#define USART_SR_LBD_POS (10U) +#define USART_SR_LBD (0x00000400UL) +#define USART_SR_MPB_POS (16U) +#define USART_SR_MPB (0x00010000UL) + +/* Bit definition for USART_DR register */ +#define USART_DR_TDR_POS (0U) +#define USART_DR_TDR (0x000001FFUL) +#define USART_DR_MPID_POS (9U) +#define USART_DR_MPID (0x00000200UL) +#define USART_DR_RDR_POS (16U) +#define USART_DR_RDR (0x01FF0000UL) + +/* Bit definition for USART_BRR register */ +#define USART_BRR_DIV_FRACTION_POS (0U) +#define USART_BRR_DIV_FRACTION (0x0000007FUL) +#define USART_BRR_DIV_INTEGER_POS (8U) +#define USART_BRR_DIV_INTEGER (0x0000FF00UL) + +/* Bit definition for USART_CR1 register */ +#define USART_CR1_RTOE_POS (0U) +#define USART_CR1_RTOE (0x00000001UL) +#define USART_CR1_RTOIE_POS (1U) +#define USART_CR1_RTOIE (0x00000002UL) +#define USART_CR1_RE_POS (2U) +#define USART_CR1_RE (0x00000004UL) +#define USART_CR1_TE_POS (3U) +#define USART_CR1_TE (0x00000008UL) +#define USART_CR1_SLME_POS (4U) +#define USART_CR1_SLME (0x00000010UL) +#define USART_CR1_RIE_POS (5U) +#define USART_CR1_RIE (0x00000020UL) +#define USART_CR1_TCIE_POS (6U) +#define USART_CR1_TCIE (0x00000040UL) +#define USART_CR1_TXEIE_POS (7U) +#define USART_CR1_TXEIE (0x00000080UL) +#define USART_CR1_PS_POS (9U) +#define USART_CR1_PS (0x00000200UL) +#define USART_CR1_PCE_POS (10U) +#define USART_CR1_PCE (0x00000400UL) +#define USART_CR1_M_POS (12U) +#define USART_CR1_M (0x00001000UL) +#define USART_CR1_OVER8_POS (15U) +#define USART_CR1_OVER8 (0x00008000UL) +#define USART_CR1_CPE_POS (16U) +#define USART_CR1_CPE (0x00010000UL) +#define USART_CR1_CFE_POS (17U) +#define USART_CR1_CFE (0x00020000UL) +#define USART_CR1_CNF_POS (18U) +#define USART_CR1_CNF (0x00040000UL) +#define USART_CR1_CORE_POS (19U) +#define USART_CR1_CORE (0x00080000UL) +#define USART_CR1_CRTOF_POS (20U) +#define USART_CR1_CRTOF (0x00100000UL) +#define USART_CR1_CBE_POS (21U) +#define USART_CR1_CBE (0x00200000UL) +#define USART_CR1_CWKUP_POS (22U) +#define USART_CR1_CWKUP (0x00400000UL) +#define USART_CR1_CLBD_POS (23U) +#define USART_CR1_CLBD (0x00800000UL) +#define USART_CR1_MS_POS (24U) +#define USART_CR1_MS (0x01000000UL) +#define USART_CR1_ML_POS (28U) +#define USART_CR1_ML (0x10000000UL) +#define USART_CR1_FBME_POS (29U) +#define USART_CR1_FBME (0x20000000UL) +#define USART_CR1_NFE_POS (30U) +#define USART_CR1_NFE (0x40000000UL) +#define USART_CR1_SBS_POS (31U) +#define USART_CR1_SBS (0x80000000UL) + +/* Bit definition for USART_CR2 register */ +#define USART_CR2_MPE_POS (0U) +#define USART_CR2_MPE (0x00000001UL) +#define USART_CR2_WKUPIE_POS (1U) +#define USART_CR2_WKUPIE (0x00000002UL) +#define USART_CR2_BEIE_POS (2U) +#define USART_CR2_BEIE (0x00000004UL) +#define USART_CR2_BEE_POS (3U) +#define USART_CR2_BEE (0x00000008UL) +#define USART_CR2_LBDIE_POS (4U) +#define USART_CR2_LBDIE (0x00000010UL) +#define USART_CR2_LBDL_POS (5U) +#define USART_CR2_LBDL (0x00000020UL) +#define USART_CR2_SBKL_POS (6U) +#define USART_CR2_SBKL (0x000000C0UL) +#define USART_CR2_SBKL_0 (0x00000040UL) +#define USART_CR2_SBKL_1 (0x00000080UL) +#define USART_CR2_WKUPE_POS (8U) +#define USART_CR2_WKUPE (0x00000100UL) +#define USART_CR2_CLKC_POS (11U) +#define USART_CR2_CLKC (0x00001800UL) +#define USART_CR2_CLKC_0 (0x00000800UL) +#define USART_CR2_CLKC_1 (0x00001000UL) +#define USART_CR2_STOP_POS (13U) +#define USART_CR2_STOP (0x00002000UL) +#define USART_CR2_LINEN_POS (14U) +#define USART_CR2_LINEN (0x00004000UL) +#define USART_CR2_SBK_POS (16U) +#define USART_CR2_SBK (0x00010000UL) +#define USART_CR2_SBKM_POS (17U) +#define USART_CR2_SBKM (0x00020000UL) + +/* Bit definition for USART_CR3 register */ +#define USART_CR3_HDSEL_POS (3U) +#define USART_CR3_HDSEL (0x00000008UL) +#define USART_CR3_LOOP_POS (4U) +#define USART_CR3_LOOP (0x00000010UL) +#define USART_CR3_SCEN_POS (5U) +#define USART_CR3_SCEN (0x00000020UL) +#define USART_CR3_RTSE_POS (8U) +#define USART_CR3_RTSE (0x00000100UL) +#define USART_CR3_CTSE_POS (9U) +#define USART_CR3_CTSE (0x00000200UL) +#define USART_CR3_BCN_POS (21U) +#define USART_CR3_BCN (0x00E00000UL) +#define USART_CR3_BCN_0 (0x00200000UL) +#define USART_CR3_BCN_1 (0x00400000UL) +#define USART_CR3_BCN_2 (0x00800000UL) + +/* Bit definition for USART_PR register */ +#define USART_PR_PSC_POS (0U) +#define USART_PR_PSC (0x00000003UL) +#define USART_PR_PSC_0 (0x00000001UL) +#define USART_PR_PSC_1 (0x00000002UL) +#define USART_PR_LBMPSC_POS (2U) +#define USART_PR_LBMPSC (0x0000000CUL) +#define USART_PR_LBMPSC_0 (0x00000004UL) +#define USART_PR_LBMPSC_1 (0x00000008UL) + +/* Bit definition for USART_LBMC register */ +#define USART_LBMC_LBMC (0x0000FFFFUL) + +/******************************************************************************* + Bit definition for Peripheral USBFS +*******************************************************************************/ +/* Bit definition for USBFS_GOTGCTL register */ +#define USBFS_GOTGCTL_SESREQSCS_POS (0U) +#define USBFS_GOTGCTL_SESREQSCS (0x00000001UL) +#define USBFS_GOTGCTL_SESREQ_POS (1U) +#define USBFS_GOTGCTL_SESREQ (0x00000002UL) +#define USBFS_GOTGCTL_VBVALIDOVEN_POS (2U) +#define USBFS_GOTGCTL_VBVALIDOVEN (0x00000004UL) +#define USBFS_GOTGCTL_VBVALIDOVVAL_POS (3U) +#define USBFS_GOTGCTL_VBVALIDOVVAL (0x00000008UL) +#define USBFS_GOTGCTL_AVALIDOVEN_POS (4U) +#define USBFS_GOTGCTL_AVALIDOVEN (0x00000010UL) +#define USBFS_GOTGCTL_AVALIDOVVAL_POS (5U) +#define USBFS_GOTGCTL_AVALIDOVVAL (0x00000020UL) +#define USBFS_GOTGCTL_BVALIDOVEN_POS (6U) +#define USBFS_GOTGCTL_BVALIDOVEN (0x00000040UL) +#define USBFS_GOTGCTL_BVALIDOVVAL_POS (7U) +#define USBFS_GOTGCTL_BVALIDOVVAL (0x00000080UL) +#define USBFS_GOTGCTL_HSTNEGSCS_POS (8U) +#define USBFS_GOTGCTL_HSTNEGSCS (0x00000100UL) +#define USBFS_GOTGCTL_HNPREQ_POS (9U) +#define USBFS_GOTGCTL_HNPREQ (0x00000200UL) +#define USBFS_GOTGCTL_HSTSETHNPEN_POS (10U) +#define USBFS_GOTGCTL_HSTSETHNPEN (0x00000400UL) +#define USBFS_GOTGCTL_DEVHNPEN_POS (11U) +#define USBFS_GOTGCTL_DEVHNPEN (0x00000800UL) +#define USBFS_GOTGCTL_EHEN_POS (12U) +#define USBFS_GOTGCTL_EHEN (0x00001000UL) +#define USBFS_GOTGCTL_DBNCEFLTRBYPASS_POS (15U) +#define USBFS_GOTGCTL_DBNCEFLTRBYPASS (0x00008000UL) +#define USBFS_GOTGCTL_CONIDSTS_POS (16U) +#define USBFS_GOTGCTL_CONIDSTS (0x00010000UL) +#define USBFS_GOTGCTL_DBNCTIME_POS (17U) +#define USBFS_GOTGCTL_DBNCTIME (0x00020000UL) +#define USBFS_GOTGCTL_ASESVLD_POS (18U) +#define USBFS_GOTGCTL_ASESVLD (0x00040000UL) +#define USBFS_GOTGCTL_BSESVLD_POS (19U) +#define USBFS_GOTGCTL_BSESVLD (0x00080000UL) +#define USBFS_GOTGCTL_OTGVER_POS (20U) +#define USBFS_GOTGCTL_OTGVER (0x00100000UL) +#define USBFS_GOTGCTL_CURMOD_POS (21U) +#define USBFS_GOTGCTL_CURMOD (0x00200000UL) + +/* Bit definition for USBFS_GOTGINT register */ +#define USBFS_GOTGINT_SESENDDET_POS (2U) +#define USBFS_GOTGINT_SESENDDET (0x00000004UL) +#define USBFS_GOTGINT_SESREQSUCSTSCHNG_POS (8U) +#define USBFS_GOTGINT_SESREQSUCSTSCHNG (0x00000100UL) +#define USBFS_GOTGINT_HSTNEGSUCSTSCHNG_POS (9U) +#define USBFS_GOTGINT_HSTNEGSUCSTSCHNG (0x00000200UL) +#define USBFS_GOTGINT_HSTNEGDET_POS (17U) +#define USBFS_GOTGINT_HSTNEGDET (0x00020000UL) +#define USBFS_GOTGINT_ADEVTOUTCHG_POS (18U) +#define USBFS_GOTGINT_ADEVTOUTCHG (0x00040000UL) +#define USBFS_GOTGINT_DBNCEDONE_POS (19U) +#define USBFS_GOTGINT_DBNCEDONE (0x00080000UL) + +/* Bit definition for USBFS_GAHBCFG register */ +#define USBFS_GAHBCFG_GLBLINTRMSK_POS (0U) +#define USBFS_GAHBCFG_GLBLINTRMSK (0x00000001UL) +#define USBFS_GAHBCFG_HBSTLEN_POS (1U) +#define USBFS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBFS_GAHBCFG_HBSTLEN_0 (0x00000002UL) +#define USBFS_GAHBCFG_HBSTLEN_1 (0x00000004UL) +#define USBFS_GAHBCFG_HBSTLEN_2 (0x00000008UL) +#define USBFS_GAHBCFG_HBSTLEN_3 (0x00000010UL) +#define USBFS_GAHBCFG_DMAEN_POS (5U) +#define USBFS_GAHBCFG_DMAEN (0x00000020UL) +#define USBFS_GAHBCFG_NPTXFEMPLVL_POS (7U) +#define USBFS_GAHBCFG_NPTXFEMPLVL (0x00000080UL) +#define USBFS_GAHBCFG_PTXFEMPLVL_POS (8U) +#define USBFS_GAHBCFG_PTXFEMPLVL (0x00000100UL) +#define USBFS_GAHBCFG_REMMEMSUPP_POS (21U) +#define USBFS_GAHBCFG_REMMEMSUPP (0x00200000UL) +#define USBFS_GAHBCFG_NOTIALLDMAWRIT_POS (22U) +#define USBFS_GAHBCFG_NOTIALLDMAWRIT (0x00400000UL) +#define USBFS_GAHBCFG_AHBSINGLE_POS (23U) +#define USBFS_GAHBCFG_AHBSINGLE (0x00800000UL) + +/* Bit definition for USBFS_GUSBCFG register */ +#define USBFS_GUSBCFG_TOUTCAL_POS (0U) +#define USBFS_GUSBCFG_TOUTCAL (0x00000007UL) +#define USBFS_GUSBCFG_TOUTCAL_0 (0x00000001UL) +#define USBFS_GUSBCFG_TOUTCAL_1 (0x00000002UL) +#define USBFS_GUSBCFG_TOUTCAL_2 (0x00000004UL) +#define USBFS_GUSBCFG_PHYIF_POS (3U) +#define USBFS_GUSBCFG_PHYIF (0x00000008UL) +#define USBFS_GUSBCFG_FSINTF_POS (5U) +#define USBFS_GUSBCFG_FSINTF (0x00000020UL) +#define USBFS_GUSBCFG_PHYSEL_POS (6U) +#define USBFS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBFS_GUSBCFG_SRPCAP_POS (8U) +#define USBFS_GUSBCFG_SRPCAP (0x00000100UL) +#define USBFS_GUSBCFG_HNPCAP_POS (9U) +#define USBFS_GUSBCFG_HNPCAP (0x00000200UL) +#define USBFS_GUSBCFG_USBTRDTIM_POS (10U) +#define USBFS_GUSBCFG_USBTRDTIM (0x00003C00UL) +#define USBFS_GUSBCFG_USBTRDTIM_0 (0x00000400UL) +#define USBFS_GUSBCFG_USBTRDTIM_1 (0x00000800UL) +#define USBFS_GUSBCFG_USBTRDTIM_2 (0x00001000UL) +#define USBFS_GUSBCFG_USBTRDTIM_3 (0x00002000UL) +#define USBFS_GUSBCFG_TERMSELDLPULSE_POS (22U) +#define USBFS_GUSBCFG_TERMSELDLPULSE (0x00400000UL) +#define USBFS_GUSBCFG_IC_USBCAP_POS (26U) +#define USBFS_GUSBCFG_IC_USBCAP (0x04000000UL) +#define USBFS_GUSBCFG_TXENDDELAY_POS (28U) +#define USBFS_GUSBCFG_TXENDDELAY (0x10000000UL) +#define USBFS_GUSBCFG_FORCEHSTMODE_POS (29U) +#define USBFS_GUSBCFG_FORCEHSTMODE (0x20000000UL) +#define USBFS_GUSBCFG_FORCEDEVMODE_POS (30U) +#define USBFS_GUSBCFG_FORCEDEVMODE (0x40000000UL) +#define USBFS_GUSBCFG_CORRUPTTXPKT_POS (31U) +#define USBFS_GUSBCFG_CORRUPTTXPKT (0x80000000UL) + +/* Bit definition for USBFS_GRSTCTL register */ +#define USBFS_GRSTCTL_CSFTRST_POS (0U) +#define USBFS_GRSTCTL_CSFTRST (0x00000001UL) +#define USBFS_GRSTCTL_PIUFSSFTRST_POS (1U) +#define USBFS_GRSTCTL_PIUFSSFTRST (0x00000002UL) +#define USBFS_GRSTCTL_FRMCNTRRST_POS (2U) +#define USBFS_GRSTCTL_FRMCNTRRST (0x00000004UL) +#define USBFS_GRSTCTL_RXFFLSH_POS (4U) +#define USBFS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBFS_GRSTCTL_TXFFLSH_POS (5U) +#define USBFS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBFS_GRSTCTL_TXFNUM_POS (6U) +#define USBFS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBFS_GRSTCTL_DMAREQ_POS (30U) +#define USBFS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBFS_GRSTCTL_AHBIDLE_POS (31U) +#define USBFS_GRSTCTL_AHBIDLE (0x80000000UL) + +/* Bit definition for USBFS_GINTSTS register */ +#define USBFS_GINTSTS_CURMOD_POS (0U) +#define USBFS_GINTSTS_CURMOD (0x00000001UL) +#define USBFS_GINTSTS_MODEMIS_POS (1U) +#define USBFS_GINTSTS_MODEMIS (0x00000002UL) +#define USBFS_GINTSTS_OTGINT_POS (2U) +#define USBFS_GINTSTS_OTGINT (0x00000004UL) +#define USBFS_GINTSTS_SOF_POS (3U) +#define USBFS_GINTSTS_SOF (0x00000008UL) +#define USBFS_GINTSTS_RXFLVL_POS (4U) +#define USBFS_GINTSTS_RXFLVL (0x00000010UL) +#define USBFS_GINTSTS_NPTXFEMP_POS (5U) +#define USBFS_GINTSTS_NPTXFEMP (0x00000020UL) +#define USBFS_GINTSTS_GINNAKEFF_POS (6U) +#define USBFS_GINTSTS_GINNAKEFF (0x00000040UL) +#define USBFS_GINTSTS_GOUTNAKEFF_POS (7U) +#define USBFS_GINTSTS_GOUTNAKEFF (0x00000080UL) +#define USBFS_GINTSTS_ERLYSUSP_POS (10U) +#define USBFS_GINTSTS_ERLYSUSP (0x00000400UL) +#define USBFS_GINTSTS_USBSUSP_POS (11U) +#define USBFS_GINTSTS_USBSUSP (0x00000800UL) +#define USBFS_GINTSTS_USBRST_POS (12U) +#define USBFS_GINTSTS_USBRST (0x00001000UL) +#define USBFS_GINTSTS_ENUMDONE_POS (13U) +#define USBFS_GINTSTS_ENUMDONE (0x00002000UL) +#define USBFS_GINTSTS_ISOOUTDROP_POS (14U) +#define USBFS_GINTSTS_ISOOUTDROP (0x00004000UL) +#define USBFS_GINTSTS_EOPF_POS (15U) +#define USBFS_GINTSTS_EOPF (0x00008000UL) +#define USBFS_GINTSTS_EPMIS_POS (17U) +#define USBFS_GINTSTS_EPMIS (0x00020000UL) +#define USBFS_GINTSTS_IEPINT_POS (18U) +#define USBFS_GINTSTS_IEPINT (0x00040000UL) +#define USBFS_GINTSTS_OEPINT_POS (19U) +#define USBFS_GINTSTS_OEPINT (0x00080000UL) +#define USBFS_GINTSTS_INCOMPISOIN_POS (20U) +#define USBFS_GINTSTS_INCOMPISOIN (0x00100000UL) +#define USBFS_GINTSTS_INCOMPLP_POS (21U) +#define USBFS_GINTSTS_INCOMPLP (0x00200000UL) +#define USBFS_GINTSTS_FETSUSP_POS (22U) +#define USBFS_GINTSTS_FETSUSP (0x00400000UL) +#define USBFS_GINTSTS_RESETDET_POS (23U) +#define USBFS_GINTSTS_RESETDET (0x00800000UL) +#define USBFS_GINTSTS_PRTINT_POS (24U) +#define USBFS_GINTSTS_PRTINT (0x01000000UL) +#define USBFS_GINTSTS_HCHINT_POS (25U) +#define USBFS_GINTSTS_HCHINT (0x02000000UL) +#define USBFS_GINTSTS_PTXFEMP_POS (26U) +#define USBFS_GINTSTS_PTXFEMP (0x04000000UL) +#define USBFS_GINTSTS_LPM_INT_POS (27U) +#define USBFS_GINTSTS_LPM_INT (0x08000000UL) +#define USBFS_GINTSTS_CONIDSTSCHNG_POS (28U) +#define USBFS_GINTSTS_CONIDSTSCHNG (0x10000000UL) +#define USBFS_GINTSTS_DISCONNINT_POS (29U) +#define USBFS_GINTSTS_DISCONNINT (0x20000000UL) +#define USBFS_GINTSTS_SESSREQINT_POS (30U) +#define USBFS_GINTSTS_SESSREQINT (0x40000000UL) +#define USBFS_GINTSTS_WKUPINT_POS (31U) +#define USBFS_GINTSTS_WKUPINT (0x80000000UL) + +/* Bit definition for USBFS_GINTMSK register */ +#define USBFS_GINTMSK_MODEMISMSK_POS (1U) +#define USBFS_GINTMSK_MODEMISMSK (0x00000002UL) +#define USBFS_GINTMSK_OTGINTMSK_POS (2U) +#define USBFS_GINTMSK_OTGINTMSK (0x00000004UL) +#define USBFS_GINTMSK_SOFMSK_POS (3U) +#define USBFS_GINTMSK_SOFMSK (0x00000008UL) +#define USBFS_GINTMSK_RXFLVLMSK_POS (4U) +#define USBFS_GINTMSK_RXFLVLMSK (0x00000010UL) +#define USBFS_GINTMSK_NPTXFEMPMSK_POS (5U) +#define USBFS_GINTMSK_NPTXFEMPMSK (0x00000020UL) +#define USBFS_GINTMSK_GINNAKEFFMSK_POS (6U) +#define USBFS_GINTMSK_GINNAKEFFMSK (0x00000040UL) +#define USBFS_GINTMSK_GOUTNAKEFFMSK_POS (7U) +#define USBFS_GINTMSK_GOUTNAKEFFMSK (0x00000080UL) +#define USBFS_GINTMSK_ERLYSUSPMSK_POS (10U) +#define USBFS_GINTMSK_ERLYSUSPMSK (0x00000400UL) +#define USBFS_GINTMSK_USBSUSPMSK_POS (11U) +#define USBFS_GINTMSK_USBSUSPMSK (0x00000800UL) +#define USBFS_GINTMSK_USBRSTMSK_POS (12U) +#define USBFS_GINTMSK_USBRSTMSK (0x00001000UL) +#define USBFS_GINTMSK_ENUMDONEMSK_POS (13U) +#define USBFS_GINTMSK_ENUMDONEMSK (0x00002000UL) +#define USBFS_GINTMSK_ISOOUTDROPMSK_POS (14U) +#define USBFS_GINTMSK_ISOOUTDROPMSK (0x00004000UL) +#define USBFS_GINTMSK_EOPFMSK_POS (15U) +#define USBFS_GINTMSK_EOPFMSK (0x00008000UL) +#define USBFS_GINTMSK_EPMISMSK_POS (17U) +#define USBFS_GINTMSK_EPMISMSK (0x00020000UL) +#define USBFS_GINTMSK_IEPINTMSK_POS (18U) +#define USBFS_GINTMSK_IEPINTMSK (0x00040000UL) +#define USBFS_GINTMSK_OEPINTMSK_POS (19U) +#define USBFS_GINTMSK_OEPINTMSK (0x00080000UL) +#define USBFS_GINTMSK_INCOMPLPMSK_POS (21U) +#define USBFS_GINTMSK_INCOMPLPMSK (0x00200000UL) +#define USBFS_GINTMSK_FETSUSPMSK_POS (22U) +#define USBFS_GINTMSK_FETSUSPMSK (0x00400000UL) +#define USBFS_GINTMSK_RESETDETMSK_POS (23U) +#define USBFS_GINTMSK_RESETDETMSK (0x00800000UL) +#define USBFS_GINTMSK_PRTINTMSK_POS (24U) +#define USBFS_GINTMSK_PRTINTMSK (0x01000000UL) +#define USBFS_GINTMSK_HCHINTMSK_POS (25U) +#define USBFS_GINTMSK_HCHINTMSK (0x02000000UL) +#define USBFS_GINTMSK_PTXFEMPMSK_POS (26U) +#define USBFS_GINTMSK_PTXFEMPMSK (0x04000000UL) +#define USBFS_GINTMSK_LPM_INTMSK_POS (27U) +#define USBFS_GINTMSK_LPM_INTMSK (0x08000000UL) +#define USBFS_GINTMSK_CONIDSTSCHNGMSK_POS (28U) +#define USBFS_GINTMSK_CONIDSTSCHNGMSK (0x10000000UL) +#define USBFS_GINTMSK_DISCONNINTMSK_POS (29U) +#define USBFS_GINTMSK_DISCONNINTMSK (0x20000000UL) +#define USBFS_GINTMSK_SESSREQINTMSK_POS (30U) +#define USBFS_GINTMSK_SESSREQINTMSK (0x40000000UL) +#define USBFS_GINTMSK_WKUPINTMSK_POS (31U) +#define USBFS_GINTMSK_WKUPINTMSK (0x80000000UL) + +/* Bit definition for USBFS_GRXSTSR register */ +#define USBFS_GRXSTSR_CHNUM_POS (0U) +#define USBFS_GRXSTSR_CHNUM (0x0000000FUL) +#define USBFS_GRXSTSR_BCNT_POS (4U) +#define USBFS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSR_DPID_POS (15U) +#define USBFS_GRXSTSR_DPID (0x00018000UL) +#define USBFS_GRXSTSR_DPID_0 (0x00008000UL) +#define USBFS_GRXSTSR_DPID_1 (0x00010000UL) +#define USBFS_GRXSTSR_PKTSTS_POS (17U) +#define USBFS_GRXSTSR_PKTSTS (0x001E0000UL) +#define USBFS_GRXSTSR_PKTSTS_0 (0x00020000UL) +#define USBFS_GRXSTSR_PKTSTS_1 (0x00040000UL) +#define USBFS_GRXSTSR_PKTSTS_2 (0x00080000UL) +#define USBFS_GRXSTSR_PKTSTS_3 (0x00100000UL) +#define USBFS_GRXSTSR_FN_POS (21U) +#define USBFS_GRXSTSR_FN (0x01E00000UL) + +/* Bit definition for USBFS_GRXSTSP register */ +#define USBFS_GRXSTSP_CHNUM_POS (0U) +#define USBFS_GRXSTSP_CHNUM (0x0000000FUL) +#define USBFS_GRXSTSP_BCNT_POS (4U) +#define USBFS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBFS_GRXSTSP_DPID_POS (15U) +#define USBFS_GRXSTSP_DPID (0x00018000UL) +#define USBFS_GRXSTSP_DPID_0 (0x00008000UL) +#define USBFS_GRXSTSP_DPID_1 (0x00010000UL) +#define USBFS_GRXSTSP_PKTSTS_POS (17U) +#define USBFS_GRXSTSP_PKTSTS (0x001E0000UL) +#define USBFS_GRXSTSP_PKTSTS_0 (0x00020000UL) +#define USBFS_GRXSTSP_PKTSTS_1 (0x00040000UL) +#define USBFS_GRXSTSP_PKTSTS_2 (0x00080000UL) +#define USBFS_GRXSTSP_PKTSTS_3 (0x00100000UL) +#define USBFS_GRXSTSP_FN_POS (21U) +#define USBFS_GRXSTSP_FN (0x01E00000UL) + +/* Bit definition for USBFS_GRXFSIZ register */ +#define USBFS_GRXFSIZ_RXFDEP (0x000003FFUL) + +/* Bit definition for USBFS_GNPTXFSIZ register */ +#define USBFS_GNPTXFSIZ_NPTXFSTADDR_POS (0U) +#define USBFS_GNPTXFSIZ_NPTXFSTADDR (0x000003FFUL) +#define USBFS_GNPTXFSIZ_NPTXFDEP_POS (16U) +#define USBFS_GNPTXFSIZ_NPTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_GNPTXSTS register */ +#define USBFS_GNPTXSTS_NPTXFSPCAVAIL_POS (0U) +#define USBFS_GNPTXSTS_NPTXFSPCAVAIL (0x0000FFFFUL) +#define USBFS_GNPTXSTS_NPTXQSPCAVAIL_POS (16U) +#define USBFS_GNPTXSTS_NPTXQSPCAVAIL (0x00FF0000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_POS (24U) +#define USBFS_GNPTXSTS_NPTXQTOP (0x7F000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_0 (0x01000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_1 (0x02000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_2 (0x04000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_3 (0x08000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_4 (0x10000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_5 (0x20000000UL) +#define USBFS_GNPTXSTS_NPTXQTOP_6 (0x40000000UL) + +/* Bit definition for USBFS_GUID register */ +#define USBFS_GUID (0xFFFFFFFFUL) + +/* Bit definition for USBFS_GLPMCFG register */ +#define USBFS_GLPMCFG_LPMCAP_POS (0U) +#define USBFS_GLPMCFG_LPMCAP (0x00000001UL) +#define USBFS_GLPMCFG_APPL1RES_POS (1U) +#define USBFS_GLPMCFG_APPL1RES (0x00000002UL) +#define USBFS_GLPMCFG_HIRD_POS (2U) +#define USBFS_GLPMCFG_HIRD (0x0000003CUL) +#define USBFS_GLPMCFG_HIRD_0 (0x00000004UL) +#define USBFS_GLPMCFG_HIRD_1 (0x00000008UL) +#define USBFS_GLPMCFG_HIRD_2 (0x00000010UL) +#define USBFS_GLPMCFG_HIRD_3 (0x00000020UL) +#define USBFS_GLPMCFG_BREMOTEWAKE_POS (6U) +#define USBFS_GLPMCFG_BREMOTEWAKE (0x00000040UL) +#define USBFS_GLPMCFG_ENBLSLPM_POS (7U) +#define USBFS_GLPMCFG_ENBLSLPM (0x00000080UL) +#define USBFS_GLPMCFG_HIRD_THRES_POS (8U) +#define USBFS_GLPMCFG_HIRD_THRES (0x00001F00UL) +#define USBFS_GLPMCFG_HIRD_THRES_0 (0x00000100UL) +#define USBFS_GLPMCFG_HIRD_THRES_1 (0x00000200UL) +#define USBFS_GLPMCFG_HIRD_THRES_2 (0x00000400UL) +#define USBFS_GLPMCFG_HIRD_THRES_3 (0x00000800UL) +#define USBFS_GLPMCFG_HIRD_THRES_4 (0x00001000UL) +#define USBFS_GLPMCFG_COREL1RES_POS (13U) +#define USBFS_GLPMCFG_COREL1RES (0x00006000UL) +#define USBFS_GLPMCFG_COREL1RES_0 (0x00002000UL) +#define USBFS_GLPMCFG_COREL1RES_1 (0x00004000UL) +#define USBFS_GLPMCFG_SLPSTS_POS (15U) +#define USBFS_GLPMCFG_SLPSTS (0x00008000UL) +#define USBFS_GLPMCFG_L1RESUMEOK_POS (16U) +#define USBFS_GLPMCFG_L1RESUMEOK (0x00010000UL) +#define USBFS_GLPMCFG_LPM_CHNL_INDX_POS (17U) +#define USBFS_GLPMCFG_LPM_CHNL_INDX (0x001E0000UL) +#define USBFS_GLPMCFG_LPM_RETRY_CNT_POS (21U) +#define USBFS_GLPMCFG_LPM_RETRY_CNT (0x00E00000UL) +#define USBFS_GLPMCFG_SNDLPM_POS (24U) +#define USBFS_GLPMCFG_SNDLPM (0x01000000UL) +#define USBFS_GLPMCFG_LPM_RETRYCNT_STS_POS (25U) +#define USBFS_GLPMCFG_LPM_RETRYCNT_STS (0x0E000000UL) +#define USBFS_GLPMCFG_LPM_ENBESL_POS (28U) +#define USBFS_GLPMCFG_LPM_ENBESL (0x10000000UL) +#define USBFS_GLPMCFG_LPM_RESTORESLPSTS_POS (29U) +#define USBFS_GLPMCFG_LPM_RESTORESLPSTS (0x20000000UL) + +/* Bit definition for USBFS_GDFIFOCFG register */ +#define USBFS_GDFIFOCFG_GDFIFOCFG_POS (0U) +#define USBFS_GDFIFOCFG_GDFIFOCFG (0x0000FFFFUL) +#define USBFS_GDFIFOCFG_EPINFOBASEADDR_POS (16U) +#define USBFS_GDFIFOCFG_EPINFOBASEADDR (0xFFFF0000UL) + +/* Bit definition for USBFS_HPTXFSIZ register */ +#define USBFS_HPTXFSIZ_PTXFSTADDR_POS (0U) +#define USBFS_HPTXFSIZ_PTXFSTADDR (0x000007FFUL) +#define USBFS_HPTXFSIZ_PTXFSIZE_POS (16U) +#define USBFS_HPTXFSIZ_PTXFSIZE (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF1 register */ +#define USBFS_DIEPTXF1_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF1_INEPNTXFSTADDR (0x000007FFUL) +#define USBFS_DIEPTXF1_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF1_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF2 register */ +#define USBFS_DIEPTXF2_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF2_INEPNTXFSTADDR (0x000007FFUL) +#define USBFS_DIEPTXF2_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF2_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF3 register */ +#define USBFS_DIEPTXF3_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF3_INEPNTXFSTADDR (0x00000FFFUL) +#define USBFS_DIEPTXF3_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF3_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF4 register */ +#define USBFS_DIEPTXF4_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF4_INEPNTXFSTADDR (0x00000FFFUL) +#define USBFS_DIEPTXF4_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF4_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF5 register */ +#define USBFS_DIEPTXF5_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF5_INEPNTXFSTADDR (0x00000FFFUL) +#define USBFS_DIEPTXF5_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF5_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF6 register */ +#define USBFS_DIEPTXF6_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF6_INEPNTXFSTADDR (0x00001FFFUL) +#define USBFS_DIEPTXF6_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF6_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF7 register */ +#define USBFS_DIEPTXF7_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF7_INEPNTXFSTADDR (0x00001FFFUL) +#define USBFS_DIEPTXF7_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF7_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF8 register */ +#define USBFS_DIEPTXF8_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF8_INEPNTXFSTADDR (0x00001FFFUL) +#define USBFS_DIEPTXF8_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF8_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF9 register */ +#define USBFS_DIEPTXF9_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF9_INEPNTXFSTADDR (0x00001FFFUL) +#define USBFS_DIEPTXF9_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF9_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF10 register */ +#define USBFS_DIEPTXF10_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF10_INEPNTXFSTADDR (0x00001FFFUL) +#define USBFS_DIEPTXF10_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF10_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF11 register */ +#define USBFS_DIEPTXF11_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF11_INEPNTXFSTADDR (0x00001FFFUL) +#define USBFS_DIEPTXF11_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF11_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF12 register */ +#define USBFS_DIEPTXF12_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF12_INEPNTXFSTADDR (0x00003FFFUL) +#define USBFS_DIEPTXF12_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF12_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF13 register */ +#define USBFS_DIEPTXF13_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF13_INEPNTXFSTADDR (0x00003FFFUL) +#define USBFS_DIEPTXF13_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF13_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF14 register */ +#define USBFS_DIEPTXF14_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF14_INEPNTXFSTADDR (0x00003FFFUL) +#define USBFS_DIEPTXF14_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF14_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_DIEPTXF15 register */ +#define USBFS_DIEPTXF15_INEPNTXFSTADDR_POS (0U) +#define USBFS_DIEPTXF15_INEPNTXFSTADDR (0x00003FFFUL) +#define USBFS_DIEPTXF15_INEPNTXFDEP_POS (16U) +#define USBFS_DIEPTXF15_INEPNTXFDEP (0x03FF0000UL) + +/* Bit definition for USBFS_HCFG register */ +#define USBFS_HCFG_FSLSPCLKSEL_POS (0U) +#define USBFS_HCFG_FSLSPCLKSEL (0x00000003UL) +#define USBFS_HCFG_FSLSPCLKSEL_0 (0x00000001UL) +#define USBFS_HCFG_FSLSPCLKSEL_1 (0x00000002UL) +#define USBFS_HCFG_FSLSSUPP_POS (2U) +#define USBFS_HCFG_FSLSSUPP (0x00000004UL) +#define USBFS_HCFG_ENA32KHZS_POS (7U) +#define USBFS_HCFG_ENA32KHZS (0x00000080UL) +#define USBFS_HCFG_RESVALID_POS (8U) +#define USBFS_HCFG_RESVALID (0x0000FF00UL) +#define USBFS_HCFG_MODECHTIMEN_POS (31U) +#define USBFS_HCFG_MODECHTIMEN (0x80000000UL) + +/* Bit definition for USBFS_HFIR register */ +#define USBFS_HFIR_FRINT_POS (0U) +#define USBFS_HFIR_FRINT (0x0000FFFFUL) +#define USBFS_HFIR_HFIRRLDCTRL_POS (16U) +#define USBFS_HFIR_HFIRRLDCTRL (0x00010000UL) + +/* Bit definition for USBFS_HFNUM register */ +#define USBFS_HFNUM_FRNUM_POS (0U) +#define USBFS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBFS_HFNUM_FRREM_POS (16U) +#define USBFS_HFNUM_FRREM (0xFFFF0000UL) + +/* Bit definition for USBFS_HPTXSTS register */ +#define USBFS_HPTXSTS_PTXFSPCAVAIL_POS (0U) +#define USBFS_HPTXSTS_PTXFSPCAVAIL (0x0000FFFFUL) +#define USBFS_HPTXSTS_PTXQSPCAVAIL_POS (16U) +#define USBFS_HPTXSTS_PTXQSPCAVAIL (0x00FF0000UL) +#define USBFS_HPTXSTS_PTXQTOP_POS (24U) +#define USBFS_HPTXSTS_PTXQTOP (0xFF000000UL) +#define USBFS_HPTXSTS_PTXQTOP_0 (0x01000000UL) +#define USBFS_HPTXSTS_PTXQTOP_1 (0x02000000UL) +#define USBFS_HPTXSTS_PTXQTOP_2 (0x04000000UL) +#define USBFS_HPTXSTS_PTXQTOP_3 (0x08000000UL) +#define USBFS_HPTXSTS_PTXQTOP_4 (0x10000000UL) +#define USBFS_HPTXSTS_PTXQTOP_5 (0x20000000UL) +#define USBFS_HPTXSTS_PTXQTOP_6 (0x40000000UL) +#define USBFS_HPTXSTS_PTXQTOP_7 (0x80000000UL) + +/* Bit definition for USBFS_HAINT register */ +#define USBFS_HAINT_HAINT (0x0000FFFFUL) + +/* Bit definition for USBFS_HAINTMSK register */ +#define USBFS_HAINTMSK_HAINTMSK (0x0000FFFFUL) + +/* Bit definition for USBFS_HPRT register */ +#define USBFS_HPRT_PRTCONNSTS_POS (0U) +#define USBFS_HPRT_PRTCONNSTS (0x00000001UL) +#define USBFS_HPRT_PRTCONNDET_POS (1U) +#define USBFS_HPRT_PRTCONNDET (0x00000002UL) +#define USBFS_HPRT_PRTENA_POS (2U) +#define USBFS_HPRT_PRTENA (0x00000004UL) +#define USBFS_HPRT_PRTENCHNG_POS (3U) +#define USBFS_HPRT_PRTENCHNG (0x00000008UL) +#define USBFS_HPRT_PRTOVRCURRACT_POS (4U) +#define USBFS_HPRT_PRTOVRCURRACT (0x00000010UL) +#define USBFS_HPRT_PRTOVRCURRCHNG_POS (5U) +#define USBFS_HPRT_PRTOVRCURRCHNG (0x00000020UL) +#define USBFS_HPRT_PRTRES_POS (6U) +#define USBFS_HPRT_PRTRES (0x00000040UL) +#define USBFS_HPRT_PRTSUSP_POS (7U) +#define USBFS_HPRT_PRTSUSP (0x00000080UL) +#define USBFS_HPRT_PRTRST_POS (8U) +#define USBFS_HPRT_PRTRST (0x00000100UL) +#define USBFS_HPRT_PRTLNSTS_POS (10U) +#define USBFS_HPRT_PRTLNSTS (0x00000C00UL) +#define USBFS_HPRT_PRTLNSTS_0 (0x00000400UL) +#define USBFS_HPRT_PRTLNSTS_1 (0x00000800UL) +#define USBFS_HPRT_PRTPWR_POS (12U) +#define USBFS_HPRT_PRTPWR (0x00001000UL) +#define USBFS_HPRT_PRTTSTCTL_POS (13U) +#define USBFS_HPRT_PRTTSTCTL (0x0001E000UL) +#define USBFS_HPRT_PRTTSTCTL_0 (0x00002000UL) +#define USBFS_HPRT_PRTTSTCTL_1 (0x00004000UL) +#define USBFS_HPRT_PRTTSTCTL_2 (0x00008000UL) +#define USBFS_HPRT_PRTTSTCTL_3 (0x00010000UL) +#define USBFS_HPRT_PRTSPD_POS (17U) +#define USBFS_HPRT_PRTSPD (0x00060000UL) +#define USBFS_HPRT_PRTSPD_0 (0x00020000UL) +#define USBFS_HPRT_PRTSPD_1 (0x00040000UL) + +/* Bit definition for USBFS_HCCHAR0 register */ +#define USBFS_HCCHAR0_MPS_POS (0U) +#define USBFS_HCCHAR0_MPS (0x000007FFUL) +#define USBFS_HCCHAR0_EPNUM_POS (11U) +#define USBFS_HCCHAR0_EPNUM (0x00007800UL) +#define USBFS_HCCHAR0_EPDIR_POS (15U) +#define USBFS_HCCHAR0_EPDIR (0x00008000UL) +#define USBFS_HCCHAR0_LSPDDEV_POS (17U) +#define USBFS_HCCHAR0_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR0_EPTYPE_POS (18U) +#define USBFS_HCCHAR0_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR0_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR0_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR0_EC_POS (20U) +#define USBFS_HCCHAR0_EC (0x00300000UL) +#define USBFS_HCCHAR0_EC_0 (0x00100000UL) +#define USBFS_HCCHAR0_EC_1 (0x00200000UL) +#define USBFS_HCCHAR0_DEVADDR_POS (22U) +#define USBFS_HCCHAR0_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR0_ODDFRM_POS (29U) +#define USBFS_HCCHAR0_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR0_CHDIS_POS (30U) +#define USBFS_HCCHAR0_CHDIS (0x40000000UL) +#define USBFS_HCCHAR0_CHENA_POS (31U) +#define USBFS_HCCHAR0_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT0 register */ +#define USBFS_HCSPLT0_PRTADDR_POS (0U) +#define USBFS_HCSPLT0_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT0_HUBADDR_POS (7U) +#define USBFS_HCSPLT0_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT0_XACTPOS_POS (14U) +#define USBFS_HCSPLT0_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT0_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT0_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT0_COMPSPLT_POS (16U) +#define USBFS_HCSPLT0_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT0_SPLTENA_POS (31U) +#define USBFS_HCSPLT0_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT0 register */ +#define USBFS_HCINT0_XFERCOMPL_POS (0U) +#define USBFS_HCINT0_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT0_CHHLTD_POS (1U) +#define USBFS_HCINT0_CHHLTD (0x00000002UL) +#define USBFS_HCINT0_AHBERR_POS (2U) +#define USBFS_HCINT0_AHBERR (0x00000004UL) +#define USBFS_HCINT0_STALL_POS (3U) +#define USBFS_HCINT0_STALL (0x00000008UL) +#define USBFS_HCINT0_NAK_POS (4U) +#define USBFS_HCINT0_NAK (0x00000010UL) +#define USBFS_HCINT0_ACK_POS (5U) +#define USBFS_HCINT0_ACK (0x00000020UL) +#define USBFS_HCINT0_NYET_POS (6U) +#define USBFS_HCINT0_NYET (0x00000040UL) +#define USBFS_HCINT0_XACTERR_POS (7U) +#define USBFS_HCINT0_XACTERR (0x00000080UL) +#define USBFS_HCINT0_BBLERR_POS (8U) +#define USBFS_HCINT0_BBLERR (0x00000100UL) +#define USBFS_HCINT0_FRMOVRUN_POS (9U) +#define USBFS_HCINT0_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT0_DATATGLERR_POS (10U) +#define USBFS_HCINT0_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK0 register */ +#define USBFS_HCINTMSK0_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK0_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK0_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK0_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK0_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK0_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK0_STALLMSK_POS (3U) +#define USBFS_HCINTMSK0_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK0_NAKMSK_POS (4U) +#define USBFS_HCINTMSK0_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK0_ACKMSK_POS (5U) +#define USBFS_HCINTMSK0_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK0_NYETMSK_POS (6U) +#define USBFS_HCINTMSK0_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK0_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK0_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK0_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK0_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK0_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK0_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK0_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK0_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ0 register */ +#define USBFS_HCTSIZ0_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ0_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ0_PKTCNT_POS (19U) +#define USBFS_HCTSIZ0_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ0_PID_POS (29U) +#define USBFS_HCTSIZ0_PID (0x60000000UL) +#define USBFS_HCTSIZ0_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ0_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ0_DOPNG_POS (31U) +#define USBFS_HCTSIZ0_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA0 register */ +#define USBFS_HCDMA0 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR1 register */ +#define USBFS_HCCHAR1_MPS_POS (0U) +#define USBFS_HCCHAR1_MPS (0x000007FFUL) +#define USBFS_HCCHAR1_EPNUM_POS (11U) +#define USBFS_HCCHAR1_EPNUM (0x00007800UL) +#define USBFS_HCCHAR1_EPDIR_POS (15U) +#define USBFS_HCCHAR1_EPDIR (0x00008000UL) +#define USBFS_HCCHAR1_LSPDDEV_POS (17U) +#define USBFS_HCCHAR1_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR1_EPTYPE_POS (18U) +#define USBFS_HCCHAR1_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR1_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR1_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR1_EC_POS (20U) +#define USBFS_HCCHAR1_EC (0x00300000UL) +#define USBFS_HCCHAR1_DEVADDR_POS (22U) +#define USBFS_HCCHAR1_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR1_ODDFRM_POS (29U) +#define USBFS_HCCHAR1_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR1_CHDIS_POS (30U) +#define USBFS_HCCHAR1_CHDIS (0x40000000UL) +#define USBFS_HCCHAR1_CHENA_POS (31U) +#define USBFS_HCCHAR1_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT1 register */ +#define USBFS_HCSPLT1_PRTADDR_POS (0U) +#define USBFS_HCSPLT1_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT1_HUBADDR_POS (7U) +#define USBFS_HCSPLT1_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT1_XACTPOS_POS (14U) +#define USBFS_HCSPLT1_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT1_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT1_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT1_COMPSPLT_POS (16U) +#define USBFS_HCSPLT1_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT1_SPLTENA_POS (31U) +#define USBFS_HCSPLT1_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT1 register */ +#define USBFS_HCINT1_XFERCOMPL_POS (0U) +#define USBFS_HCINT1_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT1_CHHLTD_POS (1U) +#define USBFS_HCINT1_CHHLTD (0x00000002UL) +#define USBFS_HCINT1_AHBERR_POS (2U) +#define USBFS_HCINT1_AHBERR (0x00000004UL) +#define USBFS_HCINT1_STALL_POS (3U) +#define USBFS_HCINT1_STALL (0x00000008UL) +#define USBFS_HCINT1_NAK_POS (4U) +#define USBFS_HCINT1_NAK (0x00000010UL) +#define USBFS_HCINT1_ACK_POS (5U) +#define USBFS_HCINT1_ACK (0x00000020UL) +#define USBFS_HCINT1_NYET_POS (6U) +#define USBFS_HCINT1_NYET (0x00000040UL) +#define USBFS_HCINT1_XACTERR_POS (7U) +#define USBFS_HCINT1_XACTERR (0x00000080UL) +#define USBFS_HCINT1_BBLERR_POS (8U) +#define USBFS_HCINT1_BBLERR (0x00000100UL) +#define USBFS_HCINT1_FRMOVRUN_POS (9U) +#define USBFS_HCINT1_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT1_DATATGLERR_POS (10U) +#define USBFS_HCINT1_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK1 register */ +#define USBFS_HCINTMSK1_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK1_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK1_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK1_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK1_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK1_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK1_STALLMSK_POS (3U) +#define USBFS_HCINTMSK1_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK1_NAKMSK_POS (4U) +#define USBFS_HCINTMSK1_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK1_ACKMSK_POS (5U) +#define USBFS_HCINTMSK1_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK1_NYETMSK_POS (6U) +#define USBFS_HCINTMSK1_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK1_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK1_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK1_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK1_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK1_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK1_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK1_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK1_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ1 register */ +#define USBFS_HCTSIZ1_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ1_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ1_PKTCNT_POS (19U) +#define USBFS_HCTSIZ1_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ1_PID_POS (29U) +#define USBFS_HCTSIZ1_PID (0x60000000UL) +#define USBFS_HCTSIZ1_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ1_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ1_DOPNG_POS (31U) +#define USBFS_HCTSIZ1_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA1 register */ +#define USBFS_HCDMA1 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR2 register */ +#define USBFS_HCCHAR2_MPS_POS (0U) +#define USBFS_HCCHAR2_MPS (0x000007FFUL) +#define USBFS_HCCHAR2_EPNUM_POS (11U) +#define USBFS_HCCHAR2_EPNUM (0x00007800UL) +#define USBFS_HCCHAR2_EPDIR_POS (15U) +#define USBFS_HCCHAR2_EPDIR (0x00008000UL) +#define USBFS_HCCHAR2_LSPDDEV_POS (17U) +#define USBFS_HCCHAR2_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR2_EPTYPE_POS (18U) +#define USBFS_HCCHAR2_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR2_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR2_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR2_EC_POS (20U) +#define USBFS_HCCHAR2_EC (0x00300000UL) +#define USBFS_HCCHAR2_DEVADDR_POS (22U) +#define USBFS_HCCHAR2_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR2_ODDFRM_POS (29U) +#define USBFS_HCCHAR2_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR2_CHDIS_POS (30U) +#define USBFS_HCCHAR2_CHDIS (0x40000000UL) +#define USBFS_HCCHAR2_CHENA_POS (31U) +#define USBFS_HCCHAR2_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT2 register */ +#define USBFS_HCSPLT2_PRTADDR_POS (0U) +#define USBFS_HCSPLT2_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT2_HUBADDR_POS (7U) +#define USBFS_HCSPLT2_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT2_XACTPOS_POS (14U) +#define USBFS_HCSPLT2_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT2_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT2_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT2_COMPSPLT_POS (16U) +#define USBFS_HCSPLT2_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT2_SPLTENA_POS (31U) +#define USBFS_HCSPLT2_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT2 register */ +#define USBFS_HCINT2_XFERCOMPL_POS (0U) +#define USBFS_HCINT2_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT2_CHHLTD_POS (1U) +#define USBFS_HCINT2_CHHLTD (0x00000002UL) +#define USBFS_HCINT2_AHBERR_POS (2U) +#define USBFS_HCINT2_AHBERR (0x00000004UL) +#define USBFS_HCINT2_STALL_POS (3U) +#define USBFS_HCINT2_STALL (0x00000008UL) +#define USBFS_HCINT2_NAK_POS (4U) +#define USBFS_HCINT2_NAK (0x00000010UL) +#define USBFS_HCINT2_ACK_POS (5U) +#define USBFS_HCINT2_ACK (0x00000020UL) +#define USBFS_HCINT2_NYET_POS (6U) +#define USBFS_HCINT2_NYET (0x00000040UL) +#define USBFS_HCINT2_XACTERR_POS (7U) +#define USBFS_HCINT2_XACTERR (0x00000080UL) +#define USBFS_HCINT2_BBLERR_POS (8U) +#define USBFS_HCINT2_BBLERR (0x00000100UL) +#define USBFS_HCINT2_FRMOVRUN_POS (9U) +#define USBFS_HCINT2_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT2_DATATGLERR_POS (10U) +#define USBFS_HCINT2_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK2 register */ +#define USBFS_HCINTMSK2_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK2_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK2_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK2_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK2_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK2_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK2_STALLMSK_POS (3U) +#define USBFS_HCINTMSK2_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK2_NAKMSK_POS (4U) +#define USBFS_HCINTMSK2_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK2_ACKMSK_POS (5U) +#define USBFS_HCINTMSK2_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK2_NYETMSK_POS (6U) +#define USBFS_HCINTMSK2_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK2_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK2_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK2_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK2_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK2_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK2_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK2_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK2_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ2 register */ +#define USBFS_HCTSIZ2_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ2_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ2_PKTCNT_POS (19U) +#define USBFS_HCTSIZ2_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ2_PID_POS (29U) +#define USBFS_HCTSIZ2_PID (0x60000000UL) +#define USBFS_HCTSIZ2_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ2_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ2_DOPNG_POS (31U) +#define USBFS_HCTSIZ2_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA2 register */ +#define USBFS_HCDMA2 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR3 register */ +#define USBFS_HCCHAR3_MPS_POS (0U) +#define USBFS_HCCHAR3_MPS (0x000007FFUL) +#define USBFS_HCCHAR3_EPNUM_POS (11U) +#define USBFS_HCCHAR3_EPNUM (0x00007800UL) +#define USBFS_HCCHAR3_EPDIR_POS (15U) +#define USBFS_HCCHAR3_EPDIR (0x00008000UL) +#define USBFS_HCCHAR3_LSPDDEV_POS (17U) +#define USBFS_HCCHAR3_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR3_EPTYPE_POS (18U) +#define USBFS_HCCHAR3_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR3_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR3_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR3_EC_POS (20U) +#define USBFS_HCCHAR3_EC (0x00300000UL) +#define USBFS_HCCHAR3_DEVADDR_POS (22U) +#define USBFS_HCCHAR3_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR3_ODDFRM_POS (29U) +#define USBFS_HCCHAR3_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR3_CHDIS_POS (30U) +#define USBFS_HCCHAR3_CHDIS (0x40000000UL) +#define USBFS_HCCHAR3_CHENA_POS (31U) +#define USBFS_HCCHAR3_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT3 register */ +#define USBFS_HCSPLT3_PRTADDR_POS (0U) +#define USBFS_HCSPLT3_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT3_HUBADDR_POS (7U) +#define USBFS_HCSPLT3_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT3_XACTPOS_POS (14U) +#define USBFS_HCSPLT3_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT3_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT3_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT3_COMPSPLT_POS (16U) +#define USBFS_HCSPLT3_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT3_SPLTENA_POS (31U) +#define USBFS_HCSPLT3_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT3 register */ +#define USBFS_HCINT3_XFERCOMPL_POS (0U) +#define USBFS_HCINT3_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT3_CHHLTD_POS (1U) +#define USBFS_HCINT3_CHHLTD (0x00000002UL) +#define USBFS_HCINT3_AHBERR_POS (2U) +#define USBFS_HCINT3_AHBERR (0x00000004UL) +#define USBFS_HCINT3_STALL_POS (3U) +#define USBFS_HCINT3_STALL (0x00000008UL) +#define USBFS_HCINT3_NAK_POS (4U) +#define USBFS_HCINT3_NAK (0x00000010UL) +#define USBFS_HCINT3_ACK_POS (5U) +#define USBFS_HCINT3_ACK (0x00000020UL) +#define USBFS_HCINT3_NYET_POS (6U) +#define USBFS_HCINT3_NYET (0x00000040UL) +#define USBFS_HCINT3_XACTERR_POS (7U) +#define USBFS_HCINT3_XACTERR (0x00000080UL) +#define USBFS_HCINT3_BBLERR_POS (8U) +#define USBFS_HCINT3_BBLERR (0x00000100UL) +#define USBFS_HCINT3_FRMOVRUN_POS (9U) +#define USBFS_HCINT3_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT3_DATATGLERR_POS (10U) +#define USBFS_HCINT3_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK3 register */ +#define USBFS_HCINTMSK3_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK3_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK3_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK3_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK3_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK3_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK3_STALLMSK_POS (3U) +#define USBFS_HCINTMSK3_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK3_NAKMSK_POS (4U) +#define USBFS_HCINTMSK3_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK3_ACKMSK_POS (5U) +#define USBFS_HCINTMSK3_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK3_NYETMSK_POS (6U) +#define USBFS_HCINTMSK3_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK3_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK3_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK3_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK3_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK3_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK3_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK3_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK3_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ3 register */ +#define USBFS_HCTSIZ3_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ3_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ3_PKTCNT_POS (19U) +#define USBFS_HCTSIZ3_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ3_PID_POS (29U) +#define USBFS_HCTSIZ3_PID (0x60000000UL) +#define USBFS_HCTSIZ3_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ3_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ3_DOPNG_POS (31U) +#define USBFS_HCTSIZ3_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA3 register */ +#define USBFS_HCDMA3 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR4 register */ +#define USBFS_HCCHAR4_MPS_POS (0U) +#define USBFS_HCCHAR4_MPS (0x000007FFUL) +#define USBFS_HCCHAR4_EPNUM_POS (11U) +#define USBFS_HCCHAR4_EPNUM (0x00007800UL) +#define USBFS_HCCHAR4_EPDIR_POS (15U) +#define USBFS_HCCHAR4_EPDIR (0x00008000UL) +#define USBFS_HCCHAR4_LSPDDEV_POS (17U) +#define USBFS_HCCHAR4_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR4_EPTYPE_POS (18U) +#define USBFS_HCCHAR4_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR4_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR4_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR4_EC_POS (20U) +#define USBFS_HCCHAR4_EC (0x00300000UL) +#define USBFS_HCCHAR4_DEVADDR_POS (22U) +#define USBFS_HCCHAR4_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR4_ODDFRM_POS (29U) +#define USBFS_HCCHAR4_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR4_CHDIS_POS (30U) +#define USBFS_HCCHAR4_CHDIS (0x40000000UL) +#define USBFS_HCCHAR4_CHENA_POS (31U) +#define USBFS_HCCHAR4_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT4 register */ +#define USBFS_HCSPLT4_PRTADDR_POS (0U) +#define USBFS_HCSPLT4_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT4_HUBADDR_POS (7U) +#define USBFS_HCSPLT4_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT4_XACTPOS_POS (14U) +#define USBFS_HCSPLT4_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT4_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT4_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT4_COMPSPLT_POS (16U) +#define USBFS_HCSPLT4_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT4_SPLTENA_POS (31U) +#define USBFS_HCSPLT4_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT4 register */ +#define USBFS_HCINT4_XFERCOMPL_POS (0U) +#define USBFS_HCINT4_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT4_CHHLTD_POS (1U) +#define USBFS_HCINT4_CHHLTD (0x00000002UL) +#define USBFS_HCINT4_AHBERR_POS (2U) +#define USBFS_HCINT4_AHBERR (0x00000004UL) +#define USBFS_HCINT4_STALL_POS (3U) +#define USBFS_HCINT4_STALL (0x00000008UL) +#define USBFS_HCINT4_NAK_POS (4U) +#define USBFS_HCINT4_NAK (0x00000010UL) +#define USBFS_HCINT4_ACK_POS (5U) +#define USBFS_HCINT4_ACK (0x00000020UL) +#define USBFS_HCINT4_NYET_POS (6U) +#define USBFS_HCINT4_NYET (0x00000040UL) +#define USBFS_HCINT4_XACTERR_POS (7U) +#define USBFS_HCINT4_XACTERR (0x00000080UL) +#define USBFS_HCINT4_BBLERR_POS (8U) +#define USBFS_HCINT4_BBLERR (0x00000100UL) +#define USBFS_HCINT4_FRMOVRUN_POS (9U) +#define USBFS_HCINT4_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT4_DATATGLERR_POS (10U) +#define USBFS_HCINT4_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK4 register */ +#define USBFS_HCINTMSK4_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK4_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK4_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK4_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK4_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK4_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK4_STALLMSK_POS (3U) +#define USBFS_HCINTMSK4_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK4_NAKMSK_POS (4U) +#define USBFS_HCINTMSK4_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK4_ACKMSK_POS (5U) +#define USBFS_HCINTMSK4_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK4_NYETMSK_POS (6U) +#define USBFS_HCINTMSK4_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK4_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK4_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK4_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK4_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK4_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK4_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK4_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK4_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ4 register */ +#define USBFS_HCTSIZ4_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ4_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ4_PKTCNT_POS (19U) +#define USBFS_HCTSIZ4_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ4_PID_POS (29U) +#define USBFS_HCTSIZ4_PID (0x60000000UL) +#define USBFS_HCTSIZ4_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ4_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ4_DOPNG_POS (31U) +#define USBFS_HCTSIZ4_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA4 register */ +#define USBFS_HCDMA4 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR5 register */ +#define USBFS_HCCHAR5_MPS_POS (0U) +#define USBFS_HCCHAR5_MPS (0x000007FFUL) +#define USBFS_HCCHAR5_EPNUM_POS (11U) +#define USBFS_HCCHAR5_EPNUM (0x00007800UL) +#define USBFS_HCCHAR5_EPDIR_POS (15U) +#define USBFS_HCCHAR5_EPDIR (0x00008000UL) +#define USBFS_HCCHAR5_LSPDDEV_POS (17U) +#define USBFS_HCCHAR5_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR5_EPTYPE_POS (18U) +#define USBFS_HCCHAR5_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR5_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR5_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR5_EC_POS (20U) +#define USBFS_HCCHAR5_EC (0x00300000UL) +#define USBFS_HCCHAR5_DEVADDR_POS (22U) +#define USBFS_HCCHAR5_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR5_ODDFRM_POS (29U) +#define USBFS_HCCHAR5_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR5_CHDIS_POS (30U) +#define USBFS_HCCHAR5_CHDIS (0x40000000UL) +#define USBFS_HCCHAR5_CHENA_POS (31U) +#define USBFS_HCCHAR5_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT5 register */ +#define USBFS_HCSPLT5_PRTADDR_POS (0U) +#define USBFS_HCSPLT5_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT5_HUBADDR_POS (7U) +#define USBFS_HCSPLT5_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT5_XACTPOS_POS (14U) +#define USBFS_HCSPLT5_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT5_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT5_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT5_COMPSPLT_POS (16U) +#define USBFS_HCSPLT5_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT5_SPLTENA_POS (31U) +#define USBFS_HCSPLT5_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT5 register */ +#define USBFS_HCINT5_XFERCOMPL_POS (0U) +#define USBFS_HCINT5_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT5_CHHLTD_POS (1U) +#define USBFS_HCINT5_CHHLTD (0x00000002UL) +#define USBFS_HCINT5_AHBERR_POS (2U) +#define USBFS_HCINT5_AHBERR (0x00000004UL) +#define USBFS_HCINT5_STALL_POS (3U) +#define USBFS_HCINT5_STALL (0x00000008UL) +#define USBFS_HCINT5_NAK_POS (4U) +#define USBFS_HCINT5_NAK (0x00000010UL) +#define USBFS_HCINT5_ACK_POS (5U) +#define USBFS_HCINT5_ACK (0x00000020UL) +#define USBFS_HCINT5_NYET_POS (6U) +#define USBFS_HCINT5_NYET (0x00000040UL) +#define USBFS_HCINT5_XACTERR_POS (7U) +#define USBFS_HCINT5_XACTERR (0x00000080UL) +#define USBFS_HCINT5_BBLERR_POS (8U) +#define USBFS_HCINT5_BBLERR (0x00000100UL) +#define USBFS_HCINT5_FRMOVRUN_POS (9U) +#define USBFS_HCINT5_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT5_DATATGLERR_POS (10U) +#define USBFS_HCINT5_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK5 register */ +#define USBFS_HCINTMSK5_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK5_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK5_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK5_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK5_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK5_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK5_STALLMSK_POS (3U) +#define USBFS_HCINTMSK5_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK5_NAKMSK_POS (4U) +#define USBFS_HCINTMSK5_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK5_ACKMSK_POS (5U) +#define USBFS_HCINTMSK5_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK5_NYETMSK_POS (6U) +#define USBFS_HCINTMSK5_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK5_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK5_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK5_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK5_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK5_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK5_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK5_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK5_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ5 register */ +#define USBFS_HCTSIZ5_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ5_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ5_PKTCNT_POS (19U) +#define USBFS_HCTSIZ5_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ5_PID_POS (29U) +#define USBFS_HCTSIZ5_PID (0x60000000UL) +#define USBFS_HCTSIZ5_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ5_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ5_DOPNG_POS (31U) +#define USBFS_HCTSIZ5_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA5 register */ +#define USBFS_HCDMA5 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR6 register */ +#define USBFS_HCCHAR6_MPS_POS (0U) +#define USBFS_HCCHAR6_MPS (0x000007FFUL) +#define USBFS_HCCHAR6_EPNUM_POS (11U) +#define USBFS_HCCHAR6_EPNUM (0x00007800UL) +#define USBFS_HCCHAR6_EPDIR_POS (15U) +#define USBFS_HCCHAR6_EPDIR (0x00008000UL) +#define USBFS_HCCHAR6_LSPDDEV_POS (17U) +#define USBFS_HCCHAR6_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR6_EPTYPE_POS (18U) +#define USBFS_HCCHAR6_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR6_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR6_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR6_EC_POS (20U) +#define USBFS_HCCHAR6_EC (0x00300000UL) +#define USBFS_HCCHAR6_DEVADDR_POS (22U) +#define USBFS_HCCHAR6_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR6_ODDFRM_POS (29U) +#define USBFS_HCCHAR6_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR6_CHDIS_POS (30U) +#define USBFS_HCCHAR6_CHDIS (0x40000000UL) +#define USBFS_HCCHAR6_CHENA_POS (31U) +#define USBFS_HCCHAR6_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT6 register */ +#define USBFS_HCSPLT6_PRTADDR_POS (0U) +#define USBFS_HCSPLT6_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT6_HUBADDR_POS (7U) +#define USBFS_HCSPLT6_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT6_XACTPOS_POS (14U) +#define USBFS_HCSPLT6_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT6_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT6_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT6_COMPSPLT_POS (16U) +#define USBFS_HCSPLT6_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT6_SPLTENA_POS (31U) +#define USBFS_HCSPLT6_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT6 register */ +#define USBFS_HCINT6_XFERCOMPL_POS (0U) +#define USBFS_HCINT6_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT6_CHHLTD_POS (1U) +#define USBFS_HCINT6_CHHLTD (0x00000002UL) +#define USBFS_HCINT6_AHBERR_POS (2U) +#define USBFS_HCINT6_AHBERR (0x00000004UL) +#define USBFS_HCINT6_STALL_POS (3U) +#define USBFS_HCINT6_STALL (0x00000008UL) +#define USBFS_HCINT6_NAK_POS (4U) +#define USBFS_HCINT6_NAK (0x00000010UL) +#define USBFS_HCINT6_ACK_POS (5U) +#define USBFS_HCINT6_ACK (0x00000020UL) +#define USBFS_HCINT6_NYET_POS (6U) +#define USBFS_HCINT6_NYET (0x00000040UL) +#define USBFS_HCINT6_XACTERR_POS (7U) +#define USBFS_HCINT6_XACTERR (0x00000080UL) +#define USBFS_HCINT6_BBLERR_POS (8U) +#define USBFS_HCINT6_BBLERR (0x00000100UL) +#define USBFS_HCINT6_FRMOVRUN_POS (9U) +#define USBFS_HCINT6_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT6_DATATGLERR_POS (10U) +#define USBFS_HCINT6_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK6 register */ +#define USBFS_HCINTMSK6_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK6_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK6_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK6_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK6_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK6_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK6_STALLMSK_POS (3U) +#define USBFS_HCINTMSK6_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK6_NAKMSK_POS (4U) +#define USBFS_HCINTMSK6_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK6_ACKMSK_POS (5U) +#define USBFS_HCINTMSK6_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK6_NYETMSK_POS (6U) +#define USBFS_HCINTMSK6_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK6_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK6_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK6_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK6_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK6_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK6_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK6_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK6_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ6 register */ +#define USBFS_HCTSIZ6_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ6_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ6_PKTCNT_POS (19U) +#define USBFS_HCTSIZ6_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ6_PID_POS (29U) +#define USBFS_HCTSIZ6_PID (0x60000000UL) +#define USBFS_HCTSIZ6_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ6_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ6_DOPNG_POS (31U) +#define USBFS_HCTSIZ6_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA6 register */ +#define USBFS_HCDMA6 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR7 register */ +#define USBFS_HCCHAR7_MPS_POS (0U) +#define USBFS_HCCHAR7_MPS (0x000007FFUL) +#define USBFS_HCCHAR7_EPNUM_POS (11U) +#define USBFS_HCCHAR7_EPNUM (0x00007800UL) +#define USBFS_HCCHAR7_EPDIR_POS (15U) +#define USBFS_HCCHAR7_EPDIR (0x00008000UL) +#define USBFS_HCCHAR7_LSPDDEV_POS (17U) +#define USBFS_HCCHAR7_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR7_EPTYPE_POS (18U) +#define USBFS_HCCHAR7_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR7_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR7_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR7_EC_POS (20U) +#define USBFS_HCCHAR7_EC (0x00300000UL) +#define USBFS_HCCHAR7_DEVADDR_POS (22U) +#define USBFS_HCCHAR7_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR7_ODDFRM_POS (29U) +#define USBFS_HCCHAR7_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR7_CHDIS_POS (30U) +#define USBFS_HCCHAR7_CHDIS (0x40000000UL) +#define USBFS_HCCHAR7_CHENA_POS (31U) +#define USBFS_HCCHAR7_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT7 register */ +#define USBFS_HCSPLT7_PRTADDR_POS (0U) +#define USBFS_HCSPLT7_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT7_HUBADDR_POS (7U) +#define USBFS_HCSPLT7_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT7_XACTPOS_POS (14U) +#define USBFS_HCSPLT7_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT7_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT7_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT7_COMPSPLT_POS (16U) +#define USBFS_HCSPLT7_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT7_SPLTENA_POS (31U) +#define USBFS_HCSPLT7_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT7 register */ +#define USBFS_HCINT7_XFERCOMPL_POS (0U) +#define USBFS_HCINT7_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT7_CHHLTD_POS (1U) +#define USBFS_HCINT7_CHHLTD (0x00000002UL) +#define USBFS_HCINT7_AHBERR_POS (2U) +#define USBFS_HCINT7_AHBERR (0x00000004UL) +#define USBFS_HCINT7_STALL_POS (3U) +#define USBFS_HCINT7_STALL (0x00000008UL) +#define USBFS_HCINT7_NAK_POS (4U) +#define USBFS_HCINT7_NAK (0x00000010UL) +#define USBFS_HCINT7_ACK_POS (5U) +#define USBFS_HCINT7_ACK (0x00000020UL) +#define USBFS_HCINT7_NYET_POS (6U) +#define USBFS_HCINT7_NYET (0x00000040UL) +#define USBFS_HCINT7_XACTERR_POS (7U) +#define USBFS_HCINT7_XACTERR (0x00000080UL) +#define USBFS_HCINT7_BBLERR_POS (8U) +#define USBFS_HCINT7_BBLERR (0x00000100UL) +#define USBFS_HCINT7_FRMOVRUN_POS (9U) +#define USBFS_HCINT7_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT7_DATATGLERR_POS (10U) +#define USBFS_HCINT7_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK7 register */ +#define USBFS_HCINTMSK7_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK7_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK7_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK7_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK7_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK7_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK7_STALLMSK_POS (3U) +#define USBFS_HCINTMSK7_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK7_NAKMSK_POS (4U) +#define USBFS_HCINTMSK7_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK7_ACKMSK_POS (5U) +#define USBFS_HCINTMSK7_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK7_NYETMSK_POS (6U) +#define USBFS_HCINTMSK7_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK7_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK7_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK7_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK7_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK7_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK7_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK7_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK7_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ7 register */ +#define USBFS_HCTSIZ7_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ7_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ7_PKTCNT_POS (19U) +#define USBFS_HCTSIZ7_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ7_PID_POS (29U) +#define USBFS_HCTSIZ7_PID (0x60000000UL) +#define USBFS_HCTSIZ7_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ7_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ7_DOPNG_POS (31U) +#define USBFS_HCTSIZ7_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA7 register */ +#define USBFS_HCDMA7 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR8 register */ +#define USBFS_HCCHAR8_MPS_POS (0U) +#define USBFS_HCCHAR8_MPS (0x000007FFUL) +#define USBFS_HCCHAR8_EPNUM_POS (11U) +#define USBFS_HCCHAR8_EPNUM (0x00007800UL) +#define USBFS_HCCHAR8_EPDIR_POS (15U) +#define USBFS_HCCHAR8_EPDIR (0x00008000UL) +#define USBFS_HCCHAR8_LSPDDEV_POS (17U) +#define USBFS_HCCHAR8_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR8_EPTYPE_POS (18U) +#define USBFS_HCCHAR8_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR8_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR8_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR8_EC_POS (20U) +#define USBFS_HCCHAR8_EC (0x00300000UL) +#define USBFS_HCCHAR8_DEVADDR_POS (22U) +#define USBFS_HCCHAR8_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR8_ODDFRM_POS (29U) +#define USBFS_HCCHAR8_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR8_CHDIS_POS (30U) +#define USBFS_HCCHAR8_CHDIS (0x40000000UL) +#define USBFS_HCCHAR8_CHENA_POS (31U) +#define USBFS_HCCHAR8_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT8 register */ +#define USBFS_HCSPLT8_PRTADDR_POS (0U) +#define USBFS_HCSPLT8_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT8_HUBADDR_POS (7U) +#define USBFS_HCSPLT8_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT8_XACTPOS_POS (14U) +#define USBFS_HCSPLT8_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT8_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT8_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT8_COMPSPLT_POS (16U) +#define USBFS_HCSPLT8_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT8_SPLTENA_POS (31U) +#define USBFS_HCSPLT8_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT8 register */ +#define USBFS_HCINT8_XFERCOMPL_POS (0U) +#define USBFS_HCINT8_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT8_CHHLTD_POS (1U) +#define USBFS_HCINT8_CHHLTD (0x00000002UL) +#define USBFS_HCINT8_AHBERR_POS (2U) +#define USBFS_HCINT8_AHBERR (0x00000004UL) +#define USBFS_HCINT8_STALL_POS (3U) +#define USBFS_HCINT8_STALL (0x00000008UL) +#define USBFS_HCINT8_NAK_POS (4U) +#define USBFS_HCINT8_NAK (0x00000010UL) +#define USBFS_HCINT8_ACK_POS (5U) +#define USBFS_HCINT8_ACK (0x00000020UL) +#define USBFS_HCINT8_NYET_POS (6U) +#define USBFS_HCINT8_NYET (0x00000040UL) +#define USBFS_HCINT8_XACTERR_POS (7U) +#define USBFS_HCINT8_XACTERR (0x00000080UL) +#define USBFS_HCINT8_BBLERR_POS (8U) +#define USBFS_HCINT8_BBLERR (0x00000100UL) +#define USBFS_HCINT8_FRMOVRUN_POS (9U) +#define USBFS_HCINT8_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT8_DATATGLERR_POS (10U) +#define USBFS_HCINT8_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK8 register */ +#define USBFS_HCINTMSK8_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK8_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK8_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK8_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK8_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK8_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK8_STALLMSK_POS (3U) +#define USBFS_HCINTMSK8_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK8_NAKMSK_POS (4U) +#define USBFS_HCINTMSK8_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK8_ACKMSK_POS (5U) +#define USBFS_HCINTMSK8_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK8_NYETMSK_POS (6U) +#define USBFS_HCINTMSK8_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK8_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK8_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK8_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK8_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK8_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK8_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK8_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK8_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ8 register */ +#define USBFS_HCTSIZ8_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ8_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ8_PKTCNT_POS (19U) +#define USBFS_HCTSIZ8_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ8_PID_POS (29U) +#define USBFS_HCTSIZ8_PID (0x60000000UL) +#define USBFS_HCTSIZ8_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ8_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ8_DOPNG_POS (31U) +#define USBFS_HCTSIZ8_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA8 register */ +#define USBFS_HCDMA8 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR9 register */ +#define USBFS_HCCHAR9_MPS_POS (0U) +#define USBFS_HCCHAR9_MPS (0x000007FFUL) +#define USBFS_HCCHAR9_EPNUM_POS (11U) +#define USBFS_HCCHAR9_EPNUM (0x00007800UL) +#define USBFS_HCCHAR9_EPDIR_POS (15U) +#define USBFS_HCCHAR9_EPDIR (0x00008000UL) +#define USBFS_HCCHAR9_LSPDDEV_POS (17U) +#define USBFS_HCCHAR9_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR9_EPTYPE_POS (18U) +#define USBFS_HCCHAR9_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR9_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR9_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR9_EC_POS (20U) +#define USBFS_HCCHAR9_EC (0x00300000UL) +#define USBFS_HCCHAR9_DEVADDR_POS (22U) +#define USBFS_HCCHAR9_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR9_ODDFRM_POS (29U) +#define USBFS_HCCHAR9_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR9_CHDIS_POS (30U) +#define USBFS_HCCHAR9_CHDIS (0x40000000UL) +#define USBFS_HCCHAR9_CHENA_POS (31U) +#define USBFS_HCCHAR9_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT9 register */ +#define USBFS_HCSPLT9_PRTADDR_POS (0U) +#define USBFS_HCSPLT9_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT9_HUBADDR_POS (7U) +#define USBFS_HCSPLT9_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT9_XACTPOS_POS (14U) +#define USBFS_HCSPLT9_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT9_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT9_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT9_COMPSPLT_POS (16U) +#define USBFS_HCSPLT9_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT9_SPLTENA_POS (31U) +#define USBFS_HCSPLT9_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT9 register */ +#define USBFS_HCINT9_XFERCOMPL_POS (0U) +#define USBFS_HCINT9_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT9_CHHLTD_POS (1U) +#define USBFS_HCINT9_CHHLTD (0x00000002UL) +#define USBFS_HCINT9_AHBERR_POS (2U) +#define USBFS_HCINT9_AHBERR (0x00000004UL) +#define USBFS_HCINT9_STALL_POS (3U) +#define USBFS_HCINT9_STALL (0x00000008UL) +#define USBFS_HCINT9_NAK_POS (4U) +#define USBFS_HCINT9_NAK (0x00000010UL) +#define USBFS_HCINT9_ACK_POS (5U) +#define USBFS_HCINT9_ACK (0x00000020UL) +#define USBFS_HCINT9_NYET_POS (6U) +#define USBFS_HCINT9_NYET (0x00000040UL) +#define USBFS_HCINT9_XACTERR_POS (7U) +#define USBFS_HCINT9_XACTERR (0x00000080UL) +#define USBFS_HCINT9_BBLERR_POS (8U) +#define USBFS_HCINT9_BBLERR (0x00000100UL) +#define USBFS_HCINT9_FRMOVRUN_POS (9U) +#define USBFS_HCINT9_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT9_DATATGLERR_POS (10U) +#define USBFS_HCINT9_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK9 register */ +#define USBFS_HCINTMSK9_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK9_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK9_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK9_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK9_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK9_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK9_STALLMSK_POS (3U) +#define USBFS_HCINTMSK9_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK9_NAKMSK_POS (4U) +#define USBFS_HCINTMSK9_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK9_ACKMSK_POS (5U) +#define USBFS_HCINTMSK9_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK9_NYETMSK_POS (6U) +#define USBFS_HCINTMSK9_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK9_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK9_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK9_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK9_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK9_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK9_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK9_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK9_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ9 register */ +#define USBFS_HCTSIZ9_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ9_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ9_PKTCNT_POS (19U) +#define USBFS_HCTSIZ9_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ9_PID_POS (29U) +#define USBFS_HCTSIZ9_PID (0x60000000UL) +#define USBFS_HCTSIZ9_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ9_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ9_DOPNG_POS (31U) +#define USBFS_HCTSIZ9_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA9 register */ +#define USBFS_HCDMA9 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR10 register */ +#define USBFS_HCCHAR10_MPS_POS (0U) +#define USBFS_HCCHAR10_MPS (0x000007FFUL) +#define USBFS_HCCHAR10_EPNUM_POS (11U) +#define USBFS_HCCHAR10_EPNUM (0x00007800UL) +#define USBFS_HCCHAR10_EPDIR_POS (15U) +#define USBFS_HCCHAR10_EPDIR (0x00008000UL) +#define USBFS_HCCHAR10_LSPDDEV_POS (17U) +#define USBFS_HCCHAR10_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR10_EPTYPE_POS (18U) +#define USBFS_HCCHAR10_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR10_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR10_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR10_EC_POS (20U) +#define USBFS_HCCHAR10_EC (0x00300000UL) +#define USBFS_HCCHAR10_DEVADDR_POS (22U) +#define USBFS_HCCHAR10_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR10_ODDFRM_POS (29U) +#define USBFS_HCCHAR10_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR10_CHDIS_POS (30U) +#define USBFS_HCCHAR10_CHDIS (0x40000000UL) +#define USBFS_HCCHAR10_CHENA_POS (31U) +#define USBFS_HCCHAR10_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT10 register */ +#define USBFS_HCSPLT10_PRTADDR_POS (0U) +#define USBFS_HCSPLT10_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT10_HUBADDR_POS (7U) +#define USBFS_HCSPLT10_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT10_XACTPOS_POS (14U) +#define USBFS_HCSPLT10_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT10_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT10_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT10_COMPSPLT_POS (16U) +#define USBFS_HCSPLT10_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT10_SPLTENA_POS (31U) +#define USBFS_HCSPLT10_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT10 register */ +#define USBFS_HCINT10_XFERCOMPL_POS (0U) +#define USBFS_HCINT10_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT10_CHHLTD_POS (1U) +#define USBFS_HCINT10_CHHLTD (0x00000002UL) +#define USBFS_HCINT10_AHBERR_POS (2U) +#define USBFS_HCINT10_AHBERR (0x00000004UL) +#define USBFS_HCINT10_STALL_POS (3U) +#define USBFS_HCINT10_STALL (0x00000008UL) +#define USBFS_HCINT10_NAK_POS (4U) +#define USBFS_HCINT10_NAK (0x00000010UL) +#define USBFS_HCINT10_ACK_POS (5U) +#define USBFS_HCINT10_ACK (0x00000020UL) +#define USBFS_HCINT10_NYET_POS (6U) +#define USBFS_HCINT10_NYET (0x00000040UL) +#define USBFS_HCINT10_XACTERR_POS (7U) +#define USBFS_HCINT10_XACTERR (0x00000080UL) +#define USBFS_HCINT10_BBLERR_POS (8U) +#define USBFS_HCINT10_BBLERR (0x00000100UL) +#define USBFS_HCINT10_FRMOVRUN_POS (9U) +#define USBFS_HCINT10_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT10_DATATGLERR_POS (10U) +#define USBFS_HCINT10_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK10 register */ +#define USBFS_HCINTMSK10_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK10_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK10_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK10_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK10_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK10_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK10_STALLMSK_POS (3U) +#define USBFS_HCINTMSK10_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK10_NAKMSK_POS (4U) +#define USBFS_HCINTMSK10_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK10_ACKMSK_POS (5U) +#define USBFS_HCINTMSK10_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK10_NYETMSK_POS (6U) +#define USBFS_HCINTMSK10_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK10_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK10_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK10_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK10_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK10_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK10_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK10_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK10_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ10 register */ +#define USBFS_HCTSIZ10_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ10_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ10_PKTCNT_POS (19U) +#define USBFS_HCTSIZ10_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ10_PID_POS (29U) +#define USBFS_HCTSIZ10_PID (0x60000000UL) +#define USBFS_HCTSIZ10_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ10_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ10_DOPNG_POS (31U) +#define USBFS_HCTSIZ10_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA10 register */ +#define USBFS_HCDMA10 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR11 register */ +#define USBFS_HCCHAR11_MPS_POS (0U) +#define USBFS_HCCHAR11_MPS (0x000007FFUL) +#define USBFS_HCCHAR11_EPNUM_POS (11U) +#define USBFS_HCCHAR11_EPNUM (0x00007800UL) +#define USBFS_HCCHAR11_EPDIR_POS (15U) +#define USBFS_HCCHAR11_EPDIR (0x00008000UL) +#define USBFS_HCCHAR11_LSPDDEV_POS (17U) +#define USBFS_HCCHAR11_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR11_EPTYPE_POS (18U) +#define USBFS_HCCHAR11_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR11_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR11_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR11_EC_POS (20U) +#define USBFS_HCCHAR11_EC (0x00300000UL) +#define USBFS_HCCHAR11_DEVADDR_POS (22U) +#define USBFS_HCCHAR11_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR11_ODDFRM_POS (29U) +#define USBFS_HCCHAR11_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR11_CHDIS_POS (30U) +#define USBFS_HCCHAR11_CHDIS (0x40000000UL) +#define USBFS_HCCHAR11_CHENA_POS (31U) +#define USBFS_HCCHAR11_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT11 register */ +#define USBFS_HCSPLT11_PRTADDR_POS (0U) +#define USBFS_HCSPLT11_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT11_HUBADDR_POS (7U) +#define USBFS_HCSPLT11_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT11_XACTPOS_POS (14U) +#define USBFS_HCSPLT11_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT11_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT11_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT11_COMPSPLT_POS (16U) +#define USBFS_HCSPLT11_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT11_SPLTENA_POS (31U) +#define USBFS_HCSPLT11_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT11 register */ +#define USBFS_HCINT11_XFERCOMPL_POS (0U) +#define USBFS_HCINT11_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT11_CHHLTD_POS (1U) +#define USBFS_HCINT11_CHHLTD (0x00000002UL) +#define USBFS_HCINT11_AHBERR_POS (2U) +#define USBFS_HCINT11_AHBERR (0x00000004UL) +#define USBFS_HCINT11_STALL_POS (3U) +#define USBFS_HCINT11_STALL (0x00000008UL) +#define USBFS_HCINT11_NAK_POS (4U) +#define USBFS_HCINT11_NAK (0x00000010UL) +#define USBFS_HCINT11_ACK_POS (5U) +#define USBFS_HCINT11_ACK (0x00000020UL) +#define USBFS_HCINT11_NYET_POS (6U) +#define USBFS_HCINT11_NYET (0x00000040UL) +#define USBFS_HCINT11_XACTERR_POS (7U) +#define USBFS_HCINT11_XACTERR (0x00000080UL) +#define USBFS_HCINT11_BBLERR_POS (8U) +#define USBFS_HCINT11_BBLERR (0x00000100UL) +#define USBFS_HCINT11_FRMOVRUN_POS (9U) +#define USBFS_HCINT11_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT11_DATATGLERR_POS (10U) +#define USBFS_HCINT11_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK11 register */ +#define USBFS_HCINTMSK11_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK11_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK11_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK11_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK11_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK11_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK11_STALLMSK_POS (3U) +#define USBFS_HCINTMSK11_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK11_NAKMSK_POS (4U) +#define USBFS_HCINTMSK11_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK11_ACKMSK_POS (5U) +#define USBFS_HCINTMSK11_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK11_NYETMSK_POS (6U) +#define USBFS_HCINTMSK11_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK11_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK11_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK11_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK11_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK11_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK11_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK11_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK11_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ11 register */ +#define USBFS_HCTSIZ11_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ11_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ11_PKTCNT_POS (19U) +#define USBFS_HCTSIZ11_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ11_PID_POS (29U) +#define USBFS_HCTSIZ11_PID (0x60000000UL) +#define USBFS_HCTSIZ11_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ11_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ11_DOPNG_POS (31U) +#define USBFS_HCTSIZ11_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA11 register */ +#define USBFS_HCDMA11 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR12 register */ +#define USBFS_HCCHAR12_MPS_POS (0U) +#define USBFS_HCCHAR12_MPS (0x000007FFUL) +#define USBFS_HCCHAR12_EPNUM_POS (11U) +#define USBFS_HCCHAR12_EPNUM (0x00007800UL) +#define USBFS_HCCHAR12_EPDIR_POS (15U) +#define USBFS_HCCHAR12_EPDIR (0x00008000UL) +#define USBFS_HCCHAR12_LSPDDEV_POS (17U) +#define USBFS_HCCHAR12_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR12_EPTYPE_POS (18U) +#define USBFS_HCCHAR12_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR12_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR12_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR12_EC_POS (20U) +#define USBFS_HCCHAR12_EC (0x00300000UL) +#define USBFS_HCCHAR12_DEVADDR_POS (22U) +#define USBFS_HCCHAR12_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR12_ODDFRM_POS (29U) +#define USBFS_HCCHAR12_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR12_CHDIS_POS (30U) +#define USBFS_HCCHAR12_CHDIS (0x40000000UL) +#define USBFS_HCCHAR12_CHENA_POS (31U) +#define USBFS_HCCHAR12_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT12 register */ +#define USBFS_HCSPLT12_PRTADDR_POS (0U) +#define USBFS_HCSPLT12_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT12_HUBADDR_POS (7U) +#define USBFS_HCSPLT12_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT12_XACTPOS_POS (14U) +#define USBFS_HCSPLT12_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT12_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT12_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT12_COMPSPLT_POS (16U) +#define USBFS_HCSPLT12_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT12_SPLTENA_POS (31U) +#define USBFS_HCSPLT12_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT12 register */ +#define USBFS_HCINT12_XFERCOMPL_POS (0U) +#define USBFS_HCINT12_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT12_CHHLTD_POS (1U) +#define USBFS_HCINT12_CHHLTD (0x00000002UL) +#define USBFS_HCINT12_AHBERR_POS (2U) +#define USBFS_HCINT12_AHBERR (0x00000004UL) +#define USBFS_HCINT12_STALL_POS (3U) +#define USBFS_HCINT12_STALL (0x00000008UL) +#define USBFS_HCINT12_NAK_POS (4U) +#define USBFS_HCINT12_NAK (0x00000010UL) +#define USBFS_HCINT12_ACK_POS (5U) +#define USBFS_HCINT12_ACK (0x00000020UL) +#define USBFS_HCINT12_NYET_POS (6U) +#define USBFS_HCINT12_NYET (0x00000040UL) +#define USBFS_HCINT12_XACTERR_POS (7U) +#define USBFS_HCINT12_XACTERR (0x00000080UL) +#define USBFS_HCINT12_BBLERR_POS (8U) +#define USBFS_HCINT12_BBLERR (0x00000100UL) +#define USBFS_HCINT12_FRMOVRUN_POS (9U) +#define USBFS_HCINT12_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT12_DATATGLERR_POS (10U) +#define USBFS_HCINT12_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK12 register */ +#define USBFS_HCINTMSK12_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK12_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK12_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK12_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK12_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK12_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK12_STALLMSK_POS (3U) +#define USBFS_HCINTMSK12_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK12_NAKMSK_POS (4U) +#define USBFS_HCINTMSK12_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK12_ACKMSK_POS (5U) +#define USBFS_HCINTMSK12_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK12_NYETMSK_POS (6U) +#define USBFS_HCINTMSK12_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK12_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK12_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK12_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK12_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK12_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK12_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK12_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK12_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ12 register */ +#define USBFS_HCTSIZ12_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ12_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ12_PKTCNT_POS (19U) +#define USBFS_HCTSIZ12_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ12_PID_POS (29U) +#define USBFS_HCTSIZ12_PID (0x60000000UL) +#define USBFS_HCTSIZ12_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ12_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ12_DOPNG_POS (31U) +#define USBFS_HCTSIZ12_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA12 register */ +#define USBFS_HCDMA12 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR13 register */ +#define USBFS_HCCHAR13_MPS_POS (0U) +#define USBFS_HCCHAR13_MPS (0x000007FFUL) +#define USBFS_HCCHAR13_EPNUM_POS (11U) +#define USBFS_HCCHAR13_EPNUM (0x00007800UL) +#define USBFS_HCCHAR13_EPDIR_POS (15U) +#define USBFS_HCCHAR13_EPDIR (0x00008000UL) +#define USBFS_HCCHAR13_LSPDDEV_POS (17U) +#define USBFS_HCCHAR13_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR13_EPTYPE_POS (18U) +#define USBFS_HCCHAR13_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR13_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR13_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR13_EC_POS (20U) +#define USBFS_HCCHAR13_EC (0x00300000UL) +#define USBFS_HCCHAR13_DEVADDR_POS (22U) +#define USBFS_HCCHAR13_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR13_ODDFRM_POS (29U) +#define USBFS_HCCHAR13_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR13_CHDIS_POS (30U) +#define USBFS_HCCHAR13_CHDIS (0x40000000UL) +#define USBFS_HCCHAR13_CHENA_POS (31U) +#define USBFS_HCCHAR13_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT13 register */ +#define USBFS_HCSPLT13_PRTADDR_POS (0U) +#define USBFS_HCSPLT13_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT13_HUBADDR_POS (7U) +#define USBFS_HCSPLT13_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT13_XACTPOS_POS (14U) +#define USBFS_HCSPLT13_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT13_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT13_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT13_COMPSPLT_POS (16U) +#define USBFS_HCSPLT13_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT13_SPLTENA_POS (31U) +#define USBFS_HCSPLT13_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT13 register */ +#define USBFS_HCINT13_XFERCOMPL_POS (0U) +#define USBFS_HCINT13_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT13_CHHLTD_POS (1U) +#define USBFS_HCINT13_CHHLTD (0x00000002UL) +#define USBFS_HCINT13_AHBERR_POS (2U) +#define USBFS_HCINT13_AHBERR (0x00000004UL) +#define USBFS_HCINT13_STALL_POS (3U) +#define USBFS_HCINT13_STALL (0x00000008UL) +#define USBFS_HCINT13_NAK_POS (4U) +#define USBFS_HCINT13_NAK (0x00000010UL) +#define USBFS_HCINT13_ACK_POS (5U) +#define USBFS_HCINT13_ACK (0x00000020UL) +#define USBFS_HCINT13_NYET_POS (6U) +#define USBFS_HCINT13_NYET (0x00000040UL) +#define USBFS_HCINT13_XACTERR_POS (7U) +#define USBFS_HCINT13_XACTERR (0x00000080UL) +#define USBFS_HCINT13_BBLERR_POS (8U) +#define USBFS_HCINT13_BBLERR (0x00000100UL) +#define USBFS_HCINT13_FRMOVRUN_POS (9U) +#define USBFS_HCINT13_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT13_DATATGLERR_POS (10U) +#define USBFS_HCINT13_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK13 register */ +#define USBFS_HCINTMSK13_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK13_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK13_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK13_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK13_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK13_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK13_STALLMSK_POS (3U) +#define USBFS_HCINTMSK13_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK13_NAKMSK_POS (4U) +#define USBFS_HCINTMSK13_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK13_ACKMSK_POS (5U) +#define USBFS_HCINTMSK13_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK13_NYETMSK_POS (6U) +#define USBFS_HCINTMSK13_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK13_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK13_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK13_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK13_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK13_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK13_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK13_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK13_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ13 register */ +#define USBFS_HCTSIZ13_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ13_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ13_PKTCNT_POS (19U) +#define USBFS_HCTSIZ13_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ13_PID_POS (29U) +#define USBFS_HCTSIZ13_PID (0x60000000UL) +#define USBFS_HCTSIZ13_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ13_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ13_DOPNG_POS (31U) +#define USBFS_HCTSIZ13_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA13 register */ +#define USBFS_HCDMA13 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR14 register */ +#define USBFS_HCCHAR14_MPS_POS (0U) +#define USBFS_HCCHAR14_MPS (0x000007FFUL) +#define USBFS_HCCHAR14_EPNUM_POS (11U) +#define USBFS_HCCHAR14_EPNUM (0x00007800UL) +#define USBFS_HCCHAR14_EPDIR_POS (15U) +#define USBFS_HCCHAR14_EPDIR (0x00008000UL) +#define USBFS_HCCHAR14_LSPDDEV_POS (17U) +#define USBFS_HCCHAR14_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR14_EPTYPE_POS (18U) +#define USBFS_HCCHAR14_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR14_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR14_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR14_EC_POS (20U) +#define USBFS_HCCHAR14_EC (0x00300000UL) +#define USBFS_HCCHAR14_DEVADDR_POS (22U) +#define USBFS_HCCHAR14_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR14_ODDFRM_POS (29U) +#define USBFS_HCCHAR14_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR14_CHDIS_POS (30U) +#define USBFS_HCCHAR14_CHDIS (0x40000000UL) +#define USBFS_HCCHAR14_CHENA_POS (31U) +#define USBFS_HCCHAR14_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT14 register */ +#define USBFS_HCSPLT14_PRTADDR_POS (0U) +#define USBFS_HCSPLT14_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT14_HUBADDR_POS (7U) +#define USBFS_HCSPLT14_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT14_XACTPOS_POS (14U) +#define USBFS_HCSPLT14_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT14_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT14_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT14_COMPSPLT_POS (16U) +#define USBFS_HCSPLT14_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT14_SPLTENA_POS (31U) +#define USBFS_HCSPLT14_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT14 register */ +#define USBFS_HCINT14_XFERCOMPL_POS (0U) +#define USBFS_HCINT14_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT14_CHHLTD_POS (1U) +#define USBFS_HCINT14_CHHLTD (0x00000002UL) +#define USBFS_HCINT14_AHBERR_POS (2U) +#define USBFS_HCINT14_AHBERR (0x00000004UL) +#define USBFS_HCINT14_STALL_POS (3U) +#define USBFS_HCINT14_STALL (0x00000008UL) +#define USBFS_HCINT14_NAK_POS (4U) +#define USBFS_HCINT14_NAK (0x00000010UL) +#define USBFS_HCINT14_ACK_POS (5U) +#define USBFS_HCINT14_ACK (0x00000020UL) +#define USBFS_HCINT14_NYET_POS (6U) +#define USBFS_HCINT14_NYET (0x00000040UL) +#define USBFS_HCINT14_XACTERR_POS (7U) +#define USBFS_HCINT14_XACTERR (0x00000080UL) +#define USBFS_HCINT14_BBLERR_POS (8U) +#define USBFS_HCINT14_BBLERR (0x00000100UL) +#define USBFS_HCINT14_FRMOVRUN_POS (9U) +#define USBFS_HCINT14_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT14_DATATGLERR_POS (10U) +#define USBFS_HCINT14_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK14 register */ +#define USBFS_HCINTMSK14_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK14_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK14_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK14_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK14_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK14_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK14_STALLMSK_POS (3U) +#define USBFS_HCINTMSK14_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK14_NAKMSK_POS (4U) +#define USBFS_HCINTMSK14_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK14_ACKMSK_POS (5U) +#define USBFS_HCINTMSK14_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK14_NYETMSK_POS (6U) +#define USBFS_HCINTMSK14_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK14_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK14_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK14_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK14_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK14_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK14_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK14_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK14_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ14 register */ +#define USBFS_HCTSIZ14_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ14_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ14_PKTCNT_POS (19U) +#define USBFS_HCTSIZ14_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ14_PID_POS (29U) +#define USBFS_HCTSIZ14_PID (0x60000000UL) +#define USBFS_HCTSIZ14_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ14_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ14_DOPNG_POS (31U) +#define USBFS_HCTSIZ14_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA14 register */ +#define USBFS_HCDMA14 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_HCCHAR15 register */ +#define USBFS_HCCHAR15_MPS_POS (0U) +#define USBFS_HCCHAR15_MPS (0x000007FFUL) +#define USBFS_HCCHAR15_EPNUM_POS (11U) +#define USBFS_HCCHAR15_EPNUM (0x00007800UL) +#define USBFS_HCCHAR15_EPDIR_POS (15U) +#define USBFS_HCCHAR15_EPDIR (0x00008000UL) +#define USBFS_HCCHAR15_LSPDDEV_POS (17U) +#define USBFS_HCCHAR15_LSPDDEV (0x00020000UL) +#define USBFS_HCCHAR15_EPTYPE_POS (18U) +#define USBFS_HCCHAR15_EPTYPE (0x000C0000UL) +#define USBFS_HCCHAR15_EPTYPE_0 (0x00040000UL) +#define USBFS_HCCHAR15_EPTYPE_1 (0x00080000UL) +#define USBFS_HCCHAR15_EC_POS (20U) +#define USBFS_HCCHAR15_EC (0x00300000UL) +#define USBFS_HCCHAR15_DEVADDR_POS (22U) +#define USBFS_HCCHAR15_DEVADDR (0x1FC00000UL) +#define USBFS_HCCHAR15_ODDFRM_POS (29U) +#define USBFS_HCCHAR15_ODDFRM (0x20000000UL) +#define USBFS_HCCHAR15_CHDIS_POS (30U) +#define USBFS_HCCHAR15_CHDIS (0x40000000UL) +#define USBFS_HCCHAR15_CHENA_POS (31U) +#define USBFS_HCCHAR15_CHENA (0x80000000UL) + +/* Bit definition for USBFS_HCSPLT15 register */ +#define USBFS_HCSPLT15_PRTADDR_POS (0U) +#define USBFS_HCSPLT15_PRTADDR (0x0000007FUL) +#define USBFS_HCSPLT15_HUBADDR_POS (7U) +#define USBFS_HCSPLT15_HUBADDR (0x00003F80UL) +#define USBFS_HCSPLT15_XACTPOS_POS (14U) +#define USBFS_HCSPLT15_XACTPOS (0x0000C000UL) +#define USBFS_HCSPLT15_XACTPOS_0 (0x00004000UL) +#define USBFS_HCSPLT15_XACTPOS_1 (0x00008000UL) +#define USBFS_HCSPLT15_COMPSPLT_POS (16U) +#define USBFS_HCSPLT15_COMPSPLT (0x00010000UL) +#define USBFS_HCSPLT15_SPLTENA_POS (31U) +#define USBFS_HCSPLT15_SPLTENA (0x80000000UL) + +/* Bit definition for USBFS_HCINT15 register */ +#define USBFS_HCINT15_XFERCOMPL_POS (0U) +#define USBFS_HCINT15_XFERCOMPL (0x00000001UL) +#define USBFS_HCINT15_CHHLTD_POS (1U) +#define USBFS_HCINT15_CHHLTD (0x00000002UL) +#define USBFS_HCINT15_AHBERR_POS (2U) +#define USBFS_HCINT15_AHBERR (0x00000004UL) +#define USBFS_HCINT15_STALL_POS (3U) +#define USBFS_HCINT15_STALL (0x00000008UL) +#define USBFS_HCINT15_NAK_POS (4U) +#define USBFS_HCINT15_NAK (0x00000010UL) +#define USBFS_HCINT15_ACK_POS (5U) +#define USBFS_HCINT15_ACK (0x00000020UL) +#define USBFS_HCINT15_NYET_POS (6U) +#define USBFS_HCINT15_NYET (0x00000040UL) +#define USBFS_HCINT15_XACTERR_POS (7U) +#define USBFS_HCINT15_XACTERR (0x00000080UL) +#define USBFS_HCINT15_BBLERR_POS (8U) +#define USBFS_HCINT15_BBLERR (0x00000100UL) +#define USBFS_HCINT15_FRMOVRUN_POS (9U) +#define USBFS_HCINT15_FRMOVRUN (0x00000200UL) +#define USBFS_HCINT15_DATATGLERR_POS (10U) +#define USBFS_HCINT15_DATATGLERR (0x00000400UL) + +/* Bit definition for USBFS_HCINTMSK15 register */ +#define USBFS_HCINTMSK15_XFERCOMPLMSK_POS (0U) +#define USBFS_HCINTMSK15_XFERCOMPLMSK (0x00000001UL) +#define USBFS_HCINTMSK15_CHHLTDMSK_POS (1U) +#define USBFS_HCINTMSK15_CHHLTDMSK (0x00000002UL) +#define USBFS_HCINTMSK15_AHBERRMSK_POS (2U) +#define USBFS_HCINTMSK15_AHBERRMSK (0x00000004UL) +#define USBFS_HCINTMSK15_STALLMSK_POS (3U) +#define USBFS_HCINTMSK15_STALLMSK (0x00000008UL) +#define USBFS_HCINTMSK15_NAKMSK_POS (4U) +#define USBFS_HCINTMSK15_NAKMSK (0x00000010UL) +#define USBFS_HCINTMSK15_ACKMSK_POS (5U) +#define USBFS_HCINTMSK15_ACKMSK (0x00000020UL) +#define USBFS_HCINTMSK15_NYETMSK_POS (6U) +#define USBFS_HCINTMSK15_NYETMSK (0x00000040UL) +#define USBFS_HCINTMSK15_XACTERRMSK_POS (7U) +#define USBFS_HCINTMSK15_XACTERRMSK (0x00000080UL) +#define USBFS_HCINTMSK15_BBLERRMSK_POS (8U) +#define USBFS_HCINTMSK15_BBLERRMSK (0x00000100UL) +#define USBFS_HCINTMSK15_FRMOVRUNMSK_POS (9U) +#define USBFS_HCINTMSK15_FRMOVRUNMSK (0x00000200UL) +#define USBFS_HCINTMSK15_DATATGLERRMSK_POS (10U) +#define USBFS_HCINTMSK15_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBFS_HCTSIZ15 register */ +#define USBFS_HCTSIZ15_XFERSIZE_POS (0U) +#define USBFS_HCTSIZ15_XFERSIZE (0x0007FFFFUL) +#define USBFS_HCTSIZ15_PKTCNT_POS (19U) +#define USBFS_HCTSIZ15_PKTCNT (0x1FF80000UL) +#define USBFS_HCTSIZ15_PID_POS (29U) +#define USBFS_HCTSIZ15_PID (0x60000000UL) +#define USBFS_HCTSIZ15_PID_0 (0x20000000UL) +#define USBFS_HCTSIZ15_PID_1 (0x40000000UL) +#define USBFS_HCTSIZ15_DOPNG_POS (31U) +#define USBFS_HCTSIZ15_DOPNG (0x80000000UL) + +/* Bit definition for USBFS_HCDMA15 register */ +#define USBFS_HCDMA15 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DCFG register */ +#define USBFS_DCFG_DEVSPD_POS (0U) +#define USBFS_DCFG_DEVSPD (0x00000003UL) +#define USBFS_DCFG_DEVSPD_0 (0x00000001UL) +#define USBFS_DCFG_DEVSPD_1 (0x00000002UL) +#define USBFS_DCFG_NZSTSOUTHSHK_POS (2U) +#define USBFS_DCFG_NZSTSOUTHSHK (0x00000004UL) +#define USBFS_DCFG_ENA32KHZSUSP_POS (3U) +#define USBFS_DCFG_ENA32KHZSUSP (0x00000008UL) +#define USBFS_DCFG_DEVADDR_POS (4U) +#define USBFS_DCFG_DEVADDR (0x000007F0UL) +#define USBFS_DCFG_PERFRINT_POS (11U) +#define USBFS_DCFG_PERFRINT (0x00001800UL) +#define USBFS_DCFG_PERFRINT_0 (0x00000800UL) +#define USBFS_DCFG_PERFRINT_1 (0x00001000UL) +#define USBFS_DCFG_XCVRDLY_POS (14U) +#define USBFS_DCFG_XCVRDLY (0x00004000UL) +#define USBFS_DCFG_ERRATICINTMSK_POS (15U) +#define USBFS_DCFG_ERRATICINTMSK (0x00008000UL) +#define USBFS_DCFG_PERSCHINTVL_POS (24U) +#define USBFS_DCFG_PERSCHINTVL (0x03000000UL) +#define USBFS_DCFG_PERSCHINTVL_0 (0x01000000UL) +#define USBFS_DCFG_PERSCHINTVL_1 (0x02000000UL) +#define USBFS_DCFG_RESVALID_POS (26U) +#define USBFS_DCFG_RESVALID (0xFC000000UL) + +/* Bit definition for USBFS_DCTL register */ +#define USBFS_DCTL_RMTWKUPSIG_POS (0U) +#define USBFS_DCTL_RMTWKUPSIG (0x00000001UL) +#define USBFS_DCTL_SFTDISCON_POS (1U) +#define USBFS_DCTL_SFTDISCON (0x00000002UL) +#define USBFS_DCTL_GNPINNAKSTS_POS (2U) +#define USBFS_DCTL_GNPINNAKSTS (0x00000004UL) +#define USBFS_DCTL_GOUTNAKSTS_POS (3U) +#define USBFS_DCTL_GOUTNAKSTS (0x00000008UL) +#define USBFS_DCTL_TSTCTL_POS (4U) +#define USBFS_DCTL_TSTCTL (0x00000070UL) +#define USBFS_DCTL_TSTCTL_0 (0x00000010UL) +#define USBFS_DCTL_TSTCTL_1 (0x00000020UL) +#define USBFS_DCTL_TSTCTL_2 (0x00000040UL) +#define USBFS_DCTL_SGNPINNAK_POS (7U) +#define USBFS_DCTL_SGNPINNAK (0x00000080UL) +#define USBFS_DCTL_CGNPINNAK_POS (8U) +#define USBFS_DCTL_CGNPINNAK (0x00000100UL) +#define USBFS_DCTL_SGOUTNAK_POS (9U) +#define USBFS_DCTL_SGOUTNAK (0x00000200UL) +#define USBFS_DCTL_CGOUTNAK_POS (10U) +#define USBFS_DCTL_CGOUTNAK (0x00000400UL) +#define USBFS_DCTL_PWRONPRGDONE_POS (11U) +#define USBFS_DCTL_PWRONPRGDONE (0x00000800UL) +#define USBFS_DCTL_IGNRFRMNUM_POS (15U) +#define USBFS_DCTL_IGNRFRMNUM (0x00008000UL) +#define USBFS_DCTL_NAKONBBLE_POS (16U) +#define USBFS_DCTL_NAKONBBLE (0x00010000UL) +#define USBFS_DCTL_DEEPSLEEPBESLREJECT_POS (18U) +#define USBFS_DCTL_DEEPSLEEPBESLREJECT (0x00040000UL) +#define USBFS_DCTL_SERVINT_POS (19U) +#define USBFS_DCTL_SERVINT (0x00080000UL) + +/* Bit definition for USBFS_DSTS register */ +#define USBFS_DSTS_SUSPSTS_POS (0U) +#define USBFS_DSTS_SUSPSTS (0x00000001UL) +#define USBFS_DSTS_ENUMSPD_POS (1U) +#define USBFS_DSTS_ENUMSPD (0x00000006UL) +#define USBFS_DSTS_ENUMSPD_0 (0x00000002UL) +#define USBFS_DSTS_ENUMSPD_1 (0x00000004UL) +#define USBFS_DSTS_ERRTICERR_POS (3U) +#define USBFS_DSTS_ERRTICERR (0x00000008UL) +#define USBFS_DSTS_SOFFN_POS (8U) +#define USBFS_DSTS_SOFFN (0x003FFF00UL) +#define USBFS_DSTS_DEVLNSTS_POS (22U) +#define USBFS_DSTS_DEVLNSTS (0x00C00000UL) +#define USBFS_DSTS_DEVLNSTS_0 (0x00400000UL) +#define USBFS_DSTS_DEVLNSTS_1 (0x00800000UL) + +/* Bit definition for USBFS_DIEPMSK register */ +#define USBFS_DIEPMSK_XFERCOMPLMSK_POS (0U) +#define USBFS_DIEPMSK_XFERCOMPLMSK (0x00000001UL) +#define USBFS_DIEPMSK_EPDISBLDMSK_POS (1U) +#define USBFS_DIEPMSK_EPDISBLDMSK (0x00000002UL) +#define USBFS_DIEPMSK_AHBERRMSK_POS (2U) +#define USBFS_DIEPMSK_AHBERRMSK (0x00000004UL) +#define USBFS_DIEPMSK_TIMEOUTMSK_POS (3U) +#define USBFS_DIEPMSK_TIMEOUTMSK (0x00000008UL) +#define USBFS_DIEPMSK_INTKNTXFEMPMSK_POS (4U) +#define USBFS_DIEPMSK_INTKNTXFEMPMSK (0x00000010UL) +#define USBFS_DIEPMSK_INTKNEPMISMSK_POS (5U) +#define USBFS_DIEPMSK_INTKNEPMISMSK (0x00000020UL) +#define USBFS_DIEPMSK_INEPNAKEFFMSK_POS (6U) +#define USBFS_DIEPMSK_INEPNAKEFFMSK (0x00000040UL) +#define USBFS_DIEPMSK_TXFIFOUNDRNMSK_POS (8U) +#define USBFS_DIEPMSK_TXFIFOUNDRNMSK (0x00000100UL) +#define USBFS_DIEPMSK_NAKMSK_POS (13U) +#define USBFS_DIEPMSK_NAKMSK (0x00002000UL) + +/* Bit definition for USBFS_DOEPMSK register */ +#define USBFS_DOEPMSK_XFERCOMPLMSK_POS (0U) +#define USBFS_DOEPMSK_XFERCOMPLMSK (0x00000001UL) +#define USBFS_DOEPMSK_EPDISBLDMSK_POS (1U) +#define USBFS_DOEPMSK_EPDISBLDMSK (0x00000002UL) +#define USBFS_DOEPMSK_AHBERRMSK_POS (2U) +#define USBFS_DOEPMSK_AHBERRMSK (0x00000004UL) +#define USBFS_DOEPMSK_SETUPMSK_POS (3U) +#define USBFS_DOEPMSK_SETUPMSK (0x00000008UL) +#define USBFS_DOEPMSK_OUTTKNEPDISMSK_POS (4U) +#define USBFS_DOEPMSK_OUTTKNEPDISMSK (0x00000010UL) +#define USBFS_DOEPMSK_STSPHSERCVDMSK_POS (5U) +#define USBFS_DOEPMSK_STSPHSERCVDMSK (0x00000020UL) +#define USBFS_DOEPMSK_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPMSK_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPMSK_OUTPKTERRMSK_POS (8U) +#define USBFS_DOEPMSK_OUTPKTERRMSK (0x00000100UL) +#define USBFS_DOEPMSK_BBLEERRMSK_POS (12U) +#define USBFS_DOEPMSK_BBLEERRMSK (0x00001000UL) +#define USBFS_DOEPMSK_NAKMSK_POS (13U) +#define USBFS_DOEPMSK_NAKMSK (0x00002000UL) +#define USBFS_DOEPMSK_NYETMSK_POS (14U) +#define USBFS_DOEPMSK_NYETMSK (0x00004000UL) + +/* Bit definition for USBFS_DAINT register */ +#define USBFS_DAINT_INEPINT0_POS (0U) +#define USBFS_DAINT_INEPINT0 (0x00000001UL) +#define USBFS_DAINT_INEPINT1_POS (1U) +#define USBFS_DAINT_INEPINT1 (0x00000002UL) +#define USBFS_DAINT_INEPINT2_POS (2U) +#define USBFS_DAINT_INEPINT2 (0x00000004UL) +#define USBFS_DAINT_INEPINT3_POS (3U) +#define USBFS_DAINT_INEPINT3 (0x00000008UL) +#define USBFS_DAINT_INEPINT4_POS (4U) +#define USBFS_DAINT_INEPINT4 (0x00000010UL) +#define USBFS_DAINT_INEPINT5_POS (5U) +#define USBFS_DAINT_INEPINT5 (0x00000020UL) +#define USBFS_DAINT_INEPINT6_POS (6U) +#define USBFS_DAINT_INEPINT6 (0x00000040UL) +#define USBFS_DAINT_INEPINT7_POS (7U) +#define USBFS_DAINT_INEPINT7 (0x00000080UL) +#define USBFS_DAINT_INEPINT8_POS (8U) +#define USBFS_DAINT_INEPINT8 (0x00000100UL) +#define USBFS_DAINT_INEPINT9_POS (9U) +#define USBFS_DAINT_INEPINT9 (0x00000200UL) +#define USBFS_DAINT_INEPINT10_POS (10U) +#define USBFS_DAINT_INEPINT10 (0x00000400UL) +#define USBFS_DAINT_INEPINT11_POS (11U) +#define USBFS_DAINT_INEPINT11 (0x00000800UL) +#define USBFS_DAINT_INEPINT12_POS (12U) +#define USBFS_DAINT_INEPINT12 (0x00001000UL) +#define USBFS_DAINT_INEPINT13_POS (13U) +#define USBFS_DAINT_INEPINT13 (0x00002000UL) +#define USBFS_DAINT_INEPINT14_POS (14U) +#define USBFS_DAINT_INEPINT14 (0x00004000UL) +#define USBFS_DAINT_INEPINT15_POS (15U) +#define USBFS_DAINT_INEPINT15 (0x00008000UL) +#define USBFS_DAINT_OUTEPINT0_POS (16U) +#define USBFS_DAINT_OUTEPINT0 (0x00010000UL) +#define USBFS_DAINT_OUTEPINT1_POS (17U) +#define USBFS_DAINT_OUTEPINT1 (0x00020000UL) +#define USBFS_DAINT_OUTEPINT2_POS (18U) +#define USBFS_DAINT_OUTEPINT2 (0x00040000UL) +#define USBFS_DAINT_OUTEPINT3_POS (19U) +#define USBFS_DAINT_OUTEPINT3 (0x00080000UL) +#define USBFS_DAINT_OUTEPINT4_POS (20U) +#define USBFS_DAINT_OUTEPINT4 (0x00100000UL) +#define USBFS_DAINT_OUTEPINT5_POS (21U) +#define USBFS_DAINT_OUTEPINT5 (0x00200000UL) +#define USBFS_DAINT_OUTEPINT6_POS (22U) +#define USBFS_DAINT_OUTEPINT6 (0x00400000UL) +#define USBFS_DAINT_OUTEPINT7_POS (23U) +#define USBFS_DAINT_OUTEPINT7 (0x00800000UL) +#define USBFS_DAINT_OUTEPINT8_POS (24U) +#define USBFS_DAINT_OUTEPINT8 (0x01000000UL) +#define USBFS_DAINT_OUTEPINT9_POS (25U) +#define USBFS_DAINT_OUTEPINT9 (0x02000000UL) +#define USBFS_DAINT_OUTEPINT10_POS (26U) +#define USBFS_DAINT_OUTEPINT10 (0x04000000UL) +#define USBFS_DAINT_OUTEPINT11_POS (27U) +#define USBFS_DAINT_OUTEPINT11 (0x08000000UL) +#define USBFS_DAINT_OUTEPINT12_POS (28U) +#define USBFS_DAINT_OUTEPINT12 (0x10000000UL) +#define USBFS_DAINT_OUTEPINT13_POS (29U) +#define USBFS_DAINT_OUTEPINT13 (0x20000000UL) +#define USBFS_DAINT_OUTEPINT14_POS (30U) +#define USBFS_DAINT_OUTEPINT14 (0x40000000UL) +#define USBFS_DAINT_OUTEPINT15_POS (31U) +#define USBFS_DAINT_OUTEPINT15 (0x80000000UL) + +/* Bit definition for USBFS_DAINTMSK register */ +#define USBFS_DAINTMSK_INEPMSK0_POS (0U) +#define USBFS_DAINTMSK_INEPMSK0 (0x00000001UL) +#define USBFS_DAINTMSK_INEPMSK1_POS (1U) +#define USBFS_DAINTMSK_INEPMSK1 (0x00000002UL) +#define USBFS_DAINTMSK_INEPMSK2_POS (2U) +#define USBFS_DAINTMSK_INEPMSK2 (0x00000004UL) +#define USBFS_DAINTMSK_INEPMSK3_POS (3U) +#define USBFS_DAINTMSK_INEPMSK3 (0x00000008UL) +#define USBFS_DAINTMSK_INEPMSK4_POS (4U) +#define USBFS_DAINTMSK_INEPMSK4 (0x00000010UL) +#define USBFS_DAINTMSK_INEPMSK5_POS (5U) +#define USBFS_DAINTMSK_INEPMSK5 (0x00000020UL) +#define USBFS_DAINTMSK_INEPMSK6_POS (6U) +#define USBFS_DAINTMSK_INEPMSK6 (0x00000040UL) +#define USBFS_DAINTMSK_INEPMSK7_POS (7U) +#define USBFS_DAINTMSK_INEPMSK7 (0x00000080UL) +#define USBFS_DAINTMSK_INEPMSK8_POS (8U) +#define USBFS_DAINTMSK_INEPMSK8 (0x00000100UL) +#define USBFS_DAINTMSK_INEPMSK9_POS (9U) +#define USBFS_DAINTMSK_INEPMSK9 (0x00000200UL) +#define USBFS_DAINTMSK_INEPMSK10_POS (10U) +#define USBFS_DAINTMSK_INEPMSK10 (0x00000400UL) +#define USBFS_DAINTMSK_INEPMSK11_POS (11U) +#define USBFS_DAINTMSK_INEPMSK11 (0x00000800UL) +#define USBFS_DAINTMSK_INEPMSK12_POS (12U) +#define USBFS_DAINTMSK_INEPMSK12 (0x00001000UL) +#define USBFS_DAINTMSK_INEPMSK13_POS (13U) +#define USBFS_DAINTMSK_INEPMSK13 (0x00002000UL) +#define USBFS_DAINTMSK_INEPMSK14_POS (14U) +#define USBFS_DAINTMSK_INEPMSK14 (0x00004000UL) +#define USBFS_DAINTMSK_INEPMSK15_POS (15U) +#define USBFS_DAINTMSK_INEPMSK15 (0x00008000UL) +#define USBFS_DAINTMSK_OUTEPMSK0_POS (16U) +#define USBFS_DAINTMSK_OUTEPMSK0 (0x00010000UL) +#define USBFS_DAINTMSK_OUTEPMSK1_POS (17U) +#define USBFS_DAINTMSK_OUTEPMSK1 (0x00020000UL) +#define USBFS_DAINTMSK_OUTEPMSK2_POS (18U) +#define USBFS_DAINTMSK_OUTEPMSK2 (0x00040000UL) +#define USBFS_DAINTMSK_OUTEPMSK3_POS (19U) +#define USBFS_DAINTMSK_OUTEPMSK3 (0x00080000UL) +#define USBFS_DAINTMSK_OUTEPMSK4_POS (20U) +#define USBFS_DAINTMSK_OUTEPMSK4 (0x00100000UL) +#define USBFS_DAINTMSK_OUTEPMSK5_POS (21U) +#define USBFS_DAINTMSK_OUTEPMSK5 (0x00200000UL) +#define USBFS_DAINTMSK_OUTEPMSK6_POS (22U) +#define USBFS_DAINTMSK_OUTEPMSK6 (0x00400000UL) +#define USBFS_DAINTMSK_OUTEPMSK7_POS (23U) +#define USBFS_DAINTMSK_OUTEPMSK7 (0x00800000UL) +#define USBFS_DAINTMSK_OUTEPMSK8_POS (24U) +#define USBFS_DAINTMSK_OUTEPMSK8 (0x01000000UL) +#define USBFS_DAINTMSK_OUTEPMSK9_POS (25U) +#define USBFS_DAINTMSK_OUTEPMSK9 (0x02000000UL) +#define USBFS_DAINTMSK_OUTEPMSK10_POS (26U) +#define USBFS_DAINTMSK_OUTEPMSK10 (0x04000000UL) +#define USBFS_DAINTMSK_OUTEPMSK11_POS (27U) +#define USBFS_DAINTMSK_OUTEPMSK11 (0x08000000UL) +#define USBFS_DAINTMSK_OUTEPMSK12_POS (28U) +#define USBFS_DAINTMSK_OUTEPMSK12 (0x10000000UL) +#define USBFS_DAINTMSK_OUTEPMSK13_POS (29U) +#define USBFS_DAINTMSK_OUTEPMSK13 (0x20000000UL) +#define USBFS_DAINTMSK_OUTEPMSK14_POS (30U) +#define USBFS_DAINTMSK_OUTEPMSK14 (0x40000000UL) +#define USBFS_DAINTMSK_OUTEPMSK15_POS (31U) +#define USBFS_DAINTMSK_OUTEPMSK15 (0x80000000UL) + +/* Bit definition for USBFS_DIEPEMPMSK register */ +#define USBFS_DIEPEMPMSK_INEPTXFEMPMSK (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL0 register */ +#define USBFS_DIEPCTL0_MPS_POS (0U) +#define USBFS_DIEPCTL0_MPS (0x00000003UL) +#define USBFS_DIEPCTL0_USBACTEP_POS (15U) +#define USBFS_DIEPCTL0_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL0_NAKSTS_POS (17U) +#define USBFS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL0_EPTYPE_POS (18U) +#define USBFS_DIEPCTL0_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL0_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL0_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL0_STALL_POS (21U) +#define USBFS_DIEPCTL0_STALL (0x00200000UL) +#define USBFS_DIEPCTL0_TXFNUM_POS (22U) +#define USBFS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL0_CNAK_POS (26U) +#define USBFS_DIEPCTL0_CNAK (0x04000000UL) +#define USBFS_DIEPCTL0_SNAK_POS (27U) +#define USBFS_DIEPCTL0_SNAK (0x08000000UL) +#define USBFS_DIEPCTL0_EPDIS_POS (30U) +#define USBFS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL0_EPENA_POS (31U) +#define USBFS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT0 register */ +#define USBFS_DIEPINT0_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT0_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT0_EPDISBLD_POS (1U) +#define USBFS_DIEPINT0_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT0_AHBERR_POS (2U) +#define USBFS_DIEPINT0_AHBERR (0x00000004UL) +#define USBFS_DIEPINT0_TIMEOUT_POS (3U) +#define USBFS_DIEPINT0_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT0_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT0_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT0_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT0_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT0_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT0_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT0_TXFEMP_POS (7U) +#define USBFS_DIEPINT0_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT0_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT0_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT0_BNAINTR_POS (9U) +#define USBFS_DIEPINT0_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT0_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT0_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT0_BBLEERR_POS (12U) +#define USBFS_DIEPINT0_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT0_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT0_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT0_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT0_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ0 register */ +#define USBFS_DIEPTSIZ0_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ0_XFERSIZE (0x0000007FUL) +#define USBFS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ0_PKTCNT (0x00180000UL) + +/* Bit definition for USBFS_DIEPDMA0 register */ +#define USBFS_DIEPDMA0 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS0 register */ +#define USBFS_DTXFSTS0_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL1 register */ +#define USBFS_DIEPCTL1_MPS_POS (0U) +#define USBFS_DIEPCTL1_MPS (0x000007FFUL) +#define USBFS_DIEPCTL1_USBACTEP_POS (15U) +#define USBFS_DIEPCTL1_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL1_DPID_POS (16U) +#define USBFS_DIEPCTL1_DPID (0x00010000UL) +#define USBFS_DIEPCTL1_NAKSTS_POS (17U) +#define USBFS_DIEPCTL1_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL1_EPTYPE_POS (18U) +#define USBFS_DIEPCTL1_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL1_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL1_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL1_STALL_POS (21U) +#define USBFS_DIEPCTL1_STALL (0x00200000UL) +#define USBFS_DIEPCTL1_TXFNUM_POS (22U) +#define USBFS_DIEPCTL1_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL1_CNAK_POS (26U) +#define USBFS_DIEPCTL1_CNAK (0x04000000UL) +#define USBFS_DIEPCTL1_SNAK_POS (27U) +#define USBFS_DIEPCTL1_SNAK (0x08000000UL) +#define USBFS_DIEPCTL1_SETD0PID_POS (28U) +#define USBFS_DIEPCTL1_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL1_SETD1PID_POS (29U) +#define USBFS_DIEPCTL1_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL1_EPDIS_POS (30U) +#define USBFS_DIEPCTL1_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL1_EPENA_POS (31U) +#define USBFS_DIEPCTL1_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT1 register */ +#define USBFS_DIEPINT1_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT1_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT1_EPDISBLD_POS (1U) +#define USBFS_DIEPINT1_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT1_AHBERR_POS (2U) +#define USBFS_DIEPINT1_AHBERR (0x00000004UL) +#define USBFS_DIEPINT1_TIMEOUT_POS (3U) +#define USBFS_DIEPINT1_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT1_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT1_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT1_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT1_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT1_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT1_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT1_TXFEMP_POS (7U) +#define USBFS_DIEPINT1_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT1_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT1_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT1_BNAINTR_POS (9U) +#define USBFS_DIEPINT1_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT1_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT1_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT1_BBLEERR_POS (12U) +#define USBFS_DIEPINT1_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT1_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT1_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT1_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT1_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ1 register */ +#define USBFS_DIEPTSIZ1_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ1_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ1_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ1_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ1_MC_POS (29U) +#define USBFS_DIEPTSIZ1_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA1 register */ +#define USBFS_DIEPDMA1 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS1 register */ +#define USBFS_DTXFSTS1_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL2 register */ +#define USBFS_DIEPCTL2_MPS_POS (0U) +#define USBFS_DIEPCTL2_MPS (0x000007FFUL) +#define USBFS_DIEPCTL2_USBACTEP_POS (15U) +#define USBFS_DIEPCTL2_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL2_DPID_POS (16U) +#define USBFS_DIEPCTL2_DPID (0x00010000UL) +#define USBFS_DIEPCTL2_NAKSTS_POS (17U) +#define USBFS_DIEPCTL2_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL2_EPTYPE_POS (18U) +#define USBFS_DIEPCTL2_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL2_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL2_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL2_STALL_POS (21U) +#define USBFS_DIEPCTL2_STALL (0x00200000UL) +#define USBFS_DIEPCTL2_TXFNUM_POS (22U) +#define USBFS_DIEPCTL2_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL2_CNAK_POS (26U) +#define USBFS_DIEPCTL2_CNAK (0x04000000UL) +#define USBFS_DIEPCTL2_SNAK_POS (27U) +#define USBFS_DIEPCTL2_SNAK (0x08000000UL) +#define USBFS_DIEPCTL2_SETD0PID_POS (28U) +#define USBFS_DIEPCTL2_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL2_SETD1PID_POS (29U) +#define USBFS_DIEPCTL2_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL2_EPDIS_POS (30U) +#define USBFS_DIEPCTL2_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL2_EPENA_POS (31U) +#define USBFS_DIEPCTL2_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT2 register */ +#define USBFS_DIEPINT2_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT2_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT2_EPDISBLD_POS (1U) +#define USBFS_DIEPINT2_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT2_AHBERR_POS (2U) +#define USBFS_DIEPINT2_AHBERR (0x00000004UL) +#define USBFS_DIEPINT2_TIMEOUT_POS (3U) +#define USBFS_DIEPINT2_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT2_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT2_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT2_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT2_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT2_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT2_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT2_TXFEMP_POS (7U) +#define USBFS_DIEPINT2_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT2_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT2_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT2_BNAINTR_POS (9U) +#define USBFS_DIEPINT2_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT2_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT2_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT2_BBLEERR_POS (12U) +#define USBFS_DIEPINT2_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT2_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT2_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT2_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT2_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ2 register */ +#define USBFS_DIEPTSIZ2_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ2_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ2_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ2_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ2_MC_POS (29U) +#define USBFS_DIEPTSIZ2_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA2 register */ +#define USBFS_DIEPDMA2 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS2 register */ +#define USBFS_DTXFSTS2_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL3 register */ +#define USBFS_DIEPCTL3_MPS_POS (0U) +#define USBFS_DIEPCTL3_MPS (0x000007FFUL) +#define USBFS_DIEPCTL3_USBACTEP_POS (15U) +#define USBFS_DIEPCTL3_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL3_DPID_POS (16U) +#define USBFS_DIEPCTL3_DPID (0x00010000UL) +#define USBFS_DIEPCTL3_NAKSTS_POS (17U) +#define USBFS_DIEPCTL3_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL3_EPTYPE_POS (18U) +#define USBFS_DIEPCTL3_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL3_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL3_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL3_STALL_POS (21U) +#define USBFS_DIEPCTL3_STALL (0x00200000UL) +#define USBFS_DIEPCTL3_TXFNUM_POS (22U) +#define USBFS_DIEPCTL3_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL3_CNAK_POS (26U) +#define USBFS_DIEPCTL3_CNAK (0x04000000UL) +#define USBFS_DIEPCTL3_SNAK_POS (27U) +#define USBFS_DIEPCTL3_SNAK (0x08000000UL) +#define USBFS_DIEPCTL3_SETD0PID_POS (28U) +#define USBFS_DIEPCTL3_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL3_SETD1PID_POS (29U) +#define USBFS_DIEPCTL3_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL3_EPDIS_POS (30U) +#define USBFS_DIEPCTL3_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL3_EPENA_POS (31U) +#define USBFS_DIEPCTL3_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT3 register */ +#define USBFS_DIEPINT3_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT3_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT3_EPDISBLD_POS (1U) +#define USBFS_DIEPINT3_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT3_AHBERR_POS (2U) +#define USBFS_DIEPINT3_AHBERR (0x00000004UL) +#define USBFS_DIEPINT3_TIMEOUT_POS (3U) +#define USBFS_DIEPINT3_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT3_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT3_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT3_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT3_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT3_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT3_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT3_TXFEMP_POS (7U) +#define USBFS_DIEPINT3_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT3_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT3_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT3_BNAINTR_POS (9U) +#define USBFS_DIEPINT3_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT3_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT3_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT3_BBLEERR_POS (12U) +#define USBFS_DIEPINT3_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT3_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT3_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT3_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT3_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ3 register */ +#define USBFS_DIEPTSIZ3_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ3_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ3_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ3_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ3_MC_POS (29U) +#define USBFS_DIEPTSIZ3_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA3 register */ +#define USBFS_DIEPDMA3 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS3 register */ +#define USBFS_DTXFSTS3_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL4 register */ +#define USBFS_DIEPCTL4_MPS_POS (0U) +#define USBFS_DIEPCTL4_MPS (0x000007FFUL) +#define USBFS_DIEPCTL4_USBACTEP_POS (15U) +#define USBFS_DIEPCTL4_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL4_DPID_POS (16U) +#define USBFS_DIEPCTL4_DPID (0x00010000UL) +#define USBFS_DIEPCTL4_NAKSTS_POS (17U) +#define USBFS_DIEPCTL4_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL4_EPTYPE_POS (18U) +#define USBFS_DIEPCTL4_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL4_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL4_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL4_STALL_POS (21U) +#define USBFS_DIEPCTL4_STALL (0x00200000UL) +#define USBFS_DIEPCTL4_TXFNUM_POS (22U) +#define USBFS_DIEPCTL4_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL4_CNAK_POS (26U) +#define USBFS_DIEPCTL4_CNAK (0x04000000UL) +#define USBFS_DIEPCTL4_SNAK_POS (27U) +#define USBFS_DIEPCTL4_SNAK (0x08000000UL) +#define USBFS_DIEPCTL4_SETD0PID_POS (28U) +#define USBFS_DIEPCTL4_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL4_SETD1PID_POS (29U) +#define USBFS_DIEPCTL4_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL4_EPDIS_POS (30U) +#define USBFS_DIEPCTL4_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL4_EPENA_POS (31U) +#define USBFS_DIEPCTL4_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT4 register */ +#define USBFS_DIEPINT4_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT4_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT4_EPDISBLD_POS (1U) +#define USBFS_DIEPINT4_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT4_AHBERR_POS (2U) +#define USBFS_DIEPINT4_AHBERR (0x00000004UL) +#define USBFS_DIEPINT4_TIMEOUT_POS (3U) +#define USBFS_DIEPINT4_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT4_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT4_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT4_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT4_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT4_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT4_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT4_TXFEMP_POS (7U) +#define USBFS_DIEPINT4_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT4_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT4_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT4_BNAINTR_POS (9U) +#define USBFS_DIEPINT4_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT4_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT4_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT4_BBLEERR_POS (12U) +#define USBFS_DIEPINT4_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT4_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT4_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT4_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT4_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ4 register */ +#define USBFS_DIEPTSIZ4_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ4_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ4_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ4_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ4_MC_POS (29U) +#define USBFS_DIEPTSIZ4_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA4 register */ +#define USBFS_DIEPDMA4 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS4 register */ +#define USBFS_DTXFSTS4_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL5 register */ +#define USBFS_DIEPCTL5_MPS_POS (0U) +#define USBFS_DIEPCTL5_MPS (0x000007FFUL) +#define USBFS_DIEPCTL5_USBACTEP_POS (15U) +#define USBFS_DIEPCTL5_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL5_DPID_POS (16U) +#define USBFS_DIEPCTL5_DPID (0x00010000UL) +#define USBFS_DIEPCTL5_NAKSTS_POS (17U) +#define USBFS_DIEPCTL5_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL5_EPTYPE_POS (18U) +#define USBFS_DIEPCTL5_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL5_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL5_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL5_STALL_POS (21U) +#define USBFS_DIEPCTL5_STALL (0x00200000UL) +#define USBFS_DIEPCTL5_TXFNUM_POS (22U) +#define USBFS_DIEPCTL5_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL5_CNAK_POS (26U) +#define USBFS_DIEPCTL5_CNAK (0x04000000UL) +#define USBFS_DIEPCTL5_SNAK_POS (27U) +#define USBFS_DIEPCTL5_SNAK (0x08000000UL) +#define USBFS_DIEPCTL5_SETD0PID_POS (28U) +#define USBFS_DIEPCTL5_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL5_SETD1PID_POS (29U) +#define USBFS_DIEPCTL5_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL5_EPDIS_POS (30U) +#define USBFS_DIEPCTL5_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL5_EPENA_POS (31U) +#define USBFS_DIEPCTL5_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT5 register */ +#define USBFS_DIEPINT5_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT5_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT5_EPDISBLD_POS (1U) +#define USBFS_DIEPINT5_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT5_AHBERR_POS (2U) +#define USBFS_DIEPINT5_AHBERR (0x00000004UL) +#define USBFS_DIEPINT5_TIMEOUT_POS (3U) +#define USBFS_DIEPINT5_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT5_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT5_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT5_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT5_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT5_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT5_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT5_TXFEMP_POS (7U) +#define USBFS_DIEPINT5_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT5_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT5_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT5_BNAINTR_POS (9U) +#define USBFS_DIEPINT5_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT5_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT5_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT5_BBLEERR_POS (12U) +#define USBFS_DIEPINT5_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT5_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT5_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT5_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT5_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ5 register */ +#define USBFS_DIEPTSIZ5_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ5_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ5_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ5_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ5_MC_POS (29U) +#define USBFS_DIEPTSIZ5_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA5 register */ +#define USBFS_DIEPDMA5 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS5 register */ +#define USBFS_DTXFSTS5_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL6 register */ +#define USBFS_DIEPCTL6_MPS_POS (0U) +#define USBFS_DIEPCTL6_MPS (0x000007FFUL) +#define USBFS_DIEPCTL6_USBACTEP_POS (15U) +#define USBFS_DIEPCTL6_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL6_DPID_POS (16U) +#define USBFS_DIEPCTL6_DPID (0x00010000UL) +#define USBFS_DIEPCTL6_NAKSTS_POS (17U) +#define USBFS_DIEPCTL6_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL6_EPTYPE_POS (18U) +#define USBFS_DIEPCTL6_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL6_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL6_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL6_STALL_POS (21U) +#define USBFS_DIEPCTL6_STALL (0x00200000UL) +#define USBFS_DIEPCTL6_TXFNUM_POS (22U) +#define USBFS_DIEPCTL6_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL6_CNAK_POS (26U) +#define USBFS_DIEPCTL6_CNAK (0x04000000UL) +#define USBFS_DIEPCTL6_SNAK_POS (27U) +#define USBFS_DIEPCTL6_SNAK (0x08000000UL) +#define USBFS_DIEPCTL6_SETD0PID_POS (28U) +#define USBFS_DIEPCTL6_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL6_SETD1PID_POS (29U) +#define USBFS_DIEPCTL6_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL6_EPDIS_POS (30U) +#define USBFS_DIEPCTL6_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL6_EPENA_POS (31U) +#define USBFS_DIEPCTL6_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT6 register */ +#define USBFS_DIEPINT6_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT6_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT6_EPDISBLD_POS (1U) +#define USBFS_DIEPINT6_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT6_AHBERR_POS (2U) +#define USBFS_DIEPINT6_AHBERR (0x00000004UL) +#define USBFS_DIEPINT6_TIMEOUT_POS (3U) +#define USBFS_DIEPINT6_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT6_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT6_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT6_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT6_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT6_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT6_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT6_TXFEMP_POS (7U) +#define USBFS_DIEPINT6_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT6_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT6_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT6_BNAINTR_POS (9U) +#define USBFS_DIEPINT6_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT6_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT6_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT6_BBLEERR_POS (12U) +#define USBFS_DIEPINT6_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT6_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT6_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT6_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT6_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ6 register */ +#define USBFS_DIEPTSIZ6_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ6_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ6_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ6_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ6_MC_POS (29U) +#define USBFS_DIEPTSIZ6_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA6 register */ +#define USBFS_DIEPDMA6 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS6 register */ +#define USBFS_DTXFSTS6_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL7 register */ +#define USBFS_DIEPCTL7_MPS_POS (0U) +#define USBFS_DIEPCTL7_MPS (0x000007FFUL) +#define USBFS_DIEPCTL7_USBACTEP_POS (15U) +#define USBFS_DIEPCTL7_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL7_DPID_POS (16U) +#define USBFS_DIEPCTL7_DPID (0x00010000UL) +#define USBFS_DIEPCTL7_NAKSTS_POS (17U) +#define USBFS_DIEPCTL7_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL7_EPTYPE_POS (18U) +#define USBFS_DIEPCTL7_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL7_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL7_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL7_STALL_POS (21U) +#define USBFS_DIEPCTL7_STALL (0x00200000UL) +#define USBFS_DIEPCTL7_TXFNUM_POS (22U) +#define USBFS_DIEPCTL7_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL7_CNAK_POS (26U) +#define USBFS_DIEPCTL7_CNAK (0x04000000UL) +#define USBFS_DIEPCTL7_SNAK_POS (27U) +#define USBFS_DIEPCTL7_SNAK (0x08000000UL) +#define USBFS_DIEPCTL7_SETD0PID_POS (28U) +#define USBFS_DIEPCTL7_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL7_SETD1PID_POS (29U) +#define USBFS_DIEPCTL7_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL7_EPDIS_POS (30U) +#define USBFS_DIEPCTL7_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL7_EPENA_POS (31U) +#define USBFS_DIEPCTL7_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT7 register */ +#define USBFS_DIEPINT7_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT7_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT7_EPDISBLD_POS (1U) +#define USBFS_DIEPINT7_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT7_AHBERR_POS (2U) +#define USBFS_DIEPINT7_AHBERR (0x00000004UL) +#define USBFS_DIEPINT7_TIMEOUT_POS (3U) +#define USBFS_DIEPINT7_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT7_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT7_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT7_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT7_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT7_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT7_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT7_TXFEMP_POS (7U) +#define USBFS_DIEPINT7_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT7_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT7_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT7_BNAINTR_POS (9U) +#define USBFS_DIEPINT7_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT7_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT7_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT7_BBLEERR_POS (12U) +#define USBFS_DIEPINT7_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT7_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT7_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT7_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT7_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ7 register */ +#define USBFS_DIEPTSIZ7_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ7_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ7_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ7_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ7_MC_POS (29U) +#define USBFS_DIEPTSIZ7_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA7 register */ +#define USBFS_DIEPDMA7 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS7 register */ +#define USBFS_DTXFSTS7_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL8 register */ +#define USBFS_DIEPCTL8_MPS_POS (0U) +#define USBFS_DIEPCTL8_MPS (0x000007FFUL) +#define USBFS_DIEPCTL8_USBACTEP_POS (15U) +#define USBFS_DIEPCTL8_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL8_DPID_POS (16U) +#define USBFS_DIEPCTL8_DPID (0x00010000UL) +#define USBFS_DIEPCTL8_NAKSTS_POS (17U) +#define USBFS_DIEPCTL8_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL8_EPTYPE_POS (18U) +#define USBFS_DIEPCTL8_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL8_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL8_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL8_STALL_POS (21U) +#define USBFS_DIEPCTL8_STALL (0x00200000UL) +#define USBFS_DIEPCTL8_TXFNUM_POS (22U) +#define USBFS_DIEPCTL8_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL8_CNAK_POS (26U) +#define USBFS_DIEPCTL8_CNAK (0x04000000UL) +#define USBFS_DIEPCTL8_SNAK_POS (27U) +#define USBFS_DIEPCTL8_SNAK (0x08000000UL) +#define USBFS_DIEPCTL8_SETD0PID_POS (28U) +#define USBFS_DIEPCTL8_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL8_SETD1PID_POS (29U) +#define USBFS_DIEPCTL8_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL8_EPDIS_POS (30U) +#define USBFS_DIEPCTL8_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL8_EPENA_POS (31U) +#define USBFS_DIEPCTL8_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT8 register */ +#define USBFS_DIEPINT8_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT8_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT8_EPDISBLD_POS (1U) +#define USBFS_DIEPINT8_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT8_AHBERR_POS (2U) +#define USBFS_DIEPINT8_AHBERR (0x00000004UL) +#define USBFS_DIEPINT8_TIMEOUT_POS (3U) +#define USBFS_DIEPINT8_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT8_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT8_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT8_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT8_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT8_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT8_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT8_TXFEMP_POS (7U) +#define USBFS_DIEPINT8_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT8_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT8_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT8_BNAINTR_POS (9U) +#define USBFS_DIEPINT8_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT8_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT8_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT8_BBLEERR_POS (12U) +#define USBFS_DIEPINT8_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT8_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT8_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT8_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT8_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ8 register */ +#define USBFS_DIEPTSIZ8_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ8_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ8_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ8_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ8_MC_POS (29U) +#define USBFS_DIEPTSIZ8_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA8 register */ +#define USBFS_DIEPDMA8 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS8 register */ +#define USBFS_DTXFSTS8_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL9 register */ +#define USBFS_DIEPCTL9_MPS_POS (0U) +#define USBFS_DIEPCTL9_MPS (0x000007FFUL) +#define USBFS_DIEPCTL9_USBACTEP_POS (15U) +#define USBFS_DIEPCTL9_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL9_DPID_POS (16U) +#define USBFS_DIEPCTL9_DPID (0x00010000UL) +#define USBFS_DIEPCTL9_NAKSTS_POS (17U) +#define USBFS_DIEPCTL9_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL9_EPTYPE_POS (18U) +#define USBFS_DIEPCTL9_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL9_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL9_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL9_STALL_POS (21U) +#define USBFS_DIEPCTL9_STALL (0x00200000UL) +#define USBFS_DIEPCTL9_TXFNUM_POS (22U) +#define USBFS_DIEPCTL9_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL9_CNAK_POS (26U) +#define USBFS_DIEPCTL9_CNAK (0x04000000UL) +#define USBFS_DIEPCTL9_SNAK_POS (27U) +#define USBFS_DIEPCTL9_SNAK (0x08000000UL) +#define USBFS_DIEPCTL9_SETD0PID_POS (28U) +#define USBFS_DIEPCTL9_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL9_SETD1PID_POS (29U) +#define USBFS_DIEPCTL9_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL9_EPDIS_POS (30U) +#define USBFS_DIEPCTL9_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL9_EPENA_POS (31U) +#define USBFS_DIEPCTL9_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT9 register */ +#define USBFS_DIEPINT9_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT9_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT9_EPDISBLD_POS (1U) +#define USBFS_DIEPINT9_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT9_AHBERR_POS (2U) +#define USBFS_DIEPINT9_AHBERR (0x00000004UL) +#define USBFS_DIEPINT9_TIMEOUT_POS (3U) +#define USBFS_DIEPINT9_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT9_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT9_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT9_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT9_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT9_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT9_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT9_TXFEMP_POS (7U) +#define USBFS_DIEPINT9_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT9_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT9_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT9_BNAINTR_POS (9U) +#define USBFS_DIEPINT9_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT9_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT9_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT9_BBLEERR_POS (12U) +#define USBFS_DIEPINT9_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT9_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT9_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT9_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT9_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ9 register */ +#define USBFS_DIEPTSIZ9_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ9_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ9_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ9_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ9_MC_POS (29U) +#define USBFS_DIEPTSIZ9_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA9 register */ +#define USBFS_DIEPDMA9 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS9 register */ +#define USBFS_DTXFSTS9_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL10 register */ +#define USBFS_DIEPCTL10_MPS_POS (0U) +#define USBFS_DIEPCTL10_MPS (0x000007FFUL) +#define USBFS_DIEPCTL10_USBACTEP_POS (15U) +#define USBFS_DIEPCTL10_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL10_DPID_POS (16U) +#define USBFS_DIEPCTL10_DPID (0x00010000UL) +#define USBFS_DIEPCTL10_NAKSTS_POS (17U) +#define USBFS_DIEPCTL10_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL10_EPTYPE_POS (18U) +#define USBFS_DIEPCTL10_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL10_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL10_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL10_STALL_POS (21U) +#define USBFS_DIEPCTL10_STALL (0x00200000UL) +#define USBFS_DIEPCTL10_TXFNUM_POS (22U) +#define USBFS_DIEPCTL10_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL10_CNAK_POS (26U) +#define USBFS_DIEPCTL10_CNAK (0x04000000UL) +#define USBFS_DIEPCTL10_SNAK_POS (27U) +#define USBFS_DIEPCTL10_SNAK (0x08000000UL) +#define USBFS_DIEPCTL10_SETD0PID_POS (28U) +#define USBFS_DIEPCTL10_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL10_SETD1PID_POS (29U) +#define USBFS_DIEPCTL10_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL10_EPDIS_POS (30U) +#define USBFS_DIEPCTL10_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL10_EPENA_POS (31U) +#define USBFS_DIEPCTL10_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT10 register */ +#define USBFS_DIEPINT10_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT10_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT10_EPDISBLD_POS (1U) +#define USBFS_DIEPINT10_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT10_AHBERR_POS (2U) +#define USBFS_DIEPINT10_AHBERR (0x00000004UL) +#define USBFS_DIEPINT10_TIMEOUT_POS (3U) +#define USBFS_DIEPINT10_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT10_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT10_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT10_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT10_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT10_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT10_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT10_TXFEMP_POS (7U) +#define USBFS_DIEPINT10_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT10_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT10_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT10_BNAINTR_POS (9U) +#define USBFS_DIEPINT10_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT10_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT10_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT10_BBLEERR_POS (12U) +#define USBFS_DIEPINT10_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT10_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT10_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT10_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT10_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ10 register */ +#define USBFS_DIEPTSIZ10_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ10_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ10_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ10_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ10_MC_POS (29U) +#define USBFS_DIEPTSIZ10_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA10 register */ +#define USBFS_DIEPDMA10 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS10 register */ +#define USBFS_DTXFSTS10_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL11 register */ +#define USBFS_DIEPCTL11_MPS_POS (0U) +#define USBFS_DIEPCTL11_MPS (0x000007FFUL) +#define USBFS_DIEPCTL11_USBACTEP_POS (15U) +#define USBFS_DIEPCTL11_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL11_DPID_POS (16U) +#define USBFS_DIEPCTL11_DPID (0x00010000UL) +#define USBFS_DIEPCTL11_NAKSTS_POS (17U) +#define USBFS_DIEPCTL11_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL11_EPTYPE_POS (18U) +#define USBFS_DIEPCTL11_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL11_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL11_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL11_STALL_POS (21U) +#define USBFS_DIEPCTL11_STALL (0x00200000UL) +#define USBFS_DIEPCTL11_TXFNUM_POS (22U) +#define USBFS_DIEPCTL11_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL11_CNAK_POS (26U) +#define USBFS_DIEPCTL11_CNAK (0x04000000UL) +#define USBFS_DIEPCTL11_SNAK_POS (27U) +#define USBFS_DIEPCTL11_SNAK (0x08000000UL) +#define USBFS_DIEPCTL11_SETD0PID_POS (28U) +#define USBFS_DIEPCTL11_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL11_SETD1PID_POS (29U) +#define USBFS_DIEPCTL11_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL11_EPDIS_POS (30U) +#define USBFS_DIEPCTL11_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL11_EPENA_POS (31U) +#define USBFS_DIEPCTL11_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT11 register */ +#define USBFS_DIEPINT11_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT11_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT11_EPDISBLD_POS (1U) +#define USBFS_DIEPINT11_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT11_AHBERR_POS (2U) +#define USBFS_DIEPINT11_AHBERR (0x00000004UL) +#define USBFS_DIEPINT11_TIMEOUT_POS (3U) +#define USBFS_DIEPINT11_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT11_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT11_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT11_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT11_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT11_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT11_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT11_TXFEMP_POS (7U) +#define USBFS_DIEPINT11_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT11_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT11_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT11_BNAINTR_POS (9U) +#define USBFS_DIEPINT11_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT11_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT11_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT11_BBLEERR_POS (12U) +#define USBFS_DIEPINT11_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT11_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT11_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT11_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT11_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ11 register */ +#define USBFS_DIEPTSIZ11_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ11_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ11_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ11_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ11_MC_POS (29U) +#define USBFS_DIEPTSIZ11_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA11 register */ +#define USBFS_DIEPDMA11 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS11 register */ +#define USBFS_DTXFSTS11_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL12 register */ +#define USBFS_DIEPCTL12_MPS_POS (0U) +#define USBFS_DIEPCTL12_MPS (0x000007FFUL) +#define USBFS_DIEPCTL12_USBACTEP_POS (15U) +#define USBFS_DIEPCTL12_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL12_DPID_POS (16U) +#define USBFS_DIEPCTL12_DPID (0x00010000UL) +#define USBFS_DIEPCTL12_NAKSTS_POS (17U) +#define USBFS_DIEPCTL12_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL12_EPTYPE_POS (18U) +#define USBFS_DIEPCTL12_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL12_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL12_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL12_STALL_POS (21U) +#define USBFS_DIEPCTL12_STALL (0x00200000UL) +#define USBFS_DIEPCTL12_TXFNUM_POS (22U) +#define USBFS_DIEPCTL12_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL12_CNAK_POS (26U) +#define USBFS_DIEPCTL12_CNAK (0x04000000UL) +#define USBFS_DIEPCTL12_SNAK_POS (27U) +#define USBFS_DIEPCTL12_SNAK (0x08000000UL) +#define USBFS_DIEPCTL12_SETD0PID_POS (28U) +#define USBFS_DIEPCTL12_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL12_SETD1PID_POS (29U) +#define USBFS_DIEPCTL12_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL12_EPDIS_POS (30U) +#define USBFS_DIEPCTL12_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL12_EPENA_POS (31U) +#define USBFS_DIEPCTL12_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT12 register */ +#define USBFS_DIEPINT12_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT12_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT12_EPDISBLD_POS (1U) +#define USBFS_DIEPINT12_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT12_AHBERR_POS (2U) +#define USBFS_DIEPINT12_AHBERR (0x00000004UL) +#define USBFS_DIEPINT12_TIMEOUT_POS (3U) +#define USBFS_DIEPINT12_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT12_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT12_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT12_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT12_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT12_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT12_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT12_TXFEMP_POS (7U) +#define USBFS_DIEPINT12_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT12_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT12_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT12_BNAINTR_POS (9U) +#define USBFS_DIEPINT12_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT12_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT12_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT12_BBLEERR_POS (12U) +#define USBFS_DIEPINT12_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT12_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT12_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT12_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT12_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ12 register */ +#define USBFS_DIEPTSIZ12_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ12_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ12_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ12_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ12_MC_POS (29U) +#define USBFS_DIEPTSIZ12_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA12 register */ +#define USBFS_DIEPDMA12 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS12 register */ +#define USBFS_DTXFSTS12_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL13 register */ +#define USBFS_DIEPCTL13_MPS_POS (0U) +#define USBFS_DIEPCTL13_MPS (0x000007FFUL) +#define USBFS_DIEPCTL13_USBACTEP_POS (15U) +#define USBFS_DIEPCTL13_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL13_DPID_POS (16U) +#define USBFS_DIEPCTL13_DPID (0x00010000UL) +#define USBFS_DIEPCTL13_NAKSTS_POS (17U) +#define USBFS_DIEPCTL13_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL13_EPTYPE_POS (18U) +#define USBFS_DIEPCTL13_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL13_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL13_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL13_STALL_POS (21U) +#define USBFS_DIEPCTL13_STALL (0x00200000UL) +#define USBFS_DIEPCTL13_TXFNUM_POS (22U) +#define USBFS_DIEPCTL13_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL13_CNAK_POS (26U) +#define USBFS_DIEPCTL13_CNAK (0x04000000UL) +#define USBFS_DIEPCTL13_SNAK_POS (27U) +#define USBFS_DIEPCTL13_SNAK (0x08000000UL) +#define USBFS_DIEPCTL13_SETD0PID_POS (28U) +#define USBFS_DIEPCTL13_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL13_SETD1PID_POS (29U) +#define USBFS_DIEPCTL13_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL13_EPDIS_POS (30U) +#define USBFS_DIEPCTL13_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL13_EPENA_POS (31U) +#define USBFS_DIEPCTL13_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT13 register */ +#define USBFS_DIEPINT13_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT13_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT13_EPDISBLD_POS (1U) +#define USBFS_DIEPINT13_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT13_AHBERR_POS (2U) +#define USBFS_DIEPINT13_AHBERR (0x00000004UL) +#define USBFS_DIEPINT13_TIMEOUT_POS (3U) +#define USBFS_DIEPINT13_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT13_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT13_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT13_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT13_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT13_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT13_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT13_TXFEMP_POS (7U) +#define USBFS_DIEPINT13_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT13_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT13_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT13_BNAINTR_POS (9U) +#define USBFS_DIEPINT13_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT13_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT13_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT13_BBLEERR_POS (12U) +#define USBFS_DIEPINT13_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT13_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT13_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT13_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT13_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ13 register */ +#define USBFS_DIEPTSIZ13_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ13_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ13_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ13_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ13_MC_POS (29U) +#define USBFS_DIEPTSIZ13_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA13 register */ +#define USBFS_DIEPDMA13 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS13 register */ +#define USBFS_DTXFSTS13_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL14 register */ +#define USBFS_DIEPCTL14_MPS_POS (0U) +#define USBFS_DIEPCTL14_MPS (0x000007FFUL) +#define USBFS_DIEPCTL14_USBACTEP_POS (15U) +#define USBFS_DIEPCTL14_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL14_DPID_POS (16U) +#define USBFS_DIEPCTL14_DPID (0x00010000UL) +#define USBFS_DIEPCTL14_NAKSTS_POS (17U) +#define USBFS_DIEPCTL14_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL14_EPTYPE_POS (18U) +#define USBFS_DIEPCTL14_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL14_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL14_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL14_STALL_POS (21U) +#define USBFS_DIEPCTL14_STALL (0x00200000UL) +#define USBFS_DIEPCTL14_TXFNUM_POS (22U) +#define USBFS_DIEPCTL14_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL14_CNAK_POS (26U) +#define USBFS_DIEPCTL14_CNAK (0x04000000UL) +#define USBFS_DIEPCTL14_SNAK_POS (27U) +#define USBFS_DIEPCTL14_SNAK (0x08000000UL) +#define USBFS_DIEPCTL14_SETD0PID_POS (28U) +#define USBFS_DIEPCTL14_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL14_SETD1PID_POS (29U) +#define USBFS_DIEPCTL14_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL14_EPDIS_POS (30U) +#define USBFS_DIEPCTL14_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL14_EPENA_POS (31U) +#define USBFS_DIEPCTL14_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT14 register */ +#define USBFS_DIEPINT14_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT14_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT14_EPDISBLD_POS (1U) +#define USBFS_DIEPINT14_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT14_AHBERR_POS (2U) +#define USBFS_DIEPINT14_AHBERR (0x00000004UL) +#define USBFS_DIEPINT14_TIMEOUT_POS (3U) +#define USBFS_DIEPINT14_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT14_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT14_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT14_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT14_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT14_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT14_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT14_TXFEMP_POS (7U) +#define USBFS_DIEPINT14_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT14_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT14_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT14_BNAINTR_POS (9U) +#define USBFS_DIEPINT14_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT14_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT14_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT14_BBLEERR_POS (12U) +#define USBFS_DIEPINT14_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT14_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT14_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT14_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT14_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ14 register */ +#define USBFS_DIEPTSIZ14_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ14_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ14_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ14_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ14_MC_POS (29U) +#define USBFS_DIEPTSIZ14_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA14 register */ +#define USBFS_DIEPDMA14 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS14 register */ +#define USBFS_DTXFSTS14_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DIEPCTL15 register */ +#define USBFS_DIEPCTL15_MPS_POS (0U) +#define USBFS_DIEPCTL15_MPS (0x000007FFUL) +#define USBFS_DIEPCTL15_USBACTEP_POS (15U) +#define USBFS_DIEPCTL15_USBACTEP (0x00008000UL) +#define USBFS_DIEPCTL15_DPID_POS (16U) +#define USBFS_DIEPCTL15_DPID (0x00010000UL) +#define USBFS_DIEPCTL15_NAKSTS_POS (17U) +#define USBFS_DIEPCTL15_NAKSTS (0x00020000UL) +#define USBFS_DIEPCTL15_EPTYPE_POS (18U) +#define USBFS_DIEPCTL15_EPTYPE (0x000C0000UL) +#define USBFS_DIEPCTL15_EPTYPE_0 (0x00040000UL) +#define USBFS_DIEPCTL15_EPTYPE_1 (0x00080000UL) +#define USBFS_DIEPCTL15_STALL_POS (21U) +#define USBFS_DIEPCTL15_STALL (0x00200000UL) +#define USBFS_DIEPCTL15_TXFNUM_POS (22U) +#define USBFS_DIEPCTL15_TXFNUM (0x03C00000UL) +#define USBFS_DIEPCTL15_CNAK_POS (26U) +#define USBFS_DIEPCTL15_CNAK (0x04000000UL) +#define USBFS_DIEPCTL15_SNAK_POS (27U) +#define USBFS_DIEPCTL15_SNAK (0x08000000UL) +#define USBFS_DIEPCTL15_SETD0PID_POS (28U) +#define USBFS_DIEPCTL15_SETD0PID (0x10000000UL) +#define USBFS_DIEPCTL15_SETD1PID_POS (29U) +#define USBFS_DIEPCTL15_SETD1PID (0x20000000UL) +#define USBFS_DIEPCTL15_EPDIS_POS (30U) +#define USBFS_DIEPCTL15_EPDIS (0x40000000UL) +#define USBFS_DIEPCTL15_EPENA_POS (31U) +#define USBFS_DIEPCTL15_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DIEPINT15 register */ +#define USBFS_DIEPINT15_XFERCOMPL_POS (0U) +#define USBFS_DIEPINT15_XFERCOMPL (0x00000001UL) +#define USBFS_DIEPINT15_EPDISBLD_POS (1U) +#define USBFS_DIEPINT15_EPDISBLD (0x00000002UL) +#define USBFS_DIEPINT15_AHBERR_POS (2U) +#define USBFS_DIEPINT15_AHBERR (0x00000004UL) +#define USBFS_DIEPINT15_TIMEOUT_POS (3U) +#define USBFS_DIEPINT15_TIMEOUT (0x00000008UL) +#define USBFS_DIEPINT15_INTKNTXFEMP_POS (4U) +#define USBFS_DIEPINT15_INTKNTXFEMP (0x00000010UL) +#define USBFS_DIEPINT15_INTKNEPMIS_POS (5U) +#define USBFS_DIEPINT15_INTKNEPMIS (0x00000020UL) +#define USBFS_DIEPINT15_INEPNAKEFF_POS (6U) +#define USBFS_DIEPINT15_INEPNAKEFF (0x00000040UL) +#define USBFS_DIEPINT15_TXFEMP_POS (7U) +#define USBFS_DIEPINT15_TXFEMP (0x00000080UL) +#define USBFS_DIEPINT15_TXFIFOUNDRN_POS (8U) +#define USBFS_DIEPINT15_TXFIFOUNDRN (0x00000100UL) +#define USBFS_DIEPINT15_BNAINTR_POS (9U) +#define USBFS_DIEPINT15_BNAINTR (0x00000200UL) +#define USBFS_DIEPINT15_PKTDRPSTS_POS (11U) +#define USBFS_DIEPINT15_PKTDRPSTS (0x00000800UL) +#define USBFS_DIEPINT15_BBLEERR_POS (12U) +#define USBFS_DIEPINT15_BBLEERR (0x00001000UL) +#define USBFS_DIEPINT15_NAKINTRPT_POS (13U) +#define USBFS_DIEPINT15_NAKINTRPT (0x00002000UL) +#define USBFS_DIEPINT15_NYETINTRPT_POS (14U) +#define USBFS_DIEPINT15_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBFS_DIEPTSIZ15 register */ +#define USBFS_DIEPTSIZ15_XFERSIZE_POS (0U) +#define USBFS_DIEPTSIZ15_XFERSIZE (0x0007FFFFUL) +#define USBFS_DIEPTSIZ15_PKTCNT_POS (19U) +#define USBFS_DIEPTSIZ15_PKTCNT (0x1FF80000UL) +#define USBFS_DIEPTSIZ15_MC_POS (29U) +#define USBFS_DIEPTSIZ15_MC (0x60000000UL) + +/* Bit definition for USBFS_DIEPDMA15 register */ +#define USBFS_DIEPDMA15 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DTXFSTS15 register */ +#define USBFS_DTXFSTS15_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBFS_DOEPCTL0 register */ +#define USBFS_DOEPCTL0_MPS_POS (0U) +#define USBFS_DOEPCTL0_MPS (0x00000003UL) +#define USBFS_DOEPCTL0_USBACTEP_POS (15U) +#define USBFS_DOEPCTL0_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL0_NAKSTS_POS (17U) +#define USBFS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL0_EPTYPE_POS (18U) +#define USBFS_DOEPCTL0_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL0_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL0_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL0_SNP_POS (20U) +#define USBFS_DOEPCTL0_SNP (0x00100000UL) +#define USBFS_DOEPCTL0_STALL_POS (21U) +#define USBFS_DOEPCTL0_STALL (0x00200000UL) +#define USBFS_DOEPCTL0_CNAK_POS (26U) +#define USBFS_DOEPCTL0_CNAK (0x04000000UL) +#define USBFS_DOEPCTL0_SNAK_POS (27U) +#define USBFS_DOEPCTL0_SNAK (0x08000000UL) +#define USBFS_DOEPCTL0_EPDIS_POS (30U) +#define USBFS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL0_EPENA_POS (31U) +#define USBFS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT0 register */ +#define USBFS_DOEPINT0_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT0_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT0_EPDISBLD_POS (1U) +#define USBFS_DOEPINT0_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT0_AHBERR_POS (2U) +#define USBFS_DOEPINT0_AHBERR (0x00000004UL) +#define USBFS_DOEPINT0_SETUP_POS (3U) +#define USBFS_DOEPINT0_SETUP (0x00000008UL) +#define USBFS_DOEPINT0_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT0_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT0_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT0_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT0_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT0_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT0_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT0_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT0_BNAINTR_POS (9U) +#define USBFS_DOEPINT0_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT0_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT0_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT0_BBLEERR_POS (12U) +#define USBFS_DOEPINT0_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT0_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT0_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT0_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT0_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT0_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT0_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ0 register */ +#define USBFS_DOEPTSIZ0_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ0_XFERSIZE (0x0000007FUL) +#define USBFS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ0_SUPCNT_POS (29U) +#define USBFS_DOEPTSIZ0_SUPCNT (0x60000000UL) + +/* Bit definition for USBFS_DOEPDMA0 register */ +#define USBFS_DOEPDMA0 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL1 register */ +#define USBFS_DOEPCTL1_MPS_POS (0U) +#define USBFS_DOEPCTL1_MPS (0x000007FFUL) +#define USBFS_DOEPCTL1_USBACTEP_POS (15U) +#define USBFS_DOEPCTL1_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL1_DPID_POS (16U) +#define USBFS_DOEPCTL1_DPID (0x00010000UL) +#define USBFS_DOEPCTL1_NAKSTS_POS (17U) +#define USBFS_DOEPCTL1_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL1_EPTYPE_POS (18U) +#define USBFS_DOEPCTL1_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL1_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL1_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL1_SNP_POS (20U) +#define USBFS_DOEPCTL1_SNP (0x00100000UL) +#define USBFS_DOEPCTL1_STALL_POS (21U) +#define USBFS_DOEPCTL1_STALL (0x00200000UL) +#define USBFS_DOEPCTL1_CNAK_POS (26U) +#define USBFS_DOEPCTL1_CNAK (0x04000000UL) +#define USBFS_DOEPCTL1_SNAK_POS (27U) +#define USBFS_DOEPCTL1_SNAK (0x08000000UL) +#define USBFS_DOEPCTL1_SETD0PID_POS (28U) +#define USBFS_DOEPCTL1_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL1_SETD1PID_POS (29U) +#define USBFS_DOEPCTL1_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL1_EPDIS_POS (30U) +#define USBFS_DOEPCTL1_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL1_EPENA_POS (31U) +#define USBFS_DOEPCTL1_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT1 register */ +#define USBFS_DOEPINT1_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT1_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT1_EPDISBLD_POS (1U) +#define USBFS_DOEPINT1_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT1_AHBERR_POS (2U) +#define USBFS_DOEPINT1_AHBERR (0x00000004UL) +#define USBFS_DOEPINT1_SETUP_POS (3U) +#define USBFS_DOEPINT1_SETUP (0x00000008UL) +#define USBFS_DOEPINT1_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT1_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT1_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT1_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT1_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT1_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT1_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT1_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT1_BNAINTR_POS (9U) +#define USBFS_DOEPINT1_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT1_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT1_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT1_BBLEERR_POS (12U) +#define USBFS_DOEPINT1_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT1_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT1_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT1_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT1_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT1_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT1_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ1 register */ +#define USBFS_DOEPTSIZ1_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ1_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ1_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ1_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ1_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ1_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ1_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ1_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA1 register */ +#define USBFS_DOEPDMA1 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL2 register */ +#define USBFS_DOEPCTL2_MPS_POS (0U) +#define USBFS_DOEPCTL2_MPS (0x000007FFUL) +#define USBFS_DOEPCTL2_USBACTEP_POS (15U) +#define USBFS_DOEPCTL2_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL2_DPID_POS (16U) +#define USBFS_DOEPCTL2_DPID (0x00010000UL) +#define USBFS_DOEPCTL2_NAKSTS_POS (17U) +#define USBFS_DOEPCTL2_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL2_EPTYPE_POS (18U) +#define USBFS_DOEPCTL2_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL2_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL2_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL2_SNP_POS (20U) +#define USBFS_DOEPCTL2_SNP (0x00100000UL) +#define USBFS_DOEPCTL2_STALL_POS (21U) +#define USBFS_DOEPCTL2_STALL (0x00200000UL) +#define USBFS_DOEPCTL2_CNAK_POS (26U) +#define USBFS_DOEPCTL2_CNAK (0x04000000UL) +#define USBFS_DOEPCTL2_SNAK_POS (27U) +#define USBFS_DOEPCTL2_SNAK (0x08000000UL) +#define USBFS_DOEPCTL2_SETD0PID_POS (28U) +#define USBFS_DOEPCTL2_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL2_SETD1PID_POS (29U) +#define USBFS_DOEPCTL2_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL2_EPDIS_POS (30U) +#define USBFS_DOEPCTL2_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL2_EPENA_POS (31U) +#define USBFS_DOEPCTL2_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT2 register */ +#define USBFS_DOEPINT2_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT2_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT2_EPDISBLD_POS (1U) +#define USBFS_DOEPINT2_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT2_AHBERR_POS (2U) +#define USBFS_DOEPINT2_AHBERR (0x00000004UL) +#define USBFS_DOEPINT2_SETUP_POS (3U) +#define USBFS_DOEPINT2_SETUP (0x00000008UL) +#define USBFS_DOEPINT2_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT2_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT2_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT2_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT2_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT2_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT2_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT2_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT2_BNAINTR_POS (9U) +#define USBFS_DOEPINT2_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT2_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT2_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT2_BBLEERR_POS (12U) +#define USBFS_DOEPINT2_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT2_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT2_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT2_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT2_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT2_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT2_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ2 register */ +#define USBFS_DOEPTSIZ2_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ2_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ2_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ2_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ2_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ2_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ2_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ2_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA2 register */ +#define USBFS_DOEPDMA2 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL3 register */ +#define USBFS_DOEPCTL3_MPS_POS (0U) +#define USBFS_DOEPCTL3_MPS (0x000007FFUL) +#define USBFS_DOEPCTL3_USBACTEP_POS (15U) +#define USBFS_DOEPCTL3_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL3_DPID_POS (16U) +#define USBFS_DOEPCTL3_DPID (0x00010000UL) +#define USBFS_DOEPCTL3_NAKSTS_POS (17U) +#define USBFS_DOEPCTL3_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL3_EPTYPE_POS (18U) +#define USBFS_DOEPCTL3_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL3_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL3_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL3_SNP_POS (20U) +#define USBFS_DOEPCTL3_SNP (0x00100000UL) +#define USBFS_DOEPCTL3_STALL_POS (21U) +#define USBFS_DOEPCTL3_STALL (0x00200000UL) +#define USBFS_DOEPCTL3_CNAK_POS (26U) +#define USBFS_DOEPCTL3_CNAK (0x04000000UL) +#define USBFS_DOEPCTL3_SNAK_POS (27U) +#define USBFS_DOEPCTL3_SNAK (0x08000000UL) +#define USBFS_DOEPCTL3_SETD0PID_POS (28U) +#define USBFS_DOEPCTL3_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL3_SETD1PID_POS (29U) +#define USBFS_DOEPCTL3_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL3_EPDIS_POS (30U) +#define USBFS_DOEPCTL3_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL3_EPENA_POS (31U) +#define USBFS_DOEPCTL3_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT3 register */ +#define USBFS_DOEPINT3_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT3_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT3_EPDISBLD_POS (1U) +#define USBFS_DOEPINT3_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT3_AHBERR_POS (2U) +#define USBFS_DOEPINT3_AHBERR (0x00000004UL) +#define USBFS_DOEPINT3_SETUP_POS (3U) +#define USBFS_DOEPINT3_SETUP (0x00000008UL) +#define USBFS_DOEPINT3_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT3_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT3_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT3_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT3_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT3_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT3_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT3_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT3_BNAINTR_POS (9U) +#define USBFS_DOEPINT3_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT3_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT3_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT3_BBLEERR_POS (12U) +#define USBFS_DOEPINT3_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT3_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT3_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT3_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT3_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT3_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT3_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ3 register */ +#define USBFS_DOEPTSIZ3_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ3_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ3_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ3_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ3_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ3_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ3_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ3_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA3 register */ +#define USBFS_DOEPDMA3 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL4 register */ +#define USBFS_DOEPCTL4_MPS_POS (0U) +#define USBFS_DOEPCTL4_MPS (0x000007FFUL) +#define USBFS_DOEPCTL4_USBACTEP_POS (15U) +#define USBFS_DOEPCTL4_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL4_DPID_POS (16U) +#define USBFS_DOEPCTL4_DPID (0x00010000UL) +#define USBFS_DOEPCTL4_NAKSTS_POS (17U) +#define USBFS_DOEPCTL4_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL4_EPTYPE_POS (18U) +#define USBFS_DOEPCTL4_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL4_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL4_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL4_SNP_POS (20U) +#define USBFS_DOEPCTL4_SNP (0x00100000UL) +#define USBFS_DOEPCTL4_STALL_POS (21U) +#define USBFS_DOEPCTL4_STALL (0x00200000UL) +#define USBFS_DOEPCTL4_CNAK_POS (26U) +#define USBFS_DOEPCTL4_CNAK (0x04000000UL) +#define USBFS_DOEPCTL4_SNAK_POS (27U) +#define USBFS_DOEPCTL4_SNAK (0x08000000UL) +#define USBFS_DOEPCTL4_SETD0PID_POS (28U) +#define USBFS_DOEPCTL4_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL4_SETD1PID_POS (29U) +#define USBFS_DOEPCTL4_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL4_EPDIS_POS (30U) +#define USBFS_DOEPCTL4_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL4_EPENA_POS (31U) +#define USBFS_DOEPCTL4_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT4 register */ +#define USBFS_DOEPINT4_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT4_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT4_EPDISBLD_POS (1U) +#define USBFS_DOEPINT4_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT4_AHBERR_POS (2U) +#define USBFS_DOEPINT4_AHBERR (0x00000004UL) +#define USBFS_DOEPINT4_SETUP_POS (3U) +#define USBFS_DOEPINT4_SETUP (0x00000008UL) +#define USBFS_DOEPINT4_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT4_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT4_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT4_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT4_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT4_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT4_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT4_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT4_BNAINTR_POS (9U) +#define USBFS_DOEPINT4_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT4_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT4_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT4_BBLEERR_POS (12U) +#define USBFS_DOEPINT4_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT4_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT4_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT4_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT4_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT4_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT4_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ4 register */ +#define USBFS_DOEPTSIZ4_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ4_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ4_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ4_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ4_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ4_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ4_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ4_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA4 register */ +#define USBFS_DOEPDMA4 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL5 register */ +#define USBFS_DOEPCTL5_MPS_POS (0U) +#define USBFS_DOEPCTL5_MPS (0x000007FFUL) +#define USBFS_DOEPCTL5_USBACTEP_POS (15U) +#define USBFS_DOEPCTL5_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL5_DPID_POS (16U) +#define USBFS_DOEPCTL5_DPID (0x00010000UL) +#define USBFS_DOEPCTL5_NAKSTS_POS (17U) +#define USBFS_DOEPCTL5_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL5_EPTYPE_POS (18U) +#define USBFS_DOEPCTL5_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL5_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL5_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL5_SNP_POS (20U) +#define USBFS_DOEPCTL5_SNP (0x00100000UL) +#define USBFS_DOEPCTL5_STALL_POS (21U) +#define USBFS_DOEPCTL5_STALL (0x00200000UL) +#define USBFS_DOEPCTL5_CNAK_POS (26U) +#define USBFS_DOEPCTL5_CNAK (0x04000000UL) +#define USBFS_DOEPCTL5_SNAK_POS (27U) +#define USBFS_DOEPCTL5_SNAK (0x08000000UL) +#define USBFS_DOEPCTL5_SETD0PID_POS (28U) +#define USBFS_DOEPCTL5_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL5_SETD1PID_POS (29U) +#define USBFS_DOEPCTL5_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL5_EPDIS_POS (30U) +#define USBFS_DOEPCTL5_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL5_EPENA_POS (31U) +#define USBFS_DOEPCTL5_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT5 register */ +#define USBFS_DOEPINT5_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT5_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT5_EPDISBLD_POS (1U) +#define USBFS_DOEPINT5_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT5_AHBERR_POS (2U) +#define USBFS_DOEPINT5_AHBERR (0x00000004UL) +#define USBFS_DOEPINT5_SETUP_POS (3U) +#define USBFS_DOEPINT5_SETUP (0x00000008UL) +#define USBFS_DOEPINT5_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT5_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT5_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT5_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT5_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT5_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT5_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT5_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT5_BNAINTR_POS (9U) +#define USBFS_DOEPINT5_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT5_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT5_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT5_BBLEERR_POS (12U) +#define USBFS_DOEPINT5_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT5_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT5_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT5_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT5_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT5_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT5_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ5 register */ +#define USBFS_DOEPTSIZ5_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ5_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ5_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ5_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ5_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ5_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ5_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ5_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA5 register */ +#define USBFS_DOEPDMA5 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL6 register */ +#define USBFS_DOEPCTL6_MPS_POS (0U) +#define USBFS_DOEPCTL6_MPS (0x000007FFUL) +#define USBFS_DOEPCTL6_USBACTEP_POS (15U) +#define USBFS_DOEPCTL6_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL6_DPID_POS (16U) +#define USBFS_DOEPCTL6_DPID (0x00010000UL) +#define USBFS_DOEPCTL6_NAKSTS_POS (17U) +#define USBFS_DOEPCTL6_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL6_EPTYPE_POS (18U) +#define USBFS_DOEPCTL6_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL6_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL6_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL6_SNP_POS (20U) +#define USBFS_DOEPCTL6_SNP (0x00100000UL) +#define USBFS_DOEPCTL6_STALL_POS (21U) +#define USBFS_DOEPCTL6_STALL (0x00200000UL) +#define USBFS_DOEPCTL6_CNAK_POS (26U) +#define USBFS_DOEPCTL6_CNAK (0x04000000UL) +#define USBFS_DOEPCTL6_SNAK_POS (27U) +#define USBFS_DOEPCTL6_SNAK (0x08000000UL) +#define USBFS_DOEPCTL6_SETD0PID_POS (28U) +#define USBFS_DOEPCTL6_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL6_SETD1PID_POS (29U) +#define USBFS_DOEPCTL6_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL6_EPDIS_POS (30U) +#define USBFS_DOEPCTL6_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL6_EPENA_POS (31U) +#define USBFS_DOEPCTL6_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT6 register */ +#define USBFS_DOEPINT6_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT6_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT6_EPDISBLD_POS (1U) +#define USBFS_DOEPINT6_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT6_AHBERR_POS (2U) +#define USBFS_DOEPINT6_AHBERR (0x00000004UL) +#define USBFS_DOEPINT6_SETUP_POS (3U) +#define USBFS_DOEPINT6_SETUP (0x00000008UL) +#define USBFS_DOEPINT6_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT6_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT6_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT6_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT6_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT6_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT6_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT6_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT6_BNAINTR_POS (9U) +#define USBFS_DOEPINT6_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT6_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT6_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT6_BBLEERR_POS (12U) +#define USBFS_DOEPINT6_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT6_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT6_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT6_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT6_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT6_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT6_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ6 register */ +#define USBFS_DOEPTSIZ6_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ6_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ6_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ6_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ6_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ6_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ6_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ6_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA6 register */ +#define USBFS_DOEPDMA6 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL7 register */ +#define USBFS_DOEPCTL7_MPS_POS (0U) +#define USBFS_DOEPCTL7_MPS (0x000007FFUL) +#define USBFS_DOEPCTL7_USBACTEP_POS (15U) +#define USBFS_DOEPCTL7_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL7_DPID_POS (16U) +#define USBFS_DOEPCTL7_DPID (0x00010000UL) +#define USBFS_DOEPCTL7_NAKSTS_POS (17U) +#define USBFS_DOEPCTL7_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL7_EPTYPE_POS (18U) +#define USBFS_DOEPCTL7_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL7_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL7_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL7_SNP_POS (20U) +#define USBFS_DOEPCTL7_SNP (0x00100000UL) +#define USBFS_DOEPCTL7_STALL_POS (21U) +#define USBFS_DOEPCTL7_STALL (0x00200000UL) +#define USBFS_DOEPCTL7_CNAK_POS (26U) +#define USBFS_DOEPCTL7_CNAK (0x04000000UL) +#define USBFS_DOEPCTL7_SNAK_POS (27U) +#define USBFS_DOEPCTL7_SNAK (0x08000000UL) +#define USBFS_DOEPCTL7_SETD0PID_POS (28U) +#define USBFS_DOEPCTL7_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL7_SETD1PID_POS (29U) +#define USBFS_DOEPCTL7_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL7_EPDIS_POS (30U) +#define USBFS_DOEPCTL7_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL7_EPENA_POS (31U) +#define USBFS_DOEPCTL7_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT7 register */ +#define USBFS_DOEPINT7_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT7_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT7_EPDISBLD_POS (1U) +#define USBFS_DOEPINT7_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT7_AHBERR_POS (2U) +#define USBFS_DOEPINT7_AHBERR (0x00000004UL) +#define USBFS_DOEPINT7_SETUP_POS (3U) +#define USBFS_DOEPINT7_SETUP (0x00000008UL) +#define USBFS_DOEPINT7_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT7_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT7_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT7_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT7_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT7_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT7_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT7_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT7_BNAINTR_POS (9U) +#define USBFS_DOEPINT7_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT7_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT7_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT7_BBLEERR_POS (12U) +#define USBFS_DOEPINT7_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT7_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT7_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT7_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT7_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT7_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT7_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ7 register */ +#define USBFS_DOEPTSIZ7_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ7_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ7_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ7_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ7_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ7_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ7_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ7_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA7 register */ +#define USBFS_DOEPDMA7 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL8 register */ +#define USBFS_DOEPCTL8_MPS_POS (0U) +#define USBFS_DOEPCTL8_MPS (0x000007FFUL) +#define USBFS_DOEPCTL8_USBACTEP_POS (15U) +#define USBFS_DOEPCTL8_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL8_DPID_POS (16U) +#define USBFS_DOEPCTL8_DPID (0x00010000UL) +#define USBFS_DOEPCTL8_NAKSTS_POS (17U) +#define USBFS_DOEPCTL8_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL8_EPTYPE_POS (18U) +#define USBFS_DOEPCTL8_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL8_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL8_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL8_SNP_POS (20U) +#define USBFS_DOEPCTL8_SNP (0x00100000UL) +#define USBFS_DOEPCTL8_STALL_POS (21U) +#define USBFS_DOEPCTL8_STALL (0x00200000UL) +#define USBFS_DOEPCTL8_CNAK_POS (26U) +#define USBFS_DOEPCTL8_CNAK (0x04000000UL) +#define USBFS_DOEPCTL8_SNAK_POS (27U) +#define USBFS_DOEPCTL8_SNAK (0x08000000UL) +#define USBFS_DOEPCTL8_SETD0PID_POS (28U) +#define USBFS_DOEPCTL8_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL8_SETD1PID_POS (29U) +#define USBFS_DOEPCTL8_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL8_EPDIS_POS (30U) +#define USBFS_DOEPCTL8_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL8_EPENA_POS (31U) +#define USBFS_DOEPCTL8_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT8 register */ +#define USBFS_DOEPINT8_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT8_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT8_EPDISBLD_POS (1U) +#define USBFS_DOEPINT8_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT8_AHBERR_POS (2U) +#define USBFS_DOEPINT8_AHBERR (0x00000004UL) +#define USBFS_DOEPINT8_SETUP_POS (3U) +#define USBFS_DOEPINT8_SETUP (0x00000008UL) +#define USBFS_DOEPINT8_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT8_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT8_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT8_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT8_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT8_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT8_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT8_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT8_BNAINTR_POS (9U) +#define USBFS_DOEPINT8_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT8_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT8_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT8_BBLEERR_POS (12U) +#define USBFS_DOEPINT8_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT8_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT8_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT8_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT8_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT8_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT8_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ8 register */ +#define USBFS_DOEPTSIZ8_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ8_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ8_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ8_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ8_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ8_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ8_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ8_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA8 register */ +#define USBFS_DOEPDMA8 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL9 register */ +#define USBFS_DOEPCTL9_MPS_POS (0U) +#define USBFS_DOEPCTL9_MPS (0x000007FFUL) +#define USBFS_DOEPCTL9_USBACTEP_POS (15U) +#define USBFS_DOEPCTL9_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL9_DPID_POS (16U) +#define USBFS_DOEPCTL9_DPID (0x00010000UL) +#define USBFS_DOEPCTL9_NAKSTS_POS (17U) +#define USBFS_DOEPCTL9_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL9_EPTYPE_POS (18U) +#define USBFS_DOEPCTL9_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL9_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL9_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL9_SNP_POS (20U) +#define USBFS_DOEPCTL9_SNP (0x00100000UL) +#define USBFS_DOEPCTL9_STALL_POS (21U) +#define USBFS_DOEPCTL9_STALL (0x00200000UL) +#define USBFS_DOEPCTL9_CNAK_POS (26U) +#define USBFS_DOEPCTL9_CNAK (0x04000000UL) +#define USBFS_DOEPCTL9_SNAK_POS (27U) +#define USBFS_DOEPCTL9_SNAK (0x08000000UL) +#define USBFS_DOEPCTL9_SETD0PID_POS (28U) +#define USBFS_DOEPCTL9_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL9_SETD1PID_POS (29U) +#define USBFS_DOEPCTL9_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL9_EPDIS_POS (30U) +#define USBFS_DOEPCTL9_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL9_EPENA_POS (31U) +#define USBFS_DOEPCTL9_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT9 register */ +#define USBFS_DOEPINT9_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT9_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT9_EPDISBLD_POS (1U) +#define USBFS_DOEPINT9_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT9_AHBERR_POS (2U) +#define USBFS_DOEPINT9_AHBERR (0x00000004UL) +#define USBFS_DOEPINT9_SETUP_POS (3U) +#define USBFS_DOEPINT9_SETUP (0x00000008UL) +#define USBFS_DOEPINT9_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT9_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT9_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT9_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT9_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT9_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT9_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT9_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT9_BNAINTR_POS (9U) +#define USBFS_DOEPINT9_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT9_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT9_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT9_BBLEERR_POS (12U) +#define USBFS_DOEPINT9_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT9_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT9_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT9_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT9_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT9_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT9_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ9 register */ +#define USBFS_DOEPTSIZ9_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ9_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ9_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ9_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ9_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ9_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ9_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ9_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA9 register */ +#define USBFS_DOEPDMA9 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL10 register */ +#define USBFS_DOEPCTL10_MPS_POS (0U) +#define USBFS_DOEPCTL10_MPS (0x000007FFUL) +#define USBFS_DOEPCTL10_USBACTEP_POS (15U) +#define USBFS_DOEPCTL10_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL10_DPID_POS (16U) +#define USBFS_DOEPCTL10_DPID (0x00010000UL) +#define USBFS_DOEPCTL10_NAKSTS_POS (17U) +#define USBFS_DOEPCTL10_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL10_EPTYPE_POS (18U) +#define USBFS_DOEPCTL10_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL10_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL10_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL10_SNP_POS (20U) +#define USBFS_DOEPCTL10_SNP (0x00100000UL) +#define USBFS_DOEPCTL10_STALL_POS (21U) +#define USBFS_DOEPCTL10_STALL (0x00200000UL) +#define USBFS_DOEPCTL10_CNAK_POS (26U) +#define USBFS_DOEPCTL10_CNAK (0x04000000UL) +#define USBFS_DOEPCTL10_SNAK_POS (27U) +#define USBFS_DOEPCTL10_SNAK (0x08000000UL) +#define USBFS_DOEPCTL10_SETD0PID_POS (28U) +#define USBFS_DOEPCTL10_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL10_SETD1PID_POS (29U) +#define USBFS_DOEPCTL10_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL10_EPDIS_POS (30U) +#define USBFS_DOEPCTL10_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL10_EPENA_POS (31U) +#define USBFS_DOEPCTL10_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT10 register */ +#define USBFS_DOEPINT10_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT10_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT10_EPDISBLD_POS (1U) +#define USBFS_DOEPINT10_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT10_AHBERR_POS (2U) +#define USBFS_DOEPINT10_AHBERR (0x00000004UL) +#define USBFS_DOEPINT10_SETUP_POS (3U) +#define USBFS_DOEPINT10_SETUP (0x00000008UL) +#define USBFS_DOEPINT10_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT10_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT10_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT10_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT10_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT10_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT10_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT10_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT10_BNAINTR_POS (9U) +#define USBFS_DOEPINT10_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT10_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT10_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT10_BBLEERR_POS (12U) +#define USBFS_DOEPINT10_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT10_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT10_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT10_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT10_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT10_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT10_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ10 register */ +#define USBFS_DOEPTSIZ10_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ10_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ10_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ10_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ10_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ10_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ10_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ10_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA10 register */ +#define USBFS_DOEPDMA10 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL11 register */ +#define USBFS_DOEPCTL11_MPS_POS (0U) +#define USBFS_DOEPCTL11_MPS (0x000007FFUL) +#define USBFS_DOEPCTL11_USBACTEP_POS (15U) +#define USBFS_DOEPCTL11_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL11_DPID_POS (16U) +#define USBFS_DOEPCTL11_DPID (0x00010000UL) +#define USBFS_DOEPCTL11_NAKSTS_POS (17U) +#define USBFS_DOEPCTL11_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL11_EPTYPE_POS (18U) +#define USBFS_DOEPCTL11_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL11_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL11_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL11_SNP_POS (20U) +#define USBFS_DOEPCTL11_SNP (0x00100000UL) +#define USBFS_DOEPCTL11_STALL_POS (21U) +#define USBFS_DOEPCTL11_STALL (0x00200000UL) +#define USBFS_DOEPCTL11_CNAK_POS (26U) +#define USBFS_DOEPCTL11_CNAK (0x04000000UL) +#define USBFS_DOEPCTL11_SNAK_POS (27U) +#define USBFS_DOEPCTL11_SNAK (0x08000000UL) +#define USBFS_DOEPCTL11_SETD0PID_POS (28U) +#define USBFS_DOEPCTL11_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL11_SETD1PID_POS (29U) +#define USBFS_DOEPCTL11_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL11_EPDIS_POS (30U) +#define USBFS_DOEPCTL11_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL11_EPENA_POS (31U) +#define USBFS_DOEPCTL11_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT11 register */ +#define USBFS_DOEPINT11_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT11_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT11_EPDISBLD_POS (1U) +#define USBFS_DOEPINT11_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT11_AHBERR_POS (2U) +#define USBFS_DOEPINT11_AHBERR (0x00000004UL) +#define USBFS_DOEPINT11_SETUP_POS (3U) +#define USBFS_DOEPINT11_SETUP (0x00000008UL) +#define USBFS_DOEPINT11_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT11_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT11_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT11_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT11_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT11_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT11_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT11_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT11_BNAINTR_POS (9U) +#define USBFS_DOEPINT11_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT11_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT11_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT11_BBLEERR_POS (12U) +#define USBFS_DOEPINT11_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT11_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT11_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT11_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT11_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT11_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT11_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ11 register */ +#define USBFS_DOEPTSIZ11_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ11_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ11_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ11_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ11_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ11_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ11_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ11_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA11 register */ +#define USBFS_DOEPDMA11 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL12 register */ +#define USBFS_DOEPCTL12_MPS_POS (0U) +#define USBFS_DOEPCTL12_MPS (0x000007FFUL) +#define USBFS_DOEPCTL12_USBACTEP_POS (15U) +#define USBFS_DOEPCTL12_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL12_DPID_POS (16U) +#define USBFS_DOEPCTL12_DPID (0x00010000UL) +#define USBFS_DOEPCTL12_NAKSTS_POS (17U) +#define USBFS_DOEPCTL12_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL12_EPTYPE_POS (18U) +#define USBFS_DOEPCTL12_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL12_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL12_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL12_SNP_POS (20U) +#define USBFS_DOEPCTL12_SNP (0x00100000UL) +#define USBFS_DOEPCTL12_STALL_POS (21U) +#define USBFS_DOEPCTL12_STALL (0x00200000UL) +#define USBFS_DOEPCTL12_CNAK_POS (26U) +#define USBFS_DOEPCTL12_CNAK (0x04000000UL) +#define USBFS_DOEPCTL12_SNAK_POS (27U) +#define USBFS_DOEPCTL12_SNAK (0x08000000UL) +#define USBFS_DOEPCTL12_SETD0PID_POS (28U) +#define USBFS_DOEPCTL12_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL12_SETD1PID_POS (29U) +#define USBFS_DOEPCTL12_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL12_EPDIS_POS (30U) +#define USBFS_DOEPCTL12_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL12_EPENA_POS (31U) +#define USBFS_DOEPCTL12_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT12 register */ +#define USBFS_DOEPINT12_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT12_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT12_EPDISBLD_POS (1U) +#define USBFS_DOEPINT12_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT12_AHBERR_POS (2U) +#define USBFS_DOEPINT12_AHBERR (0x00000004UL) +#define USBFS_DOEPINT12_SETUP_POS (3U) +#define USBFS_DOEPINT12_SETUP (0x00000008UL) +#define USBFS_DOEPINT12_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT12_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT12_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT12_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT12_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT12_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT12_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT12_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT12_BNAINTR_POS (9U) +#define USBFS_DOEPINT12_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT12_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT12_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT12_BBLEERR_POS (12U) +#define USBFS_DOEPINT12_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT12_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT12_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT12_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT12_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT12_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT12_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ12 register */ +#define USBFS_DOEPTSIZ12_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ12_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ12_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ12_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ12_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ12_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ12_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ12_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA12 register */ +#define USBFS_DOEPDMA12 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL13 register */ +#define USBFS_DOEPCTL13_MPS_POS (0U) +#define USBFS_DOEPCTL13_MPS (0x000007FFUL) +#define USBFS_DOEPCTL13_USBACTEP_POS (15U) +#define USBFS_DOEPCTL13_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL13_DPID_POS (16U) +#define USBFS_DOEPCTL13_DPID (0x00010000UL) +#define USBFS_DOEPCTL13_NAKSTS_POS (17U) +#define USBFS_DOEPCTL13_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL13_EPTYPE_POS (18U) +#define USBFS_DOEPCTL13_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL13_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL13_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL13_SNP_POS (20U) +#define USBFS_DOEPCTL13_SNP (0x00100000UL) +#define USBFS_DOEPCTL13_STALL_POS (21U) +#define USBFS_DOEPCTL13_STALL (0x00200000UL) +#define USBFS_DOEPCTL13_CNAK_POS (26U) +#define USBFS_DOEPCTL13_CNAK (0x04000000UL) +#define USBFS_DOEPCTL13_SNAK_POS (27U) +#define USBFS_DOEPCTL13_SNAK (0x08000000UL) +#define USBFS_DOEPCTL13_SETD0PID_POS (28U) +#define USBFS_DOEPCTL13_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL13_SETD1PID_POS (29U) +#define USBFS_DOEPCTL13_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL13_EPDIS_POS (30U) +#define USBFS_DOEPCTL13_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL13_EPENA_POS (31U) +#define USBFS_DOEPCTL13_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT13 register */ +#define USBFS_DOEPINT13_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT13_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT13_EPDISBLD_POS (1U) +#define USBFS_DOEPINT13_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT13_AHBERR_POS (2U) +#define USBFS_DOEPINT13_AHBERR (0x00000004UL) +#define USBFS_DOEPINT13_SETUP_POS (3U) +#define USBFS_DOEPINT13_SETUP (0x00000008UL) +#define USBFS_DOEPINT13_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT13_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT13_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT13_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT13_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT13_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT13_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT13_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT13_BNAINTR_POS (9U) +#define USBFS_DOEPINT13_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT13_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT13_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT13_BBLEERR_POS (12U) +#define USBFS_DOEPINT13_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT13_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT13_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT13_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT13_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT13_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT13_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ13 register */ +#define USBFS_DOEPTSIZ13_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ13_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ13_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ13_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ13_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ13_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ13_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ13_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA13 register */ +#define USBFS_DOEPDMA13 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL14 register */ +#define USBFS_DOEPCTL14_MPS_POS (0U) +#define USBFS_DOEPCTL14_MPS (0x000007FFUL) +#define USBFS_DOEPCTL14_USBACTEP_POS (15U) +#define USBFS_DOEPCTL14_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL14_DPID_POS (16U) +#define USBFS_DOEPCTL14_DPID (0x00010000UL) +#define USBFS_DOEPCTL14_NAKSTS_POS (17U) +#define USBFS_DOEPCTL14_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL14_EPTYPE_POS (18U) +#define USBFS_DOEPCTL14_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL14_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL14_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL14_SNP_POS (20U) +#define USBFS_DOEPCTL14_SNP (0x00100000UL) +#define USBFS_DOEPCTL14_STALL_POS (21U) +#define USBFS_DOEPCTL14_STALL (0x00200000UL) +#define USBFS_DOEPCTL14_CNAK_POS (26U) +#define USBFS_DOEPCTL14_CNAK (0x04000000UL) +#define USBFS_DOEPCTL14_SNAK_POS (27U) +#define USBFS_DOEPCTL14_SNAK (0x08000000UL) +#define USBFS_DOEPCTL14_SETD0PID_POS (28U) +#define USBFS_DOEPCTL14_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL14_SETD1PID_POS (29U) +#define USBFS_DOEPCTL14_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL14_EPDIS_POS (30U) +#define USBFS_DOEPCTL14_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL14_EPENA_POS (31U) +#define USBFS_DOEPCTL14_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT14 register */ +#define USBFS_DOEPINT14_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT14_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT14_EPDISBLD_POS (1U) +#define USBFS_DOEPINT14_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT14_AHBERR_POS (2U) +#define USBFS_DOEPINT14_AHBERR (0x00000004UL) +#define USBFS_DOEPINT14_SETUP_POS (3U) +#define USBFS_DOEPINT14_SETUP (0x00000008UL) +#define USBFS_DOEPINT14_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT14_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT14_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT14_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT14_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT14_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT14_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT14_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT14_BNAINTR_POS (9U) +#define USBFS_DOEPINT14_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT14_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT14_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT14_BBLEERR_POS (12U) +#define USBFS_DOEPINT14_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT14_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT14_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT14_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT14_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT14_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT14_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ14 register */ +#define USBFS_DOEPTSIZ14_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ14_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ14_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ14_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ14_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ14_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ14_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ14_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA14 register */ +#define USBFS_DOEPDMA14 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_DOEPCTL15 register */ +#define USBFS_DOEPCTL15_MPS_POS (0U) +#define USBFS_DOEPCTL15_MPS (0x000007FFUL) +#define USBFS_DOEPCTL15_USBACTEP_POS (15U) +#define USBFS_DOEPCTL15_USBACTEP (0x00008000UL) +#define USBFS_DOEPCTL15_DPID_POS (16U) +#define USBFS_DOEPCTL15_DPID (0x00010000UL) +#define USBFS_DOEPCTL15_NAKSTS_POS (17U) +#define USBFS_DOEPCTL15_NAKSTS (0x00020000UL) +#define USBFS_DOEPCTL15_EPTYPE_POS (18U) +#define USBFS_DOEPCTL15_EPTYPE (0x000C0000UL) +#define USBFS_DOEPCTL15_EPTYPE_0 (0x00040000UL) +#define USBFS_DOEPCTL15_EPTYPE_1 (0x00080000UL) +#define USBFS_DOEPCTL15_SNP_POS (20U) +#define USBFS_DOEPCTL15_SNP (0x00100000UL) +#define USBFS_DOEPCTL15_STALL_POS (21U) +#define USBFS_DOEPCTL15_STALL (0x00200000UL) +#define USBFS_DOEPCTL15_CNAK_POS (26U) +#define USBFS_DOEPCTL15_CNAK (0x04000000UL) +#define USBFS_DOEPCTL15_SNAK_POS (27U) +#define USBFS_DOEPCTL15_SNAK (0x08000000UL) +#define USBFS_DOEPCTL15_SETD0PID_POS (28U) +#define USBFS_DOEPCTL15_SETD0PID (0x10000000UL) +#define USBFS_DOEPCTL15_SETD1PID_POS (29U) +#define USBFS_DOEPCTL15_SETD1PID (0x20000000UL) +#define USBFS_DOEPCTL15_EPDIS_POS (30U) +#define USBFS_DOEPCTL15_EPDIS (0x40000000UL) +#define USBFS_DOEPCTL15_EPENA_POS (31U) +#define USBFS_DOEPCTL15_EPENA (0x80000000UL) + +/* Bit definition for USBFS_DOEPINT15 register */ +#define USBFS_DOEPINT15_XFERCOMPL_POS (0U) +#define USBFS_DOEPINT15_XFERCOMPL (0x00000001UL) +#define USBFS_DOEPINT15_EPDISBLD_POS (1U) +#define USBFS_DOEPINT15_EPDISBLD (0x00000002UL) +#define USBFS_DOEPINT15_AHBERR_POS (2U) +#define USBFS_DOEPINT15_AHBERR (0x00000004UL) +#define USBFS_DOEPINT15_SETUP_POS (3U) +#define USBFS_DOEPINT15_SETUP (0x00000008UL) +#define USBFS_DOEPINT15_OUTTKNEPDIS_POS (4U) +#define USBFS_DOEPINT15_OUTTKNEPDIS (0x00000010UL) +#define USBFS_DOEPINT15_STSPHSERCVD_POS (5U) +#define USBFS_DOEPINT15_STSPHSERCVD (0x00000020UL) +#define USBFS_DOEPINT15_BACK2BACKSETUP_POS (6U) +#define USBFS_DOEPINT15_BACK2BACKSETUP (0x00000040UL) +#define USBFS_DOEPINT15_OUTPKTERR_POS (8U) +#define USBFS_DOEPINT15_OUTPKTERR (0x00000100UL) +#define USBFS_DOEPINT15_BNAINTR_POS (9U) +#define USBFS_DOEPINT15_BNAINTR (0x00000200UL) +#define USBFS_DOEPINT15_PKTDRPSTS_POS (11U) +#define USBFS_DOEPINT15_PKTDRPSTS (0x00000800UL) +#define USBFS_DOEPINT15_BBLEERR_POS (12U) +#define USBFS_DOEPINT15_BBLEERR (0x00001000UL) +#define USBFS_DOEPINT15_NAKINTRPT_POS (13U) +#define USBFS_DOEPINT15_NAKINTRPT (0x00002000UL) +#define USBFS_DOEPINT15_NYETINTRPT_POS (14U) +#define USBFS_DOEPINT15_NYETINTRPT (0x00004000UL) +#define USBFS_DOEPINT15_STUPPKTRCVD_POS (15U) +#define USBFS_DOEPINT15_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBFS_DOEPTSIZ15 register */ +#define USBFS_DOEPTSIZ15_XFERSIZE_POS (0U) +#define USBFS_DOEPTSIZ15_XFERSIZE (0x0007FFFFUL) +#define USBFS_DOEPTSIZ15_PKTCNT_POS (19U) +#define USBFS_DOEPTSIZ15_PKTCNT (0x1FF80000UL) +#define USBFS_DOEPTSIZ15_RXDPID_POS (29U) +#define USBFS_DOEPTSIZ15_RXDPID (0x60000000UL) +#define USBFS_DOEPTSIZ15_RXDPID_0 (0x20000000UL) +#define USBFS_DOEPTSIZ15_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBFS_DOEPDMA15 register */ +#define USBFS_DOEPDMA15 (0xFFFFFFFFUL) + +/* Bit definition for USBFS_PCGCCTL register */ +#define USBFS_PCGCCTL_STOPPCLK_POS (0U) +#define USBFS_PCGCCTL_STOPPCLK (0x00000001UL) +#define USBFS_PCGCCTL_GATEHCLK_POS (1U) +#define USBFS_PCGCCTL_GATEHCLK (0x00000002UL) +#define USBFS_PCGCCTL_PWRCLMP_POS (2U) +#define USBFS_PCGCCTL_PWRCLMP (0x00000004UL) +#define USBFS_PCGCCTL_RSTPDWNMODULE_POS (3U) +#define USBFS_PCGCCTL_RSTPDWNMODULE (0x00000008UL) +#define USBFS_PCGCCTL_ENBL_L1GATING_POS (5U) +#define USBFS_PCGCCTL_ENBL_L1GATING (0x00000020UL) +#define USBFS_PCGCCTL_PHYSLEEP_POS (6U) +#define USBFS_PCGCCTL_PHYSLEEP (0x00000040UL) +#define USBFS_PCGCCTL_L1SUSPENDED_POS (7U) +#define USBFS_PCGCCTL_L1SUSPENDED (0x00000080UL) +#define USBFS_PCGCCTL_RESETAFTERSUSP_POS (8U) +#define USBFS_PCGCCTL_RESETAFTERSUSP (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral USBHS +*******************************************************************************/ +/* Bit definition for USBHS_GOTGCTL register */ +#define USBHS_GOTGCTL_SESREQSCS_POS (0U) +#define USBHS_GOTGCTL_SESREQSCS (0x00000001UL) +#define USBHS_GOTGCTL_SESREQ_POS (1U) +#define USBHS_GOTGCTL_SESREQ (0x00000002UL) +#define USBHS_GOTGCTL_VBVALIDOVEN_POS (2U) +#define USBHS_GOTGCTL_VBVALIDOVEN (0x00000004UL) +#define USBHS_GOTGCTL_VBVALIDOVVAL_POS (3U) +#define USBHS_GOTGCTL_VBVALIDOVVAL (0x00000008UL) +#define USBHS_GOTGCTL_AVALIDOVEN_POS (4U) +#define USBHS_GOTGCTL_AVALIDOVEN (0x00000010UL) +#define USBHS_GOTGCTL_AVALIDOVVAL_POS (5U) +#define USBHS_GOTGCTL_AVALIDOVVAL (0x00000020UL) +#define USBHS_GOTGCTL_BVALIDOVEN_POS (6U) +#define USBHS_GOTGCTL_BVALIDOVEN (0x00000040UL) +#define USBHS_GOTGCTL_BVALIDOVVAL_POS (7U) +#define USBHS_GOTGCTL_BVALIDOVVAL (0x00000080UL) +#define USBHS_GOTGCTL_HSTNEGSCS_POS (8U) +#define USBHS_GOTGCTL_HSTNEGSCS (0x00000100UL) +#define USBHS_GOTGCTL_HNPREQ_POS (9U) +#define USBHS_GOTGCTL_HNPREQ (0x00000200UL) +#define USBHS_GOTGCTL_HSTSETHNPEN_POS (10U) +#define USBHS_GOTGCTL_HSTSETHNPEN (0x00000400UL) +#define USBHS_GOTGCTL_DEVHNPEN_POS (11U) +#define USBHS_GOTGCTL_DEVHNPEN (0x00000800UL) +#define USBHS_GOTGCTL_EHEN_POS (12U) +#define USBHS_GOTGCTL_EHEN (0x00001000UL) +#define USBHS_GOTGCTL_DBNCEFLTRBYPASS_POS (15U) +#define USBHS_GOTGCTL_DBNCEFLTRBYPASS (0x00008000UL) +#define USBHS_GOTGCTL_CONIDSTS_POS (16U) +#define USBHS_GOTGCTL_CONIDSTS (0x00010000UL) +#define USBHS_GOTGCTL_DBNCTIME_POS (17U) +#define USBHS_GOTGCTL_DBNCTIME (0x00020000UL) +#define USBHS_GOTGCTL_ASESVLD_POS (18U) +#define USBHS_GOTGCTL_ASESVLD (0x00040000UL) +#define USBHS_GOTGCTL_BSESVLD_POS (19U) +#define USBHS_GOTGCTL_BSESVLD (0x00080000UL) +#define USBHS_GOTGCTL_OTGVER_POS (20U) +#define USBHS_GOTGCTL_OTGVER (0x00100000UL) +#define USBHS_GOTGCTL_CURMOD_POS (21U) +#define USBHS_GOTGCTL_CURMOD (0x00200000UL) +#define USBHS_GOTGCTL_TESTMODE_CORR_EUSB2_POS (31U) +#define USBHS_GOTGCTL_TESTMODE_CORR_EUSB2 (0x80000000UL) + +/* Bit definition for USBHS_GOTGINT register */ +#define USBHS_GOTGINT_SESENDDET_POS (2U) +#define USBHS_GOTGINT_SESENDDET (0x00000004UL) +#define USBHS_GOTGINT_SESREQSUCSTSCHNG_POS (8U) +#define USBHS_GOTGINT_SESREQSUCSTSCHNG (0x00000100UL) +#define USBHS_GOTGINT_HSTNEGSUCSTSCHNG_POS (9U) +#define USBHS_GOTGINT_HSTNEGSUCSTSCHNG (0x00000200UL) +#define USBHS_GOTGINT_HSTNEGDET_POS (17U) +#define USBHS_GOTGINT_HSTNEGDET (0x00020000UL) +#define USBHS_GOTGINT_ADEVTOUTCHG_POS (18U) +#define USBHS_GOTGINT_ADEVTOUTCHG (0x00040000UL) +#define USBHS_GOTGINT_DBNCEDONE_POS (19U) +#define USBHS_GOTGINT_DBNCEDONE (0x00080000UL) + +/* Bit definition for USBHS_GAHBCFG register */ +#define USBHS_GAHBCFG_GLBLINTRMSK_POS (0U) +#define USBHS_GAHBCFG_GLBLINTRMSK (0x00000001UL) +#define USBHS_GAHBCFG_HBSTLEN_POS (1U) +#define USBHS_GAHBCFG_HBSTLEN (0x0000001EUL) +#define USBHS_GAHBCFG_HBSTLEN_0 (0x00000002UL) +#define USBHS_GAHBCFG_HBSTLEN_1 (0x00000004UL) +#define USBHS_GAHBCFG_HBSTLEN_2 (0x00000008UL) +#define USBHS_GAHBCFG_HBSTLEN_3 (0x00000010UL) +#define USBHS_GAHBCFG_DMAEN_POS (5U) +#define USBHS_GAHBCFG_DMAEN (0x00000020UL) +#define USBHS_GAHBCFG_NPTXFEMPLVL_POS (7U) +#define USBHS_GAHBCFG_NPTXFEMPLVL (0x00000080UL) +#define USBHS_GAHBCFG_PTXFEMPLVL_POS (8U) +#define USBHS_GAHBCFG_PTXFEMPLVL (0x00000100UL) +#define USBHS_GAHBCFG_REMMEMSUPP_POS (21U) +#define USBHS_GAHBCFG_REMMEMSUPP (0x00200000UL) +#define USBHS_GAHBCFG_NOTIALLDMAWRIT_POS (22U) +#define USBHS_GAHBCFG_NOTIALLDMAWRIT (0x00400000UL) +#define USBHS_GAHBCFG_AHBSINGLE_POS (23U) +#define USBHS_GAHBCFG_AHBSINGLE (0x00800000UL) + +/* Bit definition for USBHS_GUSBCFG register */ +#define USBHS_GUSBCFG_TOUTCAL_POS (0U) +#define USBHS_GUSBCFG_TOUTCAL (0x00000007UL) +#define USBHS_GUSBCFG_TOUTCAL_0 (0x00000001UL) +#define USBHS_GUSBCFG_TOUTCAL_1 (0x00000002UL) +#define USBHS_GUSBCFG_TOUTCAL_2 (0x00000004UL) +#define USBHS_GUSBCFG_PHYIF_POS (3U) +#define USBHS_GUSBCFG_PHYIF (0x00000008UL) +#define USBHS_GUSBCFG_ULPI_UTMI_SEL_POS (4U) +#define USBHS_GUSBCFG_ULPI_UTMI_SEL (0x00000010UL) +#define USBHS_GUSBCFG_FSINTF_POS (5U) +#define USBHS_GUSBCFG_FSINTF (0x00000020UL) +#define USBHS_GUSBCFG_PHYSEL_POS (6U) +#define USBHS_GUSBCFG_PHYSEL (0x00000040UL) +#define USBHS_GUSBCFG_DDRSEL_POS (7U) +#define USBHS_GUSBCFG_DDRSEL (0x00000080UL) +#define USBHS_GUSBCFG_SRPCAP_POS (8U) +#define USBHS_GUSBCFG_SRPCAP (0x00000100UL) +#define USBHS_GUSBCFG_HNPCAP_POS (9U) +#define USBHS_GUSBCFG_HNPCAP (0x00000200UL) +#define USBHS_GUSBCFG_USBTRDTIM_POS (10U) +#define USBHS_GUSBCFG_USBTRDTIM (0x00003C00UL) +#define USBHS_GUSBCFG_USBTRDTIM_0 (0x00000400UL) +#define USBHS_GUSBCFG_USBTRDTIM_1 (0x00000800UL) +#define USBHS_GUSBCFG_USBTRDTIM_2 (0x00001000UL) +#define USBHS_GUSBCFG_USBTRDTIM_3 (0x00002000UL) +#define USBHS_GUSBCFG_ULPIFSLS_POS (17U) +#define USBHS_GUSBCFG_ULPIFSLS (0x00020000UL) +#define USBHS_GUSBCFG_ULPIAUTORES_POS (18U) +#define USBHS_GUSBCFG_ULPIAUTORES (0x00040000UL) +#define USBHS_GUSBCFG_ULPICLKSUSM_POS (19U) +#define USBHS_GUSBCFG_ULPICLKSUSM (0x00080000UL) +#define USBHS_GUSBCFG_ULPIEXTVBUSDRV_POS (20U) +#define USBHS_GUSBCFG_ULPIEXTVBUSDRV (0x00100000UL) +#define USBHS_GUSBCFG_ULPIEXTVBUSINDICATOR_POS (21U) +#define USBHS_GUSBCFG_ULPIEXTVBUSINDICATOR (0x00200000UL) +#define USBHS_GUSBCFG_TERMSELDLPULSE_POS (22U) +#define USBHS_GUSBCFG_TERMSELDLPULSE (0x00400000UL) +#define USBHS_GUSBCFG_COMPLEMENT_POS (23U) +#define USBHS_GUSBCFG_COMPLEMENT (0x00800000UL) +#define USBHS_GUSBCFG_INDICATOR_POS (24U) +#define USBHS_GUSBCFG_INDICATOR (0x01000000UL) +#define USBHS_GUSBCFG_ULPI_POS (25U) +#define USBHS_GUSBCFG_ULPI (0x02000000UL) +#define USBHS_GUSBCFG_IC_USBCAP_POS (26U) +#define USBHS_GUSBCFG_IC_USBCAP (0x04000000UL) +#define USBHS_GUSBCFG_TXENDDELAY_POS (28U) +#define USBHS_GUSBCFG_TXENDDELAY (0x10000000UL) +#define USBHS_GUSBCFG_FORCEHSTMODE_POS (29U) +#define USBHS_GUSBCFG_FORCEHSTMODE (0x20000000UL) +#define USBHS_GUSBCFG_FORCEDEVMODE_POS (30U) +#define USBHS_GUSBCFG_FORCEDEVMODE (0x40000000UL) +#define USBHS_GUSBCFG_CORRUPTTXPKT_POS (31U) +#define USBHS_GUSBCFG_CORRUPTTXPKT (0x80000000UL) + +/* Bit definition for USBHS_GRSTCTL register */ +#define USBHS_GRSTCTL_CSFTRST_POS (0U) +#define USBHS_GRSTCTL_CSFTRST (0x00000001UL) +#define USBHS_GRSTCTL_PIUFSSFTRST_POS (1U) +#define USBHS_GRSTCTL_PIUFSSFTRST (0x00000002UL) +#define USBHS_GRSTCTL_FRMCNTRRST_POS (2U) +#define USBHS_GRSTCTL_FRMCNTRRST (0x00000004UL) +#define USBHS_GRSTCTL_RXFFLSH_POS (4U) +#define USBHS_GRSTCTL_RXFFLSH (0x00000010UL) +#define USBHS_GRSTCTL_TXFFLSH_POS (5U) +#define USBHS_GRSTCTL_TXFFLSH (0x00000020UL) +#define USBHS_GRSTCTL_TXFNUM_POS (6U) +#define USBHS_GRSTCTL_TXFNUM (0x000007C0UL) +#define USBHS_GRSTCTL_TXFNUM_0 (0x00000040UL) +#define USBHS_GRSTCTL_TXFNUM_1 (0x00000080UL) +#define USBHS_GRSTCTL_TXFNUM_2 (0x00000100UL) +#define USBHS_GRSTCTL_TXFNUM_3 (0x00000200UL) +#define USBHS_GRSTCTL_TXFNUM_4 (0x00000400UL) +#define USBHS_GRSTCTL_DMAREQ_POS (30U) +#define USBHS_GRSTCTL_DMAREQ (0x40000000UL) +#define USBHS_GRSTCTL_AHBIDLE_POS (31U) +#define USBHS_GRSTCTL_AHBIDLE (0x80000000UL) + +/* Bit definition for USBHS_GINTSTS register */ +#define USBHS_GINTSTS_CURMOD_POS (0U) +#define USBHS_GINTSTS_CURMOD (0x00000001UL) +#define USBHS_GINTSTS_MODEMIS_POS (1U) +#define USBHS_GINTSTS_MODEMIS (0x00000002UL) +#define USBHS_GINTSTS_OTGINT_POS (2U) +#define USBHS_GINTSTS_OTGINT (0x00000004UL) +#define USBHS_GINTSTS_SOF_POS (3U) +#define USBHS_GINTSTS_SOF (0x00000008UL) +#define USBHS_GINTSTS_RXFLVL_POS (4U) +#define USBHS_GINTSTS_RXFLVL (0x00000010UL) +#define USBHS_GINTSTS_NPTXFEMP_POS (5U) +#define USBHS_GINTSTS_NPTXFEMP (0x00000020UL) +#define USBHS_GINTSTS_GINNAKEFF_POS (6U) +#define USBHS_GINTSTS_GINNAKEFF (0x00000040UL) +#define USBHS_GINTSTS_GOUTNAKEFF_POS (7U) +#define USBHS_GINTSTS_GOUTNAKEFF (0x00000080UL) +#define USBHS_GINTSTS_ERLYSUSP_POS (10U) +#define USBHS_GINTSTS_ERLYSUSP (0x00000400UL) +#define USBHS_GINTSTS_USBSUSP_POS (11U) +#define USBHS_GINTSTS_USBSUSP (0x00000800UL) +#define USBHS_GINTSTS_USBRST_POS (12U) +#define USBHS_GINTSTS_USBRST (0x00001000UL) +#define USBHS_GINTSTS_ENUMDONE_POS (13U) +#define USBHS_GINTSTS_ENUMDONE (0x00002000UL) +#define USBHS_GINTSTS_ISOOUTDROP_POS (14U) +#define USBHS_GINTSTS_ISOOUTDROP (0x00004000UL) +#define USBHS_GINTSTS_EOPF_POS (15U) +#define USBHS_GINTSTS_EOPF (0x00008000UL) +#define USBHS_GINTSTS_EPMIS_POS (17U) +#define USBHS_GINTSTS_EPMIS (0x00020000UL) +#define USBHS_GINTSTS_IEPINT_POS (18U) +#define USBHS_GINTSTS_IEPINT (0x00040000UL) +#define USBHS_GINTSTS_OEPINT_POS (19U) +#define USBHS_GINTSTS_OEPINT (0x00080000UL) +#define USBHS_GINTSTS_INCOMPISOIN_POS (20U) +#define USBHS_GINTSTS_INCOMPISOIN (0x00100000UL) +#define USBHS_GINTSTS_INCOMPLP_POS (21U) +#define USBHS_GINTSTS_INCOMPLP (0x00200000UL) +#define USBHS_GINTSTS_FETSUSP_POS (22U) +#define USBHS_GINTSTS_FETSUSP (0x00400000UL) +#define USBHS_GINTSTS_RESETDET_POS (23U) +#define USBHS_GINTSTS_RESETDET (0x00800000UL) +#define USBHS_GINTSTS_PRTINT_POS (24U) +#define USBHS_GINTSTS_PRTINT (0x01000000UL) +#define USBHS_GINTSTS_HCHINT_POS (25U) +#define USBHS_GINTSTS_HCHINT (0x02000000UL) +#define USBHS_GINTSTS_PTXFEMP_POS (26U) +#define USBHS_GINTSTS_PTXFEMP (0x04000000UL) +#define USBHS_GINTSTS_LPM_INT_POS (27U) +#define USBHS_GINTSTS_LPM_INT (0x08000000UL) +#define USBHS_GINTSTS_CONIDSTSCHNG_POS (28U) +#define USBHS_GINTSTS_CONIDSTSCHNG (0x10000000UL) +#define USBHS_GINTSTS_DISCONNINT_POS (29U) +#define USBHS_GINTSTS_DISCONNINT (0x20000000UL) +#define USBHS_GINTSTS_SESSREQINT_POS (30U) +#define USBHS_GINTSTS_SESSREQINT (0x40000000UL) +#define USBHS_GINTSTS_WKUPINT_POS (31U) +#define USBHS_GINTSTS_WKUPINT (0x80000000UL) + +/* Bit definition for USBHS_GINTMSK register */ +#define USBHS_GINTMSK_MODEMISMSK_POS (1U) +#define USBHS_GINTMSK_MODEMISMSK (0x00000002UL) +#define USBHS_GINTMSK_OTGINTMSK_POS (2U) +#define USBHS_GINTMSK_OTGINTMSK (0x00000004UL) +#define USBHS_GINTMSK_SOFMSK_POS (3U) +#define USBHS_GINTMSK_SOFMSK (0x00000008UL) +#define USBHS_GINTMSK_RXFLVLMSK_POS (4U) +#define USBHS_GINTMSK_RXFLVLMSK (0x00000010UL) +#define USBHS_GINTMSK_NPTXFEMPMSK_POS (5U) +#define USBHS_GINTMSK_NPTXFEMPMSK (0x00000020UL) +#define USBHS_GINTMSK_GINNAKEFFMSK_POS (6U) +#define USBHS_GINTMSK_GINNAKEFFMSK (0x00000040UL) +#define USBHS_GINTMSK_GOUTNAKEFFMSK_POS (7U) +#define USBHS_GINTMSK_GOUTNAKEFFMSK (0x00000080UL) +#define USBHS_GINTMSK_ERLYSUSPMSK_POS (10U) +#define USBHS_GINTMSK_ERLYSUSPMSK (0x00000400UL) +#define USBHS_GINTMSK_USBSUSPMSK_POS (11U) +#define USBHS_GINTMSK_USBSUSPMSK (0x00000800UL) +#define USBHS_GINTMSK_USBRSTMSK_POS (12U) +#define USBHS_GINTMSK_USBRSTMSK (0x00001000UL) +#define USBHS_GINTMSK_ENUMDONEMSK_POS (13U) +#define USBHS_GINTMSK_ENUMDONEMSK (0x00002000UL) +#define USBHS_GINTMSK_ISOOUTDROPMSK_POS (14U) +#define USBHS_GINTMSK_ISOOUTDROPMSK (0x00004000UL) +#define USBHS_GINTMSK_EOPFMSK_POS (15U) +#define USBHS_GINTMSK_EOPFMSK (0x00008000UL) +#define USBHS_GINTMSK_EPMISMSK_POS (17U) +#define USBHS_GINTMSK_EPMISMSK (0x00020000UL) +#define USBHS_GINTMSK_IEPINTMSK_POS (18U) +#define USBHS_GINTMSK_IEPINTMSK (0x00040000UL) +#define USBHS_GINTMSK_OEPINTMSK_POS (19U) +#define USBHS_GINTMSK_OEPINTMSK (0x00080000UL) +#define USBHS_GINTMSK_INCOMPLPMSK_POS (21U) +#define USBHS_GINTMSK_INCOMPLPMSK (0x00200000UL) +#define USBHS_GINTMSK_FETSUSPMSK_POS (22U) +#define USBHS_GINTMSK_FETSUSPMSK (0x00400000UL) +#define USBHS_GINTMSK_RESETDETMSK_POS (23U) +#define USBHS_GINTMSK_RESETDETMSK (0x00800000UL) +#define USBHS_GINTMSK_PRTINTMSK_POS (24U) +#define USBHS_GINTMSK_PRTINTMSK (0x01000000UL) +#define USBHS_GINTMSK_HCHINTMSK_POS (25U) +#define USBHS_GINTMSK_HCHINTMSK (0x02000000UL) +#define USBHS_GINTMSK_PTXFEMPMSK_POS (26U) +#define USBHS_GINTMSK_PTXFEMPMSK (0x04000000UL) +#define USBHS_GINTMSK_LPM_INTMSK_POS (27U) +#define USBHS_GINTMSK_LPM_INTMSK (0x08000000UL) +#define USBHS_GINTMSK_CONIDSTSCHNGMSK_POS (28U) +#define USBHS_GINTMSK_CONIDSTSCHNGMSK (0x10000000UL) +#define USBHS_GINTMSK_DISCONNINTMSK_POS (29U) +#define USBHS_GINTMSK_DISCONNINTMSK (0x20000000UL) +#define USBHS_GINTMSK_SESSREQINTMSK_POS (30U) +#define USBHS_GINTMSK_SESSREQINTMSK (0x40000000UL) +#define USBHS_GINTMSK_WKUPINTMSK_POS (31U) +#define USBHS_GINTMSK_WKUPINTMSK (0x80000000UL) + +/* Bit definition for USBHS_GRXSTSR register */ +#define USBHS_GRXSTSR_CHNUM_POS (0U) +#define USBHS_GRXSTSR_CHNUM (0x0000000FUL) +#define USBHS_GRXSTSR_CHNUM_0 (0x00000001UL) +#define USBHS_GRXSTSR_CHNUM_1 (0x00000002UL) +#define USBHS_GRXSTSR_CHNUM_2 (0x00000004UL) +#define USBHS_GRXSTSR_CHNUM_3 (0x00000008UL) +#define USBHS_GRXSTSR_BCNT_POS (4U) +#define USBHS_GRXSTSR_BCNT (0x00007FF0UL) +#define USBHS_GRXSTSR_BCNT_0 (0x00000010UL) +#define USBHS_GRXSTSR_BCNT_1 (0x00000020UL) +#define USBHS_GRXSTSR_BCNT_2 (0x00000040UL) +#define USBHS_GRXSTSR_BCNT_3 (0x00000080UL) +#define USBHS_GRXSTSR_BCNT_4 (0x00000100UL) +#define USBHS_GRXSTSR_BCNT_5 (0x00000200UL) +#define USBHS_GRXSTSR_BCNT_6 (0x00000400UL) +#define USBHS_GRXSTSR_BCNT_7 (0x00000800UL) +#define USBHS_GRXSTSR_BCNT_8 (0x00001000UL) +#define USBHS_GRXSTSR_BCNT_9 (0x00002000UL) +#define USBHS_GRXSTSR_BCNT_10 (0x00004000UL) +#define USBHS_GRXSTSR_DPID_POS (15U) +#define USBHS_GRXSTSR_DPID (0x00018000UL) +#define USBHS_GRXSTSR_DPID_0 (0x00008000UL) +#define USBHS_GRXSTSR_DPID_1 (0x00010000UL) +#define USBHS_GRXSTSR_PKTSTS_POS (17U) +#define USBHS_GRXSTSR_PKTSTS (0x001E0000UL) +#define USBHS_GRXSTSR_PKTSTS_0 (0x00020000UL) +#define USBHS_GRXSTSR_PKTSTS_1 (0x00040000UL) +#define USBHS_GRXSTSR_PKTSTS_2 (0x00080000UL) +#define USBHS_GRXSTSR_PKTSTS_3 (0x00100000UL) +#define USBHS_GRXSTSR_FN_POS (21U) +#define USBHS_GRXSTSR_FN (0x01E00000UL) +#define USBHS_GRXSTSR_FN_0 (0x00200000UL) +#define USBHS_GRXSTSR_FN_1 (0x00400000UL) +#define USBHS_GRXSTSR_FN_2 (0x00800000UL) +#define USBHS_GRXSTSR_FN_3 (0x01000000UL) + +/* Bit definition for USBHS_GRXSTSP register */ +#define USBHS_GRXSTSP_CHNUM_POS (0U) +#define USBHS_GRXSTSP_CHNUM (0x0000000FUL) +#define USBHS_GRXSTSP_CHNUM_0 (0x00000001UL) +#define USBHS_GRXSTSP_CHNUM_1 (0x00000002UL) +#define USBHS_GRXSTSP_CHNUM_2 (0x00000004UL) +#define USBHS_GRXSTSP_CHNUM_3 (0x00000008UL) +#define USBHS_GRXSTSP_BCNT_POS (4U) +#define USBHS_GRXSTSP_BCNT (0x00007FF0UL) +#define USBHS_GRXSTSP_BCNT_0 (0x00000010UL) +#define USBHS_GRXSTSP_BCNT_1 (0x00000020UL) +#define USBHS_GRXSTSP_BCNT_2 (0x00000040UL) +#define USBHS_GRXSTSP_BCNT_3 (0x00000080UL) +#define USBHS_GRXSTSP_BCNT_4 (0x00000100UL) +#define USBHS_GRXSTSP_BCNT_5 (0x00000200UL) +#define USBHS_GRXSTSP_BCNT_6 (0x00000400UL) +#define USBHS_GRXSTSP_BCNT_7 (0x00000800UL) +#define USBHS_GRXSTSP_BCNT_8 (0x00001000UL) +#define USBHS_GRXSTSP_BCNT_9 (0x00002000UL) +#define USBHS_GRXSTSP_BCNT_10 (0x00004000UL) +#define USBHS_GRXSTSP_DPID_POS (15U) +#define USBHS_GRXSTSP_DPID (0x00018000UL) +#define USBHS_GRXSTSP_DPID_0 (0x00008000UL) +#define USBHS_GRXSTSP_DPID_1 (0x00010000UL) +#define USBHS_GRXSTSP_PKTSTS_POS (17U) +#define USBHS_GRXSTSP_PKTSTS (0x001E0000UL) +#define USBHS_GRXSTSP_PKTSTS_0 (0x00020000UL) +#define USBHS_GRXSTSP_PKTSTS_1 (0x00040000UL) +#define USBHS_GRXSTSP_PKTSTS_2 (0x00080000UL) +#define USBHS_GRXSTSP_PKTSTS_3 (0x00100000UL) +#define USBHS_GRXSTSP_FN_POS (21U) +#define USBHS_GRXSTSP_FN (0x01E00000UL) +#define USBHS_GRXSTSP_FN_0 (0x00200000UL) +#define USBHS_GRXSTSP_FN_1 (0x00400000UL) +#define USBHS_GRXSTSP_FN_2 (0x00800000UL) +#define USBHS_GRXSTSP_FN_3 (0x01000000UL) + +/* Bit definition for USBHS_GRXFSIZ register */ +#define USBHS_GRXFSIZ_RXFDEP (0x00000FFFUL) + +/* Bit definition for USBHS_GNPTXFSIZ register */ +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_POS (0U) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR (0x00000FFFUL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_0 (0x00000001UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_1 (0x00000002UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_2 (0x00000004UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_3 (0x00000008UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_4 (0x00000010UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_5 (0x00000020UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_6 (0x00000040UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_7 (0x00000080UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_8 (0x00000100UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_9 (0x00000200UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_10 (0x00000400UL) +#define USBHS_GNPTXFSIZ_NPTXFSTADDR_11 (0x00000800UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_POS (16U) +#define USBHS_GNPTXFSIZ_NPTXFDEP (0x0FFF0000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_0 (0x00010000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_1 (0x00020000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_2 (0x00040000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_3 (0x00080000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_4 (0x00100000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_5 (0x00200000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_6 (0x00400000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_7 (0x00800000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_8 (0x01000000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_9 (0x02000000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_10 (0x04000000UL) +#define USBHS_GNPTXFSIZ_NPTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_GNPTXSTS register */ +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_POS (0U) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL (0x0000FFFFUL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_0 (0x00000001UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_1 (0x00000002UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_2 (0x00000004UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_3 (0x00000008UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_4 (0x00000010UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_5 (0x00000020UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_6 (0x00000040UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_7 (0x00000080UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_8 (0x00000100UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_9 (0x00000200UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_10 (0x00000400UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_11 (0x00000800UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_12 (0x00001000UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_13 (0x00002000UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_14 (0x00004000UL) +#define USBHS_GNPTXSTS_NPTXFSPCAVAIL_15 (0x00008000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_POS (16U) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL (0x00FF0000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_0 (0x00010000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_1 (0x00020000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_2 (0x00040000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_3 (0x00080000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_4 (0x00100000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_5 (0x00200000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_6 (0x00400000UL) +#define USBHS_GNPTXSTS_NPTXQSPCAVAIL_7 (0x00800000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_POS (24U) +#define USBHS_GNPTXSTS_NPTXQTOP (0x7F000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_0 (0x01000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_1 (0x02000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_2 (0x04000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_3 (0x08000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_4 (0x10000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_5 (0x20000000UL) +#define USBHS_GNPTXSTS_NPTXQTOP_6 (0x40000000UL) + +/* Bit definition for USBHS_GPVNDCTL register */ +#define USBHS_GPVNDCTL_REGDATA_POS (0U) +#define USBHS_GPVNDCTL_REGDATA (0x000000FFUL) +#define USBHS_GPVNDCTL_REGDATA_0 (0x00000001UL) +#define USBHS_GPVNDCTL_REGDATA_1 (0x00000002UL) +#define USBHS_GPVNDCTL_REGDATA_2 (0x00000004UL) +#define USBHS_GPVNDCTL_REGDATA_3 (0x00000008UL) +#define USBHS_GPVNDCTL_REGDATA_4 (0x00000010UL) +#define USBHS_GPVNDCTL_REGDATA_5 (0x00000020UL) +#define USBHS_GPVNDCTL_REGDATA_6 (0x00000040UL) +#define USBHS_GPVNDCTL_REGDATA_7 (0x00000080UL) +#define USBHS_GPVNDCTL_VCTRL_POS (8U) +#define USBHS_GPVNDCTL_VCTRL (0x0000FF00UL) +#define USBHS_GPVNDCTL_VCTRL_0 (0x00000100UL) +#define USBHS_GPVNDCTL_VCTRL_1 (0x00000200UL) +#define USBHS_GPVNDCTL_VCTRL_2 (0x00000400UL) +#define USBHS_GPVNDCTL_VCTRL_3 (0x00000800UL) +#define USBHS_GPVNDCTL_VCTRL_4 (0x00001000UL) +#define USBHS_GPVNDCTL_VCTRL_5 (0x00002000UL) +#define USBHS_GPVNDCTL_VCTRL_6 (0x00004000UL) +#define USBHS_GPVNDCTL_VCTRL_7 (0x00008000UL) +#define USBHS_GPVNDCTL_REGADDR_POS (16U) +#define USBHS_GPVNDCTL_REGADDR (0x003F0000UL) +#define USBHS_GPVNDCTL_REGADDR_0 (0x00010000UL) +#define USBHS_GPVNDCTL_REGADDR_1 (0x00020000UL) +#define USBHS_GPVNDCTL_REGADDR_2 (0x00040000UL) +#define USBHS_GPVNDCTL_REGADDR_3 (0x00080000UL) +#define USBHS_GPVNDCTL_REGADDR_4 (0x00100000UL) +#define USBHS_GPVNDCTL_REGADDR_5 (0x00200000UL) +#define USBHS_GPVNDCTL_REGWR_POS (22U) +#define USBHS_GPVNDCTL_REGWR (0x00400000UL) +#define USBHS_GPVNDCTL_NEWREGREQ_POS (25U) +#define USBHS_GPVNDCTL_NEWREGREQ (0x02000000UL) +#define USBHS_GPVNDCTL_VSTSBSY_POS (26U) +#define USBHS_GPVNDCTL_VSTSBSY (0x04000000UL) +#define USBHS_GPVNDCTL_VSTSDONE_POS (27U) +#define USBHS_GPVNDCTL_VSTSDONE (0x08000000UL) + +/* Bit definition for USBHS_GUID register */ +#define USBHS_GUID (0xFFFFFFFFUL) + +/* Bit definition for USBHS_GLPMCFG register */ +#define USBHS_GLPMCFG_LPMCAP_POS (0U) +#define USBHS_GLPMCFG_LPMCAP (0x00000001UL) +#define USBHS_GLPMCFG_APPL1RES_POS (1U) +#define USBHS_GLPMCFG_APPL1RES (0x00000002UL) +#define USBHS_GLPMCFG_HIRD_POS (2U) +#define USBHS_GLPMCFG_HIRD (0x0000003CUL) +#define USBHS_GLPMCFG_HIRD_0 (0x00000004UL) +#define USBHS_GLPMCFG_HIRD_1 (0x00000008UL) +#define USBHS_GLPMCFG_HIRD_2 (0x00000010UL) +#define USBHS_GLPMCFG_HIRD_3 (0x00000020UL) +#define USBHS_GLPMCFG_BREMOTEWAKE_POS (6U) +#define USBHS_GLPMCFG_BREMOTEWAKE (0x00000040UL) +#define USBHS_GLPMCFG_ENBLSLPM_POS (7U) +#define USBHS_GLPMCFG_ENBLSLPM (0x00000080UL) +#define USBHS_GLPMCFG_HIRD_THRES_POS (8U) +#define USBHS_GLPMCFG_HIRD_THRES (0x00001F00UL) +#define USBHS_GLPMCFG_HIRD_THRES_0 (0x00000100UL) +#define USBHS_GLPMCFG_HIRD_THRES_1 (0x00000200UL) +#define USBHS_GLPMCFG_HIRD_THRES_2 (0x00000400UL) +#define USBHS_GLPMCFG_HIRD_THRES_3 (0x00000800UL) +#define USBHS_GLPMCFG_HIRD_THRES_4 (0x00001000UL) +#define USBHS_GLPMCFG_COREL1RES_POS (13U) +#define USBHS_GLPMCFG_COREL1RES (0x00006000UL) +#define USBHS_GLPMCFG_COREL1RES_0 (0x00002000UL) +#define USBHS_GLPMCFG_COREL1RES_1 (0x00004000UL) +#define USBHS_GLPMCFG_SLPSTS_POS (15U) +#define USBHS_GLPMCFG_SLPSTS (0x00008000UL) +#define USBHS_GLPMCFG_L1RESUMEOK_POS (16U) +#define USBHS_GLPMCFG_L1RESUMEOK (0x00010000UL) +#define USBHS_GLPMCFG_LPM_CHNL_INDX_POS (17U) +#define USBHS_GLPMCFG_LPM_CHNL_INDX (0x001E0000UL) +#define USBHS_GLPMCFG_LPM_CHNL_INDX_0 (0x00020000UL) +#define USBHS_GLPMCFG_LPM_CHNL_INDX_1 (0x00040000UL) +#define USBHS_GLPMCFG_LPM_CHNL_INDX_2 (0x00080000UL) +#define USBHS_GLPMCFG_LPM_CHNL_INDX_3 (0x00100000UL) +#define USBHS_GLPMCFG_LPM_RETRY_CNT_POS (21U) +#define USBHS_GLPMCFG_LPM_RETRY_CNT (0x00E00000UL) +#define USBHS_GLPMCFG_LPM_RETRY_CNT_0 (0x00200000UL) +#define USBHS_GLPMCFG_LPM_RETRY_CNT_1 (0x00400000UL) +#define USBHS_GLPMCFG_LPM_RETRY_CNT_2 (0x00800000UL) +#define USBHS_GLPMCFG_SNDLPM_POS (24U) +#define USBHS_GLPMCFG_SNDLPM (0x01000000UL) +#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_POS (25U) +#define USBHS_GLPMCFG_LPM_RETRYCNT_STS (0x0E000000UL) +#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_0 (0x02000000UL) +#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_1 (0x04000000UL) +#define USBHS_GLPMCFG_LPM_RETRYCNT_STS_2 (0x08000000UL) +#define USBHS_GLPMCFG_LPM_ENBESL_POS (28U) +#define USBHS_GLPMCFG_LPM_ENBESL (0x10000000UL) +#define USBHS_GLPMCFG_LPM_RESTORESLPSTS_POS (29U) +#define USBHS_GLPMCFG_LPM_RESTORESLPSTS (0x20000000UL) + +/* Bit definition for USBHS_GDFIFOCFG register */ +#define USBHS_GDFIFOCFG_GDFIFOCFG_POS (0U) +#define USBHS_GDFIFOCFG_GDFIFOCFG (0x0000FFFFUL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_0 (0x00000001UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_1 (0x00000002UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_2 (0x00000004UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_3 (0x00000008UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_4 (0x00000010UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_5 (0x00000020UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_6 (0x00000040UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_7 (0x00000080UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_8 (0x00000100UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_9 (0x00000200UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_10 (0x00000400UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_11 (0x00000800UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_12 (0x00001000UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_13 (0x00002000UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_14 (0x00004000UL) +#define USBHS_GDFIFOCFG_GDFIFOCFG_15 (0x00008000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_POS (16U) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR (0xFFFF0000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_0 (0x00010000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_1 (0x00020000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_2 (0x00040000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_3 (0x00080000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_4 (0x00100000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_5 (0x00200000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_6 (0x00400000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_7 (0x00800000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_8 (0x01000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_9 (0x02000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_10 (0x04000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_11 (0x08000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_12 (0x10000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_13 (0x20000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_14 (0x40000000UL) +#define USBHS_GDFIFOCFG_EPINFOBASEADDR_15 (0x80000000UL) + +/* Bit definition for USBHS_HPTXFSIZ register */ +#define USBHS_HPTXFSIZ_PTXFSTADDR_POS (0U) +#define USBHS_HPTXFSIZ_PTXFSTADDR (0x00001FFFUL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_0 (0x00000001UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_1 (0x00000002UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_2 (0x00000004UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_3 (0x00000008UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_4 (0x00000010UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_5 (0x00000020UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_6 (0x00000040UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_7 (0x00000080UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_8 (0x00000100UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_9 (0x00000200UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_10 (0x00000400UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_11 (0x00000800UL) +#define USBHS_HPTXFSIZ_PTXFSTADDR_12 (0x00001000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_POS (16U) +#define USBHS_HPTXFSIZ_PTXFSIZE (0x0FFF0000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_0 (0x00010000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_1 (0x00020000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_2 (0x00040000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_3 (0x00080000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_4 (0x00100000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_5 (0x00200000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_6 (0x00400000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_7 (0x00800000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_8 (0x01000000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_9 (0x02000000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_10 (0x04000000UL) +#define USBHS_HPTXFSIZ_PTXFSIZE_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF1 register */ +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR (0x00001FFFUL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF1_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF1_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF1_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF2 register */ +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR (0x00001FFFUL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF2_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF2_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF2_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF3 register */ +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR (0x00003FFFUL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF3_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF3_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF3_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF4 register */ +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR (0x00003FFFUL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF4_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF4_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF4_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF5 register */ +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR (0x00003FFFUL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF5_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF5_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF5_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF6 register */ +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR (0x00003FFFUL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF6_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF6_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF6_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF7 register */ +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF7_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF7_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF7_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF8 register */ +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF8_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF8_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF8_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF9 register */ +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF9_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF9_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF9_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF10 register */ +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF10_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF10_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF10_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF11 register */ +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF11_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF11_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF11_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF12 register */ +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF12_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF12_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF12_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF13 register */ +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF13_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF13_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF13_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF14 register */ +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR (0x00007FFFUL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF14_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF14_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF14_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_DIEPTXF15 register */ +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_POS (0U) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR (0x0000FFFFUL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_0 (0x00000001UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_1 (0x00000002UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_2 (0x00000004UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_3 (0x00000008UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_4 (0x00000010UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_5 (0x00000020UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_6 (0x00000040UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_7 (0x00000080UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_8 (0x00000100UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_9 (0x00000200UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_10 (0x00000400UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_11 (0x00000800UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_12 (0x00001000UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_13 (0x00002000UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_14 (0x00004000UL) +#define USBHS_DIEPTXF15_INEPNTXFSTADDR_15 (0x00008000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_POS (16U) +#define USBHS_DIEPTXF15_INEPNTXFDEP (0x0FFF0000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_0 (0x00010000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_1 (0x00020000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_2 (0x00040000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_3 (0x00080000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_4 (0x00100000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_5 (0x00200000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_6 (0x00400000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_7 (0x00800000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_8 (0x01000000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_9 (0x02000000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_10 (0x04000000UL) +#define USBHS_DIEPTXF15_INEPNTXFDEP_11 (0x08000000UL) + +/* Bit definition for USBHS_HCFG register */ +#define USBHS_HCFG_FSLSPCLKSEL_POS (0U) +#define USBHS_HCFG_FSLSPCLKSEL (0x00000003UL) +#define USBHS_HCFG_FSLSPCLKSEL_0 (0x00000001UL) +#define USBHS_HCFG_FSLSPCLKSEL_1 (0x00000002UL) +#define USBHS_HCFG_FSLSSUPP_POS (2U) +#define USBHS_HCFG_FSLSSUPP (0x00000004UL) +#define USBHS_HCFG_ENA32KHZS_POS (7U) +#define USBHS_HCFG_ENA32KHZS (0x00000080UL) +#define USBHS_HCFG_RESVALID_POS (8U) +#define USBHS_HCFG_RESVALID (0x0000FF00UL) +#define USBHS_HCFG_RESVALID_0 (0x00000100UL) +#define USBHS_HCFG_RESVALID_1 (0x00000200UL) +#define USBHS_HCFG_RESVALID_2 (0x00000400UL) +#define USBHS_HCFG_RESVALID_3 (0x00000800UL) +#define USBHS_HCFG_RESVALID_4 (0x00001000UL) +#define USBHS_HCFG_RESVALID_5 (0x00002000UL) +#define USBHS_HCFG_RESVALID_6 (0x00004000UL) +#define USBHS_HCFG_RESVALID_7 (0x00008000UL) +#define USBHS_HCFG_MODECHTIMEN_POS (31U) +#define USBHS_HCFG_MODECHTIMEN (0x80000000UL) + +/* Bit definition for USBHS_HFIR register */ +#define USBHS_HFIR_FRINT_POS (0U) +#define USBHS_HFIR_FRINT (0x0000FFFFUL) +#define USBHS_HFIR_FRINT_0 (0x00000001UL) +#define USBHS_HFIR_FRINT_1 (0x00000002UL) +#define USBHS_HFIR_FRINT_2 (0x00000004UL) +#define USBHS_HFIR_FRINT_3 (0x00000008UL) +#define USBHS_HFIR_FRINT_4 (0x00000010UL) +#define USBHS_HFIR_FRINT_5 (0x00000020UL) +#define USBHS_HFIR_FRINT_6 (0x00000040UL) +#define USBHS_HFIR_FRINT_7 (0x00000080UL) +#define USBHS_HFIR_FRINT_8 (0x00000100UL) +#define USBHS_HFIR_FRINT_9 (0x00000200UL) +#define USBHS_HFIR_FRINT_10 (0x00000400UL) +#define USBHS_HFIR_FRINT_11 (0x00000800UL) +#define USBHS_HFIR_FRINT_12 (0x00001000UL) +#define USBHS_HFIR_FRINT_13 (0x00002000UL) +#define USBHS_HFIR_FRINT_14 (0x00004000UL) +#define USBHS_HFIR_FRINT_15 (0x00008000UL) +#define USBHS_HFIR_HFIRRLDCTRL_POS (16U) +#define USBHS_HFIR_HFIRRLDCTRL (0x00010000UL) + +/* Bit definition for USBHS_HFNUM register */ +#define USBHS_HFNUM_FRNUM_POS (0U) +#define USBHS_HFNUM_FRNUM (0x0000FFFFUL) +#define USBHS_HFNUM_FRNUM_0 (0x00000001UL) +#define USBHS_HFNUM_FRNUM_1 (0x00000002UL) +#define USBHS_HFNUM_FRNUM_2 (0x00000004UL) +#define USBHS_HFNUM_FRNUM_3 (0x00000008UL) +#define USBHS_HFNUM_FRNUM_4 (0x00000010UL) +#define USBHS_HFNUM_FRNUM_5 (0x00000020UL) +#define USBHS_HFNUM_FRNUM_6 (0x00000040UL) +#define USBHS_HFNUM_FRNUM_7 (0x00000080UL) +#define USBHS_HFNUM_FRNUM_8 (0x00000100UL) +#define USBHS_HFNUM_FRNUM_9 (0x00000200UL) +#define USBHS_HFNUM_FRNUM_10 (0x00000400UL) +#define USBHS_HFNUM_FRNUM_11 (0x00000800UL) +#define USBHS_HFNUM_FRNUM_12 (0x00001000UL) +#define USBHS_HFNUM_FRNUM_13 (0x00002000UL) +#define USBHS_HFNUM_FRNUM_14 (0x00004000UL) +#define USBHS_HFNUM_FRNUM_15 (0x00008000UL) +#define USBHS_HFNUM_FRREM_POS (16U) +#define USBHS_HFNUM_FRREM (0xFFFF0000UL) +#define USBHS_HFNUM_FRREM_0 (0x00010000UL) +#define USBHS_HFNUM_FRREM_1 (0x00020000UL) +#define USBHS_HFNUM_FRREM_2 (0x00040000UL) +#define USBHS_HFNUM_FRREM_3 (0x00080000UL) +#define USBHS_HFNUM_FRREM_4 (0x00100000UL) +#define USBHS_HFNUM_FRREM_5 (0x00200000UL) +#define USBHS_HFNUM_FRREM_6 (0x00400000UL) +#define USBHS_HFNUM_FRREM_7 (0x00800000UL) +#define USBHS_HFNUM_FRREM_8 (0x01000000UL) +#define USBHS_HFNUM_FRREM_9 (0x02000000UL) +#define USBHS_HFNUM_FRREM_10 (0x04000000UL) +#define USBHS_HFNUM_FRREM_11 (0x08000000UL) +#define USBHS_HFNUM_FRREM_12 (0x10000000UL) +#define USBHS_HFNUM_FRREM_13 (0x20000000UL) +#define USBHS_HFNUM_FRREM_14 (0x40000000UL) +#define USBHS_HFNUM_FRREM_15 (0x80000000UL) + +/* Bit definition for USBHS_HPTXSTS register */ +#define USBHS_HPTXSTS_PTXFSPCAVAIL_POS (0U) +#define USBHS_HPTXSTS_PTXFSPCAVAIL (0x0000FFFFUL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_0 (0x00000001UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_1 (0x00000002UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_2 (0x00000004UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_3 (0x00000008UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_4 (0x00000010UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_5 (0x00000020UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_6 (0x00000040UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_7 (0x00000080UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_8 (0x00000100UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_9 (0x00000200UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_10 (0x00000400UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_11 (0x00000800UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_12 (0x00001000UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_13 (0x00002000UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_14 (0x00004000UL) +#define USBHS_HPTXSTS_PTXFSPCAVAIL_15 (0x00008000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_POS (16U) +#define USBHS_HPTXSTS_PTXQSPCAVAIL (0x00FF0000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_0 (0x00010000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_1 (0x00020000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_2 (0x00040000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_3 (0x00080000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_4 (0x00100000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_5 (0x00200000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_6 (0x00400000UL) +#define USBHS_HPTXSTS_PTXQSPCAVAIL_7 (0x00800000UL) +#define USBHS_HPTXSTS_PTXQTOP_POS (24U) +#define USBHS_HPTXSTS_PTXQTOP (0xFF000000UL) +#define USBHS_HPTXSTS_PTXQTOP_0 (0x01000000UL) +#define USBHS_HPTXSTS_PTXQTOP_1 (0x02000000UL) +#define USBHS_HPTXSTS_PTXQTOP_2 (0x04000000UL) +#define USBHS_HPTXSTS_PTXQTOP_3 (0x08000000UL) +#define USBHS_HPTXSTS_PTXQTOP_4 (0x10000000UL) +#define USBHS_HPTXSTS_PTXQTOP_5 (0x20000000UL) +#define USBHS_HPTXSTS_PTXQTOP_6 (0x40000000UL) +#define USBHS_HPTXSTS_PTXQTOP_7 (0x80000000UL) + +/* Bit definition for USBHS_HAINT register */ +#define USBHS_HAINT_HAINT (0x0000FFFFUL) + +/* Bit definition for USBHS_HAINTMSK register */ +#define USBHS_HAINTMSK_HAINTMSK (0x0000FFFFUL) + +/* Bit definition for USBHS_HPRT register */ +#define USBHS_HPRT_PRTCONNSTS_POS (0U) +#define USBHS_HPRT_PRTCONNSTS (0x00000001UL) +#define USBHS_HPRT_PRTCONNDET_POS (1U) +#define USBHS_HPRT_PRTCONNDET (0x00000002UL) +#define USBHS_HPRT_PRTENA_POS (2U) +#define USBHS_HPRT_PRTENA (0x00000004UL) +#define USBHS_HPRT_PRTENCHNG_POS (3U) +#define USBHS_HPRT_PRTENCHNG (0x00000008UL) +#define USBHS_HPRT_PRTOVRCURRACT_POS (4U) +#define USBHS_HPRT_PRTOVRCURRACT (0x00000010UL) +#define USBHS_HPRT_PRTOVRCURRCHNG_POS (5U) +#define USBHS_HPRT_PRTOVRCURRCHNG (0x00000020UL) +#define USBHS_HPRT_PRTRES_POS (6U) +#define USBHS_HPRT_PRTRES (0x00000040UL) +#define USBHS_HPRT_PRTSUSP_POS (7U) +#define USBHS_HPRT_PRTSUSP (0x00000080UL) +#define USBHS_HPRT_PRTRST_POS (8U) +#define USBHS_HPRT_PRTRST (0x00000100UL) +#define USBHS_HPRT_PRTLNSTS_POS (10U) +#define USBHS_HPRT_PRTLNSTS (0x00000C00UL) +#define USBHS_HPRT_PRTLNSTS_0 (0x00000400UL) +#define USBHS_HPRT_PRTLNSTS_1 (0x00000800UL) +#define USBHS_HPRT_PRTPWR_POS (12U) +#define USBHS_HPRT_PRTPWR (0x00001000UL) +#define USBHS_HPRT_PRTTSTCTL_POS (13U) +#define USBHS_HPRT_PRTTSTCTL (0x0001E000UL) +#define USBHS_HPRT_PRTTSTCTL_0 (0x00002000UL) +#define USBHS_HPRT_PRTTSTCTL_1 (0x00004000UL) +#define USBHS_HPRT_PRTTSTCTL_2 (0x00008000UL) +#define USBHS_HPRT_PRTTSTCTL_3 (0x00010000UL) +#define USBHS_HPRT_PRTSPD_POS (17U) +#define USBHS_HPRT_PRTSPD (0x00060000UL) +#define USBHS_HPRT_PRTSPD_0 (0x00020000UL) +#define USBHS_HPRT_PRTSPD_1 (0x00040000UL) + +/* Bit definition for USBHS_HCCHAR0 register */ +#define USBHS_HCCHAR0_MPS_POS (0U) +#define USBHS_HCCHAR0_MPS (0x000007FFUL) +#define USBHS_HCCHAR0_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR0_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR0_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR0_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR0_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR0_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR0_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR0_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR0_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR0_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR0_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR0_EPNUM_POS (11U) +#define USBHS_HCCHAR0_EPNUM (0x00007800UL) +#define USBHS_HCCHAR0_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR0_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR0_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR0_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR0_EPDIR_POS (15U) +#define USBHS_HCCHAR0_EPDIR (0x00008000UL) +#define USBHS_HCCHAR0_LSPDDEV_POS (17U) +#define USBHS_HCCHAR0_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR0_EPTYPE_POS (18U) +#define USBHS_HCCHAR0_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR0_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR0_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR0_EC_POS (20U) +#define USBHS_HCCHAR0_EC (0x00300000UL) +#define USBHS_HCCHAR0_EC_0 (0x00100000UL) +#define USBHS_HCCHAR0_EC_1 (0x00200000UL) +#define USBHS_HCCHAR0_DEVADDR_POS (22U) +#define USBHS_HCCHAR0_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR0_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR0_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR0_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR0_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR0_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR0_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR0_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR0_ODDFRM_POS (29U) +#define USBHS_HCCHAR0_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR0_CHDIS_POS (30U) +#define USBHS_HCCHAR0_CHDIS (0x40000000UL) +#define USBHS_HCCHAR0_CHENA_POS (31U) +#define USBHS_HCCHAR0_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT0 register */ +#define USBHS_HCSPLT0_PRTADDR_POS (0U) +#define USBHS_HCSPLT0_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT0_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT0_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT0_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT0_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT0_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT0_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT0_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT0_HUBADDR_POS (7U) +#define USBHS_HCSPLT0_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT0_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT0_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT0_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT0_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT0_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT0_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT0_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT0_XACTPOS_POS (14U) +#define USBHS_HCSPLT0_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT0_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT0_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT0_COMPSPLT_POS (16U) +#define USBHS_HCSPLT0_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT0_SPLTENA_POS (31U) +#define USBHS_HCSPLT0_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT0 register */ +#define USBHS_HCINT0_XFERCOMPL_POS (0U) +#define USBHS_HCINT0_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT0_CHHLTD_POS (1U) +#define USBHS_HCINT0_CHHLTD (0x00000002UL) +#define USBHS_HCINT0_AHBERR_POS (2U) +#define USBHS_HCINT0_AHBERR (0x00000004UL) +#define USBHS_HCINT0_STALL_POS (3U) +#define USBHS_HCINT0_STALL (0x00000008UL) +#define USBHS_HCINT0_NAK_POS (4U) +#define USBHS_HCINT0_NAK (0x00000010UL) +#define USBHS_HCINT0_ACK_POS (5U) +#define USBHS_HCINT0_ACK (0x00000020UL) +#define USBHS_HCINT0_NYET_POS (6U) +#define USBHS_HCINT0_NYET (0x00000040UL) +#define USBHS_HCINT0_XACTERR_POS (7U) +#define USBHS_HCINT0_XACTERR (0x00000080UL) +#define USBHS_HCINT0_BBLERR_POS (8U) +#define USBHS_HCINT0_BBLERR (0x00000100UL) +#define USBHS_HCINT0_FRMOVRUN_POS (9U) +#define USBHS_HCINT0_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT0_DATATGLERR_POS (10U) +#define USBHS_HCINT0_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK0 register */ +#define USBHS_HCINTMSK0_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK0_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK0_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK0_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK0_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK0_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK0_STALLMSK_POS (3U) +#define USBHS_HCINTMSK0_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK0_NAKMSK_POS (4U) +#define USBHS_HCINTMSK0_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK0_ACKMSK_POS (5U) +#define USBHS_HCINTMSK0_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK0_NYETMSK_POS (6U) +#define USBHS_HCINTMSK0_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK0_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK0_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK0_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK0_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK0_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK0_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK0_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK0_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ0 register */ +#define USBHS_HCTSIZ0_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ0_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ0_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ0_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ0_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ0_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ0_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ0_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ0_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ0_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ0_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ0_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ0_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ0_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ0_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ0_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ0_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ0_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ0_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ0_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ0_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ0_PKTCNT_POS (19U) +#define USBHS_HCTSIZ0_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ0_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ0_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ0_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ0_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ0_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ0_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ0_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ0_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ0_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ0_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ0_PID_POS (29U) +#define USBHS_HCTSIZ0_PID (0x60000000UL) +#define USBHS_HCTSIZ0_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ0_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ0_DOPNG_POS (31U) +#define USBHS_HCTSIZ0_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA0 register */ +#define USBHS_HCDMA0 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR1 register */ +#define USBHS_HCCHAR1_MPS_POS (0U) +#define USBHS_HCCHAR1_MPS (0x000007FFUL) +#define USBHS_HCCHAR1_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR1_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR1_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR1_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR1_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR1_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR1_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR1_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR1_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR1_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR1_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR1_EPNUM_POS (11U) +#define USBHS_HCCHAR1_EPNUM (0x00007800UL) +#define USBHS_HCCHAR1_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR1_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR1_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR1_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR1_EPDIR_POS (15U) +#define USBHS_HCCHAR1_EPDIR (0x00008000UL) +#define USBHS_HCCHAR1_LSPDDEV_POS (17U) +#define USBHS_HCCHAR1_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR1_EPTYPE_POS (18U) +#define USBHS_HCCHAR1_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR1_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR1_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR1_EC_POS (20U) +#define USBHS_HCCHAR1_EC (0x00300000UL) +#define USBHS_HCCHAR1_EC_0 (0x00100000UL) +#define USBHS_HCCHAR1_EC_1 (0x00200000UL) +#define USBHS_HCCHAR1_DEVADDR_POS (22U) +#define USBHS_HCCHAR1_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR1_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR1_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR1_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR1_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR1_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR1_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR1_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR1_ODDFRM_POS (29U) +#define USBHS_HCCHAR1_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR1_CHDIS_POS (30U) +#define USBHS_HCCHAR1_CHDIS (0x40000000UL) +#define USBHS_HCCHAR1_CHENA_POS (31U) +#define USBHS_HCCHAR1_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT1 register */ +#define USBHS_HCSPLT1_PRTADDR_POS (0U) +#define USBHS_HCSPLT1_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT1_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT1_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT1_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT1_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT1_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT1_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT1_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT1_HUBADDR_POS (7U) +#define USBHS_HCSPLT1_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT1_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT1_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT1_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT1_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT1_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT1_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT1_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT1_XACTPOS_POS (14U) +#define USBHS_HCSPLT1_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT1_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT1_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT1_COMPSPLT_POS (16U) +#define USBHS_HCSPLT1_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT1_SPLTENA_POS (31U) +#define USBHS_HCSPLT1_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT1 register */ +#define USBHS_HCINT1_XFERCOMPL_POS (0U) +#define USBHS_HCINT1_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT1_CHHLTD_POS (1U) +#define USBHS_HCINT1_CHHLTD (0x00000002UL) +#define USBHS_HCINT1_AHBERR_POS (2U) +#define USBHS_HCINT1_AHBERR (0x00000004UL) +#define USBHS_HCINT1_STALL_POS (3U) +#define USBHS_HCINT1_STALL (0x00000008UL) +#define USBHS_HCINT1_NAK_POS (4U) +#define USBHS_HCINT1_NAK (0x00000010UL) +#define USBHS_HCINT1_ACK_POS (5U) +#define USBHS_HCINT1_ACK (0x00000020UL) +#define USBHS_HCINT1_NYET_POS (6U) +#define USBHS_HCINT1_NYET (0x00000040UL) +#define USBHS_HCINT1_XACTERR_POS (7U) +#define USBHS_HCINT1_XACTERR (0x00000080UL) +#define USBHS_HCINT1_BBLERR_POS (8U) +#define USBHS_HCINT1_BBLERR (0x00000100UL) +#define USBHS_HCINT1_FRMOVRUN_POS (9U) +#define USBHS_HCINT1_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT1_DATATGLERR_POS (10U) +#define USBHS_HCINT1_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK1 register */ +#define USBHS_HCINTMSK1_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK1_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK1_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK1_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK1_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK1_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK1_STALLMSK_POS (3U) +#define USBHS_HCINTMSK1_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK1_NAKMSK_POS (4U) +#define USBHS_HCINTMSK1_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK1_ACKMSK_POS (5U) +#define USBHS_HCINTMSK1_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK1_NYETMSK_POS (6U) +#define USBHS_HCINTMSK1_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK1_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK1_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK1_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK1_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK1_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK1_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK1_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK1_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ1 register */ +#define USBHS_HCTSIZ1_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ1_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ1_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ1_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ1_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ1_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ1_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ1_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ1_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ1_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ1_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ1_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ1_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ1_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ1_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ1_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ1_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ1_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ1_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ1_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ1_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ1_PKTCNT_POS (19U) +#define USBHS_HCTSIZ1_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ1_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ1_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ1_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ1_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ1_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ1_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ1_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ1_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ1_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ1_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ1_PID_POS (29U) +#define USBHS_HCTSIZ1_PID (0x60000000UL) +#define USBHS_HCTSIZ1_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ1_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ1_DOPNG_POS (31U) +#define USBHS_HCTSIZ1_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA1 register */ +#define USBHS_HCDMA1 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR2 register */ +#define USBHS_HCCHAR2_MPS_POS (0U) +#define USBHS_HCCHAR2_MPS (0x000007FFUL) +#define USBHS_HCCHAR2_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR2_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR2_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR2_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR2_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR2_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR2_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR2_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR2_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR2_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR2_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR2_EPNUM_POS (11U) +#define USBHS_HCCHAR2_EPNUM (0x00007800UL) +#define USBHS_HCCHAR2_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR2_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR2_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR2_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR2_EPDIR_POS (15U) +#define USBHS_HCCHAR2_EPDIR (0x00008000UL) +#define USBHS_HCCHAR2_LSPDDEV_POS (17U) +#define USBHS_HCCHAR2_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR2_EPTYPE_POS (18U) +#define USBHS_HCCHAR2_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR2_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR2_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR2_EC_POS (20U) +#define USBHS_HCCHAR2_EC (0x00300000UL) +#define USBHS_HCCHAR2_EC_0 (0x00100000UL) +#define USBHS_HCCHAR2_EC_1 (0x00200000UL) +#define USBHS_HCCHAR2_DEVADDR_POS (22U) +#define USBHS_HCCHAR2_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR2_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR2_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR2_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR2_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR2_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR2_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR2_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR2_ODDFRM_POS (29U) +#define USBHS_HCCHAR2_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR2_CHDIS_POS (30U) +#define USBHS_HCCHAR2_CHDIS (0x40000000UL) +#define USBHS_HCCHAR2_CHENA_POS (31U) +#define USBHS_HCCHAR2_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT2 register */ +#define USBHS_HCSPLT2_PRTADDR_POS (0U) +#define USBHS_HCSPLT2_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT2_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT2_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT2_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT2_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT2_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT2_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT2_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT2_HUBADDR_POS (7U) +#define USBHS_HCSPLT2_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT2_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT2_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT2_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT2_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT2_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT2_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT2_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT2_XACTPOS_POS (14U) +#define USBHS_HCSPLT2_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT2_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT2_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT2_COMPSPLT_POS (16U) +#define USBHS_HCSPLT2_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT2_SPLTENA_POS (31U) +#define USBHS_HCSPLT2_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT2 register */ +#define USBHS_HCINT2_XFERCOMPL_POS (0U) +#define USBHS_HCINT2_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT2_CHHLTD_POS (1U) +#define USBHS_HCINT2_CHHLTD (0x00000002UL) +#define USBHS_HCINT2_AHBERR_POS (2U) +#define USBHS_HCINT2_AHBERR (0x00000004UL) +#define USBHS_HCINT2_STALL_POS (3U) +#define USBHS_HCINT2_STALL (0x00000008UL) +#define USBHS_HCINT2_NAK_POS (4U) +#define USBHS_HCINT2_NAK (0x00000010UL) +#define USBHS_HCINT2_ACK_POS (5U) +#define USBHS_HCINT2_ACK (0x00000020UL) +#define USBHS_HCINT2_NYET_POS (6U) +#define USBHS_HCINT2_NYET (0x00000040UL) +#define USBHS_HCINT2_XACTERR_POS (7U) +#define USBHS_HCINT2_XACTERR (0x00000080UL) +#define USBHS_HCINT2_BBLERR_POS (8U) +#define USBHS_HCINT2_BBLERR (0x00000100UL) +#define USBHS_HCINT2_FRMOVRUN_POS (9U) +#define USBHS_HCINT2_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT2_DATATGLERR_POS (10U) +#define USBHS_HCINT2_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK2 register */ +#define USBHS_HCINTMSK2_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK2_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK2_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK2_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK2_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK2_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK2_STALLMSK_POS (3U) +#define USBHS_HCINTMSK2_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK2_NAKMSK_POS (4U) +#define USBHS_HCINTMSK2_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK2_ACKMSK_POS (5U) +#define USBHS_HCINTMSK2_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK2_NYETMSK_POS (6U) +#define USBHS_HCINTMSK2_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK2_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK2_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK2_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK2_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK2_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK2_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK2_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK2_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ2 register */ +#define USBHS_HCTSIZ2_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ2_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ2_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ2_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ2_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ2_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ2_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ2_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ2_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ2_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ2_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ2_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ2_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ2_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ2_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ2_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ2_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ2_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ2_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ2_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ2_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ2_PKTCNT_POS (19U) +#define USBHS_HCTSIZ2_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ2_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ2_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ2_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ2_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ2_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ2_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ2_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ2_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ2_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ2_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ2_PID_POS (29U) +#define USBHS_HCTSIZ2_PID (0x60000000UL) +#define USBHS_HCTSIZ2_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ2_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ2_DOPNG_POS (31U) +#define USBHS_HCTSIZ2_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA2 register */ +#define USBHS_HCDMA2 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR3 register */ +#define USBHS_HCCHAR3_MPS_POS (0U) +#define USBHS_HCCHAR3_MPS (0x000007FFUL) +#define USBHS_HCCHAR3_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR3_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR3_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR3_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR3_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR3_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR3_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR3_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR3_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR3_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR3_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR3_EPNUM_POS (11U) +#define USBHS_HCCHAR3_EPNUM (0x00007800UL) +#define USBHS_HCCHAR3_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR3_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR3_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR3_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR3_EPDIR_POS (15U) +#define USBHS_HCCHAR3_EPDIR (0x00008000UL) +#define USBHS_HCCHAR3_LSPDDEV_POS (17U) +#define USBHS_HCCHAR3_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR3_EPTYPE_POS (18U) +#define USBHS_HCCHAR3_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR3_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR3_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR3_EC_POS (20U) +#define USBHS_HCCHAR3_EC (0x00300000UL) +#define USBHS_HCCHAR3_EC_0 (0x00100000UL) +#define USBHS_HCCHAR3_EC_1 (0x00200000UL) +#define USBHS_HCCHAR3_DEVADDR_POS (22U) +#define USBHS_HCCHAR3_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR3_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR3_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR3_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR3_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR3_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR3_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR3_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR3_ODDFRM_POS (29U) +#define USBHS_HCCHAR3_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR3_CHDIS_POS (30U) +#define USBHS_HCCHAR3_CHDIS (0x40000000UL) +#define USBHS_HCCHAR3_CHENA_POS (31U) +#define USBHS_HCCHAR3_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT3 register */ +#define USBHS_HCSPLT3_PRTADDR_POS (0U) +#define USBHS_HCSPLT3_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT3_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT3_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT3_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT3_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT3_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT3_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT3_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT3_HUBADDR_POS (7U) +#define USBHS_HCSPLT3_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT3_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT3_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT3_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT3_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT3_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT3_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT3_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT3_XACTPOS_POS (14U) +#define USBHS_HCSPLT3_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT3_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT3_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT3_COMPSPLT_POS (16U) +#define USBHS_HCSPLT3_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT3_SPLTENA_POS (31U) +#define USBHS_HCSPLT3_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT3 register */ +#define USBHS_HCINT3_XFERCOMPL_POS (0U) +#define USBHS_HCINT3_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT3_CHHLTD_POS (1U) +#define USBHS_HCINT3_CHHLTD (0x00000002UL) +#define USBHS_HCINT3_AHBERR_POS (2U) +#define USBHS_HCINT3_AHBERR (0x00000004UL) +#define USBHS_HCINT3_STALL_POS (3U) +#define USBHS_HCINT3_STALL (0x00000008UL) +#define USBHS_HCINT3_NAK_POS (4U) +#define USBHS_HCINT3_NAK (0x00000010UL) +#define USBHS_HCINT3_ACK_POS (5U) +#define USBHS_HCINT3_ACK (0x00000020UL) +#define USBHS_HCINT3_NYET_POS (6U) +#define USBHS_HCINT3_NYET (0x00000040UL) +#define USBHS_HCINT3_XACTERR_POS (7U) +#define USBHS_HCINT3_XACTERR (0x00000080UL) +#define USBHS_HCINT3_BBLERR_POS (8U) +#define USBHS_HCINT3_BBLERR (0x00000100UL) +#define USBHS_HCINT3_FRMOVRUN_POS (9U) +#define USBHS_HCINT3_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT3_DATATGLERR_POS (10U) +#define USBHS_HCINT3_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK3 register */ +#define USBHS_HCINTMSK3_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK3_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK3_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK3_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK3_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK3_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK3_STALLMSK_POS (3U) +#define USBHS_HCINTMSK3_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK3_NAKMSK_POS (4U) +#define USBHS_HCINTMSK3_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK3_ACKMSK_POS (5U) +#define USBHS_HCINTMSK3_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK3_NYETMSK_POS (6U) +#define USBHS_HCINTMSK3_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK3_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK3_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK3_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK3_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK3_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK3_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK3_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK3_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ3 register */ +#define USBHS_HCTSIZ3_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ3_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ3_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ3_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ3_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ3_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ3_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ3_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ3_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ3_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ3_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ3_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ3_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ3_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ3_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ3_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ3_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ3_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ3_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ3_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ3_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ3_PKTCNT_POS (19U) +#define USBHS_HCTSIZ3_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ3_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ3_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ3_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ3_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ3_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ3_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ3_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ3_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ3_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ3_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ3_PID_POS (29U) +#define USBHS_HCTSIZ3_PID (0x60000000UL) +#define USBHS_HCTSIZ3_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ3_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ3_DOPNG_POS (31U) +#define USBHS_HCTSIZ3_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA3 register */ +#define USBHS_HCDMA3 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR4 register */ +#define USBHS_HCCHAR4_MPS_POS (0U) +#define USBHS_HCCHAR4_MPS (0x000007FFUL) +#define USBHS_HCCHAR4_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR4_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR4_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR4_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR4_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR4_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR4_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR4_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR4_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR4_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR4_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR4_EPNUM_POS (11U) +#define USBHS_HCCHAR4_EPNUM (0x00007800UL) +#define USBHS_HCCHAR4_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR4_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR4_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR4_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR4_EPDIR_POS (15U) +#define USBHS_HCCHAR4_EPDIR (0x00008000UL) +#define USBHS_HCCHAR4_LSPDDEV_POS (17U) +#define USBHS_HCCHAR4_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR4_EPTYPE_POS (18U) +#define USBHS_HCCHAR4_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR4_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR4_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR4_EC_POS (20U) +#define USBHS_HCCHAR4_EC (0x00300000UL) +#define USBHS_HCCHAR4_EC_0 (0x00100000UL) +#define USBHS_HCCHAR4_EC_1 (0x00200000UL) +#define USBHS_HCCHAR4_DEVADDR_POS (22U) +#define USBHS_HCCHAR4_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR4_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR4_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR4_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR4_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR4_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR4_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR4_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR4_ODDFRM_POS (29U) +#define USBHS_HCCHAR4_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR4_CHDIS_POS (30U) +#define USBHS_HCCHAR4_CHDIS (0x40000000UL) +#define USBHS_HCCHAR4_CHENA_POS (31U) +#define USBHS_HCCHAR4_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT4 register */ +#define USBHS_HCSPLT4_PRTADDR_POS (0U) +#define USBHS_HCSPLT4_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT4_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT4_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT4_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT4_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT4_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT4_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT4_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT4_HUBADDR_POS (7U) +#define USBHS_HCSPLT4_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT4_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT4_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT4_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT4_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT4_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT4_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT4_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT4_XACTPOS_POS (14U) +#define USBHS_HCSPLT4_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT4_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT4_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT4_COMPSPLT_POS (16U) +#define USBHS_HCSPLT4_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT4_SPLTENA_POS (31U) +#define USBHS_HCSPLT4_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT4 register */ +#define USBHS_HCINT4_XFERCOMPL_POS (0U) +#define USBHS_HCINT4_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT4_CHHLTD_POS (1U) +#define USBHS_HCINT4_CHHLTD (0x00000002UL) +#define USBHS_HCINT4_AHBERR_POS (2U) +#define USBHS_HCINT4_AHBERR (0x00000004UL) +#define USBHS_HCINT4_STALL_POS (3U) +#define USBHS_HCINT4_STALL (0x00000008UL) +#define USBHS_HCINT4_NAK_POS (4U) +#define USBHS_HCINT4_NAK (0x00000010UL) +#define USBHS_HCINT4_ACK_POS (5U) +#define USBHS_HCINT4_ACK (0x00000020UL) +#define USBHS_HCINT4_NYET_POS (6U) +#define USBHS_HCINT4_NYET (0x00000040UL) +#define USBHS_HCINT4_XACTERR_POS (7U) +#define USBHS_HCINT4_XACTERR (0x00000080UL) +#define USBHS_HCINT4_BBLERR_POS (8U) +#define USBHS_HCINT4_BBLERR (0x00000100UL) +#define USBHS_HCINT4_FRMOVRUN_POS (9U) +#define USBHS_HCINT4_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT4_DATATGLERR_POS (10U) +#define USBHS_HCINT4_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK4 register */ +#define USBHS_HCINTMSK4_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK4_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK4_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK4_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK4_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK4_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK4_STALLMSK_POS (3U) +#define USBHS_HCINTMSK4_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK4_NAKMSK_POS (4U) +#define USBHS_HCINTMSK4_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK4_ACKMSK_POS (5U) +#define USBHS_HCINTMSK4_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK4_NYETMSK_POS (6U) +#define USBHS_HCINTMSK4_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK4_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK4_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK4_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK4_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK4_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK4_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK4_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK4_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ4 register */ +#define USBHS_HCTSIZ4_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ4_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ4_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ4_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ4_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ4_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ4_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ4_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ4_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ4_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ4_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ4_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ4_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ4_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ4_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ4_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ4_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ4_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ4_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ4_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ4_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ4_PKTCNT_POS (19U) +#define USBHS_HCTSIZ4_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ4_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ4_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ4_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ4_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ4_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ4_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ4_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ4_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ4_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ4_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ4_PID_POS (29U) +#define USBHS_HCTSIZ4_PID (0x60000000UL) +#define USBHS_HCTSIZ4_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ4_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ4_DOPNG_POS (31U) +#define USBHS_HCTSIZ4_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA4 register */ +#define USBHS_HCDMA4 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR5 register */ +#define USBHS_HCCHAR5_MPS_POS (0U) +#define USBHS_HCCHAR5_MPS (0x000007FFUL) +#define USBHS_HCCHAR5_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR5_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR5_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR5_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR5_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR5_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR5_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR5_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR5_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR5_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR5_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR5_EPNUM_POS (11U) +#define USBHS_HCCHAR5_EPNUM (0x00007800UL) +#define USBHS_HCCHAR5_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR5_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR5_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR5_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR5_EPDIR_POS (15U) +#define USBHS_HCCHAR5_EPDIR (0x00008000UL) +#define USBHS_HCCHAR5_LSPDDEV_POS (17U) +#define USBHS_HCCHAR5_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR5_EPTYPE_POS (18U) +#define USBHS_HCCHAR5_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR5_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR5_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR5_EC_POS (20U) +#define USBHS_HCCHAR5_EC (0x00300000UL) +#define USBHS_HCCHAR5_EC_0 (0x00100000UL) +#define USBHS_HCCHAR5_EC_1 (0x00200000UL) +#define USBHS_HCCHAR5_DEVADDR_POS (22U) +#define USBHS_HCCHAR5_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR5_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR5_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR5_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR5_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR5_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR5_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR5_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR5_ODDFRM_POS (29U) +#define USBHS_HCCHAR5_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR5_CHDIS_POS (30U) +#define USBHS_HCCHAR5_CHDIS (0x40000000UL) +#define USBHS_HCCHAR5_CHENA_POS (31U) +#define USBHS_HCCHAR5_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT5 register */ +#define USBHS_HCSPLT5_PRTADDR_POS (0U) +#define USBHS_HCSPLT5_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT5_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT5_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT5_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT5_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT5_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT5_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT5_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT5_HUBADDR_POS (7U) +#define USBHS_HCSPLT5_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT5_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT5_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT5_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT5_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT5_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT5_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT5_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT5_XACTPOS_POS (14U) +#define USBHS_HCSPLT5_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT5_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT5_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT5_COMPSPLT_POS (16U) +#define USBHS_HCSPLT5_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT5_SPLTENA_POS (31U) +#define USBHS_HCSPLT5_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT5 register */ +#define USBHS_HCINT5_XFERCOMPL_POS (0U) +#define USBHS_HCINT5_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT5_CHHLTD_POS (1U) +#define USBHS_HCINT5_CHHLTD (0x00000002UL) +#define USBHS_HCINT5_AHBERR_POS (2U) +#define USBHS_HCINT5_AHBERR (0x00000004UL) +#define USBHS_HCINT5_STALL_POS (3U) +#define USBHS_HCINT5_STALL (0x00000008UL) +#define USBHS_HCINT5_NAK_POS (4U) +#define USBHS_HCINT5_NAK (0x00000010UL) +#define USBHS_HCINT5_ACK_POS (5U) +#define USBHS_HCINT5_ACK (0x00000020UL) +#define USBHS_HCINT5_NYET_POS (6U) +#define USBHS_HCINT5_NYET (0x00000040UL) +#define USBHS_HCINT5_XACTERR_POS (7U) +#define USBHS_HCINT5_XACTERR (0x00000080UL) +#define USBHS_HCINT5_BBLERR_POS (8U) +#define USBHS_HCINT5_BBLERR (0x00000100UL) +#define USBHS_HCINT5_FRMOVRUN_POS (9U) +#define USBHS_HCINT5_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT5_DATATGLERR_POS (10U) +#define USBHS_HCINT5_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK5 register */ +#define USBHS_HCINTMSK5_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK5_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK5_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK5_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK5_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK5_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK5_STALLMSK_POS (3U) +#define USBHS_HCINTMSK5_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK5_NAKMSK_POS (4U) +#define USBHS_HCINTMSK5_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK5_ACKMSK_POS (5U) +#define USBHS_HCINTMSK5_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK5_NYETMSK_POS (6U) +#define USBHS_HCINTMSK5_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK5_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK5_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK5_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK5_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK5_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK5_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK5_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK5_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ5 register */ +#define USBHS_HCTSIZ5_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ5_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ5_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ5_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ5_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ5_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ5_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ5_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ5_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ5_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ5_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ5_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ5_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ5_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ5_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ5_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ5_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ5_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ5_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ5_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ5_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ5_PKTCNT_POS (19U) +#define USBHS_HCTSIZ5_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ5_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ5_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ5_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ5_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ5_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ5_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ5_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ5_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ5_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ5_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ5_PID_POS (29U) +#define USBHS_HCTSIZ5_PID (0x60000000UL) +#define USBHS_HCTSIZ5_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ5_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ5_DOPNG_POS (31U) +#define USBHS_HCTSIZ5_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA5 register */ +#define USBHS_HCDMA5 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR6 register */ +#define USBHS_HCCHAR6_MPS_POS (0U) +#define USBHS_HCCHAR6_MPS (0x000007FFUL) +#define USBHS_HCCHAR6_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR6_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR6_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR6_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR6_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR6_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR6_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR6_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR6_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR6_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR6_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR6_EPNUM_POS (11U) +#define USBHS_HCCHAR6_EPNUM (0x00007800UL) +#define USBHS_HCCHAR6_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR6_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR6_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR6_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR6_EPDIR_POS (15U) +#define USBHS_HCCHAR6_EPDIR (0x00008000UL) +#define USBHS_HCCHAR6_LSPDDEV_POS (17U) +#define USBHS_HCCHAR6_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR6_EPTYPE_POS (18U) +#define USBHS_HCCHAR6_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR6_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR6_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR6_EC_POS (20U) +#define USBHS_HCCHAR6_EC (0x00300000UL) +#define USBHS_HCCHAR6_EC_0 (0x00100000UL) +#define USBHS_HCCHAR6_EC_1 (0x00200000UL) +#define USBHS_HCCHAR6_DEVADDR_POS (22U) +#define USBHS_HCCHAR6_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR6_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR6_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR6_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR6_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR6_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR6_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR6_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR6_ODDFRM_POS (29U) +#define USBHS_HCCHAR6_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR6_CHDIS_POS (30U) +#define USBHS_HCCHAR6_CHDIS (0x40000000UL) +#define USBHS_HCCHAR6_CHENA_POS (31U) +#define USBHS_HCCHAR6_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT6 register */ +#define USBHS_HCSPLT6_PRTADDR_POS (0U) +#define USBHS_HCSPLT6_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT6_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT6_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT6_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT6_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT6_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT6_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT6_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT6_HUBADDR_POS (7U) +#define USBHS_HCSPLT6_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT6_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT6_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT6_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT6_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT6_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT6_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT6_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT6_XACTPOS_POS (14U) +#define USBHS_HCSPLT6_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT6_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT6_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT6_COMPSPLT_POS (16U) +#define USBHS_HCSPLT6_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT6_SPLTENA_POS (31U) +#define USBHS_HCSPLT6_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT6 register */ +#define USBHS_HCINT6_XFERCOMPL_POS (0U) +#define USBHS_HCINT6_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT6_CHHLTD_POS (1U) +#define USBHS_HCINT6_CHHLTD (0x00000002UL) +#define USBHS_HCINT6_AHBERR_POS (2U) +#define USBHS_HCINT6_AHBERR (0x00000004UL) +#define USBHS_HCINT6_STALL_POS (3U) +#define USBHS_HCINT6_STALL (0x00000008UL) +#define USBHS_HCINT6_NAK_POS (4U) +#define USBHS_HCINT6_NAK (0x00000010UL) +#define USBHS_HCINT6_ACK_POS (5U) +#define USBHS_HCINT6_ACK (0x00000020UL) +#define USBHS_HCINT6_NYET_POS (6U) +#define USBHS_HCINT6_NYET (0x00000040UL) +#define USBHS_HCINT6_XACTERR_POS (7U) +#define USBHS_HCINT6_XACTERR (0x00000080UL) +#define USBHS_HCINT6_BBLERR_POS (8U) +#define USBHS_HCINT6_BBLERR (0x00000100UL) +#define USBHS_HCINT6_FRMOVRUN_POS (9U) +#define USBHS_HCINT6_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT6_DATATGLERR_POS (10U) +#define USBHS_HCINT6_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK6 register */ +#define USBHS_HCINTMSK6_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK6_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK6_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK6_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK6_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK6_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK6_STALLMSK_POS (3U) +#define USBHS_HCINTMSK6_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK6_NAKMSK_POS (4U) +#define USBHS_HCINTMSK6_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK6_ACKMSK_POS (5U) +#define USBHS_HCINTMSK6_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK6_NYETMSK_POS (6U) +#define USBHS_HCINTMSK6_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK6_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK6_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK6_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK6_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK6_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK6_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK6_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK6_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ6 register */ +#define USBHS_HCTSIZ6_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ6_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ6_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ6_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ6_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ6_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ6_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ6_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ6_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ6_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ6_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ6_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ6_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ6_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ6_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ6_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ6_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ6_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ6_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ6_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ6_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ6_PKTCNT_POS (19U) +#define USBHS_HCTSIZ6_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ6_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ6_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ6_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ6_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ6_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ6_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ6_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ6_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ6_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ6_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ6_PID_POS (29U) +#define USBHS_HCTSIZ6_PID (0x60000000UL) +#define USBHS_HCTSIZ6_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ6_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ6_DOPNG_POS (31U) +#define USBHS_HCTSIZ6_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA6 register */ +#define USBHS_HCDMA6 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR7 register */ +#define USBHS_HCCHAR7_MPS_POS (0U) +#define USBHS_HCCHAR7_MPS (0x000007FFUL) +#define USBHS_HCCHAR7_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR7_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR7_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR7_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR7_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR7_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR7_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR7_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR7_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR7_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR7_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR7_EPNUM_POS (11U) +#define USBHS_HCCHAR7_EPNUM (0x00007800UL) +#define USBHS_HCCHAR7_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR7_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR7_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR7_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR7_EPDIR_POS (15U) +#define USBHS_HCCHAR7_EPDIR (0x00008000UL) +#define USBHS_HCCHAR7_LSPDDEV_POS (17U) +#define USBHS_HCCHAR7_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR7_EPTYPE_POS (18U) +#define USBHS_HCCHAR7_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR7_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR7_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR7_EC_POS (20U) +#define USBHS_HCCHAR7_EC (0x00300000UL) +#define USBHS_HCCHAR7_EC_0 (0x00100000UL) +#define USBHS_HCCHAR7_EC_1 (0x00200000UL) +#define USBHS_HCCHAR7_DEVADDR_POS (22U) +#define USBHS_HCCHAR7_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR7_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR7_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR7_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR7_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR7_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR7_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR7_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR7_ODDFRM_POS (29U) +#define USBHS_HCCHAR7_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR7_CHDIS_POS (30U) +#define USBHS_HCCHAR7_CHDIS (0x40000000UL) +#define USBHS_HCCHAR7_CHENA_POS (31U) +#define USBHS_HCCHAR7_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT7 register */ +#define USBHS_HCSPLT7_PRTADDR_POS (0U) +#define USBHS_HCSPLT7_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT7_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT7_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT7_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT7_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT7_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT7_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT7_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT7_HUBADDR_POS (7U) +#define USBHS_HCSPLT7_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT7_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT7_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT7_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT7_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT7_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT7_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT7_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT7_XACTPOS_POS (14U) +#define USBHS_HCSPLT7_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT7_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT7_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT7_COMPSPLT_POS (16U) +#define USBHS_HCSPLT7_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT7_SPLTENA_POS (31U) +#define USBHS_HCSPLT7_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT7 register */ +#define USBHS_HCINT7_XFERCOMPL_POS (0U) +#define USBHS_HCINT7_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT7_CHHLTD_POS (1U) +#define USBHS_HCINT7_CHHLTD (0x00000002UL) +#define USBHS_HCINT7_AHBERR_POS (2U) +#define USBHS_HCINT7_AHBERR (0x00000004UL) +#define USBHS_HCINT7_STALL_POS (3U) +#define USBHS_HCINT7_STALL (0x00000008UL) +#define USBHS_HCINT7_NAK_POS (4U) +#define USBHS_HCINT7_NAK (0x00000010UL) +#define USBHS_HCINT7_ACK_POS (5U) +#define USBHS_HCINT7_ACK (0x00000020UL) +#define USBHS_HCINT7_NYET_POS (6U) +#define USBHS_HCINT7_NYET (0x00000040UL) +#define USBHS_HCINT7_XACTERR_POS (7U) +#define USBHS_HCINT7_XACTERR (0x00000080UL) +#define USBHS_HCINT7_BBLERR_POS (8U) +#define USBHS_HCINT7_BBLERR (0x00000100UL) +#define USBHS_HCINT7_FRMOVRUN_POS (9U) +#define USBHS_HCINT7_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT7_DATATGLERR_POS (10U) +#define USBHS_HCINT7_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK7 register */ +#define USBHS_HCINTMSK7_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK7_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK7_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK7_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK7_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK7_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK7_STALLMSK_POS (3U) +#define USBHS_HCINTMSK7_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK7_NAKMSK_POS (4U) +#define USBHS_HCINTMSK7_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK7_ACKMSK_POS (5U) +#define USBHS_HCINTMSK7_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK7_NYETMSK_POS (6U) +#define USBHS_HCINTMSK7_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK7_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK7_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK7_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK7_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK7_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK7_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK7_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK7_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ7 register */ +#define USBHS_HCTSIZ7_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ7_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ7_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ7_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ7_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ7_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ7_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ7_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ7_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ7_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ7_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ7_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ7_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ7_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ7_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ7_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ7_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ7_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ7_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ7_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ7_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ7_PKTCNT_POS (19U) +#define USBHS_HCTSIZ7_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ7_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ7_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ7_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ7_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ7_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ7_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ7_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ7_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ7_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ7_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ7_PID_POS (29U) +#define USBHS_HCTSIZ7_PID (0x60000000UL) +#define USBHS_HCTSIZ7_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ7_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ7_DOPNG_POS (31U) +#define USBHS_HCTSIZ7_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA7 register */ +#define USBHS_HCDMA7 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR8 register */ +#define USBHS_HCCHAR8_MPS_POS (0U) +#define USBHS_HCCHAR8_MPS (0x000007FFUL) +#define USBHS_HCCHAR8_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR8_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR8_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR8_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR8_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR8_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR8_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR8_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR8_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR8_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR8_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR8_EPNUM_POS (11U) +#define USBHS_HCCHAR8_EPNUM (0x00007800UL) +#define USBHS_HCCHAR8_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR8_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR8_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR8_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR8_EPDIR_POS (15U) +#define USBHS_HCCHAR8_EPDIR (0x00008000UL) +#define USBHS_HCCHAR8_LSPDDEV_POS (17U) +#define USBHS_HCCHAR8_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR8_EPTYPE_POS (18U) +#define USBHS_HCCHAR8_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR8_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR8_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR8_EC_POS (20U) +#define USBHS_HCCHAR8_EC (0x00300000UL) +#define USBHS_HCCHAR8_EC_0 (0x00100000UL) +#define USBHS_HCCHAR8_EC_1 (0x00200000UL) +#define USBHS_HCCHAR8_DEVADDR_POS (22U) +#define USBHS_HCCHAR8_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR8_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR8_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR8_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR8_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR8_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR8_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR8_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR8_ODDFRM_POS (29U) +#define USBHS_HCCHAR8_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR8_CHDIS_POS (30U) +#define USBHS_HCCHAR8_CHDIS (0x40000000UL) +#define USBHS_HCCHAR8_CHENA_POS (31U) +#define USBHS_HCCHAR8_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT8 register */ +#define USBHS_HCSPLT8_PRTADDR_POS (0U) +#define USBHS_HCSPLT8_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT8_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT8_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT8_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT8_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT8_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT8_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT8_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT8_HUBADDR_POS (7U) +#define USBHS_HCSPLT8_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT8_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT8_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT8_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT8_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT8_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT8_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT8_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT8_XACTPOS_POS (14U) +#define USBHS_HCSPLT8_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT8_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT8_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT8_COMPSPLT_POS (16U) +#define USBHS_HCSPLT8_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT8_SPLTENA_POS (31U) +#define USBHS_HCSPLT8_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT8 register */ +#define USBHS_HCINT8_XFERCOMPL_POS (0U) +#define USBHS_HCINT8_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT8_CHHLTD_POS (1U) +#define USBHS_HCINT8_CHHLTD (0x00000002UL) +#define USBHS_HCINT8_AHBERR_POS (2U) +#define USBHS_HCINT8_AHBERR (0x00000004UL) +#define USBHS_HCINT8_STALL_POS (3U) +#define USBHS_HCINT8_STALL (0x00000008UL) +#define USBHS_HCINT8_NAK_POS (4U) +#define USBHS_HCINT8_NAK (0x00000010UL) +#define USBHS_HCINT8_ACK_POS (5U) +#define USBHS_HCINT8_ACK (0x00000020UL) +#define USBHS_HCINT8_NYET_POS (6U) +#define USBHS_HCINT8_NYET (0x00000040UL) +#define USBHS_HCINT8_XACTERR_POS (7U) +#define USBHS_HCINT8_XACTERR (0x00000080UL) +#define USBHS_HCINT8_BBLERR_POS (8U) +#define USBHS_HCINT8_BBLERR (0x00000100UL) +#define USBHS_HCINT8_FRMOVRUN_POS (9U) +#define USBHS_HCINT8_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT8_DATATGLERR_POS (10U) +#define USBHS_HCINT8_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK8 register */ +#define USBHS_HCINTMSK8_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK8_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK8_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK8_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK8_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK8_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK8_STALLMSK_POS (3U) +#define USBHS_HCINTMSK8_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK8_NAKMSK_POS (4U) +#define USBHS_HCINTMSK8_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK8_ACKMSK_POS (5U) +#define USBHS_HCINTMSK8_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK8_NYETMSK_POS (6U) +#define USBHS_HCINTMSK8_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK8_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK8_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK8_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK8_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK8_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK8_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK8_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK8_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ8 register */ +#define USBHS_HCTSIZ8_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ8_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ8_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ8_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ8_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ8_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ8_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ8_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ8_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ8_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ8_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ8_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ8_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ8_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ8_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ8_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ8_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ8_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ8_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ8_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ8_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ8_PKTCNT_POS (19U) +#define USBHS_HCTSIZ8_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ8_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ8_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ8_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ8_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ8_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ8_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ8_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ8_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ8_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ8_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ8_PID_POS (29U) +#define USBHS_HCTSIZ8_PID (0x60000000UL) +#define USBHS_HCTSIZ8_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ8_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ8_DOPNG_POS (31U) +#define USBHS_HCTSIZ8_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA8 register */ +#define USBHS_HCDMA8 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR9 register */ +#define USBHS_HCCHAR9_MPS_POS (0U) +#define USBHS_HCCHAR9_MPS (0x000007FFUL) +#define USBHS_HCCHAR9_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR9_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR9_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR9_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR9_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR9_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR9_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR9_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR9_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR9_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR9_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR9_EPNUM_POS (11U) +#define USBHS_HCCHAR9_EPNUM (0x00007800UL) +#define USBHS_HCCHAR9_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR9_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR9_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR9_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR9_EPDIR_POS (15U) +#define USBHS_HCCHAR9_EPDIR (0x00008000UL) +#define USBHS_HCCHAR9_LSPDDEV_POS (17U) +#define USBHS_HCCHAR9_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR9_EPTYPE_POS (18U) +#define USBHS_HCCHAR9_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR9_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR9_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR9_EC_POS (20U) +#define USBHS_HCCHAR9_EC (0x00300000UL) +#define USBHS_HCCHAR9_EC_0 (0x00100000UL) +#define USBHS_HCCHAR9_EC_1 (0x00200000UL) +#define USBHS_HCCHAR9_DEVADDR_POS (22U) +#define USBHS_HCCHAR9_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR9_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR9_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR9_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR9_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR9_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR9_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR9_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR9_ODDFRM_POS (29U) +#define USBHS_HCCHAR9_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR9_CHDIS_POS (30U) +#define USBHS_HCCHAR9_CHDIS (0x40000000UL) +#define USBHS_HCCHAR9_CHENA_POS (31U) +#define USBHS_HCCHAR9_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT9 register */ +#define USBHS_HCSPLT9_PRTADDR_POS (0U) +#define USBHS_HCSPLT9_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT9_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT9_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT9_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT9_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT9_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT9_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT9_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT9_HUBADDR_POS (7U) +#define USBHS_HCSPLT9_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT9_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT9_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT9_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT9_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT9_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT9_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT9_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT9_XACTPOS_POS (14U) +#define USBHS_HCSPLT9_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT9_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT9_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT9_COMPSPLT_POS (16U) +#define USBHS_HCSPLT9_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT9_SPLTENA_POS (31U) +#define USBHS_HCSPLT9_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT9 register */ +#define USBHS_HCINT9_XFERCOMPL_POS (0U) +#define USBHS_HCINT9_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT9_CHHLTD_POS (1U) +#define USBHS_HCINT9_CHHLTD (0x00000002UL) +#define USBHS_HCINT9_AHBERR_POS (2U) +#define USBHS_HCINT9_AHBERR (0x00000004UL) +#define USBHS_HCINT9_STALL_POS (3U) +#define USBHS_HCINT9_STALL (0x00000008UL) +#define USBHS_HCINT9_NAK_POS (4U) +#define USBHS_HCINT9_NAK (0x00000010UL) +#define USBHS_HCINT9_ACK_POS (5U) +#define USBHS_HCINT9_ACK (0x00000020UL) +#define USBHS_HCINT9_NYET_POS (6U) +#define USBHS_HCINT9_NYET (0x00000040UL) +#define USBHS_HCINT9_XACTERR_POS (7U) +#define USBHS_HCINT9_XACTERR (0x00000080UL) +#define USBHS_HCINT9_BBLERR_POS (8U) +#define USBHS_HCINT9_BBLERR (0x00000100UL) +#define USBHS_HCINT9_FRMOVRUN_POS (9U) +#define USBHS_HCINT9_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT9_DATATGLERR_POS (10U) +#define USBHS_HCINT9_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK9 register */ +#define USBHS_HCINTMSK9_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK9_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK9_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK9_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK9_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK9_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK9_STALLMSK_POS (3U) +#define USBHS_HCINTMSK9_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK9_NAKMSK_POS (4U) +#define USBHS_HCINTMSK9_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK9_ACKMSK_POS (5U) +#define USBHS_HCINTMSK9_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK9_NYETMSK_POS (6U) +#define USBHS_HCINTMSK9_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK9_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK9_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK9_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK9_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK9_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK9_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK9_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK9_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ9 register */ +#define USBHS_HCTSIZ9_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ9_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ9_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ9_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ9_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ9_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ9_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ9_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ9_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ9_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ9_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ9_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ9_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ9_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ9_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ9_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ9_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ9_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ9_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ9_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ9_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ9_PKTCNT_POS (19U) +#define USBHS_HCTSIZ9_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ9_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ9_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ9_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ9_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ9_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ9_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ9_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ9_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ9_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ9_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ9_PID_POS (29U) +#define USBHS_HCTSIZ9_PID (0x60000000UL) +#define USBHS_HCTSIZ9_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ9_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ9_DOPNG_POS (31U) +#define USBHS_HCTSIZ9_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA9 register */ +#define USBHS_HCDMA9 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR10 register */ +#define USBHS_HCCHAR10_MPS_POS (0U) +#define USBHS_HCCHAR10_MPS (0x000007FFUL) +#define USBHS_HCCHAR10_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR10_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR10_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR10_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR10_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR10_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR10_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR10_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR10_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR10_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR10_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR10_EPNUM_POS (11U) +#define USBHS_HCCHAR10_EPNUM (0x00007800UL) +#define USBHS_HCCHAR10_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR10_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR10_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR10_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR10_EPDIR_POS (15U) +#define USBHS_HCCHAR10_EPDIR (0x00008000UL) +#define USBHS_HCCHAR10_LSPDDEV_POS (17U) +#define USBHS_HCCHAR10_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR10_EPTYPE_POS (18U) +#define USBHS_HCCHAR10_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR10_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR10_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR10_EC_POS (20U) +#define USBHS_HCCHAR10_EC (0x00300000UL) +#define USBHS_HCCHAR10_EC_0 (0x00100000UL) +#define USBHS_HCCHAR10_EC_1 (0x00200000UL) +#define USBHS_HCCHAR10_DEVADDR_POS (22U) +#define USBHS_HCCHAR10_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR10_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR10_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR10_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR10_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR10_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR10_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR10_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR10_ODDFRM_POS (29U) +#define USBHS_HCCHAR10_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR10_CHDIS_POS (30U) +#define USBHS_HCCHAR10_CHDIS (0x40000000UL) +#define USBHS_HCCHAR10_CHENA_POS (31U) +#define USBHS_HCCHAR10_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT10 register */ +#define USBHS_HCSPLT10_PRTADDR_POS (0U) +#define USBHS_HCSPLT10_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT10_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT10_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT10_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT10_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT10_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT10_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT10_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT10_HUBADDR_POS (7U) +#define USBHS_HCSPLT10_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT10_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT10_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT10_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT10_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT10_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT10_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT10_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT10_XACTPOS_POS (14U) +#define USBHS_HCSPLT10_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT10_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT10_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT10_COMPSPLT_POS (16U) +#define USBHS_HCSPLT10_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT10_SPLTENA_POS (31U) +#define USBHS_HCSPLT10_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT10 register */ +#define USBHS_HCINT10_XFERCOMPL_POS (0U) +#define USBHS_HCINT10_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT10_CHHLTD_POS (1U) +#define USBHS_HCINT10_CHHLTD (0x00000002UL) +#define USBHS_HCINT10_AHBERR_POS (2U) +#define USBHS_HCINT10_AHBERR (0x00000004UL) +#define USBHS_HCINT10_STALL_POS (3U) +#define USBHS_HCINT10_STALL (0x00000008UL) +#define USBHS_HCINT10_NAK_POS (4U) +#define USBHS_HCINT10_NAK (0x00000010UL) +#define USBHS_HCINT10_ACK_POS (5U) +#define USBHS_HCINT10_ACK (0x00000020UL) +#define USBHS_HCINT10_NYET_POS (6U) +#define USBHS_HCINT10_NYET (0x00000040UL) +#define USBHS_HCINT10_XACTERR_POS (7U) +#define USBHS_HCINT10_XACTERR (0x00000080UL) +#define USBHS_HCINT10_BBLERR_POS (8U) +#define USBHS_HCINT10_BBLERR (0x00000100UL) +#define USBHS_HCINT10_FRMOVRUN_POS (9U) +#define USBHS_HCINT10_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT10_DATATGLERR_POS (10U) +#define USBHS_HCINT10_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK10 register */ +#define USBHS_HCINTMSK10_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK10_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK10_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK10_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK10_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK10_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK10_STALLMSK_POS (3U) +#define USBHS_HCINTMSK10_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK10_NAKMSK_POS (4U) +#define USBHS_HCINTMSK10_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK10_ACKMSK_POS (5U) +#define USBHS_HCINTMSK10_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK10_NYETMSK_POS (6U) +#define USBHS_HCINTMSK10_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK10_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK10_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK10_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK10_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK10_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK10_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK10_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK10_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ10 register */ +#define USBHS_HCTSIZ10_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ10_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ10_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ10_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ10_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ10_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ10_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ10_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ10_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ10_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ10_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ10_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ10_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ10_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ10_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ10_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ10_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ10_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ10_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ10_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ10_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ10_PKTCNT_POS (19U) +#define USBHS_HCTSIZ10_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ10_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ10_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ10_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ10_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ10_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ10_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ10_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ10_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ10_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ10_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ10_PID_POS (29U) +#define USBHS_HCTSIZ10_PID (0x60000000UL) +#define USBHS_HCTSIZ10_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ10_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ10_DOPNG_POS (31U) +#define USBHS_HCTSIZ10_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA10 register */ +#define USBHS_HCDMA10 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR11 register */ +#define USBHS_HCCHAR11_MPS_POS (0U) +#define USBHS_HCCHAR11_MPS (0x000007FFUL) +#define USBHS_HCCHAR11_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR11_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR11_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR11_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR11_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR11_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR11_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR11_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR11_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR11_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR11_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR11_EPNUM_POS (11U) +#define USBHS_HCCHAR11_EPNUM (0x00007800UL) +#define USBHS_HCCHAR11_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR11_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR11_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR11_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR11_EPDIR_POS (15U) +#define USBHS_HCCHAR11_EPDIR (0x00008000UL) +#define USBHS_HCCHAR11_LSPDDEV_POS (17U) +#define USBHS_HCCHAR11_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR11_EPTYPE_POS (18U) +#define USBHS_HCCHAR11_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR11_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR11_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR11_EC_POS (20U) +#define USBHS_HCCHAR11_EC (0x00300000UL) +#define USBHS_HCCHAR11_EC_0 (0x00100000UL) +#define USBHS_HCCHAR11_EC_1 (0x00200000UL) +#define USBHS_HCCHAR11_DEVADDR_POS (22U) +#define USBHS_HCCHAR11_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR11_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR11_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR11_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR11_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR11_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR11_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR11_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR11_ODDFRM_POS (29U) +#define USBHS_HCCHAR11_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR11_CHDIS_POS (30U) +#define USBHS_HCCHAR11_CHDIS (0x40000000UL) +#define USBHS_HCCHAR11_CHENA_POS (31U) +#define USBHS_HCCHAR11_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT11 register */ +#define USBHS_HCSPLT11_PRTADDR_POS (0U) +#define USBHS_HCSPLT11_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT11_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT11_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT11_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT11_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT11_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT11_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT11_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT11_HUBADDR_POS (7U) +#define USBHS_HCSPLT11_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT11_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT11_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT11_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT11_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT11_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT11_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT11_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT11_XACTPOS_POS (14U) +#define USBHS_HCSPLT11_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT11_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT11_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT11_COMPSPLT_POS (16U) +#define USBHS_HCSPLT11_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT11_SPLTENA_POS (31U) +#define USBHS_HCSPLT11_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT11 register */ +#define USBHS_HCINT11_XFERCOMPL_POS (0U) +#define USBHS_HCINT11_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT11_CHHLTD_POS (1U) +#define USBHS_HCINT11_CHHLTD (0x00000002UL) +#define USBHS_HCINT11_AHBERR_POS (2U) +#define USBHS_HCINT11_AHBERR (0x00000004UL) +#define USBHS_HCINT11_STALL_POS (3U) +#define USBHS_HCINT11_STALL (0x00000008UL) +#define USBHS_HCINT11_NAK_POS (4U) +#define USBHS_HCINT11_NAK (0x00000010UL) +#define USBHS_HCINT11_ACK_POS (5U) +#define USBHS_HCINT11_ACK (0x00000020UL) +#define USBHS_HCINT11_NYET_POS (6U) +#define USBHS_HCINT11_NYET (0x00000040UL) +#define USBHS_HCINT11_XACTERR_POS (7U) +#define USBHS_HCINT11_XACTERR (0x00000080UL) +#define USBHS_HCINT11_BBLERR_POS (8U) +#define USBHS_HCINT11_BBLERR (0x00000100UL) +#define USBHS_HCINT11_FRMOVRUN_POS (9U) +#define USBHS_HCINT11_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT11_DATATGLERR_POS (10U) +#define USBHS_HCINT11_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK11 register */ +#define USBHS_HCINTMSK11_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK11_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK11_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK11_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK11_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK11_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK11_STALLMSK_POS (3U) +#define USBHS_HCINTMSK11_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK11_NAKMSK_POS (4U) +#define USBHS_HCINTMSK11_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK11_ACKMSK_POS (5U) +#define USBHS_HCINTMSK11_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK11_NYETMSK_POS (6U) +#define USBHS_HCINTMSK11_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK11_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK11_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK11_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK11_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK11_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK11_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK11_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK11_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ11 register */ +#define USBHS_HCTSIZ11_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ11_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ11_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ11_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ11_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ11_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ11_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ11_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ11_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ11_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ11_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ11_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ11_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ11_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ11_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ11_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ11_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ11_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ11_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ11_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ11_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ11_PKTCNT_POS (19U) +#define USBHS_HCTSIZ11_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ11_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ11_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ11_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ11_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ11_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ11_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ11_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ11_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ11_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ11_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ11_PID_POS (29U) +#define USBHS_HCTSIZ11_PID (0x60000000UL) +#define USBHS_HCTSIZ11_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ11_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ11_DOPNG_POS (31U) +#define USBHS_HCTSIZ11_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA11 register */ +#define USBHS_HCDMA11 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR12 register */ +#define USBHS_HCCHAR12_MPS_POS (0U) +#define USBHS_HCCHAR12_MPS (0x000007FFUL) +#define USBHS_HCCHAR12_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR12_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR12_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR12_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR12_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR12_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR12_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR12_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR12_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR12_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR12_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR12_EPNUM_POS (11U) +#define USBHS_HCCHAR12_EPNUM (0x00007800UL) +#define USBHS_HCCHAR12_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR12_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR12_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR12_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR12_EPDIR_POS (15U) +#define USBHS_HCCHAR12_EPDIR (0x00008000UL) +#define USBHS_HCCHAR12_LSPDDEV_POS (17U) +#define USBHS_HCCHAR12_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR12_EPTYPE_POS (18U) +#define USBHS_HCCHAR12_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR12_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR12_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR12_EC_POS (20U) +#define USBHS_HCCHAR12_EC (0x00300000UL) +#define USBHS_HCCHAR12_EC_0 (0x00100000UL) +#define USBHS_HCCHAR12_EC_1 (0x00200000UL) +#define USBHS_HCCHAR12_DEVADDR_POS (22U) +#define USBHS_HCCHAR12_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR12_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR12_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR12_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR12_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR12_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR12_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR12_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR12_ODDFRM_POS (29U) +#define USBHS_HCCHAR12_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR12_CHDIS_POS (30U) +#define USBHS_HCCHAR12_CHDIS (0x40000000UL) +#define USBHS_HCCHAR12_CHENA_POS (31U) +#define USBHS_HCCHAR12_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT12 register */ +#define USBHS_HCSPLT12_PRTADDR_POS (0U) +#define USBHS_HCSPLT12_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT12_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT12_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT12_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT12_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT12_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT12_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT12_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT12_HUBADDR_POS (7U) +#define USBHS_HCSPLT12_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT12_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT12_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT12_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT12_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT12_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT12_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT12_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT12_XACTPOS_POS (14U) +#define USBHS_HCSPLT12_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT12_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT12_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT12_COMPSPLT_POS (16U) +#define USBHS_HCSPLT12_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT12_SPLTENA_POS (31U) +#define USBHS_HCSPLT12_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT12 register */ +#define USBHS_HCINT12_XFERCOMPL_POS (0U) +#define USBHS_HCINT12_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT12_CHHLTD_POS (1U) +#define USBHS_HCINT12_CHHLTD (0x00000002UL) +#define USBHS_HCINT12_AHBERR_POS (2U) +#define USBHS_HCINT12_AHBERR (0x00000004UL) +#define USBHS_HCINT12_STALL_POS (3U) +#define USBHS_HCINT12_STALL (0x00000008UL) +#define USBHS_HCINT12_NAK_POS (4U) +#define USBHS_HCINT12_NAK (0x00000010UL) +#define USBHS_HCINT12_ACK_POS (5U) +#define USBHS_HCINT12_ACK (0x00000020UL) +#define USBHS_HCINT12_NYET_POS (6U) +#define USBHS_HCINT12_NYET (0x00000040UL) +#define USBHS_HCINT12_XACTERR_POS (7U) +#define USBHS_HCINT12_XACTERR (0x00000080UL) +#define USBHS_HCINT12_BBLERR_POS (8U) +#define USBHS_HCINT12_BBLERR (0x00000100UL) +#define USBHS_HCINT12_FRMOVRUN_POS (9U) +#define USBHS_HCINT12_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT12_DATATGLERR_POS (10U) +#define USBHS_HCINT12_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK12 register */ +#define USBHS_HCINTMSK12_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK12_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK12_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK12_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK12_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK12_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK12_STALLMSK_POS (3U) +#define USBHS_HCINTMSK12_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK12_NAKMSK_POS (4U) +#define USBHS_HCINTMSK12_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK12_ACKMSK_POS (5U) +#define USBHS_HCINTMSK12_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK12_NYETMSK_POS (6U) +#define USBHS_HCINTMSK12_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK12_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK12_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK12_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK12_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK12_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK12_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK12_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK12_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ12 register */ +#define USBHS_HCTSIZ12_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ12_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ12_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ12_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ12_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ12_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ12_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ12_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ12_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ12_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ12_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ12_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ12_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ12_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ12_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ12_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ12_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ12_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ12_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ12_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ12_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ12_PKTCNT_POS (19U) +#define USBHS_HCTSIZ12_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ12_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ12_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ12_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ12_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ12_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ12_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ12_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ12_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ12_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ12_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ12_PID_POS (29U) +#define USBHS_HCTSIZ12_PID (0x60000000UL) +#define USBHS_HCTSIZ12_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ12_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ12_DOPNG_POS (31U) +#define USBHS_HCTSIZ12_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA12 register */ +#define USBHS_HCDMA12 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR13 register */ +#define USBHS_HCCHAR13_MPS_POS (0U) +#define USBHS_HCCHAR13_MPS (0x000007FFUL) +#define USBHS_HCCHAR13_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR13_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR13_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR13_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR13_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR13_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR13_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR13_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR13_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR13_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR13_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR13_EPNUM_POS (11U) +#define USBHS_HCCHAR13_EPNUM (0x00007800UL) +#define USBHS_HCCHAR13_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR13_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR13_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR13_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR13_EPDIR_POS (15U) +#define USBHS_HCCHAR13_EPDIR (0x00008000UL) +#define USBHS_HCCHAR13_LSPDDEV_POS (17U) +#define USBHS_HCCHAR13_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR13_EPTYPE_POS (18U) +#define USBHS_HCCHAR13_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR13_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR13_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR13_EC_POS (20U) +#define USBHS_HCCHAR13_EC (0x00300000UL) +#define USBHS_HCCHAR13_EC_0 (0x00100000UL) +#define USBHS_HCCHAR13_EC_1 (0x00200000UL) +#define USBHS_HCCHAR13_DEVADDR_POS (22U) +#define USBHS_HCCHAR13_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR13_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR13_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR13_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR13_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR13_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR13_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR13_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR13_ODDFRM_POS (29U) +#define USBHS_HCCHAR13_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR13_CHDIS_POS (30U) +#define USBHS_HCCHAR13_CHDIS (0x40000000UL) +#define USBHS_HCCHAR13_CHENA_POS (31U) +#define USBHS_HCCHAR13_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT13 register */ +#define USBHS_HCSPLT13_PRTADDR_POS (0U) +#define USBHS_HCSPLT13_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT13_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT13_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT13_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT13_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT13_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT13_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT13_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT13_HUBADDR_POS (7U) +#define USBHS_HCSPLT13_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT13_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT13_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT13_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT13_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT13_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT13_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT13_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT13_XACTPOS_POS (14U) +#define USBHS_HCSPLT13_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT13_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT13_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT13_COMPSPLT_POS (16U) +#define USBHS_HCSPLT13_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT13_SPLTENA_POS (31U) +#define USBHS_HCSPLT13_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT13 register */ +#define USBHS_HCINT13_XFERCOMPL_POS (0U) +#define USBHS_HCINT13_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT13_CHHLTD_POS (1U) +#define USBHS_HCINT13_CHHLTD (0x00000002UL) +#define USBHS_HCINT13_AHBERR_POS (2U) +#define USBHS_HCINT13_AHBERR (0x00000004UL) +#define USBHS_HCINT13_STALL_POS (3U) +#define USBHS_HCINT13_STALL (0x00000008UL) +#define USBHS_HCINT13_NAK_POS (4U) +#define USBHS_HCINT13_NAK (0x00000010UL) +#define USBHS_HCINT13_ACK_POS (5U) +#define USBHS_HCINT13_ACK (0x00000020UL) +#define USBHS_HCINT13_NYET_POS (6U) +#define USBHS_HCINT13_NYET (0x00000040UL) +#define USBHS_HCINT13_XACTERR_POS (7U) +#define USBHS_HCINT13_XACTERR (0x00000080UL) +#define USBHS_HCINT13_BBLERR_POS (8U) +#define USBHS_HCINT13_BBLERR (0x00000100UL) +#define USBHS_HCINT13_FRMOVRUN_POS (9U) +#define USBHS_HCINT13_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT13_DATATGLERR_POS (10U) +#define USBHS_HCINT13_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK13 register */ +#define USBHS_HCINTMSK13_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK13_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK13_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK13_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK13_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK13_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK13_STALLMSK_POS (3U) +#define USBHS_HCINTMSK13_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK13_NAKMSK_POS (4U) +#define USBHS_HCINTMSK13_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK13_ACKMSK_POS (5U) +#define USBHS_HCINTMSK13_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK13_NYETMSK_POS (6U) +#define USBHS_HCINTMSK13_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK13_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK13_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK13_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK13_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK13_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK13_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK13_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK13_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ13 register */ +#define USBHS_HCTSIZ13_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ13_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ13_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ13_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ13_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ13_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ13_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ13_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ13_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ13_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ13_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ13_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ13_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ13_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ13_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ13_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ13_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ13_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ13_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ13_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ13_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ13_PKTCNT_POS (19U) +#define USBHS_HCTSIZ13_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ13_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ13_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ13_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ13_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ13_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ13_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ13_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ13_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ13_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ13_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ13_PID_POS (29U) +#define USBHS_HCTSIZ13_PID (0x60000000UL) +#define USBHS_HCTSIZ13_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ13_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ13_DOPNG_POS (31U) +#define USBHS_HCTSIZ13_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA13 register */ +#define USBHS_HCDMA13 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR14 register */ +#define USBHS_HCCHAR14_MPS_POS (0U) +#define USBHS_HCCHAR14_MPS (0x000007FFUL) +#define USBHS_HCCHAR14_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR14_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR14_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR14_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR14_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR14_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR14_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR14_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR14_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR14_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR14_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR14_EPNUM_POS (11U) +#define USBHS_HCCHAR14_EPNUM (0x00007800UL) +#define USBHS_HCCHAR14_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR14_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR14_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR14_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR14_EPDIR_POS (15U) +#define USBHS_HCCHAR14_EPDIR (0x00008000UL) +#define USBHS_HCCHAR14_LSPDDEV_POS (17U) +#define USBHS_HCCHAR14_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR14_EPTYPE_POS (18U) +#define USBHS_HCCHAR14_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR14_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR14_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR14_EC_POS (20U) +#define USBHS_HCCHAR14_EC (0x00300000UL) +#define USBHS_HCCHAR14_EC_0 (0x00100000UL) +#define USBHS_HCCHAR14_EC_1 (0x00200000UL) +#define USBHS_HCCHAR14_DEVADDR_POS (22U) +#define USBHS_HCCHAR14_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR14_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR14_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR14_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR14_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR14_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR14_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR14_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR14_ODDFRM_POS (29U) +#define USBHS_HCCHAR14_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR14_CHDIS_POS (30U) +#define USBHS_HCCHAR14_CHDIS (0x40000000UL) +#define USBHS_HCCHAR14_CHENA_POS (31U) +#define USBHS_HCCHAR14_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT14 register */ +#define USBHS_HCSPLT14_PRTADDR_POS (0U) +#define USBHS_HCSPLT14_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT14_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT14_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT14_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT14_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT14_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT14_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT14_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT14_HUBADDR_POS (7U) +#define USBHS_HCSPLT14_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT14_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT14_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT14_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT14_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT14_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT14_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT14_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT14_XACTPOS_POS (14U) +#define USBHS_HCSPLT14_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT14_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT14_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT14_COMPSPLT_POS (16U) +#define USBHS_HCSPLT14_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT14_SPLTENA_POS (31U) +#define USBHS_HCSPLT14_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT14 register */ +#define USBHS_HCINT14_XFERCOMPL_POS (0U) +#define USBHS_HCINT14_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT14_CHHLTD_POS (1U) +#define USBHS_HCINT14_CHHLTD (0x00000002UL) +#define USBHS_HCINT14_AHBERR_POS (2U) +#define USBHS_HCINT14_AHBERR (0x00000004UL) +#define USBHS_HCINT14_STALL_POS (3U) +#define USBHS_HCINT14_STALL (0x00000008UL) +#define USBHS_HCINT14_NAK_POS (4U) +#define USBHS_HCINT14_NAK (0x00000010UL) +#define USBHS_HCINT14_ACK_POS (5U) +#define USBHS_HCINT14_ACK (0x00000020UL) +#define USBHS_HCINT14_NYET_POS (6U) +#define USBHS_HCINT14_NYET (0x00000040UL) +#define USBHS_HCINT14_XACTERR_POS (7U) +#define USBHS_HCINT14_XACTERR (0x00000080UL) +#define USBHS_HCINT14_BBLERR_POS (8U) +#define USBHS_HCINT14_BBLERR (0x00000100UL) +#define USBHS_HCINT14_FRMOVRUN_POS (9U) +#define USBHS_HCINT14_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT14_DATATGLERR_POS (10U) +#define USBHS_HCINT14_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK14 register */ +#define USBHS_HCINTMSK14_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK14_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK14_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK14_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK14_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK14_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK14_STALLMSK_POS (3U) +#define USBHS_HCINTMSK14_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK14_NAKMSK_POS (4U) +#define USBHS_HCINTMSK14_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK14_ACKMSK_POS (5U) +#define USBHS_HCINTMSK14_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK14_NYETMSK_POS (6U) +#define USBHS_HCINTMSK14_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK14_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK14_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK14_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK14_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK14_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK14_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK14_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK14_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ14 register */ +#define USBHS_HCTSIZ14_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ14_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ14_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ14_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ14_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ14_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ14_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ14_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ14_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ14_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ14_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ14_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ14_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ14_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ14_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ14_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ14_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ14_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ14_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ14_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ14_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ14_PKTCNT_POS (19U) +#define USBHS_HCTSIZ14_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ14_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ14_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ14_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ14_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ14_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ14_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ14_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ14_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ14_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ14_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ14_PID_POS (29U) +#define USBHS_HCTSIZ14_PID (0x60000000UL) +#define USBHS_HCTSIZ14_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ14_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ14_DOPNG_POS (31U) +#define USBHS_HCTSIZ14_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA14 register */ +#define USBHS_HCDMA14 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_HCCHAR15 register */ +#define USBHS_HCCHAR15_MPS_POS (0U) +#define USBHS_HCCHAR15_MPS (0x000007FFUL) +#define USBHS_HCCHAR15_MPS_0 (0x00000001UL) +#define USBHS_HCCHAR15_MPS_1 (0x00000002UL) +#define USBHS_HCCHAR15_MPS_2 (0x00000004UL) +#define USBHS_HCCHAR15_MPS_3 (0x00000008UL) +#define USBHS_HCCHAR15_MPS_4 (0x00000010UL) +#define USBHS_HCCHAR15_MPS_5 (0x00000020UL) +#define USBHS_HCCHAR15_MPS_6 (0x00000040UL) +#define USBHS_HCCHAR15_MPS_7 (0x00000080UL) +#define USBHS_HCCHAR15_MPS_8 (0x00000100UL) +#define USBHS_HCCHAR15_MPS_9 (0x00000200UL) +#define USBHS_HCCHAR15_MPS_10 (0x00000400UL) +#define USBHS_HCCHAR15_EPNUM_POS (11U) +#define USBHS_HCCHAR15_EPNUM (0x00007800UL) +#define USBHS_HCCHAR15_EPNUM_0 (0x00000800UL) +#define USBHS_HCCHAR15_EPNUM_1 (0x00001000UL) +#define USBHS_HCCHAR15_EPNUM_2 (0x00002000UL) +#define USBHS_HCCHAR15_EPNUM_3 (0x00004000UL) +#define USBHS_HCCHAR15_EPDIR_POS (15U) +#define USBHS_HCCHAR15_EPDIR (0x00008000UL) +#define USBHS_HCCHAR15_LSPDDEV_POS (17U) +#define USBHS_HCCHAR15_LSPDDEV (0x00020000UL) +#define USBHS_HCCHAR15_EPTYPE_POS (18U) +#define USBHS_HCCHAR15_EPTYPE (0x000C0000UL) +#define USBHS_HCCHAR15_EPTYPE_0 (0x00040000UL) +#define USBHS_HCCHAR15_EPTYPE_1 (0x00080000UL) +#define USBHS_HCCHAR15_EC_POS (20U) +#define USBHS_HCCHAR15_EC (0x00300000UL) +#define USBHS_HCCHAR15_EC_0 (0x00100000UL) +#define USBHS_HCCHAR15_EC_1 (0x00200000UL) +#define USBHS_HCCHAR15_DEVADDR_POS (22U) +#define USBHS_HCCHAR15_DEVADDR (0x1FC00000UL) +#define USBHS_HCCHAR15_DEVADDR_0 (0x00400000UL) +#define USBHS_HCCHAR15_DEVADDR_1 (0x00800000UL) +#define USBHS_HCCHAR15_DEVADDR_2 (0x01000000UL) +#define USBHS_HCCHAR15_DEVADDR_3 (0x02000000UL) +#define USBHS_HCCHAR15_DEVADDR_4 (0x04000000UL) +#define USBHS_HCCHAR15_DEVADDR_5 (0x08000000UL) +#define USBHS_HCCHAR15_DEVADDR_6 (0x10000000UL) +#define USBHS_HCCHAR15_ODDFRM_POS (29U) +#define USBHS_HCCHAR15_ODDFRM (0x20000000UL) +#define USBHS_HCCHAR15_CHDIS_POS (30U) +#define USBHS_HCCHAR15_CHDIS (0x40000000UL) +#define USBHS_HCCHAR15_CHENA_POS (31U) +#define USBHS_HCCHAR15_CHENA (0x80000000UL) + +/* Bit definition for USBHS_HCSPLT15 register */ +#define USBHS_HCSPLT15_PRTADDR_POS (0U) +#define USBHS_HCSPLT15_PRTADDR (0x0000007FUL) +#define USBHS_HCSPLT15_PRTADDR_0 (0x00000001UL) +#define USBHS_HCSPLT15_PRTADDR_1 (0x00000002UL) +#define USBHS_HCSPLT15_PRTADDR_2 (0x00000004UL) +#define USBHS_HCSPLT15_PRTADDR_3 (0x00000008UL) +#define USBHS_HCSPLT15_PRTADDR_4 (0x00000010UL) +#define USBHS_HCSPLT15_PRTADDR_5 (0x00000020UL) +#define USBHS_HCSPLT15_PRTADDR_6 (0x00000040UL) +#define USBHS_HCSPLT15_HUBADDR_POS (7U) +#define USBHS_HCSPLT15_HUBADDR (0x00003F80UL) +#define USBHS_HCSPLT15_HUBADDR_0 (0x00000080UL) +#define USBHS_HCSPLT15_HUBADDR_1 (0x00000100UL) +#define USBHS_HCSPLT15_HUBADDR_2 (0x00000200UL) +#define USBHS_HCSPLT15_HUBADDR_3 (0x00000400UL) +#define USBHS_HCSPLT15_HUBADDR_4 (0x00000800UL) +#define USBHS_HCSPLT15_HUBADDR_5 (0x00001000UL) +#define USBHS_HCSPLT15_HUBADDR_6 (0x00002000UL) +#define USBHS_HCSPLT15_XACTPOS_POS (14U) +#define USBHS_HCSPLT15_XACTPOS (0x0000C000UL) +#define USBHS_HCSPLT15_XACTPOS_0 (0x00004000UL) +#define USBHS_HCSPLT15_XACTPOS_1 (0x00008000UL) +#define USBHS_HCSPLT15_COMPSPLT_POS (16U) +#define USBHS_HCSPLT15_COMPSPLT (0x00010000UL) +#define USBHS_HCSPLT15_SPLTENA_POS (31U) +#define USBHS_HCSPLT15_SPLTENA (0x80000000UL) + +/* Bit definition for USBHS_HCINT15 register */ +#define USBHS_HCINT15_XFERCOMPL_POS (0U) +#define USBHS_HCINT15_XFERCOMPL (0x00000001UL) +#define USBHS_HCINT15_CHHLTD_POS (1U) +#define USBHS_HCINT15_CHHLTD (0x00000002UL) +#define USBHS_HCINT15_AHBERR_POS (2U) +#define USBHS_HCINT15_AHBERR (0x00000004UL) +#define USBHS_HCINT15_STALL_POS (3U) +#define USBHS_HCINT15_STALL (0x00000008UL) +#define USBHS_HCINT15_NAK_POS (4U) +#define USBHS_HCINT15_NAK (0x00000010UL) +#define USBHS_HCINT15_ACK_POS (5U) +#define USBHS_HCINT15_ACK (0x00000020UL) +#define USBHS_HCINT15_NYET_POS (6U) +#define USBHS_HCINT15_NYET (0x00000040UL) +#define USBHS_HCINT15_XACTERR_POS (7U) +#define USBHS_HCINT15_XACTERR (0x00000080UL) +#define USBHS_HCINT15_BBLERR_POS (8U) +#define USBHS_HCINT15_BBLERR (0x00000100UL) +#define USBHS_HCINT15_FRMOVRUN_POS (9U) +#define USBHS_HCINT15_FRMOVRUN (0x00000200UL) +#define USBHS_HCINT15_DATATGLERR_POS (10U) +#define USBHS_HCINT15_DATATGLERR (0x00000400UL) + +/* Bit definition for USBHS_HCINTMSK15 register */ +#define USBHS_HCINTMSK15_XFERCOMPLMSK_POS (0U) +#define USBHS_HCINTMSK15_XFERCOMPLMSK (0x00000001UL) +#define USBHS_HCINTMSK15_CHHLTDMSK_POS (1U) +#define USBHS_HCINTMSK15_CHHLTDMSK (0x00000002UL) +#define USBHS_HCINTMSK15_AHBERRMSK_POS (2U) +#define USBHS_HCINTMSK15_AHBERRMSK (0x00000004UL) +#define USBHS_HCINTMSK15_STALLMSK_POS (3U) +#define USBHS_HCINTMSK15_STALLMSK (0x00000008UL) +#define USBHS_HCINTMSK15_NAKMSK_POS (4U) +#define USBHS_HCINTMSK15_NAKMSK (0x00000010UL) +#define USBHS_HCINTMSK15_ACKMSK_POS (5U) +#define USBHS_HCINTMSK15_ACKMSK (0x00000020UL) +#define USBHS_HCINTMSK15_NYETMSK_POS (6U) +#define USBHS_HCINTMSK15_NYETMSK (0x00000040UL) +#define USBHS_HCINTMSK15_XACTERRMSK_POS (7U) +#define USBHS_HCINTMSK15_XACTERRMSK (0x00000080UL) +#define USBHS_HCINTMSK15_BBLERRMSK_POS (8U) +#define USBHS_HCINTMSK15_BBLERRMSK (0x00000100UL) +#define USBHS_HCINTMSK15_FRMOVRUNMSK_POS (9U) +#define USBHS_HCINTMSK15_FRMOVRUNMSK (0x00000200UL) +#define USBHS_HCINTMSK15_DATATGLERRMSK_POS (10U) +#define USBHS_HCINTMSK15_DATATGLERRMSK (0x00000400UL) + +/* Bit definition for USBHS_HCTSIZ15 register */ +#define USBHS_HCTSIZ15_XFERSIZE_POS (0U) +#define USBHS_HCTSIZ15_XFERSIZE (0x0007FFFFUL) +#define USBHS_HCTSIZ15_XFERSIZE_0 (0x00000001UL) +#define USBHS_HCTSIZ15_XFERSIZE_1 (0x00000002UL) +#define USBHS_HCTSIZ15_XFERSIZE_2 (0x00000004UL) +#define USBHS_HCTSIZ15_XFERSIZE_3 (0x00000008UL) +#define USBHS_HCTSIZ15_XFERSIZE_4 (0x00000010UL) +#define USBHS_HCTSIZ15_XFERSIZE_5 (0x00000020UL) +#define USBHS_HCTSIZ15_XFERSIZE_6 (0x00000040UL) +#define USBHS_HCTSIZ15_XFERSIZE_7 (0x00000080UL) +#define USBHS_HCTSIZ15_XFERSIZE_8 (0x00000100UL) +#define USBHS_HCTSIZ15_XFERSIZE_9 (0x00000200UL) +#define USBHS_HCTSIZ15_XFERSIZE_10 (0x00000400UL) +#define USBHS_HCTSIZ15_XFERSIZE_11 (0x00000800UL) +#define USBHS_HCTSIZ15_XFERSIZE_12 (0x00001000UL) +#define USBHS_HCTSIZ15_XFERSIZE_13 (0x00002000UL) +#define USBHS_HCTSIZ15_XFERSIZE_14 (0x00004000UL) +#define USBHS_HCTSIZ15_XFERSIZE_15 (0x00008000UL) +#define USBHS_HCTSIZ15_XFERSIZE_16 (0x00010000UL) +#define USBHS_HCTSIZ15_XFERSIZE_17 (0x00020000UL) +#define USBHS_HCTSIZ15_XFERSIZE_18 (0x00040000UL) +#define USBHS_HCTSIZ15_PKTCNT_POS (19U) +#define USBHS_HCTSIZ15_PKTCNT (0x1FF80000UL) +#define USBHS_HCTSIZ15_PKTCNT_0 (0x00080000UL) +#define USBHS_HCTSIZ15_PKTCNT_1 (0x00100000UL) +#define USBHS_HCTSIZ15_PKTCNT_2 (0x00200000UL) +#define USBHS_HCTSIZ15_PKTCNT_3 (0x00400000UL) +#define USBHS_HCTSIZ15_PKTCNT_4 (0x00800000UL) +#define USBHS_HCTSIZ15_PKTCNT_5 (0x01000000UL) +#define USBHS_HCTSIZ15_PKTCNT_6 (0x02000000UL) +#define USBHS_HCTSIZ15_PKTCNT_7 (0x04000000UL) +#define USBHS_HCTSIZ15_PKTCNT_8 (0x08000000UL) +#define USBHS_HCTSIZ15_PKTCNT_9 (0x10000000UL) +#define USBHS_HCTSIZ15_PID_POS (29U) +#define USBHS_HCTSIZ15_PID (0x60000000UL) +#define USBHS_HCTSIZ15_PID_0 (0x20000000UL) +#define USBHS_HCTSIZ15_PID_1 (0x40000000UL) +#define USBHS_HCTSIZ15_DOPNG_POS (31U) +#define USBHS_HCTSIZ15_DOPNG (0x80000000UL) + +/* Bit definition for USBHS_HCDMA15 register */ +#define USBHS_HCDMA15 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DCFG register */ +#define USBHS_DCFG_DEVSPD_POS (0U) +#define USBHS_DCFG_DEVSPD (0x00000003UL) +#define USBHS_DCFG_DEVSPD_0 (0x00000001UL) +#define USBHS_DCFG_DEVSPD_1 (0x00000002UL) +#define USBHS_DCFG_NZSTSOUTHSHK_POS (2U) +#define USBHS_DCFG_NZSTSOUTHSHK (0x00000004UL) +#define USBHS_DCFG_ENA32KHZSUSP_POS (3U) +#define USBHS_DCFG_ENA32KHZSUSP (0x00000008UL) +#define USBHS_DCFG_DEVADDR_POS (4U) +#define USBHS_DCFG_DEVADDR (0x000007F0UL) +#define USBHS_DCFG_DEVADDR_0 (0x00000010UL) +#define USBHS_DCFG_DEVADDR_1 (0x00000020UL) +#define USBHS_DCFG_DEVADDR_2 (0x00000040UL) +#define USBHS_DCFG_DEVADDR_3 (0x00000080UL) +#define USBHS_DCFG_DEVADDR_4 (0x00000100UL) +#define USBHS_DCFG_DEVADDR_5 (0x00000200UL) +#define USBHS_DCFG_DEVADDR_6 (0x00000400UL) +#define USBHS_DCFG_PERFRINT_POS (11U) +#define USBHS_DCFG_PERFRINT (0x00001800UL) +#define USBHS_DCFG_PERFRINT_0 (0x00000800UL) +#define USBHS_DCFG_PERFRINT_1 (0x00001000UL) +#define USBHS_DCFG_XCVRDLY_POS (14U) +#define USBHS_DCFG_XCVRDLY (0x00004000UL) +#define USBHS_DCFG_ERRATICINTMSK_POS (15U) +#define USBHS_DCFG_ERRATICINTMSK (0x00008000UL) +#define USBHS_DCFG_IPGISOCSUPT_POS (17U) +#define USBHS_DCFG_IPGISOCSUPT (0x00020000UL) +#define USBHS_DCFG_PERSCHINTVL_POS (24U) +#define USBHS_DCFG_PERSCHINTVL (0x03000000UL) +#define USBHS_DCFG_PERSCHINTVL_0 (0x01000000UL) +#define USBHS_DCFG_PERSCHINTVL_1 (0x02000000UL) +#define USBHS_DCFG_RESVALID_POS (26U) +#define USBHS_DCFG_RESVALID (0xFC000000UL) +#define USBHS_DCFG_RESVALID_0 (0x04000000UL) +#define USBHS_DCFG_RESVALID_1 (0x08000000UL) +#define USBHS_DCFG_RESVALID_2 (0x10000000UL) +#define USBHS_DCFG_RESVALID_3 (0x20000000UL) +#define USBHS_DCFG_RESVALID_4 (0x40000000UL) +#define USBHS_DCFG_RESVALID_5 (0x80000000UL) + +/* Bit definition for USBHS_DCTL register */ +#define USBHS_DCTL_RMTWKUPSIG_POS (0U) +#define USBHS_DCTL_RMTWKUPSIG (0x00000001UL) +#define USBHS_DCTL_SFTDISCON_POS (1U) +#define USBHS_DCTL_SFTDISCON (0x00000002UL) +#define USBHS_DCTL_GNPINNAKSTS_POS (2U) +#define USBHS_DCTL_GNPINNAKSTS (0x00000004UL) +#define USBHS_DCTL_GOUTNAKSTS_POS (3U) +#define USBHS_DCTL_GOUTNAKSTS (0x00000008UL) +#define USBHS_DCTL_TSTCTL_POS (4U) +#define USBHS_DCTL_TSTCTL (0x00000070UL) +#define USBHS_DCTL_TSTCTL_0 (0x00000010UL) +#define USBHS_DCTL_TSTCTL_1 (0x00000020UL) +#define USBHS_DCTL_TSTCTL_2 (0x00000040UL) +#define USBHS_DCTL_SGNPINNAK_POS (7U) +#define USBHS_DCTL_SGNPINNAK (0x00000080UL) +#define USBHS_DCTL_CGNPINNAK_POS (8U) +#define USBHS_DCTL_CGNPINNAK (0x00000100UL) +#define USBHS_DCTL_SGOUTNAK_POS (9U) +#define USBHS_DCTL_SGOUTNAK (0x00000200UL) +#define USBHS_DCTL_CGOUTNAK_POS (10U) +#define USBHS_DCTL_CGOUTNAK (0x00000400UL) +#define USBHS_DCTL_PWRONPRGDONE_POS (11U) +#define USBHS_DCTL_PWRONPRGDONE (0x00000800UL) +#define USBHS_DCTL_IGNRFRMNUM_POS (15U) +#define USBHS_DCTL_IGNRFRMNUM (0x00008000UL) +#define USBHS_DCTL_NAKONBBLE_POS (16U) +#define USBHS_DCTL_NAKONBBLE (0x00010000UL) +#define USBHS_DCTL_DEEPSLEEPBESLREJECT_POS (18U) +#define USBHS_DCTL_DEEPSLEEPBESLREJECT (0x00040000UL) +#define USBHS_DCTL_SERVINT_POS (19U) +#define USBHS_DCTL_SERVINT (0x00080000UL) + +/* Bit definition for USBHS_DSTS register */ +#define USBHS_DSTS_SUSPSTS_POS (0U) +#define USBHS_DSTS_SUSPSTS (0x00000001UL) +#define USBHS_DSTS_ENUMSPD_POS (1U) +#define USBHS_DSTS_ENUMSPD (0x00000006UL) +#define USBHS_DSTS_ENUMSPD_0 (0x00000002UL) +#define USBHS_DSTS_ENUMSPD_1 (0x00000004UL) +#define USBHS_DSTS_ERRTICERR_POS (3U) +#define USBHS_DSTS_ERRTICERR (0x00000008UL) +#define USBHS_DSTS_SOFFN_POS (8U) +#define USBHS_DSTS_SOFFN (0x003FFF00UL) +#define USBHS_DSTS_SOFFN_0 (0x00000100UL) +#define USBHS_DSTS_SOFFN_1 (0x00000200UL) +#define USBHS_DSTS_SOFFN_2 (0x00000400UL) +#define USBHS_DSTS_SOFFN_3 (0x00000800UL) +#define USBHS_DSTS_SOFFN_4 (0x00001000UL) +#define USBHS_DSTS_SOFFN_5 (0x00002000UL) +#define USBHS_DSTS_SOFFN_6 (0x00004000UL) +#define USBHS_DSTS_SOFFN_7 (0x00008000UL) +#define USBHS_DSTS_SOFFN_8 (0x00010000UL) +#define USBHS_DSTS_SOFFN_9 (0x00020000UL) +#define USBHS_DSTS_SOFFN_10 (0x00040000UL) +#define USBHS_DSTS_SOFFN_11 (0x00080000UL) +#define USBHS_DSTS_SOFFN_12 (0x00100000UL) +#define USBHS_DSTS_SOFFN_13 (0x00200000UL) +#define USBHS_DSTS_DEVLNSTS_POS (22U) +#define USBHS_DSTS_DEVLNSTS (0x00C00000UL) +#define USBHS_DSTS_DEVLNSTS_0 (0x00400000UL) +#define USBHS_DSTS_DEVLNSTS_1 (0x00800000UL) + +/* Bit definition for USBHS_DIEPMSK register */ +#define USBHS_DIEPMSK_XFERCOMPLMSK_POS (0U) +#define USBHS_DIEPMSK_XFERCOMPLMSK (0x00000001UL) +#define USBHS_DIEPMSK_EPDISBLDMSK_POS (1U) +#define USBHS_DIEPMSK_EPDISBLDMSK (0x00000002UL) +#define USBHS_DIEPMSK_AHBERRMSK_POS (2U) +#define USBHS_DIEPMSK_AHBERRMSK (0x00000004UL) +#define USBHS_DIEPMSK_TIMEOUTMSK_POS (3U) +#define USBHS_DIEPMSK_TIMEOUTMSK (0x00000008UL) +#define USBHS_DIEPMSK_INTKNTXFEMPMSK_POS (4U) +#define USBHS_DIEPMSK_INTKNTXFEMPMSK (0x00000010UL) +#define USBHS_DIEPMSK_INTKNEPMISMSK_POS (5U) +#define USBHS_DIEPMSK_INTKNEPMISMSK (0x00000020UL) +#define USBHS_DIEPMSK_INEPNAKEFFMSK_POS (6U) +#define USBHS_DIEPMSK_INEPNAKEFFMSK (0x00000040UL) +#define USBHS_DIEPMSK_TXFIFOUNDRNMSK_POS (8U) +#define USBHS_DIEPMSK_TXFIFOUNDRNMSK (0x00000100UL) +#define USBHS_DIEPMSK_NAKMSK_POS (13U) +#define USBHS_DIEPMSK_NAKMSK (0x00002000UL) + +/* Bit definition for USBHS_DOEPMSK register */ +#define USBHS_DOEPMSK_XFERCOMPLMSK_POS (0U) +#define USBHS_DOEPMSK_XFERCOMPLMSK (0x00000001UL) +#define USBHS_DOEPMSK_EPDISBLDMSK_POS (1U) +#define USBHS_DOEPMSK_EPDISBLDMSK (0x00000002UL) +#define USBHS_DOEPMSK_AHBERRMSK_POS (2U) +#define USBHS_DOEPMSK_AHBERRMSK (0x00000004UL) +#define USBHS_DOEPMSK_SETUPMSK_POS (3U) +#define USBHS_DOEPMSK_SETUPMSK (0x00000008UL) +#define USBHS_DOEPMSK_OUTTKNEPDISMSK_POS (4U) +#define USBHS_DOEPMSK_OUTTKNEPDISMSK (0x00000010UL) +#define USBHS_DOEPMSK_STSPHSERCVDMSK_POS (5U) +#define USBHS_DOEPMSK_STSPHSERCVDMSK (0x00000020UL) +#define USBHS_DOEPMSK_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPMSK_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPMSK_OUTPKTERRMSK_POS (8U) +#define USBHS_DOEPMSK_OUTPKTERRMSK (0x00000100UL) +#define USBHS_DOEPMSK_BBLEERRMSK_POS (12U) +#define USBHS_DOEPMSK_BBLEERRMSK (0x00001000UL) +#define USBHS_DOEPMSK_NAKMSK_POS (13U) +#define USBHS_DOEPMSK_NAKMSK (0x00002000UL) +#define USBHS_DOEPMSK_NYETMSK_POS (14U) +#define USBHS_DOEPMSK_NYETMSK (0x00004000UL) + +/* Bit definition for USBHS_DAINT register */ +#define USBHS_DAINT_INEPINT0_POS (0U) +#define USBHS_DAINT_INEPINT0 (0x00000001UL) +#define USBHS_DAINT_INEPINT1_POS (1U) +#define USBHS_DAINT_INEPINT1 (0x00000002UL) +#define USBHS_DAINT_INEPINT2_POS (2U) +#define USBHS_DAINT_INEPINT2 (0x00000004UL) +#define USBHS_DAINT_INEPINT3_POS (3U) +#define USBHS_DAINT_INEPINT3 (0x00000008UL) +#define USBHS_DAINT_INEPINT4_POS (4U) +#define USBHS_DAINT_INEPINT4 (0x00000010UL) +#define USBHS_DAINT_INEPINT5_POS (5U) +#define USBHS_DAINT_INEPINT5 (0x00000020UL) +#define USBHS_DAINT_INEPINT6_POS (6U) +#define USBHS_DAINT_INEPINT6 (0x00000040UL) +#define USBHS_DAINT_INEPINT7_POS (7U) +#define USBHS_DAINT_INEPINT7 (0x00000080UL) +#define USBHS_DAINT_INEPINT8_POS (8U) +#define USBHS_DAINT_INEPINT8 (0x00000100UL) +#define USBHS_DAINT_INEPINT9_POS (9U) +#define USBHS_DAINT_INEPINT9 (0x00000200UL) +#define USBHS_DAINT_INEPINT10_POS (10U) +#define USBHS_DAINT_INEPINT10 (0x00000400UL) +#define USBHS_DAINT_INEPINT11_POS (11U) +#define USBHS_DAINT_INEPINT11 (0x00000800UL) +#define USBHS_DAINT_INEPINT12_POS (12U) +#define USBHS_DAINT_INEPINT12 (0x00001000UL) +#define USBHS_DAINT_INEPINT13_POS (13U) +#define USBHS_DAINT_INEPINT13 (0x00002000UL) +#define USBHS_DAINT_INEPINT14_POS (14U) +#define USBHS_DAINT_INEPINT14 (0x00004000UL) +#define USBHS_DAINT_INEPINT15_POS (15U) +#define USBHS_DAINT_INEPINT15 (0x00008000UL) +#define USBHS_DAINT_OUTEPINT0_POS (16U) +#define USBHS_DAINT_OUTEPINT0 (0x00010000UL) +#define USBHS_DAINT_OUTEPINT1_POS (17U) +#define USBHS_DAINT_OUTEPINT1 (0x00020000UL) +#define USBHS_DAINT_OUTEPINT2_POS (18U) +#define USBHS_DAINT_OUTEPINT2 (0x00040000UL) +#define USBHS_DAINT_OUTEPINT3_POS (19U) +#define USBHS_DAINT_OUTEPINT3 (0x00080000UL) +#define USBHS_DAINT_OUTEPINT4_POS (20U) +#define USBHS_DAINT_OUTEPINT4 (0x00100000UL) +#define USBHS_DAINT_OUTEPINT5_POS (21U) +#define USBHS_DAINT_OUTEPINT5 (0x00200000UL) +#define USBHS_DAINT_OUTEPINT6_POS (22U) +#define USBHS_DAINT_OUTEPINT6 (0x00400000UL) +#define USBHS_DAINT_OUTEPINT7_POS (23U) +#define USBHS_DAINT_OUTEPINT7 (0x00800000UL) +#define USBHS_DAINT_OUTEPINT8_POS (24U) +#define USBHS_DAINT_OUTEPINT8 (0x01000000UL) +#define USBHS_DAINT_OUTEPINT9_POS (25U) +#define USBHS_DAINT_OUTEPINT9 (0x02000000UL) +#define USBHS_DAINT_OUTEPINT10_POS (26U) +#define USBHS_DAINT_OUTEPINT10 (0x04000000UL) +#define USBHS_DAINT_OUTEPINT11_POS (27U) +#define USBHS_DAINT_OUTEPINT11 (0x08000000UL) +#define USBHS_DAINT_OUTEPINT12_POS (28U) +#define USBHS_DAINT_OUTEPINT12 (0x10000000UL) +#define USBHS_DAINT_OUTEPINT13_POS (29U) +#define USBHS_DAINT_OUTEPINT13 (0x20000000UL) +#define USBHS_DAINT_OUTEPINT14_POS (30U) +#define USBHS_DAINT_OUTEPINT14 (0x40000000UL) +#define USBHS_DAINT_OUTEPINT15_POS (31U) +#define USBHS_DAINT_OUTEPINT15 (0x80000000UL) + +/* Bit definition for USBHS_DAINTMSK register */ +#define USBHS_DAINTMSK_INEPMSK0_POS (0U) +#define USBHS_DAINTMSK_INEPMSK0 (0x00000001UL) +#define USBHS_DAINTMSK_INEPMSK1_POS (1U) +#define USBHS_DAINTMSK_INEPMSK1 (0x00000002UL) +#define USBHS_DAINTMSK_INEPMSK2_POS (2U) +#define USBHS_DAINTMSK_INEPMSK2 (0x00000004UL) +#define USBHS_DAINTMSK_INEPMSK3_POS (3U) +#define USBHS_DAINTMSK_INEPMSK3 (0x00000008UL) +#define USBHS_DAINTMSK_INEPMSK4_POS (4U) +#define USBHS_DAINTMSK_INEPMSK4 (0x00000010UL) +#define USBHS_DAINTMSK_INEPMSK5_POS (5U) +#define USBHS_DAINTMSK_INEPMSK5 (0x00000020UL) +#define USBHS_DAINTMSK_INEPMSK6_POS (6U) +#define USBHS_DAINTMSK_INEPMSK6 (0x00000040UL) +#define USBHS_DAINTMSK_INEPMSK7_POS (7U) +#define USBHS_DAINTMSK_INEPMSK7 (0x00000080UL) +#define USBHS_DAINTMSK_INEPMSK8_POS (8U) +#define USBHS_DAINTMSK_INEPMSK8 (0x00000100UL) +#define USBHS_DAINTMSK_INEPMSK9_POS (9U) +#define USBHS_DAINTMSK_INEPMSK9 (0x00000200UL) +#define USBHS_DAINTMSK_INEPMSK10_POS (10U) +#define USBHS_DAINTMSK_INEPMSK10 (0x00000400UL) +#define USBHS_DAINTMSK_INEPMSK11_POS (11U) +#define USBHS_DAINTMSK_INEPMSK11 (0x00000800UL) +#define USBHS_DAINTMSK_INEPMSK12_POS (12U) +#define USBHS_DAINTMSK_INEPMSK12 (0x00001000UL) +#define USBHS_DAINTMSK_INEPMSK13_POS (13U) +#define USBHS_DAINTMSK_INEPMSK13 (0x00002000UL) +#define USBHS_DAINTMSK_INEPMSK14_POS (14U) +#define USBHS_DAINTMSK_INEPMSK14 (0x00004000UL) +#define USBHS_DAINTMSK_INEPMSK15_POS (15U) +#define USBHS_DAINTMSK_INEPMSK15 (0x00008000UL) +#define USBHS_DAINTMSK_OUTEPMSK0_POS (16U) +#define USBHS_DAINTMSK_OUTEPMSK0 (0x00010000UL) +#define USBHS_DAINTMSK_OUTEPMSK1_POS (17U) +#define USBHS_DAINTMSK_OUTEPMSK1 (0x00020000UL) +#define USBHS_DAINTMSK_OUTEPMSK2_POS (18U) +#define USBHS_DAINTMSK_OUTEPMSK2 (0x00040000UL) +#define USBHS_DAINTMSK_OUTEPMSK3_POS (19U) +#define USBHS_DAINTMSK_OUTEPMSK3 (0x00080000UL) +#define USBHS_DAINTMSK_OUTEPMSK4_POS (20U) +#define USBHS_DAINTMSK_OUTEPMSK4 (0x00100000UL) +#define USBHS_DAINTMSK_OUTEPMSK5_POS (21U) +#define USBHS_DAINTMSK_OUTEPMSK5 (0x00200000UL) +#define USBHS_DAINTMSK_OUTEPMSK6_POS (22U) +#define USBHS_DAINTMSK_OUTEPMSK6 (0x00400000UL) +#define USBHS_DAINTMSK_OUTEPMSK7_POS (23U) +#define USBHS_DAINTMSK_OUTEPMSK7 (0x00800000UL) +#define USBHS_DAINTMSK_OUTEPMSK8_POS (24U) +#define USBHS_DAINTMSK_OUTEPMSK8 (0x01000000UL) +#define USBHS_DAINTMSK_OUTEPMSK9_POS (25U) +#define USBHS_DAINTMSK_OUTEPMSK9 (0x02000000UL) +#define USBHS_DAINTMSK_OUTEPMSK10_POS (26U) +#define USBHS_DAINTMSK_OUTEPMSK10 (0x04000000UL) +#define USBHS_DAINTMSK_OUTEPMSK11_POS (27U) +#define USBHS_DAINTMSK_OUTEPMSK11 (0x08000000UL) +#define USBHS_DAINTMSK_OUTEPMSK12_POS (28U) +#define USBHS_DAINTMSK_OUTEPMSK12 (0x10000000UL) +#define USBHS_DAINTMSK_OUTEPMSK13_POS (29U) +#define USBHS_DAINTMSK_OUTEPMSK13 (0x20000000UL) +#define USBHS_DAINTMSK_OUTEPMSK14_POS (30U) +#define USBHS_DAINTMSK_OUTEPMSK14 (0x40000000UL) +#define USBHS_DAINTMSK_OUTEPMSK15_POS (31U) +#define USBHS_DAINTMSK_OUTEPMSK15 (0x80000000UL) + +/* Bit definition for USBHS_DTHRCTL register */ +#define USBHS_DTHRCTL_NONISOTHREN_POS (0U) +#define USBHS_DTHRCTL_NONISOTHREN (0x00000001UL) +#define USBHS_DTHRCTL_ISOTHREN_POS (1U) +#define USBHS_DTHRCTL_ISOTHREN (0x00000002UL) +#define USBHS_DTHRCTL_TXTHRLEN_POS (2U) +#define USBHS_DTHRCTL_TXTHRLEN (0x000007FCUL) +#define USBHS_DTHRCTL_TXTHRLEN_0 (0x00000004UL) +#define USBHS_DTHRCTL_TXTHRLEN_1 (0x00000008UL) +#define USBHS_DTHRCTL_TXTHRLEN_2 (0x00000010UL) +#define USBHS_DTHRCTL_TXTHRLEN_3 (0x00000020UL) +#define USBHS_DTHRCTL_TXTHRLEN_4 (0x00000040UL) +#define USBHS_DTHRCTL_TXTHRLEN_5 (0x00000080UL) +#define USBHS_DTHRCTL_TXTHRLEN_6 (0x00000100UL) +#define USBHS_DTHRCTL_TXTHRLEN_7 (0x00000200UL) +#define USBHS_DTHRCTL_TXTHRLEN_8 (0x00000400UL) +#define USBHS_DTHRCTL_AHBTHRRATIO_POS (11U) +#define USBHS_DTHRCTL_AHBTHRRATIO (0x00001800UL) +#define USBHS_DTHRCTL_AHBTHRRATIO_0 (0x00000800UL) +#define USBHS_DTHRCTL_AHBTHRRATIO_1 (0x00001000UL) +#define USBHS_DTHRCTL_RXTHREN_POS (16U) +#define USBHS_DTHRCTL_RXTHREN (0x00010000UL) +#define USBHS_DTHRCTL_RXTHRLEN_POS (17U) +#define USBHS_DTHRCTL_RXTHRLEN (0x03FE0000UL) +#define USBHS_DTHRCTL_RXTHRLEN_0 (0x00020000UL) +#define USBHS_DTHRCTL_RXTHRLEN_1 (0x00040000UL) +#define USBHS_DTHRCTL_RXTHRLEN_2 (0x00080000UL) +#define USBHS_DTHRCTL_RXTHRLEN_3 (0x00100000UL) +#define USBHS_DTHRCTL_RXTHRLEN_4 (0x00200000UL) +#define USBHS_DTHRCTL_RXTHRLEN_5 (0x00400000UL) +#define USBHS_DTHRCTL_RXTHRLEN_6 (0x00800000UL) +#define USBHS_DTHRCTL_RXTHRLEN_7 (0x01000000UL) +#define USBHS_DTHRCTL_RXTHRLEN_8 (0x02000000UL) +#define USBHS_DTHRCTL_ARBPRKEN_POS (27U) +#define USBHS_DTHRCTL_ARBPRKEN (0x08000000UL) + +/* Bit definition for USBHS_DIEPEMPMSK register */ +#define USBHS_DIEPEMPMSK_INEPTXFEMPMSK (0x0000FFFFUL) + +/* Bit definition for USBHS_DEACHINT register */ +#define USBHS_DEACHINT_ECHINEPINT_POS (0U) +#define USBHS_DEACHINT_ECHINEPINT (0x0000FFFFUL) +#define USBHS_DEACHINT_ECHINEPINT_0 (0x00000001UL) +#define USBHS_DEACHINT_ECHINEPINT_1 (0x00000002UL) +#define USBHS_DEACHINT_ECHINEPINT_2 (0x00000004UL) +#define USBHS_DEACHINT_ECHINEPINT_3 (0x00000008UL) +#define USBHS_DEACHINT_ECHINEPINT_4 (0x00000010UL) +#define USBHS_DEACHINT_ECHINEPINT_5 (0x00000020UL) +#define USBHS_DEACHINT_ECHINEPINT_6 (0x00000040UL) +#define USBHS_DEACHINT_ECHINEPINT_7 (0x00000080UL) +#define USBHS_DEACHINT_ECHINEPINT_8 (0x00000100UL) +#define USBHS_DEACHINT_ECHINEPINT_9 (0x00000200UL) +#define USBHS_DEACHINT_ECHINEPINT_10 (0x00000400UL) +#define USBHS_DEACHINT_ECHINEPINT_11 (0x00000800UL) +#define USBHS_DEACHINT_ECHINEPINT_12 (0x00001000UL) +#define USBHS_DEACHINT_ECHINEPINT_13 (0x00002000UL) +#define USBHS_DEACHINT_ECHINEPINT_14 (0x00004000UL) +#define USBHS_DEACHINT_ECHINEPINT_15 (0x00008000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_POS (16U) +#define USBHS_DEACHINT_ECHOUTEPINT (0xFFFF0000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_0 (0x00010000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_1 (0x00020000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_2 (0x00040000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_3 (0x00080000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_4 (0x00100000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_5 (0x00200000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_6 (0x00400000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_7 (0x00800000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_8 (0x01000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_9 (0x02000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_10 (0x04000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_11 (0x08000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_12 (0x10000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_13 (0x20000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_14 (0x40000000UL) +#define USBHS_DEACHINT_ECHOUTEPINT_15 (0x80000000UL) + +/* Bit definition for USBHS_DEACHINTMSK register */ +#define USBHS_DEACHINTMSK_ECHINEPMSK0_POS (0U) +#define USBHS_DEACHINTMSK_ECHINEPMSK0 (0x00000001UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK1_POS (1U) +#define USBHS_DEACHINTMSK_ECHINEPMSK1 (0x00000002UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK2_POS (2U) +#define USBHS_DEACHINTMSK_ECHINEPMSK2 (0x00000004UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK3_POS (3U) +#define USBHS_DEACHINTMSK_ECHINEPMSK3 (0x00000008UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK4_POS (4U) +#define USBHS_DEACHINTMSK_ECHINEPMSK4 (0x00000010UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK5_POS (5U) +#define USBHS_DEACHINTMSK_ECHINEPMSK5 (0x00000020UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK6_POS (6U) +#define USBHS_DEACHINTMSK_ECHINEPMSK6 (0x00000040UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK7_POS (7U) +#define USBHS_DEACHINTMSK_ECHINEPMSK7 (0x00000080UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK8_POS (8U) +#define USBHS_DEACHINTMSK_ECHINEPMSK8 (0x00000100UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK9_POS (9U) +#define USBHS_DEACHINTMSK_ECHINEPMSK9 (0x00000200UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK10_POS (10U) +#define USBHS_DEACHINTMSK_ECHINEPMSK10 (0x00000400UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK11_POS (11U) +#define USBHS_DEACHINTMSK_ECHINEPMSK11 (0x00000800UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK12_POS (12U) +#define USBHS_DEACHINTMSK_ECHINEPMSK12 (0x00001000UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK13_POS (13U) +#define USBHS_DEACHINTMSK_ECHINEPMSK13 (0x00002000UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK14_POS (14U) +#define USBHS_DEACHINTMSK_ECHINEPMSK14 (0x00004000UL) +#define USBHS_DEACHINTMSK_ECHINEPMSK15_POS (15U) +#define USBHS_DEACHINTMSK_ECHINEPMSK15 (0x00008000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK0_POS (16U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK0 (0x00010000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK1_POS (17U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK1 (0x00020000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK2_POS (18U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK2 (0x00040000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK3_POS (19U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK3 (0x00080000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK4_POS (20U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK4 (0x00100000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK5_POS (21U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK5 (0x00200000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK6_POS (22U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK6 (0x00400000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK7_POS (23U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK7 (0x00800000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK8_POS (24U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK8 (0x01000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK9_POS (25U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK9 (0x02000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK10_POS (26U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK10 (0x04000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK11_POS (27U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK11 (0x08000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK12_POS (28U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK12 (0x10000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK13_POS (29U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK13 (0x20000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK14_POS (30U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK14 (0x40000000UL) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK15_POS (31U) +#define USBHS_DEACHINTMSK_ECHOUTEPMSK15 (0x80000000UL) + +/* Bit definition for USBHS_DIEPEACHMSK1 register */ +#define USBHS_DIEPEACHMSK1_XFERCOMPLMSK_POS (0U) +#define USBHS_DIEPEACHMSK1_XFERCOMPLMSK (0x00000001UL) +#define USBHS_DIEPEACHMSK1_EPDISBLDMSK_POS (1U) +#define USBHS_DIEPEACHMSK1_EPDISBLDMSK (0x00000002UL) +#define USBHS_DIEPEACHMSK1_AHBERRMSK_POS (2U) +#define USBHS_DIEPEACHMSK1_AHBERRMSK (0x00000004UL) +#define USBHS_DIEPEACHMSK1_TIMEOUTMSK_POS (3U) +#define USBHS_DIEPEACHMSK1_TIMEOUTMSK (0x00000008UL) +#define USBHS_DIEPEACHMSK1_INTKNTXFEMPMSK_POS (4U) +#define USBHS_DIEPEACHMSK1_INTKNTXFEMPMSK (0x00000010UL) +#define USBHS_DIEPEACHMSK1_INTKNEPMISMSK_POS (5U) +#define USBHS_DIEPEACHMSK1_INTKNEPMISMSK (0x00000020UL) +#define USBHS_DIEPEACHMSK1_INEPNAKEFFMSK_POS (6U) +#define USBHS_DIEPEACHMSK1_INEPNAKEFFMSK (0x00000040UL) +#define USBHS_DIEPEACHMSK1_TXFIFOUNDRNMSK_POS (8U) +#define USBHS_DIEPEACHMSK1_TXFIFOUNDRNMSK (0x00000100UL) +#define USBHS_DIEPEACHMSK1_NAKMSK_POS (13U) +#define USBHS_DIEPEACHMSK1_NAKMSK (0x00002000UL) + +/* Bit definition for USBHS_DOEPEACHMSK1 register */ +#define USBHS_DOEPEACHMSK1_XFERCOMPLMSK_POS (0U) +#define USBHS_DOEPEACHMSK1_XFERCOMPLMSK (0x00000001UL) +#define USBHS_DOEPEACHMSK1_EPDISBLDMSK_POS (1U) +#define USBHS_DOEPEACHMSK1_EPDISBLDMSK (0x00000002UL) +#define USBHS_DOEPEACHMSK1_AHBERRMSK_POS (2U) +#define USBHS_DOEPEACHMSK1_AHBERRMSK (0x00000004UL) +#define USBHS_DOEPEACHMSK1_SETUPMSK_POS (3U) +#define USBHS_DOEPEACHMSK1_SETUPMSK (0x00000008UL) +#define USBHS_DOEPEACHMSK1_OUTTKNEPDISMSK_POS (4U) +#define USBHS_DOEPEACHMSK1_OUTTKNEPDISMSK (0x00000010UL) +#define USBHS_DOEPEACHMSK1_STSPHSRCVDMSK_POS (5U) +#define USBHS_DOEPEACHMSK1_STSPHSRCVDMSK (0x00000020UL) +#define USBHS_DOEPEACHMSK1_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPEACHMSK1_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPEACHMSK1_OUTPKTERRMSK_POS (8U) +#define USBHS_DOEPEACHMSK1_OUTPKTERRMSK (0x00000100UL) +#define USBHS_DOEPEACHMSK1_BBLEERRMSK_POS (12U) +#define USBHS_DOEPEACHMSK1_BBLEERRMSK (0x00001000UL) +#define USBHS_DOEPEACHMSK1_NAKMSK_POS (13U) +#define USBHS_DOEPEACHMSK1_NAKMSK (0x00002000UL) +#define USBHS_DOEPEACHMSK1_NYETMSK_POS (14U) +#define USBHS_DOEPEACHMSK1_NYETMSK (0x00004000UL) + +/* Bit definition for USBHS_DIEPCTL0 register */ +#define USBHS_DIEPCTL0_MPS_POS (0U) +#define USBHS_DIEPCTL0_MPS (0x00000003UL) +#define USBHS_DIEPCTL0_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL0_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL0_USBACTEP_POS (15U) +#define USBHS_DIEPCTL0_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL0_NAKSTS_POS (17U) +#define USBHS_DIEPCTL0_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL0_EPTYPE_POS (18U) +#define USBHS_DIEPCTL0_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL0_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL0_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL0_STALL_POS (21U) +#define USBHS_DIEPCTL0_STALL (0x00200000UL) +#define USBHS_DIEPCTL0_TXFNUM_POS (22U) +#define USBHS_DIEPCTL0_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL0_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL0_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL0_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL0_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL0_CNAK_POS (26U) +#define USBHS_DIEPCTL0_CNAK (0x04000000UL) +#define USBHS_DIEPCTL0_SNAK_POS (27U) +#define USBHS_DIEPCTL0_SNAK (0x08000000UL) +#define USBHS_DIEPCTL0_EPDIS_POS (30U) +#define USBHS_DIEPCTL0_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL0_EPENA_POS (31U) +#define USBHS_DIEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT0 register */ +#define USBHS_DIEPINT0_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT0_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT0_EPDISBLD_POS (1U) +#define USBHS_DIEPINT0_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT0_AHBERR_POS (2U) +#define USBHS_DIEPINT0_AHBERR (0x00000004UL) +#define USBHS_DIEPINT0_TIMEOUT_POS (3U) +#define USBHS_DIEPINT0_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT0_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT0_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT0_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT0_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT0_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT0_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT0_TXFEMP_POS (7U) +#define USBHS_DIEPINT0_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT0_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT0_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT0_BNAINTR_POS (9U) +#define USBHS_DIEPINT0_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT0_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT0_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT0_BBLEERR_POS (12U) +#define USBHS_DIEPINT0_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT0_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT0_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT0_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT0_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ0 register */ +#define USBHS_DIEPTSIZ0_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ0_XFERSIZE (0x0000007FUL) +#define USBHS_DIEPTSIZ0_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ0_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ0_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ0_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ0_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ0_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ0_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ0_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ0_PKTCNT (0x00180000UL) +#define USBHS_DIEPTSIZ0_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ0_PKTCNT_1 (0x00100000UL) + +/* Bit definition for USBHS_DIEPDMA0 register */ +#define USBHS_DIEPDMA0 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS0 register */ +#define USBHS_DTXFSTS0_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL1 register */ +#define USBHS_DIEPCTL1_MPS_POS (0U) +#define USBHS_DIEPCTL1_MPS (0x000007FFUL) +#define USBHS_DIEPCTL1_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL1_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL1_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL1_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL1_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL1_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL1_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL1_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL1_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL1_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL1_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL1_USBACTEP_POS (15U) +#define USBHS_DIEPCTL1_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL1_DPID_POS (16U) +#define USBHS_DIEPCTL1_DPID (0x00010000UL) +#define USBHS_DIEPCTL1_NAKSTS_POS (17U) +#define USBHS_DIEPCTL1_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL1_EPTYPE_POS (18U) +#define USBHS_DIEPCTL1_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL1_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL1_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL1_STALL_POS (21U) +#define USBHS_DIEPCTL1_STALL (0x00200000UL) +#define USBHS_DIEPCTL1_TXFNUM_POS (22U) +#define USBHS_DIEPCTL1_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL1_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL1_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL1_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL1_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL1_CNAK_POS (26U) +#define USBHS_DIEPCTL1_CNAK (0x04000000UL) +#define USBHS_DIEPCTL1_SNAK_POS (27U) +#define USBHS_DIEPCTL1_SNAK (0x08000000UL) +#define USBHS_DIEPCTL1_SETD0PID_POS (28U) +#define USBHS_DIEPCTL1_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL1_SETD1PID_POS (29U) +#define USBHS_DIEPCTL1_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL1_EPDIS_POS (30U) +#define USBHS_DIEPCTL1_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL1_EPENA_POS (31U) +#define USBHS_DIEPCTL1_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT1 register */ +#define USBHS_DIEPINT1_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT1_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT1_EPDISBLD_POS (1U) +#define USBHS_DIEPINT1_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT1_AHBERR_POS (2U) +#define USBHS_DIEPINT1_AHBERR (0x00000004UL) +#define USBHS_DIEPINT1_TIMEOUT_POS (3U) +#define USBHS_DIEPINT1_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT1_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT1_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT1_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT1_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT1_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT1_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT1_TXFEMP_POS (7U) +#define USBHS_DIEPINT1_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT1_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT1_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT1_BNAINTR_POS (9U) +#define USBHS_DIEPINT1_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT1_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT1_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT1_BBLEERR_POS (12U) +#define USBHS_DIEPINT1_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT1_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT1_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT1_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT1_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ1 register */ +#define USBHS_DIEPTSIZ1_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ1_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ1_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ1_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ1_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ1_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ1_MC_POS (29U) +#define USBHS_DIEPTSIZ1_MC (0x60000000UL) +#define USBHS_DIEPTSIZ1_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ1_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA1 register */ +#define USBHS_DIEPDMA1 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS1 register */ +#define USBHS_DTXFSTS1_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL2 register */ +#define USBHS_DIEPCTL2_MPS_POS (0U) +#define USBHS_DIEPCTL2_MPS (0x000007FFUL) +#define USBHS_DIEPCTL2_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL2_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL2_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL2_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL2_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL2_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL2_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL2_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL2_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL2_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL2_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL2_USBACTEP_POS (15U) +#define USBHS_DIEPCTL2_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL2_DPID_POS (16U) +#define USBHS_DIEPCTL2_DPID (0x00010000UL) +#define USBHS_DIEPCTL2_NAKSTS_POS (17U) +#define USBHS_DIEPCTL2_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL2_EPTYPE_POS (18U) +#define USBHS_DIEPCTL2_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL2_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL2_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL2_STALL_POS (21U) +#define USBHS_DIEPCTL2_STALL (0x00200000UL) +#define USBHS_DIEPCTL2_TXFNUM_POS (22U) +#define USBHS_DIEPCTL2_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL2_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL2_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL2_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL2_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL2_CNAK_POS (26U) +#define USBHS_DIEPCTL2_CNAK (0x04000000UL) +#define USBHS_DIEPCTL2_SNAK_POS (27U) +#define USBHS_DIEPCTL2_SNAK (0x08000000UL) +#define USBHS_DIEPCTL2_SETD0PID_POS (28U) +#define USBHS_DIEPCTL2_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL2_SETD1PID_POS (29U) +#define USBHS_DIEPCTL2_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL2_EPDIS_POS (30U) +#define USBHS_DIEPCTL2_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL2_EPENA_POS (31U) +#define USBHS_DIEPCTL2_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT2 register */ +#define USBHS_DIEPINT2_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT2_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT2_EPDISBLD_POS (1U) +#define USBHS_DIEPINT2_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT2_AHBERR_POS (2U) +#define USBHS_DIEPINT2_AHBERR (0x00000004UL) +#define USBHS_DIEPINT2_TIMEOUT_POS (3U) +#define USBHS_DIEPINT2_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT2_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT2_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT2_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT2_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT2_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT2_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT2_TXFEMP_POS (7U) +#define USBHS_DIEPINT2_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT2_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT2_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT2_BNAINTR_POS (9U) +#define USBHS_DIEPINT2_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT2_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT2_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT2_BBLEERR_POS (12U) +#define USBHS_DIEPINT2_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT2_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT2_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT2_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT2_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ2 register */ +#define USBHS_DIEPTSIZ2_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ2_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ2_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ2_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ2_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ2_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ2_MC_POS (29U) +#define USBHS_DIEPTSIZ2_MC (0x60000000UL) +#define USBHS_DIEPTSIZ2_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ2_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA2 register */ +#define USBHS_DIEPDMA2 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS2 register */ +#define USBHS_DTXFSTS2_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL3 register */ +#define USBHS_DIEPCTL3_MPS_POS (0U) +#define USBHS_DIEPCTL3_MPS (0x000007FFUL) +#define USBHS_DIEPCTL3_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL3_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL3_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL3_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL3_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL3_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL3_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL3_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL3_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL3_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL3_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL3_USBACTEP_POS (15U) +#define USBHS_DIEPCTL3_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL3_DPID_POS (16U) +#define USBHS_DIEPCTL3_DPID (0x00010000UL) +#define USBHS_DIEPCTL3_NAKSTS_POS (17U) +#define USBHS_DIEPCTL3_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL3_EPTYPE_POS (18U) +#define USBHS_DIEPCTL3_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL3_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL3_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL3_STALL_POS (21U) +#define USBHS_DIEPCTL3_STALL (0x00200000UL) +#define USBHS_DIEPCTL3_TXFNUM_POS (22U) +#define USBHS_DIEPCTL3_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL3_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL3_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL3_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL3_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL3_CNAK_POS (26U) +#define USBHS_DIEPCTL3_CNAK (0x04000000UL) +#define USBHS_DIEPCTL3_SNAK_POS (27U) +#define USBHS_DIEPCTL3_SNAK (0x08000000UL) +#define USBHS_DIEPCTL3_SETD0PID_POS (28U) +#define USBHS_DIEPCTL3_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL3_SETD1PID_POS (29U) +#define USBHS_DIEPCTL3_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL3_EPDIS_POS (30U) +#define USBHS_DIEPCTL3_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL3_EPENA_POS (31U) +#define USBHS_DIEPCTL3_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT3 register */ +#define USBHS_DIEPINT3_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT3_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT3_EPDISBLD_POS (1U) +#define USBHS_DIEPINT3_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT3_AHBERR_POS (2U) +#define USBHS_DIEPINT3_AHBERR (0x00000004UL) +#define USBHS_DIEPINT3_TIMEOUT_POS (3U) +#define USBHS_DIEPINT3_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT3_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT3_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT3_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT3_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT3_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT3_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT3_TXFEMP_POS (7U) +#define USBHS_DIEPINT3_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT3_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT3_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT3_BNAINTR_POS (9U) +#define USBHS_DIEPINT3_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT3_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT3_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT3_BBLEERR_POS (12U) +#define USBHS_DIEPINT3_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT3_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT3_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT3_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT3_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ3 register */ +#define USBHS_DIEPTSIZ3_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ3_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ3_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ3_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ3_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ3_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ3_MC_POS (29U) +#define USBHS_DIEPTSIZ3_MC (0x60000000UL) +#define USBHS_DIEPTSIZ3_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ3_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA3 register */ +#define USBHS_DIEPDMA3 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS3 register */ +#define USBHS_DTXFSTS3_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL4 register */ +#define USBHS_DIEPCTL4_MPS_POS (0U) +#define USBHS_DIEPCTL4_MPS (0x000007FFUL) +#define USBHS_DIEPCTL4_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL4_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL4_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL4_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL4_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL4_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL4_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL4_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL4_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL4_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL4_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL4_USBACTEP_POS (15U) +#define USBHS_DIEPCTL4_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL4_DPID_POS (16U) +#define USBHS_DIEPCTL4_DPID (0x00010000UL) +#define USBHS_DIEPCTL4_NAKSTS_POS (17U) +#define USBHS_DIEPCTL4_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL4_EPTYPE_POS (18U) +#define USBHS_DIEPCTL4_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL4_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL4_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL4_STALL_POS (21U) +#define USBHS_DIEPCTL4_STALL (0x00200000UL) +#define USBHS_DIEPCTL4_TXFNUM_POS (22U) +#define USBHS_DIEPCTL4_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL4_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL4_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL4_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL4_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL4_CNAK_POS (26U) +#define USBHS_DIEPCTL4_CNAK (0x04000000UL) +#define USBHS_DIEPCTL4_SNAK_POS (27U) +#define USBHS_DIEPCTL4_SNAK (0x08000000UL) +#define USBHS_DIEPCTL4_SETD0PID_POS (28U) +#define USBHS_DIEPCTL4_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL4_SETD1PID_POS (29U) +#define USBHS_DIEPCTL4_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL4_EPDIS_POS (30U) +#define USBHS_DIEPCTL4_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL4_EPENA_POS (31U) +#define USBHS_DIEPCTL4_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT4 register */ +#define USBHS_DIEPINT4_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT4_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT4_EPDISBLD_POS (1U) +#define USBHS_DIEPINT4_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT4_AHBERR_POS (2U) +#define USBHS_DIEPINT4_AHBERR (0x00000004UL) +#define USBHS_DIEPINT4_TIMEOUT_POS (3U) +#define USBHS_DIEPINT4_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT4_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT4_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT4_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT4_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT4_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT4_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT4_TXFEMP_POS (7U) +#define USBHS_DIEPINT4_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT4_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT4_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT4_BNAINTR_POS (9U) +#define USBHS_DIEPINT4_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT4_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT4_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT4_BBLEERR_POS (12U) +#define USBHS_DIEPINT4_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT4_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT4_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT4_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT4_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ4 register */ +#define USBHS_DIEPTSIZ4_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ4_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ4_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ4_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ4_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ4_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ4_MC_POS (29U) +#define USBHS_DIEPTSIZ4_MC (0x60000000UL) +#define USBHS_DIEPTSIZ4_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ4_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA4 register */ +#define USBHS_DIEPDMA4 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS4 register */ +#define USBHS_DTXFSTS4_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL5 register */ +#define USBHS_DIEPCTL5_MPS_POS (0U) +#define USBHS_DIEPCTL5_MPS (0x000007FFUL) +#define USBHS_DIEPCTL5_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL5_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL5_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL5_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL5_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL5_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL5_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL5_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL5_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL5_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL5_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL5_USBACTEP_POS (15U) +#define USBHS_DIEPCTL5_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL5_DPID_POS (16U) +#define USBHS_DIEPCTL5_DPID (0x00010000UL) +#define USBHS_DIEPCTL5_NAKSTS_POS (17U) +#define USBHS_DIEPCTL5_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL5_EPTYPE_POS (18U) +#define USBHS_DIEPCTL5_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL5_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL5_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL5_STALL_POS (21U) +#define USBHS_DIEPCTL5_STALL (0x00200000UL) +#define USBHS_DIEPCTL5_TXFNUM_POS (22U) +#define USBHS_DIEPCTL5_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL5_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL5_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL5_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL5_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL5_CNAK_POS (26U) +#define USBHS_DIEPCTL5_CNAK (0x04000000UL) +#define USBHS_DIEPCTL5_SNAK_POS (27U) +#define USBHS_DIEPCTL5_SNAK (0x08000000UL) +#define USBHS_DIEPCTL5_SETD0PID_POS (28U) +#define USBHS_DIEPCTL5_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL5_SETD1PID_POS (29U) +#define USBHS_DIEPCTL5_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL5_EPDIS_POS (30U) +#define USBHS_DIEPCTL5_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL5_EPENA_POS (31U) +#define USBHS_DIEPCTL5_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT5 register */ +#define USBHS_DIEPINT5_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT5_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT5_EPDISBLD_POS (1U) +#define USBHS_DIEPINT5_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT5_AHBERR_POS (2U) +#define USBHS_DIEPINT5_AHBERR (0x00000004UL) +#define USBHS_DIEPINT5_TIMEOUT_POS (3U) +#define USBHS_DIEPINT5_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT5_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT5_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT5_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT5_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT5_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT5_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT5_TXFEMP_POS (7U) +#define USBHS_DIEPINT5_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT5_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT5_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT5_BNAINTR_POS (9U) +#define USBHS_DIEPINT5_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT5_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT5_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT5_BBLEERR_POS (12U) +#define USBHS_DIEPINT5_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT5_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT5_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT5_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT5_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ5 register */ +#define USBHS_DIEPTSIZ5_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ5_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ5_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ5_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ5_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ5_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ5_MC_POS (29U) +#define USBHS_DIEPTSIZ5_MC (0x60000000UL) +#define USBHS_DIEPTSIZ5_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ5_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA5 register */ +#define USBHS_DIEPDMA5 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS5 register */ +#define USBHS_DTXFSTS5_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL6 register */ +#define USBHS_DIEPCTL6_MPS_POS (0U) +#define USBHS_DIEPCTL6_MPS (0x000007FFUL) +#define USBHS_DIEPCTL6_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL6_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL6_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL6_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL6_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL6_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL6_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL6_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL6_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL6_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL6_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL6_USBACTEP_POS (15U) +#define USBHS_DIEPCTL6_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL6_DPID_POS (16U) +#define USBHS_DIEPCTL6_DPID (0x00010000UL) +#define USBHS_DIEPCTL6_NAKSTS_POS (17U) +#define USBHS_DIEPCTL6_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL6_EPTYPE_POS (18U) +#define USBHS_DIEPCTL6_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL6_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL6_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL6_STALL_POS (21U) +#define USBHS_DIEPCTL6_STALL (0x00200000UL) +#define USBHS_DIEPCTL6_TXFNUM_POS (22U) +#define USBHS_DIEPCTL6_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL6_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL6_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL6_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL6_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL6_CNAK_POS (26U) +#define USBHS_DIEPCTL6_CNAK (0x04000000UL) +#define USBHS_DIEPCTL6_SNAK_POS (27U) +#define USBHS_DIEPCTL6_SNAK (0x08000000UL) +#define USBHS_DIEPCTL6_SETD0PID_POS (28U) +#define USBHS_DIEPCTL6_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL6_SETD1PID_POS (29U) +#define USBHS_DIEPCTL6_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL6_EPDIS_POS (30U) +#define USBHS_DIEPCTL6_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL6_EPENA_POS (31U) +#define USBHS_DIEPCTL6_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT6 register */ +#define USBHS_DIEPINT6_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT6_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT6_EPDISBLD_POS (1U) +#define USBHS_DIEPINT6_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT6_AHBERR_POS (2U) +#define USBHS_DIEPINT6_AHBERR (0x00000004UL) +#define USBHS_DIEPINT6_TIMEOUT_POS (3U) +#define USBHS_DIEPINT6_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT6_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT6_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT6_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT6_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT6_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT6_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT6_TXFEMP_POS (7U) +#define USBHS_DIEPINT6_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT6_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT6_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT6_BNAINTR_POS (9U) +#define USBHS_DIEPINT6_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT6_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT6_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT6_BBLEERR_POS (12U) +#define USBHS_DIEPINT6_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT6_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT6_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT6_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT6_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ6 register */ +#define USBHS_DIEPTSIZ6_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ6_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ6_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ6_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ6_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ6_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ6_MC_POS (29U) +#define USBHS_DIEPTSIZ6_MC (0x60000000UL) +#define USBHS_DIEPTSIZ6_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ6_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA6 register */ +#define USBHS_DIEPDMA6 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS6 register */ +#define USBHS_DTXFSTS6_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL7 register */ +#define USBHS_DIEPCTL7_MPS_POS (0U) +#define USBHS_DIEPCTL7_MPS (0x000007FFUL) +#define USBHS_DIEPCTL7_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL7_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL7_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL7_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL7_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL7_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL7_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL7_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL7_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL7_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL7_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL7_USBACTEP_POS (15U) +#define USBHS_DIEPCTL7_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL7_DPID_POS (16U) +#define USBHS_DIEPCTL7_DPID (0x00010000UL) +#define USBHS_DIEPCTL7_NAKSTS_POS (17U) +#define USBHS_DIEPCTL7_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL7_EPTYPE_POS (18U) +#define USBHS_DIEPCTL7_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL7_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL7_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL7_STALL_POS (21U) +#define USBHS_DIEPCTL7_STALL (0x00200000UL) +#define USBHS_DIEPCTL7_TXFNUM_POS (22U) +#define USBHS_DIEPCTL7_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL7_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL7_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL7_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL7_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL7_CNAK_POS (26U) +#define USBHS_DIEPCTL7_CNAK (0x04000000UL) +#define USBHS_DIEPCTL7_SNAK_POS (27U) +#define USBHS_DIEPCTL7_SNAK (0x08000000UL) +#define USBHS_DIEPCTL7_SETD0PID_POS (28U) +#define USBHS_DIEPCTL7_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL7_SETD1PID_POS (29U) +#define USBHS_DIEPCTL7_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL7_EPDIS_POS (30U) +#define USBHS_DIEPCTL7_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL7_EPENA_POS (31U) +#define USBHS_DIEPCTL7_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT7 register */ +#define USBHS_DIEPINT7_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT7_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT7_EPDISBLD_POS (1U) +#define USBHS_DIEPINT7_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT7_AHBERR_POS (2U) +#define USBHS_DIEPINT7_AHBERR (0x00000004UL) +#define USBHS_DIEPINT7_TIMEOUT_POS (3U) +#define USBHS_DIEPINT7_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT7_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT7_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT7_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT7_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT7_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT7_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT7_TXFEMP_POS (7U) +#define USBHS_DIEPINT7_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT7_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT7_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT7_BNAINTR_POS (9U) +#define USBHS_DIEPINT7_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT7_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT7_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT7_BBLEERR_POS (12U) +#define USBHS_DIEPINT7_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT7_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT7_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT7_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT7_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ7 register */ +#define USBHS_DIEPTSIZ7_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ7_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ7_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ7_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ7_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ7_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ7_MC_POS (29U) +#define USBHS_DIEPTSIZ7_MC (0x60000000UL) +#define USBHS_DIEPTSIZ7_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ7_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA7 register */ +#define USBHS_DIEPDMA7 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS7 register */ +#define USBHS_DTXFSTS7_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL8 register */ +#define USBHS_DIEPCTL8_MPS_POS (0U) +#define USBHS_DIEPCTL8_MPS (0x000007FFUL) +#define USBHS_DIEPCTL8_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL8_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL8_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL8_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL8_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL8_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL8_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL8_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL8_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL8_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL8_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL8_USBACTEP_POS (15U) +#define USBHS_DIEPCTL8_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL8_DPID_POS (16U) +#define USBHS_DIEPCTL8_DPID (0x00010000UL) +#define USBHS_DIEPCTL8_NAKSTS_POS (17U) +#define USBHS_DIEPCTL8_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL8_EPTYPE_POS (18U) +#define USBHS_DIEPCTL8_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL8_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL8_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL8_STALL_POS (21U) +#define USBHS_DIEPCTL8_STALL (0x00200000UL) +#define USBHS_DIEPCTL8_TXFNUM_POS (22U) +#define USBHS_DIEPCTL8_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL8_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL8_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL8_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL8_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL8_CNAK_POS (26U) +#define USBHS_DIEPCTL8_CNAK (0x04000000UL) +#define USBHS_DIEPCTL8_SNAK_POS (27U) +#define USBHS_DIEPCTL8_SNAK (0x08000000UL) +#define USBHS_DIEPCTL8_SETD0PID_POS (28U) +#define USBHS_DIEPCTL8_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL8_SETD1PID_POS (29U) +#define USBHS_DIEPCTL8_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL8_EPDIS_POS (30U) +#define USBHS_DIEPCTL8_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL8_EPENA_POS (31U) +#define USBHS_DIEPCTL8_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT8 register */ +#define USBHS_DIEPINT8_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT8_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT8_EPDISBLD_POS (1U) +#define USBHS_DIEPINT8_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT8_AHBERR_POS (2U) +#define USBHS_DIEPINT8_AHBERR (0x00000004UL) +#define USBHS_DIEPINT8_TIMEOUT_POS (3U) +#define USBHS_DIEPINT8_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT8_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT8_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT8_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT8_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT8_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT8_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT8_TXFEMP_POS (7U) +#define USBHS_DIEPINT8_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT8_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT8_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT8_BNAINTR_POS (9U) +#define USBHS_DIEPINT8_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT8_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT8_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT8_BBLEERR_POS (12U) +#define USBHS_DIEPINT8_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT8_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT8_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT8_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT8_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ8 register */ +#define USBHS_DIEPTSIZ8_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ8_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ8_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ8_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ8_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ8_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ8_MC_POS (29U) +#define USBHS_DIEPTSIZ8_MC (0x60000000UL) +#define USBHS_DIEPTSIZ8_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ8_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA8 register */ +#define USBHS_DIEPDMA8 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS8 register */ +#define USBHS_DTXFSTS8_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL9 register */ +#define USBHS_DIEPCTL9_MPS_POS (0U) +#define USBHS_DIEPCTL9_MPS (0x000007FFUL) +#define USBHS_DIEPCTL9_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL9_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL9_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL9_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL9_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL9_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL9_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL9_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL9_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL9_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL9_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL9_USBACTEP_POS (15U) +#define USBHS_DIEPCTL9_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL9_DPID_POS (16U) +#define USBHS_DIEPCTL9_DPID (0x00010000UL) +#define USBHS_DIEPCTL9_NAKSTS_POS (17U) +#define USBHS_DIEPCTL9_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL9_EPTYPE_POS (18U) +#define USBHS_DIEPCTL9_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL9_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL9_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL9_STALL_POS (21U) +#define USBHS_DIEPCTL9_STALL (0x00200000UL) +#define USBHS_DIEPCTL9_TXFNUM_POS (22U) +#define USBHS_DIEPCTL9_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL9_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL9_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL9_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL9_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL9_CNAK_POS (26U) +#define USBHS_DIEPCTL9_CNAK (0x04000000UL) +#define USBHS_DIEPCTL9_SNAK_POS (27U) +#define USBHS_DIEPCTL9_SNAK (0x08000000UL) +#define USBHS_DIEPCTL9_SETD0PID_POS (28U) +#define USBHS_DIEPCTL9_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL9_SETD1PID_POS (29U) +#define USBHS_DIEPCTL9_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL9_EPDIS_POS (30U) +#define USBHS_DIEPCTL9_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL9_EPENA_POS (31U) +#define USBHS_DIEPCTL9_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT9 register */ +#define USBHS_DIEPINT9_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT9_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT9_EPDISBLD_POS (1U) +#define USBHS_DIEPINT9_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT9_AHBERR_POS (2U) +#define USBHS_DIEPINT9_AHBERR (0x00000004UL) +#define USBHS_DIEPINT9_TIMEOUT_POS (3U) +#define USBHS_DIEPINT9_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT9_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT9_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT9_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT9_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT9_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT9_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT9_TXFEMP_POS (7U) +#define USBHS_DIEPINT9_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT9_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT9_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT9_BNAINTR_POS (9U) +#define USBHS_DIEPINT9_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT9_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT9_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT9_BBLEERR_POS (12U) +#define USBHS_DIEPINT9_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT9_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT9_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT9_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT9_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ9 register */ +#define USBHS_DIEPTSIZ9_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ9_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ9_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ9_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ9_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ9_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ9_MC_POS (29U) +#define USBHS_DIEPTSIZ9_MC (0x60000000UL) +#define USBHS_DIEPTSIZ9_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ9_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA9 register */ +#define USBHS_DIEPDMA9 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS9 register */ +#define USBHS_DTXFSTS9_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL10 register */ +#define USBHS_DIEPCTL10_MPS_POS (0U) +#define USBHS_DIEPCTL10_MPS (0x000007FFUL) +#define USBHS_DIEPCTL10_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL10_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL10_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL10_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL10_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL10_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL10_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL10_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL10_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL10_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL10_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL10_USBACTEP_POS (15U) +#define USBHS_DIEPCTL10_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL10_DPID_POS (16U) +#define USBHS_DIEPCTL10_DPID (0x00010000UL) +#define USBHS_DIEPCTL10_NAKSTS_POS (17U) +#define USBHS_DIEPCTL10_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL10_EPTYPE_POS (18U) +#define USBHS_DIEPCTL10_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL10_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL10_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL10_STALL_POS (21U) +#define USBHS_DIEPCTL10_STALL (0x00200000UL) +#define USBHS_DIEPCTL10_TXFNUM_POS (22U) +#define USBHS_DIEPCTL10_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL10_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL10_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL10_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL10_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL10_CNAK_POS (26U) +#define USBHS_DIEPCTL10_CNAK (0x04000000UL) +#define USBHS_DIEPCTL10_SNAK_POS (27U) +#define USBHS_DIEPCTL10_SNAK (0x08000000UL) +#define USBHS_DIEPCTL10_SETD0PID_POS (28U) +#define USBHS_DIEPCTL10_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL10_SETD1PID_POS (29U) +#define USBHS_DIEPCTL10_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL10_EPDIS_POS (30U) +#define USBHS_DIEPCTL10_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL10_EPENA_POS (31U) +#define USBHS_DIEPCTL10_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT10 register */ +#define USBHS_DIEPINT10_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT10_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT10_EPDISBLD_POS (1U) +#define USBHS_DIEPINT10_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT10_AHBERR_POS (2U) +#define USBHS_DIEPINT10_AHBERR (0x00000004UL) +#define USBHS_DIEPINT10_TIMEOUT_POS (3U) +#define USBHS_DIEPINT10_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT10_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT10_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT10_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT10_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT10_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT10_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT10_TXFEMP_POS (7U) +#define USBHS_DIEPINT10_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT10_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT10_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT10_BNAINTR_POS (9U) +#define USBHS_DIEPINT10_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT10_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT10_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT10_BBLEERR_POS (12U) +#define USBHS_DIEPINT10_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT10_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT10_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT10_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT10_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ10 register */ +#define USBHS_DIEPTSIZ10_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ10_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ10_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ10_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ10_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ10_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ10_MC_POS (29U) +#define USBHS_DIEPTSIZ10_MC (0x60000000UL) +#define USBHS_DIEPTSIZ10_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ10_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA10 register */ +#define USBHS_DIEPDMA10 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS10 register */ +#define USBHS_DTXFSTS10_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL11 register */ +#define USBHS_DIEPCTL11_MPS_POS (0U) +#define USBHS_DIEPCTL11_MPS (0x000007FFUL) +#define USBHS_DIEPCTL11_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL11_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL11_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL11_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL11_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL11_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL11_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL11_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL11_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL11_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL11_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL11_USBACTEP_POS (15U) +#define USBHS_DIEPCTL11_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL11_DPID_POS (16U) +#define USBHS_DIEPCTL11_DPID (0x00010000UL) +#define USBHS_DIEPCTL11_NAKSTS_POS (17U) +#define USBHS_DIEPCTL11_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL11_EPTYPE_POS (18U) +#define USBHS_DIEPCTL11_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL11_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL11_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL11_STALL_POS (21U) +#define USBHS_DIEPCTL11_STALL (0x00200000UL) +#define USBHS_DIEPCTL11_TXFNUM_POS (22U) +#define USBHS_DIEPCTL11_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL11_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL11_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL11_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL11_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL11_CNAK_POS (26U) +#define USBHS_DIEPCTL11_CNAK (0x04000000UL) +#define USBHS_DIEPCTL11_SNAK_POS (27U) +#define USBHS_DIEPCTL11_SNAK (0x08000000UL) +#define USBHS_DIEPCTL11_SETD0PID_POS (28U) +#define USBHS_DIEPCTL11_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL11_SETD1PID_POS (29U) +#define USBHS_DIEPCTL11_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL11_EPDIS_POS (30U) +#define USBHS_DIEPCTL11_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL11_EPENA_POS (31U) +#define USBHS_DIEPCTL11_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT11 register */ +#define USBHS_DIEPINT11_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT11_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT11_EPDISBLD_POS (1U) +#define USBHS_DIEPINT11_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT11_AHBERR_POS (2U) +#define USBHS_DIEPINT11_AHBERR (0x00000004UL) +#define USBHS_DIEPINT11_TIMEOUT_POS (3U) +#define USBHS_DIEPINT11_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT11_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT11_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT11_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT11_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT11_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT11_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT11_TXFEMP_POS (7U) +#define USBHS_DIEPINT11_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT11_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT11_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT11_BNAINTR_POS (9U) +#define USBHS_DIEPINT11_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT11_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT11_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT11_BBLEERR_POS (12U) +#define USBHS_DIEPINT11_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT11_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT11_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT11_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT11_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ11 register */ +#define USBHS_DIEPTSIZ11_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ11_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ11_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ11_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ11_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ11_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ11_MC_POS (29U) +#define USBHS_DIEPTSIZ11_MC (0x60000000UL) +#define USBHS_DIEPTSIZ11_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ11_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA11 register */ +#define USBHS_DIEPDMA11 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS11 register */ +#define USBHS_DTXFSTS11_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL12 register */ +#define USBHS_DIEPCTL12_MPS_POS (0U) +#define USBHS_DIEPCTL12_MPS (0x000007FFUL) +#define USBHS_DIEPCTL12_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL12_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL12_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL12_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL12_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL12_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL12_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL12_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL12_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL12_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL12_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL12_USBACTEP_POS (15U) +#define USBHS_DIEPCTL12_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL12_DPID_POS (16U) +#define USBHS_DIEPCTL12_DPID (0x00010000UL) +#define USBHS_DIEPCTL12_NAKSTS_POS (17U) +#define USBHS_DIEPCTL12_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL12_EPTYPE_POS (18U) +#define USBHS_DIEPCTL12_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL12_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL12_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL12_STALL_POS (21U) +#define USBHS_DIEPCTL12_STALL (0x00200000UL) +#define USBHS_DIEPCTL12_TXFNUM_POS (22U) +#define USBHS_DIEPCTL12_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL12_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL12_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL12_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL12_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL12_CNAK_POS (26U) +#define USBHS_DIEPCTL12_CNAK (0x04000000UL) +#define USBHS_DIEPCTL12_SNAK_POS (27U) +#define USBHS_DIEPCTL12_SNAK (0x08000000UL) +#define USBHS_DIEPCTL12_SETD0PID_POS (28U) +#define USBHS_DIEPCTL12_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL12_SETD1PID_POS (29U) +#define USBHS_DIEPCTL12_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL12_EPDIS_POS (30U) +#define USBHS_DIEPCTL12_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL12_EPENA_POS (31U) +#define USBHS_DIEPCTL12_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT12 register */ +#define USBHS_DIEPINT12_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT12_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT12_EPDISBLD_POS (1U) +#define USBHS_DIEPINT12_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT12_AHBERR_POS (2U) +#define USBHS_DIEPINT12_AHBERR (0x00000004UL) +#define USBHS_DIEPINT12_TIMEOUT_POS (3U) +#define USBHS_DIEPINT12_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT12_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT12_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT12_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT12_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT12_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT12_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT12_TXFEMP_POS (7U) +#define USBHS_DIEPINT12_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT12_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT12_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT12_BNAINTR_POS (9U) +#define USBHS_DIEPINT12_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT12_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT12_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT12_BBLEERR_POS (12U) +#define USBHS_DIEPINT12_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT12_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT12_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT12_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT12_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ12 register */ +#define USBHS_DIEPTSIZ12_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ12_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ12_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ12_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ12_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ12_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ12_MC_POS (29U) +#define USBHS_DIEPTSIZ12_MC (0x60000000UL) +#define USBHS_DIEPTSIZ12_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ12_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA12 register */ +#define USBHS_DIEPDMA12 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS12 register */ +#define USBHS_DTXFSTS12_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL13 register */ +#define USBHS_DIEPCTL13_MPS_POS (0U) +#define USBHS_DIEPCTL13_MPS (0x000007FFUL) +#define USBHS_DIEPCTL13_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL13_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL13_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL13_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL13_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL13_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL13_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL13_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL13_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL13_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL13_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL13_USBACTEP_POS (15U) +#define USBHS_DIEPCTL13_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL13_DPID_POS (16U) +#define USBHS_DIEPCTL13_DPID (0x00010000UL) +#define USBHS_DIEPCTL13_NAKSTS_POS (17U) +#define USBHS_DIEPCTL13_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL13_EPTYPE_POS (18U) +#define USBHS_DIEPCTL13_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL13_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL13_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL13_STALL_POS (21U) +#define USBHS_DIEPCTL13_STALL (0x00200000UL) +#define USBHS_DIEPCTL13_TXFNUM_POS (22U) +#define USBHS_DIEPCTL13_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL13_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL13_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL13_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL13_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL13_CNAK_POS (26U) +#define USBHS_DIEPCTL13_CNAK (0x04000000UL) +#define USBHS_DIEPCTL13_SNAK_POS (27U) +#define USBHS_DIEPCTL13_SNAK (0x08000000UL) +#define USBHS_DIEPCTL13_SETD0PID_POS (28U) +#define USBHS_DIEPCTL13_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL13_SETD1PID_POS (29U) +#define USBHS_DIEPCTL13_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL13_EPDIS_POS (30U) +#define USBHS_DIEPCTL13_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL13_EPENA_POS (31U) +#define USBHS_DIEPCTL13_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT13 register */ +#define USBHS_DIEPINT13_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT13_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT13_EPDISBLD_POS (1U) +#define USBHS_DIEPINT13_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT13_AHBERR_POS (2U) +#define USBHS_DIEPINT13_AHBERR (0x00000004UL) +#define USBHS_DIEPINT13_TIMEOUT_POS (3U) +#define USBHS_DIEPINT13_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT13_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT13_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT13_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT13_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT13_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT13_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT13_TXFEMP_POS (7U) +#define USBHS_DIEPINT13_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT13_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT13_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT13_BNAINTR_POS (9U) +#define USBHS_DIEPINT13_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT13_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT13_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT13_BBLEERR_POS (12U) +#define USBHS_DIEPINT13_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT13_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT13_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT13_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT13_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ13 register */ +#define USBHS_DIEPTSIZ13_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ13_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ13_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ13_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ13_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ13_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ13_MC_POS (29U) +#define USBHS_DIEPTSIZ13_MC (0x60000000UL) +#define USBHS_DIEPTSIZ13_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ13_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA13 register */ +#define USBHS_DIEPDMA13 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS13 register */ +#define USBHS_DTXFSTS13_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL14 register */ +#define USBHS_DIEPCTL14_MPS_POS (0U) +#define USBHS_DIEPCTL14_MPS (0x000007FFUL) +#define USBHS_DIEPCTL14_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL14_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL14_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL14_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL14_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL14_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL14_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL14_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL14_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL14_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL14_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL14_USBACTEP_POS (15U) +#define USBHS_DIEPCTL14_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL14_DPID_POS (16U) +#define USBHS_DIEPCTL14_DPID (0x00010000UL) +#define USBHS_DIEPCTL14_NAKSTS_POS (17U) +#define USBHS_DIEPCTL14_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL14_EPTYPE_POS (18U) +#define USBHS_DIEPCTL14_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL14_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL14_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL14_STALL_POS (21U) +#define USBHS_DIEPCTL14_STALL (0x00200000UL) +#define USBHS_DIEPCTL14_TXFNUM_POS (22U) +#define USBHS_DIEPCTL14_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL14_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL14_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL14_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL14_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL14_CNAK_POS (26U) +#define USBHS_DIEPCTL14_CNAK (0x04000000UL) +#define USBHS_DIEPCTL14_SNAK_POS (27U) +#define USBHS_DIEPCTL14_SNAK (0x08000000UL) +#define USBHS_DIEPCTL14_SETD0PID_POS (28U) +#define USBHS_DIEPCTL14_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL14_SETD1PID_POS (29U) +#define USBHS_DIEPCTL14_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL14_EPDIS_POS (30U) +#define USBHS_DIEPCTL14_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL14_EPENA_POS (31U) +#define USBHS_DIEPCTL14_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT14 register */ +#define USBHS_DIEPINT14_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT14_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT14_EPDISBLD_POS (1U) +#define USBHS_DIEPINT14_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT14_AHBERR_POS (2U) +#define USBHS_DIEPINT14_AHBERR (0x00000004UL) +#define USBHS_DIEPINT14_TIMEOUT_POS (3U) +#define USBHS_DIEPINT14_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT14_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT14_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT14_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT14_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT14_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT14_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT14_TXFEMP_POS (7U) +#define USBHS_DIEPINT14_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT14_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT14_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT14_BNAINTR_POS (9U) +#define USBHS_DIEPINT14_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT14_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT14_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT14_BBLEERR_POS (12U) +#define USBHS_DIEPINT14_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT14_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT14_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT14_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT14_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ14 register */ +#define USBHS_DIEPTSIZ14_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ14_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ14_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ14_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ14_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ14_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ14_MC_POS (29U) +#define USBHS_DIEPTSIZ14_MC (0x60000000UL) +#define USBHS_DIEPTSIZ14_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ14_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA14 register */ +#define USBHS_DIEPDMA14 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS14 register */ +#define USBHS_DTXFSTS14_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DIEPCTL15 register */ +#define USBHS_DIEPCTL15_MPS_POS (0U) +#define USBHS_DIEPCTL15_MPS (0x000007FFUL) +#define USBHS_DIEPCTL15_MPS_0 (0x00000001UL) +#define USBHS_DIEPCTL15_MPS_1 (0x00000002UL) +#define USBHS_DIEPCTL15_MPS_2 (0x00000004UL) +#define USBHS_DIEPCTL15_MPS_3 (0x00000008UL) +#define USBHS_DIEPCTL15_MPS_4 (0x00000010UL) +#define USBHS_DIEPCTL15_MPS_5 (0x00000020UL) +#define USBHS_DIEPCTL15_MPS_6 (0x00000040UL) +#define USBHS_DIEPCTL15_MPS_7 (0x00000080UL) +#define USBHS_DIEPCTL15_MPS_8 (0x00000100UL) +#define USBHS_DIEPCTL15_MPS_9 (0x00000200UL) +#define USBHS_DIEPCTL15_MPS_10 (0x00000400UL) +#define USBHS_DIEPCTL15_USBACTEP_POS (15U) +#define USBHS_DIEPCTL15_USBACTEP (0x00008000UL) +#define USBHS_DIEPCTL15_DPID_POS (16U) +#define USBHS_DIEPCTL15_DPID (0x00010000UL) +#define USBHS_DIEPCTL15_NAKSTS_POS (17U) +#define USBHS_DIEPCTL15_NAKSTS (0x00020000UL) +#define USBHS_DIEPCTL15_EPTYPE_POS (18U) +#define USBHS_DIEPCTL15_EPTYPE (0x000C0000UL) +#define USBHS_DIEPCTL15_EPTYPE_0 (0x00040000UL) +#define USBHS_DIEPCTL15_EPTYPE_1 (0x00080000UL) +#define USBHS_DIEPCTL15_STALL_POS (21U) +#define USBHS_DIEPCTL15_STALL (0x00200000UL) +#define USBHS_DIEPCTL15_TXFNUM_POS (22U) +#define USBHS_DIEPCTL15_TXFNUM (0x03C00000UL) +#define USBHS_DIEPCTL15_TXFNUM_0 (0x00400000UL) +#define USBHS_DIEPCTL15_TXFNUM_1 (0x00800000UL) +#define USBHS_DIEPCTL15_TXFNUM_2 (0x01000000UL) +#define USBHS_DIEPCTL15_TXFNUM_3 (0x02000000UL) +#define USBHS_DIEPCTL15_CNAK_POS (26U) +#define USBHS_DIEPCTL15_CNAK (0x04000000UL) +#define USBHS_DIEPCTL15_SNAK_POS (27U) +#define USBHS_DIEPCTL15_SNAK (0x08000000UL) +#define USBHS_DIEPCTL15_SETD0PID_POS (28U) +#define USBHS_DIEPCTL15_SETD0PID (0x10000000UL) +#define USBHS_DIEPCTL15_SETD1PID_POS (29U) +#define USBHS_DIEPCTL15_SETD1PID (0x20000000UL) +#define USBHS_DIEPCTL15_EPDIS_POS (30U) +#define USBHS_DIEPCTL15_EPDIS (0x40000000UL) +#define USBHS_DIEPCTL15_EPENA_POS (31U) +#define USBHS_DIEPCTL15_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DIEPINT15 register */ +#define USBHS_DIEPINT15_XFERCOMPL_POS (0U) +#define USBHS_DIEPINT15_XFERCOMPL (0x00000001UL) +#define USBHS_DIEPINT15_EPDISBLD_POS (1U) +#define USBHS_DIEPINT15_EPDISBLD (0x00000002UL) +#define USBHS_DIEPINT15_AHBERR_POS (2U) +#define USBHS_DIEPINT15_AHBERR (0x00000004UL) +#define USBHS_DIEPINT15_TIMEOUT_POS (3U) +#define USBHS_DIEPINT15_TIMEOUT (0x00000008UL) +#define USBHS_DIEPINT15_INTKNTXFEMP_POS (4U) +#define USBHS_DIEPINT15_INTKNTXFEMP (0x00000010UL) +#define USBHS_DIEPINT15_INTKNEPMIS_POS (5U) +#define USBHS_DIEPINT15_INTKNEPMIS (0x00000020UL) +#define USBHS_DIEPINT15_INEPNAKEFF_POS (6U) +#define USBHS_DIEPINT15_INEPNAKEFF (0x00000040UL) +#define USBHS_DIEPINT15_TXFEMP_POS (7U) +#define USBHS_DIEPINT15_TXFEMP (0x00000080UL) +#define USBHS_DIEPINT15_TXFIFOUNDRN_POS (8U) +#define USBHS_DIEPINT15_TXFIFOUNDRN (0x00000100UL) +#define USBHS_DIEPINT15_BNAINTR_POS (9U) +#define USBHS_DIEPINT15_BNAINTR (0x00000200UL) +#define USBHS_DIEPINT15_PKTDRPSTS_POS (11U) +#define USBHS_DIEPINT15_PKTDRPSTS (0x00000800UL) +#define USBHS_DIEPINT15_BBLEERR_POS (12U) +#define USBHS_DIEPINT15_BBLEERR (0x00001000UL) +#define USBHS_DIEPINT15_NAKINTRPT_POS (13U) +#define USBHS_DIEPINT15_NAKINTRPT (0x00002000UL) +#define USBHS_DIEPINT15_NYETINTRPT_POS (14U) +#define USBHS_DIEPINT15_NYETINTRPT (0x00004000UL) + +/* Bit definition for USBHS_DIEPTSIZ15 register */ +#define USBHS_DIEPTSIZ15_XFERSIZE_POS (0U) +#define USBHS_DIEPTSIZ15_XFERSIZE (0x0007FFFFUL) +#define USBHS_DIEPTSIZ15_XFERSIZE_0 (0x00000001UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_1 (0x00000002UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_2 (0x00000004UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_3 (0x00000008UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_4 (0x00000010UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_5 (0x00000020UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_6 (0x00000040UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_7 (0x00000080UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_8 (0x00000100UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_9 (0x00000200UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_10 (0x00000400UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_11 (0x00000800UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_12 (0x00001000UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_13 (0x00002000UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_14 (0x00004000UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_15 (0x00008000UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_16 (0x00010000UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_17 (0x00020000UL) +#define USBHS_DIEPTSIZ15_XFERSIZE_18 (0x00040000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_POS (19U) +#define USBHS_DIEPTSIZ15_PKTCNT (0x1FF80000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_0 (0x00080000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_1 (0x00100000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_2 (0x00200000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_3 (0x00400000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_4 (0x00800000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_5 (0x01000000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_6 (0x02000000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_7 (0x04000000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_8 (0x08000000UL) +#define USBHS_DIEPTSIZ15_PKTCNT_9 (0x10000000UL) +#define USBHS_DIEPTSIZ15_MC_POS (29U) +#define USBHS_DIEPTSIZ15_MC (0x60000000UL) +#define USBHS_DIEPTSIZ15_MC_0 (0x20000000UL) +#define USBHS_DIEPTSIZ15_MC_1 (0x40000000UL) + +/* Bit definition for USBHS_DIEPDMA15 register */ +#define USBHS_DIEPDMA15 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DTXFSTS15 register */ +#define USBHS_DTXFSTS15_INEPTXFSPCAVAIL (0x0000FFFFUL) + +/* Bit definition for USBHS_DOEPCTL0 register */ +#define USBHS_DOEPCTL0_MPS_POS (0U) +#define USBHS_DOEPCTL0_MPS (0x00000003UL) +#define USBHS_DOEPCTL0_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL0_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL0_USBACTEP_POS (15U) +#define USBHS_DOEPCTL0_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL0_NAKSTS_POS (17U) +#define USBHS_DOEPCTL0_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL0_EPTYPE_POS (18U) +#define USBHS_DOEPCTL0_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL0_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL0_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL0_SNP_POS (20U) +#define USBHS_DOEPCTL0_SNP (0x00100000UL) +#define USBHS_DOEPCTL0_STALL_POS (21U) +#define USBHS_DOEPCTL0_STALL (0x00200000UL) +#define USBHS_DOEPCTL0_CNAK_POS (26U) +#define USBHS_DOEPCTL0_CNAK (0x04000000UL) +#define USBHS_DOEPCTL0_SNAK_POS (27U) +#define USBHS_DOEPCTL0_SNAK (0x08000000UL) +#define USBHS_DOEPCTL0_EPDIS_POS (30U) +#define USBHS_DOEPCTL0_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL0_EPENA_POS (31U) +#define USBHS_DOEPCTL0_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT0 register */ +#define USBHS_DOEPINT0_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT0_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT0_EPDISBLD_POS (1U) +#define USBHS_DOEPINT0_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT0_AHBERR_POS (2U) +#define USBHS_DOEPINT0_AHBERR (0x00000004UL) +#define USBHS_DOEPINT0_SETUP_POS (3U) +#define USBHS_DOEPINT0_SETUP (0x00000008UL) +#define USBHS_DOEPINT0_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT0_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT0_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT0_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT0_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT0_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT0_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT0_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT0_BNAINTR_POS (9U) +#define USBHS_DOEPINT0_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT0_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT0_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT0_BBLEERR_POS (12U) +#define USBHS_DOEPINT0_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT0_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT0_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT0_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT0_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT0_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT0_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ0 register */ +#define USBHS_DOEPTSIZ0_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ0_XFERSIZE (0x0000007FUL) +#define USBHS_DOEPTSIZ0_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ0_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ0_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ0_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ0_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ0_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ0_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ0_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ0_PKTCNT (0x00080000UL) +#define USBHS_DOEPTSIZ0_SUPCNT_POS (29U) +#define USBHS_DOEPTSIZ0_SUPCNT (0x60000000UL) +#define USBHS_DOEPTSIZ0_SUPCNT_0 (0x20000000UL) +#define USBHS_DOEPTSIZ0_SUPCNT_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA0 register */ +#define USBHS_DOEPDMA0 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL1 register */ +#define USBHS_DOEPCTL1_MPS_POS (0U) +#define USBHS_DOEPCTL1_MPS (0x000007FFUL) +#define USBHS_DOEPCTL1_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL1_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL1_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL1_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL1_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL1_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL1_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL1_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL1_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL1_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL1_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL1_USBACTEP_POS (15U) +#define USBHS_DOEPCTL1_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL1_DPID_POS (16U) +#define USBHS_DOEPCTL1_DPID (0x00010000UL) +#define USBHS_DOEPCTL1_NAKSTS_POS (17U) +#define USBHS_DOEPCTL1_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL1_EPTYPE_POS (18U) +#define USBHS_DOEPCTL1_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL1_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL1_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL1_SNP_POS (20U) +#define USBHS_DOEPCTL1_SNP (0x00100000UL) +#define USBHS_DOEPCTL1_STALL_POS (21U) +#define USBHS_DOEPCTL1_STALL (0x00200000UL) +#define USBHS_DOEPCTL1_CNAK_POS (26U) +#define USBHS_DOEPCTL1_CNAK (0x04000000UL) +#define USBHS_DOEPCTL1_SNAK_POS (27U) +#define USBHS_DOEPCTL1_SNAK (0x08000000UL) +#define USBHS_DOEPCTL1_SETD0PID_POS (28U) +#define USBHS_DOEPCTL1_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL1_SETD1PID_POS (29U) +#define USBHS_DOEPCTL1_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL1_EPDIS_POS (30U) +#define USBHS_DOEPCTL1_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL1_EPENA_POS (31U) +#define USBHS_DOEPCTL1_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT1 register */ +#define USBHS_DOEPINT1_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT1_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT1_EPDISBLD_POS (1U) +#define USBHS_DOEPINT1_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT1_AHBERR_POS (2U) +#define USBHS_DOEPINT1_AHBERR (0x00000004UL) +#define USBHS_DOEPINT1_SETUP_POS (3U) +#define USBHS_DOEPINT1_SETUP (0x00000008UL) +#define USBHS_DOEPINT1_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT1_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT1_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT1_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT1_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT1_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT1_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT1_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT1_BNAINTR_POS (9U) +#define USBHS_DOEPINT1_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT1_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT1_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT1_BBLEERR_POS (12U) +#define USBHS_DOEPINT1_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT1_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT1_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT1_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT1_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT1_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT1_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ1 register */ +#define USBHS_DOEPTSIZ1_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ1_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ1_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ1_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ1_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ1_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ1_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ1_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ1_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ1_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA1 register */ +#define USBHS_DOEPDMA1 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL2 register */ +#define USBHS_DOEPCTL2_MPS_POS (0U) +#define USBHS_DOEPCTL2_MPS (0x000007FFUL) +#define USBHS_DOEPCTL2_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL2_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL2_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL2_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL2_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL2_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL2_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL2_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL2_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL2_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL2_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL2_USBACTEP_POS (15U) +#define USBHS_DOEPCTL2_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL2_DPID_POS (16U) +#define USBHS_DOEPCTL2_DPID (0x00010000UL) +#define USBHS_DOEPCTL2_NAKSTS_POS (17U) +#define USBHS_DOEPCTL2_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL2_EPTYPE_POS (18U) +#define USBHS_DOEPCTL2_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL2_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL2_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL2_SNP_POS (20U) +#define USBHS_DOEPCTL2_SNP (0x00100000UL) +#define USBHS_DOEPCTL2_STALL_POS (21U) +#define USBHS_DOEPCTL2_STALL (0x00200000UL) +#define USBHS_DOEPCTL2_CNAK_POS (26U) +#define USBHS_DOEPCTL2_CNAK (0x04000000UL) +#define USBHS_DOEPCTL2_SNAK_POS (27U) +#define USBHS_DOEPCTL2_SNAK (0x08000000UL) +#define USBHS_DOEPCTL2_SETD0PID_POS (28U) +#define USBHS_DOEPCTL2_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL2_SETD1PID_POS (29U) +#define USBHS_DOEPCTL2_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL2_EPDIS_POS (30U) +#define USBHS_DOEPCTL2_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL2_EPENA_POS (31U) +#define USBHS_DOEPCTL2_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT2 register */ +#define USBHS_DOEPINT2_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT2_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT2_EPDISBLD_POS (1U) +#define USBHS_DOEPINT2_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT2_AHBERR_POS (2U) +#define USBHS_DOEPINT2_AHBERR (0x00000004UL) +#define USBHS_DOEPINT2_SETUP_POS (3U) +#define USBHS_DOEPINT2_SETUP (0x00000008UL) +#define USBHS_DOEPINT2_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT2_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT2_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT2_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT2_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT2_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT2_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT2_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT2_BNAINTR_POS (9U) +#define USBHS_DOEPINT2_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT2_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT2_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT2_BBLEERR_POS (12U) +#define USBHS_DOEPINT2_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT2_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT2_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT2_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT2_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT2_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT2_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ2 register */ +#define USBHS_DOEPTSIZ2_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ2_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ2_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ2_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ2_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ2_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ2_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ2_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ2_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ2_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA2 register */ +#define USBHS_DOEPDMA2 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL3 register */ +#define USBHS_DOEPCTL3_MPS_POS (0U) +#define USBHS_DOEPCTL3_MPS (0x000007FFUL) +#define USBHS_DOEPCTL3_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL3_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL3_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL3_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL3_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL3_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL3_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL3_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL3_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL3_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL3_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL3_USBACTEP_POS (15U) +#define USBHS_DOEPCTL3_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL3_DPID_POS (16U) +#define USBHS_DOEPCTL3_DPID (0x00010000UL) +#define USBHS_DOEPCTL3_NAKSTS_POS (17U) +#define USBHS_DOEPCTL3_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL3_EPTYPE_POS (18U) +#define USBHS_DOEPCTL3_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL3_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL3_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL3_SNP_POS (20U) +#define USBHS_DOEPCTL3_SNP (0x00100000UL) +#define USBHS_DOEPCTL3_STALL_POS (21U) +#define USBHS_DOEPCTL3_STALL (0x00200000UL) +#define USBHS_DOEPCTL3_CNAK_POS (26U) +#define USBHS_DOEPCTL3_CNAK (0x04000000UL) +#define USBHS_DOEPCTL3_SNAK_POS (27U) +#define USBHS_DOEPCTL3_SNAK (0x08000000UL) +#define USBHS_DOEPCTL3_SETD0PID_POS (28U) +#define USBHS_DOEPCTL3_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL3_SETD1PID_POS (29U) +#define USBHS_DOEPCTL3_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL3_EPDIS_POS (30U) +#define USBHS_DOEPCTL3_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL3_EPENA_POS (31U) +#define USBHS_DOEPCTL3_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT3 register */ +#define USBHS_DOEPINT3_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT3_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT3_EPDISBLD_POS (1U) +#define USBHS_DOEPINT3_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT3_AHBERR_POS (2U) +#define USBHS_DOEPINT3_AHBERR (0x00000004UL) +#define USBHS_DOEPINT3_SETUP_POS (3U) +#define USBHS_DOEPINT3_SETUP (0x00000008UL) +#define USBHS_DOEPINT3_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT3_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT3_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT3_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT3_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT3_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT3_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT3_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT3_BNAINTR_POS (9U) +#define USBHS_DOEPINT3_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT3_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT3_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT3_BBLEERR_POS (12U) +#define USBHS_DOEPINT3_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT3_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT3_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT3_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT3_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT3_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT3_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ3 register */ +#define USBHS_DOEPTSIZ3_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ3_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ3_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ3_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ3_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ3_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ3_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ3_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ3_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ3_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA3 register */ +#define USBHS_DOEPDMA3 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL4 register */ +#define USBHS_DOEPCTL4_MPS_POS (0U) +#define USBHS_DOEPCTL4_MPS (0x000007FFUL) +#define USBHS_DOEPCTL4_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL4_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL4_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL4_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL4_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL4_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL4_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL4_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL4_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL4_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL4_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL4_USBACTEP_POS (15U) +#define USBHS_DOEPCTL4_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL4_DPID_POS (16U) +#define USBHS_DOEPCTL4_DPID (0x00010000UL) +#define USBHS_DOEPCTL4_NAKSTS_POS (17U) +#define USBHS_DOEPCTL4_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL4_EPTYPE_POS (18U) +#define USBHS_DOEPCTL4_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL4_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL4_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL4_SNP_POS (20U) +#define USBHS_DOEPCTL4_SNP (0x00100000UL) +#define USBHS_DOEPCTL4_STALL_POS (21U) +#define USBHS_DOEPCTL4_STALL (0x00200000UL) +#define USBHS_DOEPCTL4_CNAK_POS (26U) +#define USBHS_DOEPCTL4_CNAK (0x04000000UL) +#define USBHS_DOEPCTL4_SNAK_POS (27U) +#define USBHS_DOEPCTL4_SNAK (0x08000000UL) +#define USBHS_DOEPCTL4_SETD0PID_POS (28U) +#define USBHS_DOEPCTL4_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL4_SETD1PID_POS (29U) +#define USBHS_DOEPCTL4_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL4_EPDIS_POS (30U) +#define USBHS_DOEPCTL4_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL4_EPENA_POS (31U) +#define USBHS_DOEPCTL4_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT4 register */ +#define USBHS_DOEPINT4_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT4_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT4_EPDISBLD_POS (1U) +#define USBHS_DOEPINT4_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT4_AHBERR_POS (2U) +#define USBHS_DOEPINT4_AHBERR (0x00000004UL) +#define USBHS_DOEPINT4_SETUP_POS (3U) +#define USBHS_DOEPINT4_SETUP (0x00000008UL) +#define USBHS_DOEPINT4_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT4_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT4_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT4_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT4_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT4_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT4_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT4_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT4_BNAINTR_POS (9U) +#define USBHS_DOEPINT4_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT4_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT4_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT4_BBLEERR_POS (12U) +#define USBHS_DOEPINT4_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT4_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT4_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT4_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT4_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT4_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT4_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ4 register */ +#define USBHS_DOEPTSIZ4_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ4_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ4_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ4_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ4_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ4_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ4_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ4_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ4_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ4_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA4 register */ +#define USBHS_DOEPDMA4 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL5 register */ +#define USBHS_DOEPCTL5_MPS_POS (0U) +#define USBHS_DOEPCTL5_MPS (0x000007FFUL) +#define USBHS_DOEPCTL5_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL5_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL5_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL5_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL5_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL5_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL5_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL5_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL5_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL5_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL5_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL5_USBACTEP_POS (15U) +#define USBHS_DOEPCTL5_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL5_DPID_POS (16U) +#define USBHS_DOEPCTL5_DPID (0x00010000UL) +#define USBHS_DOEPCTL5_NAKSTS_POS (17U) +#define USBHS_DOEPCTL5_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL5_EPTYPE_POS (18U) +#define USBHS_DOEPCTL5_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL5_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL5_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL5_SNP_POS (20U) +#define USBHS_DOEPCTL5_SNP (0x00100000UL) +#define USBHS_DOEPCTL5_STALL_POS (21U) +#define USBHS_DOEPCTL5_STALL (0x00200000UL) +#define USBHS_DOEPCTL5_CNAK_POS (26U) +#define USBHS_DOEPCTL5_CNAK (0x04000000UL) +#define USBHS_DOEPCTL5_SNAK_POS (27U) +#define USBHS_DOEPCTL5_SNAK (0x08000000UL) +#define USBHS_DOEPCTL5_SETD0PID_POS (28U) +#define USBHS_DOEPCTL5_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL5_SETD1PID_POS (29U) +#define USBHS_DOEPCTL5_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL5_EPDIS_POS (30U) +#define USBHS_DOEPCTL5_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL5_EPENA_POS (31U) +#define USBHS_DOEPCTL5_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT5 register */ +#define USBHS_DOEPINT5_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT5_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT5_EPDISBLD_POS (1U) +#define USBHS_DOEPINT5_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT5_AHBERR_POS (2U) +#define USBHS_DOEPINT5_AHBERR (0x00000004UL) +#define USBHS_DOEPINT5_SETUP_POS (3U) +#define USBHS_DOEPINT5_SETUP (0x00000008UL) +#define USBHS_DOEPINT5_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT5_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT5_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT5_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT5_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT5_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT5_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT5_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT5_BNAINTR_POS (9U) +#define USBHS_DOEPINT5_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT5_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT5_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT5_BBLEERR_POS (12U) +#define USBHS_DOEPINT5_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT5_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT5_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT5_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT5_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT5_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT5_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ5 register */ +#define USBHS_DOEPTSIZ5_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ5_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ5_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ5_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ5_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ5_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ5_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ5_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ5_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ5_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA5 register */ +#define USBHS_DOEPDMA5 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL6 register */ +#define USBHS_DOEPCTL6_MPS_POS (0U) +#define USBHS_DOEPCTL6_MPS (0x000007FFUL) +#define USBHS_DOEPCTL6_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL6_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL6_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL6_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL6_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL6_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL6_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL6_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL6_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL6_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL6_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL6_USBACTEP_POS (15U) +#define USBHS_DOEPCTL6_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL6_DPID_POS (16U) +#define USBHS_DOEPCTL6_DPID (0x00010000UL) +#define USBHS_DOEPCTL6_NAKSTS_POS (17U) +#define USBHS_DOEPCTL6_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL6_EPTYPE_POS (18U) +#define USBHS_DOEPCTL6_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL6_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL6_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL6_SNP_POS (20U) +#define USBHS_DOEPCTL6_SNP (0x00100000UL) +#define USBHS_DOEPCTL6_STALL_POS (21U) +#define USBHS_DOEPCTL6_STALL (0x00200000UL) +#define USBHS_DOEPCTL6_CNAK_POS (26U) +#define USBHS_DOEPCTL6_CNAK (0x04000000UL) +#define USBHS_DOEPCTL6_SNAK_POS (27U) +#define USBHS_DOEPCTL6_SNAK (0x08000000UL) +#define USBHS_DOEPCTL6_SETD0PID_POS (28U) +#define USBHS_DOEPCTL6_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL6_SETD1PID_POS (29U) +#define USBHS_DOEPCTL6_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL6_EPDIS_POS (30U) +#define USBHS_DOEPCTL6_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL6_EPENA_POS (31U) +#define USBHS_DOEPCTL6_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT6 register */ +#define USBHS_DOEPINT6_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT6_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT6_EPDISBLD_POS (1U) +#define USBHS_DOEPINT6_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT6_AHBERR_POS (2U) +#define USBHS_DOEPINT6_AHBERR (0x00000004UL) +#define USBHS_DOEPINT6_SETUP_POS (3U) +#define USBHS_DOEPINT6_SETUP (0x00000008UL) +#define USBHS_DOEPINT6_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT6_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT6_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT6_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT6_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT6_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT6_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT6_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT6_BNAINTR_POS (9U) +#define USBHS_DOEPINT6_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT6_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT6_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT6_BBLEERR_POS (12U) +#define USBHS_DOEPINT6_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT6_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT6_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT6_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT6_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT6_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT6_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ6 register */ +#define USBHS_DOEPTSIZ6_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ6_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ6_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ6_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ6_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ6_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ6_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ6_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ6_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ6_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA6 register */ +#define USBHS_DOEPDMA6 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL7 register */ +#define USBHS_DOEPCTL7_MPS_POS (0U) +#define USBHS_DOEPCTL7_MPS (0x000007FFUL) +#define USBHS_DOEPCTL7_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL7_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL7_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL7_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL7_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL7_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL7_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL7_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL7_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL7_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL7_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL7_USBACTEP_POS (15U) +#define USBHS_DOEPCTL7_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL7_DPID_POS (16U) +#define USBHS_DOEPCTL7_DPID (0x00010000UL) +#define USBHS_DOEPCTL7_NAKSTS_POS (17U) +#define USBHS_DOEPCTL7_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL7_EPTYPE_POS (18U) +#define USBHS_DOEPCTL7_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL7_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL7_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL7_SNP_POS (20U) +#define USBHS_DOEPCTL7_SNP (0x00100000UL) +#define USBHS_DOEPCTL7_STALL_POS (21U) +#define USBHS_DOEPCTL7_STALL (0x00200000UL) +#define USBHS_DOEPCTL7_CNAK_POS (26U) +#define USBHS_DOEPCTL7_CNAK (0x04000000UL) +#define USBHS_DOEPCTL7_SNAK_POS (27U) +#define USBHS_DOEPCTL7_SNAK (0x08000000UL) +#define USBHS_DOEPCTL7_SETD0PID_POS (28U) +#define USBHS_DOEPCTL7_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL7_SETD1PID_POS (29U) +#define USBHS_DOEPCTL7_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL7_EPDIS_POS (30U) +#define USBHS_DOEPCTL7_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL7_EPENA_POS (31U) +#define USBHS_DOEPCTL7_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT7 register */ +#define USBHS_DOEPINT7_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT7_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT7_EPDISBLD_POS (1U) +#define USBHS_DOEPINT7_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT7_AHBERR_POS (2U) +#define USBHS_DOEPINT7_AHBERR (0x00000004UL) +#define USBHS_DOEPINT7_SETUP_POS (3U) +#define USBHS_DOEPINT7_SETUP (0x00000008UL) +#define USBHS_DOEPINT7_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT7_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT7_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT7_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT7_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT7_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT7_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT7_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT7_BNAINTR_POS (9U) +#define USBHS_DOEPINT7_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT7_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT7_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT7_BBLEERR_POS (12U) +#define USBHS_DOEPINT7_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT7_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT7_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT7_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT7_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT7_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT7_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ7 register */ +#define USBHS_DOEPTSIZ7_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ7_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ7_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ7_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ7_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ7_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ7_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ7_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ7_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ7_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA7 register */ +#define USBHS_DOEPDMA7 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL8 register */ +#define USBHS_DOEPCTL8_MPS_POS (0U) +#define USBHS_DOEPCTL8_MPS (0x000007FFUL) +#define USBHS_DOEPCTL8_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL8_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL8_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL8_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL8_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL8_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL8_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL8_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL8_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL8_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL8_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL8_USBACTEP_POS (15U) +#define USBHS_DOEPCTL8_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL8_DPID_POS (16U) +#define USBHS_DOEPCTL8_DPID (0x00010000UL) +#define USBHS_DOEPCTL8_NAKSTS_POS (17U) +#define USBHS_DOEPCTL8_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL8_EPTYPE_POS (18U) +#define USBHS_DOEPCTL8_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL8_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL8_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL8_SNP_POS (20U) +#define USBHS_DOEPCTL8_SNP (0x00100000UL) +#define USBHS_DOEPCTL8_STALL_POS (21U) +#define USBHS_DOEPCTL8_STALL (0x00200000UL) +#define USBHS_DOEPCTL8_CNAK_POS (26U) +#define USBHS_DOEPCTL8_CNAK (0x04000000UL) +#define USBHS_DOEPCTL8_SNAK_POS (27U) +#define USBHS_DOEPCTL8_SNAK (0x08000000UL) +#define USBHS_DOEPCTL8_SETD0PID_POS (28U) +#define USBHS_DOEPCTL8_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL8_SETD1PID_POS (29U) +#define USBHS_DOEPCTL8_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL8_EPDIS_POS (30U) +#define USBHS_DOEPCTL8_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL8_EPENA_POS (31U) +#define USBHS_DOEPCTL8_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT8 register */ +#define USBHS_DOEPINT8_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT8_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT8_EPDISBLD_POS (1U) +#define USBHS_DOEPINT8_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT8_AHBERR_POS (2U) +#define USBHS_DOEPINT8_AHBERR (0x00000004UL) +#define USBHS_DOEPINT8_SETUP_POS (3U) +#define USBHS_DOEPINT8_SETUP (0x00000008UL) +#define USBHS_DOEPINT8_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT8_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT8_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT8_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT8_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT8_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT8_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT8_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT8_BNAINTR_POS (9U) +#define USBHS_DOEPINT8_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT8_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT8_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT8_BBLEERR_POS (12U) +#define USBHS_DOEPINT8_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT8_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT8_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT8_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT8_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT8_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT8_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ8 register */ +#define USBHS_DOEPTSIZ8_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ8_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ8_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ8_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ8_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ8_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ8_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ8_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ8_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ8_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA8 register */ +#define USBHS_DOEPDMA8 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL9 register */ +#define USBHS_DOEPCTL9_MPS_POS (0U) +#define USBHS_DOEPCTL9_MPS (0x000007FFUL) +#define USBHS_DOEPCTL9_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL9_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL9_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL9_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL9_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL9_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL9_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL9_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL9_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL9_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL9_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL9_USBACTEP_POS (15U) +#define USBHS_DOEPCTL9_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL9_DPID_POS (16U) +#define USBHS_DOEPCTL9_DPID (0x00010000UL) +#define USBHS_DOEPCTL9_NAKSTS_POS (17U) +#define USBHS_DOEPCTL9_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL9_EPTYPE_POS (18U) +#define USBHS_DOEPCTL9_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL9_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL9_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL9_SNP_POS (20U) +#define USBHS_DOEPCTL9_SNP (0x00100000UL) +#define USBHS_DOEPCTL9_STALL_POS (21U) +#define USBHS_DOEPCTL9_STALL (0x00200000UL) +#define USBHS_DOEPCTL9_CNAK_POS (26U) +#define USBHS_DOEPCTL9_CNAK (0x04000000UL) +#define USBHS_DOEPCTL9_SNAK_POS (27U) +#define USBHS_DOEPCTL9_SNAK (0x08000000UL) +#define USBHS_DOEPCTL9_SETD0PID_POS (28U) +#define USBHS_DOEPCTL9_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL9_SETD1PID_POS (29U) +#define USBHS_DOEPCTL9_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL9_EPDIS_POS (30U) +#define USBHS_DOEPCTL9_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL9_EPENA_POS (31U) +#define USBHS_DOEPCTL9_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT9 register */ +#define USBHS_DOEPINT9_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT9_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT9_EPDISBLD_POS (1U) +#define USBHS_DOEPINT9_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT9_AHBERR_POS (2U) +#define USBHS_DOEPINT9_AHBERR (0x00000004UL) +#define USBHS_DOEPINT9_SETUP_POS (3U) +#define USBHS_DOEPINT9_SETUP (0x00000008UL) +#define USBHS_DOEPINT9_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT9_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT9_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT9_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT9_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT9_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT9_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT9_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT9_BNAINTR_POS (9U) +#define USBHS_DOEPINT9_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT9_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT9_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT9_BBLEERR_POS (12U) +#define USBHS_DOEPINT9_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT9_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT9_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT9_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT9_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT9_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT9_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ9 register */ +#define USBHS_DOEPTSIZ9_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ9_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ9_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ9_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ9_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ9_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ9_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ9_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ9_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ9_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA9 register */ +#define USBHS_DOEPDMA9 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL10 register */ +#define USBHS_DOEPCTL10_MPS_POS (0U) +#define USBHS_DOEPCTL10_MPS (0x000007FFUL) +#define USBHS_DOEPCTL10_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL10_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL10_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL10_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL10_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL10_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL10_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL10_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL10_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL10_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL10_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL10_USBACTEP_POS (15U) +#define USBHS_DOEPCTL10_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL10_DPID_POS (16U) +#define USBHS_DOEPCTL10_DPID (0x00010000UL) +#define USBHS_DOEPCTL10_NAKSTS_POS (17U) +#define USBHS_DOEPCTL10_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL10_EPTYPE_POS (18U) +#define USBHS_DOEPCTL10_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL10_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL10_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL10_SNP_POS (20U) +#define USBHS_DOEPCTL10_SNP (0x00100000UL) +#define USBHS_DOEPCTL10_STALL_POS (21U) +#define USBHS_DOEPCTL10_STALL (0x00200000UL) +#define USBHS_DOEPCTL10_CNAK_POS (26U) +#define USBHS_DOEPCTL10_CNAK (0x04000000UL) +#define USBHS_DOEPCTL10_SNAK_POS (27U) +#define USBHS_DOEPCTL10_SNAK (0x08000000UL) +#define USBHS_DOEPCTL10_SETD0PID_POS (28U) +#define USBHS_DOEPCTL10_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL10_SETD1PID_POS (29U) +#define USBHS_DOEPCTL10_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL10_EPDIS_POS (30U) +#define USBHS_DOEPCTL10_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL10_EPENA_POS (31U) +#define USBHS_DOEPCTL10_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT10 register */ +#define USBHS_DOEPINT10_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT10_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT10_EPDISBLD_POS (1U) +#define USBHS_DOEPINT10_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT10_AHBERR_POS (2U) +#define USBHS_DOEPINT10_AHBERR (0x00000004UL) +#define USBHS_DOEPINT10_SETUP_POS (3U) +#define USBHS_DOEPINT10_SETUP (0x00000008UL) +#define USBHS_DOEPINT10_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT10_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT10_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT10_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT10_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT10_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT10_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT10_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT10_BNAINTR_POS (9U) +#define USBHS_DOEPINT10_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT10_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT10_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT10_BBLEERR_POS (12U) +#define USBHS_DOEPINT10_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT10_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT10_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT10_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT10_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT10_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT10_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ10 register */ +#define USBHS_DOEPTSIZ10_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ10_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ10_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ10_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ10_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ10_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ10_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ10_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ10_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ10_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA10 register */ +#define USBHS_DOEPDMA10 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL11 register */ +#define USBHS_DOEPCTL11_MPS_POS (0U) +#define USBHS_DOEPCTL11_MPS (0x000007FFUL) +#define USBHS_DOEPCTL11_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL11_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL11_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL11_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL11_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL11_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL11_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL11_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL11_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL11_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL11_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL11_USBACTEP_POS (15U) +#define USBHS_DOEPCTL11_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL11_DPID_POS (16U) +#define USBHS_DOEPCTL11_DPID (0x00010000UL) +#define USBHS_DOEPCTL11_NAKSTS_POS (17U) +#define USBHS_DOEPCTL11_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL11_EPTYPE_POS (18U) +#define USBHS_DOEPCTL11_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL11_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL11_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL11_SNP_POS (20U) +#define USBHS_DOEPCTL11_SNP (0x00100000UL) +#define USBHS_DOEPCTL11_STALL_POS (21U) +#define USBHS_DOEPCTL11_STALL (0x00200000UL) +#define USBHS_DOEPCTL11_CNAK_POS (26U) +#define USBHS_DOEPCTL11_CNAK (0x04000000UL) +#define USBHS_DOEPCTL11_SNAK_POS (27U) +#define USBHS_DOEPCTL11_SNAK (0x08000000UL) +#define USBHS_DOEPCTL11_SETD0PID_POS (28U) +#define USBHS_DOEPCTL11_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL11_SETD1PID_POS (29U) +#define USBHS_DOEPCTL11_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL11_EPDIS_POS (30U) +#define USBHS_DOEPCTL11_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL11_EPENA_POS (31U) +#define USBHS_DOEPCTL11_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT11 register */ +#define USBHS_DOEPINT11_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT11_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT11_EPDISBLD_POS (1U) +#define USBHS_DOEPINT11_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT11_AHBERR_POS (2U) +#define USBHS_DOEPINT11_AHBERR (0x00000004UL) +#define USBHS_DOEPINT11_SETUP_POS (3U) +#define USBHS_DOEPINT11_SETUP (0x00000008UL) +#define USBHS_DOEPINT11_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT11_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT11_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT11_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT11_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT11_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT11_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT11_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT11_BNAINTR_POS (9U) +#define USBHS_DOEPINT11_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT11_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT11_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT11_BBLEERR_POS (12U) +#define USBHS_DOEPINT11_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT11_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT11_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT11_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT11_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT11_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT11_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ11 register */ +#define USBHS_DOEPTSIZ11_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ11_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ11_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ11_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ11_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ11_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ11_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ11_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ11_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ11_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA11 register */ +#define USBHS_DOEPDMA11 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL12 register */ +#define USBHS_DOEPCTL12_MPS_POS (0U) +#define USBHS_DOEPCTL12_MPS (0x000007FFUL) +#define USBHS_DOEPCTL12_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL12_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL12_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL12_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL12_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL12_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL12_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL12_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL12_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL12_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL12_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL12_USBACTEP_POS (15U) +#define USBHS_DOEPCTL12_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL12_DPID_POS (16U) +#define USBHS_DOEPCTL12_DPID (0x00010000UL) +#define USBHS_DOEPCTL12_NAKSTS_POS (17U) +#define USBHS_DOEPCTL12_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL12_EPTYPE_POS (18U) +#define USBHS_DOEPCTL12_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL12_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL12_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL12_SNP_POS (20U) +#define USBHS_DOEPCTL12_SNP (0x00100000UL) +#define USBHS_DOEPCTL12_STALL_POS (21U) +#define USBHS_DOEPCTL12_STALL (0x00200000UL) +#define USBHS_DOEPCTL12_CNAK_POS (26U) +#define USBHS_DOEPCTL12_CNAK (0x04000000UL) +#define USBHS_DOEPCTL12_SNAK_POS (27U) +#define USBHS_DOEPCTL12_SNAK (0x08000000UL) +#define USBHS_DOEPCTL12_SETD0PID_POS (28U) +#define USBHS_DOEPCTL12_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL12_SETD1PID_POS (29U) +#define USBHS_DOEPCTL12_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL12_EPDIS_POS (30U) +#define USBHS_DOEPCTL12_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL12_EPENA_POS (31U) +#define USBHS_DOEPCTL12_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT12 register */ +#define USBHS_DOEPINT12_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT12_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT12_EPDISBLD_POS (1U) +#define USBHS_DOEPINT12_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT12_AHBERR_POS (2U) +#define USBHS_DOEPINT12_AHBERR (0x00000004UL) +#define USBHS_DOEPINT12_SETUP_POS (3U) +#define USBHS_DOEPINT12_SETUP (0x00000008UL) +#define USBHS_DOEPINT12_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT12_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT12_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT12_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT12_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT12_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT12_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT12_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT12_BNAINTR_POS (9U) +#define USBHS_DOEPINT12_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT12_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT12_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT12_BBLEERR_POS (12U) +#define USBHS_DOEPINT12_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT12_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT12_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT12_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT12_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT12_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT12_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ12 register */ +#define USBHS_DOEPTSIZ12_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ12_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ12_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ12_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ12_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ12_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ12_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ12_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ12_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ12_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA12 register */ +#define USBHS_DOEPDMA12 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL13 register */ +#define USBHS_DOEPCTL13_MPS_POS (0U) +#define USBHS_DOEPCTL13_MPS (0x000007FFUL) +#define USBHS_DOEPCTL13_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL13_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL13_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL13_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL13_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL13_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL13_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL13_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL13_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL13_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL13_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL13_USBACTEP_POS (15U) +#define USBHS_DOEPCTL13_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL13_DPID_POS (16U) +#define USBHS_DOEPCTL13_DPID (0x00010000UL) +#define USBHS_DOEPCTL13_NAKSTS_POS (17U) +#define USBHS_DOEPCTL13_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL13_EPTYPE_POS (18U) +#define USBHS_DOEPCTL13_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL13_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL13_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL13_SNP_POS (20U) +#define USBHS_DOEPCTL13_SNP (0x00100000UL) +#define USBHS_DOEPCTL13_STALL_POS (21U) +#define USBHS_DOEPCTL13_STALL (0x00200000UL) +#define USBHS_DOEPCTL13_CNAK_POS (26U) +#define USBHS_DOEPCTL13_CNAK (0x04000000UL) +#define USBHS_DOEPCTL13_SNAK_POS (27U) +#define USBHS_DOEPCTL13_SNAK (0x08000000UL) +#define USBHS_DOEPCTL13_SETD0PID_POS (28U) +#define USBHS_DOEPCTL13_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL13_SETD1PID_POS (29U) +#define USBHS_DOEPCTL13_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL13_EPDIS_POS (30U) +#define USBHS_DOEPCTL13_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL13_EPENA_POS (31U) +#define USBHS_DOEPCTL13_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT13 register */ +#define USBHS_DOEPINT13_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT13_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT13_EPDISBLD_POS (1U) +#define USBHS_DOEPINT13_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT13_AHBERR_POS (2U) +#define USBHS_DOEPINT13_AHBERR (0x00000004UL) +#define USBHS_DOEPINT13_SETUP_POS (3U) +#define USBHS_DOEPINT13_SETUP (0x00000008UL) +#define USBHS_DOEPINT13_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT13_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT13_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT13_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT13_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT13_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT13_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT13_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT13_BNAINTR_POS (9U) +#define USBHS_DOEPINT13_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT13_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT13_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT13_BBLEERR_POS (12U) +#define USBHS_DOEPINT13_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT13_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT13_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT13_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT13_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT13_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT13_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ13 register */ +#define USBHS_DOEPTSIZ13_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ13_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ13_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ13_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ13_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ13_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ13_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ13_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ13_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ13_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA13 register */ +#define USBHS_DOEPDMA13 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL14 register */ +#define USBHS_DOEPCTL14_MPS_POS (0U) +#define USBHS_DOEPCTL14_MPS (0x000007FFUL) +#define USBHS_DOEPCTL14_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL14_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL14_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL14_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL14_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL14_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL14_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL14_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL14_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL14_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL14_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL14_USBACTEP_POS (15U) +#define USBHS_DOEPCTL14_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL14_DPID_POS (16U) +#define USBHS_DOEPCTL14_DPID (0x00010000UL) +#define USBHS_DOEPCTL14_NAKSTS_POS (17U) +#define USBHS_DOEPCTL14_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL14_EPTYPE_POS (18U) +#define USBHS_DOEPCTL14_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL14_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL14_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL14_SNP_POS (20U) +#define USBHS_DOEPCTL14_SNP (0x00100000UL) +#define USBHS_DOEPCTL14_STALL_POS (21U) +#define USBHS_DOEPCTL14_STALL (0x00200000UL) +#define USBHS_DOEPCTL14_CNAK_POS (26U) +#define USBHS_DOEPCTL14_CNAK (0x04000000UL) +#define USBHS_DOEPCTL14_SNAK_POS (27U) +#define USBHS_DOEPCTL14_SNAK (0x08000000UL) +#define USBHS_DOEPCTL14_SETD0PID_POS (28U) +#define USBHS_DOEPCTL14_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL14_SETD1PID_POS (29U) +#define USBHS_DOEPCTL14_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL14_EPDIS_POS (30U) +#define USBHS_DOEPCTL14_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL14_EPENA_POS (31U) +#define USBHS_DOEPCTL14_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT14 register */ +#define USBHS_DOEPINT14_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT14_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT14_EPDISBLD_POS (1U) +#define USBHS_DOEPINT14_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT14_AHBERR_POS (2U) +#define USBHS_DOEPINT14_AHBERR (0x00000004UL) +#define USBHS_DOEPINT14_SETUP_POS (3U) +#define USBHS_DOEPINT14_SETUP (0x00000008UL) +#define USBHS_DOEPINT14_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT14_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT14_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT14_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT14_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT14_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT14_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT14_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT14_BNAINTR_POS (9U) +#define USBHS_DOEPINT14_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT14_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT14_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT14_BBLEERR_POS (12U) +#define USBHS_DOEPINT14_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT14_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT14_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT14_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT14_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT14_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT14_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ14 register */ +#define USBHS_DOEPTSIZ14_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ14_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ14_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ14_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ14_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ14_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ14_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ14_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ14_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ14_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA14 register */ +#define USBHS_DOEPDMA14 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_DOEPCTL15 register */ +#define USBHS_DOEPCTL15_MPS_POS (0U) +#define USBHS_DOEPCTL15_MPS (0x000007FFUL) +#define USBHS_DOEPCTL15_MPS_0 (0x00000001UL) +#define USBHS_DOEPCTL15_MPS_1 (0x00000002UL) +#define USBHS_DOEPCTL15_MPS_2 (0x00000004UL) +#define USBHS_DOEPCTL15_MPS_3 (0x00000008UL) +#define USBHS_DOEPCTL15_MPS_4 (0x00000010UL) +#define USBHS_DOEPCTL15_MPS_5 (0x00000020UL) +#define USBHS_DOEPCTL15_MPS_6 (0x00000040UL) +#define USBHS_DOEPCTL15_MPS_7 (0x00000080UL) +#define USBHS_DOEPCTL15_MPS_8 (0x00000100UL) +#define USBHS_DOEPCTL15_MPS_9 (0x00000200UL) +#define USBHS_DOEPCTL15_MPS_10 (0x00000400UL) +#define USBHS_DOEPCTL15_USBACTEP_POS (15U) +#define USBHS_DOEPCTL15_USBACTEP (0x00008000UL) +#define USBHS_DOEPCTL15_DPID_POS (16U) +#define USBHS_DOEPCTL15_DPID (0x00010000UL) +#define USBHS_DOEPCTL15_NAKSTS_POS (17U) +#define USBHS_DOEPCTL15_NAKSTS (0x00020000UL) +#define USBHS_DOEPCTL15_EPTYPE_POS (18U) +#define USBHS_DOEPCTL15_EPTYPE (0x000C0000UL) +#define USBHS_DOEPCTL15_EPTYPE_0 (0x00040000UL) +#define USBHS_DOEPCTL15_EPTYPE_1 (0x00080000UL) +#define USBHS_DOEPCTL15_SNP_POS (20U) +#define USBHS_DOEPCTL15_SNP (0x00100000UL) +#define USBHS_DOEPCTL15_STALL_POS (21U) +#define USBHS_DOEPCTL15_STALL (0x00200000UL) +#define USBHS_DOEPCTL15_CNAK_POS (26U) +#define USBHS_DOEPCTL15_CNAK (0x04000000UL) +#define USBHS_DOEPCTL15_SNAK_POS (27U) +#define USBHS_DOEPCTL15_SNAK (0x08000000UL) +#define USBHS_DOEPCTL15_SETD0PID_POS (28U) +#define USBHS_DOEPCTL15_SETD0PID (0x10000000UL) +#define USBHS_DOEPCTL15_SETD1PID_POS (29U) +#define USBHS_DOEPCTL15_SETD1PID (0x20000000UL) +#define USBHS_DOEPCTL15_EPDIS_POS (30U) +#define USBHS_DOEPCTL15_EPDIS (0x40000000UL) +#define USBHS_DOEPCTL15_EPENA_POS (31U) +#define USBHS_DOEPCTL15_EPENA (0x80000000UL) + +/* Bit definition for USBHS_DOEPINT15 register */ +#define USBHS_DOEPINT15_XFERCOMPL_POS (0U) +#define USBHS_DOEPINT15_XFERCOMPL (0x00000001UL) +#define USBHS_DOEPINT15_EPDISBLD_POS (1U) +#define USBHS_DOEPINT15_EPDISBLD (0x00000002UL) +#define USBHS_DOEPINT15_AHBERR_POS (2U) +#define USBHS_DOEPINT15_AHBERR (0x00000004UL) +#define USBHS_DOEPINT15_SETUP_POS (3U) +#define USBHS_DOEPINT15_SETUP (0x00000008UL) +#define USBHS_DOEPINT15_OUTTKNEPDIS_POS (4U) +#define USBHS_DOEPINT15_OUTTKNEPDIS (0x00000010UL) +#define USBHS_DOEPINT15_STSPHSERCVD_POS (5U) +#define USBHS_DOEPINT15_STSPHSERCVD (0x00000020UL) +#define USBHS_DOEPINT15_BACK2BACKSETUP_POS (6U) +#define USBHS_DOEPINT15_BACK2BACKSETUP (0x00000040UL) +#define USBHS_DOEPINT15_OUTPKTERR_POS (8U) +#define USBHS_DOEPINT15_OUTPKTERR (0x00000100UL) +#define USBHS_DOEPINT15_BNAINTR_POS (9U) +#define USBHS_DOEPINT15_BNAINTR (0x00000200UL) +#define USBHS_DOEPINT15_PKTDRPSTS_POS (11U) +#define USBHS_DOEPINT15_PKTDRPSTS (0x00000800UL) +#define USBHS_DOEPINT15_BBLEERR_POS (12U) +#define USBHS_DOEPINT15_BBLEERR (0x00001000UL) +#define USBHS_DOEPINT15_NAKINTRPT_POS (13U) +#define USBHS_DOEPINT15_NAKINTRPT (0x00002000UL) +#define USBHS_DOEPINT15_NYETINTRPT_POS (14U) +#define USBHS_DOEPINT15_NYETINTRPT (0x00004000UL) +#define USBHS_DOEPINT15_STUPPKTRCVD_POS (15U) +#define USBHS_DOEPINT15_STUPPKTRCVD (0x00008000UL) + +/* Bit definition for USBHS_DOEPTSIZ15 register */ +#define USBHS_DOEPTSIZ15_XFERSIZE_POS (0U) +#define USBHS_DOEPTSIZ15_XFERSIZE (0x0007FFFFUL) +#define USBHS_DOEPTSIZ15_XFERSIZE_0 (0x00000001UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_1 (0x00000002UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_2 (0x00000004UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_3 (0x00000008UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_4 (0x00000010UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_5 (0x00000020UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_6 (0x00000040UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_7 (0x00000080UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_8 (0x00000100UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_9 (0x00000200UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_10 (0x00000400UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_11 (0x00000800UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_12 (0x00001000UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_13 (0x00002000UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_14 (0x00004000UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_15 (0x00008000UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_16 (0x00010000UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_17 (0x00020000UL) +#define USBHS_DOEPTSIZ15_XFERSIZE_18 (0x00040000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_POS (19U) +#define USBHS_DOEPTSIZ15_PKTCNT (0x1FF80000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_0 (0x00080000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_1 (0x00100000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_2 (0x00200000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_3 (0x00400000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_4 (0x00800000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_5 (0x01000000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_6 (0x02000000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_7 (0x04000000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_8 (0x08000000UL) +#define USBHS_DOEPTSIZ15_PKTCNT_9 (0x10000000UL) +#define USBHS_DOEPTSIZ15_RXDPID_POS (29U) +#define USBHS_DOEPTSIZ15_RXDPID (0x60000000UL) +#define USBHS_DOEPTSIZ15_RXDPID_0 (0x20000000UL) +#define USBHS_DOEPTSIZ15_RXDPID_1 (0x40000000UL) + +/* Bit definition for USBHS_DOEPDMA15 register */ +#define USBHS_DOEPDMA15 (0xFFFFFFFFUL) + +/* Bit definition for USBHS_PCGCCTL register */ +#define USBHS_PCGCCTL_STOPPCLK_POS (0U) +#define USBHS_PCGCCTL_STOPPCLK (0x00000001UL) +#define USBHS_PCGCCTL_GATEHCLK_POS (1U) +#define USBHS_PCGCCTL_GATEHCLK (0x00000002UL) +#define USBHS_PCGCCTL_PWRCLMP_POS (2U) +#define USBHS_PCGCCTL_PWRCLMP (0x00000004UL) +#define USBHS_PCGCCTL_RSTPDWNMODULE_POS (3U) +#define USBHS_PCGCCTL_RSTPDWNMODULE (0x00000008UL) +#define USBHS_PCGCCTL_ENBL_L1GATING_POS (5U) +#define USBHS_PCGCCTL_ENBL_L1GATING (0x00000020UL) +#define USBHS_PCGCCTL_PHYSLEEP_POS (6U) +#define USBHS_PCGCCTL_PHYSLEEP (0x00000040UL) +#define USBHS_PCGCCTL_L1SUSPENDED_POS (7U) +#define USBHS_PCGCCTL_L1SUSPENDED (0x00000080UL) +#define USBHS_PCGCCTL_RESETAFTERSUSP_POS (8U) +#define USBHS_PCGCCTL_RESETAFTERSUSP (0x00000100UL) + +/******************************************************************************* + Bit definition for Peripheral WDT +*******************************************************************************/ +/* Bit definition for WDT_CR register */ +#define WDT_CR_PERI_POS (0U) +#define WDT_CR_PERI (0x00000003UL) +#define WDT_CR_PERI_0 (0x00000001UL) +#define WDT_CR_PERI_1 (0x00000002UL) +#define WDT_CR_CKS_POS (4U) +#define WDT_CR_CKS (0x000000F0UL) +#define WDT_CR_CKS_0 (0x00000010UL) +#define WDT_CR_CKS_1 (0x00000020UL) +#define WDT_CR_CKS_2 (0x00000040UL) +#define WDT_CR_CKS_3 (0x00000080UL) +#define WDT_CR_WDPT_POS (8U) +#define WDT_CR_WDPT (0x00000F00UL) +#define WDT_CR_WDPT_0 (0x00000100UL) +#define WDT_CR_WDPT_1 (0x00000200UL) +#define WDT_CR_WDPT_2 (0x00000400UL) +#define WDT_CR_WDPT_3 (0x00000800UL) +#define WDT_CR_SLPOFF_POS (16U) +#define WDT_CR_SLPOFF (0x00010000UL) +#define WDT_CR_ITS_POS (31U) +#define WDT_CR_ITS (0x80000000UL) + +/* Bit definition for WDT_SR register */ +#define WDT_SR_CNT_POS (0U) +#define WDT_SR_CNT (0x0000FFFFUL) +#define WDT_SR_UDF_POS (16U) +#define WDT_SR_UDF (0x00010000UL) +#define WDT_SR_REF_POS (17U) +#define WDT_SR_REF (0x00020000UL) + +/* Bit definition for WDT_RR register */ +#define WDT_RR_RF (0x0000FFFFUL) + + +/******************************************************************************/ +/* Device Specific Registers bit_band structure */ +/******************************************************************************/ + +typedef struct +{ + __IO uint32_t STRT; + uint32_t RESERVED0[7]; +} stc_adc_str_bit_t; + +typedef struct +{ + __IO uint32_t MS0; + __IO uint32_t MS1; + uint32_t RESERVED0[2]; + __IO uint32_t ACCSEL0; + __IO uint32_t ACCSEL1; + __IO uint32_t CLREN; + __IO uint32_t DFMT; + __IO uint32_t AVCNT0; + __IO uint32_t AVCNT1; + __IO uint32_t AVCNT2; + uint32_t RESERVED1[5]; +} stc_adc_cr0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t RSCHSEL; + uint32_t RESERVED1[13]; +} stc_adc_cr1_bit_t; + +typedef struct +{ + __IO uint32_t TRGSELA0; + __IO uint32_t TRGSELA1; + uint32_t RESERVED0[5]; + __IO uint32_t TRGENA; + __IO uint32_t TRGSELB0; + __IO uint32_t TRGSELB1; + uint32_t RESERVED1[5]; + __IO uint32_t TRGENB; +} stc_adc_trgsr_bit_t; + +typedef struct +{ + __IO uint32_t CHSELA0; + __IO uint32_t CHSELA1; + __IO uint32_t CHSELA2; + __IO uint32_t CHSELA3; + __IO uint32_t CHSELA4; + __IO uint32_t CHSELA5; + __IO uint32_t CHSELA6; + __IO uint32_t CHSELA7; + __IO uint32_t CHSELA8; + __IO uint32_t CHSELA9; + __IO uint32_t CHSELA10; + __IO uint32_t CHSELA11; + __IO uint32_t CHSELA12; + __IO uint32_t CHSELA13; + __IO uint32_t CHSELA14; + __IO uint32_t CHSELA15; + __IO uint32_t CHSELA16; + __IO uint32_t CHSELA17; + __IO uint32_t CHSELA18; + __IO uint32_t CHSELA19; + uint32_t RESERVED0[12]; +} stc_adc_chselra_bit_t; + +typedef struct +{ + __IO uint32_t CHSELB0; + __IO uint32_t CHSELB1; + __IO uint32_t CHSELB2; + __IO uint32_t CHSELB3; + __IO uint32_t CHSELB4; + __IO uint32_t CHSELB5; + __IO uint32_t CHSELB6; + __IO uint32_t CHSELB7; + __IO uint32_t CHSELB8; + __IO uint32_t CHSELB9; + __IO uint32_t CHSELB10; + __IO uint32_t CHSELB11; + __IO uint32_t CHSELB12; + __IO uint32_t CHSELB13; + __IO uint32_t CHSELB14; + __IO uint32_t CHSELB15; + __IO uint32_t CHSELB16; + __IO uint32_t CHSELB17; + __IO uint32_t CHSELB18; + __IO uint32_t CHSELB19; + uint32_t RESERVED0[12]; +} stc_adc_chselrb_bit_t; + +typedef struct +{ + __IO uint32_t AVCHSEL0; + __IO uint32_t AVCHSEL1; + __IO uint32_t AVCHSEL2; + __IO uint32_t AVCHSEL3; + __IO uint32_t AVCHSEL4; + __IO uint32_t AVCHSEL5; + __IO uint32_t AVCHSEL6; + __IO uint32_t AVCHSEL7; + __IO uint32_t AVCHSEL8; + __IO uint32_t AVCHSEL9; + __IO uint32_t AVCHSEL10; + __IO uint32_t AVCHSEL11; + __IO uint32_t AVCHSEL12; + __IO uint32_t AVCHSEL13; + __IO uint32_t AVCHSEL14; + __IO uint32_t AVCHSEL15; + __IO uint32_t AVCHSEL16; + __IO uint32_t AVCHSEL17; + __IO uint32_t AVCHSEL18; + __IO uint32_t AVCHSEL19; + uint32_t RESERVED0[12]; +} stc_adc_avchselr_bit_t; + +typedef struct +{ + __IO uint32_t EXCHSEL; + uint32_t RESERVED0[7]; +} stc_adc_exchselr_bit_t; + +typedef struct +{ + __IO uint32_t SHSST0; + __IO uint32_t SHSST1; + __IO uint32_t SHSST2; + __IO uint32_t SHSST3; + __IO uint32_t SHSST4; + __IO uint32_t SHSST5; + __IO uint32_t SHSST6; + __IO uint32_t SHSST7; + __IO uint32_t SHSEL0; + __IO uint32_t SHSEL1; + __IO uint32_t SHSEL2; + uint32_t RESERVED0[5]; +} stc_adc_shcr_bit_t; + +typedef struct +{ + __IO uint32_t CH00MUX0; + __IO uint32_t CH00MUX1; + __IO uint32_t CH00MUX2; + __IO uint32_t CH00MUX3; + __IO uint32_t CH01MUX0; + __IO uint32_t CH01MUX1; + __IO uint32_t CH01MUX2; + __IO uint32_t CH01MUX3; + __IO uint32_t CH02MUX0; + __IO uint32_t CH02MUX1; + __IO uint32_t CH02MUX2; + __IO uint32_t CH02MUX3; + __IO uint32_t CH03MUX0; + __IO uint32_t CH03MUX1; + __IO uint32_t CH03MUX2; + __IO uint32_t CH03MUX3; +} stc_adc_chmuxr0_bit_t; + +typedef struct +{ + __IO uint32_t CH04MUX0; + __IO uint32_t CH04MUX1; + __IO uint32_t CH04MUX2; + __IO uint32_t CH04MUX3; + __IO uint32_t CH05MUX0; + __IO uint32_t CH05MUX1; + __IO uint32_t CH05MUX2; + __IO uint32_t CH05MUX3; + __IO uint32_t CH06MUX0; + __IO uint32_t CH06MUX1; + __IO uint32_t CH06MUX2; + __IO uint32_t CH06MUX3; + __IO uint32_t CH07MUX0; + __IO uint32_t CH07MUX1; + __IO uint32_t CH07MUX2; + __IO uint32_t CH07MUX3; +} stc_adc_chmuxr1_bit_t; + +typedef struct +{ + __IO uint32_t CH08MUX0; + __IO uint32_t CH08MUX1; + __IO uint32_t CH08MUX2; + __IO uint32_t CH08MUX3; + __IO uint32_t CH09MUX0; + __IO uint32_t CH09MUX1; + __IO uint32_t CH09MUX2; + __IO uint32_t CH09MUX3; + __IO uint32_t CH10MUX0; + __IO uint32_t CH10MUX1; + __IO uint32_t CH10MUX2; + __IO uint32_t CH10MUX3; + __IO uint32_t CH11MUX0; + __IO uint32_t CH11MUX1; + __IO uint32_t CH11MUX2; + __IO uint32_t CH11MUX3; +} stc_adc_chmuxr2_bit_t; + +typedef struct +{ + __IO uint32_t CH12MUX0; + __IO uint32_t CH12MUX1; + __IO uint32_t CH12MUX2; + __IO uint32_t CH12MUX3; + __IO uint32_t CH13MUX0; + __IO uint32_t CH13MUX1; + __IO uint32_t CH13MUX2; + __IO uint32_t CH13MUX3; + __IO uint32_t CH14MUX0; + __IO uint32_t CH14MUX1; + __IO uint32_t CH14MUX2; + __IO uint32_t CH14MUX3; + __IO uint32_t CH15MUX0; + __IO uint32_t CH15MUX1; + __IO uint32_t CH15MUX2; + __IO uint32_t CH15MUX3; +} stc_adc_chmuxr3_bit_t; + +typedef struct +{ + __IO uint32_t EOCAF; + __IO uint32_t EOCBF; + uint32_t RESERVED0[2]; + __IO uint32_t SASTPDF; + uint32_t RESERVED1[3]; +} stc_adc_isr_bit_t; + +typedef struct +{ + __IO uint32_t EOCAIEN; + __IO uint32_t EOCBIEN; + uint32_t RESERVED0[6]; +} stc_adc_icr_bit_t; + +typedef struct +{ + __IO uint32_t CLREOCAF; + __IO uint32_t CLREOCBF; + uint32_t RESERVED0[2]; + __IO uint32_t CLRSASTPDF; + uint32_t RESERVED1[3]; +} stc_adc_isclrr_bit_t; + +typedef struct +{ + __IO uint32_t SYNCEN; + uint32_t RESERVED0[3]; + __IO uint32_t SYNCMD0; + __IO uint32_t SYNCMD1; + __IO uint32_t SYNCMD2; + uint32_t RESERVED1[1]; + __IO uint32_t SYNCDLY0; + __IO uint32_t SYNCDLY1; + __IO uint32_t SYNCDLY2; + __IO uint32_t SYNCDLY3; + __IO uint32_t SYNCDLY4; + __IO uint32_t SYNCDLY5; + __IO uint32_t SYNCDLY6; + __IO uint32_t SYNCDLY7; +} stc_adc_synccr_bit_t; + +typedef struct +{ + __IO uint32_t AWD0EN; + __IO uint32_t AWD0IEN; + __IO uint32_t AWD0MD; + uint32_t RESERVED0[1]; + __IO uint32_t AWD1EN; + __IO uint32_t AWD1IEN; + __IO uint32_t AWD1MD; + uint32_t RESERVED1[1]; + __IO uint32_t AWDCM0; + __IO uint32_t AWDCM1; + uint32_t RESERVED2[6]; +} stc_adc_awdcr_bit_t; + +typedef struct +{ + __IO uint32_t AWD0F; + __IO uint32_t AWD1F; + uint32_t RESERVED0[2]; + __IO uint32_t AWDCMF; + uint32_t RESERVED1[3]; +} stc_adc_awdsr_bit_t; + +typedef struct +{ + __IO uint32_t CLRAWD0F; + __IO uint32_t CLRAWD1F; + uint32_t RESERVED0[2]; + __IO uint32_t CLRAWDCMF; + uint32_t RESERVED1[3]; +} stc_adc_awdsclrr_bit_t; + +typedef struct +{ + __IO uint32_t AWDCH0; + __IO uint32_t AWDCH1; + __IO uint32_t AWDCH2; + __IO uint32_t AWDCH3; + __IO uint32_t AWDCH4; + uint32_t RESERVED0[11]; +} stc_adc_awd0chsr_bit_t; + +typedef struct +{ + __IO uint32_t AWDCH0; + __IO uint32_t AWDCH1; + __IO uint32_t AWDCH2; + __IO uint32_t AWDCH3; + __IO uint32_t AWDCH4; + uint32_t RESERVED0[11]; +} stc_adc_awd1chsr_bit_t; + +typedef struct +{ + __IO uint32_t PGACTL0; + __IO uint32_t PGACTL1; + __IO uint32_t PGACTL2; + __IO uint32_t PGACTL3; + __IO uint32_t PGAGAIN0; + __IO uint32_t PGAGAIN1; + __IO uint32_t PGAGAIN2; + __IO uint32_t PGAGAIN3; +} stc_adc_pgacr1_bit_t; + +typedef struct +{ + __IO uint32_t PGACTL0; + __IO uint32_t PGACTL1; + __IO uint32_t PGACTL2; + __IO uint32_t PGACTL3; + __IO uint32_t PGAGAIN0; + __IO uint32_t PGAGAIN1; + __IO uint32_t PGAGAIN2; + __IO uint32_t PGAGAIN3; +} stc_adc_pgacr2_bit_t; + +typedef struct +{ + __IO uint32_t PGACTL0; + __IO uint32_t PGACTL1; + __IO uint32_t PGACTL2; + __IO uint32_t PGACTL3; + __IO uint32_t PGAGAIN0; + __IO uint32_t PGAGAIN1; + __IO uint32_t PGAGAIN2; + __IO uint32_t PGAGAIN3; +} stc_adc_pgacr3_bit_t; + +typedef struct +{ + __IO uint32_t PGAVSSEN0; + __IO uint32_t PGAVSSEN1; + __IO uint32_t PGAVSSEN2; + uint32_t RESERVED0[5]; +} stc_adc_pgavssenr_bit_t; + +typedef struct +{ + __IO uint32_t START; + __IO uint32_t MODE; + uint32_t RESERVED0[30]; +} stc_aes_cr_bit_t; + +typedef struct +{ + __IO uint32_t STRG; + uint32_t RESERVED0[31]; +} stc_aos_int_sfttrg_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dcu_1_trgsel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dcu_2_trgsel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dcu_3_trgsel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dcu_4_trgsel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dma_1_trgsel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dma_2_trgsel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_dma_trgselrc_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmr6_htssr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_port_pevnttrgsr12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_port_pevnttrgsr34_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmr0_htssr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmr2_htssr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_hash_itrgsela_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_hash_itrgselb_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_tmra_htssr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_ots_trg_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_adc_1_itrgselr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_adc_2_itrgselr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[30]; + __IO uint32_t COMTRG_EN0; + __IO uint32_t COMTRG_EN1; +} stc_aos_adc_3_itrgselr_bit_t; + +typedef struct +{ + __IO uint32_t PDIR0; + __IO uint32_t PDIR1; + __IO uint32_t PDIR2; + __IO uint32_t PDIR3; + __IO uint32_t PDIR4; + __IO uint32_t PDIR5; + __IO uint32_t PDIR6; + __IO uint32_t PDIR7; + __IO uint32_t PDIR8; + __IO uint32_t PDIR9; + __IO uint32_t PDIR10; + __IO uint32_t PDIR11; + __IO uint32_t PDIR12; + __IO uint32_t PDIR13; + __IO uint32_t PDIR14; + __IO uint32_t PDIR15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntdirr_bit_t; + +typedef struct +{ + __IO uint32_t PIN0; + __IO uint32_t PIN1; + __IO uint32_t PIN2; + __IO uint32_t PIN3; + __IO uint32_t PIN4; + __IO uint32_t PIN5; + __IO uint32_t PIN6; + __IO uint32_t PIN7; + __IO uint32_t PIN8; + __IO uint32_t PIN9; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntidr_bit_t; + +typedef struct +{ + __IO uint32_t POUT0; + __IO uint32_t POUT1; + __IO uint32_t POUT2; + __IO uint32_t POUT3; + __IO uint32_t POUT4; + __IO uint32_t POUT5; + __IO uint32_t POUT6; + __IO uint32_t POUT7; + __IO uint32_t POUT8; + __IO uint32_t POUT9; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntodr_bit_t; + +typedef struct +{ + __IO uint32_t POR0; + __IO uint32_t POR1; + __IO uint32_t POR2; + __IO uint32_t POR3; + __IO uint32_t POR4; + __IO uint32_t POR5; + __IO uint32_t POR6; + __IO uint32_t POR7; + __IO uint32_t POR8; + __IO uint32_t POR9; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntorr_bit_t; + +typedef struct +{ + __IO uint32_t POS0; + __IO uint32_t POS1; + __IO uint32_t POS2; + __IO uint32_t POS3; + __IO uint32_t POS4; + __IO uint32_t POS5; + __IO uint32_t POS6; + __IO uint32_t POS7; + __IO uint32_t POS8; + __IO uint32_t POS9; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntosr_bit_t; + +typedef struct +{ + __IO uint32_t RIS0; + __IO uint32_t RIS1; + __IO uint32_t RIS2; + __IO uint32_t RIS3; + __IO uint32_t RIS4; + __IO uint32_t RIS5; + __IO uint32_t RIS6; + __IO uint32_t RIS7; + __IO uint32_t RIS8; + __IO uint32_t RIS9; + __IO uint32_t RIS10; + __IO uint32_t RIS11; + __IO uint32_t RIS12; + __IO uint32_t RIS13; + __IO uint32_t RIS14; + __IO uint32_t RIS15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntrisr_bit_t; + +typedef struct +{ + __IO uint32_t FAL0; + __IO uint32_t FAL1; + __IO uint32_t FAL2; + __IO uint32_t FAL3; + __IO uint32_t FAL4; + __IO uint32_t FAL5; + __IO uint32_t FAL6; + __IO uint32_t FAL7; + __IO uint32_t FAL8; + __IO uint32_t FAL9; + __IO uint32_t FAL10; + __IO uint32_t FAL11; + __IO uint32_t FAL12; + __IO uint32_t FAL13; + __IO uint32_t FAL14; + __IO uint32_t FAL15; + uint32_t RESERVED0[16]; +} stc_aos_gpio_pevntfal_bit_t; + +typedef struct +{ + __IO uint32_t NFEN1; + uint32_t RESERVED0[7]; + __IO uint32_t NFEN2; + uint32_t RESERVED1[7]; + __IO uint32_t NFEN3; + uint32_t RESERVED2[7]; + __IO uint32_t NFEN4; + uint32_t RESERVED3[7]; +} stc_aos_gpio_pevntnfcr_bit_t; + +typedef struct +{ + __IO uint32_t BUSOFF; + __IO uint32_t TACTIVE; + __IO uint32_t RACTIVE; + __IO uint32_t TSSS; + __IO uint32_t TPSS; + __IO uint32_t LBMI; + __IO uint32_t LBME; + __IO uint32_t RESET; +} stc_can_cfg_stat_bit_t; + +typedef struct +{ + __IO uint32_t TSA; + __IO uint32_t TSALL; + __IO uint32_t TSONE; + __IO uint32_t TPA; + __IO uint32_t TPE; + uint32_t RESERVED0[1]; + __IO uint32_t LOM; + __IO uint32_t TBSEL; +} stc_can_tcmd_bit_t; + +typedef struct +{ + __IO uint32_t TSSTAT0; + __IO uint32_t TSSTAT1; + uint32_t RESERVED0[2]; + __IO uint32_t TTTBM; + __IO uint32_t TSMODE; + __IO uint32_t TSNEXT; + __IO uint32_t FD_ISO; +} stc_can_tctrl_bit_t; + +typedef struct +{ + __IO uint32_t RSTAT0; + __IO uint32_t RSTAT1; + uint32_t RESERVED0[1]; + __IO uint32_t RBALL; + __IO uint32_t RREL; + __IO uint32_t ROV; + __IO uint32_t ROM; + __IO uint32_t SACK; +} stc_can_rctrl_bit_t; + +typedef struct +{ + __IO uint32_t TSFF; + __IO uint32_t EIE; + __IO uint32_t TSIE; + __IO uint32_t TPIE; + __IO uint32_t RAFIE; + __IO uint32_t RFIE; + __IO uint32_t ROIE; + __IO uint32_t RIE; +} stc_can_rtie_bit_t; + +typedef struct +{ + __IO uint32_t AIF; + __IO uint32_t EIF; + __IO uint32_t TSIF; + __IO uint32_t TPIF; + __IO uint32_t RAFIF; + __IO uint32_t RFIF; + __IO uint32_t ROIF; + __IO uint32_t RIF; +} stc_can_rtif_bit_t; + +typedef struct +{ + __IO uint32_t BEIF; + __IO uint32_t BEIE; + __IO uint32_t ALIF; + __IO uint32_t ALIE; + __IO uint32_t EPIF; + __IO uint32_t EPIE; + __IO uint32_t EPASS; + __IO uint32_t EWARN; +} stc_can_errint_bit_t; + +typedef struct +{ + __IO uint32_t EWL0; + __IO uint32_t EWL1; + __IO uint32_t EWL2; + __IO uint32_t EWL3; + __IO uint32_t AFWL0; + __IO uint32_t AFWL1; + __IO uint32_t AFWL2; + __IO uint32_t AFWL3; +} stc_can_limit_bit_t; + +typedef struct +{ + __IO uint32_t S_SEG_10; + __IO uint32_t S_SEG_11; + __IO uint32_t S_SEG_12; + __IO uint32_t S_SEG_13; + __IO uint32_t S_SEG_14; + __IO uint32_t S_SEG_15; + __IO uint32_t S_SEG_16; + __IO uint32_t S_SEG_17; + __IO uint32_t S_SEG_20; + __IO uint32_t S_SEG_21; + __IO uint32_t S_SEG_22; + __IO uint32_t S_SEG_23; + __IO uint32_t S_SEG_24; + __IO uint32_t S_SEG_25; + __IO uint32_t S_SEG_26; + uint32_t RESERVED0[1]; + __IO uint32_t S_SJW0; + __IO uint32_t S_SJW1; + __IO uint32_t S_SJW2; + __IO uint32_t S_SJW3; + __IO uint32_t S_SJW4; + __IO uint32_t S_SJW5; + __IO uint32_t S_SJW6; + uint32_t RESERVED1[1]; + __IO uint32_t S_PRESC0; + __IO uint32_t S_PRESC1; + __IO uint32_t S_PRESC2; + __IO uint32_t S_PRESC3; + __IO uint32_t S_PRESC4; + __IO uint32_t S_PRESC5; + __IO uint32_t S_PRESC6; + __IO uint32_t S_PRESC7; +} stc_can_sbt_bit_t; + +typedef struct +{ + __IO uint32_t F_SEG_10; + __IO uint32_t F_SEG_11; + __IO uint32_t F_SEG_12; + __IO uint32_t F_SEG_13; + __IO uint32_t F_SEG_14; + uint32_t RESERVED0[3]; + __IO uint32_t F_SEG_20; + __IO uint32_t F_SEG_21; + __IO uint32_t F_SEG_22; + __IO uint32_t F_SEG_23; + uint32_t RESERVED1[4]; + __IO uint32_t F_SJW0; + __IO uint32_t F_SJW1; + __IO uint32_t F_SJW2; + __IO uint32_t F_SJW3; + uint32_t RESERVED2[4]; + __IO uint32_t F_PRESC0; + __IO uint32_t F_PRESC1; + __IO uint32_t F_PRESC2; + __IO uint32_t F_PRESC3; + __IO uint32_t F_PRESC4; + __IO uint32_t F_PRESC5; + __IO uint32_t F_PRESC6; + __IO uint32_t F_PRESC7; +} stc_can_fbt_bit_t; + +typedef struct +{ + __IO uint32_t ALC0; + __IO uint32_t ALC1; + __IO uint32_t ALC2; + __IO uint32_t ALC3; + __IO uint32_t ALC4; + __IO uint32_t KOER0; + __IO uint32_t KOER1; + __IO uint32_t KOER2; +} stc_can_ealcap_bit_t; + +typedef struct +{ + __IO uint32_t SSPOFF0; + __IO uint32_t SSPOFF1; + __IO uint32_t SSPOFF2; + __IO uint32_t SSPOFF3; + __IO uint32_t SSPOFF4; + __IO uint32_t SSPOFF5; + __IO uint32_t SSPOFF6; + __IO uint32_t TDCEN; +} stc_can_tdc_bit_t; + +typedef struct +{ + __IO uint32_t ACFADR0; + __IO uint32_t ACFADR1; + __IO uint32_t ACFADR2; + __IO uint32_t ACFADR3; + uint32_t RESERVED0[1]; + __IO uint32_t SELMASK; + uint32_t RESERVED1[2]; +} stc_can_acfctrl_bit_t; + +typedef struct +{ + __IO uint32_t AE_1; + __IO uint32_t AE_2; + __IO uint32_t AE_3; + __IO uint32_t AE_4; + __IO uint32_t AE_5; + __IO uint32_t AE_6; + __IO uint32_t AE_7; + __IO uint32_t AE_8; + __IO uint32_t AE_9; + __IO uint32_t AE_10; + __IO uint32_t AE_11; + __IO uint32_t AE_12; + __IO uint32_t AE_13; + __IO uint32_t AE_14; + __IO uint32_t AE_15; + __IO uint32_t AE_16; +} stc_can_acfen_bit_t; + +typedef struct +{ + __IO uint32_t ACODEORAMASK0; + __IO uint32_t ACODEORAMASK1; + __IO uint32_t ACODEORAMASK2; + __IO uint32_t ACODEORAMASK3; + __IO uint32_t ACODEORAMASK4; + __IO uint32_t ACODEORAMASK5; + __IO uint32_t ACODEORAMASK6; + __IO uint32_t ACODEORAMASK7; + __IO uint32_t ACODEORAMASK8; + __IO uint32_t ACODEORAMASK9; + __IO uint32_t ACODEORAMASK10; + __IO uint32_t ACODEORAMASK11; + __IO uint32_t ACODEORAMASK12; + __IO uint32_t ACODEORAMASK13; + __IO uint32_t ACODEORAMASK14; + __IO uint32_t ACODEORAMASK15; + __IO uint32_t ACODEORAMASK16; + __IO uint32_t ACODEORAMASK17; + __IO uint32_t ACODEORAMASK18; + __IO uint32_t ACODEORAMASK19; + __IO uint32_t ACODEORAMASK20; + __IO uint32_t ACODEORAMASK21; + __IO uint32_t ACODEORAMASK22; + __IO uint32_t ACODEORAMASK23; + __IO uint32_t ACODEORAMASK24; + __IO uint32_t ACODEORAMASK25; + __IO uint32_t ACODEORAMASK26; + __IO uint32_t ACODEORAMASK27; + __IO uint32_t ACODEORAMASK28; + __IO uint32_t AIDE; + __IO uint32_t AIDEE; + uint32_t RESERVED0[1]; +} stc_can_acf_bit_t; + +typedef struct +{ + __IO uint32_t TBPTR0; + __IO uint32_t TBPTR1; + __IO uint32_t TBPTR2; + __IO uint32_t TBPTR3; + __IO uint32_t TBPTR4; + __IO uint32_t TBPTR5; + __IO uint32_t TBF; + __IO uint32_t TBE; +} stc_can_tbslot_bit_t; + +typedef struct +{ + __IO uint32_t TTEN; + __IO uint32_t T_PRESC0; + __IO uint32_t T_PRESC1; + __IO uint32_t TTIF; + __IO uint32_t TTIE; + __IO uint32_t TEIF; + __IO uint32_t WTIF; + __IO uint32_t WTIE; +} stc_can_ttcfg_bit_t; + +typedef struct +{ + __IO uint32_t REF_ID0; + __IO uint32_t REF_ID1; + __IO uint32_t REF_ID2; + __IO uint32_t REF_ID3; + __IO uint32_t REF_ID4; + __IO uint32_t REF_ID5; + __IO uint32_t REF_ID6; + __IO uint32_t REF_ID7; + __IO uint32_t REF_ID8; + __IO uint32_t REF_ID9; + __IO uint32_t REF_ID10; + __IO uint32_t REF_ID11; + __IO uint32_t REF_ID12; + __IO uint32_t REF_ID13; + __IO uint32_t REF_ID14; + __IO uint32_t REF_ID15; + __IO uint32_t REF_ID16; + __IO uint32_t REF_ID17; + __IO uint32_t REF_ID18; + __IO uint32_t REF_ID19; + __IO uint32_t REF_ID20; + __IO uint32_t REF_ID21; + __IO uint32_t REF_ID22; + __IO uint32_t REF_ID23; + __IO uint32_t REF_ID24; + __IO uint32_t REF_ID25; + __IO uint32_t REF_ID26; + __IO uint32_t REF_ID27; + __IO uint32_t REF_ID28; + uint32_t RESERVED0[2]; + __IO uint32_t REF_IDE; +} stc_can_ref_msg_bit_t; + +typedef struct +{ + __IO uint32_t TTPTR0; + __IO uint32_t TTPTR1; + __IO uint32_t TTPTR2; + __IO uint32_t TTPTR3; + __IO uint32_t TTPTR4; + __IO uint32_t TTPTR5; + uint32_t RESERVED0[2]; + __IO uint32_t TTYPE0; + __IO uint32_t TTYPE1; + __IO uint32_t TTYPE2; + uint32_t RESERVED1[1]; + __IO uint32_t TEW0; + __IO uint32_t TEW1; + __IO uint32_t TEW2; + __IO uint32_t TEW3; +} stc_can_trg_cfg_bit_t; + +typedef struct +{ + __IO uint32_t CENB; + __IO uint32_t CWDE; + uint32_t RESERVED0[5]; + __IO uint32_t CMON; +} stc_cmp_mdr_bit_t; + +typedef struct +{ + __IO uint32_t FCKS0; + __IO uint32_t FCKS1; + uint32_t RESERVED0[2]; + __IO uint32_t EDGS0; + __IO uint32_t EDGS1; + __IO uint32_t CIEN; + uint32_t RESERVED1[1]; +} stc_cmp_fir_bit_t; + +typedef struct +{ + __IO uint32_t COEN; + __IO uint32_t COPS; + __IO uint32_t CPOE; + __IO uint32_t TWOE; + __IO uint32_t TWOL; + uint32_t RESERVED0[3]; +} stc_cmp_ocr_bit_t; + +typedef struct +{ + __IO uint32_t RVSL0; + __IO uint32_t RVSL1; + __IO uint32_t RVSL2; + __IO uint32_t RVSL3; + __IO uint32_t CVSL0; + __IO uint32_t CVSL1; + __IO uint32_t CVSL2; + __IO uint32_t CVSL3; +} stc_cmp_pmsr_bit_t; + +typedef struct +{ + __IO uint32_t CTWS0; + __IO uint32_t CTWS1; + __IO uint32_t CTWS2; + __IO uint32_t CTWS3; + __IO uint32_t CTWS4; + __IO uint32_t CTWS5; + __IO uint32_t CTWS6; + __IO uint32_t CTWS7; + __IO uint32_t CTWS8; + __IO uint32_t CTWS9; + __IO uint32_t CTWS10; + __IO uint32_t CTWS11; + __IO uint32_t CTWS12; + __IO uint32_t CTWS13; + __IO uint32_t CTWS14; + __IO uint32_t CTWS15; +} stc_cmp_twsr_bit_t; + +typedef struct +{ + __IO uint32_t CTWP0; + __IO uint32_t CTWP1; + __IO uint32_t CTWP2; + __IO uint32_t CTWP3; + __IO uint32_t CTWP4; + __IO uint32_t CTWP5; + __IO uint32_t CTWP6; + __IO uint32_t CTWP7; + __IO uint32_t CTWP8; + __IO uint32_t CTWP9; + __IO uint32_t CTWP10; + __IO uint32_t CTWP11; + __IO uint32_t CTWP12; + __IO uint32_t CTWP13; + __IO uint32_t CTWP14; + __IO uint32_t CTWP15; +} stc_cmp_twpr_bit_t; + +typedef struct +{ + __IO uint32_t P2SL0; + __IO uint32_t P2SL1; + __IO uint32_t P2SL2; + uint32_t RESERVED0[1]; + __IO uint32_t P3SL0; + __IO uint32_t P3SL1; + uint32_t RESERVED1[10]; +} stc_cmp_visr_bit_t; + +typedef struct +{ + __IO uint32_t XTAL32STP; + uint32_t RESERVED0[7]; +} stc_cmu_xtal32cr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_cmu_xtal32cfgr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_cmu_xtal32nfr_bit_t; + +typedef struct +{ + __IO uint32_t LRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_lrccr_bit_t; + +typedef struct +{ + __IO uint32_t RTCLRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_rtclrccr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[6]; + __IO uint32_t XTALMS; + uint32_t RESERVED1[1]; +} stc_cmu_xtalcfgr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; +} stc_cmu_pericksel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; +} stc_cmu_i2scksel_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_cmu_canckcfgr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_cmu_usbckcfgr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_cmu_ckswr_bit_t; + +typedef struct +{ + __IO uint32_t PLLHOFF; + uint32_t RESERVED0[7]; +} stc_cmu_pllhcr_bit_t; + +typedef struct +{ + __IO uint32_t PLLAOFF; + uint32_t RESERVED0[7]; +} stc_cmu_pllacr_bit_t; + +typedef struct +{ + __IO uint32_t XTALSTP; + uint32_t RESERVED0[7]; +} stc_cmu_xtalcr_bit_t; + +typedef struct +{ + __IO uint32_t HRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_hrccr_bit_t; + +typedef struct +{ + __IO uint32_t MRCSTP; + uint32_t RESERVED0[7]; +} stc_cmu_mrccr_bit_t; + +typedef struct +{ + __IO uint32_t HRCSTBF; + uint32_t RESERVED0[2]; + __IO uint32_t XTALSTBF; + uint32_t RESERVED1[1]; + __IO uint32_t PLLHSTBF; + __IO uint32_t PLLASTBF; + __IO uint32_t PLLBSTBF; +} stc_cmu_oscstbsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[7]; + __IO uint32_t MCO1EN; +} stc_cmu_mco1cfgr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[7]; + __IO uint32_t MCO2EN; +} stc_cmu_mco2cfgr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[7]; + __IO uint32_t TPIUCKOE; +} stc_cmu_tpiuckcfgr_bit_t; + +typedef struct +{ + __IO uint32_t XTALSTDIE; + __IO uint32_t XTALSTDRE; + __IO uint32_t XTALSTDRIS; + uint32_t RESERVED0[4]; + __IO uint32_t XTALSTDE; +} stc_cmu_xtalstdcr_bit_t; + +typedef struct +{ + __IO uint32_t XTALSTDF; + uint32_t RESERVED0[7]; +} stc_cmu_xtalstdsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_cmu_xtalstbcr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[7]; + __IO uint32_t PLLSRC; + uint32_t RESERVED1[24]; +} stc_cmu_pllhcfgr_bit_t; + +typedef struct +{ + __IO uint32_t CR; + __IO uint32_t FLAG; + uint32_t RESERVED0[30]; +} stc_crc_cr_bit_t; + +typedef struct +{ + __IO uint32_t REFPSC0; + __IO uint32_t REFPSC1; + __IO uint32_t REFPSC2; + uint32_t RESERVED0[1]; + __IO uint32_t REFCKS0; + __IO uint32_t REFCKS1; + __IO uint32_t ERRIE; + __IO uint32_t CTCEN; + uint32_t RESERVED1[24]; +} stc_ctc_cr1_bit_t; + +typedef struct +{ + __IO uint32_t OFSVAL0; + __IO uint32_t OFSVAL1; + __IO uint32_t OFSVAL2; + __IO uint32_t OFSVAL3; + __IO uint32_t OFSVAL4; + __IO uint32_t OFSVAL5; + __IO uint32_t OFSVAL6; + __IO uint32_t OFSVAL7; + uint32_t RESERVED0[24]; +} stc_ctc_cr2_bit_t; + +typedef struct +{ + __IO uint32_t TRIMOK; + __IO uint32_t TRMOVF; + __IO uint32_t TRMUDF; + __IO uint32_t CTCBSY; + uint32_t RESERVED0[28]; +} stc_ctc_str_bit_t; + +typedef struct +{ + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DL0R4; + __IO uint32_t DL1R5; + __IO uint32_t DL2R6; + __IO uint32_t DL3R7; + __IO uint32_t DL4R8; + __IO uint32_t DL5R9; + __IO uint32_t DL6R10; + __IO uint32_t DL7R11; + __IO uint32_t DL8; + __IO uint32_t DL9; + __IO uint32_t DL10; + __IO uint32_t DL11; +} stc_dac_dadr1_bit_t; + +typedef struct +{ + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DL0R4; + __IO uint32_t DL1R5; + __IO uint32_t DL2R6; + __IO uint32_t DL3R7; + __IO uint32_t DL4R8; + __IO uint32_t DL5R9; + __IO uint32_t DL6R10; + __IO uint32_t DL7R11; + __IO uint32_t DL8; + __IO uint32_t DL9; + __IO uint32_t DL10; + __IO uint32_t DL11; +} stc_dac_dadr2_bit_t; + +typedef struct +{ + __IO uint32_t DAE; + __IO uint32_t DA1E; + __IO uint32_t DA2E; + uint32_t RESERVED0[5]; + __IO uint32_t DPSEL; + __IO uint32_t DAAMP1; + __IO uint32_t DAAMP2; + __IO uint32_t EXTDSL1; + __IO uint32_t EXTDSL2; + uint32_t RESERVED1[3]; +} stc_dac_dacr_bit_t; + +typedef struct +{ + __IO uint32_t ADPSL1; + __IO uint32_t ADPSL2; + __IO uint32_t ADPSL3; + uint32_t RESERVED0[5]; + __IO uint32_t DA1SF; + __IO uint32_t DA2SF; + uint32_t RESERVED1[5]; + __IO uint32_t ADPEN; +} stc_dac_daadpcr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t DAODIS1; + __IO uint32_t DAODIS2; +} stc_dac_daocr_bit_t; + +typedef struct +{ + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t MODE2; + __IO uint32_t MODE3; + __IO uint32_t DATASIZE0; + __IO uint32_t DATASIZE1; + uint32_t RESERVED0[2]; + __IO uint32_t COMP_TRG; + uint32_t RESERVED1[22]; + __IO uint32_t INTEN; +} stc_dcu_ctl_bit_t; + +typedef struct +{ + __IO uint32_t FLAG_OP; + __IO uint32_t FLAG_LS2; + __IO uint32_t FLAG_EQ2; + __IO uint32_t FLAG_GT2; + __IO uint32_t FLAG_LS1; + __IO uint32_t FLAG_EQ1; + __IO uint32_t FLAG_GT1; + uint32_t RESERVED0[2]; + __IO uint32_t FLAG_RLD; + __IO uint32_t FLAG_BTM; + __IO uint32_t FLAG_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_flag_bit_t; + +typedef struct +{ + __IO uint32_t CLR_OP; + __IO uint32_t CLR_LS2; + __IO uint32_t CLR_EQ2; + __IO uint32_t CLR_GT2; + __IO uint32_t CLR_LS1; + __IO uint32_t CLR_EQ1; + __IO uint32_t CLR_GT1; + uint32_t RESERVED0[2]; + __IO uint32_t CLR_RLD; + __IO uint32_t CLR_BTM; + __IO uint32_t CLR_TOP; + uint32_t RESERVED1[20]; +} stc_dcu_flagclr_bit_t; + +typedef struct +{ + __IO uint32_t SEL_OP; + __IO uint32_t SEL_LS2; + __IO uint32_t SEL_EQ2; + __IO uint32_t SEL_GT2; + __IO uint32_t SEL_LS1; + __IO uint32_t SEL_EQ1; + __IO uint32_t SEL_GT1; + __IO uint32_t SEL_WIN0; + __IO uint32_t SEL_WIN1; + __IO uint32_t SEL_RLD; + __IO uint32_t SEL_BTM; + __IO uint32_t SEL_TOP; + uint32_t RESERVED0[20]; +} stc_dcu_intevtsel_bit_t; + +typedef struct +{ + __IO uint32_t EN; + uint32_t RESERVED0[31]; +} stc_dma_en_bit_t; + +typedef struct +{ + __IO uint32_t TRNERR0; + __IO uint32_t TRNERR1; + __IO uint32_t TRNERR2; + __IO uint32_t TRNERR3; + __IO uint32_t TRNERR4; + __IO uint32_t TRNERR5; + __IO uint32_t TRNERR6; + __IO uint32_t TRNERR7; + uint32_t RESERVED0[8]; + __IO uint32_t REQERR0; + __IO uint32_t REQERR1; + __IO uint32_t REQERR2; + __IO uint32_t REQERR3; + __IO uint32_t REQERR4; + __IO uint32_t REQERR5; + __IO uint32_t REQERR6; + __IO uint32_t REQERR7; + uint32_t RESERVED1[8]; +} stc_dma_intstat0_bit_t; + +typedef struct +{ + __IO uint32_t TC0; + __IO uint32_t TC1; + __IO uint32_t TC2; + __IO uint32_t TC3; + __IO uint32_t TC4; + __IO uint32_t TC5; + __IO uint32_t TC6; + __IO uint32_t TC7; + uint32_t RESERVED0[8]; + __IO uint32_t BTC0; + __IO uint32_t BTC1; + __IO uint32_t BTC2; + __IO uint32_t BTC3; + __IO uint32_t BTC4; + __IO uint32_t BTC5; + __IO uint32_t BTC6; + __IO uint32_t BTC7; + uint32_t RESERVED1[8]; +} stc_dma_intstat1_bit_t; + +typedef struct +{ + __IO uint32_t MSKTRNERR0; + __IO uint32_t MSKTRNERR1; + __IO uint32_t MSKTRNERR2; + __IO uint32_t MSKTRNERR3; + __IO uint32_t MSKTRNERR4; + __IO uint32_t MSKTRNERR5; + __IO uint32_t MSKTRNERR6; + __IO uint32_t MSKTRNERR7; + uint32_t RESERVED0[8]; + __IO uint32_t MSKREQERR0; + __IO uint32_t MSKREQERR1; + __IO uint32_t MSKREQERR2; + __IO uint32_t MSKREQERR3; + __IO uint32_t MSKREQERR4; + __IO uint32_t MSKREQERR5; + __IO uint32_t MSKREQERR6; + __IO uint32_t MSKREQERR7; + uint32_t RESERVED1[8]; +} stc_dma_intmask0_bit_t; + +typedef struct +{ + __IO uint32_t MSKTC0; + __IO uint32_t MSKTC1; + __IO uint32_t MSKTC2; + __IO uint32_t MSKTC3; + __IO uint32_t MSKTC4; + __IO uint32_t MSKTC5; + __IO uint32_t MSKTC6; + __IO uint32_t MSKTC7; + uint32_t RESERVED0[8]; + __IO uint32_t MSKBTC0; + __IO uint32_t MSKBTC1; + __IO uint32_t MSKBTC2; + __IO uint32_t MSKBTC3; + __IO uint32_t MSKBTC4; + __IO uint32_t MSKBTC5; + __IO uint32_t MSKBTC6; + __IO uint32_t MSKBTC7; + uint32_t RESERVED1[8]; +} stc_dma_intmask1_bit_t; + +typedef struct +{ + __IO uint32_t CLRTRNERR0; + __IO uint32_t CLRTRNERR1; + __IO uint32_t CLRTRNERR2; + __IO uint32_t CLRTRNERR3; + __IO uint32_t CLRTRNERR4; + __IO uint32_t CLRTRNERR5; + __IO uint32_t CLRTRNERR6; + __IO uint32_t CLRTRNERR7; + uint32_t RESERVED0[8]; + __IO uint32_t CLRREQERR0; + __IO uint32_t CLRREQERR1; + __IO uint32_t CLRREQERR2; + __IO uint32_t CLRREQERR3; + __IO uint32_t CLRREQERR4; + __IO uint32_t CLRREQERR5; + __IO uint32_t CLRREQERR6; + __IO uint32_t CLRREQERR7; + uint32_t RESERVED1[8]; +} stc_dma_intclr0_bit_t; + +typedef struct +{ + __IO uint32_t CLRTC0; + __IO uint32_t CLRTC1; + __IO uint32_t CLRTC2; + __IO uint32_t CLRTC3; + __IO uint32_t CLRTC4; + __IO uint32_t CLRTC5; + __IO uint32_t CLRTC6; + __IO uint32_t CLRTC7; + uint32_t RESERVED0[8]; + __IO uint32_t CLRBTC0; + __IO uint32_t CLRBTC1; + __IO uint32_t CLRBTC2; + __IO uint32_t CLRBTC3; + __IO uint32_t CLRBTC4; + __IO uint32_t CLRBTC5; + __IO uint32_t CLRBTC6; + __IO uint32_t CLRBTC7; + uint32_t RESERVED1[8]; +} stc_dma_intclr1_bit_t; + +typedef struct +{ + __IO uint32_t CHEN0; + __IO uint32_t CHEN1; + __IO uint32_t CHEN2; + __IO uint32_t CHEN3; + __IO uint32_t CHEN4; + __IO uint32_t CHEN5; + __IO uint32_t CHEN6; + __IO uint32_t CHEN7; + uint32_t RESERVED0[24]; +} stc_dma_chen_bit_t; + +typedef struct +{ + __IO uint32_t CHREQ0; + __IO uint32_t CHREQ1; + __IO uint32_t CHREQ2; + __IO uint32_t CHREQ3; + __IO uint32_t CHREQ4; + __IO uint32_t CHREQ5; + __IO uint32_t CHREQ6; + __IO uint32_t CHREQ7; + uint32_t RESERVED0[7]; + __IO uint32_t RCFGREQ; + uint32_t RESERVED1[16]; +} stc_dma_reqstat_bit_t; + +typedef struct +{ + __IO uint32_t DMAACT; + __IO uint32_t RCFGACT; + uint32_t RESERVED0[14]; + __IO uint32_t CHACT0; + __IO uint32_t CHACT1; + __IO uint32_t CHACT2; + __IO uint32_t CHACT3; + __IO uint32_t CHACT4; + __IO uint32_t CHACT5; + __IO uint32_t CHACT6; + __IO uint32_t CHACT7; + uint32_t RESERVED1[8]; +} stc_dma_chstat_bit_t; + +typedef struct +{ + __IO uint32_t RCFGEN; + __IO uint32_t RCFGLLP; + uint32_t RESERVED0[14]; + __IO uint32_t SARMD0; + __IO uint32_t SARMD1; + __IO uint32_t DARMD0; + __IO uint32_t DARMD1; + __IO uint32_t CNTMD0; + __IO uint32_t CNTMD1; + uint32_t RESERVED1[10]; +} stc_dma_rcfgctl_bit_t; + +typedef struct +{ + __IO uint32_t CHENCLR0; + __IO uint32_t CHENCLR1; + __IO uint32_t CHENCLR2; + __IO uint32_t CHENCLR3; + __IO uint32_t CHENCLR4; + __IO uint32_t CHENCLR5; + __IO uint32_t CHENCLR6; + __IO uint32_t CHENCLR7; + uint32_t RESERVED0[24]; +} stc_dma_chenclr_bit_t; + +typedef struct +{ + __IO uint32_t SINC0; + __IO uint32_t SINC1; + __IO uint32_t DINC0; + __IO uint32_t DINC1; + __IO uint32_t SRTPEN; + __IO uint32_t DRPTEN; + __IO uint32_t SNSEQEN; + __IO uint32_t DNSEQEN; + __IO uint32_t HSIZE0; + __IO uint32_t HSIZE1; + __IO uint32_t LLPEN; + __IO uint32_t LLPRUN; + __IO uint32_t IE; + uint32_t RESERVED0[19]; +} stc_dma_chctl_bit_t; + +typedef struct +{ + __IO uint32_t CAPEN; + __IO uint32_t CAPMD; + __IO uint32_t CROPEN; + __IO uint32_t JPEGEN; + __IO uint32_t SWSYNC; + __IO uint32_t PIXCKSEL; + __IO uint32_t HSYNCSEL; + __IO uint32_t VSYNCSEL; + __IO uint32_t CAPFRC0; + __IO uint32_t CAPFRC1; + __IO uint32_t BITSEL0; + __IO uint32_t BITSEL1; + uint32_t RESERVED0[2]; + __IO uint32_t DVPEN; + uint32_t RESERVED1[17]; +} stc_dvp_ctr_bit_t; + +typedef struct +{ + __IO uint32_t FSF; + __IO uint32_t LSF; + __IO uint32_t LEF; + __IO uint32_t FEF; + __IO uint32_t SQUERF; + __IO uint32_t FIFOERF; + uint32_t RESERVED0[26]; +} stc_dvp_str_bit_t; + +typedef struct +{ + __IO uint32_t FSIEN; + __IO uint32_t LSIEN; + __IO uint32_t LEIEN; + __IO uint32_t FEIEN; + __IO uint32_t SQUERIEN; + __IO uint32_t FIFOERIEN; + uint32_t RESERVED0[26]; +} stc_dvp_ier_bit_t; + +typedef struct +{ + __IO uint32_t FAPRT0; + __IO uint32_t FAPRT1; + __IO uint32_t FAPRT2; + __IO uint32_t FAPRT3; + __IO uint32_t FAPRT4; + __IO uint32_t FAPRT5; + __IO uint32_t FAPRT6; + __IO uint32_t FAPRT7; + __IO uint32_t FAPRT8; + __IO uint32_t FAPRT9; + __IO uint32_t FAPRT10; + __IO uint32_t FAPRT11; + __IO uint32_t FAPRT12; + __IO uint32_t FAPRT13; + __IO uint32_t FAPRT14; + __IO uint32_t FAPRT15; + uint32_t RESERVED0[16]; +} stc_efm_faprt_bit_t; + +typedef struct +{ + __IO uint32_t F0STP; + __IO uint32_t F1STP; + uint32_t RESERVED0[30]; +} stc_efm_fstp_bit_t; + +typedef struct +{ + __IO uint32_t FLWT0; + __IO uint32_t FLWT1; + __IO uint32_t FLWT2; + __IO uint32_t FLWT3; + uint32_t RESERVED0[4]; + __IO uint32_t LVM; + uint32_t RESERVED1[7]; + __IO uint32_t ICACHE; + __IO uint32_t DCACHE; + __IO uint32_t PREFE; + __IO uint32_t CRST; + uint32_t RESERVED2[12]; +} stc_efm_frmc_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; + __IO uint32_t BUSHLDCTL; + uint32_t RESERVED1[7]; + __IO uint32_t KEY1LOCK; + __IO uint32_t KEY2LOCK; + uint32_t RESERVED2[14]; +} stc_efm_fwmc_bit_t; + +typedef struct +{ + __IO uint32_t OTPWERR0; + __IO uint32_t PRTWERR0; + __IO uint32_t PGSZERR0; + __IO uint32_t MISMTCH0; + __IO uint32_t OPTEND0; + __IO uint32_t COLERR0; + uint32_t RESERVED0[2]; + __IO uint32_t RDY0; + uint32_t RESERVED1[8]; + __IO uint32_t PRTWERR1; + __IO uint32_t PGSZERR1; + __IO uint32_t MISMTCH1; + __IO uint32_t OPTEND1; + __IO uint32_t COLERR1; + uint32_t RESERVED2[2]; + __IO uint32_t RDY1; + uint32_t RESERVED3[7]; +} stc_efm_fsr_bit_t; + +typedef struct +{ + __IO uint32_t OTPWERRCLR0; + __IO uint32_t PRTWERRCLR0; + __IO uint32_t PGSZERRCLR0; + __IO uint32_t MISMTCHCLR0; + __IO uint32_t OPTENDCLR0; + __IO uint32_t COLERRCLR0; + uint32_t RESERVED0[11]; + __IO uint32_t PRTWERRCLR1; + __IO uint32_t PGSZERRCLR1; + __IO uint32_t MISMTCHCLR1; + __IO uint32_t OPTENDCLR1; + __IO uint32_t COLERRCLR1; + uint32_t RESERVED1[10]; +} stc_efm_fsclr_bit_t; + +typedef struct +{ + __IO uint32_t PEERRITE; + __IO uint32_t OPTENDITE; + __IO uint32_t COLERRITE; + uint32_t RESERVED0[29]; +} stc_efm_fite_bit_t; + +typedef struct +{ + __IO uint32_t FSWP; + uint32_t RESERVED0[31]; +} stc_efm_fswp_bit_t; + +typedef struct +{ + uint32_t RESERVED0[31]; + __IO uint32_t EN0; +} stc_mmf_remcr0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[31]; + __IO uint32_t EN1; +} stc_mmf_remcr1_bit_t; + +typedef struct +{ + __IO uint32_t WLOCK0; + __IO uint32_t WLOCK1; + __IO uint32_t WLOCK2; + __IO uint32_t WLOCK3; + __IO uint32_t WLOCK4; + __IO uint32_t WLOCK5; + __IO uint32_t WLOCK6; + __IO uint32_t WLOCK7; + uint32_t RESERVED0[24]; +} stc_efm_wlock_bit_t; + +typedef struct +{ + __IO uint32_t CMPEN0; + __IO uint32_t CMPEN1; + __IO uint32_t CMPEN2; + __IO uint32_t CMPEN3; + __IO uint32_t OSCSTPEN; + __IO uint32_t PWMSEN0; + __IO uint32_t PWMSEN1; + __IO uint32_t PWMSEN2; + __IO uint32_t PWMSEN3; + __IO uint32_t PWMSEN4; + __IO uint32_t PWMSEN5; + __IO uint32_t PWMSEN6; + __IO uint32_t PWMSEN7; + uint32_t RESERVED0[3]; + __IO uint32_t PORTINEN1; + __IO uint32_t PORTINEN2; + __IO uint32_t PORTINEN3; + __IO uint32_t PORTINEN4; + uint32_t RESERVED1[2]; + __IO uint32_t INVSEL1; + __IO uint32_t INVSEL2; + __IO uint32_t INVSEL3; + __IO uint32_t INVSEL4; + uint32_t RESERVED2[6]; +} stc_emb_ctl1_bit_t; + +typedef struct +{ + __IO uint32_t PWMLV0; + __IO uint32_t PWMLV1; + __IO uint32_t PWMLV2; + __IO uint32_t PWMLV3; + __IO uint32_t PWMLV4; + __IO uint32_t PWMLV5; + __IO uint32_t PWMLV6; + __IO uint32_t PWMLV7; + uint32_t RESERVED0[8]; + __IO uint32_t NFSEL10; + __IO uint32_t NFSEL11; + __IO uint32_t NFEN1; + __IO uint32_t NFSEL20; + __IO uint32_t NFSEL21; + __IO uint32_t NFEN2; + __IO uint32_t NFSEL30; + __IO uint32_t NFSEL31; + __IO uint32_t NFEN3; + __IO uint32_t NFSEL40; + __IO uint32_t NFSEL41; + __IO uint32_t NFEN4; + uint32_t RESERVED1[4]; +} stc_emb_ctl2_bit_t; + +typedef struct +{ + __IO uint32_t SOE; + uint32_t RESERVED0[31]; +} stc_emb_soe_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t PWMSF; + __IO uint32_t CMPF; + __IO uint32_t OSF; + uint32_t RESERVED1[1]; + __IO uint32_t PWMST; + __IO uint32_t CMPST; + __IO uint32_t OSST; + __IO uint32_t PORTINF1; + __IO uint32_t PORTINF2; + __IO uint32_t PORTINF3; + __IO uint32_t PORTINF4; + uint32_t RESERVED2[2]; + __IO uint32_t PORTINST1; + __IO uint32_t PORTINST2; + __IO uint32_t PORTINST3; + __IO uint32_t PORTINST4; + uint32_t RESERVED3[14]; +} stc_emb_stat_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t PWMSFCLR; + __IO uint32_t CMPFCLR; + __IO uint32_t OSFCLR; + uint32_t RESERVED1[4]; + __IO uint32_t PORTINFCLR1; + __IO uint32_t PORTINFCLR2; + __IO uint32_t PORTINFCLR3; + __IO uint32_t PORTINFCLR4; + uint32_t RESERVED2[20]; +} stc_emb_statclr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t PWMSINTEN; + __IO uint32_t CMPINTEN; + __IO uint32_t OSINTEN; + uint32_t RESERVED1[4]; + __IO uint32_t PORTINTEN1; + __IO uint32_t PORTINTEN2; + __IO uint32_t PORTINTEN3; + __IO uint32_t PORTINTEN4; + uint32_t RESERVED2[20]; +} stc_emb_inten_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t PWMRSEL; + __IO uint32_t CMPRSEL; + __IO uint32_t OSRSEL; + uint32_t RESERVED1[4]; + __IO uint32_t PORTINRSEL1; + __IO uint32_t PORTINRSEL2; + __IO uint32_t PORTINRSEL3; + __IO uint32_t PORTINRSEL4; + uint32_t RESERVED2[20]; +} stc_emb_rlssel_bit_t; + +typedef struct +{ + __IO uint32_t IFSEL; + uint32_t RESERVED0[3]; + __IO uint32_t RCKINV; + __IO uint32_t TCKINV; + uint32_t RESERVED1[26]; +} stc_eth_mac_ifconfr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t DC; + __IO uint32_t BL0; + __IO uint32_t BL1; + __IO uint32_t ACS; + uint32_t RESERVED1[1]; + __IO uint32_t DRTY; + __IO uint32_t IPCO; + __IO uint32_t DM; + __IO uint32_t LM; + __IO uint32_t DO; + __IO uint32_t FES; + uint32_t RESERVED2[1]; + __IO uint32_t DCRS; + __IO uint32_t IFG0; + __IO uint32_t IFG1; + __IO uint32_t IFG2; + uint32_t RESERVED3[2]; + __IO uint32_t MJB; + __IO uint32_t MWD; + uint32_t RESERVED4[1]; + __IO uint32_t CST; + uint32_t RESERVED5[2]; + __IO uint32_t SAIRC0; + __IO uint32_t SAIRC1; + __IO uint32_t SAIRC2; + uint32_t RESERVED6[1]; +} stc_eth_mac_configr_bit_t; + +typedef struct +{ + __IO uint32_t PR; + __IO uint32_t HUC; + __IO uint32_t HMC; + __IO uint32_t DAIF; + __IO uint32_t PMF; + __IO uint32_t DBF; + __IO uint32_t PCF0; + __IO uint32_t PCF1; + __IO uint32_t SAIF; + __IO uint32_t SAF; + __IO uint32_t HPF; + uint32_t RESERVED0[5]; + __IO uint32_t VTFE; + uint32_t RESERVED1[3]; + __IO uint32_t IPFE; + __IO uint32_t DNTU; + uint32_t RESERVED2[9]; + __IO uint32_t RA; +} stc_eth_mac_fltctlr_bit_t; + +typedef struct +{ + __IO uint32_t SMIB; + __IO uint32_t SMIW; + __IO uint32_t SMIC0; + __IO uint32_t SMIC1; + __IO uint32_t SMIC2; + __IO uint32_t SMIC3; + __IO uint32_t SMIR0; + __IO uint32_t SMIR1; + __IO uint32_t SMIR2; + __IO uint32_t SMIR3; + __IO uint32_t SMIR4; + __IO uint32_t SMIA0; + __IO uint32_t SMIA1; + __IO uint32_t SMIA2; + __IO uint32_t SMIA3; + __IO uint32_t SMIA4; + uint32_t RESERVED0[16]; +} stc_eth_mac_smiaddr_bit_t; + +typedef struct +{ + __IO uint32_t FCA_BPA; + __IO uint32_t TFE; + __IO uint32_t RFE; + __IO uint32_t UNP; + __IO uint32_t PLT0; + __IO uint32_t PLT1; + uint32_t RESERVED0[1]; + __IO uint32_t DZPQ; + uint32_t RESERVED1[24]; +} stc_eth_mac_floctlr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; + __IO uint32_t VTAL; + __IO uint32_t VTIM; + uint32_t RESERVED1[1]; + __IO uint32_t VTHM; + uint32_t RESERVED2[12]; +} stc_eth_mac_vtafltr_bit_t; + +typedef struct +{ + __IO uint32_t MREA; + __IO uint32_t MRS0; + __IO uint32_t MRS1; + uint32_t RESERVED0[1]; + __IO uint32_t RFWA; + __IO uint32_t RFRS0; + __IO uint32_t RFRS1; + uint32_t RESERVED1[1]; + __IO uint32_t RFFL0; + __IO uint32_t RFFL1; + uint32_t RESERVED2[6]; + __IO uint32_t MTEA; + __IO uint32_t MTS0; + __IO uint32_t MTS1; + __IO uint32_t MTP; + __IO uint32_t TFRS0; + __IO uint32_t TFRS1; + __IO uint32_t TFWA; + uint32_t RESERVED3[1]; + __IO uint32_t TFNE; + __IO uint32_t TFF; + uint32_t RESERVED4[6]; +} stc_eth_mac_macstsr_bit_t; + +typedef struct +{ + __IO uint32_t PWDN; + __IO uint32_t MPEN; + __IO uint32_t WKEN; + uint32_t RESERVED0[2]; + __IO uint32_t MPFR; + __IO uint32_t WKFR; + uint32_t RESERVED1[2]; + __IO uint32_t GLUB; + __IO uint32_t RTWKTR; + uint32_t RESERVED2[13]; + __IO uint32_t RTWKPT0; + __IO uint32_t RTWKPT1; + __IO uint32_t RTWKPT2; + uint32_t RESERVED3[4]; + __IO uint32_t RTWKFR; +} stc_eth_mac_pmtctlr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[3]; + __IO uint32_t PMTIS; + __IO uint32_t MMCIS; + __IO uint32_t MMCRXIS; + __IO uint32_t MMCTXIS; + uint32_t RESERVED1[2]; + __IO uint32_t TSPIS; + uint32_t RESERVED2[22]; +} stc_eth_mac_intstsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[3]; + __IO uint32_t PMTIM; + uint32_t RESERVED1[5]; + __IO uint32_t TSPIM; + uint32_t RESERVED2[22]; +} stc_eth_mac_intmskr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[31]; + __IO uint32_t AE0; +} stc_eth_mac_macadhr0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[24]; + __IO uint32_t MBC10; + __IO uint32_t MBC11; + __IO uint32_t MBC12; + __IO uint32_t MBC13; + __IO uint32_t MBC14; + __IO uint32_t MBC15; + __IO uint32_t SA1; + __IO uint32_t AE1; +} stc_eth_mac_macadhr1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[24]; + __IO uint32_t MBC20; + __IO uint32_t MBC21; + __IO uint32_t MBC22; + __IO uint32_t MBC23; + __IO uint32_t MBC24; + __IO uint32_t MBC25; + __IO uint32_t SA2; + __IO uint32_t AE2; +} stc_eth_mac_macadhr2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[24]; + __IO uint32_t MBC30; + __IO uint32_t MBC31; + __IO uint32_t MBC32; + __IO uint32_t MBC33; + __IO uint32_t MBC34; + __IO uint32_t MBC35; + __IO uint32_t SA3; + __IO uint32_t AE3; +} stc_eth_mac_macadhr3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[24]; + __IO uint32_t MBC40; + __IO uint32_t MBC41; + __IO uint32_t MBC42; + __IO uint32_t MBC43; + __IO uint32_t MBC44; + __IO uint32_t MBC45; + __IO uint32_t SA4; + __IO uint32_t AE4; +} stc_eth_mac_macadhr4_bit_t; + +typedef struct +{ + __IO uint32_t CRST; + __IO uint32_t COS; + __IO uint32_t ROR; + __IO uint32_t MCF; + __IO uint32_t MCPSET; + __IO uint32_t MCPSEL; + uint32_t RESERVED0[26]; +} stc_eth_mmc_mmcctlr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[3]; + __IO uint32_t RXBGIS; + __IO uint32_t RXMGIS; + __IO uint32_t RXCEIS; + __IO uint32_t RXAEIS; + __IO uint32_t RXREIS; + uint32_t RESERVED1[9]; + __IO uint32_t RXUGIS; + __IO uint32_t RXLEIS; + __IO uint32_t RXOEIS; + uint32_t RESERVED2[12]; +} stc_eth_mmc_revstsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t TXBGIS; + __IO uint32_t TXMGIS; + uint32_t RESERVED1[12]; + __IO uint32_t TXDEEIS; + __IO uint32_t TXLCEIS; + __IO uint32_t TXECEIS; + __IO uint32_t TXCAEIS; + uint32_t RESERVED2[1]; + __IO uint32_t TXUGIS; + __IO uint32_t TXEDEIS; + uint32_t RESERVED3[9]; +} stc_eth_mmc_trsstsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[3]; + __IO uint32_t RXBGIM; + __IO uint32_t RXMGIM; + __IO uint32_t RXCEIM; + __IO uint32_t RXAEIM; + __IO uint32_t RXREIM; + uint32_t RESERVED1[9]; + __IO uint32_t RXUGIM; + __IO uint32_t RXLEIM; + __IO uint32_t RXOEIM; + uint32_t RESERVED2[12]; +} stc_eth_mmc_ritctlr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t TXBGIM; + __IO uint32_t TXMGIM; + uint32_t RESERVED1[12]; + __IO uint32_t TXDEEIM; + __IO uint32_t TXLCEIM; + __IO uint32_t TXECEIM; + __IO uint32_t TXCAEIM; + uint32_t RESERVED2[1]; + __IO uint32_t TXUGIM; + __IO uint32_t TXEDEIM; + uint32_t RESERVED3[9]; +} stc_eth_mmc_titctlr_bit_t; + +typedef struct +{ + __IO uint32_t L3PEN; + uint32_t RESERVED0[1]; + __IO uint32_t L3SAM; + __IO uint32_t L3SAIM; + __IO uint32_t L3DAM; + __IO uint32_t L3DAIM; + __IO uint32_t L3HSBM0; + __IO uint32_t L3HSBM1; + __IO uint32_t L3HSBM2; + __IO uint32_t L3HSBM3; + __IO uint32_t L3HSBM4; + __IO uint32_t L3HDBM0; + __IO uint32_t L3HDBM1; + __IO uint32_t L3HDBM2; + __IO uint32_t L3HDBM3; + __IO uint32_t L3HDBM4; + __IO uint32_t L4PEN; + uint32_t RESERVED1[1]; + __IO uint32_t L4SPM; + __IO uint32_t L4SPIM; + __IO uint32_t L4DPM; + __IO uint32_t L4DPIM; + uint32_t RESERVED2[10]; +} stc_eth_mac_l34ctlr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; + __IO uint32_t VLANC0; + __IO uint32_t VLANC1; + __IO uint32_t VLANS; + uint32_t RESERVED1[13]; +} stc_eth_mac_vtactlr_bit_t; + +typedef struct +{ + __IO uint32_t TSPEN; + __IO uint32_t TSPUPSEL; + __IO uint32_t TSPINI; + __IO uint32_t TSPUP; + __IO uint32_t TSPINT; + __IO uint32_t TSPADUP; + uint32_t RESERVED0[2]; + __IO uint32_t TSPEALL; + __IO uint32_t TSPSSR; + __IO uint32_t TSPVER; + __IO uint32_t TSPOVETH; + __IO uint32_t TSPOVIPV6; + __IO uint32_t TSPOVIPV4; + __IO uint32_t TSPMTSEL0; + __IO uint32_t TSPMTSEL1; + __IO uint32_t TSPMTSEL2; + __IO uint32_t TSPMTSEL3; + __IO uint32_t TSPADF; + uint32_t RESERVED1[13]; +} stc_eth_ptp_tspctlr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[31]; + __IO uint32_t TSPUPNS; +} stc_eth_ptp_tmunser_bit_t; + +typedef struct +{ + __IO uint32_t TSOVF; + __IO uint32_t TSTAR0; + uint32_t RESERVED0[1]; + __IO uint32_t TSERR0; + __IO uint32_t TSTAR1; + __IO uint32_t TSERR1; + uint32_t RESERVED1[26]; +} stc_eth_ptp_tspstsr_bit_t; + +typedef struct +{ + __IO uint32_t PPSFRE00; + __IO uint32_t PPSFRE01; + __IO uint32_t PPSFRE02; + __IO uint32_t PPSFRE03; + __IO uint32_t PPSOMD; + __IO uint32_t TT0SEL0; + __IO uint32_t TT0SEL1; + uint32_t RESERVED0[1]; + __IO uint32_t PPSFRE10; + __IO uint32_t PPSFRE11; + __IO uint32_t PPSFRE12; + uint32_t RESERVED1[2]; + __IO uint32_t TT1SEL0; + __IO uint32_t TT1SEL1; + uint32_t RESERVED2[17]; +} stc_eth_ptp_ppsctlr_bit_t; + +typedef struct +{ + __IO uint32_t SWR; + __IO uint32_t DMAA; + __IO uint32_t DSL0; + __IO uint32_t DSL1; + __IO uint32_t DSL2; + __IO uint32_t DSL3; + __IO uint32_t DSL4; + __IO uint32_t DSEN; + __IO uint32_t TPBL0; + __IO uint32_t TPBL1; + __IO uint32_t TPBL2; + __IO uint32_t TPBL3; + __IO uint32_t TPBL4; + __IO uint32_t TPBL5; + __IO uint32_t PRAT0; + __IO uint32_t PRAT1; + __IO uint32_t FBST; + __IO uint32_t RPBL0; + __IO uint32_t RPBL1; + __IO uint32_t RPBL2; + __IO uint32_t RPBL3; + __IO uint32_t RPBL4; + __IO uint32_t RPBL5; + __IO uint32_t SPBL; + __IO uint32_t M8PBL; + __IO uint32_t AAL; + __IO uint32_t MBST; + __IO uint32_t TXPR; + uint32_t RESERVED0[4]; +} stc_eth_dma_busmodr_bit_t; + +typedef struct +{ + __IO uint32_t TIS; + __IO uint32_t TSS; + __IO uint32_t TUS; + __IO uint32_t TJS; + __IO uint32_t OVS; + __IO uint32_t UNS; + __IO uint32_t RIS; + __IO uint32_t RUS; + __IO uint32_t RSS; + __IO uint32_t RWS; + __IO uint32_t ETS; + uint32_t RESERVED0[2]; + __IO uint32_t FBS; + __IO uint32_t ERS; + __IO uint32_t AIS; + __IO uint32_t NIS; + __IO uint32_t RSTS0; + __IO uint32_t RSTS1; + __IO uint32_t RSTS2; + __IO uint32_t TSTS0; + __IO uint32_t TSTS1; + __IO uint32_t TSTS2; + __IO uint32_t EBUS0; + __IO uint32_t EBUS1; + __IO uint32_t EBUS2; + uint32_t RESERVED1[1]; + __IO uint32_t MMCS; + __IO uint32_t PMTS; + __IO uint32_t PTPS; + uint32_t RESERVED2[2]; +} stc_eth_dma_dmastsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t STR; + __IO uint32_t OSF; + __IO uint32_t RTC0; + __IO uint32_t RTC1; + __IO uint32_t DGF; + __IO uint32_t FUF; + __IO uint32_t FEF; + uint32_t RESERVED1[5]; + __IO uint32_t STT; + __IO uint32_t TTC0; + __IO uint32_t TTC1; + __IO uint32_t TTC2; + uint32_t RESERVED2[3]; + __IO uint32_t FTF; + __IO uint32_t TSF; + uint32_t RESERVED3[2]; + __IO uint32_t DFRF; + __IO uint32_t RSF; + __IO uint32_t DTCOE; + uint32_t RESERVED4[5]; +} stc_eth_dma_oprmodr_bit_t; + +typedef struct +{ + __IO uint32_t TIE; + __IO uint32_t TSE; + __IO uint32_t TUE; + __IO uint32_t TJE; + __IO uint32_t OVE; + __IO uint32_t UNE; + __IO uint32_t RIE; + __IO uint32_t RUE; + __IO uint32_t RSE; + __IO uint32_t RWE; + __IO uint32_t ETE; + uint32_t RESERVED0[2]; + __IO uint32_t FBE; + __IO uint32_t ERE; + __IO uint32_t AIE; + __IO uint32_t NIE; + uint32_t RESERVED1[15]; +} stc_eth_dma_intenar_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; + __IO uint32_t UNAOVF; + uint32_t RESERVED1[11]; + __IO uint32_t OVFOVF; + uint32_t RESERVED2[3]; +} stc_eth_dma_rfrcntr_bit_t; + +typedef struct +{ + __IO uint32_t START; + uint32_t RESERVED0[31]; +} stc_fcm_str_bit_t; + +typedef struct +{ + uint32_t RESERVED0[7]; + __IO uint32_t INEXS; + __IO uint32_t DNFS0; + __IO uint32_t DNFS1; + uint32_t RESERVED1[2]; + __IO uint32_t EDGES0; + __IO uint32_t EDGES1; + uint32_t RESERVED2[1]; + __IO uint32_t EXREFE; + uint32_t RESERVED3[16]; +} stc_fcm_rccr_bit_t; + +typedef struct +{ + __IO uint32_t ERRIE; + __IO uint32_t MENDIE; + __IO uint32_t OVFIE; + uint32_t RESERVED0[1]; + __IO uint32_t ERRINTRS; + uint32_t RESERVED1[2]; + __IO uint32_t ERRE; + uint32_t RESERVED2[24]; +} stc_fcm_rier_bit_t; + +typedef struct +{ + __IO uint32_t ERRF; + __IO uint32_t MENDF; + __IO uint32_t OVF; + uint32_t RESERVED0[29]; +} stc_fcm_sr_bit_t; + +typedef struct +{ + __IO uint32_t ERRFCLR; + __IO uint32_t MENDFCLR; + __IO uint32_t OVFCLR; + uint32_t RESERVED0[29]; +} stc_fcm_clr_bit_t; + +typedef struct +{ + __IO uint32_t FMACEN; + uint32_t RESERVED0[31]; +} stc_fmac_enr_bit_t; + +typedef struct +{ + __IO uint32_t INTEN; + uint32_t RESERVED0[31]; +} stc_fmac_ier_bit_t; + +typedef struct +{ + uint32_t RESERVED0[31]; + __IO uint32_t READY; +} stc_fmac_str_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidra_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podra_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poera_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posra_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porra_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potra_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidrb_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podrb_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poerb_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posrb_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porrb_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potrb_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidrc_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podrc_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poerc_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posrc_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porrc_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potrc_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidrd_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podrd_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poerd_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posrd_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porrd_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potrd_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidre_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podre_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poere_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posre_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porre_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potre_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidrf_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podrf_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poerf_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posrf_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porrf_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potrf_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidrg_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podrg_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poerg_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posrg_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porrg_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potrg_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + __IO uint32_t PIN14; + __IO uint32_t PIN15; +} stc_gpio_pidrh_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + __IO uint32_t POUT14; + __IO uint32_t POUT15; +} stc_gpio_podrh_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + __IO uint32_t POUTE14; + __IO uint32_t POUTE15; +} stc_gpio_poerh_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + __IO uint32_t POS14; + __IO uint32_t POS15; +} stc_gpio_posrh_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + __IO uint32_t POR14; + __IO uint32_t POR15; +} stc_gpio_porrh_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + __IO uint32_t POT14; + __IO uint32_t POT15; +} stc_gpio_potrh_bit_t; + +typedef struct +{ + __IO uint32_t PIN00; + __IO uint32_t PIN01; + __IO uint32_t PIN02; + __IO uint32_t PIN03; + __IO uint32_t PIN04; + __IO uint32_t PIN05; + __IO uint32_t PIN06; + __IO uint32_t PIN07; + __IO uint32_t PIN08; + __IO uint32_t PIN09; + __IO uint32_t PIN10; + __IO uint32_t PIN11; + __IO uint32_t PIN12; + __IO uint32_t PIN13; + uint32_t RESERVED0[2]; +} stc_gpio_pidri_bit_t; + +typedef struct +{ + __IO uint32_t POUT00; + __IO uint32_t POUT01; + __IO uint32_t POUT02; + __IO uint32_t POUT03; + __IO uint32_t POUT04; + __IO uint32_t POUT05; + __IO uint32_t POUT06; + __IO uint32_t POUT07; + __IO uint32_t POUT08; + __IO uint32_t POUT09; + __IO uint32_t POUT10; + __IO uint32_t POUT11; + __IO uint32_t POUT12; + __IO uint32_t POUT13; + uint32_t RESERVED0[2]; +} stc_gpio_podri_bit_t; + +typedef struct +{ + __IO uint32_t POUTE00; + __IO uint32_t POUTE01; + __IO uint32_t POUTE02; + __IO uint32_t POUTE03; + __IO uint32_t POUTE04; + __IO uint32_t POUTE05; + __IO uint32_t POUTE06; + __IO uint32_t POUTE07; + __IO uint32_t POUTE08; + __IO uint32_t POUTE09; + __IO uint32_t POUTE10; + __IO uint32_t POUTE11; + __IO uint32_t POUTE12; + __IO uint32_t POUTE13; + uint32_t RESERVED0[2]; +} stc_gpio_poeri_bit_t; + +typedef struct +{ + __IO uint32_t POS00; + __IO uint32_t POS01; + __IO uint32_t POS02; + __IO uint32_t POS03; + __IO uint32_t POS04; + __IO uint32_t POS05; + __IO uint32_t POS06; + __IO uint32_t POS07; + __IO uint32_t POS08; + __IO uint32_t POS09; + __IO uint32_t POS10; + __IO uint32_t POS11; + __IO uint32_t POS12; + __IO uint32_t POS13; + uint32_t RESERVED0[2]; +} stc_gpio_posri_bit_t; + +typedef struct +{ + __IO uint32_t POR00; + __IO uint32_t POR01; + __IO uint32_t POR02; + __IO uint32_t POR03; + __IO uint32_t POR04; + __IO uint32_t POR05; + __IO uint32_t POR06; + __IO uint32_t POR07; + __IO uint32_t POR08; + __IO uint32_t POR09; + __IO uint32_t POR10; + __IO uint32_t POR11; + __IO uint32_t POR12; + __IO uint32_t POR13; + uint32_t RESERVED0[2]; +} stc_gpio_porri_bit_t; + +typedef struct +{ + __IO uint32_t POT00; + __IO uint32_t POT01; + __IO uint32_t POT02; + __IO uint32_t POT03; + __IO uint32_t POT04; + __IO uint32_t POT05; + __IO uint32_t POT06; + __IO uint32_t POT07; + __IO uint32_t POT08; + __IO uint32_t POT09; + __IO uint32_t POT10; + __IO uint32_t POT11; + __IO uint32_t POT12; + __IO uint32_t POT13; + uint32_t RESERVED0[2]; +} stc_gpio_potri_bit_t; + +typedef struct +{ + __IO uint32_t SPFE0; + __IO uint32_t SPFE1; + __IO uint32_t SPFE2; + __IO uint32_t SPFE3; + __IO uint32_t SPFE4; + uint32_t RESERVED0[11]; +} stc_gpio_pspcr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; +} stc_gpio_pccr_bit_t; + +typedef struct +{ + __IO uint32_t PINAE0; + __IO uint32_t PINAE1; + __IO uint32_t PINAE2; + __IO uint32_t PINAE3; + __IO uint32_t PINAE4; + __IO uint32_t PINAE5; + __IO uint32_t PINAE6; + __IO uint32_t PINAE7; + __IO uint32_t PINAE8; + uint32_t RESERVED0[7]; +} stc_gpio_pinaer_bit_t; + +typedef struct +{ + __IO uint32_t WE; + uint32_t RESERVED0[15]; +} stc_gpio_pwpr_bit_t; + +typedef struct +{ + __IO uint32_t POUT; + __IO uint32_t POUTE; + __IO uint32_t NOD; + uint32_t RESERVED0[1]; + __IO uint32_t DRV0; + __IO uint32_t DRV1; + __IO uint32_t PUU; + uint32_t RESERVED1[1]; + __IO uint32_t PIN; + __IO uint32_t INVE; + __IO uint32_t CINSEL; + uint32_t RESERVED2[1]; + __IO uint32_t INTE; + uint32_t RESERVED3[1]; + __IO uint32_t LTE; + __IO uint32_t DDIS; +} stc_gpio_pcr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; + __IO uint32_t BFE; + uint32_t RESERVED1[7]; +} stc_gpio_pfsr_bit_t; + +typedef struct +{ + __IO uint32_t START; + __IO uint32_t FST_GRP; + __IO uint32_t KMSG_END; + uint32_t RESERVED0[1]; + __IO uint32_t MODE0; + __IO uint32_t MODE1; + __IO uint32_t LKEY; + uint32_t RESERVED1[1]; + __IO uint32_t BUSY; + __IO uint32_t CYC_END; + __IO uint32_t HMAC_END; + uint32_t RESERVED2[3]; + __IO uint32_t HCIE; + __IO uint32_t HEIE; + uint32_t RESERVED3[16]; +} stc_hash_cr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t NE; + __IO uint32_t PE; + __IO uint32_t EN; +} stc_hrpwm_cr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[12]; + __IO uint32_t ENDF; + uint32_t RESERVED1[2]; + __IO uint32_t CALEN; + uint32_t RESERVED2[16]; +} stc_hrpwm_calcr_bit_t; + +typedef struct +{ + __IO uint32_t PE; + __IO uint32_t SMBUS; + __IO uint32_t SMBALRTEN; + __IO uint32_t SMBDEFAULTEN; + __IO uint32_t SMBHOSTEN; + uint32_t RESERVED0[1]; + __IO uint32_t ENGC; + __IO uint32_t RESTART; + __IO uint32_t START; + __IO uint32_t STOP; + __IO uint32_t ACK; + uint32_t RESERVED1[4]; + __IO uint32_t SWRST; + uint32_t RESERVED2[16]; +} stc_i2c_cr1_bit_t; + +typedef struct +{ + __IO uint32_t STARTIE; + __IO uint32_t SLADDR0IE; + __IO uint32_t SLADDR1IE; + __IO uint32_t TENDIE; + __IO uint32_t STOPIE; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLIE; + __IO uint32_t TEMPTYIE; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOIE; + uint32_t RESERVED2[2]; + __IO uint32_t NACKIE; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTIE; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLIE; + __IO uint32_t SMBDEFAULTIE; + __IO uint32_t SMHOSTIE; + __IO uint32_t SMBALRTIE; + uint32_t RESERVED5[8]; +} stc_i2c_cr2_bit_t; + +typedef struct +{ + __IO uint32_t TMOUTEN; + __IO uint32_t LTMOUT; + __IO uint32_t HTMOUT; + uint32_t RESERVED0[4]; + __IO uint32_t FACKEN; + uint32_t RESERVED1[24]; +} stc_i2c_cr3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR0EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD0; + uint32_t RESERVED2[16]; +} stc_i2c_slr0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[12]; + __IO uint32_t SLADDR1EN; + uint32_t RESERVED1[2]; + __IO uint32_t ADDRMOD1; + uint32_t RESERVED2[16]; +} stc_i2c_slr1_bit_t; + +typedef struct +{ + __IO uint32_t STARTF; + __IO uint32_t SLADDR0F; + __IO uint32_t SLADDR1F; + __IO uint32_t TENDF; + __IO uint32_t STOPF; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLF; + __IO uint32_t TEMPTYF; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOF; + __IO uint32_t ACKRF; + uint32_t RESERVED2[1]; + __IO uint32_t NACKF; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTF; + uint32_t RESERVED4[1]; + __IO uint32_t MSL; + __IO uint32_t BUSY; + __IO uint32_t TRA; + uint32_t RESERVED5[1]; + __IO uint32_t GENCALLF; + __IO uint32_t SMBDEFAULTF; + __IO uint32_t SMBHOSTF; + __IO uint32_t SMBALRTF; + uint32_t RESERVED6[8]; +} stc_i2c_sr_bit_t; + +typedef struct +{ + __IO uint32_t STARTFCLR; + __IO uint32_t SLADDR0FCLR; + __IO uint32_t SLADDR1FCLR; + __IO uint32_t TENDFCLR; + __IO uint32_t STOPFCLR; + uint32_t RESERVED0[1]; + __IO uint32_t RFULLFCLR; + __IO uint32_t TEMPTYFCLR; + uint32_t RESERVED1[1]; + __IO uint32_t ARLOFCLR; + uint32_t RESERVED2[2]; + __IO uint32_t NACKFCLR; + uint32_t RESERVED3[1]; + __IO uint32_t TMOUTFCLR; + uint32_t RESERVED4[5]; + __IO uint32_t GENCALLFCLR; + __IO uint32_t SMBDEFAULTFCLR; + __IO uint32_t SMBHOSTFCLR; + __IO uint32_t SMBALRTFCLR; + uint32_t RESERVED5[8]; +} stc_i2c_clr_bit_t; + +typedef struct +{ + __IO uint32_t DT0; + __IO uint32_t DT1; + __IO uint32_t DT2; + __IO uint32_t DT3; + __IO uint32_t DT4; + __IO uint32_t DT5; + __IO uint32_t DT6; + __IO uint32_t DT7; +} stc_i2c_dtr_bit_t; + +typedef struct +{ + __IO uint32_t DR0; + __IO uint32_t DR1; + __IO uint32_t DR2; + __IO uint32_t DR3; + __IO uint32_t DR4; + __IO uint32_t DR5; + __IO uint32_t DR6; + __IO uint32_t DR7; +} stc_i2c_drr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[4]; + __IO uint32_t DNFEN; + __IO uint32_t ANFEN; + uint32_t RESERVED1[26]; +} stc_i2c_fltr_bit_t; + +typedef struct +{ + __IO uint32_t TXE; + __IO uint32_t TXIE; + __IO uint32_t RXE; + __IO uint32_t RXIE; + __IO uint32_t EIE; + __IO uint32_t WMS; + __IO uint32_t ODD; + __IO uint32_t MCKOE; + __IO uint32_t TXBIRQWL0; + __IO uint32_t TXBIRQWL1; + __IO uint32_t TXBIRQWL2; + uint32_t RESERVED0[1]; + __IO uint32_t RXBIRQWL0; + __IO uint32_t RXBIRQWL1; + __IO uint32_t RXBIRQWL2; + uint32_t RESERVED1[1]; + __IO uint32_t FIFOR; + __IO uint32_t CODECRC; + __IO uint32_t I2SPLLSEL; + __IO uint32_t SDOE; + __IO uint32_t LRCKOE; + __IO uint32_t CKOE; + __IO uint32_t DUPLEX; + __IO uint32_t CLKSEL; + __IO uint32_t SRST; + uint32_t RESERVED2[7]; +} stc_i2s_ctrl_bit_t; + +typedef struct +{ + __IO uint32_t TXBA; + __IO uint32_t RXBA; + __IO uint32_t TXBE; + __IO uint32_t TXBF; + __IO uint32_t RXBE; + __IO uint32_t RXBF; + uint32_t RESERVED0[26]; +} stc_i2s_sr_bit_t; + +typedef struct +{ + __IO uint32_t TXERR; + __IO uint32_t RXERR; + uint32_t RESERVED0[30]; +} stc_i2s_er_bit_t; + +typedef struct +{ + __IO uint32_t I2SSTD0; + __IO uint32_t I2SSTD1; + __IO uint32_t DATLEN0; + __IO uint32_t DATLEN1; + __IO uint32_t CHLEN; + __IO uint32_t PCMSYNC; + uint32_t RESERVED0[26]; +} stc_i2s_cfgr_bit_t; + +typedef struct +{ + __IO uint32_t I2SDIV0; + __IO uint32_t I2SDIV1; + __IO uint32_t I2SDIV2; + __IO uint32_t I2SDIV3; + __IO uint32_t I2SDIV4; + __IO uint32_t I2SDIV5; + __IO uint32_t I2SDIV6; + __IO uint32_t I2SDIV7; + uint32_t RESERVED0[24]; +} stc_i2s_pr_bit_t; + +typedef struct +{ + __IO uint32_t SWDTAUTS; + __IO uint32_t SWDTITS; + __IO uint32_t SWDTPERI0; + __IO uint32_t SWDTPERI1; + __IO uint32_t SWDTCKS0; + __IO uint32_t SWDTCKS1; + __IO uint32_t SWDTCKS2; + __IO uint32_t SWDTCKS3; + __IO uint32_t SWDTWDPT0; + __IO uint32_t SWDTWDPT1; + __IO uint32_t SWDTWDPT2; + __IO uint32_t SWDTWDPT3; + __IO uint32_t SWDTSLPOFF; + uint32_t RESERVED0[3]; + __IO uint32_t WDTAUTS; + __IO uint32_t WDTITS; + __IO uint32_t WDTPERI0; + __IO uint32_t WDTPERI1; + __IO uint32_t WDTCKS0; + __IO uint32_t WDTCKS1; + __IO uint32_t WDTCKS2; + __IO uint32_t WDTCKS3; + __IO uint32_t WDTWDPT0; + __IO uint32_t WDTWDPT1; + __IO uint32_t WDTWDPT2; + __IO uint32_t WDTWDPT3; + __IO uint32_t WDTSLPOFF; + uint32_t RESERVED1[3]; +} stc_icg_icg0_bit_t; + +typedef struct +{ + __IO uint32_t HRCFREQSEL; + uint32_t RESERVED0[7]; + __IO uint32_t HRCSTOP; + uint32_t RESERVED1[7]; + __IO uint32_t BOR_LEV0; + __IO uint32_t BOR_LEV1; + __IO uint32_t BORDIS; + uint32_t RESERVED2[13]; +} stc_icg_icg1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t SWDTENR; + __IO uint32_t PVD1ENR; + __IO uint32_t PVD2ENR; + __IO uint32_t XTAL32STPENR; + __IO uint32_t XTALSTPENR; + uint32_t RESERVED1[2]; + __IO uint32_t REPENR; + __IO uint32_t RECCENR; + __IO uint32_t BUSMENR; + __IO uint32_t WDTENR; + uint32_t RESERVED2[20]; +} stc_intc_nmienr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t SWDTFR; + __IO uint32_t PVD1FR; + __IO uint32_t PVD2FR; + __IO uint32_t XTAL32STPFR; + __IO uint32_t XTALSTPFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPFR; + __IO uint32_t RECCFR; + __IO uint32_t BUSMFR; + __IO uint32_t WDTFR; + uint32_t RESERVED2[20]; +} stc_intc_nmifr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t SWDTCFR; + __IO uint32_t PVD1CFR; + __IO uint32_t PVD2CFR; + __IO uint32_t XTAL32STPCFR; + __IO uint32_t XTALSTPCFR; + uint32_t RESERVED1[2]; + __IO uint32_t REPCFR; + __IO uint32_t RECCCFR; + __IO uint32_t BUSMCFR; + __IO uint32_t WDTCFR; + uint32_t RESERVED2[20]; +} stc_intc_nmicfr_bit_t; + +typedef struct +{ + __IO uint32_t EIRQTRG0; + __IO uint32_t EIRQTRG1; + uint32_t RESERVED0[2]; + __IO uint32_t EISMPCLK0; + __IO uint32_t EISMPCLK1; + uint32_t RESERVED1[1]; + __IO uint32_t EFEN; + uint32_t RESERVED2[7]; + __IO uint32_t NOCEN; + uint32_t RESERVED3[16]; +} stc_intc_eirqcr_bit_t; + +typedef struct +{ + __IO uint32_t EIRQWUEN0; + __IO uint32_t EIRQWUEN1; + __IO uint32_t EIRQWUEN2; + __IO uint32_t EIRQWUEN3; + __IO uint32_t EIRQWUEN4; + __IO uint32_t EIRQWUEN5; + __IO uint32_t EIRQWUEN6; + __IO uint32_t EIRQWUEN7; + __IO uint32_t EIRQWUEN8; + __IO uint32_t EIRQWUEN9; + __IO uint32_t EIRQWUEN10; + __IO uint32_t EIRQWUEN11; + __IO uint32_t EIRQWUEN12; + __IO uint32_t EIRQWUEN13; + __IO uint32_t EIRQWUEN14; + __IO uint32_t EIRQWUEN15; + __IO uint32_t SWDTWUEN; + __IO uint32_t PVD1WUEN; + __IO uint32_t PVD2WUEN; + __IO uint32_t CMPWUEN; + __IO uint32_t WKTMWUEN; + __IO uint32_t RTCALMWUEN; + __IO uint32_t RTCPRDWUEN; + __IO uint32_t TMR0GCMWUEN; + __IO uint32_t TMR2GCMWUEN; + __IO uint32_t TMR2OVFWUEN; + __IO uint32_t RXWUEN; + __IO uint32_t USHWUEN; + __IO uint32_t USFWUEN; + __IO uint32_t ETHWUEN; + uint32_t RESERVED0[2]; +} stc_intc_wupen_bit_t; + +typedef struct +{ + __IO uint32_t EIFR0; + __IO uint32_t EIFR1; + __IO uint32_t EIFR2; + __IO uint32_t EIFR3; + __IO uint32_t EIFR4; + __IO uint32_t EIFR5; + __IO uint32_t EIFR6; + __IO uint32_t EIFR7; + __IO uint32_t EIFR8; + __IO uint32_t EIFR9; + __IO uint32_t EIFR10; + __IO uint32_t EIFR11; + __IO uint32_t EIFR12; + __IO uint32_t EIFR13; + __IO uint32_t EIFR14; + __IO uint32_t EIFR15; + uint32_t RESERVED0[16]; +} stc_intc_eifr_bit_t; + +typedef struct +{ + __IO uint32_t EICFR0; + __IO uint32_t EICFR1; + __IO uint32_t EICFR2; + __IO uint32_t EICFR3; + __IO uint32_t EICFR4; + __IO uint32_t EICFR5; + __IO uint32_t EICFR6; + __IO uint32_t EICFR7; + __IO uint32_t EICFR8; + __IO uint32_t EICFR9; + __IO uint32_t EICFR10; + __IO uint32_t EICFR11; + __IO uint32_t EICFR12; + __IO uint32_t EICFR13; + __IO uint32_t EICFR14; + __IO uint32_t EICFR15; + uint32_t RESERVED0[16]; +} stc_intc_eicfr_bit_t; + +typedef struct +{ + __IO uint32_t VSEL0; + __IO uint32_t VSEL1; + __IO uint32_t VSEL2; + __IO uint32_t VSEL3; + __IO uint32_t VSEL4; + __IO uint32_t VSEL5; + __IO uint32_t VSEL6; + __IO uint32_t VSEL7; + __IO uint32_t VSEL8; + __IO uint32_t VSEL9; + __IO uint32_t VSEL10; + __IO uint32_t VSEL11; + __IO uint32_t VSEL12; + __IO uint32_t VSEL13; + __IO uint32_t VSEL14; + __IO uint32_t VSEL15; + __IO uint32_t VSEL16; + __IO uint32_t VSEL17; + __IO uint32_t VSEL18; + __IO uint32_t VSEL19; + __IO uint32_t VSEL20; + __IO uint32_t VSEL21; + __IO uint32_t VSEL22; + __IO uint32_t VSEL23; + __IO uint32_t VSEL24; + __IO uint32_t VSEL25; + __IO uint32_t VSEL26; + __IO uint32_t VSEL27; + __IO uint32_t VSEL28; + __IO uint32_t VSEL29; + __IO uint32_t VSEL30; + __IO uint32_t VSEL31; +} stc_intc_vssel_bit_t; + +typedef struct +{ + __IO uint32_t SWIE0; + __IO uint32_t SWIE1; + __IO uint32_t SWIE2; + __IO uint32_t SWIE3; + __IO uint32_t SWIE4; + __IO uint32_t SWIE5; + __IO uint32_t SWIE6; + __IO uint32_t SWIE7; + __IO uint32_t SWIE8; + __IO uint32_t SWIE9; + __IO uint32_t SWIE10; + __IO uint32_t SWIE11; + __IO uint32_t SWIE12; + __IO uint32_t SWIE13; + __IO uint32_t SWIE14; + __IO uint32_t SWIE15; + __IO uint32_t SWIE16; + __IO uint32_t SWIE17; + __IO uint32_t SWIE18; + __IO uint32_t SWIE19; + __IO uint32_t SWIE20; + __IO uint32_t SWIE21; + __IO uint32_t SWIE22; + __IO uint32_t SWIE23; + __IO uint32_t SWIE24; + __IO uint32_t SWIE25; + __IO uint32_t SWIE26; + __IO uint32_t SWIE27; + __IO uint32_t SWIE28; + __IO uint32_t SWIE29; + __IO uint32_t SWIE30; + __IO uint32_t SWIE31; +} stc_intc_swier_bit_t; + +typedef struct +{ + __IO uint32_t EVTE0; + __IO uint32_t EVTE1; + __IO uint32_t EVTE2; + __IO uint32_t EVTE3; + __IO uint32_t EVTE4; + __IO uint32_t EVTE5; + __IO uint32_t EVTE6; + __IO uint32_t EVTE7; + __IO uint32_t EVTE8; + __IO uint32_t EVTE9; + __IO uint32_t EVTE10; + __IO uint32_t EVTE11; + __IO uint32_t EVTE12; + __IO uint32_t EVTE13; + __IO uint32_t EVTE14; + __IO uint32_t EVTE15; + __IO uint32_t EVTE16; + __IO uint32_t EVTE17; + __IO uint32_t EVTE18; + __IO uint32_t EVTE19; + __IO uint32_t EVTE20; + __IO uint32_t EVTE21; + __IO uint32_t EVTE22; + __IO uint32_t EVTE23; + __IO uint32_t EVTE24; + __IO uint32_t EVTE25; + __IO uint32_t EVTE26; + __IO uint32_t EVTE27; + __IO uint32_t EVTE28; + __IO uint32_t EVTE29; + __IO uint32_t EVTE30; + __IO uint32_t EVTE31; +} stc_intc_evter_bit_t; + +typedef struct +{ + __IO uint32_t IER0; + __IO uint32_t IER1; + __IO uint32_t IER2; + __IO uint32_t IER3; + __IO uint32_t IER4; + __IO uint32_t IER5; + __IO uint32_t IER6; + __IO uint32_t IER7; + __IO uint32_t IER8; + __IO uint32_t IER9; + __IO uint32_t IER10; + __IO uint32_t IER11; + __IO uint32_t IER12; + __IO uint32_t IER13; + __IO uint32_t IER14; + __IO uint32_t IER15; + __IO uint32_t IER16; + __IO uint32_t IER17; + __IO uint32_t IER18; + __IO uint32_t IER19; + __IO uint32_t IER20; + __IO uint32_t IER21; + __IO uint32_t IER22; + __IO uint32_t IER23; + __IO uint32_t IER24; + __IO uint32_t IER25; + __IO uint32_t IER26; + __IO uint32_t IER27; + __IO uint32_t IER28; + __IO uint32_t IER29; + __IO uint32_t IER30; + __IO uint32_t IER31; +} stc_intc_ier_bit_t; + +typedef struct +{ + __IO uint32_t KEYINSEL0; + __IO uint32_t KEYINSEL1; + __IO uint32_t KEYINSEL2; + __IO uint32_t KEYINSEL3; + __IO uint32_t KEYINSEL4; + __IO uint32_t KEYINSEL5; + __IO uint32_t KEYINSEL6; + __IO uint32_t KEYINSEL7; + __IO uint32_t KEYINSEL8; + __IO uint32_t KEYINSEL9; + __IO uint32_t KEYINSEL10; + __IO uint32_t KEYINSEL11; + __IO uint32_t KEYINSEL12; + __IO uint32_t KEYINSEL13; + __IO uint32_t KEYINSEL14; + __IO uint32_t KEYINSEL15; + uint32_t RESERVED0[4]; + __IO uint32_t CKSEL0; + __IO uint32_t CKSEL1; + uint32_t RESERVED1[10]; +} stc_keyscan_scr_bit_t; + +typedef struct +{ + __IO uint32_t SEN; + uint32_t RESERVED0[31]; +} stc_keyscan_ser_bit_t; + +typedef struct +{ + __IO uint32_t START; + __IO uint32_t INTEN; + uint32_t RESERVED0[1]; + __IO uint32_t BUSY; + uint32_t RESERVED1[28]; +} stc_mau_csr_bit_t; + +typedef struct +{ + __IO uint32_t SQRT_DOUT0; + __IO uint32_t SQRT_DOUT1; + __IO uint32_t SQRT_DOUT2; + __IO uint32_t SQRT_DOUT3; + __IO uint32_t SQRT_DOUT4; + __IO uint32_t SQRT_DOUT5; + __IO uint32_t SQRT_DOUT6; + __IO uint32_t SQRT_DOUT7; + __IO uint32_t SQRT_DOUT8; + __IO uint32_t SQRT_DOUT9; + __IO uint32_t SQRT_DOUT10; + __IO uint32_t SQRT_DOUT11; + __IO uint32_t SQRT_DOUT12; + __IO uint32_t SQRT_DOUT13; + __IO uint32_t SQRT_DOUT14; + __IO uint32_t SQRT_DOUT15; + __IO uint32_t SQRT_DOUT16; + uint32_t RESERVED0[15]; +} stc_mau_rtr0_bit_t; + +typedef struct +{ + __IO uint32_t SIN_DIN0; + __IO uint32_t SIN_DIN1; + __IO uint32_t SIN_DIN2; + __IO uint32_t SIN_DIN3; + __IO uint32_t SIN_DIN4; + __IO uint32_t SIN_DIN5; + __IO uint32_t SIN_DIN6; + __IO uint32_t SIN_DIN7; + __IO uint32_t SIN_DIN8; + __IO uint32_t SIN_DIN9; + __IO uint32_t SIN_DIN10; + __IO uint32_t SIN_DIN11; + uint32_t RESERVED0[20]; +} stc_mau_dtr1_bit_t; + +typedef struct +{ + __IO uint32_t SIN_DOUT0; + __IO uint32_t SIN_DOUT1; + __IO uint32_t SIN_DOUT2; + __IO uint32_t SIN_DOUT3; + __IO uint32_t SIN_DOUT4; + __IO uint32_t SIN_DOUT5; + __IO uint32_t SIN_DOUT6; + __IO uint32_t SIN_DOUT7; + __IO uint32_t SIN_DOUT8; + __IO uint32_t SIN_DOUT9; + __IO uint32_t SIN_DOUT10; + __IO uint32_t SIN_DOUT11; + __IO uint32_t SIN_DOUT12; + __IO uint32_t SIN_DOUT13; + __IO uint32_t SIN_DOUT14; + __IO uint32_t SIN_DOUT15; + uint32_t RESERVED0[16]; +} stc_mau_rtr1_bit_t; + +typedef struct +{ + __IO uint32_t MPURGSIZE0; + __IO uint32_t MPURGSIZE1; + __IO uint32_t MPURGSIZE2; + __IO uint32_t MPURGSIZE3; + __IO uint32_t MPURGSIZE4; + uint32_t RESERVED0[27]; +} stc_mpu_rgd_bit_t; + +typedef struct +{ + __IO uint32_t SMPU1EAF; + __IO uint32_t SMPU2EAF; + __IO uint32_t FMPUEAF; + __IO uint32_t HMPUEAF; + __IO uint32_t EMPUEAF; + uint32_t RESERVED0[27]; +} stc_mpu_sr_bit_t; + +typedef struct +{ + __IO uint32_t SMPU1ECLR; + __IO uint32_t SMPU2ECLR; + __IO uint32_t FMPUECLR; + __IO uint32_t HMPUECLR; + __IO uint32_t EMPUECLR; + uint32_t RESERVED0[27]; +} stc_mpu_eclr_bit_t; + +typedef struct +{ + __IO uint32_t MPUWE; + uint32_t RESERVED0[31]; +} stc_mpu_wp_bit_t; + +typedef struct +{ + __IO uint32_t AESRDP; + __IO uint32_t AESWRP; + __IO uint32_t HASHRDP; + __IO uint32_t HASHWRP; + __IO uint32_t TRNGRDP; + __IO uint32_t TRNGWRP; + __IO uint32_t CRCRDP; + __IO uint32_t CRCWRP; + __IO uint32_t FMCRDP; + __IO uint32_t FMCWRP; + uint32_t RESERVED0[2]; + __IO uint32_t WDTRDP; + __IO uint32_t WDTWRP; + __IO uint32_t SWDTRDP; + __IO uint32_t SWDTWRP; + __IO uint32_t BKSRAMRDP; + __IO uint32_t BKSRAMWRP; + __IO uint32_t RTCRDP; + __IO uint32_t RTCWRP; + __IO uint32_t DMPURDP; + __IO uint32_t DMPUWRP; + __IO uint32_t SRAMCRDP; + __IO uint32_t SRAMCWRP; + __IO uint32_t INTCRDP; + __IO uint32_t INTCWRP; + __IO uint32_t SYSCRDP; + __IO uint32_t SYSCWRP; + __IO uint32_t MSTPRDP; + __IO uint32_t MSPTWRP; + uint32_t RESERVED1[1]; + __IO uint32_t BUSERRE; +} stc_mpu_ippr_bit_t; + +typedef struct +{ + __IO uint32_t S1RG0E; + __IO uint32_t S1RG1E; + __IO uint32_t S1RG2E; + __IO uint32_t S1RG3E; + __IO uint32_t S1RG4E; + __IO uint32_t S1RG5E; + __IO uint32_t S1RG6E; + __IO uint32_t S1RG7E; + __IO uint32_t S1RG8E; + __IO uint32_t S1RG9E; + __IO uint32_t S1RG10E; + __IO uint32_t S1RG11E; + __IO uint32_t S1RG12E; + __IO uint32_t S1RG13E; + __IO uint32_t S1RG14E; + __IO uint32_t S1RG15E; + uint32_t RESERVED0[16]; +} stc_mpu_s1rge_bit_t; + +typedef struct +{ + __IO uint32_t S1RG0WP; + __IO uint32_t S1RG1WP; + __IO uint32_t S1RG2WP; + __IO uint32_t S1RG3WP; + __IO uint32_t S1RG4WP; + __IO uint32_t S1RG5WP; + __IO uint32_t S1RG6WP; + __IO uint32_t S1RG7WP; + __IO uint32_t S1RG8WP; + __IO uint32_t S1RG9WP; + __IO uint32_t S1RG10WP; + __IO uint32_t S1RG11WP; + __IO uint32_t S1RG12WP; + __IO uint32_t S1RG13WP; + __IO uint32_t S1RG14WP; + __IO uint32_t S1RG15WP; + uint32_t RESERVED0[16]; +} stc_mpu_s1rgwp_bit_t; + +typedef struct +{ + __IO uint32_t S1RG0RP; + __IO uint32_t S1RG1RP; + __IO uint32_t S1RG2RP; + __IO uint32_t S1RG3RP; + __IO uint32_t S1RG4RP; + __IO uint32_t S1RG5RP; + __IO uint32_t S1RG6RP; + __IO uint32_t S1RG7RP; + __IO uint32_t S1RG8RP; + __IO uint32_t S1RG9RP; + __IO uint32_t S1RG10RP; + __IO uint32_t S1RG11RP; + __IO uint32_t S1RG12RP; + __IO uint32_t S1RG13RP; + __IO uint32_t S1RG14RP; + __IO uint32_t S1RG15RP; + uint32_t RESERVED0[16]; +} stc_mpu_s1rgrp_bit_t; + +typedef struct +{ + __IO uint32_t SMPU1BRP; + __IO uint32_t SMPU1BWP; + __IO uint32_t SMPU1ACT0; + __IO uint32_t SMPU1ACT1; + uint32_t RESERVED0[3]; + __IO uint32_t SMPU1E; + uint32_t RESERVED1[24]; +} stc_mpu_s1cr_bit_t; + +typedef struct +{ + __IO uint32_t S2RG0E; + __IO uint32_t S2RG1E; + __IO uint32_t S2RG2E; + __IO uint32_t S2RG3E; + __IO uint32_t S2RG4E; + __IO uint32_t S2RG5E; + __IO uint32_t S2RG6E; + __IO uint32_t S2RG7E; + __IO uint32_t S2RG8E; + __IO uint32_t S2RG9E; + __IO uint32_t S2RG10E; + __IO uint32_t S2RG11E; + __IO uint32_t S2RG12E; + __IO uint32_t S2RG13E; + __IO uint32_t S2RG14E; + __IO uint32_t S2RG15E; + uint32_t RESERVED0[16]; +} stc_mpu_s2rge_bit_t; + +typedef struct +{ + __IO uint32_t S2RG0WP; + __IO uint32_t S2RG1WP; + __IO uint32_t S2RG2WP; + __IO uint32_t S2RG3WP; + __IO uint32_t S2RG4WP; + __IO uint32_t S2RG5WP; + __IO uint32_t S2RG6WP; + __IO uint32_t S2RG7WP; + __IO uint32_t S2RG8WP; + __IO uint32_t S2RG9WP; + __IO uint32_t S2RG10WP; + __IO uint32_t S2RG11WP; + __IO uint32_t S2RG12WP; + __IO uint32_t S2RG13WP; + __IO uint32_t S2RG14WP; + __IO uint32_t S2RG15WP; + uint32_t RESERVED0[16]; +} stc_mpu_s2rgwp_bit_t; + +typedef struct +{ + __IO uint32_t S2RG0RP; + __IO uint32_t S2RG1RP; + __IO uint32_t S2RG2RP; + __IO uint32_t S2RG3RP; + __IO uint32_t S2RG4RP; + __IO uint32_t S2RG5RP; + __IO uint32_t S2RG6RP; + __IO uint32_t S2RG7RP; + __IO uint32_t S2RG8RP; + __IO uint32_t S2RG9RP; + __IO uint32_t S2RG10RP; + __IO uint32_t S2RG11RP; + __IO uint32_t S2RG12RP; + __IO uint32_t S2RG13RP; + __IO uint32_t S2RG14RP; + __IO uint32_t S2RG15RP; + uint32_t RESERVED0[16]; +} stc_mpu_s2rgrp_bit_t; + +typedef struct +{ + __IO uint32_t SMPU2BRP; + __IO uint32_t SMPU2BWP; + __IO uint32_t SMPU2ACT0; + __IO uint32_t SMPU2ACT1; + uint32_t RESERVED0[3]; + __IO uint32_t SMPU2E; + uint32_t RESERVED1[24]; +} stc_mpu_s2cr_bit_t; + +typedef struct +{ + __IO uint32_t FMPU0E; + __IO uint32_t FMPU1E; + __IO uint32_t FMPU2E; + __IO uint32_t FMPU3E; + __IO uint32_t FMPU4E; + __IO uint32_t FMPU5E; + __IO uint32_t FMPU6E; + __IO uint32_t FMPU7E; + uint32_t RESERVED0[24]; +} stc_mpu_frge_bit_t; + +typedef struct +{ + __IO uint32_t FMPU0WP; + __IO uint32_t FMPU1WP; + __IO uint32_t FMPU2WP; + __IO uint32_t FMPU3WP; + __IO uint32_t FMPU4WP; + __IO uint32_t FMPU5WP; + __IO uint32_t FMPU6WP; + __IO uint32_t FMPU7WP; + uint32_t RESERVED0[24]; +} stc_mpu_frgwp_bit_t; + +typedef struct +{ + __IO uint32_t FMPU0RP; + __IO uint32_t FMPU1RP; + __IO uint32_t FMPU2RP; + __IO uint32_t FMPU3RP; + __IO uint32_t FMPU4RP; + __IO uint32_t FMPU5RP; + __IO uint32_t FMPU6RP; + __IO uint32_t FMPU7RP; + uint32_t RESERVED0[24]; +} stc_mpu_frgrp_bit_t; + +typedef struct +{ + __IO uint32_t FMPUBRP; + __IO uint32_t FMPUBWP; + __IO uint32_t FMPUACT0; + __IO uint32_t FMPUACT1; + uint32_t RESERVED0[3]; + __IO uint32_t FMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_fcr_bit_t; + +typedef struct +{ + __IO uint32_t HMPU0E; + __IO uint32_t HMPU1E; + __IO uint32_t HMPU2E; + __IO uint32_t HMPU3E; + __IO uint32_t HMPU4E; + __IO uint32_t HMPU5E; + __IO uint32_t HMPU6E; + __IO uint32_t HMPU7E; + uint32_t RESERVED0[24]; +} stc_mpu_hrge_bit_t; + +typedef struct +{ + __IO uint32_t HMPU0WP; + __IO uint32_t HMPU1WP; + __IO uint32_t HMPU2WP; + __IO uint32_t HMPU3WP; + __IO uint32_t HMPU4WP; + __IO uint32_t HMPU5WP; + __IO uint32_t HMPU6WP; + __IO uint32_t HMPU7WP; + uint32_t RESERVED0[24]; +} stc_mpu_hrgwp_bit_t; + +typedef struct +{ + __IO uint32_t HMPU0RP; + __IO uint32_t HMPU1RP; + __IO uint32_t HMPU2RP; + __IO uint32_t HMPU3RP; + __IO uint32_t HMPU4RP; + __IO uint32_t HMPU5RP; + __IO uint32_t HMPU6RP; + __IO uint32_t HMPU7RP; + uint32_t RESERVED0[24]; +} stc_mpu_hrgrp_bit_t; + +typedef struct +{ + __IO uint32_t HMPUBRP; + __IO uint32_t HMPUBWP; + __IO uint32_t HMPUACT0; + __IO uint32_t HMPUACT1; + uint32_t RESERVED0[3]; + __IO uint32_t HMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_hcr_bit_t; + +typedef struct +{ + __IO uint32_t EMPU0E; + __IO uint32_t EMPU1E; + __IO uint32_t EMPU2E; + __IO uint32_t EMPU3E; + __IO uint32_t EMPU4E; + __IO uint32_t EMPU5E; + __IO uint32_t EMPU6E; + __IO uint32_t EMPU7E; + uint32_t RESERVED0[24]; +} stc_mpu_erge_bit_t; + +typedef struct +{ + __IO uint32_t EMPU0WP; + __IO uint32_t EMPU1WP; + __IO uint32_t EMPU2WP; + __IO uint32_t EMPU3WP; + __IO uint32_t EMPU4WP; + __IO uint32_t EMPU5WP; + __IO uint32_t EMPU6WP; + __IO uint32_t EMPU7WP; + uint32_t RESERVED0[24]; +} stc_mpu_ergwp_bit_t; + +typedef struct +{ + __IO uint32_t EMPU0RP; + __IO uint32_t EMPU1RP; + __IO uint32_t EMPU2RP; + __IO uint32_t EMPU3RP; + __IO uint32_t EMPU4RP; + __IO uint32_t EMPU5RP; + __IO uint32_t EMPU6RP; + __IO uint32_t EMPU7RP; + uint32_t RESERVED0[24]; +} stc_mpu_ergrp_bit_t; + +typedef struct +{ + __IO uint32_t EMPUBRP; + __IO uint32_t EMPUBWP; + __IO uint32_t EMPUACT0; + __IO uint32_t EMPUACT1; + uint32_t RESERVED0[3]; + __IO uint32_t EMPUE; + uint32_t RESERVED1[24]; +} stc_mpu_ecr_bit_t; + +typedef struct +{ + __IO uint32_t OTSST; + __IO uint32_t OTSCK; + __IO uint32_t OTSIE; + __IO uint32_t TSSTP; + uint32_t RESERVED0[12]; +} stc_ots_ctl_bit_t; + +typedef struct +{ + __IO uint32_t TSOFS0; + __IO uint32_t TSOFS1; + __IO uint32_t TSOFS2; + __IO uint32_t TSOFS3; + __IO uint32_t TSOFS4; + __IO uint32_t TSOFS5; + __IO uint32_t TSOFS6; + __IO uint32_t TSOFS7; + __IO uint32_t TSSLP0; + __IO uint32_t TSSLP1; + __IO uint32_t TSSLP2; + __IO uint32_t TSSLP3; + __IO uint32_t TSSLP4; + __IO uint32_t TSSLP5; + __IO uint32_t TSSLP6; + __IO uint32_t TSSLP7; + __IO uint32_t TSSLP8; + __IO uint32_t TSSLP9; + __IO uint32_t TSSLP10; + __IO uint32_t TSSLP11; + __IO uint32_t TSSLP12; + __IO uint32_t TSSLP13; + __IO uint32_t TSSLP14; + __IO uint32_t TSSLP15; + __IO uint32_t TSSLP16; + __IO uint32_t TSSLP17; + __IO uint32_t TSSLP18; + __IO uint32_t TSSLP19; + __IO uint32_t TSSLP20; + __IO uint32_t TSSLP21; + __IO uint32_t TSSLP22; + __IO uint32_t TSSLP23; +} stc_ots_lpr_bit_t; + +typedef struct +{ + __IO uint32_t USBFS_DFB; + __IO uint32_t USBFS_SOFEN; + uint32_t RESERVED0[6]; + __IO uint32_t USBHS_DFB; + __IO uint32_t USBHS_SOFEN; + __IO uint32_t USBHS_FSPHYE; + uint32_t RESERVED1[5]; + __IO uint32_t USBFS_NFS0; + __IO uint32_t USBFS_NFS1; + __IO uint32_t USBFS_NFE; + uint32_t RESERVED2[5]; + __IO uint32_t USBHS_NFS0; + __IO uint32_t USBHS_NFS1; + __IO uint32_t USBHS_NFE; + uint32_t RESERVED3[5]; +} stc_peric_usb_syctlreg_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t SELMMC1; + uint32_t RESERVED1[1]; + __IO uint32_t SELMMC2; + uint32_t RESERVED2[28]; +} stc_peric_sdioc_syctlreg_bit_t; + +typedef struct +{ + __IO uint32_t OPO; + uint32_t RESERVED0[31]; +} stc_peric_nfc_syctlreg_bit_t; + +typedef struct +{ + __IO uint32_t DMCEN; + __IO uint32_t SMCEN; + __IO uint32_t NFCEN; + uint32_t RESERVED0[29]; +} stc_peric_exmc_enar_bit_t; + +typedef struct +{ + __IO uint32_t CAN1FDE; + __IO uint32_t CAN2FDE; + uint32_t RESERVED0[30]; +} stc_peric_can_syctlreg_bit_t; + +typedef struct +{ + __IO uint32_t NFS0; + __IO uint32_t NFS1; + __IO uint32_t NFE; + uint32_t RESERVED0[29]; +} stc_peric_usart1_nfc_bit_t; + +typedef struct +{ + __IO uint32_t CHIPBUSY0; + __IO uint32_t CHIPBUSY1; + __IO uint32_t CHIPBUSY2; + __IO uint32_t CHIPBUSY3; + __IO uint32_t CHIPBUSY4; + __IO uint32_t CHIPBUSY5; + __IO uint32_t CHIPBUSY6; + __IO uint32_t CHIPBUSY7; + __IO uint32_t PECC; + uint32_t RESERVED0[23]; +} stc_peric_nfc_systatreg_bit_t; + +typedef struct +{ + __IO uint32_t SRAMH; + uint32_t RESERVED0[3]; + __IO uint32_t SRAM1; + __IO uint32_t SRAM2; + __IO uint32_t SRAM3; + __IO uint32_t SRAM4; + uint32_t RESERVED1[2]; + __IO uint32_t SRAMB; + uint32_t RESERVED2[2]; + __IO uint32_t KEY; + __IO uint32_t DMA1; + __IO uint32_t DMA2; + __IO uint32_t FCM; + __IO uint32_t AOS; + __IO uint32_t CTC; + __IO uint32_t CORDIC; + __IO uint32_t AES; + __IO uint32_t HASH; + __IO uint32_t TRNG; + __IO uint32_t CRC; + __IO uint32_t DCU1; + __IO uint32_t DCU2; + __IO uint32_t DCU3; + __IO uint32_t DCU4; + __IO uint32_t DCU5; + __IO uint32_t DCU6; + __IO uint32_t DCU7; + __IO uint32_t DCU8; +} stc_pwc_fcg0_bit_t; + +typedef struct +{ + __IO uint32_t CAN1; + __IO uint32_t CAN2; + __IO uint32_t ETHER; + __IO uint32_t QSPI; + __IO uint32_t IIC1; + __IO uint32_t IIC2; + __IO uint32_t IIC3; + __IO uint32_t IIC4; + __IO uint32_t IIC5; + __IO uint32_t IIC6; + __IO uint32_t SDIOC1; + __IO uint32_t SDIOC2; + __IO uint32_t I2S1; + __IO uint32_t I2S2; + __IO uint32_t I2S3; + __IO uint32_t I2S4; + __IO uint32_t SPI1; + __IO uint32_t SPI2; + __IO uint32_t SPI3; + __IO uint32_t SPI4; + __IO uint32_t SPI5; + __IO uint32_t SPI6; + __IO uint32_t USBFS; + __IO uint32_t USBHS; + __IO uint32_t FMAC1; + __IO uint32_t FMAC2; + __IO uint32_t FMAC3; + __IO uint32_t FMAC4; + uint32_t RESERVED0[4]; +} stc_pwc_fcg1_bit_t; + +typedef struct +{ + __IO uint32_t TMR6_1; + __IO uint32_t TMR6_2; + __IO uint32_t TMR6_3; + __IO uint32_t TMR6_4; + __IO uint32_t TMR6_5; + __IO uint32_t TMR6_6; + __IO uint32_t TMR6_7; + __IO uint32_t TMR6_8; + __IO uint32_t TMR4_1; + __IO uint32_t TMR4_2; + __IO uint32_t TMR4_3; + __IO uint32_t HRPWM; + __IO uint32_t TMR0_1; + __IO uint32_t TMR0_2; + uint32_t RESERVED0[1]; + __IO uint32_t EMB; + __IO uint32_t TMR2_1; + __IO uint32_t TMR2_2; + __IO uint32_t TMR2_3; + __IO uint32_t TMR2_4; + __IO uint32_t TMRA_1; + __IO uint32_t TMRA_2; + __IO uint32_t TMRA_3; + __IO uint32_t TMRA_4; + __IO uint32_t TMRA_5; + __IO uint32_t TMRA_6; + __IO uint32_t TMRA_7; + __IO uint32_t TMRA_8; + __IO uint32_t TMRA_9; + __IO uint32_t TMRA_10; + __IO uint32_t TMRA_11; + __IO uint32_t TMRA_12; +} stc_pwc_fcg2_bit_t; + +typedef struct +{ + __IO uint32_t ADC1; + __IO uint32_t ADC2; + __IO uint32_t ADC3; + __IO uint32_t CMBIAS; + __IO uint32_t DAC1; + __IO uint32_t DAC2; + uint32_t RESERVED0[2]; + __IO uint32_t CMP1; + __IO uint32_t CMP2; + uint32_t RESERVED1[2]; + __IO uint32_t OTS; + uint32_t RESERVED2[2]; + __IO uint32_t DVP; + __IO uint32_t SMC; + __IO uint32_t DMC; + __IO uint32_t NFC; + uint32_t RESERVED3[1]; + __IO uint32_t USART1; + __IO uint32_t USART2; + __IO uint32_t USART3; + __IO uint32_t USART4; + __IO uint32_t USART5; + __IO uint32_t USART6; + __IO uint32_t USART7; + __IO uint32_t USART8; + __IO uint32_t USART9; + __IO uint32_t USART10; + uint32_t RESERVED4[2]; +} stc_pwc_fcg3_bit_t; + +typedef struct +{ + __IO uint32_t PRT0; + uint32_t RESERVED0[31]; +} stc_pwc_fcg0pc_bit_t; + +typedef struct +{ + __IO uint32_t VBTRSD; + __IO uint32_t RAMVALID; + __IO uint32_t RAMPDF; + __IO uint32_t VBATDIVMONE; + uint32_t RESERVED0[3]; + __IO uint32_t CSDIS; +} stc_pwc_vbatcr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_pwc_wktc0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_pwc_wktc1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[4]; + __IO uint32_t WKOVF; + __IO uint32_t WKCKS0; + __IO uint32_t WKCKS1; + __IO uint32_t WKTCE; +} stc_pwc_wktc2_bit_t; + +typedef struct +{ + __IO uint32_t PDMDS0; + __IO uint32_t PDMDS1; + uint32_t RESERVED0[2]; + __IO uint32_t IORTN0; + __IO uint32_t IORTN1; + uint32_t RESERVED1[1]; + __IO uint32_t PWDN; +} stc_pwc_pwrc0_bit_t; + +typedef struct +{ + __IO uint32_t VPLLSD0; + __IO uint32_t VPLLSD1; + __IO uint32_t VHRCSD; + __IO uint32_t PDTS; + uint32_t RESERVED0[2]; + __IO uint32_t STPDAS0; + __IO uint32_t STPDAS1; +} stc_pwc_pwrc1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[4]; + __IO uint32_t DVS0; + __IO uint32_t DVS1; + uint32_t RESERVED1[2]; +} stc_pwc_pwrc2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_pwc_pwrc3_bit_t; + +typedef struct +{ + __IO uint32_t VBATREFSEL; + __IO uint32_t VBATME; + uint32_t RESERVED0[2]; + __IO uint32_t VBATMON; + uint32_t RESERVED1[1]; + __IO uint32_t ADBUFS; + __IO uint32_t ADBUFE; +} stc_pwc_pwrc4_bit_t; + +typedef struct +{ + __IO uint32_t EXVCCINEN; + uint32_t RESERVED0[4]; + __IO uint32_t PVD1EN; + __IO uint32_t PVD2EN; + uint32_t RESERVED1[1]; +} stc_pwc_pvdcr0_bit_t; + +typedef struct +{ + __IO uint32_t PVD1IRE; + __IO uint32_t PVD1IRS; + __IO uint32_t PVD1CMPOE; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2IRE; + __IO uint32_t PVD2IRS; + __IO uint32_t PVD2CMPOE; + uint32_t RESERVED1[1]; +} stc_pwc_pvdcr1_bit_t; + +typedef struct +{ + __IO uint32_t PVD1NFDIS; + __IO uint32_t PVD1NFCKS0; + __IO uint32_t PVD1NFCKS1; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2NFDIS; + __IO uint32_t PVD2NFCKS0; + __IO uint32_t PVD2NFCKS1; + uint32_t RESERVED1[1]; +} stc_pwc_pvdfcr_bit_t; + +typedef struct +{ + __IO uint32_t PVD1LVL0; + __IO uint32_t PVD1LVL1; + __IO uint32_t PVD1LVL2; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2LVL0; + __IO uint32_t PVD2LVL1; + __IO uint32_t PVD2LVL2; + uint32_t RESERVED1[1]; +} stc_pwc_pvdlcr_bit_t; + +typedef struct +{ + __IO uint32_t WKE0_0; + __IO uint32_t WKE0_1; + __IO uint32_t WKE0_2; + __IO uint32_t WKE0_3; + __IO uint32_t WKE1_0; + __IO uint32_t WKE1_1; + __IO uint32_t WKE1_2; + __IO uint32_t WKE1_3; +} stc_pwc_pdwke0_bit_t; + +typedef struct +{ + __IO uint32_t WKE2_0; + __IO uint32_t WKE2_1; + __IO uint32_t WKE2_2; + __IO uint32_t WKE2_3; + __IO uint32_t WKE3_0; + __IO uint32_t WKE3_1; + __IO uint32_t WKE3_2; + __IO uint32_t WKE3_3; +} stc_pwc_pdwke1_bit_t; + +typedef struct +{ + __IO uint32_t VD1WKE; + __IO uint32_t VD2WKE; + uint32_t RESERVED0[2]; + __IO uint32_t RTCPRDWKE; + __IO uint32_t RTCALMWKE; + __IO uint32_t XTAL32ERWKE; + __IO uint32_t WKTMWKE; +} stc_pwc_pdwke2_bit_t; + +typedef struct +{ + __IO uint32_t WK0EGS; + __IO uint32_t WK1EGS; + __IO uint32_t WK2EGS; + __IO uint32_t WK3EGS; + __IO uint32_t VD1EGS; + __IO uint32_t VD2EGS; + uint32_t RESERVED0[2]; +} stc_pwc_pdwkes_bit_t; + +typedef struct +{ + __IO uint32_t PTWK0F; + __IO uint32_t PTWK1F; + __IO uint32_t PTWK2F; + __IO uint32_t PTWK3F; + __IO uint32_t VD1WKF; + __IO uint32_t VD2WKF; + uint32_t RESERVED0[2]; +} stc_pwc_pdwkf0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[3]; + __IO uint32_t RXD0WKF; + __IO uint32_t RTCPRDWKF; + __IO uint32_t RTCALMWKF; + __IO uint32_t XTAL32ERWKF; + __IO uint32_t WKTMWKF; +} stc_pwc_pdwkf1_bit_t; + +typedef struct +{ + __IO uint32_t RAMPDC0; + __IO uint32_t RAMPDC1; + __IO uint32_t RAMPDC2; + __IO uint32_t RAMPDC3; + __IO uint32_t RAMPDC4; + __IO uint32_t RAMPDC5; + __IO uint32_t RAMPDC6; + __IO uint32_t RAMPDC7; + __IO uint32_t RAMPDC8; + __IO uint32_t RAMPDC9; + __IO uint32_t RAMPDC10; + uint32_t RESERVED0[21]; +} stc_pwc_rampc0_bit_t; + +typedef struct +{ + __IO uint32_t RAMOPM0; + __IO uint32_t RAMOPM1; + __IO uint32_t RAMOPM2; + __IO uint32_t RAMOPM3; + __IO uint32_t RAMOPM4; + __IO uint32_t RAMOPM5; + __IO uint32_t RAMOPM6; + __IO uint32_t RAMOPM7; + __IO uint32_t RAMOPM8; + __IO uint32_t RAMOPM9; + __IO uint32_t RAMOPM10; + __IO uint32_t RAMOPM11; + __IO uint32_t RAMOPM12; + __IO uint32_t RAMOPM13; + __IO uint32_t RAMOPM14; + __IO uint32_t RAMOPM15; + uint32_t RESERVED0[16]; +} stc_pwc_ramopm_bit_t; + +typedef struct +{ + __IO uint32_t PRAMPDC0; + __IO uint32_t PRAMPDC1; + __IO uint32_t PRAMPDC2; + __IO uint32_t PRAMPDC3; + __IO uint32_t PRAMPDC4; + __IO uint32_t PRAMPDC5; + __IO uint32_t PRAMPDC6; + __IO uint32_t PRAMPDC7; + __IO uint32_t PRAMPDC8; + __IO uint32_t PRAMPDC9; + uint32_t RESERVED0[22]; +} stc_pwc_pramlpc_bit_t; + +typedef struct +{ + __IO uint32_t PVD1NMIS; + __IO uint32_t PVD1EDGS0; + __IO uint32_t PVD1EDGS1; + uint32_t RESERVED0[1]; + __IO uint32_t PVD2NMIS; + __IO uint32_t PVD2EDGS0; + __IO uint32_t PVD2EDGS1; + uint32_t RESERVED1[1]; +} stc_pwc_pvdicr_bit_t; + +typedef struct +{ + __IO uint32_t PVD1MON; + __IO uint32_t PVD1DETFLG; + uint32_t RESERVED0[2]; + __IO uint32_t PVD2MON; + __IO uint32_t PVD2DETFLG; + uint32_t RESERVED1[2]; +} stc_pwc_pvddsr_bit_t; + +typedef struct +{ + __IO uint32_t FLNWT; + __IO uint32_t CKSMRC; + uint32_t RESERVED0[12]; + __IO uint32_t EXBUSOE; + __IO uint32_t STOP; +} stc_pwc_stpmcr_bit_t; + +typedef struct +{ + __IO uint32_t FPRCB0; + __IO uint32_t FPRCB1; + __IO uint32_t FPRCB2; + __IO uint32_t FPRCB3; + uint32_t RESERVED0[12]; +} stc_pwc_fprc_bit_t; + +typedef struct +{ + uint32_t RESERVED0[5]; + __IO uint32_t LKUPREN; + uint32_t RESERVED1[2]; +} stc_rmu_prstcr0_bit_t; + +typedef struct +{ + __IO uint32_t PORF; + __IO uint32_t PINRF; + __IO uint32_t BORF; + __IO uint32_t PVD1RF; + __IO uint32_t PVD2RF; + __IO uint32_t WDRF; + __IO uint32_t SWDRF; + __IO uint32_t PDRF; + __IO uint32_t SWRF; + __IO uint32_t MPUERF; + __IO uint32_t RAPERF; + __IO uint32_t RAECRF; + __IO uint32_t CKFERF; + __IO uint32_t XTALERF; + __IO uint32_t LKUPRF; + uint32_t RESERVED0[15]; + __IO uint32_t MULTIRF; + __IO uint32_t CLRF; +} stc_rmu_rstf0_bit_t; + +typedef struct +{ + __IO uint32_t RESET; + uint32_t RESERVED0[7]; +} stc_rtc_cr0_bit_t; + +typedef struct +{ + __IO uint32_t PRDS0; + __IO uint32_t PRDS1; + __IO uint32_t PRDS2; + __IO uint32_t AMPM; + uint32_t RESERVED0[1]; + __IO uint32_t ONEHZOE; + __IO uint32_t ONEHZSEL; + __IO uint32_t START; +} stc_rtc_cr1_bit_t; + +typedef struct +{ + __IO uint32_t RWREQ; + __IO uint32_t RWEN; + __IO uint32_t PRDF; + __IO uint32_t ALMF; + uint32_t RESERVED0[1]; + __IO uint32_t PRDIE; + __IO uint32_t ALMIE; + __IO uint32_t ALME; +} stc_rtc_cr2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[4]; + __IO uint32_t LRCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RCKSEL; +} stc_rtc_cr3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_sec_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_min_bit_t; + +typedef struct +{ + __IO uint32_t HOURU0; + __IO uint32_t HOURU1; + __IO uint32_t HOURU2; + __IO uint32_t HOURU3; + __IO uint32_t HOURD0; + __IO uint32_t HOURD1; + uint32_t RESERVED0[2]; +} stc_rtc_hour_bit_t; + +typedef struct +{ + __IO uint32_t WEEK0; + __IO uint32_t WEEK1; + __IO uint32_t WEEK2; + uint32_t RESERVED0[5]; +} stc_rtc_week_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_day_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_mon_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_year_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_almmin_bit_t; + +typedef struct +{ + __IO uint32_t ALMHOURU0; + __IO uint32_t ALMHOURU1; + __IO uint32_t ALMHOURU2; + __IO uint32_t ALMHOURU3; + __IO uint32_t ALMHOURD0; + __IO uint32_t ALMHOURD1; + uint32_t RESERVED0[2]; +} stc_rtc_almhour_bit_t; + +typedef struct +{ + __IO uint32_t ALMWEEK0; + __IO uint32_t ALMWEEK1; + __IO uint32_t ALMWEEK2; + __IO uint32_t ALMWEEK3; + __IO uint32_t ALMWEEK4; + __IO uint32_t ALMWEEK5; + __IO uint32_t ALMWEEK6; + uint32_t RESERVED0[1]; +} stc_rtc_almweek_bit_t; + +typedef struct +{ + __IO uint32_t COMP8; + uint32_t RESERVED0[6]; + __IO uint32_t COMPEN; +} stc_rtc_errcrh_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_errcrl_bit_t; + +typedef struct +{ + __IO uint32_t TPCT00; + __IO uint32_t TPCT01; + __IO uint32_t TPNF00; + __IO uint32_t TPNF01; + __IO uint32_t TPRSTE0; + __IO uint32_t TPIE0; + __IO uint32_t TSTPE0; + __IO uint32_t TPEN0; +} stc_rtc_tpcr0_bit_t; + +typedef struct +{ + __IO uint32_t TPCT10; + __IO uint32_t TPCT11; + __IO uint32_t TPNF10; + __IO uint32_t TPNF11; + __IO uint32_t TPRSTE1; + __IO uint32_t TPIE1; + __IO uint32_t TSTPE1; + __IO uint32_t TPEN1; +} stc_rtc_tpcr1_bit_t; + +typedef struct +{ + __IO uint32_t TPF0; + __IO uint32_t TPF1; + __IO uint32_t TPOVF; + uint32_t RESERVED0[5]; +} stc_rtc_tpsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_sectp_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_mintp_bit_t; + +typedef struct +{ + __IO uint32_t HOURTPU0; + __IO uint32_t HOURTPU1; + __IO uint32_t HOURTPU2; + __IO uint32_t HOURTPU3; + __IO uint32_t HOURTPD0; + __IO uint32_t HOURTPD1; + uint32_t RESERVED0[2]; +} stc_rtc_hourtp_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_daytp_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; +} stc_rtc_montp_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; +} stc_sdioc_blksize_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t BCE; + __IO uint32_t ATCEN0; + __IO uint32_t ATCEN1; + __IO uint32_t DDIR; + __IO uint32_t MULB; + uint32_t RESERVED1[10]; +} stc_sdioc_transmode_bit_t; + +typedef struct +{ + __IO uint32_t RESTYP0; + __IO uint32_t RESTYP1; + uint32_t RESERVED0[1]; + __IO uint32_t CCE; + __IO uint32_t ICE; + __IO uint32_t DAT; + __IO uint32_t TYP0; + __IO uint32_t TYP1; + __IO uint32_t IDX0; + __IO uint32_t IDX1; + __IO uint32_t IDX2; + __IO uint32_t IDX3; + __IO uint32_t IDX4; + __IO uint32_t IDX5; + uint32_t RESERVED1[2]; +} stc_sdioc_cmd_bit_t; + +typedef struct +{ + __IO uint32_t CIC; + __IO uint32_t CID; + __IO uint32_t DA; + uint32_t RESERVED0[5]; + __IO uint32_t WTA; + __IO uint32_t RTA; + __IO uint32_t BWE; + __IO uint32_t BRE; + uint32_t RESERVED1[4]; + __IO uint32_t CIN; + __IO uint32_t CSS; + __IO uint32_t CDL; + __IO uint32_t WPL; + __IO uint32_t DATL0; + __IO uint32_t DATL1; + __IO uint32_t DATL2; + __IO uint32_t DATL3; + __IO uint32_t CMDL; + uint32_t RESERVED2[7]; +} stc_sdioc_pstat_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t DW; + __IO uint32_t HSEN; + uint32_t RESERVED1[2]; + __IO uint32_t EXDW; + __IO uint32_t CDTL; + __IO uint32_t CDSS; +} stc_sdioc_hostcon_bit_t; + +typedef struct +{ + __IO uint32_t PWON; + uint32_t RESERVED0[7]; +} stc_sdioc_pwrcon_bit_t; + +typedef struct +{ + __IO uint32_t SABGR; + __IO uint32_t CR; + __IO uint32_t RWC; + __IO uint32_t IABG; + uint32_t RESERVED0[4]; +} stc_sdioc_blkgpcon_bit_t; + +typedef struct +{ + __IO uint32_t ICE; + uint32_t RESERVED0[1]; + __IO uint32_t CE; + uint32_t RESERVED1[5]; + __IO uint32_t FS0; + __IO uint32_t FS1; + __IO uint32_t FS2; + __IO uint32_t FS3; + __IO uint32_t FS4; + __IO uint32_t FS5; + __IO uint32_t FS6; + __IO uint32_t FS7; +} stc_sdioc_clkcon_bit_t; + +typedef struct +{ + __IO uint32_t DTO0; + __IO uint32_t DTO1; + __IO uint32_t DTO2; + __IO uint32_t DTO3; + uint32_t RESERVED0[4]; +} stc_sdioc_toutcon_bit_t; + +typedef struct +{ + __IO uint32_t RSTA; + __IO uint32_t RSTC; + __IO uint32_t RSTD; + uint32_t RESERVED0[5]; +} stc_sdioc_sftrst_bit_t; + +typedef struct +{ + __IO uint32_t CC; + __IO uint32_t TC; + __IO uint32_t BGE; + uint32_t RESERVED0[1]; + __IO uint32_t BWR; + __IO uint32_t BRR; + __IO uint32_t CIST; + __IO uint32_t CRM; + __IO uint32_t CINT; + uint32_t RESERVED1[6]; + __IO uint32_t EI; +} stc_sdioc_norintst_bit_t; + +typedef struct +{ + __IO uint32_t CTOE; + __IO uint32_t CCE; + __IO uint32_t CEBE; + __IO uint32_t CIE; + __IO uint32_t DTOE; + __IO uint32_t DCE; + __IO uint32_t DEBE; + uint32_t RESERVED0[1]; + __IO uint32_t ACE; + uint32_t RESERVED1[7]; +} stc_sdioc_errintst_bit_t; + +typedef struct +{ + __IO uint32_t CCEN; + __IO uint32_t TCEN; + __IO uint32_t BGEEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWREN; + __IO uint32_t BRREN; + __IO uint32_t CISTEN; + __IO uint32_t CRMEN; + __IO uint32_t CINTEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsten_bit_t; + +typedef struct +{ + __IO uint32_t CTOEEN; + __IO uint32_t CCEEN; + __IO uint32_t CEBEEN; + __IO uint32_t CIEEN; + __IO uint32_t DTOEEN; + __IO uint32_t DCEEN; + __IO uint32_t DEBEEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACEEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsten_bit_t; + +typedef struct +{ + __IO uint32_t CCSEN; + __IO uint32_t TCSEN; + __IO uint32_t BGESEN; + uint32_t RESERVED0[1]; + __IO uint32_t BWRSEN; + __IO uint32_t BRRSEN; + __IO uint32_t CISTSEN; + __IO uint32_t CRMSEN; + __IO uint32_t CINTSEN; + uint32_t RESERVED1[7]; +} stc_sdioc_norintsgen_bit_t; + +typedef struct +{ + __IO uint32_t CTOESEN; + __IO uint32_t CCESEN; + __IO uint32_t CEBESEN; + __IO uint32_t CIESEN; + __IO uint32_t DTOESEN; + __IO uint32_t DCESEN; + __IO uint32_t DEBESEN; + uint32_t RESERVED0[1]; + __IO uint32_t ACESEN; + uint32_t RESERVED1[7]; +} stc_sdioc_errintsgen_bit_t; + +typedef struct +{ + __IO uint32_t NE; + __IO uint32_t TOE; + __IO uint32_t CE; + __IO uint32_t EBE; + __IO uint32_t IE; + uint32_t RESERVED0[2]; + __IO uint32_t CMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_atcerrst_bit_t; + +typedef struct +{ + __IO uint32_t FNE; + __IO uint32_t FTOE; + __IO uint32_t FCE; + __IO uint32_t FEBE; + __IO uint32_t FIE; + uint32_t RESERVED0[2]; + __IO uint32_t FCMDE; + uint32_t RESERVED1[8]; +} stc_sdioc_fea_bit_t; + +typedef struct +{ + __IO uint32_t FCTOE; + __IO uint32_t FCCE; + __IO uint32_t FCEBE; + __IO uint32_t FCIE; + __IO uint32_t FDTOE; + __IO uint32_t FDCE; + __IO uint32_t FDEBE; + uint32_t RESERVED0[1]; + __IO uint32_t FACE; + uint32_t RESERVED1[7]; +} stc_sdioc_fee_bit_t; + +typedef struct +{ + __IO uint32_t SPIMDS; + __IO uint32_t TXMDS; + uint32_t RESERVED0[1]; + __IO uint32_t MSTR; + __IO uint32_t SPLPBK; + __IO uint32_t SPLPBK2; + __IO uint32_t SPE; + __IO uint32_t CSUSPE; + __IO uint32_t EIE; + __IO uint32_t TXIE; + __IO uint32_t RXIE; + __IO uint32_t IDIE; + __IO uint32_t MODFE; + __IO uint32_t PATE; + __IO uint32_t PAOE; + __IO uint32_t PAE; + uint32_t RESERVED1[16]; +} stc_spi_cr1_bit_t; + +typedef struct +{ + __IO uint32_t FTHLV0; + __IO uint32_t FTHLV1; + uint32_t RESERVED0[4]; + __IO uint32_t SPRDTD; + uint32_t RESERVED1[1]; + __IO uint32_t SS0PV; + __IO uint32_t SS1PV; + __IO uint32_t SS2PV; + __IO uint32_t SS3PV; + uint32_t RESERVED2[8]; + __IO uint32_t MSSI0; + __IO uint32_t MSSI1; + __IO uint32_t MSSI2; + uint32_t RESERVED3[1]; + __IO uint32_t MSSDL0; + __IO uint32_t MSSDL1; + __IO uint32_t MSSDL2; + uint32_t RESERVED4[1]; + __IO uint32_t MIDI0; + __IO uint32_t MIDI1; + __IO uint32_t MIDI2; + uint32_t RESERVED5[1]; +} stc_spi_cfg1_bit_t; + +typedef struct +{ + __IO uint32_t OVRERF; + __IO uint32_t IDLNF; + __IO uint32_t MODFERF; + __IO uint32_t PERF; + __IO uint32_t UDRERF; + __IO uint32_t TDEF; + uint32_t RESERVED0[1]; + __IO uint32_t RDFF; + uint32_t RESERVED1[24]; +} stc_spi_sr_bit_t; + +typedef struct +{ + __IO uint32_t CPHA; + __IO uint32_t CPOL; + __IO uint32_t MBR0; + __IO uint32_t MBR1; + __IO uint32_t MBR2; + __IO uint32_t SSA0; + __IO uint32_t SSA1; + __IO uint32_t SSA2; + __IO uint32_t DSIZE0; + __IO uint32_t DSIZE1; + __IO uint32_t DSIZE2; + __IO uint32_t DSIZE3; + __IO uint32_t LSBF; + __IO uint32_t MIDIE; + __IO uint32_t MSSDLE; + __IO uint32_t MSSIE; + uint32_t RESERVED0[16]; +} stc_spi_cfg2_bit_t; + +typedef struct +{ + __IO uint32_t SRAM123RWT0; + __IO uint32_t SRAM123RWT1; + __IO uint32_t SRAM123RWT2; + uint32_t RESERVED0[1]; + __IO uint32_t SRAM123WWT0; + __IO uint32_t SRAM123WWT1; + __IO uint32_t SRAM123WWT2; + uint32_t RESERVED1[1]; + __IO uint32_t SRAM4RWT0; + __IO uint32_t SRAM4RWT1; + __IO uint32_t SRAM4RWT2; + uint32_t RESERVED2[1]; + __IO uint32_t SRAM4WWT0; + __IO uint32_t SRAM4WWT1; + __IO uint32_t SRAM4WWT2; + uint32_t RESERVED3[1]; + __IO uint32_t SRAMHRWT0; + __IO uint32_t SRAMHRWT1; + __IO uint32_t SRAMHRWT2; + uint32_t RESERVED4[1]; + __IO uint32_t SRAMHWWT0; + __IO uint32_t SRAMHWWT1; + __IO uint32_t SRAMHWWT2; + uint32_t RESERVED5[1]; + __IO uint32_t SRAMBRWT0; + __IO uint32_t SRAMBRWT1; + __IO uint32_t SRAMBRWT2; + uint32_t RESERVED6[1]; + __IO uint32_t SRAMBWWT0; + __IO uint32_t SRAMBWWT1; + __IO uint32_t SRAMBWWT2; + uint32_t RESERVED7[1]; +} stc_sramc_wtcr_bit_t; + +typedef struct +{ + __IO uint32_t WTPRC; + __IO uint32_t WTPRKW0; + __IO uint32_t WTPRKW1; + __IO uint32_t WTPRKW2; + __IO uint32_t WTPRKW3; + __IO uint32_t WTPRKW4; + __IO uint32_t WTPRKW5; + __IO uint32_t WTPRKW6; + uint32_t RESERVED0[24]; +} stc_sramc_wtpr_bit_t; + +typedef struct +{ + __IO uint32_t PYOAD; + uint32_t RESERVED0[15]; + __IO uint32_t ECCOAD; + __IO uint32_t BECCOAD; + uint32_t RESERVED1[6]; + __IO uint32_t ECCMOD0; + __IO uint32_t ECCMOD1; + __IO uint32_t BECCMOD0; + __IO uint32_t BECCMOD1; + uint32_t RESERVED2[4]; +} stc_sramc_ckcr_bit_t; + +typedef struct +{ + __IO uint32_t CKPRC; + __IO uint32_t CKPRKW0; + __IO uint32_t CKPRKW1; + __IO uint32_t CKPRKW2; + __IO uint32_t CKPRKW3; + __IO uint32_t CKPRKW4; + __IO uint32_t CKPRKW5; + __IO uint32_t CKPRKW6; + uint32_t RESERVED0[24]; +} stc_sramc_ckpr_bit_t; + +typedef struct +{ + __IO uint32_t SRAM1_PYERR; + __IO uint32_t SRAM2_PYERR; + __IO uint32_t SRAM3_PYERR; + __IO uint32_t SRAMH_PYERR; + __IO uint32_t SRAM4_1ERR; + __IO uint32_t SRAM4_2ERR; + __IO uint32_t SRAMB_1ERR; + __IO uint32_t SRAMB_2ERR; + __IO uint32_t CACHE_PYERR; + uint32_t RESERVED0[23]; +} stc_sramc_cksr_bit_t; + +typedef struct +{ + __IO uint32_t PERI0; + __IO uint32_t PERI1; + uint32_t RESERVED0[2]; + __IO uint32_t CKS0; + __IO uint32_t CKS1; + __IO uint32_t CKS2; + __IO uint32_t CKS3; + __IO uint32_t WDPT0; + __IO uint32_t WDPT1; + __IO uint32_t WDPT2; + __IO uint32_t WDPT3; + uint32_t RESERVED1[4]; + __IO uint32_t SLPOFF; + uint32_t RESERVED2[14]; + __IO uint32_t ITS; +} stc_swdt_cr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_swdt_sr_bit_t; + +typedef struct +{ + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + __IO uint32_t INTENA; + uint32_t RESERVED0[5]; + __IO uint32_t SYNSA; + __IO uint32_t SYNCLKA; + __IO uint32_t ASYNCLKA; + uint32_t RESERVED1[1]; + __IO uint32_t HSTAA; + __IO uint32_t HSTPA; + __IO uint32_t HCLEA; + __IO uint32_t HICPA; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + __IO uint32_t INTENB; + uint32_t RESERVED2[5]; + __IO uint32_t SYNSB; + __IO uint32_t SYNCLKB; + __IO uint32_t ASYNCLKB; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB; + __IO uint32_t HSTPB; + __IO uint32_t HCLEB; + __IO uint32_t HICPB; +} stc_tmr0_bconr_bit_t; + +typedef struct +{ + __IO uint32_t CMFA; + uint32_t RESERVED0[15]; + __IO uint32_t CMFB; + uint32_t RESERVED1[15]; +} stc_tmr0_stflr_bit_t; + +typedef struct +{ + __IO uint32_t CNTA0; + __IO uint32_t CNTA1; + __IO uint32_t CNTA2; + __IO uint32_t CNTA3; + __IO uint32_t CNTA4; + __IO uint32_t CNTA5; + __IO uint32_t CNTA6; + __IO uint32_t CNTA7; + __IO uint32_t CNTA8; + __IO uint32_t CNTA9; + __IO uint32_t CNTA10; + __IO uint32_t CNTA11; + __IO uint32_t CNTA12; + __IO uint32_t CNTA13; + __IO uint32_t CNTA14; + __IO uint32_t CNTA15; + uint32_t RESERVED0[16]; +} stc_tmr2_cntar_bit_t; + +typedef struct +{ + __IO uint32_t CNTB0; + __IO uint32_t CNTB1; + __IO uint32_t CNTB2; + __IO uint32_t CNTB3; + __IO uint32_t CNTB4; + __IO uint32_t CNTB5; + __IO uint32_t CNTB6; + __IO uint32_t CNTB7; + __IO uint32_t CNTB8; + __IO uint32_t CNTB9; + __IO uint32_t CNTB10; + __IO uint32_t CNTB11; + __IO uint32_t CNTB12; + __IO uint32_t CNTB13; + __IO uint32_t CNTB14; + __IO uint32_t CNTB15; + uint32_t RESERVED0[16]; +} stc_tmr2_cntbr_bit_t; + +typedef struct +{ + __IO uint32_t CMPA0; + __IO uint32_t CMPA1; + __IO uint32_t CMPA2; + __IO uint32_t CMPA3; + __IO uint32_t CMPA4; + __IO uint32_t CMPA5; + __IO uint32_t CMPA6; + __IO uint32_t CMPA7; + __IO uint32_t CMPA8; + __IO uint32_t CMPA9; + __IO uint32_t CMPA10; + __IO uint32_t CMPA11; + __IO uint32_t CMPA12; + __IO uint32_t CMPA13; + __IO uint32_t CMPA14; + __IO uint32_t CMPA15; + uint32_t RESERVED0[16]; +} stc_tmr2_cmpar_bit_t; + +typedef struct +{ + __IO uint32_t CMPB0; + __IO uint32_t CMPB1; + __IO uint32_t CMPB2; + __IO uint32_t CMPB3; + __IO uint32_t CMPB4; + __IO uint32_t CMPB5; + __IO uint32_t CMPB6; + __IO uint32_t CMPB7; + __IO uint32_t CMPB8; + __IO uint32_t CMPB9; + __IO uint32_t CMPB10; + __IO uint32_t CMPB11; + __IO uint32_t CMPB12; + __IO uint32_t CMPB13; + __IO uint32_t CMPB14; + __IO uint32_t CMPB15; + uint32_t RESERVED0[16]; +} stc_tmr2_cmpbr_bit_t; + +typedef struct +{ + __IO uint32_t CSTA; + __IO uint32_t CAPMDA; + uint32_t RESERVED0[1]; + __IO uint32_t SYNSA; + __IO uint32_t CKDIVA0; + __IO uint32_t CKDIVA1; + __IO uint32_t CKDIVA2; + __IO uint32_t CKDIVA3; + __IO uint32_t SYNCLKA0; + __IO uint32_t SYNCLKA1; + __IO uint32_t ASYNCLKA0; + __IO uint32_t ASYNCLKA1; + __IO uint32_t SYNCLKAT0; + __IO uint32_t SYNCLKAT1; + uint32_t RESERVED1[2]; + __IO uint32_t CSTB; + __IO uint32_t CAPMDB; + uint32_t RESERVED2[1]; + __IO uint32_t SYNSB; + __IO uint32_t CKDIVB0; + __IO uint32_t CKDIVB1; + __IO uint32_t CKDIVB2; + __IO uint32_t CKDIVB3; + __IO uint32_t SYNCLKB0; + __IO uint32_t SYNCLKB1; + __IO uint32_t ASYNCLKB0; + __IO uint32_t ASYNCLKB1; + __IO uint32_t SYNCLKBT0; + __IO uint32_t SYNCLKBT1; + uint32_t RESERVED3[2]; +} stc_tmr2_bconr_bit_t; + +typedef struct +{ + __IO uint32_t CMENA; + __IO uint32_t OVENA; + uint32_t RESERVED0[14]; + __IO uint32_t CMENB; + __IO uint32_t OVENB; + uint32_t RESERVED1[6]; + __IO uint32_t RESV; + uint32_t RESERVED2[7]; +} stc_tmr2_iconr_bit_t; + +typedef struct +{ + __IO uint32_t STACA0; + __IO uint32_t STACA1; + __IO uint32_t STPCA0; + __IO uint32_t STPCA1; + __IO uint32_t CMPCA0; + __IO uint32_t CMPCA1; + uint32_t RESERVED0[2]; + __IO uint32_t OUTENA; + uint32_t RESERVED1[3]; + __IO uint32_t NOFIENA; + __IO uint32_t NOFICKA0; + __IO uint32_t NOFICKA1; + uint32_t RESERVED2[1]; + __IO uint32_t STACB0; + __IO uint32_t STACB1; + __IO uint32_t STPCB0; + __IO uint32_t STPCB1; + __IO uint32_t CMPCB0; + __IO uint32_t CMPCB1; + uint32_t RESERVED3[2]; + __IO uint32_t OUTENB; + uint32_t RESERVED4[3]; + __IO uint32_t NOFIENB; + __IO uint32_t NOFICKB0; + __IO uint32_t NOFICKB1; + uint32_t RESERVED5[1]; +} stc_tmr2_pconr_bit_t; + +typedef struct +{ + __IO uint32_t HSTAA0; + __IO uint32_t HSTAA1; + __IO uint32_t HSTAA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTPA0; + __IO uint32_t HSTPA1; + __IO uint32_t HSTPA2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLEA0; + __IO uint32_t HCLEA1; + __IO uint32_t HCLEA2; + uint32_t RESERVED2[1]; + __IO uint32_t HICPA0; + __IO uint32_t HICPA1; + __IO uint32_t HICPA2; + uint32_t RESERVED3[1]; + __IO uint32_t HSTAB0; + __IO uint32_t HSTAB1; + __IO uint32_t HSTAB2; + uint32_t RESERVED4[1]; + __IO uint32_t HSTPB0; + __IO uint32_t HSTPB1; + __IO uint32_t HSTPB2; + uint32_t RESERVED5[1]; + __IO uint32_t HCLEB0; + __IO uint32_t HCLEB1; + __IO uint32_t HCLEB2; + uint32_t RESERVED6[1]; + __IO uint32_t HICPB0; + __IO uint32_t HICPB1; + __IO uint32_t HICPB2; + uint32_t RESERVED7[1]; +} stc_tmr2_hconr_bit_t; + +typedef struct +{ + __IO uint32_t CMFA; + __IO uint32_t OVFA; + uint32_t RESERVED0[14]; + __IO uint32_t CMFB; + __IO uint32_t OVFB; + uint32_t RESERVED1[6]; + __IO uint32_t RESV; + uint32_t RESERVED2[7]; +} stc_tmr2_stflr_bit_t; + +typedef struct +{ + __IO uint32_t OCEH; + __IO uint32_t OCEL; + __IO uint32_t OCPH; + __IO uint32_t OCPL; + __IO uint32_t OCIEH; + __IO uint32_t OCIEL; + __IO uint32_t OCFH; + __IO uint32_t OCFL; + uint32_t RESERVED0[8]; +} stc_tmr4_ocsr_bit_t; + +typedef struct +{ + __IO uint32_t CHBUFEN0; + __IO uint32_t CHBUFEN1; + __IO uint32_t CLBUFEN0; + __IO uint32_t CLBUFEN1; + __IO uint32_t MHBUFEN0; + __IO uint32_t MHBUFEN1; + __IO uint32_t MLBUFEN0; + __IO uint32_t MLBUFEN1; + __IO uint32_t LMCH; + __IO uint32_t LMCL; + __IO uint32_t LMMH; + __IO uint32_t LMML; + __IO uint32_t MCECH; + __IO uint32_t MCECL; + uint32_t RESERVED0[2]; +} stc_tmr4_ocer_bit_t; + +typedef struct +{ + __IO uint32_t OCFDCH; + __IO uint32_t OCFPKH; + __IO uint32_t OCFUCH; + __IO uint32_t OCFZRH; + __IO uint32_t OPDCH0; + __IO uint32_t OPDCH1; + __IO uint32_t OPPKH0; + __IO uint32_t OPPKH1; + __IO uint32_t OPUCH0; + __IO uint32_t OPUCH1; + __IO uint32_t OPZRH0; + __IO uint32_t OPZRH1; + __IO uint32_t OPNPKH0; + __IO uint32_t OPNPKH1; + __IO uint32_t OPNZRH0; + __IO uint32_t OPNZRH1; +} stc_tmr4_ocmrh_bit_t; + +typedef struct +{ + __IO uint32_t OCFDCL; + __IO uint32_t OCFPKL; + __IO uint32_t OCFUCL; + __IO uint32_t OCFZRL; + __IO uint32_t OPDCL0; + __IO uint32_t OPDCL1; + __IO uint32_t OPPKL0; + __IO uint32_t OPPKL1; + __IO uint32_t OPUCL0; + __IO uint32_t OPUCL1; + __IO uint32_t OPZRL0; + __IO uint32_t OPZRL1; + __IO uint32_t OPNPKL0; + __IO uint32_t OPNPKL1; + __IO uint32_t OPNZRL0; + __IO uint32_t OPNZRL1; + __IO uint32_t EOPNDCL0; + __IO uint32_t EOPNDCL1; + __IO uint32_t EOPNUCL0; + __IO uint32_t EOPNUCL1; + __IO uint32_t EOPDCL0; + __IO uint32_t EOPDCL1; + __IO uint32_t EOPPKL0; + __IO uint32_t EOPPKL1; + __IO uint32_t EOPUCL0; + __IO uint32_t EOPUCL1; + __IO uint32_t EOPZRL0; + __IO uint32_t EOPZRL1; + __IO uint32_t EOPNPKL0; + __IO uint32_t EOPNPKL1; + __IO uint32_t EOPNZRL0; + __IO uint32_t EOPNZRL1; +} stc_tmr4_ocmrl_bit_t; + +typedef struct +{ + __IO uint32_t CKDIV0; + __IO uint32_t CKDIV1; + __IO uint32_t CKDIV2; + __IO uint32_t CKDIV3; + __IO uint32_t CLEAR; + __IO uint32_t MODE; + __IO uint32_t STOP; + __IO uint32_t BUFEN; + __IO uint32_t IRQPEN; + __IO uint32_t IRQPF; + uint32_t RESERVED0[3]; + __IO uint32_t IRQZEN; + __IO uint32_t IRQZF; + __IO uint32_t ECKEN; +} stc_tmr4_ccsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; +} stc_tmr4_cvpr_bit_t; + +typedef struct +{ + __IO uint32_t DIVCK0; + __IO uint32_t DIVCK1; + __IO uint32_t DIVCK2; + uint32_t RESERVED0[1]; + __IO uint32_t PWMMD0; + __IO uint32_t PWMMD1; + __IO uint32_t LVLS0; + __IO uint32_t LVLS1; + uint32_t RESERVED1[8]; +} stc_tmr4_pocr_bit_t; + +typedef struct +{ + __IO uint32_t RTIDU; + __IO uint32_t RTIDV; + __IO uint32_t RTIDW; + uint32_t RESERVED0[1]; + __IO uint32_t RTIFU; + __IO uint32_t RTICU; + __IO uint32_t RTEU; + __IO uint32_t RTSU; + __IO uint32_t RTIFV; + __IO uint32_t RTICV; + __IO uint32_t RTEV; + __IO uint32_t RTSV; + __IO uint32_t RTIFW; + __IO uint32_t RTICW; + __IO uint32_t RTEW; + __IO uint32_t RTSW; +} stc_tmr4_rcsr_bit_t; + +typedef struct +{ + __IO uint32_t BUFEN0; + __IO uint32_t BUFEN1; + __IO uint32_t EVTOS0; + __IO uint32_t EVTOS1; + __IO uint32_t EVTOS2; + __IO uint32_t LMC; + uint32_t RESERVED0[2]; + __IO uint32_t EVTMS; + __IO uint32_t EVTDS; + uint32_t RESERVED1[2]; + __IO uint32_t DEN; + __IO uint32_t PEN; + __IO uint32_t UEN; + __IO uint32_t ZEN; +} stc_tmr4_scsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[6]; + __IO uint32_t MZCE; + __IO uint32_t MPCE; + uint32_t RESERVED1[8]; +} stc_tmr4_scmr_bit_t; + +typedef struct +{ + __IO uint32_t OEUH; + __IO uint32_t OEUL; + __IO uint32_t OEVH; + __IO uint32_t OEVL; + __IO uint32_t OEWH; + __IO uint32_t OEWL; + __IO uint32_t ODT0; + __IO uint32_t ODT1; + __IO uint32_t MOE; + __IO uint32_t AOE; + uint32_t RESERVED0[6]; + __IO uint32_t OSUH0; + __IO uint32_t OSUH1; + __IO uint32_t OSUL0; + __IO uint32_t OSUL1; + __IO uint32_t OSVH0; + __IO uint32_t OSVH1; + __IO uint32_t OSVL0; + __IO uint32_t OSVL1; + __IO uint32_t OSWH0; + __IO uint32_t OSWH1; + __IO uint32_t OSWL0; + __IO uint32_t OSWL1; + uint32_t RESERVED1[4]; +} stc_tmr4_pscr_bit_t; + +typedef struct +{ + __IO uint32_t EVTRS0; + __IO uint32_t EVTRS1; + __IO uint32_t EVTRS2; + __IO uint32_t PCTS; + uint32_t RESERVED0[12]; +} stc_tmr4_scer_bit_t; + +typedef struct +{ + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + uint32_t RESERVED0[1]; + __IO uint32_t CKDIV0; + __IO uint32_t CKDIV1; + __IO uint32_t CKDIV2; + __IO uint32_t CKDIV3; + __IO uint32_t OVSTP; + uint32_t RESERVED1[7]; + __IO uint32_t ZMSKREV; + __IO uint32_t ZMSKPOS; + __IO uint32_t ZMSKVAL0; + __IO uint32_t ZMSKVAL1; + uint32_t RESERVED2[12]; +} stc_tmr6_gconr_bit_t; + +typedef struct +{ + __IO uint32_t INTENA; + __IO uint32_t INTENB; + __IO uint32_t INTENC; + __IO uint32_t INTEND; + __IO uint32_t INTENE; + __IO uint32_t INTENF; + __IO uint32_t INTENOVF; + __IO uint32_t INTENUDF; + __IO uint32_t INTENDTE; + uint32_t RESERVED0[7]; + __IO uint32_t INTENSAU; + __IO uint32_t INTENSAD; + __IO uint32_t INTENSBU; + __IO uint32_t INTENSBD; + uint32_t RESERVED1[12]; +} stc_tmr6_iconr_bit_t; + +typedef struct +{ + __IO uint32_t BENA; + __IO uint32_t BSEA; + __IO uint32_t BTRUA; + __IO uint32_t BTRDA; + __IO uint32_t BENB; + __IO uint32_t BSEB; + __IO uint32_t BTRUB; + __IO uint32_t BTRDB; + __IO uint32_t BENP; + __IO uint32_t BSEP; + __IO uint32_t BTRUP; + __IO uint32_t BTRDP; + uint32_t RESERVED0[4]; + __IO uint32_t BENSPA; + __IO uint32_t BSESPA; + __IO uint32_t BTRUSPA; + __IO uint32_t BTRDSPA; + __IO uint32_t BENSPB; + __IO uint32_t BSESPB; + __IO uint32_t BTRUSPB; + __IO uint32_t BTRDSPB; + uint32_t RESERVED1[8]; +} stc_tmr6_bconr_bit_t; + +typedef struct +{ + __IO uint32_t DTCEN; + __IO uint32_t SEPA; + uint32_t RESERVED0[2]; + __IO uint32_t DTBENU; + __IO uint32_t DTBEND; + __IO uint32_t DTBTRU; + __IO uint32_t DTBTRD; + uint32_t RESERVED1[24]; +} stc_tmr6_dconr_bit_t; + +typedef struct +{ + __IO uint32_t STACA0; + __IO uint32_t STACA1; + __IO uint32_t STPCA0; + __IO uint32_t STPCA1; + __IO uint32_t OVFCA0; + __IO uint32_t OVFCA1; + __IO uint32_t UDFCA0; + __IO uint32_t UDFCA1; + __IO uint32_t CMAUCA0; + __IO uint32_t CMAUCA1; + __IO uint32_t CMADCA0; + __IO uint32_t CMADCA1; + __IO uint32_t CMBUCA0; + __IO uint32_t CMBUCA1; + __IO uint32_t CMBDCA0; + __IO uint32_t CMBDCA1; + __IO uint32_t FORCA0; + __IO uint32_t FORCA1; + uint32_t RESERVED0[2]; + __IO uint32_t EMBCA0; + __IO uint32_t EMBCA1; + __IO uint32_t EMBRA0; + __IO uint32_t EMBRA1; + __IO uint32_t EMBSA0; + __IO uint32_t EMBSA1; + uint32_t RESERVED1[2]; + __IO uint32_t OUTENA; + uint32_t RESERVED2[2]; + __IO uint32_t CAPMDA; +} stc_tmr6_pcnar_bit_t; + +typedef struct +{ + __IO uint32_t STACB0; + __IO uint32_t STACB1; + __IO uint32_t STPCB0; + __IO uint32_t STPCB1; + __IO uint32_t OVFCB0; + __IO uint32_t OVFCB1; + __IO uint32_t UDFCB0; + __IO uint32_t UDFCB1; + __IO uint32_t CMAUCB0; + __IO uint32_t CMAUCB1; + __IO uint32_t CMADCB0; + __IO uint32_t CMADCB1; + __IO uint32_t CMBUCB0; + __IO uint32_t CMBUCB1; + __IO uint32_t CMBDCB0; + __IO uint32_t CMBDCB1; + __IO uint32_t FORCB0; + __IO uint32_t FORCB1; + uint32_t RESERVED0[2]; + __IO uint32_t EMBCB0; + __IO uint32_t EMBCB1; + __IO uint32_t EMBRB0; + __IO uint32_t EMBRB1; + __IO uint32_t EMBSB0; + __IO uint32_t EMBSB1; + uint32_t RESERVED1[2]; + __IO uint32_t OUTENB; + uint32_t RESERVED2[2]; + __IO uint32_t CAPMDB; +} stc_tmr6_pcnbr_bit_t; + +typedef struct +{ + __IO uint32_t NOFIENGA; + __IO uint32_t NOFICKGA0; + __IO uint32_t NOFICKGA1; + uint32_t RESERVED0[1]; + __IO uint32_t NOFIENGB; + __IO uint32_t NOFICKGB0; + __IO uint32_t NOFICKGB1; + uint32_t RESERVED1[25]; +} stc_tmr6_fcngr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[8]; + __IO uint32_t SPPERIA; + __IO uint32_t SPPERIB; + uint32_t RESERVED1[6]; + __IO uint32_t PCNTE0; + __IO uint32_t PCNTE1; + __IO uint32_t PCNTS0; + __IO uint32_t PCNTS1; + __IO uint32_t PCNTS2; + uint32_t RESERVED2[11]; +} stc_tmr6_vperr_bit_t; + +typedef struct +{ + __IO uint32_t CMAF; + __IO uint32_t CMBF; + __IO uint32_t CMCF; + __IO uint32_t CMDF; + __IO uint32_t CMEF; + __IO uint32_t CMFF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + __IO uint32_t DTEF; + __IO uint32_t CMSAUF; + __IO uint32_t CMSADF; + __IO uint32_t CMSBUF; + __IO uint32_t CMSBDF; + uint32_t RESERVED0[8]; + __IO uint32_t VPERNUM0; + __IO uint32_t VPERNUM1; + __IO uint32_t VPERNUM2; + uint32_t RESERVED1[7]; + __IO uint32_t DIRF; +} stc_tmr6_stflr_bit_t; + +typedef struct +{ + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + __IO uint32_t HSTA3; + uint32_t RESERVED0[3]; + __IO uint32_t STAS; + __IO uint32_t HSTA8; + __IO uint32_t HSTA9; + __IO uint32_t HSTA10; + __IO uint32_t HSTA11; + uint32_t RESERVED1[4]; + __IO uint32_t HSTA16; + __IO uint32_t HSTA17; + __IO uint32_t HSTA18; + __IO uint32_t HSTA19; + __IO uint32_t HSTA20; + __IO uint32_t HSTA21; + __IO uint32_t HSTA22; + __IO uint32_t HSTA23; + uint32_t RESERVED2[8]; +} stc_tmr6_hstar_bit_t; + +typedef struct +{ + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + __IO uint32_t HSTP3; + uint32_t RESERVED0[3]; + __IO uint32_t STPS; + __IO uint32_t HSTP8; + __IO uint32_t HSTP9; + __IO uint32_t HSTP10; + __IO uint32_t HSTP11; + uint32_t RESERVED1[4]; + __IO uint32_t HSTP16; + __IO uint32_t HSTP17; + __IO uint32_t HSTP18; + __IO uint32_t HSTP19; + __IO uint32_t HSTP20; + __IO uint32_t HSTP21; + __IO uint32_t HSTP22; + __IO uint32_t HSTP23; + uint32_t RESERVED2[8]; +} stc_tmr6_hstpr_bit_t; + +typedef struct +{ + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + __IO uint32_t HCLE3; + uint32_t RESERVED0[3]; + __IO uint32_t CLES; + __IO uint32_t HCLE8; + __IO uint32_t HCLE9; + __IO uint32_t HCLE10; + __IO uint32_t HCLE11; + uint32_t RESERVED1[4]; + __IO uint32_t HCLE16; + __IO uint32_t HCLE17; + __IO uint32_t HCLE18; + __IO uint32_t HCLE19; + __IO uint32_t HCLE20; + __IO uint32_t HCLE21; + __IO uint32_t HCLE22; + __IO uint32_t HCLE23; + uint32_t RESERVED2[8]; +} stc_tmr6_hclrr_bit_t; + +typedef struct +{ + __IO uint32_t HUPD0; + __IO uint32_t HUPD1; + __IO uint32_t HUPD2; + __IO uint32_t HUPD3; + uint32_t RESERVED0[3]; + __IO uint32_t UPDS; + __IO uint32_t HUPD8; + __IO uint32_t HUPD9; + __IO uint32_t HUPD10; + __IO uint32_t HUPD11; + uint32_t RESERVED1[4]; + __IO uint32_t HUPD16; + __IO uint32_t HUPD17; + __IO uint32_t HUPD18; + __IO uint32_t HUPD19; + __IO uint32_t HUPD20; + __IO uint32_t HUPD21; + __IO uint32_t HUPD22; + __IO uint32_t HUPD23; + uint32_t RESERVED2[8]; +} stc_tmr6_hupdr_bit_t; + +typedef struct +{ + __IO uint32_t HCPA0; + __IO uint32_t HCPA1; + __IO uint32_t HCPA2; + __IO uint32_t HCPA3; + uint32_t RESERVED0[4]; + __IO uint32_t HCPA8; + __IO uint32_t HCPA9; + __IO uint32_t HCPA10; + __IO uint32_t HCPA11; + uint32_t RESERVED1[4]; + __IO uint32_t HCPA16; + __IO uint32_t HCPA17; + __IO uint32_t HCPA18; + __IO uint32_t HCPA19; + __IO uint32_t HCPA20; + __IO uint32_t HCPA21; + __IO uint32_t HCPA22; + __IO uint32_t HCPA23; + uint32_t RESERVED2[8]; +} stc_tmr6_hcpar_bit_t; + +typedef struct +{ + __IO uint32_t HCPB0; + __IO uint32_t HCPB1; + __IO uint32_t HCPB2; + __IO uint32_t HCPB3; + uint32_t RESERVED0[4]; + __IO uint32_t HCPB8; + __IO uint32_t HCPB9; + __IO uint32_t HCPB10; + __IO uint32_t HCPB11; + uint32_t RESERVED1[4]; + __IO uint32_t HCPB16; + __IO uint32_t HCPB17; + __IO uint32_t HCPB18; + __IO uint32_t HCPB19; + __IO uint32_t HCPB20; + __IO uint32_t HCPB21; + __IO uint32_t HCPB22; + __IO uint32_t HCPB23; + uint32_t RESERVED2[8]; +} stc_tmr6_hcpbr_bit_t; + +typedef struct +{ + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + uint32_t RESERVED0[4]; + __IO uint32_t HCUP16; + __IO uint32_t HCUP17; + __IO uint32_t HCUP18; + __IO uint32_t HCUP19; + __IO uint32_t HCUP20; + __IO uint32_t HCUP21; + __IO uint32_t HCUP22; + __IO uint32_t HCUP23; + uint32_t RESERVED1[8]; +} stc_tmr6_hcupr_bit_t; + +typedef struct +{ + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + uint32_t RESERVED0[4]; + __IO uint32_t HCDO16; + __IO uint32_t HCDO17; + __IO uint32_t HCDO18; + __IO uint32_t HCDO19; + __IO uint32_t HCDO20; + __IO uint32_t HCDO21; + __IO uint32_t HCDO22; + __IO uint32_t HCDO23; + uint32_t RESERVED1[8]; +} stc_tmr6_hcdor_bit_t; + +typedef struct +{ + __IO uint32_t NOFIENTA; + __IO uint32_t NOFICKTA0; + __IO uint32_t NOFICKTA1; + uint32_t RESERVED0[1]; + __IO uint32_t NOFIENTB; + __IO uint32_t NOFICKTB0; + __IO uint32_t NOFICKTB1; + uint32_t RESERVED1[1]; + __IO uint32_t NOFIENTC; + __IO uint32_t NOFICKTC0; + __IO uint32_t NOFICKTC1; + uint32_t RESERVED2[1]; + __IO uint32_t NOFIENTD; + __IO uint32_t NOFICKTD0; + __IO uint32_t NOFICKTD1; + uint32_t RESERVED3[17]; +} stc_tmr6_fcntr_bit_t; + +typedef struct +{ + __IO uint32_t SSTA1; + __IO uint32_t SSTA2; + __IO uint32_t SSTA3; + __IO uint32_t SSTA4; + __IO uint32_t SSTA5; + __IO uint32_t SSTA6; + __IO uint32_t SSTA7; + __IO uint32_t SSTA8; + uint32_t RESERVED0[24]; +} stc_tmr6_sstar_bit_t; + +typedef struct +{ + __IO uint32_t SSTP1; + __IO uint32_t SSTP2; + __IO uint32_t SSTP3; + __IO uint32_t SSTP4; + __IO uint32_t SSTP5; + __IO uint32_t SSTP6; + __IO uint32_t SSTP7; + __IO uint32_t SSTP8; + uint32_t RESERVED0[24]; +} stc_tmr6_sstpr_bit_t; + +typedef struct +{ + __IO uint32_t SCLE1; + __IO uint32_t SCLE2; + __IO uint32_t SCLE3; + __IO uint32_t SCLE4; + __IO uint32_t SCLE5; + __IO uint32_t SCLE6; + __IO uint32_t SCLE7; + __IO uint32_t SCLE8; + uint32_t RESERVED0[24]; +} stc_tmr6_sclrr_bit_t; + +typedef struct +{ + __IO uint32_t SUPD1; + __IO uint32_t SUPD2; + __IO uint32_t SUPD3; + __IO uint32_t SUPD4; + __IO uint32_t SUPD5; + __IO uint32_t SUPD6; + __IO uint32_t SUPD7; + __IO uint32_t SUPD8; + uint32_t RESERVED0[24]; +} stc_tmr6_supdr_bit_t; + +typedef struct +{ + __IO uint32_t CNT0; + __IO uint32_t CNT1; + __IO uint32_t CNT2; + __IO uint32_t CNT3; + __IO uint32_t CNT4; + __IO uint32_t CNT5; + __IO uint32_t CNT6; + __IO uint32_t CNT7; + __IO uint32_t CNT8; + __IO uint32_t CNT9; + __IO uint32_t CNT10; + __IO uint32_t CNT11; + __IO uint32_t CNT12; + __IO uint32_t CNT13; + __IO uint32_t CNT14; + __IO uint32_t CNT15; + uint32_t RESERVED0[16]; +} stc_tmra_cnter_bit_t; + +typedef struct +{ + __IO uint32_t PER0; + __IO uint32_t PER1; + __IO uint32_t PER2; + __IO uint32_t PER3; + __IO uint32_t PER4; + __IO uint32_t PER5; + __IO uint32_t PER6; + __IO uint32_t PER7; + __IO uint32_t PER8; + __IO uint32_t PER9; + __IO uint32_t PER10; + __IO uint32_t PER11; + __IO uint32_t PER12; + __IO uint32_t PER13; + __IO uint32_t PER14; + __IO uint32_t PER15; + uint32_t RESERVED0[16]; +} stc_tmra_perar_bit_t; + +typedef struct +{ + __IO uint32_t CMP0; + __IO uint32_t CMP1; + __IO uint32_t CMP2; + __IO uint32_t CMP3; + __IO uint32_t CMP4; + __IO uint32_t CMP5; + __IO uint32_t CMP6; + __IO uint32_t CMP7; + __IO uint32_t CMP8; + __IO uint32_t CMP9; + __IO uint32_t CMP10; + __IO uint32_t CMP11; + __IO uint32_t CMP12; + __IO uint32_t CMP13; + __IO uint32_t CMP14; + __IO uint32_t CMP15; + uint32_t RESERVED0[16]; +} stc_tmra_cmpar1_bit_t; + +typedef struct +{ + __IO uint32_t CMP0; + __IO uint32_t CMP1; + __IO uint32_t CMP2; + __IO uint32_t CMP3; + __IO uint32_t CMP4; + __IO uint32_t CMP5; + __IO uint32_t CMP6; + __IO uint32_t CMP7; + __IO uint32_t CMP8; + __IO uint32_t CMP9; + __IO uint32_t CMP10; + __IO uint32_t CMP11; + __IO uint32_t CMP12; + __IO uint32_t CMP13; + __IO uint32_t CMP14; + __IO uint32_t CMP15; + uint32_t RESERVED0[16]; +} stc_tmra_cmpar2_bit_t; + +typedef struct +{ + __IO uint32_t CMP0; + __IO uint32_t CMP1; + __IO uint32_t CMP2; + __IO uint32_t CMP3; + __IO uint32_t CMP4; + __IO uint32_t CMP5; + __IO uint32_t CMP6; + __IO uint32_t CMP7; + __IO uint32_t CMP8; + __IO uint32_t CMP9; + __IO uint32_t CMP10; + __IO uint32_t CMP11; + __IO uint32_t CMP12; + __IO uint32_t CMP13; + __IO uint32_t CMP14; + __IO uint32_t CMP15; + uint32_t RESERVED0[16]; +} stc_tmra_cmpar3_bit_t; + +typedef struct +{ + __IO uint32_t CMP0; + __IO uint32_t CMP1; + __IO uint32_t CMP2; + __IO uint32_t CMP3; + __IO uint32_t CMP4; + __IO uint32_t CMP5; + __IO uint32_t CMP6; + __IO uint32_t CMP7; + __IO uint32_t CMP8; + __IO uint32_t CMP9; + __IO uint32_t CMP10; + __IO uint32_t CMP11; + __IO uint32_t CMP12; + __IO uint32_t CMP13; + __IO uint32_t CMP14; + __IO uint32_t CMP15; + uint32_t RESERVED0[16]; +} stc_tmra_cmpar4_bit_t; + +typedef struct +{ + __IO uint32_t START; + __IO uint32_t DIR; + __IO uint32_t MODE; + __IO uint32_t SYNST; + __IO uint32_t CKDIV0; + __IO uint32_t CKDIV1; + __IO uint32_t CKDIV2; + __IO uint32_t CKDIV3; + __IO uint32_t OVSTP; + uint32_t RESERVED0[3]; + __IO uint32_t ITENOVF; + __IO uint32_t ITENUDF; + __IO uint32_t OVFF; + __IO uint32_t UDFF; + uint32_t RESERVED1[16]; +} stc_tmra_bcstr_bit_t; + +typedef struct +{ + __IO uint32_t HSTA0; + __IO uint32_t HSTA1; + __IO uint32_t HSTA2; + uint32_t RESERVED0[1]; + __IO uint32_t HSTP0; + __IO uint32_t HSTP1; + __IO uint32_t HSTP2; + uint32_t RESERVED1[1]; + __IO uint32_t HCLE0; + __IO uint32_t HCLE1; + __IO uint32_t HCLE2; + uint32_t RESERVED2[1]; + __IO uint32_t HCLE3; + __IO uint32_t HCLE4; + __IO uint32_t HCLE5; + __IO uint32_t HCLE6; + uint32_t RESERVED3[16]; +} stc_tmra_hconr_bit_t; + +typedef struct +{ + __IO uint32_t HCUP0; + __IO uint32_t HCUP1; + __IO uint32_t HCUP2; + __IO uint32_t HCUP3; + __IO uint32_t HCUP4; + __IO uint32_t HCUP5; + __IO uint32_t HCUP6; + __IO uint32_t HCUP7; + __IO uint32_t HCUP8; + __IO uint32_t HCUP9; + __IO uint32_t HCUP10; + __IO uint32_t HCUP11; + __IO uint32_t HCUP12; + uint32_t RESERVED0[19]; +} stc_tmra_hcupr_bit_t; + +typedef struct +{ + __IO uint32_t HCDO0; + __IO uint32_t HCDO1; + __IO uint32_t HCDO2; + __IO uint32_t HCDO3; + __IO uint32_t HCDO4; + __IO uint32_t HCDO5; + __IO uint32_t HCDO6; + __IO uint32_t HCDO7; + __IO uint32_t HCDO8; + __IO uint32_t HCDO9; + __IO uint32_t HCDO10; + __IO uint32_t HCDO11; + __IO uint32_t HCDO12; + uint32_t RESERVED0[19]; +} stc_tmra_hcdor_bit_t; + +typedef struct +{ + __IO uint32_t ITEN1; + __IO uint32_t ITEN2; + __IO uint32_t ITEN3; + __IO uint32_t ITEN4; + uint32_t RESERVED0[28]; +} stc_tmra_iconr_bit_t; + +typedef struct +{ + __IO uint32_t ETEN1; + __IO uint32_t ETEN2; + __IO uint32_t ETEN3; + __IO uint32_t ETEN4; + uint32_t RESERVED0[28]; +} stc_tmra_econr_bit_t; + +typedef struct +{ + __IO uint32_t NOFIENTG; + __IO uint32_t NOFICKTG0; + __IO uint32_t NOFICKTG1; + uint32_t RESERVED0[5]; + __IO uint32_t NOFIENCA; + __IO uint32_t NOFICKCA0; + __IO uint32_t NOFICKCA1; + uint32_t RESERVED1[1]; + __IO uint32_t NOFIENCB; + __IO uint32_t NOFICKCB0; + __IO uint32_t NOFICKCB1; + uint32_t RESERVED2[17]; +} stc_tmra_fconr_bit_t; + +typedef struct +{ + __IO uint32_t CMPF1; + __IO uint32_t CMPF2; + __IO uint32_t CMPF3; + __IO uint32_t CMPF4; + uint32_t RESERVED0[28]; +} stc_tmra_stflr_bit_t; + +typedef struct +{ + __IO uint32_t BEN; + __IO uint32_t BSE0; + __IO uint32_t BSE1; + uint32_t RESERVED0[29]; +} stc_tmra_bconr_bit_t; + +typedef struct +{ + __IO uint32_t CAPMD; + uint32_t RESERVED0[3]; + __IO uint32_t HICP0; + __IO uint32_t HICP1; + __IO uint32_t HICP2; + uint32_t RESERVED1[1]; + __IO uint32_t HICP3; + __IO uint32_t HICP4; + uint32_t RESERVED2[2]; + __IO uint32_t NOFIENCP; + __IO uint32_t NOFICKCP0; + __IO uint32_t NOFICKCP1; + uint32_t RESERVED3[17]; +} stc_tmra_cconr_bit_t; + +typedef struct +{ + __IO uint32_t STAC0; + __IO uint32_t STAC1; + __IO uint32_t STPC0; + __IO uint32_t STPC1; + __IO uint32_t CMPC0; + __IO uint32_t CMPC1; + __IO uint32_t PERC0; + __IO uint32_t PERC1; + __IO uint32_t FORC0; + __IO uint32_t FORC1; + uint32_t RESERVED0[2]; + __IO uint32_t OUTEN; + uint32_t RESERVED1[19]; +} stc_tmra_pconr_bit_t; + +typedef struct +{ + __IO uint32_t EN; + __IO uint32_t RUN; + uint32_t RESERVED0[30]; +} stc_trng_cr_bit_t; + +typedef struct +{ + __IO uint32_t LOAD; + uint32_t RESERVED0[31]; +} stc_trng_mr_bit_t; + +typedef struct +{ + __IO uint32_t PE; + __IO uint32_t FE; + uint32_t RESERVED0[1]; + __IO uint32_t ORE; + __IO uint32_t BE; + __IO uint32_t RXNE; + __IO uint32_t TC; + __IO uint32_t TXE; + __IO uint32_t RTOF; + __IO uint32_t WKUP; + __IO uint32_t LBD; + uint32_t RESERVED1[5]; + __IO uint32_t MPB; + uint32_t RESERVED2[15]; +} stc_usart_sr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[9]; + __IO uint32_t MPID; + uint32_t RESERVED1[22]; +} stc_usart_dr_bit_t; + +typedef struct +{ + __IO uint32_t RTOE; + __IO uint32_t RTOIE; + __IO uint32_t RE; + __IO uint32_t TE; + __IO uint32_t SLME; + __IO uint32_t RIE; + __IO uint32_t TCIE; + __IO uint32_t TXEIE; + uint32_t RESERVED0[1]; + __IO uint32_t PS; + __IO uint32_t PCE; + uint32_t RESERVED1[1]; + __IO uint32_t M; + uint32_t RESERVED2[2]; + __IO uint32_t OVER8; + __IO uint32_t CPE; + __IO uint32_t CFE; + __IO uint32_t CNF; + __IO uint32_t CORE; + __IO uint32_t CRTOF; + __IO uint32_t CBE; + __IO uint32_t CWKUP; + __IO uint32_t CLBD; + __IO uint32_t MS; + uint32_t RESERVED3[3]; + __IO uint32_t ML; + __IO uint32_t FBME; + __IO uint32_t NFE; + __IO uint32_t SBS; +} stc_usart_cr1_bit_t; + +typedef struct +{ + __IO uint32_t MPE; + __IO uint32_t WKUPIE; + __IO uint32_t BEIE; + __IO uint32_t BEE; + __IO uint32_t LBDIE; + __IO uint32_t LBDL; + __IO uint32_t SBKL0; + __IO uint32_t SBKL1; + __IO uint32_t WKUPE; + uint32_t RESERVED0[2]; + __IO uint32_t CLKC0; + __IO uint32_t CLKC1; + __IO uint32_t STOP; + __IO uint32_t LINEN; + uint32_t RESERVED1[1]; + __IO uint32_t SBK; + __IO uint32_t SBKM; + uint32_t RESERVED2[14]; +} stc_usart_cr2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[3]; + __IO uint32_t HDSEL; + __IO uint32_t LOOP; + __IO uint32_t SCEN; + uint32_t RESERVED1[2]; + __IO uint32_t RTSE; + __IO uint32_t CTSE; + uint32_t RESERVED2[11]; + __IO uint32_t BCN0; + __IO uint32_t BCN1; + __IO uint32_t BCN2; + uint32_t RESERVED3[8]; +} stc_usart_cr3_bit_t; + +typedef struct +{ + __IO uint32_t PSC0; + __IO uint32_t PSC1; + __IO uint32_t LBMPSC0; + __IO uint32_t LBMPSC1; + uint32_t RESERVED0[28]; +} stc_usart_pr_bit_t; + +typedef struct +{ + __IO uint32_t SESREQSCS; + __IO uint32_t SESREQ; + __IO uint32_t VBVALIDOVEN; + __IO uint32_t VBVALIDOVVAL; + __IO uint32_t AVALIDOVEN; + __IO uint32_t AVALIDOVVAL; + __IO uint32_t BVALIDOVEN; + __IO uint32_t BVALIDOVVAL; + __IO uint32_t HSTNEGSCS; + __IO uint32_t HNPREQ; + __IO uint32_t HSTSETHNPEN; + __IO uint32_t DEVHNPEN; + __IO uint32_t EHEN; + uint32_t RESERVED0[2]; + __IO uint32_t DBNCEFLTRBYPASS; + __IO uint32_t CONIDSTS; + __IO uint32_t DBNCTIME; + __IO uint32_t ASESVLD; + __IO uint32_t BSESVLD; + __IO uint32_t OTGVER; + __IO uint32_t CURMOD; + uint32_t RESERVED1[10]; +} stc_usbfs_gotgctl_bit_t; + +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t SESENDDET; + uint32_t RESERVED1[5]; + __IO uint32_t SESREQSUCSTSCHNG; + __IO uint32_t HSTNEGSUCSTSCHNG; + uint32_t RESERVED2[7]; + __IO uint32_t HSTNEGDET; + __IO uint32_t ADEVTOUTCHG; + __IO uint32_t DBNCEDONE; + uint32_t RESERVED3[12]; +} stc_usbfs_gotgint_bit_t; + +typedef struct +{ + __IO uint32_t GLBLINTRMSK; + __IO uint32_t HBSTLEN0; + __IO uint32_t HBSTLEN1; + __IO uint32_t HBSTLEN2; + __IO uint32_t HBSTLEN3; + __IO uint32_t DMAEN; + uint32_t RESERVED0[1]; + __IO uint32_t NPTXFEMPLVL; + __IO uint32_t PTXFEMPLVL; + uint32_t RESERVED1[12]; + __IO uint32_t REMMEMSUPP; + __IO uint32_t NOTIALLDMAWRIT; + __IO uint32_t AHBSINGLE; + uint32_t RESERVED2[8]; +} stc_usbfs_gahbcfg_bit_t; + +typedef struct +{ + __IO uint32_t TOUTCAL0; + __IO uint32_t TOUTCAL1; + __IO uint32_t TOUTCAL2; + __IO uint32_t PHYIF; + uint32_t RESERVED0[1]; + __IO uint32_t FSINTF; + __IO uint32_t PHYSEL; + uint32_t RESERVED1[1]; + __IO uint32_t SRPCAP; + __IO uint32_t HNPCAP; + __IO uint32_t USBTRDTIM0; + __IO uint32_t USBTRDTIM1; + __IO uint32_t USBTRDTIM2; + __IO uint32_t USBTRDTIM3; + uint32_t RESERVED2[8]; + __IO uint32_t TERMSELDLPULSE; + uint32_t RESERVED3[3]; + __IO uint32_t IC_USBCAP; + uint32_t RESERVED4[1]; + __IO uint32_t TXENDDELAY; + __IO uint32_t FORCEHSTMODE; + __IO uint32_t FORCEDEVMODE; + __IO uint32_t CORRUPTTXPKT; +} stc_usbfs_gusbcfg_bit_t; + +typedef struct +{ + __IO uint32_t CSFTRST; + __IO uint32_t PIUFSSFTRST; + __IO uint32_t FRMCNTRRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + uint32_t RESERVED1[24]; + __IO uint32_t DMAREQ; + __IO uint32_t AHBIDLE; +} stc_usbfs_grstctl_bit_t; + +typedef struct +{ + __IO uint32_t CURMOD; + __IO uint32_t MODEMIS; + __IO uint32_t OTGINT; + __IO uint32_t SOF; + __IO uint32_t RXFLVL; + __IO uint32_t NPTXFEMP; + __IO uint32_t GINNAKEFF; + __IO uint32_t GOUTNAKEFF; + uint32_t RESERVED0[2]; + __IO uint32_t ERLYSUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDONE; + __IO uint32_t ISOOUTDROP; + __IO uint32_t EOPF; + uint32_t RESERVED1[1]; + __IO uint32_t EPMIS; + __IO uint32_t IEPINT; + __IO uint32_t OEPINT; + __IO uint32_t INCOMPISOIN; + __IO uint32_t INCOMPLP; + __IO uint32_t FETSUSP; + __IO uint32_t RESETDET; + __IO uint32_t PRTINT; + __IO uint32_t HCHINT; + __IO uint32_t PTXFEMP; + __IO uint32_t LPM_INT; + __IO uint32_t CONIDSTSCHNG; + __IO uint32_t DISCONNINT; + __IO uint32_t SESSREQINT; + __IO uint32_t WKUPINT; +} stc_usbfs_gintsts_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t MODEMISMSK; + __IO uint32_t OTGINTMSK; + __IO uint32_t SOFMSK; + __IO uint32_t RXFLVLMSK; + __IO uint32_t NPTXFEMPMSK; + __IO uint32_t GINNAKEFFMSK; + __IO uint32_t GOUTNAKEFFMSK; + uint32_t RESERVED1[2]; + __IO uint32_t ERLYSUSPMSK; + __IO uint32_t USBSUSPMSK; + __IO uint32_t USBRSTMSK; + __IO uint32_t ENUMDONEMSK; + __IO uint32_t ISOOUTDROPMSK; + __IO uint32_t EOPFMSK; + uint32_t RESERVED2[1]; + __IO uint32_t EPMISMSK; + __IO uint32_t IEPINTMSK; + __IO uint32_t OEPINTMSK; + uint32_t RESERVED3[1]; + __IO uint32_t INCOMPLPMSK; + __IO uint32_t FETSUSPMSK; + __IO uint32_t RESETDETMSK; + __IO uint32_t PRTINTMSK; + __IO uint32_t HCHINTMSK; + __IO uint32_t PTXFEMPMSK; + __IO uint32_t LPM_INTMSK; + __IO uint32_t CONIDSTSCHNGMSK; + __IO uint32_t DISCONNINTMSK; + __IO uint32_t SESSREQINTMSK; + __IO uint32_t WKUPINTMSK; +} stc_usbfs_gintmsk_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t DPID0; + __IO uint32_t DPID1; + __IO uint32_t PKTSTS0; + __IO uint32_t PKTSTS1; + __IO uint32_t PKTSTS2; + __IO uint32_t PKTSTS3; + uint32_t RESERVED1[11]; +} stc_usbfs_grxstsr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t DPID0; + __IO uint32_t DPID1; + __IO uint32_t PKTSTS0; + __IO uint32_t PKTSTS1; + __IO uint32_t PKTSTS2; + __IO uint32_t PKTSTS3; + uint32_t RESERVED1[11]; +} stc_usbfs_grxstsp_bit_t; + +typedef struct +{ + __IO uint32_t RXFDEP0; + __IO uint32_t RXFDEP1; + __IO uint32_t RXFDEP2; + __IO uint32_t RXFDEP3; + __IO uint32_t RXFDEP4; + __IO uint32_t RXFDEP5; + __IO uint32_t RXFDEP6; + __IO uint32_t RXFDEP7; + __IO uint32_t RXFDEP8; + __IO uint32_t RXFDEP9; + uint32_t RESERVED0[22]; +} stc_usbfs_grxfsiz_bit_t; + +typedef struct +{ + uint32_t RESERVED0[24]; + __IO uint32_t NPTXQTOP0; + __IO uint32_t NPTXQTOP1; + __IO uint32_t NPTXQTOP2; + __IO uint32_t NPTXQTOP3; + __IO uint32_t NPTXQTOP4; + __IO uint32_t NPTXQTOP5; + __IO uint32_t NPTXQTOP6; + uint32_t RESERVED1[1]; +} stc_usbfs_gnptxsts_bit_t; + +typedef struct +{ + __IO uint32_t LPMCAP; + __IO uint32_t APPL1RES; + __IO uint32_t HIRD0; + __IO uint32_t HIRD1; + __IO uint32_t HIRD2; + __IO uint32_t HIRD3; + __IO uint32_t BREMOTEWAKE; + __IO uint32_t ENBLSLPM; + __IO uint32_t HIRD_THRES0; + __IO uint32_t HIRD_THRES1; + __IO uint32_t HIRD_THRES2; + __IO uint32_t HIRD_THRES3; + __IO uint32_t HIRD_THRES4; + __IO uint32_t COREL1RES0; + __IO uint32_t COREL1RES1; + __IO uint32_t SLPSTS; + __IO uint32_t L1RESUMEOK; + uint32_t RESERVED0[7]; + __IO uint32_t SNDLPM; + uint32_t RESERVED1[3]; + __IO uint32_t LPM_ENBESL; + __IO uint32_t LPM_RESTORESLPSTS; + uint32_t RESERVED2[2]; +} stc_usbfs_glpmcfg_bit_t; + +typedef struct +{ + __IO uint32_t FSLSPCLKSEL0; + __IO uint32_t FSLSPCLKSEL1; + __IO uint32_t FSLSSUPP; + uint32_t RESERVED0[4]; + __IO uint32_t ENA32KHZS; + uint32_t RESERVED1[23]; + __IO uint32_t MODECHTIMEN; +} stc_usbfs_hcfg_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; + __IO uint32_t HFIRRLDCTRL; + uint32_t RESERVED1[15]; +} stc_usbfs_hfir_bit_t; + +typedef struct +{ + uint32_t RESERVED0[24]; + __IO uint32_t PTXQTOP0; + __IO uint32_t PTXQTOP1; + __IO uint32_t PTXQTOP2; + __IO uint32_t PTXQTOP3; + __IO uint32_t PTXQTOP4; + __IO uint32_t PTXQTOP5; + __IO uint32_t PTXQTOP6; + __IO uint32_t PTXQTOP7; +} stc_usbfs_hptxsts_bit_t; + +typedef struct +{ + __IO uint32_t HAINT0; + __IO uint32_t HAINT1; + __IO uint32_t HAINT2; + __IO uint32_t HAINT3; + __IO uint32_t HAINT4; + __IO uint32_t HAINT5; + __IO uint32_t HAINT6; + __IO uint32_t HAINT7; + __IO uint32_t HAINT8; + __IO uint32_t HAINT9; + __IO uint32_t HAINT10; + __IO uint32_t HAINT11; + __IO uint32_t HAINT12; + __IO uint32_t HAINT13; + __IO uint32_t HAINT14; + __IO uint32_t HAINT15; + uint32_t RESERVED0[16]; +} stc_usbfs_haint_bit_t; + +typedef struct +{ + __IO uint32_t HAINTMSK0; + __IO uint32_t HAINTMSK1; + __IO uint32_t HAINTMSK2; + __IO uint32_t HAINTMSK3; + __IO uint32_t HAINTMSK4; + __IO uint32_t HAINTMSK5; + __IO uint32_t HAINTMSK6; + __IO uint32_t HAINTMSK7; + __IO uint32_t HAINTMSK8; + __IO uint32_t HAINTMSK9; + __IO uint32_t HAINTMSK10; + __IO uint32_t HAINTMSK11; + __IO uint32_t HAINTMSK12; + __IO uint32_t HAINTMSK13; + __IO uint32_t HAINTMSK14; + __IO uint32_t HAINTMSK15; + uint32_t RESERVED0[16]; +} stc_usbfs_haintmsk_bit_t; + +typedef struct +{ + __IO uint32_t PRTCONNSTS; + __IO uint32_t PRTCONNDET; + __IO uint32_t PRTENA; + __IO uint32_t PRTENCHNG; + __IO uint32_t PRTOVRCURRACT; + __IO uint32_t PRTOVRCURRCHNG; + __IO uint32_t PRTRES; + __IO uint32_t PRTSUSP; + __IO uint32_t PRTRST; + uint32_t RESERVED0[1]; + __IO uint32_t PRTLNSTS0; + __IO uint32_t PRTLNSTS1; + __IO uint32_t PRTPWR; + __IO uint32_t PRTTSTCTL0; + __IO uint32_t PRTTSTCTL1; + __IO uint32_t PRTTSTCTL2; + __IO uint32_t PRTTSTCTL3; + __IO uint32_t PRTSPD0; + __IO uint32_t PRTSPD1; + uint32_t RESERVED1[13]; +} stc_usbfs_hprt_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + uint32_t RESERVED2[7]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar4_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk4_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz4_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar5_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk5_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz5_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar6_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk6_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz6_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar7_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk7_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz7_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar8_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk8_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz8_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar9_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk9_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz9_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar10_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk10_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz10_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar11_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk11_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz11_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar13_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk13_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz13_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar14_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk14_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz14_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t EPDIR; + uint32_t RESERVED1[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[9]; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbfs_hcchar15_bit_t; + +typedef struct +{ + uint32_t RESERVED0[14]; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED1[14]; + __IO uint32_t SPLTENA; +} stc_usbfs_hcsplt15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbfs_hcint15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbfs_hcintmsk15_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbfs_hctsiz15_bit_t; + +typedef struct +{ + __IO uint32_t DEVSPD0; + __IO uint32_t DEVSPD1; + __IO uint32_t NZSTSOUTHSHK; + __IO uint32_t ENA32KHZSUSP; + uint32_t RESERVED0[7]; + __IO uint32_t PERFRINT0; + __IO uint32_t PERFRINT1; + uint32_t RESERVED1[1]; + __IO uint32_t XCVRDLY; + __IO uint32_t ERRATICINTMSK; + uint32_t RESERVED2[8]; + __IO uint32_t PERSCHINTVL0; + __IO uint32_t PERSCHINTVL1; + uint32_t RESERVED3[6]; +} stc_usbfs_dcfg_bit_t; + +typedef struct +{ + __IO uint32_t RMTWKUPSIG; + __IO uint32_t SFTDISCON; + __IO uint32_t GNPINNAKSTS; + __IO uint32_t GOUTNAKSTS; + __IO uint32_t TSTCTL0; + __IO uint32_t TSTCTL1; + __IO uint32_t TSTCTL2; + __IO uint32_t SGNPINNAK; + __IO uint32_t CGNPINNAK; + __IO uint32_t SGOUTNAK; + __IO uint32_t CGOUTNAK; + __IO uint32_t PWRONPRGDONE; + uint32_t RESERVED0[3]; + __IO uint32_t IGNRFRMNUM; + __IO uint32_t NAKONBBLE; + uint32_t RESERVED1[1]; + __IO uint32_t DEEPSLEEPBESLREJECT; + __IO uint32_t SERVINT; + uint32_t RESERVED2[12]; +} stc_usbfs_dctl_bit_t; + +typedef struct +{ + __IO uint32_t SUSPSTS; + __IO uint32_t ENUMSPD0; + __IO uint32_t ENUMSPD1; + __IO uint32_t ERRTICERR; + uint32_t RESERVED0[18]; + __IO uint32_t DEVLNSTS0; + __IO uint32_t DEVLNSTS1; + uint32_t RESERVED1[8]; +} stc_usbfs_dsts_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t EPDISBLDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t TIMEOUTMSK; + __IO uint32_t INTKNTXFEMPMSK; + __IO uint32_t INTKNEPMISMSK; + __IO uint32_t INEPNAKEFFMSK; + uint32_t RESERVED0[1]; + __IO uint32_t TXFIFOUNDRNMSK; + uint32_t RESERVED1[4]; + __IO uint32_t NAKMSK; + uint32_t RESERVED2[18]; +} stc_usbfs_diepmsk_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t EPDISBLDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t SETUPMSK; + __IO uint32_t OUTTKNEPDISMSK; + __IO uint32_t STSPHSERCVDMSK; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERRMSK; + uint32_t RESERVED1[3]; + __IO uint32_t BBLEERRMSK; + __IO uint32_t NAKMSK; + __IO uint32_t NYETMSK; + uint32_t RESERVED2[17]; +} stc_usbfs_doepmsk_bit_t; + +typedef struct +{ + __IO uint32_t INEPINT0; + __IO uint32_t INEPINT1; + __IO uint32_t INEPINT2; + __IO uint32_t INEPINT3; + __IO uint32_t INEPINT4; + __IO uint32_t INEPINT5; + __IO uint32_t INEPINT6; + __IO uint32_t INEPINT7; + __IO uint32_t INEPINT8; + __IO uint32_t INEPINT9; + __IO uint32_t INEPINT10; + __IO uint32_t INEPINT11; + __IO uint32_t INEPINT12; + __IO uint32_t INEPINT13; + __IO uint32_t INEPINT14; + __IO uint32_t INEPINT15; + __IO uint32_t OUTEPINT0; + __IO uint32_t OUTEPINT1; + __IO uint32_t OUTEPINT2; + __IO uint32_t OUTEPINT3; + __IO uint32_t OUTEPINT4; + __IO uint32_t OUTEPINT5; + __IO uint32_t OUTEPINT6; + __IO uint32_t OUTEPINT7; + __IO uint32_t OUTEPINT8; + __IO uint32_t OUTEPINT9; + __IO uint32_t OUTEPINT10; + __IO uint32_t OUTEPINT11; + __IO uint32_t OUTEPINT12; + __IO uint32_t OUTEPINT13; + __IO uint32_t OUTEPINT14; + __IO uint32_t OUTEPINT15; +} stc_usbfs_daint_bit_t; + +typedef struct +{ + __IO uint32_t INEPMSK0; + __IO uint32_t INEPMSK1; + __IO uint32_t INEPMSK2; + __IO uint32_t INEPMSK3; + __IO uint32_t INEPMSK4; + __IO uint32_t INEPMSK5; + __IO uint32_t INEPMSK6; + __IO uint32_t INEPMSK7; + __IO uint32_t INEPMSK8; + __IO uint32_t INEPMSK9; + __IO uint32_t INEPMSK10; + __IO uint32_t INEPMSK11; + __IO uint32_t INEPMSK12; + __IO uint32_t INEPMSK13; + __IO uint32_t INEPMSK14; + __IO uint32_t INEPMSK15; + __IO uint32_t OUTEPMSK0; + __IO uint32_t OUTEPMSK1; + __IO uint32_t OUTEPMSK2; + __IO uint32_t OUTEPMSK3; + __IO uint32_t OUTEPMSK4; + __IO uint32_t OUTEPMSK5; + __IO uint32_t OUTEPMSK6; + __IO uint32_t OUTEPMSK7; + __IO uint32_t OUTEPMSK8; + __IO uint32_t OUTEPMSK9; + __IO uint32_t OUTEPMSK10; + __IO uint32_t OUTEPMSK11; + __IO uint32_t OUTEPMSK12; + __IO uint32_t OUTEPMSK13; + __IO uint32_t OUTEPMSK14; + __IO uint32_t OUTEPMSK15; +} stc_usbfs_daintmsk_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFEMPMSK0; + __IO uint32_t INEPTXFEMPMSK1; + __IO uint32_t INEPTXFEMPMSK2; + __IO uint32_t INEPTXFEMPMSK3; + __IO uint32_t INEPTXFEMPMSK4; + __IO uint32_t INEPTXFEMPMSK5; + __IO uint32_t INEPTXFEMPMSK6; + __IO uint32_t INEPTXFEMPMSK7; + __IO uint32_t INEPTXFEMPMSK8; + __IO uint32_t INEPTXFEMPMSK9; + __IO uint32_t INEPTXFEMPMSK10; + __IO uint32_t INEPTXFEMPMSK11; + __IO uint32_t INEPTXFEMPMSK12; + __IO uint32_t INEPTXFEMPMSK13; + __IO uint32_t INEPTXFEMPMSK14; + __IO uint32_t INEPTXFEMPMSK15; + uint32_t RESERVED0[16]; +} stc_usbfs_diepempmsk_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + uint32_t RESERVED1[1]; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[1]; + __IO uint32_t STALL; + uint32_t RESERVED3[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED4[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint0_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbfs_dtxfsts0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint4_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint5_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint6_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint7_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint8_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint9_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint10_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint11_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint13_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint14_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_diepctl15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbfs_diepint15_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + uint32_t RESERVED1[1]; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED3[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint0_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz1_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz2_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz3_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint4_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz4_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint5_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz5_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint6_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz6_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint7_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz7_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint8_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz8_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint9_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz9_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint10_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz10_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint11_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz11_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz12_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint13_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz13_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint14_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz14_bit_t; + +typedef struct +{ + uint32_t RESERVED0[15]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbfs_doepctl15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbfs_doepint15_bit_t; + +typedef struct +{ + uint32_t RESERVED0[29]; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED1[1]; +} stc_usbfs_doeptsiz15_bit_t; + +typedef struct +{ + __IO uint32_t STOPPCLK; + __IO uint32_t GATEHCLK; + __IO uint32_t PWRCLMP; + __IO uint32_t RSTPDWNMODULE; + uint32_t RESERVED0[1]; + __IO uint32_t ENBL_L1GATING; + __IO uint32_t PHYSLEEP; + __IO uint32_t L1SUSPENDED; + __IO uint32_t RESETAFTERSUSP; + uint32_t RESERVED1[23]; +} stc_usbfs_pcgcctl_bit_t; + +typedef struct +{ + __IO uint32_t SESREQSCS; + __IO uint32_t SESREQ; + __IO uint32_t VBVALIDOVEN; + __IO uint32_t VBVALIDOVVAL; + __IO uint32_t AVALIDOVEN; + __IO uint32_t AVALIDOVVAL; + __IO uint32_t BVALIDOVEN; + __IO uint32_t BVALIDOVVAL; + __IO uint32_t HSTNEGSCS; + __IO uint32_t HNPREQ; + __IO uint32_t HSTSETHNPEN; + __IO uint32_t DEVHNPEN; + __IO uint32_t EHEN; + uint32_t RESERVED0[2]; + __IO uint32_t DBNCEFLTRBYPASS; + __IO uint32_t CONIDSTS; + __IO uint32_t DBNCTIME; + __IO uint32_t ASESVLD; + __IO uint32_t BSESVLD; + __IO uint32_t OTGVER; + __IO uint32_t CURMOD; + uint32_t RESERVED1[9]; + __IO uint32_t TESTMODE_CORR_EUSB2; +} stc_usbhs_gotgctl_bit_t; + +typedef struct +{ + uint32_t RESERVED0[2]; + __IO uint32_t SESENDDET; + uint32_t RESERVED1[5]; + __IO uint32_t SESREQSUCSTSCHNG; + __IO uint32_t HSTNEGSUCSTSCHNG; + uint32_t RESERVED2[7]; + __IO uint32_t HSTNEGDET; + __IO uint32_t ADEVTOUTCHG; + __IO uint32_t DBNCEDONE; + uint32_t RESERVED3[12]; +} stc_usbhs_gotgint_bit_t; + +typedef struct +{ + __IO uint32_t GLBLINTRMSK; + __IO uint32_t HBSTLEN0; + __IO uint32_t HBSTLEN1; + __IO uint32_t HBSTLEN2; + __IO uint32_t HBSTLEN3; + __IO uint32_t DMAEN; + uint32_t RESERVED0[1]; + __IO uint32_t NPTXFEMPLVL; + __IO uint32_t PTXFEMPLVL; + uint32_t RESERVED1[12]; + __IO uint32_t REMMEMSUPP; + __IO uint32_t NOTIALLDMAWRIT; + __IO uint32_t AHBSINGLE; + uint32_t RESERVED2[8]; +} stc_usbhs_gahbcfg_bit_t; + +typedef struct +{ + __IO uint32_t TOUTCAL0; + __IO uint32_t TOUTCAL1; + __IO uint32_t TOUTCAL2; + __IO uint32_t PHYIF; + __IO uint32_t ULPI_UTMI_SEL; + __IO uint32_t FSINTF; + __IO uint32_t PHYSEL; + __IO uint32_t DDRSEL; + __IO uint32_t SRPCAP; + __IO uint32_t HNPCAP; + __IO uint32_t USBTRDTIM0; + __IO uint32_t USBTRDTIM1; + __IO uint32_t USBTRDTIM2; + __IO uint32_t USBTRDTIM3; + uint32_t RESERVED0[3]; + __IO uint32_t ULPIFSLS; + __IO uint32_t ULPIAUTORES; + __IO uint32_t ULPICLKSUSM; + __IO uint32_t ULPIEXTVBUSDRV; + __IO uint32_t ULPIEXTVBUSINDICATOR; + __IO uint32_t TERMSELDLPULSE; + __IO uint32_t COMPLEMENT; + __IO uint32_t INDICATOR; + __IO uint32_t ULPI; + __IO uint32_t IC_USBCAP; + uint32_t RESERVED1[1]; + __IO uint32_t TXENDDELAY; + __IO uint32_t FORCEHSTMODE; + __IO uint32_t FORCEDEVMODE; + __IO uint32_t CORRUPTTXPKT; +} stc_usbhs_gusbcfg_bit_t; + +typedef struct +{ + __IO uint32_t CSFTRST; + __IO uint32_t PIUFSSFTRST; + __IO uint32_t FRMCNTRRST; + uint32_t RESERVED0[1]; + __IO uint32_t RXFFLSH; + __IO uint32_t TXFFLSH; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t TXFNUM4; + uint32_t RESERVED1[19]; + __IO uint32_t DMAREQ; + __IO uint32_t AHBIDLE; +} stc_usbhs_grstctl_bit_t; + +typedef struct +{ + __IO uint32_t CURMOD; + __IO uint32_t MODEMIS; + __IO uint32_t OTGINT; + __IO uint32_t SOF; + __IO uint32_t RXFLVL; + __IO uint32_t NPTXFEMP; + __IO uint32_t GINNAKEFF; + __IO uint32_t GOUTNAKEFF; + uint32_t RESERVED0[2]; + __IO uint32_t ERLYSUSP; + __IO uint32_t USBSUSP; + __IO uint32_t USBRST; + __IO uint32_t ENUMDONE; + __IO uint32_t ISOOUTDROP; + __IO uint32_t EOPF; + uint32_t RESERVED1[1]; + __IO uint32_t EPMIS; + __IO uint32_t IEPINT; + __IO uint32_t OEPINT; + __IO uint32_t INCOMPISOIN; + __IO uint32_t INCOMPLP; + __IO uint32_t FETSUSP; + __IO uint32_t RESETDET; + __IO uint32_t PRTINT; + __IO uint32_t HCHINT; + __IO uint32_t PTXFEMP; + __IO uint32_t LPM_INT; + __IO uint32_t CONIDSTSCHNG; + __IO uint32_t DISCONNINT; + __IO uint32_t SESSREQINT; + __IO uint32_t WKUPINT; +} stc_usbhs_gintsts_bit_t; + +typedef struct +{ + uint32_t RESERVED0[1]; + __IO uint32_t MODEMISMSK; + __IO uint32_t OTGINTMSK; + __IO uint32_t SOFMSK; + __IO uint32_t RXFLVLMSK; + __IO uint32_t NPTXFEMPMSK; + __IO uint32_t GINNAKEFFMSK; + __IO uint32_t GOUTNAKEFFMSK; + uint32_t RESERVED1[2]; + __IO uint32_t ERLYSUSPMSK; + __IO uint32_t USBSUSPMSK; + __IO uint32_t USBRSTMSK; + __IO uint32_t ENUMDONEMSK; + __IO uint32_t ISOOUTDROPMSK; + __IO uint32_t EOPFMSK; + uint32_t RESERVED2[1]; + __IO uint32_t EPMISMSK; + __IO uint32_t IEPINTMSK; + __IO uint32_t OEPINTMSK; + uint32_t RESERVED3[1]; + __IO uint32_t INCOMPLPMSK; + __IO uint32_t FETSUSPMSK; + __IO uint32_t RESETDETMSK; + __IO uint32_t PRTINTMSK; + __IO uint32_t HCHINTMSK; + __IO uint32_t PTXFEMPMSK; + __IO uint32_t LPM_INTMSK; + __IO uint32_t CONIDSTSCHNGMSK; + __IO uint32_t DISCONNINTMSK; + __IO uint32_t SESSREQINTMSK; + __IO uint32_t WKUPINTMSK; +} stc_usbhs_gintmsk_bit_t; + +typedef struct +{ + __IO uint32_t CHNUM0; + __IO uint32_t CHNUM1; + __IO uint32_t CHNUM2; + __IO uint32_t CHNUM3; + __IO uint32_t BCNT0; + __IO uint32_t BCNT1; + __IO uint32_t BCNT2; + __IO uint32_t BCNT3; + __IO uint32_t BCNT4; + __IO uint32_t BCNT5; + __IO uint32_t BCNT6; + __IO uint32_t BCNT7; + __IO uint32_t BCNT8; + __IO uint32_t BCNT9; + __IO uint32_t BCNT10; + __IO uint32_t DPID0; + __IO uint32_t DPID1; + __IO uint32_t PKTSTS0; + __IO uint32_t PKTSTS1; + __IO uint32_t PKTSTS2; + __IO uint32_t PKTSTS3; + __IO uint32_t FN0; + __IO uint32_t FN1; + __IO uint32_t FN2; + __IO uint32_t FN3; + uint32_t RESERVED0[7]; +} stc_usbhs_grxstsr_bit_t; + +typedef struct +{ + __IO uint32_t CHNUM0; + __IO uint32_t CHNUM1; + __IO uint32_t CHNUM2; + __IO uint32_t CHNUM3; + __IO uint32_t BCNT0; + __IO uint32_t BCNT1; + __IO uint32_t BCNT2; + __IO uint32_t BCNT3; + __IO uint32_t BCNT4; + __IO uint32_t BCNT5; + __IO uint32_t BCNT6; + __IO uint32_t BCNT7; + __IO uint32_t BCNT8; + __IO uint32_t BCNT9; + __IO uint32_t BCNT10; + __IO uint32_t DPID0; + __IO uint32_t DPID1; + __IO uint32_t PKTSTS0; + __IO uint32_t PKTSTS1; + __IO uint32_t PKTSTS2; + __IO uint32_t PKTSTS3; + __IO uint32_t FN0; + __IO uint32_t FN1; + __IO uint32_t FN2; + __IO uint32_t FN3; + uint32_t RESERVED0[7]; +} stc_usbhs_grxstsp_bit_t; + +typedef struct +{ + __IO uint32_t RXFDEP0; + __IO uint32_t RXFDEP1; + __IO uint32_t RXFDEP2; + __IO uint32_t RXFDEP3; + __IO uint32_t RXFDEP4; + __IO uint32_t RXFDEP5; + __IO uint32_t RXFDEP6; + __IO uint32_t RXFDEP7; + __IO uint32_t RXFDEP8; + __IO uint32_t RXFDEP9; + __IO uint32_t RXFDEP10; + __IO uint32_t RXFDEP11; + uint32_t RESERVED0[20]; +} stc_usbhs_grxfsiz_bit_t; + +typedef struct +{ + __IO uint32_t NPTXFSTADDR0; + __IO uint32_t NPTXFSTADDR1; + __IO uint32_t NPTXFSTADDR2; + __IO uint32_t NPTXFSTADDR3; + __IO uint32_t NPTXFSTADDR4; + __IO uint32_t NPTXFSTADDR5; + __IO uint32_t NPTXFSTADDR6; + __IO uint32_t NPTXFSTADDR7; + __IO uint32_t NPTXFSTADDR8; + __IO uint32_t NPTXFSTADDR9; + __IO uint32_t NPTXFSTADDR10; + __IO uint32_t NPTXFSTADDR11; + uint32_t RESERVED0[4]; + __IO uint32_t NPTXFDEP0; + __IO uint32_t NPTXFDEP1; + __IO uint32_t NPTXFDEP2; + __IO uint32_t NPTXFDEP3; + __IO uint32_t NPTXFDEP4; + __IO uint32_t NPTXFDEP5; + __IO uint32_t NPTXFDEP6; + __IO uint32_t NPTXFDEP7; + __IO uint32_t NPTXFDEP8; + __IO uint32_t NPTXFDEP9; + __IO uint32_t NPTXFDEP10; + __IO uint32_t NPTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_gnptxfsiz_bit_t; + +typedef struct +{ + __IO uint32_t NPTXFSPCAVAIL0; + __IO uint32_t NPTXFSPCAVAIL1; + __IO uint32_t NPTXFSPCAVAIL2; + __IO uint32_t NPTXFSPCAVAIL3; + __IO uint32_t NPTXFSPCAVAIL4; + __IO uint32_t NPTXFSPCAVAIL5; + __IO uint32_t NPTXFSPCAVAIL6; + __IO uint32_t NPTXFSPCAVAIL7; + __IO uint32_t NPTXFSPCAVAIL8; + __IO uint32_t NPTXFSPCAVAIL9; + __IO uint32_t NPTXFSPCAVAIL10; + __IO uint32_t NPTXFSPCAVAIL11; + __IO uint32_t NPTXFSPCAVAIL12; + __IO uint32_t NPTXFSPCAVAIL13; + __IO uint32_t NPTXFSPCAVAIL14; + __IO uint32_t NPTXFSPCAVAIL15; + __IO uint32_t NPTXQSPCAVAIL0; + __IO uint32_t NPTXQSPCAVAIL1; + __IO uint32_t NPTXQSPCAVAIL2; + __IO uint32_t NPTXQSPCAVAIL3; + __IO uint32_t NPTXQSPCAVAIL4; + __IO uint32_t NPTXQSPCAVAIL5; + __IO uint32_t NPTXQSPCAVAIL6; + __IO uint32_t NPTXQSPCAVAIL7; + __IO uint32_t NPTXQTOP0; + __IO uint32_t NPTXQTOP1; + __IO uint32_t NPTXQTOP2; + __IO uint32_t NPTXQTOP3; + __IO uint32_t NPTXQTOP4; + __IO uint32_t NPTXQTOP5; + __IO uint32_t NPTXQTOP6; + uint32_t RESERVED0[1]; +} stc_usbhs_gnptxsts_bit_t; + +typedef struct +{ + __IO uint32_t REGDATA0; + __IO uint32_t REGDATA1; + __IO uint32_t REGDATA2; + __IO uint32_t REGDATA3; + __IO uint32_t REGDATA4; + __IO uint32_t REGDATA5; + __IO uint32_t REGDATA6; + __IO uint32_t REGDATA7; + __IO uint32_t VCTRL0; + __IO uint32_t VCTRL1; + __IO uint32_t VCTRL2; + __IO uint32_t VCTRL3; + __IO uint32_t VCTRL4; + __IO uint32_t VCTRL5; + __IO uint32_t VCTRL6; + __IO uint32_t VCTRL7; + __IO uint32_t REGADDR0; + __IO uint32_t REGADDR1; + __IO uint32_t REGADDR2; + __IO uint32_t REGADDR3; + __IO uint32_t REGADDR4; + __IO uint32_t REGADDR5; + __IO uint32_t REGWR; + uint32_t RESERVED0[2]; + __IO uint32_t NEWREGREQ; + __IO uint32_t VSTSBSY; + __IO uint32_t VSTSDONE; + uint32_t RESERVED1[4]; +} stc_usbhs_gpvndctl_bit_t; + +typedef struct +{ + __IO uint32_t LPMCAP; + __IO uint32_t APPL1RES; + __IO uint32_t HIRD0; + __IO uint32_t HIRD1; + __IO uint32_t HIRD2; + __IO uint32_t HIRD3; + __IO uint32_t BREMOTEWAKE; + __IO uint32_t ENBLSLPM; + __IO uint32_t HIRD_THRES0; + __IO uint32_t HIRD_THRES1; + __IO uint32_t HIRD_THRES2; + __IO uint32_t HIRD_THRES3; + __IO uint32_t HIRD_THRES4; + __IO uint32_t COREL1RES0; + __IO uint32_t COREL1RES1; + __IO uint32_t SLPSTS; + __IO uint32_t L1RESUMEOK; + __IO uint32_t LPM_CHNL_INDX0; + __IO uint32_t LPM_CHNL_INDX1; + __IO uint32_t LPM_CHNL_INDX2; + __IO uint32_t LPM_CHNL_INDX3; + __IO uint32_t LPM_RETRY_CNT0; + __IO uint32_t LPM_RETRY_CNT1; + __IO uint32_t LPM_RETRY_CNT2; + __IO uint32_t SNDLPM; + __IO uint32_t LPM_RETRYCNT_STS0; + __IO uint32_t LPM_RETRYCNT_STS1; + __IO uint32_t LPM_RETRYCNT_STS2; + __IO uint32_t LPM_ENBESL; + __IO uint32_t LPM_RESTORESLPSTS; + uint32_t RESERVED0[2]; +} stc_usbhs_glpmcfg_bit_t; + +typedef struct +{ + __IO uint32_t GDFIFOCFG0; + __IO uint32_t GDFIFOCFG1; + __IO uint32_t GDFIFOCFG2; + __IO uint32_t GDFIFOCFG3; + __IO uint32_t GDFIFOCFG4; + __IO uint32_t GDFIFOCFG5; + __IO uint32_t GDFIFOCFG6; + __IO uint32_t GDFIFOCFG7; + __IO uint32_t GDFIFOCFG8; + __IO uint32_t GDFIFOCFG9; + __IO uint32_t GDFIFOCFG10; + __IO uint32_t GDFIFOCFG11; + __IO uint32_t GDFIFOCFG12; + __IO uint32_t GDFIFOCFG13; + __IO uint32_t GDFIFOCFG14; + __IO uint32_t GDFIFOCFG15; + __IO uint32_t EPINFOBASEADDR0; + __IO uint32_t EPINFOBASEADDR1; + __IO uint32_t EPINFOBASEADDR2; + __IO uint32_t EPINFOBASEADDR3; + __IO uint32_t EPINFOBASEADDR4; + __IO uint32_t EPINFOBASEADDR5; + __IO uint32_t EPINFOBASEADDR6; + __IO uint32_t EPINFOBASEADDR7; + __IO uint32_t EPINFOBASEADDR8; + __IO uint32_t EPINFOBASEADDR9; + __IO uint32_t EPINFOBASEADDR10; + __IO uint32_t EPINFOBASEADDR11; + __IO uint32_t EPINFOBASEADDR12; + __IO uint32_t EPINFOBASEADDR13; + __IO uint32_t EPINFOBASEADDR14; + __IO uint32_t EPINFOBASEADDR15; +} stc_usbhs_gdfifocfg_bit_t; + +typedef struct +{ + __IO uint32_t PTXFSTADDR0; + __IO uint32_t PTXFSTADDR1; + __IO uint32_t PTXFSTADDR2; + __IO uint32_t PTXFSTADDR3; + __IO uint32_t PTXFSTADDR4; + __IO uint32_t PTXFSTADDR5; + __IO uint32_t PTXFSTADDR6; + __IO uint32_t PTXFSTADDR7; + __IO uint32_t PTXFSTADDR8; + __IO uint32_t PTXFSTADDR9; + __IO uint32_t PTXFSTADDR10; + __IO uint32_t PTXFSTADDR11; + __IO uint32_t PTXFSTADDR12; + uint32_t RESERVED0[3]; + __IO uint32_t PTXFSIZE0; + __IO uint32_t PTXFSIZE1; + __IO uint32_t PTXFSIZE2; + __IO uint32_t PTXFSIZE3; + __IO uint32_t PTXFSIZE4; + __IO uint32_t PTXFSIZE5; + __IO uint32_t PTXFSIZE6; + __IO uint32_t PTXFSIZE7; + __IO uint32_t PTXFSIZE8; + __IO uint32_t PTXFSIZE9; + __IO uint32_t PTXFSIZE10; + __IO uint32_t PTXFSIZE11; + uint32_t RESERVED1[4]; +} stc_usbhs_hptxfsiz_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + uint32_t RESERVED0[3]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf1_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + uint32_t RESERVED0[3]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf2_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + uint32_t RESERVED0[2]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf3_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + uint32_t RESERVED0[2]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf4_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + uint32_t RESERVED0[2]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf5_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + uint32_t RESERVED0[2]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf6_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf7_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf8_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf9_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf10_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf11_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf12_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf13_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + uint32_t RESERVED0[1]; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED1[4]; +} stc_usbhs_dieptxf14_bit_t; + +typedef struct +{ + __IO uint32_t INEPNTXFSTADDR0; + __IO uint32_t INEPNTXFSTADDR1; + __IO uint32_t INEPNTXFSTADDR2; + __IO uint32_t INEPNTXFSTADDR3; + __IO uint32_t INEPNTXFSTADDR4; + __IO uint32_t INEPNTXFSTADDR5; + __IO uint32_t INEPNTXFSTADDR6; + __IO uint32_t INEPNTXFSTADDR7; + __IO uint32_t INEPNTXFSTADDR8; + __IO uint32_t INEPNTXFSTADDR9; + __IO uint32_t INEPNTXFSTADDR10; + __IO uint32_t INEPNTXFSTADDR11; + __IO uint32_t INEPNTXFSTADDR12; + __IO uint32_t INEPNTXFSTADDR13; + __IO uint32_t INEPNTXFSTADDR14; + __IO uint32_t INEPNTXFSTADDR15; + __IO uint32_t INEPNTXFDEP0; + __IO uint32_t INEPNTXFDEP1; + __IO uint32_t INEPNTXFDEP2; + __IO uint32_t INEPNTXFDEP3; + __IO uint32_t INEPNTXFDEP4; + __IO uint32_t INEPNTXFDEP5; + __IO uint32_t INEPNTXFDEP6; + __IO uint32_t INEPNTXFDEP7; + __IO uint32_t INEPNTXFDEP8; + __IO uint32_t INEPNTXFDEP9; + __IO uint32_t INEPNTXFDEP10; + __IO uint32_t INEPNTXFDEP11; + uint32_t RESERVED0[4]; +} stc_usbhs_dieptxf15_bit_t; + +typedef struct +{ + __IO uint32_t FSLSPCLKSEL0; + __IO uint32_t FSLSPCLKSEL1; + __IO uint32_t FSLSSUPP; + uint32_t RESERVED0[4]; + __IO uint32_t ENA32KHZS; + __IO uint32_t RESVALID0; + __IO uint32_t RESVALID1; + __IO uint32_t RESVALID2; + __IO uint32_t RESVALID3; + __IO uint32_t RESVALID4; + __IO uint32_t RESVALID5; + __IO uint32_t RESVALID6; + __IO uint32_t RESVALID7; + uint32_t RESERVED1[15]; + __IO uint32_t MODECHTIMEN; +} stc_usbhs_hcfg_bit_t; + +typedef struct +{ + __IO uint32_t FRINT0; + __IO uint32_t FRINT1; + __IO uint32_t FRINT2; + __IO uint32_t FRINT3; + __IO uint32_t FRINT4; + __IO uint32_t FRINT5; + __IO uint32_t FRINT6; + __IO uint32_t FRINT7; + __IO uint32_t FRINT8; + __IO uint32_t FRINT9; + __IO uint32_t FRINT10; + __IO uint32_t FRINT11; + __IO uint32_t FRINT12; + __IO uint32_t FRINT13; + __IO uint32_t FRINT14; + __IO uint32_t FRINT15; + __IO uint32_t HFIRRLDCTRL; + uint32_t RESERVED0[15]; +} stc_usbhs_hfir_bit_t; + +typedef struct +{ + __IO uint32_t FRNUM0; + __IO uint32_t FRNUM1; + __IO uint32_t FRNUM2; + __IO uint32_t FRNUM3; + __IO uint32_t FRNUM4; + __IO uint32_t FRNUM5; + __IO uint32_t FRNUM6; + __IO uint32_t FRNUM7; + __IO uint32_t FRNUM8; + __IO uint32_t FRNUM9; + __IO uint32_t FRNUM10; + __IO uint32_t FRNUM11; + __IO uint32_t FRNUM12; + __IO uint32_t FRNUM13; + __IO uint32_t FRNUM14; + __IO uint32_t FRNUM15; + __IO uint32_t FRREM0; + __IO uint32_t FRREM1; + __IO uint32_t FRREM2; + __IO uint32_t FRREM3; + __IO uint32_t FRREM4; + __IO uint32_t FRREM5; + __IO uint32_t FRREM6; + __IO uint32_t FRREM7; + __IO uint32_t FRREM8; + __IO uint32_t FRREM9; + __IO uint32_t FRREM10; + __IO uint32_t FRREM11; + __IO uint32_t FRREM12; + __IO uint32_t FRREM13; + __IO uint32_t FRREM14; + __IO uint32_t FRREM15; +} stc_usbhs_hfnum_bit_t; + +typedef struct +{ + __IO uint32_t PTXFSPCAVAIL0; + __IO uint32_t PTXFSPCAVAIL1; + __IO uint32_t PTXFSPCAVAIL2; + __IO uint32_t PTXFSPCAVAIL3; + __IO uint32_t PTXFSPCAVAIL4; + __IO uint32_t PTXFSPCAVAIL5; + __IO uint32_t PTXFSPCAVAIL6; + __IO uint32_t PTXFSPCAVAIL7; + __IO uint32_t PTXFSPCAVAIL8; + __IO uint32_t PTXFSPCAVAIL9; + __IO uint32_t PTXFSPCAVAIL10; + __IO uint32_t PTXFSPCAVAIL11; + __IO uint32_t PTXFSPCAVAIL12; + __IO uint32_t PTXFSPCAVAIL13; + __IO uint32_t PTXFSPCAVAIL14; + __IO uint32_t PTXFSPCAVAIL15; + __IO uint32_t PTXQSPCAVAIL0; + __IO uint32_t PTXQSPCAVAIL1; + __IO uint32_t PTXQSPCAVAIL2; + __IO uint32_t PTXQSPCAVAIL3; + __IO uint32_t PTXQSPCAVAIL4; + __IO uint32_t PTXQSPCAVAIL5; + __IO uint32_t PTXQSPCAVAIL6; + __IO uint32_t PTXQSPCAVAIL7; + __IO uint32_t PTXQTOP0; + __IO uint32_t PTXQTOP1; + __IO uint32_t PTXQTOP2; + __IO uint32_t PTXQTOP3; + __IO uint32_t PTXQTOP4; + __IO uint32_t PTXQTOP5; + __IO uint32_t PTXQTOP6; + __IO uint32_t PTXQTOP7; +} stc_usbhs_hptxsts_bit_t; + +typedef struct +{ + __IO uint32_t HAINT0; + __IO uint32_t HAINT1; + __IO uint32_t HAINT2; + __IO uint32_t HAINT3; + __IO uint32_t HAINT4; + __IO uint32_t HAINT5; + __IO uint32_t HAINT6; + __IO uint32_t HAINT7; + __IO uint32_t HAINT8; + __IO uint32_t HAINT9; + __IO uint32_t HAINT10; + __IO uint32_t HAINT11; + __IO uint32_t HAINT12; + __IO uint32_t HAINT13; + __IO uint32_t HAINT14; + __IO uint32_t HAINT15; + uint32_t RESERVED0[16]; +} stc_usbhs_haint_bit_t; + +typedef struct +{ + __IO uint32_t HAINTMSK0; + __IO uint32_t HAINTMSK1; + __IO uint32_t HAINTMSK2; + __IO uint32_t HAINTMSK3; + __IO uint32_t HAINTMSK4; + __IO uint32_t HAINTMSK5; + __IO uint32_t HAINTMSK6; + __IO uint32_t HAINTMSK7; + __IO uint32_t HAINTMSK8; + __IO uint32_t HAINTMSK9; + __IO uint32_t HAINTMSK10; + __IO uint32_t HAINTMSK11; + __IO uint32_t HAINTMSK12; + __IO uint32_t HAINTMSK13; + __IO uint32_t HAINTMSK14; + __IO uint32_t HAINTMSK15; + uint32_t RESERVED0[16]; +} stc_usbhs_haintmsk_bit_t; + +typedef struct +{ + __IO uint32_t PRTCONNSTS; + __IO uint32_t PRTCONNDET; + __IO uint32_t PRTENA; + __IO uint32_t PRTENCHNG; + __IO uint32_t PRTOVRCURRACT; + __IO uint32_t PRTOVRCURRCHNG; + __IO uint32_t PRTRES; + __IO uint32_t PRTSUSP; + __IO uint32_t PRTRST; + uint32_t RESERVED0[1]; + __IO uint32_t PRTLNSTS0; + __IO uint32_t PRTLNSTS1; + __IO uint32_t PRTPWR; + __IO uint32_t PRTTSTCTL0; + __IO uint32_t PRTTSTCTL1; + __IO uint32_t PRTTSTCTL2; + __IO uint32_t PRTTSTCTL3; + __IO uint32_t PRTSPD0; + __IO uint32_t PRTSPD1; + uint32_t RESERVED1[13]; +} stc_usbhs_hprt_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar0_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk0_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz0_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar1_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk1_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz1_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar2_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk2_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz2_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar3_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk3_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz3_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar4_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk4_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz4_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar5_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk5_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz5_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar6_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk6_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz6_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar7_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk7_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz7_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar8_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk8_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz8_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar9_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk9_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz9_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar10_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk10_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz10_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar11_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk11_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz11_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar12_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk12_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz12_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar13_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk13_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz13_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar14_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk14_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz14_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + __IO uint32_t EPNUM0; + __IO uint32_t EPNUM1; + __IO uint32_t EPNUM2; + __IO uint32_t EPNUM3; + __IO uint32_t EPDIR; + uint32_t RESERVED0[1]; + __IO uint32_t LSPDDEV; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t EC0; + __IO uint32_t EC1; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t ODDFRM; + __IO uint32_t CHDIS; + __IO uint32_t CHENA; +} stc_usbhs_hcchar15_bit_t; + +typedef struct +{ + __IO uint32_t PRTADDR0; + __IO uint32_t PRTADDR1; + __IO uint32_t PRTADDR2; + __IO uint32_t PRTADDR3; + __IO uint32_t PRTADDR4; + __IO uint32_t PRTADDR5; + __IO uint32_t PRTADDR6; + __IO uint32_t HUBADDR0; + __IO uint32_t HUBADDR1; + __IO uint32_t HUBADDR2; + __IO uint32_t HUBADDR3; + __IO uint32_t HUBADDR4; + __IO uint32_t HUBADDR5; + __IO uint32_t HUBADDR6; + __IO uint32_t XACTPOS0; + __IO uint32_t XACTPOS1; + __IO uint32_t COMPSPLT; + uint32_t RESERVED0[14]; + __IO uint32_t SPLTENA; +} stc_usbhs_hcsplt15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t CHHLTD; + __IO uint32_t AHBERR; + __IO uint32_t STALL; + __IO uint32_t NAK; + __IO uint32_t ACK; + __IO uint32_t NYET; + __IO uint32_t XACTERR; + __IO uint32_t BBLERR; + __IO uint32_t FRMOVRUN; + __IO uint32_t DATATGLERR; + uint32_t RESERVED0[21]; +} stc_usbhs_hcint15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t CHHLTDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t STALLMSK; + __IO uint32_t NAKMSK; + __IO uint32_t ACKMSK; + __IO uint32_t NYETMSK; + __IO uint32_t XACTERRMSK; + __IO uint32_t BBLERRMSK; + __IO uint32_t FRMOVRUNMSK; + __IO uint32_t DATATGLERRMSK; + uint32_t RESERVED0[21]; +} stc_usbhs_hcintmsk15_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t PID0; + __IO uint32_t PID1; + __IO uint32_t DOPNG; +} stc_usbhs_hctsiz15_bit_t; + +typedef struct +{ + __IO uint32_t DEVSPD0; + __IO uint32_t DEVSPD1; + __IO uint32_t NZSTSOUTHSHK; + __IO uint32_t ENA32KHZSUSP; + __IO uint32_t DEVADDR0; + __IO uint32_t DEVADDR1; + __IO uint32_t DEVADDR2; + __IO uint32_t DEVADDR3; + __IO uint32_t DEVADDR4; + __IO uint32_t DEVADDR5; + __IO uint32_t DEVADDR6; + __IO uint32_t PERFRINT0; + __IO uint32_t PERFRINT1; + uint32_t RESERVED0[1]; + __IO uint32_t XCVRDLY; + __IO uint32_t ERRATICINTMSK; + uint32_t RESERVED1[1]; + __IO uint32_t IPGISOCSUPT; + uint32_t RESERVED2[6]; + __IO uint32_t PERSCHINTVL0; + __IO uint32_t PERSCHINTVL1; + __IO uint32_t RESVALID0; + __IO uint32_t RESVALID1; + __IO uint32_t RESVALID2; + __IO uint32_t RESVALID3; + __IO uint32_t RESVALID4; + __IO uint32_t RESVALID5; +} stc_usbhs_dcfg_bit_t; + +typedef struct +{ + __IO uint32_t RMTWKUPSIG; + __IO uint32_t SFTDISCON; + __IO uint32_t GNPINNAKSTS; + __IO uint32_t GOUTNAKSTS; + __IO uint32_t TSTCTL0; + __IO uint32_t TSTCTL1; + __IO uint32_t TSTCTL2; + __IO uint32_t SGNPINNAK; + __IO uint32_t CGNPINNAK; + __IO uint32_t SGOUTNAK; + __IO uint32_t CGOUTNAK; + __IO uint32_t PWRONPRGDONE; + uint32_t RESERVED0[3]; + __IO uint32_t IGNRFRMNUM; + __IO uint32_t NAKONBBLE; + uint32_t RESERVED1[1]; + __IO uint32_t DEEPSLEEPBESLREJECT; + __IO uint32_t SERVINT; + uint32_t RESERVED2[12]; +} stc_usbhs_dctl_bit_t; + +typedef struct +{ + __IO uint32_t SUSPSTS; + __IO uint32_t ENUMSPD0; + __IO uint32_t ENUMSPD1; + __IO uint32_t ERRTICERR; + uint32_t RESERVED0[4]; + __IO uint32_t SOFFN0; + __IO uint32_t SOFFN1; + __IO uint32_t SOFFN2; + __IO uint32_t SOFFN3; + __IO uint32_t SOFFN4; + __IO uint32_t SOFFN5; + __IO uint32_t SOFFN6; + __IO uint32_t SOFFN7; + __IO uint32_t SOFFN8; + __IO uint32_t SOFFN9; + __IO uint32_t SOFFN10; + __IO uint32_t SOFFN11; + __IO uint32_t SOFFN12; + __IO uint32_t SOFFN13; + __IO uint32_t DEVLNSTS0; + __IO uint32_t DEVLNSTS1; + uint32_t RESERVED1[8]; +} stc_usbhs_dsts_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t EPDISBLDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t TIMEOUTMSK; + __IO uint32_t INTKNTXFEMPMSK; + __IO uint32_t INTKNEPMISMSK; + __IO uint32_t INEPNAKEFFMSK; + uint32_t RESERVED0[1]; + __IO uint32_t TXFIFOUNDRNMSK; + uint32_t RESERVED1[4]; + __IO uint32_t NAKMSK; + uint32_t RESERVED2[18]; +} stc_usbhs_diepmsk_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t EPDISBLDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t SETUPMSK; + __IO uint32_t OUTTKNEPDISMSK; + __IO uint32_t STSPHSERCVDMSK; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERRMSK; + uint32_t RESERVED1[3]; + __IO uint32_t BBLEERRMSK; + __IO uint32_t NAKMSK; + __IO uint32_t NYETMSK; + uint32_t RESERVED2[17]; +} stc_usbhs_doepmsk_bit_t; + +typedef struct +{ + __IO uint32_t INEPINT0; + __IO uint32_t INEPINT1; + __IO uint32_t INEPINT2; + __IO uint32_t INEPINT3; + __IO uint32_t INEPINT4; + __IO uint32_t INEPINT5; + __IO uint32_t INEPINT6; + __IO uint32_t INEPINT7; + __IO uint32_t INEPINT8; + __IO uint32_t INEPINT9; + __IO uint32_t INEPINT10; + __IO uint32_t INEPINT11; + __IO uint32_t INEPINT12; + __IO uint32_t INEPINT13; + __IO uint32_t INEPINT14; + __IO uint32_t INEPINT15; + __IO uint32_t OUTEPINT0; + __IO uint32_t OUTEPINT1; + __IO uint32_t OUTEPINT2; + __IO uint32_t OUTEPINT3; + __IO uint32_t OUTEPINT4; + __IO uint32_t OUTEPINT5; + __IO uint32_t OUTEPINT6; + __IO uint32_t OUTEPINT7; + __IO uint32_t OUTEPINT8; + __IO uint32_t OUTEPINT9; + __IO uint32_t OUTEPINT10; + __IO uint32_t OUTEPINT11; + __IO uint32_t OUTEPINT12; + __IO uint32_t OUTEPINT13; + __IO uint32_t OUTEPINT14; + __IO uint32_t OUTEPINT15; +} stc_usbhs_daint_bit_t; + +typedef struct +{ + __IO uint32_t INEPMSK0; + __IO uint32_t INEPMSK1; + __IO uint32_t INEPMSK2; + __IO uint32_t INEPMSK3; + __IO uint32_t INEPMSK4; + __IO uint32_t INEPMSK5; + __IO uint32_t INEPMSK6; + __IO uint32_t INEPMSK7; + __IO uint32_t INEPMSK8; + __IO uint32_t INEPMSK9; + __IO uint32_t INEPMSK10; + __IO uint32_t INEPMSK11; + __IO uint32_t INEPMSK12; + __IO uint32_t INEPMSK13; + __IO uint32_t INEPMSK14; + __IO uint32_t INEPMSK15; + __IO uint32_t OUTEPMSK0; + __IO uint32_t OUTEPMSK1; + __IO uint32_t OUTEPMSK2; + __IO uint32_t OUTEPMSK3; + __IO uint32_t OUTEPMSK4; + __IO uint32_t OUTEPMSK5; + __IO uint32_t OUTEPMSK6; + __IO uint32_t OUTEPMSK7; + __IO uint32_t OUTEPMSK8; + __IO uint32_t OUTEPMSK9; + __IO uint32_t OUTEPMSK10; + __IO uint32_t OUTEPMSK11; + __IO uint32_t OUTEPMSK12; + __IO uint32_t OUTEPMSK13; + __IO uint32_t OUTEPMSK14; + __IO uint32_t OUTEPMSK15; +} stc_usbhs_daintmsk_bit_t; + +typedef struct +{ + __IO uint32_t NONISOTHREN; + __IO uint32_t ISOTHREN; + __IO uint32_t TXTHRLEN0; + __IO uint32_t TXTHRLEN1; + __IO uint32_t TXTHRLEN2; + __IO uint32_t TXTHRLEN3; + __IO uint32_t TXTHRLEN4; + __IO uint32_t TXTHRLEN5; + __IO uint32_t TXTHRLEN6; + __IO uint32_t TXTHRLEN7; + __IO uint32_t TXTHRLEN8; + __IO uint32_t AHBTHRRATIO0; + __IO uint32_t AHBTHRRATIO1; + uint32_t RESERVED0[3]; + __IO uint32_t RXTHREN; + __IO uint32_t RXTHRLEN0; + __IO uint32_t RXTHRLEN1; + __IO uint32_t RXTHRLEN2; + __IO uint32_t RXTHRLEN3; + __IO uint32_t RXTHRLEN4; + __IO uint32_t RXTHRLEN5; + __IO uint32_t RXTHRLEN6; + __IO uint32_t RXTHRLEN7; + __IO uint32_t RXTHRLEN8; + uint32_t RESERVED1[1]; + __IO uint32_t ARBPRKEN; + uint32_t RESERVED2[4]; +} stc_usbhs_dthrctl_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFEMPMSK0; + __IO uint32_t INEPTXFEMPMSK1; + __IO uint32_t INEPTXFEMPMSK2; + __IO uint32_t INEPTXFEMPMSK3; + __IO uint32_t INEPTXFEMPMSK4; + __IO uint32_t INEPTXFEMPMSK5; + __IO uint32_t INEPTXFEMPMSK6; + __IO uint32_t INEPTXFEMPMSK7; + __IO uint32_t INEPTXFEMPMSK8; + __IO uint32_t INEPTXFEMPMSK9; + __IO uint32_t INEPTXFEMPMSK10; + __IO uint32_t INEPTXFEMPMSK11; + __IO uint32_t INEPTXFEMPMSK12; + __IO uint32_t INEPTXFEMPMSK13; + __IO uint32_t INEPTXFEMPMSK14; + __IO uint32_t INEPTXFEMPMSK15; + uint32_t RESERVED0[16]; +} stc_usbhs_diepempmsk_bit_t; + +typedef struct +{ + __IO uint32_t ECHINEPINT0; + __IO uint32_t ECHINEPINT1; + __IO uint32_t ECHINEPINT2; + __IO uint32_t ECHINEPINT3; + __IO uint32_t ECHINEPINT4; + __IO uint32_t ECHINEPINT5; + __IO uint32_t ECHINEPINT6; + __IO uint32_t ECHINEPINT7; + __IO uint32_t ECHINEPINT8; + __IO uint32_t ECHINEPINT9; + __IO uint32_t ECHINEPINT10; + __IO uint32_t ECHINEPINT11; + __IO uint32_t ECHINEPINT12; + __IO uint32_t ECHINEPINT13; + __IO uint32_t ECHINEPINT14; + __IO uint32_t ECHINEPINT15; + __IO uint32_t ECHOUTEPINT0; + __IO uint32_t ECHOUTEPINT1; + __IO uint32_t ECHOUTEPINT2; + __IO uint32_t ECHOUTEPINT3; + __IO uint32_t ECHOUTEPINT4; + __IO uint32_t ECHOUTEPINT5; + __IO uint32_t ECHOUTEPINT6; + __IO uint32_t ECHOUTEPINT7; + __IO uint32_t ECHOUTEPINT8; + __IO uint32_t ECHOUTEPINT9; + __IO uint32_t ECHOUTEPINT10; + __IO uint32_t ECHOUTEPINT11; + __IO uint32_t ECHOUTEPINT12; + __IO uint32_t ECHOUTEPINT13; + __IO uint32_t ECHOUTEPINT14; + __IO uint32_t ECHOUTEPINT15; +} stc_usbhs_deachint_bit_t; + +typedef struct +{ + __IO uint32_t ECHINEPMSK0; + __IO uint32_t ECHINEPMSK1; + __IO uint32_t ECHINEPMSK2; + __IO uint32_t ECHINEPMSK3; + __IO uint32_t ECHINEPMSK4; + __IO uint32_t ECHINEPMSK5; + __IO uint32_t ECHINEPMSK6; + __IO uint32_t ECHINEPMSK7; + __IO uint32_t ECHINEPMSK8; + __IO uint32_t ECHINEPMSK9; + __IO uint32_t ECHINEPMSK10; + __IO uint32_t ECHINEPMSK11; + __IO uint32_t ECHINEPMSK12; + __IO uint32_t ECHINEPMSK13; + __IO uint32_t ECHINEPMSK14; + __IO uint32_t ECHINEPMSK15; + __IO uint32_t ECHOUTEPMSK0; + __IO uint32_t ECHOUTEPMSK1; + __IO uint32_t ECHOUTEPMSK2; + __IO uint32_t ECHOUTEPMSK3; + __IO uint32_t ECHOUTEPMSK4; + __IO uint32_t ECHOUTEPMSK5; + __IO uint32_t ECHOUTEPMSK6; + __IO uint32_t ECHOUTEPMSK7; + __IO uint32_t ECHOUTEPMSK8; + __IO uint32_t ECHOUTEPMSK9; + __IO uint32_t ECHOUTEPMSK10; + __IO uint32_t ECHOUTEPMSK11; + __IO uint32_t ECHOUTEPMSK12; + __IO uint32_t ECHOUTEPMSK13; + __IO uint32_t ECHOUTEPMSK14; + __IO uint32_t ECHOUTEPMSK15; +} stc_usbhs_deachintmsk_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t EPDISBLDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t TIMEOUTMSK; + __IO uint32_t INTKNTXFEMPMSK; + __IO uint32_t INTKNEPMISMSK; + __IO uint32_t INEPNAKEFFMSK; + uint32_t RESERVED0[1]; + __IO uint32_t TXFIFOUNDRNMSK; + uint32_t RESERVED1[4]; + __IO uint32_t NAKMSK; + uint32_t RESERVED2[18]; +} stc_usbhs_diepeachmsk1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPLMSK; + __IO uint32_t EPDISBLDMSK; + __IO uint32_t AHBERRMSK; + __IO uint32_t SETUPMSK; + __IO uint32_t OUTTKNEPDISMSK; + __IO uint32_t STSPHSRCVDMSK; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERRMSK; + uint32_t RESERVED1[3]; + __IO uint32_t BBLEERRMSK; + __IO uint32_t NAKMSK; + __IO uint32_t NYETMSK; + uint32_t RESERVED2[17]; +} stc_usbhs_doepeachmsk1_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + uint32_t RESERVED0[13]; + __IO uint32_t USBACTEP; + uint32_t RESERVED1[1]; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED2[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED3[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint0_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + uint32_t RESERVED0[12]; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + uint32_t RESERVED1[11]; +} stc_usbhs_dieptsiz0_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts0_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint1_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz1_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts1_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint2_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz2_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts2_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint3_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz3_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts3_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint4_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz4_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts4_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint5_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz5_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts5_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint6_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz6_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts6_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint7_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz7_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts7_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint8_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz8_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts8_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint9_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz9_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts9_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint10_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz10_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts10_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint11_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz11_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts11_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint12_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz12_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts12_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint13_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz13_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts13_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint14_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz14_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts14_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + uint32_t RESERVED1[1]; + __IO uint32_t STALL; + __IO uint32_t TXFNUM0; + __IO uint32_t TXFNUM1; + __IO uint32_t TXFNUM2; + __IO uint32_t TXFNUM3; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_diepctl15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t TIMEOUT; + __IO uint32_t INTKNTXFEMP; + __IO uint32_t INTKNEPMIS; + __IO uint32_t INEPNAKEFF; + __IO uint32_t TXFEMP; + __IO uint32_t TXFIFOUNDRN; + __IO uint32_t BNAINTR; + uint32_t RESERVED0[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + uint32_t RESERVED1[17]; +} stc_usbhs_diepint15_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t MC0; + __IO uint32_t MC1; + uint32_t RESERVED0[1]; +} stc_usbhs_dieptsiz15_bit_t; + +typedef struct +{ + __IO uint32_t INEPTXFSPCAVAIL0; + __IO uint32_t INEPTXFSPCAVAIL1; + __IO uint32_t INEPTXFSPCAVAIL2; + __IO uint32_t INEPTXFSPCAVAIL3; + __IO uint32_t INEPTXFSPCAVAIL4; + __IO uint32_t INEPTXFSPCAVAIL5; + __IO uint32_t INEPTXFSPCAVAIL6; + __IO uint32_t INEPTXFSPCAVAIL7; + __IO uint32_t INEPTXFSPCAVAIL8; + __IO uint32_t INEPTXFSPCAVAIL9; + __IO uint32_t INEPTXFSPCAVAIL10; + __IO uint32_t INEPTXFSPCAVAIL11; + __IO uint32_t INEPTXFSPCAVAIL12; + __IO uint32_t INEPTXFSPCAVAIL13; + __IO uint32_t INEPTXFSPCAVAIL14; + __IO uint32_t INEPTXFSPCAVAIL15; + uint32_t RESERVED0[16]; +} stc_usbhs_dtxfsts15_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + uint32_t RESERVED0[13]; + __IO uint32_t USBACTEP; + uint32_t RESERVED1[1]; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED2[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + uint32_t RESERVED3[2]; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl0_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint0_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + uint32_t RESERVED0[12]; + __IO uint32_t PKTCNT; + uint32_t RESERVED1[9]; + __IO uint32_t SUPCNT0; + __IO uint32_t SUPCNT1; + uint32_t RESERVED2[1]; +} stc_usbhs_doeptsiz0_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl1_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint1_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz1_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl2_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint2_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz2_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl3_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint3_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz3_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl4_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint4_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz4_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl5_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint5_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz5_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl6_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint6_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz6_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl7_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint7_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz7_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl8_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint8_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz8_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl9_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint9_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz9_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl10_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint10_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz10_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl11_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint11_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz11_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl12_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint12_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz12_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl13_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint13_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz13_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl14_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint14_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz14_bit_t; + +typedef struct +{ + __IO uint32_t MPS0; + __IO uint32_t MPS1; + __IO uint32_t MPS2; + __IO uint32_t MPS3; + __IO uint32_t MPS4; + __IO uint32_t MPS5; + __IO uint32_t MPS6; + __IO uint32_t MPS7; + __IO uint32_t MPS8; + __IO uint32_t MPS9; + __IO uint32_t MPS10; + uint32_t RESERVED0[4]; + __IO uint32_t USBACTEP; + __IO uint32_t DPID; + __IO uint32_t NAKSTS; + __IO uint32_t EPTYPE0; + __IO uint32_t EPTYPE1; + __IO uint32_t SNP; + __IO uint32_t STALL; + uint32_t RESERVED1[4]; + __IO uint32_t CNAK; + __IO uint32_t SNAK; + __IO uint32_t SETD0PID; + __IO uint32_t SETD1PID; + __IO uint32_t EPDIS; + __IO uint32_t EPENA; +} stc_usbhs_doepctl15_bit_t; + +typedef struct +{ + __IO uint32_t XFERCOMPL; + __IO uint32_t EPDISBLD; + __IO uint32_t AHBERR; + __IO uint32_t SETUP; + __IO uint32_t OUTTKNEPDIS; + __IO uint32_t STSPHSERCVD; + __IO uint32_t BACK2BACKSETUP; + uint32_t RESERVED0[1]; + __IO uint32_t OUTPKTERR; + __IO uint32_t BNAINTR; + uint32_t RESERVED1[1]; + __IO uint32_t PKTDRPSTS; + __IO uint32_t BBLEERR; + __IO uint32_t NAKINTRPT; + __IO uint32_t NYETINTRPT; + __IO uint32_t STUPPKTRCVD; + uint32_t RESERVED2[16]; +} stc_usbhs_doepint15_bit_t; + +typedef struct +{ + __IO uint32_t XFERSIZE0; + __IO uint32_t XFERSIZE1; + __IO uint32_t XFERSIZE2; + __IO uint32_t XFERSIZE3; + __IO uint32_t XFERSIZE4; + __IO uint32_t XFERSIZE5; + __IO uint32_t XFERSIZE6; + __IO uint32_t XFERSIZE7; + __IO uint32_t XFERSIZE8; + __IO uint32_t XFERSIZE9; + __IO uint32_t XFERSIZE10; + __IO uint32_t XFERSIZE11; + __IO uint32_t XFERSIZE12; + __IO uint32_t XFERSIZE13; + __IO uint32_t XFERSIZE14; + __IO uint32_t XFERSIZE15; + __IO uint32_t XFERSIZE16; + __IO uint32_t XFERSIZE17; + __IO uint32_t XFERSIZE18; + __IO uint32_t PKTCNT0; + __IO uint32_t PKTCNT1; + __IO uint32_t PKTCNT2; + __IO uint32_t PKTCNT3; + __IO uint32_t PKTCNT4; + __IO uint32_t PKTCNT5; + __IO uint32_t PKTCNT6; + __IO uint32_t PKTCNT7; + __IO uint32_t PKTCNT8; + __IO uint32_t PKTCNT9; + __IO uint32_t RXDPID0; + __IO uint32_t RXDPID1; + uint32_t RESERVED0[1]; +} stc_usbhs_doeptsiz15_bit_t; + +typedef struct +{ + __IO uint32_t STOPPCLK; + __IO uint32_t GATEHCLK; + __IO uint32_t PWRCLMP; + __IO uint32_t RSTPDWNMODULE; + uint32_t RESERVED0[1]; + __IO uint32_t ENBL_L1GATING; + __IO uint32_t PHYSLEEP; + __IO uint32_t L1SUSPENDED; + __IO uint32_t RESETAFTERSUSP; + uint32_t RESERVED1[23]; +} stc_usbhs_pcgcctl_bit_t; + +typedef struct +{ + __IO uint32_t PERI0; + __IO uint32_t PERI1; + uint32_t RESERVED0[2]; + __IO uint32_t CKS0; + __IO uint32_t CKS1; + __IO uint32_t CKS2; + __IO uint32_t CKS3; + __IO uint32_t WDPT0; + __IO uint32_t WDPT1; + __IO uint32_t WDPT2; + __IO uint32_t WDPT3; + uint32_t RESERVED1[4]; + __IO uint32_t SLPOFF; + uint32_t RESERVED2[14]; + __IO uint32_t ITS; +} stc_wdt_cr_bit_t; + +typedef struct +{ + uint32_t RESERVED0[16]; + __IO uint32_t UDF; + __IO uint32_t REF; + uint32_t RESERVED1[14]; +} stc_wdt_sr_bit_t; + + +typedef struct +{ + stc_adc_str_bit_t STR_b; + uint32_t RESERVED0[8]; + stc_adc_cr0_bit_t CR0_b; + stc_adc_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_adc_trgsr_bit_t TRGSR_b; + stc_adc_chselra_bit_t CHSELRA_b; + stc_adc_chselrb_bit_t CHSELRB_b; + stc_adc_avchselr_bit_t AVCHSELR_b; + stc_adc_exchselr_bit_t EXCHSELR_b; + uint32_t RESERVED2[8]; + stc_adc_shcr_bit_t SHCR_b; + uint32_t RESERVED3[224]; + stc_adc_chmuxr0_bit_t CHMUXR0_b; + stc_adc_chmuxr1_bit_t CHMUXR1_b; + stc_adc_chmuxr2_bit_t CHMUXR2_b; + stc_adc_chmuxr3_bit_t CHMUXR3_b; + uint32_t RESERVED4[32]; + stc_adc_isr_bit_t ISR_b; + stc_adc_icr_bit_t ICR_b; + stc_adc_isclrr_bit_t ISCLRR_b; + uint32_t RESERVED5[40]; + stc_adc_synccr_bit_t SYNCCR_b; + uint32_t RESERVED6[656]; + stc_adc_awdcr_bit_t AWDCR_b; + stc_adc_awdsr_bit_t AWDSR_b; + stc_adc_awdsclrr_bit_t AWDSCLRR_b; + uint32_t RESERVED7[32]; + stc_adc_awd0chsr_bit_t AWD0CHSR_b; + uint32_t RESERVED8[48]; + stc_adc_awd1chsr_bit_t AWD1CHSR_b; + uint32_t RESERVED9[112]; + stc_adc_pgacr1_bit_t PGACR1_b; + stc_adc_pgacr2_bit_t PGACR2_b; + stc_adc_pgacr3_bit_t PGACR3_b; + uint32_t RESERVED10[8]; + stc_adc_pgavssenr_bit_t PGAVSSENR_b; +} bM4_ADC_TypeDef; + +typedef struct +{ + stc_aes_cr_bit_t CR_b; +} bM4_AES_TypeDef; + +typedef struct +{ + stc_aos_int_sfttrg_bit_t INT_SFTTRG_b; + stc_aos_dcu_1_trgsel_bit_t DCU_1_TRGSEL_b; + stc_aos_dcu_2_trgsel_bit_t DCU_2_TRGSEL_b; + stc_aos_dcu_3_trgsel_bit_t DCU_3_TRGSEL_b; + stc_aos_dcu_4_trgsel_bit_t DCU_4_TRGSEL_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL0_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL1_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL2_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL3_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL4_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL5_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL6_b; + stc_aos_dma_1_trgsel_bit_t DMA_1_TRGSEL7_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL0_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL1_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL2_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL3_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL4_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL5_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL6_b; + stc_aos_dma_2_trgsel_bit_t DMA_2_TRGSEL7_b; + stc_aos_dma_trgselrc_bit_t DMA_TRGSELRC_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR1_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR2_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR3_b; + stc_aos_tmr6_htssr_bit_t TMR6_HTSSR4_b; + stc_aos_port_pevnttrgsr12_bit_t PORT_PEVNTTRGSR12_b; + stc_aos_port_pevnttrgsr34_bit_t PORT_PEVNTTRGSR34_b; + stc_aos_tmr0_htssr_bit_t TMR0_HTSSR_b; + stc_aos_tmr2_htssr_bit_t TMR2_HTSSR_b; + stc_aos_hash_itrgsela_bit_t HASH_ITRGSELA_b; + stc_aos_hash_itrgselb_bit_t HASH_ITRGSELB_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR0_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR1_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR2_b; + stc_aos_tmra_htssr_bit_t TMRA_HTSSR3_b; + stc_aos_ots_trg_bit_t OTS_TRG_b; + stc_aos_adc_1_itrgselr_bit_t ADC_1_ITRGSELR0_b; + stc_aos_adc_1_itrgselr_bit_t ADC_1_ITRGSELR1_b; + stc_aos_adc_2_itrgselr_bit_t ADC_2_ITRGSELR0_b; + stc_aos_adc_2_itrgselr_bit_t ADC_2_ITRGSELR1_b; + stc_aos_adc_3_itrgselr_bit_t ADC_3_ITRGSELR0_b; + stc_aos_adc_3_itrgselr_bit_t ADC_3_ITRGSELR1_b; + uint32_t RESERVED0[672]; + stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR1_b; + stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR1_b; + stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR1_b; + stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR1_b; + stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR1_b; + stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR1_b; + stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL1_b; + stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR2_b; + stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR2_b; + stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR2_b; + stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR2_b; + stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR2_b; + stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR2_b; + stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL2_b; + stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR3_b; + stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR3_b; + stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR3_b; + stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR3_b; + stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR3_b; + stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR3_b; + stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL3_b; + stc_aos_gpio_pevntdirr_bit_t GPIO_PEVNTDIRR4_b; + stc_aos_gpio_pevntidr_bit_t GPIO_PEVNTIDR4_b; + stc_aos_gpio_pevntodr_bit_t GPIO_PEVNTODR4_b; + stc_aos_gpio_pevntorr_bit_t GPIO_PEVNTORR4_b; + stc_aos_gpio_pevntosr_bit_t GPIO_PEVNTOSR4_b; + stc_aos_gpio_pevntrisr_bit_t GPIO_PEVNTRISR4_b; + stc_aos_gpio_pevntfal_bit_t GPIO_PEVNTFAL4_b; + stc_aos_gpio_pevntnfcr_bit_t GPIO_PEVNTNFCR_b; +} bM4_AOS_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[1280]; + stc_can_cfg_stat_bit_t CFG_STAT_b; + stc_can_tcmd_bit_t TCMD_b; + stc_can_tctrl_bit_t TCTRL_b; + stc_can_rctrl_bit_t RCTRL_b; + stc_can_rtie_bit_t RTIE_b; + stc_can_rtif_bit_t RTIF_b; + stc_can_errint_bit_t ERRINT_b; + stc_can_limit_bit_t LIMIT_b; + stc_can_sbt_bit_t SBT_b; + stc_can_fbt_bit_t FBT_b; + stc_can_ealcap_bit_t EALCAP_b; + stc_can_tdc_bit_t TDC_b; + uint32_t RESERVED1[16]; + stc_can_acfctrl_bit_t ACFCTRL_b; + uint32_t RESERVED2[8]; + stc_can_acfen_bit_t ACFEN_b; + stc_can_acf_bit_t ACF_b; + uint32_t RESERVED3[16]; + stc_can_tbslot_bit_t TBSLOT_b; + stc_can_ttcfg_bit_t TTCFG_b; + stc_can_ref_msg_bit_t REF_MSG_b; + stc_can_trg_cfg_bit_t TRG_CFG_b; +} bM4_CAN_TypeDef; + +typedef struct +{ + stc_cmp_mdr_bit_t MDR_b; + stc_cmp_fir_bit_t FIR_b; + stc_cmp_ocr_bit_t OCR_b; + stc_cmp_pmsr_bit_t PMSR_b; + stc_cmp_twsr_bit_t TWSR_b; + stc_cmp_twpr_bit_t TWPR_b; + stc_cmp_visr_bit_t VISR_b; +} bM4_CMP_TypeDef; + +typedef struct +{ + stc_cmu_xtal32cr_bit_t XTAL32CR_b; + uint32_t RESERVED0[216]; + stc_cmu_lrccr_bit_t LRCCR_b; + uint32_t RESERVED1[24]; + stc_cmu_rtclrccr_bit_t RTCLRCCR_b; + uint32_t RESERVED2[17080]; + stc_cmu_xtalcfgr_bit_t XTALCFGR_b; + uint32_t RESERVED3[236936]; + stc_cmu_pllhcr_bit_t PLLHCR_b; + uint32_t RESERVED4[24]; + stc_cmu_pllacr_bit_t PLLACR_b; + uint32_t RESERVED5[24]; + stc_cmu_xtalcr_bit_t XTALCR_b; + uint32_t RESERVED6[24]; + stc_cmu_hrccr_bit_t HRCCR_b; + uint32_t RESERVED7[8]; + stc_cmu_mrccr_bit_t MRCCR_b; + uint32_t RESERVED8[24]; + stc_cmu_oscstbsr_bit_t OSCSTBSR_b; + stc_cmu_mco1cfgr_bit_t MCO1CFGR_b; + stc_cmu_mco2cfgr_bit_t MCO2CFGR_b; + stc_cmu_tpiuckcfgr_bit_t TPIUCKCFGR_b; + stc_cmu_xtalstdcr_bit_t XTALSTDCR_b; + stc_cmu_xtalstdsr_bit_t XTALSTDSR_b; + uint32_t RESERVED9[1520]; + stc_cmu_pllhcfgr_bit_t PLLHCFGR_b; +} bM4_CMU_TypeDef; + +typedef struct +{ + stc_crc_cr_bit_t CR_b; +} bM4_CRC_TypeDef; + +typedef struct +{ + stc_ctc_cr1_bit_t CR1_b; + stc_ctc_cr2_bit_t CR2_b; + stc_ctc_str_bit_t STR_b; +} bM4_CTC_TypeDef; + +typedef struct +{ + stc_dac_dadr1_bit_t DADR1_b; + stc_dac_dadr2_bit_t DADR2_b; + stc_dac_dacr_bit_t DACR_b; + stc_dac_daadpcr_bit_t DAADPCR_b; + uint32_t RESERVED0[160]; + stc_dac_daocr_bit_t DAOCR_b; +} bM4_DAC_TypeDef; + +typedef struct +{ + stc_dcu_ctl_bit_t CTL_b; + stc_dcu_flag_bit_t FLAG_b; + uint32_t RESERVED0[96]; + stc_dcu_flagclr_bit_t FLAGCLR_b; + stc_dcu_intevtsel_bit_t INTEVTSEL_b; +} bM4_DCU_TypeDef; + +typedef struct +{ + stc_dma_en_bit_t EN_b; + stc_dma_intstat0_bit_t INTSTAT0_b; + stc_dma_intstat1_bit_t INTSTAT1_b; + stc_dma_intmask0_bit_t INTMASK0_b; + stc_dma_intmask1_bit_t INTMASK1_b; + stc_dma_intclr0_bit_t INTCLR0_b; + stc_dma_intclr1_bit_t INTCLR1_b; + stc_dma_chen_bit_t CHEN_b; + stc_dma_reqstat_bit_t REQSTAT_b; + stc_dma_chstat_bit_t CHSTAT_b; + uint32_t RESERVED0[32]; + stc_dma_rcfgctl_bit_t RCFGCTL_b; + uint32_t RESERVED1[32]; + stc_dma_chenclr_bit_t CHENCLR_b; + uint32_t RESERVED2[384]; + stc_dma_chctl_bit_t CHCTL0_b; + uint32_t RESERVED3[512]; + stc_dma_chctl_bit_t CHCTL1_b; + uint32_t RESERVED4[512]; + stc_dma_chctl_bit_t CHCTL2_b; + uint32_t RESERVED5[512]; + stc_dma_chctl_bit_t CHCTL3_b; + uint32_t RESERVED6[512]; + stc_dma_chctl_bit_t CHCTL4_b; + uint32_t RESERVED7[512]; + stc_dma_chctl_bit_t CHCTL5_b; + uint32_t RESERVED8[512]; + stc_dma_chctl_bit_t CHCTL6_b; + uint32_t RESERVED9[512]; + stc_dma_chctl_bit_t CHCTL7_b; +} bM4_DMA_TypeDef; + +typedef struct +{ + stc_dvp_ctr_bit_t CTR_b; + uint32_t RESERVED0[32]; + stc_dvp_str_bit_t STR_b; + stc_dvp_ier_bit_t IER_b; +} bM4_DVP_TypeDef; + +typedef struct +{ + stc_efm_faprt_bit_t FAPRT_b; + uint32_t RESERVED0[128]; + stc_efm_fstp_bit_t FSTP_b; + stc_efm_frmc_bit_t FRMC_b; + stc_efm_fwmc_bit_t FWMC_b; + stc_efm_fsr_bit_t FSR_b; + stc_efm_fsclr_bit_t FSCLR_b; + stc_efm_fite_bit_t FITE_b; + stc_efm_fswp_bit_t FSWP_b; + uint32_t RESERVED1[1696]; + stc_mmf_remcr0_bit_t REMCR0_b; + stc_mmf_remcr1_bit_t REMCR1_b; + uint32_t RESERVED2[928]; + stc_efm_wlock_bit_t WLOCK_b; +} bM4_EFM_TypeDef; + +typedef struct +{ + stc_emb_ctl1_bit_t CTL1_b; + stc_emb_ctl2_bit_t CTL2_b; + stc_emb_soe_bit_t SOE_b; + stc_emb_stat_bit_t STAT_b; + stc_emb_statclr_bit_t STATCLR_b; + stc_emb_inten_bit_t INTEN_b; + stc_emb_rlssel_bit_t RLSSEL_b; +} bM4_EMB_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[172160]; + stc_eth_mac_ifconfr_bit_t MAC_IFCONFR_b; + uint32_t RESERVED1[352096]; + stc_eth_mac_configr_bit_t MAC_CONFIGR_b; + stc_eth_mac_fltctlr_bit_t MAC_FLTCTLR_b; + uint32_t RESERVED2[64]; + stc_eth_mac_smiaddr_bit_t MAC_SMIADDR_b; + uint32_t RESERVED3[32]; + stc_eth_mac_floctlr_bit_t MAC_FLOCTLR_b; + stc_eth_mac_vtafltr_bit_t MAC_VTAFLTR_b; + uint32_t RESERVED4[32]; + stc_eth_mac_macstsr_bit_t MAC_MACSTSR_b; + uint32_t RESERVED5[32]; + stc_eth_mac_pmtctlr_bit_t MAC_PMTCTLR_b; + uint32_t RESERVED6[64]; + stc_eth_mac_intstsr_bit_t MAC_INTSTSR_b; + stc_eth_mac_intmskr_bit_t MAC_INTMSKR_b; + stc_eth_mac_macadhr0_bit_t MAC_MACADHR0_b; + uint32_t RESERVED7[32]; + stc_eth_mac_macadhr1_bit_t MAC_MACADHR1_b; + uint32_t RESERVED8[32]; + stc_eth_mac_macadhr2_bit_t MAC_MACADHR2_b; + uint32_t RESERVED9[32]; + stc_eth_mac_macadhr3_bit_t MAC_MACADHR3_b; + uint32_t RESERVED10[32]; + stc_eth_mac_macadhr4_bit_t MAC_MACADHR4_b; + uint32_t RESERVED11[1248]; + stc_eth_mmc_mmcctlr_bit_t MMC_MMCCTLR_b; + stc_eth_mmc_revstsr_bit_t MMC_REVSTSR_b; + stc_eth_mmc_trsstsr_bit_t MMC_TRSSTSR_b; + stc_eth_mmc_ritctlr_bit_t MMC_RITCTLR_b; + stc_eth_mmc_titctlr_bit_t MMC_TITCTLR_b; + uint32_t RESERVED12[5984]; + stc_eth_mac_l34ctlr_bit_t MAC_L34CTLR_b; + uint32_t RESERVED13[3072]; + stc_eth_mac_vtactlr_bit_t MAC_VTACTLR_b; + uint32_t RESERVED14[3008]; + stc_eth_ptp_tspctlr_bit_t PTP_TSPCTLR_b; + uint32_t RESERVED15[128]; + stc_eth_ptp_tmunser_bit_t PTP_TMUNSER_b; + uint32_t RESERVED16[128]; + stc_eth_ptp_tspstsr_bit_t PTP_TSPSTSR_b; + stc_eth_ptp_ppsctlr_bit_t PTP_PPSCTLR_b; + uint32_t RESERVED17[18048]; + stc_eth_dma_busmodr_bit_t DMA_BUSMODR_b; + uint32_t RESERVED18[128]; + stc_eth_dma_dmastsr_bit_t DMA_DMASTSR_b; + stc_eth_dma_oprmodr_bit_t DMA_OPRMODR_b; + stc_eth_dma_intenar_bit_t DMA_INTENAR_b; + stc_eth_dma_rfrcntr_bit_t DMA_RFRCNTR_b; +} bM4_ETH_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[96]; + stc_fcm_str_bit_t STR_b; + uint32_t RESERVED1[32]; + stc_fcm_rccr_bit_t RCCR_b; + stc_fcm_rier_bit_t RIER_b; + stc_fcm_sr_bit_t SR_b; + stc_fcm_clr_bit_t CLR_b; +} bM4_FCM_TypeDef; + +typedef struct +{ + stc_fmac_enr_bit_t ENR_b; + uint32_t RESERVED0[32]; + stc_fmac_ier_bit_t IER_b; + uint32_t RESERVED1[96]; + stc_fmac_str_bit_t STR_b; +} bM4_FMAC_TypeDef; + +typedef struct +{ + stc_gpio_pidra_bit_t PIDRA_b; + uint32_t RESERVED0[16]; + stc_gpio_podra_bit_t PODRA_b; + stc_gpio_poera_bit_t POERA_b; + stc_gpio_posra_bit_t POSRA_b; + stc_gpio_porra_bit_t PORRA_b; + stc_gpio_potra_bit_t POTRA_b; + uint32_t RESERVED1[16]; + stc_gpio_pidrb_bit_t PIDRB_b; + uint32_t RESERVED2[16]; + stc_gpio_podrb_bit_t PODRB_b; + stc_gpio_poerb_bit_t POERB_b; + stc_gpio_posrb_bit_t POSRB_b; + stc_gpio_porrb_bit_t PORRB_b; + stc_gpio_potrb_bit_t POTRB_b; + uint32_t RESERVED3[16]; + stc_gpio_pidrc_bit_t PIDRC_b; + uint32_t RESERVED4[16]; + stc_gpio_podrc_bit_t PODRC_b; + stc_gpio_poerc_bit_t POERC_b; + stc_gpio_posrc_bit_t POSRC_b; + stc_gpio_porrc_bit_t PORRC_b; + stc_gpio_potrc_bit_t POTRC_b; + uint32_t RESERVED5[16]; + stc_gpio_pidrd_bit_t PIDRD_b; + uint32_t RESERVED6[16]; + stc_gpio_podrd_bit_t PODRD_b; + stc_gpio_poerd_bit_t POERD_b; + stc_gpio_posrd_bit_t POSRD_b; + stc_gpio_porrd_bit_t PORRD_b; + stc_gpio_potrd_bit_t POTRD_b; + uint32_t RESERVED7[16]; + stc_gpio_pidre_bit_t PIDRE_b; + uint32_t RESERVED8[16]; + stc_gpio_podre_bit_t PODRE_b; + stc_gpio_poere_bit_t POERE_b; + stc_gpio_posre_bit_t POSRE_b; + stc_gpio_porre_bit_t PORRE_b; + stc_gpio_potre_bit_t POTRE_b; + uint32_t RESERVED9[16]; + stc_gpio_pidrf_bit_t PIDRF_b; + uint32_t RESERVED10[16]; + stc_gpio_podrf_bit_t PODRF_b; + stc_gpio_poerf_bit_t POERF_b; + stc_gpio_posrf_bit_t POSRF_b; + stc_gpio_porrf_bit_t PORRF_b; + stc_gpio_potrf_bit_t POTRF_b; + uint32_t RESERVED11[16]; + stc_gpio_pidrg_bit_t PIDRG_b; + uint32_t RESERVED12[16]; + stc_gpio_podrg_bit_t PODRG_b; + stc_gpio_poerg_bit_t POERG_b; + stc_gpio_posrg_bit_t POSRG_b; + stc_gpio_porrg_bit_t PORRG_b; + stc_gpio_potrg_bit_t POTRG_b; + uint32_t RESERVED13[16]; + stc_gpio_pidrh_bit_t PIDRH_b; + uint32_t RESERVED14[16]; + stc_gpio_podrh_bit_t PODRH_b; + stc_gpio_poerh_bit_t POERH_b; + stc_gpio_posrh_bit_t POSRH_b; + stc_gpio_porrh_bit_t PORRH_b; + stc_gpio_potrh_bit_t POTRH_b; + uint32_t RESERVED15[16]; + stc_gpio_pidri_bit_t PIDRI_b; + uint32_t RESERVED16[16]; + stc_gpio_podri_bit_t PODRI_b; + stc_gpio_poeri_bit_t POERI_b; + stc_gpio_posri_bit_t POSRI_b; + stc_gpio_porri_bit_t PORRI_b; + stc_gpio_potri_bit_t POTRI_b; + uint32_t RESERVED17[6960]; + stc_gpio_pspcr_bit_t PSPCR_b; + uint32_t RESERVED18[32]; + stc_gpio_pinaer_bit_t PINAER_b; + stc_gpio_pwpr_bit_t PWPR_b; + uint32_t RESERVED19[16]; + stc_gpio_pcr_bit_t PCRA0_b; + stc_gpio_pfsr_bit_t PFSRA0_b; + stc_gpio_pcr_bit_t PCRA1_b; + stc_gpio_pfsr_bit_t PFSRA1_b; + stc_gpio_pcr_bit_t PCRA2_b; + stc_gpio_pfsr_bit_t PFSRA2_b; + stc_gpio_pcr_bit_t PCRA3_b; + stc_gpio_pfsr_bit_t PFSRA3_b; + stc_gpio_pcr_bit_t PCRA4_b; + stc_gpio_pfsr_bit_t PFSRA4_b; + stc_gpio_pcr_bit_t PCRA5_b; + stc_gpio_pfsr_bit_t PFSRA5_b; + stc_gpio_pcr_bit_t PCRA6_b; + stc_gpio_pfsr_bit_t PFSRA6_b; + stc_gpio_pcr_bit_t PCRA7_b; + stc_gpio_pfsr_bit_t PFSRA7_b; + stc_gpio_pcr_bit_t PCRA8_b; + stc_gpio_pfsr_bit_t PFSRA8_b; + stc_gpio_pcr_bit_t PCRA9_b; + stc_gpio_pfsr_bit_t PFSRA9_b; + stc_gpio_pcr_bit_t PCRA10_b; + stc_gpio_pfsr_bit_t PFSRA10_b; + stc_gpio_pcr_bit_t PCRA11_b; + stc_gpio_pfsr_bit_t PFSRA11_b; + stc_gpio_pcr_bit_t PCRA12_b; + stc_gpio_pfsr_bit_t PFSRA12_b; + stc_gpio_pcr_bit_t PCRA13_b; + stc_gpio_pfsr_bit_t PFSRA13_b; + stc_gpio_pcr_bit_t PCRA14_b; + stc_gpio_pfsr_bit_t PFSRA14_b; + stc_gpio_pcr_bit_t PCRA15_b; + stc_gpio_pfsr_bit_t PFSRA15_b; + stc_gpio_pcr_bit_t PCRB0_b; + stc_gpio_pfsr_bit_t PFSRB0_b; + stc_gpio_pcr_bit_t PCRB1_b; + stc_gpio_pfsr_bit_t PFSRB1_b; + stc_gpio_pcr_bit_t PCRB2_b; + stc_gpio_pfsr_bit_t PFSRB2_b; + stc_gpio_pcr_bit_t PCRB3_b; + stc_gpio_pfsr_bit_t PFSRB3_b; + stc_gpio_pcr_bit_t PCRB4_b; + stc_gpio_pfsr_bit_t PFSRB4_b; + stc_gpio_pcr_bit_t PCRB5_b; + stc_gpio_pfsr_bit_t PFSRB5_b; + stc_gpio_pcr_bit_t PCRB6_b; + stc_gpio_pfsr_bit_t PFSRB6_b; + stc_gpio_pcr_bit_t PCRB7_b; + stc_gpio_pfsr_bit_t PFSRB7_b; + stc_gpio_pcr_bit_t PCRB8_b; + stc_gpio_pfsr_bit_t PFSRB8_b; + stc_gpio_pcr_bit_t PCRB9_b; + stc_gpio_pfsr_bit_t PFSRB9_b; + stc_gpio_pcr_bit_t PCRB10_b; + stc_gpio_pfsr_bit_t PFSRB10_b; + stc_gpio_pcr_bit_t PCRB11_b; + stc_gpio_pfsr_bit_t PFSRB11_b; + stc_gpio_pcr_bit_t PCRB12_b; + stc_gpio_pfsr_bit_t PFSRB12_b; + stc_gpio_pcr_bit_t PCRB13_b; + stc_gpio_pfsr_bit_t PFSRB13_b; + stc_gpio_pcr_bit_t PCRB14_b; + stc_gpio_pfsr_bit_t PFSRB14_b; + stc_gpio_pcr_bit_t PCRB15_b; + stc_gpio_pfsr_bit_t PFSRB15_b; + stc_gpio_pcr_bit_t PCRC0_b; + stc_gpio_pfsr_bit_t PFSRC0_b; + stc_gpio_pcr_bit_t PCRC1_b; + stc_gpio_pfsr_bit_t PFSRC1_b; + stc_gpio_pcr_bit_t PCRC2_b; + stc_gpio_pfsr_bit_t PFSRC2_b; + stc_gpio_pcr_bit_t PCRC3_b; + stc_gpio_pfsr_bit_t PFSRC3_b; + stc_gpio_pcr_bit_t PCRC4_b; + stc_gpio_pfsr_bit_t PFSRC4_b; + stc_gpio_pcr_bit_t PCRC5_b; + stc_gpio_pfsr_bit_t PFSRC5_b; + stc_gpio_pcr_bit_t PCRC6_b; + stc_gpio_pfsr_bit_t PFSRC6_b; + stc_gpio_pcr_bit_t PCRC7_b; + stc_gpio_pfsr_bit_t PFSRC7_b; + stc_gpio_pcr_bit_t PCRC8_b; + stc_gpio_pfsr_bit_t PFSRC8_b; + stc_gpio_pcr_bit_t PCRC9_b; + stc_gpio_pfsr_bit_t PFSRC9_b; + stc_gpio_pcr_bit_t PCRC10_b; + stc_gpio_pfsr_bit_t PFSRC10_b; + stc_gpio_pcr_bit_t PCRC11_b; + stc_gpio_pfsr_bit_t PFSRC11_b; + stc_gpio_pcr_bit_t PCRC12_b; + stc_gpio_pfsr_bit_t PFSRC12_b; + stc_gpio_pcr_bit_t PCRC13_b; + stc_gpio_pfsr_bit_t PFSRC13_b; + stc_gpio_pcr_bit_t PCRC14_b; + stc_gpio_pfsr_bit_t PFSRC14_b; + stc_gpio_pcr_bit_t PCRC15_b; + stc_gpio_pfsr_bit_t PFSRC15_b; + stc_gpio_pcr_bit_t PCRD0_b; + stc_gpio_pfsr_bit_t PFSRD0_b; + stc_gpio_pcr_bit_t PCRD1_b; + stc_gpio_pfsr_bit_t PFSRD1_b; + stc_gpio_pcr_bit_t PCRD2_b; + stc_gpio_pfsr_bit_t PFSRD2_b; + stc_gpio_pcr_bit_t PCRD3_b; + stc_gpio_pfsr_bit_t PFSRD3_b; + stc_gpio_pcr_bit_t PCRD4_b; + stc_gpio_pfsr_bit_t PFSRD4_b; + stc_gpio_pcr_bit_t PCRD5_b; + stc_gpio_pfsr_bit_t PFSRD5_b; + stc_gpio_pcr_bit_t PCRD6_b; + stc_gpio_pfsr_bit_t PFSRD6_b; + stc_gpio_pcr_bit_t PCRD7_b; + stc_gpio_pfsr_bit_t PFSRD7_b; + stc_gpio_pcr_bit_t PCRD8_b; + stc_gpio_pfsr_bit_t PFSRD8_b; + stc_gpio_pcr_bit_t PCRD9_b; + stc_gpio_pfsr_bit_t PFSRD9_b; + stc_gpio_pcr_bit_t PCRD10_b; + stc_gpio_pfsr_bit_t PFSRD10_b; + stc_gpio_pcr_bit_t PCRD11_b; + stc_gpio_pfsr_bit_t PFSRD11_b; + stc_gpio_pcr_bit_t PCRD12_b; + stc_gpio_pfsr_bit_t PFSRD12_b; + stc_gpio_pcr_bit_t PCRD13_b; + stc_gpio_pfsr_bit_t PFSRD13_b; + stc_gpio_pcr_bit_t PCRD14_b; + stc_gpio_pfsr_bit_t PFSRD14_b; + stc_gpio_pcr_bit_t PCRD15_b; + stc_gpio_pfsr_bit_t PFSRD15_b; + stc_gpio_pcr_bit_t PCRE0_b; + stc_gpio_pfsr_bit_t PFSRE0_b; + stc_gpio_pcr_bit_t PCRE1_b; + stc_gpio_pfsr_bit_t PFSRE1_b; + stc_gpio_pcr_bit_t PCRE2_b; + stc_gpio_pfsr_bit_t PFSRE2_b; + stc_gpio_pcr_bit_t PCRE3_b; + stc_gpio_pfsr_bit_t PFSRE3_b; + stc_gpio_pcr_bit_t PCRE4_b; + stc_gpio_pfsr_bit_t PFSRE4_b; + stc_gpio_pcr_bit_t PCRE5_b; + stc_gpio_pfsr_bit_t PFSRE5_b; + stc_gpio_pcr_bit_t PCRE6_b; + stc_gpio_pfsr_bit_t PFSRE6_b; + stc_gpio_pcr_bit_t PCRE7_b; + stc_gpio_pfsr_bit_t PFSRE7_b; + stc_gpio_pcr_bit_t PCRE8_b; + stc_gpio_pfsr_bit_t PFSRE8_b; + stc_gpio_pcr_bit_t PCRE9_b; + stc_gpio_pfsr_bit_t PFSRE9_b; + stc_gpio_pcr_bit_t PCRE10_b; + stc_gpio_pfsr_bit_t PFSRE10_b; + stc_gpio_pcr_bit_t PCRE11_b; + stc_gpio_pfsr_bit_t PFSRE11_b; + stc_gpio_pcr_bit_t PCRE12_b; + stc_gpio_pfsr_bit_t PFSRE12_b; + stc_gpio_pcr_bit_t PCRE13_b; + stc_gpio_pfsr_bit_t PFSRE13_b; + stc_gpio_pcr_bit_t PCRE14_b; + stc_gpio_pfsr_bit_t PFSRE14_b; + stc_gpio_pcr_bit_t PCRE15_b; + stc_gpio_pfsr_bit_t PFSRE15_b; + stc_gpio_pcr_bit_t PCRF0_b; + stc_gpio_pfsr_bit_t PFSRF0_b; + stc_gpio_pcr_bit_t PCRF1_b; + stc_gpio_pfsr_bit_t PFSRF1_b; + stc_gpio_pcr_bit_t PCRF2_b; + stc_gpio_pfsr_bit_t PFSRF2_b; + stc_gpio_pcr_bit_t PCRF3_b; + stc_gpio_pfsr_bit_t PFSRF3_b; + stc_gpio_pcr_bit_t PCRF4_b; + stc_gpio_pfsr_bit_t PFSRF4_b; + stc_gpio_pcr_bit_t PCRF5_b; + stc_gpio_pfsr_bit_t PFSRF5_b; + stc_gpio_pcr_bit_t PCRF6_b; + stc_gpio_pfsr_bit_t PFSRF6_b; + stc_gpio_pcr_bit_t PCRF7_b; + stc_gpio_pfsr_bit_t PFSRF7_b; + stc_gpio_pcr_bit_t PCRF8_b; + stc_gpio_pfsr_bit_t PFSRF8_b; + stc_gpio_pcr_bit_t PCRF9_b; + stc_gpio_pfsr_bit_t PFSRF9_b; + stc_gpio_pcr_bit_t PCRF10_b; + stc_gpio_pfsr_bit_t PFSRF10_b; + stc_gpio_pcr_bit_t PCRF11_b; + stc_gpio_pfsr_bit_t PFSRF11_b; + stc_gpio_pcr_bit_t PCRF12_b; + stc_gpio_pfsr_bit_t PFSRF12_b; + stc_gpio_pcr_bit_t PCRF13_b; + stc_gpio_pfsr_bit_t PFSRF13_b; + stc_gpio_pcr_bit_t PCRF14_b; + stc_gpio_pfsr_bit_t PFSRF14_b; + stc_gpio_pcr_bit_t PCRF15_b; + stc_gpio_pfsr_bit_t PFSRF15_b; + stc_gpio_pcr_bit_t PCRG0_b; + stc_gpio_pfsr_bit_t PFSRG0_b; + stc_gpio_pcr_bit_t PCRG1_b; + stc_gpio_pfsr_bit_t PFSRG1_b; + stc_gpio_pcr_bit_t PCRG2_b; + stc_gpio_pfsr_bit_t PFSRG2_b; + stc_gpio_pcr_bit_t PCRG3_b; + stc_gpio_pfsr_bit_t PFSRG3_b; + stc_gpio_pcr_bit_t PCRG4_b; + stc_gpio_pfsr_bit_t PFSRG4_b; + stc_gpio_pcr_bit_t PCRG5_b; + stc_gpio_pfsr_bit_t PFSRG5_b; + stc_gpio_pcr_bit_t PCRG6_b; + stc_gpio_pfsr_bit_t PFSRG6_b; + stc_gpio_pcr_bit_t PCRG7_b; + stc_gpio_pfsr_bit_t PFSRG7_b; + stc_gpio_pcr_bit_t PCRG8_b; + stc_gpio_pfsr_bit_t PFSRG8_b; + stc_gpio_pcr_bit_t PCRG9_b; + stc_gpio_pfsr_bit_t PFSRG9_b; + stc_gpio_pcr_bit_t PCRG10_b; + stc_gpio_pfsr_bit_t PFSRG10_b; + stc_gpio_pcr_bit_t PCRG11_b; + stc_gpio_pfsr_bit_t PFSRG11_b; + stc_gpio_pcr_bit_t PCRG12_b; + stc_gpio_pfsr_bit_t PFSRG12_b; + stc_gpio_pcr_bit_t PCRG13_b; + stc_gpio_pfsr_bit_t PFSRG13_b; + stc_gpio_pcr_bit_t PCRG14_b; + stc_gpio_pfsr_bit_t PFSRG14_b; + stc_gpio_pcr_bit_t PCRG15_b; + stc_gpio_pfsr_bit_t PFSRG15_b; + stc_gpio_pcr_bit_t PCRH0_b; + stc_gpio_pfsr_bit_t PFSRH0_b; + stc_gpio_pcr_bit_t PCRH1_b; + stc_gpio_pfsr_bit_t PFSRH1_b; + stc_gpio_pcr_bit_t PCRH2_b; + stc_gpio_pfsr_bit_t PFSRH2_b; + stc_gpio_pcr_bit_t PCRH3_b; + stc_gpio_pfsr_bit_t PFSRH3_b; + stc_gpio_pcr_bit_t PCRH4_b; + stc_gpio_pfsr_bit_t PFSRH4_b; + stc_gpio_pcr_bit_t PCRH5_b; + stc_gpio_pfsr_bit_t PFSRH5_b; + stc_gpio_pcr_bit_t PCRH6_b; + stc_gpio_pfsr_bit_t PFSRH6_b; + stc_gpio_pcr_bit_t PCRH7_b; + stc_gpio_pfsr_bit_t PFSRH7_b; + stc_gpio_pcr_bit_t PCRH8_b; + stc_gpio_pfsr_bit_t PFSRH8_b; + stc_gpio_pcr_bit_t PCRH9_b; + stc_gpio_pfsr_bit_t PFSRH9_b; + stc_gpio_pcr_bit_t PCRH10_b; + stc_gpio_pfsr_bit_t PFSRH10_b; + stc_gpio_pcr_bit_t PCRH11_b; + stc_gpio_pfsr_bit_t PFSRH11_b; + stc_gpio_pcr_bit_t PCRH12_b; + stc_gpio_pfsr_bit_t PFSRH12_b; + stc_gpio_pcr_bit_t PCRH13_b; + stc_gpio_pfsr_bit_t PFSRH13_b; + stc_gpio_pcr_bit_t PCRH14_b; + stc_gpio_pfsr_bit_t PFSRH14_b; + stc_gpio_pcr_bit_t PCRH15_b; + stc_gpio_pfsr_bit_t PFSRH15_b; + stc_gpio_pcr_bit_t PCRI0_b; + stc_gpio_pfsr_bit_t PFSRI0_b; + stc_gpio_pcr_bit_t PCRI1_b; + stc_gpio_pfsr_bit_t PFSRI1_b; + stc_gpio_pcr_bit_t PCRI2_b; + stc_gpio_pfsr_bit_t PFSRI2_b; + stc_gpio_pcr_bit_t PCRI3_b; + stc_gpio_pfsr_bit_t PFSRI3_b; + stc_gpio_pcr_bit_t PCRI4_b; + stc_gpio_pfsr_bit_t PFSRI4_b; + stc_gpio_pcr_bit_t PCRI5_b; + stc_gpio_pfsr_bit_t PFSRI5_b; + stc_gpio_pcr_bit_t PCRI6_b; + stc_gpio_pfsr_bit_t PFSRI6_b; + stc_gpio_pcr_bit_t PCRI7_b; + stc_gpio_pfsr_bit_t PFSRI7_b; + stc_gpio_pcr_bit_t PCRI8_b; + stc_gpio_pfsr_bit_t PFSRI8_b; + stc_gpio_pcr_bit_t PCRI9_b; + stc_gpio_pfsr_bit_t PFSRI9_b; + stc_gpio_pcr_bit_t PCRI10_b; + stc_gpio_pfsr_bit_t PFSRI10_b; + stc_gpio_pcr_bit_t PCRI11_b; + stc_gpio_pfsr_bit_t PFSRI11_b; + stc_gpio_pcr_bit_t PCRI12_b; + stc_gpio_pfsr_bit_t PFSRI12_b; + stc_gpio_pcr_bit_t PCRI13_b; + stc_gpio_pfsr_bit_t PFSRI13_b; +} bM4_GPIO_TypeDef; + +typedef struct +{ + stc_hash_cr_bit_t CR_b; +} bM4_HASH_TypeDef; + +typedef struct +{ + stc_hrpwm_cr_bit_t CR1_b; + stc_hrpwm_cr_bit_t CR2_b; + stc_hrpwm_cr_bit_t CR3_b; + stc_hrpwm_cr_bit_t CR4_b; + stc_hrpwm_cr_bit_t CR5_b; + stc_hrpwm_cr_bit_t CR6_b; + stc_hrpwm_cr_bit_t CR7_b; + stc_hrpwm_cr_bit_t CR8_b; + stc_hrpwm_cr_bit_t CR9_b; + stc_hrpwm_cr_bit_t CR10_b; + stc_hrpwm_cr_bit_t CR11_b; + stc_hrpwm_cr_bit_t CR12_b; + stc_hrpwm_cr_bit_t CR13_b; + stc_hrpwm_cr_bit_t CR14_b; + stc_hrpwm_cr_bit_t CR15_b; + stc_hrpwm_cr_bit_t CR16_b; + uint32_t RESERVED0[128]; + stc_hrpwm_calcr_bit_t CALCR0_b; + stc_hrpwm_calcr_bit_t CALCR1_b; +} bM4_HRPWM_TypeDef; + +typedef struct +{ + stc_i2c_cr1_bit_t CR1_b; + stc_i2c_cr2_bit_t CR2_b; + stc_i2c_cr3_bit_t CR3_b; + uint32_t RESERVED0[32]; + stc_i2c_slr0_bit_t SLR0_b; + stc_i2c_slr1_bit_t SLR1_b; + uint32_t RESERVED1[32]; + stc_i2c_sr_bit_t SR_b; + stc_i2c_clr_bit_t CLR_b; + stc_i2c_dtr_bit_t DTR_b; + uint32_t RESERVED2[24]; + stc_i2c_drr_bit_t DRR_b; + uint32_t RESERVED3[56]; + stc_i2c_fltr_bit_t FLTR_b; +} bM4_I2C_TypeDef; + +typedef struct +{ + stc_i2s_ctrl_bit_t CTRL_b; + stc_i2s_sr_bit_t SR_b; + stc_i2s_er_bit_t ER_b; + stc_i2s_cfgr_bit_t CFGR_b; + uint32_t RESERVED0[64]; + stc_i2s_pr_bit_t PR_b; +} bM4_I2S_TypeDef; + +typedef struct +{ + stc_icg_icg0_bit_t ICG0_b; + stc_icg_icg1_bit_t ICG1_b; +} bM4_ICG_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[32]; + stc_intc_nmienr_bit_t NMIENR_b; + stc_intc_nmifr_bit_t NMIFR_b; + stc_intc_nmicfr_bit_t NMICFR_b; + stc_intc_eirqcr_bit_t EIRQCR0_b; + stc_intc_eirqcr_bit_t EIRQCR1_b; + stc_intc_eirqcr_bit_t EIRQCR2_b; + stc_intc_eirqcr_bit_t EIRQCR3_b; + stc_intc_eirqcr_bit_t EIRQCR4_b; + stc_intc_eirqcr_bit_t EIRQCR5_b; + stc_intc_eirqcr_bit_t EIRQCR6_b; + stc_intc_eirqcr_bit_t EIRQCR7_b; + stc_intc_eirqcr_bit_t EIRQCR8_b; + stc_intc_eirqcr_bit_t EIRQCR9_b; + stc_intc_eirqcr_bit_t EIRQCR10_b; + stc_intc_eirqcr_bit_t EIRQCR11_b; + stc_intc_eirqcr_bit_t EIRQCR12_b; + stc_intc_eirqcr_bit_t EIRQCR13_b; + stc_intc_eirqcr_bit_t EIRQCR14_b; + stc_intc_eirqcr_bit_t EIRQCR15_b; + stc_intc_wupen_bit_t WUPEN_b; + stc_intc_eifr_bit_t EIFR_b; + stc_intc_eicfr_bit_t EICFR_b; + uint32_t RESERVED1[4096]; + stc_intc_vssel_bit_t VSSEL128_b; + stc_intc_vssel_bit_t VSSEL129_b; + stc_intc_vssel_bit_t VSSEL130_b; + stc_intc_vssel_bit_t VSSEL131_b; + stc_intc_vssel_bit_t VSSEL132_b; + stc_intc_vssel_bit_t VSSEL133_b; + stc_intc_vssel_bit_t VSSEL134_b; + stc_intc_vssel_bit_t VSSEL135_b; + stc_intc_vssel_bit_t VSSEL136_b; + stc_intc_vssel_bit_t VSSEL137_b; + stc_intc_vssel_bit_t VSSEL138_b; + stc_intc_vssel_bit_t VSSEL139_b; + stc_intc_vssel_bit_t VSSEL140_b; + stc_intc_vssel_bit_t VSSEL141_b; + stc_intc_vssel_bit_t VSSEL142_b; + stc_intc_vssel_bit_t VSSEL143_b; + stc_intc_swier_bit_t SWIER_b; + stc_intc_evter_bit_t EVTER_b; + stc_intc_ier_bit_t IER_b; +} bM4_INTC_TypeDef; + +typedef struct +{ + stc_keyscan_scr_bit_t SCR_b; + stc_keyscan_ser_bit_t SER_b; +} bM4_KEYSCAN_TypeDef; + +typedef struct +{ + stc_mau_csr_bit_t CSR_b; + uint32_t RESERVED0[64]; + stc_mau_rtr0_bit_t RTR0_b; + stc_mau_dtr1_bit_t DTR1_b; + stc_mau_rtr1_bit_t RTR1_b; +} bM4_MAU_TypeDef; + +typedef struct +{ + stc_mpu_rgd_bit_t RGD0_b; + stc_mpu_rgd_bit_t RGD1_b; + stc_mpu_rgd_bit_t RGD2_b; + stc_mpu_rgd_bit_t RGD3_b; + stc_mpu_rgd_bit_t RGD4_b; + stc_mpu_rgd_bit_t RGD5_b; + stc_mpu_rgd_bit_t RGD6_b; + stc_mpu_rgd_bit_t RGD7_b; + stc_mpu_rgd_bit_t RGD8_b; + stc_mpu_rgd_bit_t RGD9_b; + stc_mpu_rgd_bit_t RGD10_b; + stc_mpu_rgd_bit_t RGD11_b; + stc_mpu_rgd_bit_t RGD12_b; + stc_mpu_rgd_bit_t RGD13_b; + stc_mpu_rgd_bit_t RGD14_b; + stc_mpu_rgd_bit_t RGD15_b; + stc_mpu_sr_bit_t SR_b; + stc_mpu_eclr_bit_t ECLR_b; + stc_mpu_wp_bit_t WP_b; + stc_mpu_ippr_bit_t IPPR_b; + stc_mpu_s1rge_bit_t S1RGE_b; + stc_mpu_s1rgwp_bit_t S1RGWP_b; + stc_mpu_s1rgrp_bit_t S1RGRP_b; + stc_mpu_s1cr_bit_t S1CR_b; + stc_mpu_s2rge_bit_t S2RGE_b; + stc_mpu_s2rgwp_bit_t S2RGWP_b; + stc_mpu_s2rgrp_bit_t S2RGRP_b; + stc_mpu_s2cr_bit_t S2CR_b; + stc_mpu_frge_bit_t FRGE_b; + stc_mpu_frgwp_bit_t FRGWP_b; + stc_mpu_frgrp_bit_t FRGRP_b; + stc_mpu_fcr_bit_t FCR_b; + stc_mpu_hrge_bit_t HRGE_b; + stc_mpu_hrgwp_bit_t HRGWP_b; + stc_mpu_hrgrp_bit_t HRGRP_b; + stc_mpu_hcr_bit_t HCR_b; + stc_mpu_erge_bit_t ERGE_b; + stc_mpu_ergwp_bit_t ERGWP_b; + stc_mpu_ergrp_bit_t ERGRP_b; + stc_mpu_ecr_bit_t ECR_b; +} bM4_MPU_TypeDef; + +typedef struct +{ + stc_ots_ctl_bit_t CTL_b; + uint32_t RESERVED0[48]; + stc_ots_lpr_bit_t LPR_b; +} bM4_OTS_TypeDef; + +typedef struct +{ + stc_peric_usb_syctlreg_bit_t USB_SYCTLREG_b; + stc_peric_sdioc_syctlreg_bit_t SDIOC_SYCTLREG_b; + stc_peric_nfc_syctlreg_bit_t NFC_SYCTLREG_b; + stc_peric_exmc_enar_bit_t EXMC_ENAR_b; + uint32_t RESERVED0[64]; + stc_peric_can_syctlreg_bit_t CAN_SYCTLREG_b; + stc_peric_usart1_nfc_bit_t USART1_NFC_b; + uint32_t RESERVED1[64]; + stc_peric_nfc_systatreg_bit_t NFC_SYSTATREG_b; +} bM4_PERIC_TypeDef; + +typedef struct +{ + stc_pwc_fcg0_bit_t FCG0_b; + stc_pwc_fcg1_bit_t FCG1_b; + stc_pwc_fcg2_bit_t FCG2_b; + stc_pwc_fcg3_bit_t FCG3_b; + stc_pwc_fcg0pc_bit_t FCG0PC_b; + uint32_t RESERVED0[139616]; + stc_pwc_vbatcr_bit_t VBATCR_b; + uint32_t RESERVED1[184]; + stc_pwc_wktc2_bit_t WKTC2_b; + uint32_t RESERVED2[15672]; + stc_pwc_pwrc0_bit_t PWRC0_b; + uint32_t RESERVED3[24]; + stc_pwc_pwrc1_bit_t PWRC1_b; + uint32_t RESERVED4[24]; + stc_pwc_pwrc2_bit_t PWRC2_b; + uint32_t RESERVED5[56]; + stc_pwc_pwrc4_bit_t PWRC4_b; + uint32_t RESERVED6[24]; + stc_pwc_pvdcr0_bit_t PVDCR0_b; + uint32_t RESERVED7[24]; + stc_pwc_pvdcr1_bit_t PVDCR1_b; + uint32_t RESERVED8[24]; + stc_pwc_pvdfcr_bit_t PVDFCR_b; + uint32_t RESERVED9[24]; + stc_pwc_pvdlcr_bit_t PVDLCR_b; + uint32_t RESERVED10[56]; + stc_pwc_pdwke0_bit_t PDWKE0_b; + uint32_t RESERVED11[24]; + stc_pwc_pdwke1_bit_t PDWKE1_b; + uint32_t RESERVED12[24]; + stc_pwc_pdwke2_bit_t PDWKE2_b; + uint32_t RESERVED13[24]; + stc_pwc_pdwkes_bit_t PDWKES_b; + uint32_t RESERVED14[24]; + stc_pwc_pdwkf0_bit_t PDWKF0_b; + uint32_t RESERVED15[24]; + stc_pwc_pdwkf1_bit_t PDWKF1_b; + uint32_t RESERVED16[1304]; + stc_pwc_rampc0_bit_t RAMPC0_b; + stc_pwc_ramopm_bit_t RAMOPM_b; + stc_pwc_pramlpc_bit_t PRAMLPC_b; + uint32_t RESERVED17[32]; + stc_pwc_pvdicr_bit_t PVDICR_b; + uint32_t RESERVED18[24]; + stc_pwc_pvddsr_bit_t PVDDSR_b; + uint32_t RESERVED19[235704]; + stc_pwc_stpmcr_bit_t STPMCR_b; + uint32_t RESERVED20[8064]; + stc_pwc_fprc_bit_t FPRC_b; +} bM4_PWC_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[1984]; + stc_rmu_prstcr0_bit_t PRSTCR0_b; + uint32_t RESERVED1[24]; + stc_rmu_rstf0_bit_t RSTF0_b; +} bM4_RMU_TypeDef; + +typedef struct +{ + stc_rtc_cr0_bit_t CR0_b; + uint32_t RESERVED0[24]; + stc_rtc_cr1_bit_t CR1_b; + uint32_t RESERVED1[24]; + stc_rtc_cr2_bit_t CR2_b; + uint32_t RESERVED2[24]; + stc_rtc_cr3_bit_t CR3_b; + uint32_t RESERVED3[88]; + stc_rtc_hour_bit_t HOUR_b; + uint32_t RESERVED4[24]; + stc_rtc_week_bit_t WEEK_b; + uint32_t RESERVED5[152]; + stc_rtc_almhour_bit_t ALMHOUR_b; + uint32_t RESERVED6[24]; + stc_rtc_almweek_bit_t ALMWEEK_b; + uint32_t RESERVED7[24]; + stc_rtc_errcrh_bit_t ERRCRH_b; + uint32_t RESERVED8[56]; + stc_rtc_tpcr0_bit_t TPCR0_b; + uint32_t RESERVED9[24]; + stc_rtc_tpcr1_bit_t TPCR1_b; + uint32_t RESERVED10[24]; + stc_rtc_tpsr_bit_t TPSR_b; + uint32_t RESERVED11[88]; + stc_rtc_hourtp_bit_t HOURTP_b; +} bM4_RTC_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[96]; + stc_sdioc_transmode_bit_t TRANSMODE_b; + stc_sdioc_cmd_bit_t CMD_b; + uint32_t RESERVED1[160]; + stc_sdioc_pstat_bit_t PSTAT_b; + stc_sdioc_hostcon_bit_t HOSTCON_b; + stc_sdioc_pwrcon_bit_t PWRCON_b; + stc_sdioc_blkgpcon_bit_t BLKGPCON_b; + uint32_t RESERVED2[8]; + stc_sdioc_clkcon_bit_t CLKCON_b; + stc_sdioc_toutcon_bit_t TOUTCON_b; + stc_sdioc_sftrst_bit_t SFTRST_b; + stc_sdioc_norintst_bit_t NORINTST_b; + stc_sdioc_errintst_bit_t ERRINTST_b; + stc_sdioc_norintsten_bit_t NORINTSTEN_b; + stc_sdioc_errintsten_bit_t ERRINTSTEN_b; + stc_sdioc_norintsgen_bit_t NORINTSGEN_b; + stc_sdioc_errintsgen_bit_t ERRINTSGEN_b; + stc_sdioc_atcerrst_bit_t ATCERRST_b; + uint32_t RESERVED3[144]; + stc_sdioc_fea_bit_t FEA_b; + stc_sdioc_fee_bit_t FEE_b; +} bM4_SDIOC_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[32]; + stc_spi_cr1_bit_t CR1_b; + uint32_t RESERVED1[32]; + stc_spi_cfg1_bit_t CFG1_b; + uint32_t RESERVED2[32]; + stc_spi_sr_bit_t SR_b; + stc_spi_cfg2_bit_t CFG2_b; +} bM4_SPI_TypeDef; + +typedef struct +{ + stc_sramc_wtcr_bit_t WTCR_b; + stc_sramc_wtpr_bit_t WTPR_b; + stc_sramc_ckcr_bit_t CKCR_b; + stc_sramc_ckpr_bit_t CKPR_b; + stc_sramc_cksr_bit_t CKSR_b; +} bM4_SRAMC_TypeDef; + +typedef struct +{ + stc_swdt_cr_bit_t CR_b; + stc_swdt_sr_bit_t SR_b; +} bM4_SWDT_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[128]; + stc_tmr0_bconr_bit_t BCONR_b; + stc_tmr0_stflr_bit_t STFLR_b; +} bM4_TMR0_TypeDef; + +typedef struct +{ + stc_tmr2_cntar_bit_t CNTAR_b; + stc_tmr2_cntbr_bit_t CNTBR_b; + stc_tmr2_cmpar_bit_t CMPAR_b; + stc_tmr2_cmpbr_bit_t CMPBR_b; + stc_tmr2_bconr_bit_t BCONR_b; + stc_tmr2_iconr_bit_t ICONR_b; + stc_tmr2_pconr_bit_t PCONR_b; + stc_tmr2_hconr_bit_t HCONR_b; + stc_tmr2_stflr_bit_t STFLR_b; +} bM4_TMR2_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[192]; + stc_tmr4_ocsr_bit_t OCSRU_b; + stc_tmr4_ocer_bit_t OCERU_b; + stc_tmr4_ocsr_bit_t OCSRV_b; + stc_tmr4_ocer_bit_t OCERV_b; + stc_tmr4_ocsr_bit_t OCSRW_b; + stc_tmr4_ocer_bit_t OCERW_b; + stc_tmr4_ocmrh_bit_t OCMRHUH_b; + uint32_t RESERVED1[16]; + stc_tmr4_ocmrl_bit_t OCMRLUL_b; + stc_tmr4_ocmrh_bit_t OCMRHVH_b; + uint32_t RESERVED2[16]; + stc_tmr4_ocmrl_bit_t OCMRLVL_b; + stc_tmr4_ocmrh_bit_t OCMRHWH_b; + uint32_t RESERVED3[16]; + stc_tmr4_ocmrl_bit_t OCMRLWL_b; + uint32_t RESERVED4[96]; + stc_tmr4_ccsr_bit_t CCSR_b; + uint32_t RESERVED5[624]; + stc_tmr4_pocr_bit_t POCRU_b; + uint32_t RESERVED6[16]; + stc_tmr4_pocr_bit_t POCRV_b; + uint32_t RESERVED7[16]; + stc_tmr4_pocr_bit_t POCRW_b; + uint32_t RESERVED8[16]; + stc_tmr4_rcsr_bit_t RCSR_b; + uint32_t RESERVED9[272]; + stc_tmr4_scsr_bit_t SCSRUH_b; + stc_tmr4_scmr_bit_t SCMRUH_b; + stc_tmr4_scsr_bit_t SCSRUL_b; + stc_tmr4_scmr_bit_t SCMRUL_b; + stc_tmr4_scsr_bit_t SCSRVH_b; + stc_tmr4_scmr_bit_t SCMRVH_b; + stc_tmr4_scsr_bit_t SCSRVL_b; + stc_tmr4_scmr_bit_t SCMRVL_b; + stc_tmr4_scsr_bit_t SCSRWH_b; + stc_tmr4_scmr_bit_t SCMRWH_b; + stc_tmr4_scsr_bit_t SCSRWL_b; + stc_tmr4_scmr_bit_t SCMRWL_b; + stc_tmr4_pscr_bit_t PSCR_b; + stc_tmr4_scer_bit_t SCER_b; +} bM4_TMR4_TypeDef; + +typedef struct +{ + uint32_t RESERVED0[2560]; + stc_tmr6_gconr_bit_t GCONR_b; + stc_tmr6_iconr_bit_t ICONR_b; + stc_tmr6_bconr_bit_t BCONR_b; + stc_tmr6_dconr_bit_t DCONR_b; + uint32_t RESERVED1[32]; + stc_tmr6_pcnar_bit_t PCNAR_b; + stc_tmr6_pcnbr_bit_t PCNBR_b; + stc_tmr6_fcngr_bit_t FCNGR_b; + stc_tmr6_vperr_bit_t VPERR_b; + stc_tmr6_stflr_bit_t STFLR_b; + uint32_t RESERVED2[192]; + stc_tmr6_hstar_bit_t HSTAR_b; + stc_tmr6_hstpr_bit_t HSTPR_b; + stc_tmr6_hclrr_bit_t HCLRR_b; + stc_tmr6_hupdr_bit_t HUPDR_b; + stc_tmr6_hcpar_bit_t HCPAR_b; + stc_tmr6_hcpbr_bit_t HCPBR_b; + stc_tmr6_hcupr_bit_t HCUPR_b; + stc_tmr6_hcdor_bit_t HCDOR_b; + uint32_t RESERVED3[4704]; + stc_tmr6_fcntr_bit_t FCNTR_b; + stc_tmr6_sstar_bit_t SSTAR_b; + stc_tmr6_sstpr_bit_t SSTPR_b; + stc_tmr6_sclrr_bit_t SCLRR_b; + stc_tmr6_supdr_bit_t SUPDR_b; +} bM4_TMR6_TypeDef; + +typedef struct +{ + stc_tmra_cnter_bit_t CNTER_b; + stc_tmra_perar_bit_t PERAR_b; + uint32_t RESERVED0[448]; + stc_tmra_cmpar1_bit_t CMPAR1_b; + stc_tmra_cmpar2_bit_t CMPAR2_b; + stc_tmra_cmpar3_bit_t CMPAR3_b; + stc_tmra_cmpar4_bit_t CMPAR4_b; + uint32_t RESERVED1[384]; + stc_tmra_bcstr_bit_t BCSTR_b; + stc_tmra_hconr_bit_t HCONR_b; + stc_tmra_hcupr_bit_t HCUPR_b; + stc_tmra_hcdor_bit_t HCDOR_b; + stc_tmra_iconr_bit_t ICONR_b; + stc_tmra_econr_bit_t ECONR_b; + stc_tmra_fconr_bit_t FCONR_b; + stc_tmra_stflr_bit_t STFLR_b; + uint32_t RESERVED2[256]; + stc_tmra_bconr_bit_t BCONR1_b; + uint32_t RESERVED3[32]; + stc_tmra_bconr_bit_t BCONR2_b; + uint32_t RESERVED4[416]; + stc_tmra_cconr_bit_t CCONR1_b; + stc_tmra_cconr_bit_t CCONR2_b; + stc_tmra_cconr_bit_t CCONR3_b; + stc_tmra_cconr_bit_t CCONR4_b; + uint32_t RESERVED5[384]; + stc_tmra_pconr_bit_t PCONR1_b; + stc_tmra_pconr_bit_t PCONR2_b; + stc_tmra_pconr_bit_t PCONR3_b; + stc_tmra_pconr_bit_t PCONR4_b; +} bM4_TMRA_TypeDef; + +typedef struct +{ + stc_trng_cr_bit_t CR_b; + stc_trng_mr_bit_t MR_b; +} bM4_TRNG_TypeDef; + +typedef struct +{ + stc_usart_sr_bit_t SR_b; + stc_usart_dr_bit_t DR_b; + uint32_t RESERVED0[32]; + stc_usart_cr1_bit_t CR1_b; + stc_usart_cr2_bit_t CR2_b; + stc_usart_cr3_bit_t CR3_b; + stc_usart_pr_bit_t PR_b; +} bM4_USART_TypeDef; + +typedef struct +{ + stc_usbfs_gotgctl_bit_t GOTGCTL_b; + stc_usbfs_gotgint_bit_t GOTGINT_b; + stc_usbfs_gahbcfg_bit_t GAHBCFG_b; + stc_usbfs_gusbcfg_bit_t GUSBCFG_b; + stc_usbfs_grstctl_bit_t GRSTCTL_b; + stc_usbfs_gintsts_bit_t GINTSTS_b; + stc_usbfs_gintmsk_bit_t GINTMSK_b; + stc_usbfs_grxstsr_bit_t GRXSTSR_b; + stc_usbfs_grxstsp_bit_t GRXSTSP_b; + stc_usbfs_grxfsiz_bit_t GRXFSIZ_b; + uint32_t RESERVED0[32]; + stc_usbfs_gnptxsts_bit_t GNPTXSTS_b; + uint32_t RESERVED1[288]; + stc_usbfs_glpmcfg_bit_t GLPMCFG_b; + uint32_t RESERVED2[7488]; + stc_usbfs_hcfg_bit_t HCFG_b; + stc_usbfs_hfir_bit_t HFIR_b; + uint32_t RESERVED3[64]; + stc_usbfs_hptxsts_bit_t HPTXSTS_b; + stc_usbfs_haint_bit_t HAINT_b; + stc_usbfs_haintmsk_bit_t HAINTMSK_b; + uint32_t RESERVED4[288]; + stc_usbfs_hprt_bit_t HPRT_b; + uint32_t RESERVED5[1504]; + stc_usbfs_hcchar0_bit_t HCCHAR0_b; + stc_usbfs_hcsplt0_bit_t HCSPLT0_b; + stc_usbfs_hcint0_bit_t HCINT0_b; + stc_usbfs_hcintmsk0_bit_t HCINTMSK0_b; + stc_usbfs_hctsiz0_bit_t HCTSIZ0_b; + uint32_t RESERVED6[96]; + stc_usbfs_hcchar1_bit_t HCCHAR1_b; + stc_usbfs_hcsplt1_bit_t HCSPLT1_b; + stc_usbfs_hcint1_bit_t HCINT1_b; + stc_usbfs_hcintmsk1_bit_t HCINTMSK1_b; + stc_usbfs_hctsiz1_bit_t HCTSIZ1_b; + uint32_t RESERVED7[96]; + stc_usbfs_hcchar2_bit_t HCCHAR2_b; + stc_usbfs_hcsplt2_bit_t HCSPLT2_b; + stc_usbfs_hcint2_bit_t HCINT2_b; + stc_usbfs_hcintmsk2_bit_t HCINTMSK2_b; + stc_usbfs_hctsiz2_bit_t HCTSIZ2_b; + uint32_t RESERVED8[96]; + stc_usbfs_hcchar3_bit_t HCCHAR3_b; + stc_usbfs_hcsplt3_bit_t HCSPLT3_b; + stc_usbfs_hcint3_bit_t HCINT3_b; + stc_usbfs_hcintmsk3_bit_t HCINTMSK3_b; + stc_usbfs_hctsiz3_bit_t HCTSIZ3_b; + uint32_t RESERVED9[96]; + stc_usbfs_hcchar4_bit_t HCCHAR4_b; + stc_usbfs_hcsplt4_bit_t HCSPLT4_b; + stc_usbfs_hcint4_bit_t HCINT4_b; + stc_usbfs_hcintmsk4_bit_t HCINTMSK4_b; + stc_usbfs_hctsiz4_bit_t HCTSIZ4_b; + uint32_t RESERVED10[96]; + stc_usbfs_hcchar5_bit_t HCCHAR5_b; + stc_usbfs_hcsplt5_bit_t HCSPLT5_b; + stc_usbfs_hcint5_bit_t HCINT5_b; + stc_usbfs_hcintmsk5_bit_t HCINTMSK5_b; + stc_usbfs_hctsiz5_bit_t HCTSIZ5_b; + uint32_t RESERVED11[96]; + stc_usbfs_hcchar6_bit_t HCCHAR6_b; + stc_usbfs_hcsplt6_bit_t HCSPLT6_b; + stc_usbfs_hcint6_bit_t HCINT6_b; + stc_usbfs_hcintmsk6_bit_t HCINTMSK6_b; + stc_usbfs_hctsiz6_bit_t HCTSIZ6_b; + uint32_t RESERVED12[96]; + stc_usbfs_hcchar7_bit_t HCCHAR7_b; + stc_usbfs_hcsplt7_bit_t HCSPLT7_b; + stc_usbfs_hcint7_bit_t HCINT7_b; + stc_usbfs_hcintmsk7_bit_t HCINTMSK7_b; + stc_usbfs_hctsiz7_bit_t HCTSIZ7_b; + uint32_t RESERVED13[96]; + stc_usbfs_hcchar8_bit_t HCCHAR8_b; + stc_usbfs_hcsplt8_bit_t HCSPLT8_b; + stc_usbfs_hcint8_bit_t HCINT8_b; + stc_usbfs_hcintmsk8_bit_t HCINTMSK8_b; + stc_usbfs_hctsiz8_bit_t HCTSIZ8_b; + uint32_t RESERVED14[96]; + stc_usbfs_hcchar9_bit_t HCCHAR9_b; + stc_usbfs_hcsplt9_bit_t HCSPLT9_b; + stc_usbfs_hcint9_bit_t HCINT9_b; + stc_usbfs_hcintmsk9_bit_t HCINTMSK9_b; + stc_usbfs_hctsiz9_bit_t HCTSIZ9_b; + uint32_t RESERVED15[96]; + stc_usbfs_hcchar10_bit_t HCCHAR10_b; + stc_usbfs_hcsplt10_bit_t HCSPLT10_b; + stc_usbfs_hcint10_bit_t HCINT10_b; + stc_usbfs_hcintmsk10_bit_t HCINTMSK10_b; + stc_usbfs_hctsiz10_bit_t HCTSIZ10_b; + uint32_t RESERVED16[96]; + stc_usbfs_hcchar11_bit_t HCCHAR11_b; + stc_usbfs_hcsplt11_bit_t HCSPLT11_b; + stc_usbfs_hcint11_bit_t HCINT11_b; + stc_usbfs_hcintmsk11_bit_t HCINTMSK11_b; + stc_usbfs_hctsiz11_bit_t HCTSIZ11_b; + uint32_t RESERVED17[96]; + stc_usbfs_hcchar12_bit_t HCCHAR12_b; + stc_usbfs_hcsplt12_bit_t HCSPLT12_b; + stc_usbfs_hcint12_bit_t HCINT12_b; + stc_usbfs_hcintmsk12_bit_t HCINTMSK12_b; + stc_usbfs_hctsiz12_bit_t HCTSIZ12_b; + uint32_t RESERVED18[96]; + stc_usbfs_hcchar13_bit_t HCCHAR13_b; + stc_usbfs_hcsplt13_bit_t HCSPLT13_b; + stc_usbfs_hcint13_bit_t HCINT13_b; + stc_usbfs_hcintmsk13_bit_t HCINTMSK13_b; + stc_usbfs_hctsiz13_bit_t HCTSIZ13_b; + uint32_t RESERVED19[96]; + stc_usbfs_hcchar14_bit_t HCCHAR14_b; + stc_usbfs_hcsplt14_bit_t HCSPLT14_b; + stc_usbfs_hcint14_bit_t HCINT14_b; + stc_usbfs_hcintmsk14_bit_t HCINTMSK14_b; + stc_usbfs_hctsiz14_bit_t HCTSIZ14_b; + uint32_t RESERVED20[96]; + stc_usbfs_hcchar15_bit_t HCCHAR15_b; + stc_usbfs_hcsplt15_bit_t HCSPLT15_b; + stc_usbfs_hcint15_bit_t HCINT15_b; + stc_usbfs_hcintmsk15_bit_t HCINTMSK15_b; + stc_usbfs_hctsiz15_bit_t HCTSIZ15_b; + uint32_t RESERVED21[2144]; + stc_usbfs_dcfg_bit_t DCFG_b; + stc_usbfs_dctl_bit_t DCTL_b; + stc_usbfs_dsts_bit_t DSTS_b; + uint32_t RESERVED22[32]; + stc_usbfs_diepmsk_bit_t DIEPMSK_b; + stc_usbfs_doepmsk_bit_t DOEPMSK_b; + stc_usbfs_daint_bit_t DAINT_b; + stc_usbfs_daintmsk_bit_t DAINTMSK_b; + uint32_t RESERVED23[160]; + stc_usbfs_diepempmsk_bit_t DIEPEMPMSK_b; + uint32_t RESERVED24[1600]; + stc_usbfs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED25[32]; + stc_usbfs_diepint0_bit_t DIEPINT0_b; + uint32_t RESERVED26[96]; + stc_usbfs_dtxfsts0_bit_t DTXFSTS0_b; + uint32_t RESERVED27[32]; + stc_usbfs_diepctl1_bit_t DIEPCTL1_b; + uint32_t RESERVED28[32]; + stc_usbfs_diepint1_bit_t DIEPINT1_b; + uint32_t RESERVED29[160]; + stc_usbfs_diepctl2_bit_t DIEPCTL2_b; + uint32_t RESERVED30[32]; + stc_usbfs_diepint2_bit_t DIEPINT2_b; + uint32_t RESERVED31[160]; + stc_usbfs_diepctl3_bit_t DIEPCTL3_b; + uint32_t RESERVED32[32]; + stc_usbfs_diepint3_bit_t DIEPINT3_b; + uint32_t RESERVED33[160]; + stc_usbfs_diepctl4_bit_t DIEPCTL4_b; + uint32_t RESERVED34[32]; + stc_usbfs_diepint4_bit_t DIEPINT4_b; + uint32_t RESERVED35[160]; + stc_usbfs_diepctl5_bit_t DIEPCTL5_b; + uint32_t RESERVED36[32]; + stc_usbfs_diepint5_bit_t DIEPINT5_b; + uint32_t RESERVED37[160]; + stc_usbfs_diepctl6_bit_t DIEPCTL6_b; + uint32_t RESERVED38[32]; + stc_usbfs_diepint6_bit_t DIEPINT6_b; + uint32_t RESERVED39[160]; + stc_usbfs_diepctl7_bit_t DIEPCTL7_b; + uint32_t RESERVED40[32]; + stc_usbfs_diepint7_bit_t DIEPINT7_b; + uint32_t RESERVED41[160]; + stc_usbfs_diepctl8_bit_t DIEPCTL8_b; + uint32_t RESERVED42[32]; + stc_usbfs_diepint8_bit_t DIEPINT8_b; + uint32_t RESERVED43[160]; + stc_usbfs_diepctl9_bit_t DIEPCTL9_b; + uint32_t RESERVED44[32]; + stc_usbfs_diepint9_bit_t DIEPINT9_b; + uint32_t RESERVED45[160]; + stc_usbfs_diepctl10_bit_t DIEPCTL10_b; + uint32_t RESERVED46[32]; + stc_usbfs_diepint10_bit_t DIEPINT10_b; + uint32_t RESERVED47[160]; + stc_usbfs_diepctl11_bit_t DIEPCTL11_b; + uint32_t RESERVED48[32]; + stc_usbfs_diepint11_bit_t DIEPINT11_b; + uint32_t RESERVED49[160]; + stc_usbfs_diepctl12_bit_t DIEPCTL12_b; + uint32_t RESERVED50[32]; + stc_usbfs_diepint12_bit_t DIEPINT12_b; + uint32_t RESERVED51[160]; + stc_usbfs_diepctl13_bit_t DIEPCTL13_b; + uint32_t RESERVED52[32]; + stc_usbfs_diepint13_bit_t DIEPINT13_b; + uint32_t RESERVED53[160]; + stc_usbfs_diepctl14_bit_t DIEPCTL14_b; + uint32_t RESERVED54[32]; + stc_usbfs_diepint14_bit_t DIEPINT14_b; + uint32_t RESERVED55[160]; + stc_usbfs_diepctl15_bit_t DIEPCTL15_b; + uint32_t RESERVED56[32]; + stc_usbfs_diepint15_bit_t DIEPINT15_b; + uint32_t RESERVED57[160]; + stc_usbfs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED58[32]; + stc_usbfs_doepint0_bit_t DOEPINT0_b; + uint32_t RESERVED59[160]; + stc_usbfs_doepctl1_bit_t DOEPCTL1_b; + uint32_t RESERVED60[32]; + stc_usbfs_doepint1_bit_t DOEPINT1_b; + uint32_t RESERVED61[32]; + stc_usbfs_doeptsiz1_bit_t DOEPTSIZ1_b; + uint32_t RESERVED62[96]; + stc_usbfs_doepctl2_bit_t DOEPCTL2_b; + uint32_t RESERVED63[32]; + stc_usbfs_doepint2_bit_t DOEPINT2_b; + uint32_t RESERVED64[32]; + stc_usbfs_doeptsiz2_bit_t DOEPTSIZ2_b; + uint32_t RESERVED65[96]; + stc_usbfs_doepctl3_bit_t DOEPCTL3_b; + uint32_t RESERVED66[32]; + stc_usbfs_doepint3_bit_t DOEPINT3_b; + uint32_t RESERVED67[32]; + stc_usbfs_doeptsiz3_bit_t DOEPTSIZ3_b; + uint32_t RESERVED68[96]; + stc_usbfs_doepctl4_bit_t DOEPCTL4_b; + uint32_t RESERVED69[32]; + stc_usbfs_doepint4_bit_t DOEPINT4_b; + uint32_t RESERVED70[32]; + stc_usbfs_doeptsiz4_bit_t DOEPTSIZ4_b; + uint32_t RESERVED71[96]; + stc_usbfs_doepctl5_bit_t DOEPCTL5_b; + uint32_t RESERVED72[32]; + stc_usbfs_doepint5_bit_t DOEPINT5_b; + uint32_t RESERVED73[32]; + stc_usbfs_doeptsiz5_bit_t DOEPTSIZ5_b; + uint32_t RESERVED74[96]; + stc_usbfs_doepctl6_bit_t DOEPCTL6_b; + uint32_t RESERVED75[32]; + stc_usbfs_doepint6_bit_t DOEPINT6_b; + uint32_t RESERVED76[32]; + stc_usbfs_doeptsiz6_bit_t DOEPTSIZ6_b; + uint32_t RESERVED77[96]; + stc_usbfs_doepctl7_bit_t DOEPCTL7_b; + uint32_t RESERVED78[32]; + stc_usbfs_doepint7_bit_t DOEPINT7_b; + uint32_t RESERVED79[32]; + stc_usbfs_doeptsiz7_bit_t DOEPTSIZ7_b; + uint32_t RESERVED80[96]; + stc_usbfs_doepctl8_bit_t DOEPCTL8_b; + uint32_t RESERVED81[32]; + stc_usbfs_doepint8_bit_t DOEPINT8_b; + uint32_t RESERVED82[32]; + stc_usbfs_doeptsiz8_bit_t DOEPTSIZ8_b; + uint32_t RESERVED83[96]; + stc_usbfs_doepctl9_bit_t DOEPCTL9_b; + uint32_t RESERVED84[32]; + stc_usbfs_doepint9_bit_t DOEPINT9_b; + uint32_t RESERVED85[32]; + stc_usbfs_doeptsiz9_bit_t DOEPTSIZ9_b; + uint32_t RESERVED86[96]; + stc_usbfs_doepctl10_bit_t DOEPCTL10_b; + uint32_t RESERVED87[32]; + stc_usbfs_doepint10_bit_t DOEPINT10_b; + uint32_t RESERVED88[32]; + stc_usbfs_doeptsiz10_bit_t DOEPTSIZ10_b; + uint32_t RESERVED89[96]; + stc_usbfs_doepctl11_bit_t DOEPCTL11_b; + uint32_t RESERVED90[32]; + stc_usbfs_doepint11_bit_t DOEPINT11_b; + uint32_t RESERVED91[32]; + stc_usbfs_doeptsiz11_bit_t DOEPTSIZ11_b; + uint32_t RESERVED92[96]; + stc_usbfs_doepctl12_bit_t DOEPCTL12_b; + uint32_t RESERVED93[32]; + stc_usbfs_doepint12_bit_t DOEPINT12_b; + uint32_t RESERVED94[32]; + stc_usbfs_doeptsiz12_bit_t DOEPTSIZ12_b; + uint32_t RESERVED95[96]; + stc_usbfs_doepctl13_bit_t DOEPCTL13_b; + uint32_t RESERVED96[32]; + stc_usbfs_doepint13_bit_t DOEPINT13_b; + uint32_t RESERVED97[32]; + stc_usbfs_doeptsiz13_bit_t DOEPTSIZ13_b; + uint32_t RESERVED98[96]; + stc_usbfs_doepctl14_bit_t DOEPCTL14_b; + uint32_t RESERVED99[32]; + stc_usbfs_doepint14_bit_t DOEPINT14_b; + uint32_t RESERVED100[32]; + stc_usbfs_doeptsiz14_bit_t DOEPTSIZ14_b; + uint32_t RESERVED101[96]; + stc_usbfs_doepctl15_bit_t DOEPCTL15_b; + uint32_t RESERVED102[32]; + stc_usbfs_doepint15_bit_t DOEPINT15_b; + uint32_t RESERVED103[32]; + stc_usbfs_doeptsiz15_bit_t DOEPTSIZ15_b; + uint32_t RESERVED104[2144]; + stc_usbfs_pcgcctl_bit_t PCGCCTL_b; +} bM4_USBFS_TypeDef; + +typedef struct +{ + stc_usbhs_gotgctl_bit_t GOTGCTL_b; + stc_usbhs_gotgint_bit_t GOTGINT_b; + stc_usbhs_gahbcfg_bit_t GAHBCFG_b; + stc_usbhs_gusbcfg_bit_t GUSBCFG_b; + stc_usbhs_grstctl_bit_t GRSTCTL_b; + stc_usbhs_gintsts_bit_t GINTSTS_b; + stc_usbhs_gintmsk_bit_t GINTMSK_b; + stc_usbhs_grxstsr_bit_t GRXSTSR_b; + stc_usbhs_grxstsp_bit_t GRXSTSP_b; + stc_usbhs_grxfsiz_bit_t GRXFSIZ_b; + stc_usbhs_gnptxfsiz_bit_t GNPTXFSIZ_b; + stc_usbhs_gnptxsts_bit_t GNPTXSTS_b; + uint32_t RESERVED0[32]; + stc_usbhs_gpvndctl_bit_t GPVNDCTL_b; + uint32_t RESERVED1[224]; + stc_usbhs_glpmcfg_bit_t GLPMCFG_b; + uint32_t RESERVED2[32]; + stc_usbhs_gdfifocfg_bit_t GDFIFOCFG_b; + uint32_t RESERVED3[1280]; + stc_usbhs_hptxfsiz_bit_t HPTXFSIZ_b; + stc_usbhs_dieptxf1_bit_t DIEPTXF1_b; + stc_usbhs_dieptxf2_bit_t DIEPTXF2_b; + stc_usbhs_dieptxf3_bit_t DIEPTXF3_b; + stc_usbhs_dieptxf4_bit_t DIEPTXF4_b; + stc_usbhs_dieptxf5_bit_t DIEPTXF5_b; + stc_usbhs_dieptxf6_bit_t DIEPTXF6_b; + stc_usbhs_dieptxf7_bit_t DIEPTXF7_b; + stc_usbhs_dieptxf8_bit_t DIEPTXF8_b; + stc_usbhs_dieptxf9_bit_t DIEPTXF9_b; + stc_usbhs_dieptxf10_bit_t DIEPTXF10_b; + stc_usbhs_dieptxf11_bit_t DIEPTXF11_b; + stc_usbhs_dieptxf12_bit_t DIEPTXF12_b; + stc_usbhs_dieptxf13_bit_t DIEPTXF13_b; + stc_usbhs_dieptxf14_bit_t DIEPTXF14_b; + stc_usbhs_dieptxf15_bit_t DIEPTXF15_b; + uint32_t RESERVED4[5632]; + stc_usbhs_hcfg_bit_t HCFG_b; + stc_usbhs_hfir_bit_t HFIR_b; + stc_usbhs_hfnum_bit_t HFNUM_b; + uint32_t RESERVED5[32]; + stc_usbhs_hptxsts_bit_t HPTXSTS_b; + stc_usbhs_haint_bit_t HAINT_b; + stc_usbhs_haintmsk_bit_t HAINTMSK_b; + uint32_t RESERVED6[288]; + stc_usbhs_hprt_bit_t HPRT_b; + uint32_t RESERVED7[1504]; + stc_usbhs_hcchar0_bit_t HCCHAR0_b; + stc_usbhs_hcsplt0_bit_t HCSPLT0_b; + stc_usbhs_hcint0_bit_t HCINT0_b; + stc_usbhs_hcintmsk0_bit_t HCINTMSK0_b; + stc_usbhs_hctsiz0_bit_t HCTSIZ0_b; + uint32_t RESERVED8[96]; + stc_usbhs_hcchar1_bit_t HCCHAR1_b; + stc_usbhs_hcsplt1_bit_t HCSPLT1_b; + stc_usbhs_hcint1_bit_t HCINT1_b; + stc_usbhs_hcintmsk1_bit_t HCINTMSK1_b; + stc_usbhs_hctsiz1_bit_t HCTSIZ1_b; + uint32_t RESERVED9[96]; + stc_usbhs_hcchar2_bit_t HCCHAR2_b; + stc_usbhs_hcsplt2_bit_t HCSPLT2_b; + stc_usbhs_hcint2_bit_t HCINT2_b; + stc_usbhs_hcintmsk2_bit_t HCINTMSK2_b; + stc_usbhs_hctsiz2_bit_t HCTSIZ2_b; + uint32_t RESERVED10[96]; + stc_usbhs_hcchar3_bit_t HCCHAR3_b; + stc_usbhs_hcsplt3_bit_t HCSPLT3_b; + stc_usbhs_hcint3_bit_t HCINT3_b; + stc_usbhs_hcintmsk3_bit_t HCINTMSK3_b; + stc_usbhs_hctsiz3_bit_t HCTSIZ3_b; + uint32_t RESERVED11[96]; + stc_usbhs_hcchar4_bit_t HCCHAR4_b; + stc_usbhs_hcsplt4_bit_t HCSPLT4_b; + stc_usbhs_hcint4_bit_t HCINT4_b; + stc_usbhs_hcintmsk4_bit_t HCINTMSK4_b; + stc_usbhs_hctsiz4_bit_t HCTSIZ4_b; + uint32_t RESERVED12[96]; + stc_usbhs_hcchar5_bit_t HCCHAR5_b; + stc_usbhs_hcsplt5_bit_t HCSPLT5_b; + stc_usbhs_hcint5_bit_t HCINT5_b; + stc_usbhs_hcintmsk5_bit_t HCINTMSK5_b; + stc_usbhs_hctsiz5_bit_t HCTSIZ5_b; + uint32_t RESERVED13[96]; + stc_usbhs_hcchar6_bit_t HCCHAR6_b; + stc_usbhs_hcsplt6_bit_t HCSPLT6_b; + stc_usbhs_hcint6_bit_t HCINT6_b; + stc_usbhs_hcintmsk6_bit_t HCINTMSK6_b; + stc_usbhs_hctsiz6_bit_t HCTSIZ6_b; + uint32_t RESERVED14[96]; + stc_usbhs_hcchar7_bit_t HCCHAR7_b; + stc_usbhs_hcsplt7_bit_t HCSPLT7_b; + stc_usbhs_hcint7_bit_t HCINT7_b; + stc_usbhs_hcintmsk7_bit_t HCINTMSK7_b; + stc_usbhs_hctsiz7_bit_t HCTSIZ7_b; + uint32_t RESERVED15[96]; + stc_usbhs_hcchar8_bit_t HCCHAR8_b; + stc_usbhs_hcsplt8_bit_t HCSPLT8_b; + stc_usbhs_hcint8_bit_t HCINT8_b; + stc_usbhs_hcintmsk8_bit_t HCINTMSK8_b; + stc_usbhs_hctsiz8_bit_t HCTSIZ8_b; + uint32_t RESERVED16[96]; + stc_usbhs_hcchar9_bit_t HCCHAR9_b; + stc_usbhs_hcsplt9_bit_t HCSPLT9_b; + stc_usbhs_hcint9_bit_t HCINT9_b; + stc_usbhs_hcintmsk9_bit_t HCINTMSK9_b; + stc_usbhs_hctsiz9_bit_t HCTSIZ9_b; + uint32_t RESERVED17[96]; + stc_usbhs_hcchar10_bit_t HCCHAR10_b; + stc_usbhs_hcsplt10_bit_t HCSPLT10_b; + stc_usbhs_hcint10_bit_t HCINT10_b; + stc_usbhs_hcintmsk10_bit_t HCINTMSK10_b; + stc_usbhs_hctsiz10_bit_t HCTSIZ10_b; + uint32_t RESERVED18[96]; + stc_usbhs_hcchar11_bit_t HCCHAR11_b; + stc_usbhs_hcsplt11_bit_t HCSPLT11_b; + stc_usbhs_hcint11_bit_t HCINT11_b; + stc_usbhs_hcintmsk11_bit_t HCINTMSK11_b; + stc_usbhs_hctsiz11_bit_t HCTSIZ11_b; + uint32_t RESERVED19[96]; + stc_usbhs_hcchar12_bit_t HCCHAR12_b; + stc_usbhs_hcsplt12_bit_t HCSPLT12_b; + stc_usbhs_hcint12_bit_t HCINT12_b; + stc_usbhs_hcintmsk12_bit_t HCINTMSK12_b; + stc_usbhs_hctsiz12_bit_t HCTSIZ12_b; + uint32_t RESERVED20[96]; + stc_usbhs_hcchar13_bit_t HCCHAR13_b; + stc_usbhs_hcsplt13_bit_t HCSPLT13_b; + stc_usbhs_hcint13_bit_t HCINT13_b; + stc_usbhs_hcintmsk13_bit_t HCINTMSK13_b; + stc_usbhs_hctsiz13_bit_t HCTSIZ13_b; + uint32_t RESERVED21[96]; + stc_usbhs_hcchar14_bit_t HCCHAR14_b; + stc_usbhs_hcsplt14_bit_t HCSPLT14_b; + stc_usbhs_hcint14_bit_t HCINT14_b; + stc_usbhs_hcintmsk14_bit_t HCINTMSK14_b; + stc_usbhs_hctsiz14_bit_t HCTSIZ14_b; + uint32_t RESERVED22[96]; + stc_usbhs_hcchar15_bit_t HCCHAR15_b; + stc_usbhs_hcsplt15_bit_t HCSPLT15_b; + stc_usbhs_hcint15_bit_t HCINT15_b; + stc_usbhs_hcintmsk15_bit_t HCINTMSK15_b; + stc_usbhs_hctsiz15_bit_t HCTSIZ15_b; + uint32_t RESERVED23[2144]; + stc_usbhs_dcfg_bit_t DCFG_b; + stc_usbhs_dctl_bit_t DCTL_b; + stc_usbhs_dsts_bit_t DSTS_b; + uint32_t RESERVED24[32]; + stc_usbhs_diepmsk_bit_t DIEPMSK_b; + stc_usbhs_doepmsk_bit_t DOEPMSK_b; + stc_usbhs_daint_bit_t DAINT_b; + stc_usbhs_daintmsk_bit_t DAINTMSK_b; + uint32_t RESERVED25[128]; + stc_usbhs_dthrctl_bit_t DTHRCTL_b; + stc_usbhs_diepempmsk_bit_t DIEPEMPMSK_b; + stc_usbhs_deachint_bit_t DEACHINT_b; + stc_usbhs_deachintmsk_bit_t DEACHINTMSK_b; + uint32_t RESERVED26[32]; + stc_usbhs_diepeachmsk1_bit_t DIEPEACHMSK1_b; + uint32_t RESERVED27[480]; + stc_usbhs_doepeachmsk1_bit_t DOEPEACHMSK1_b; + uint32_t RESERVED28[960]; + stc_usbhs_diepctl0_bit_t DIEPCTL0_b; + uint32_t RESERVED29[32]; + stc_usbhs_diepint0_bit_t DIEPINT0_b; + uint32_t RESERVED30[32]; + stc_usbhs_dieptsiz0_bit_t DIEPTSIZ0_b; + uint32_t RESERVED31[32]; + stc_usbhs_dtxfsts0_bit_t DTXFSTS0_b; + uint32_t RESERVED32[32]; + stc_usbhs_diepctl1_bit_t DIEPCTL1_b; + uint32_t RESERVED33[32]; + stc_usbhs_diepint1_bit_t DIEPINT1_b; + uint32_t RESERVED34[32]; + stc_usbhs_dieptsiz1_bit_t DIEPTSIZ1_b; + uint32_t RESERVED35[32]; + stc_usbhs_dtxfsts1_bit_t DTXFSTS1_b; + uint32_t RESERVED36[32]; + stc_usbhs_diepctl2_bit_t DIEPCTL2_b; + uint32_t RESERVED37[32]; + stc_usbhs_diepint2_bit_t DIEPINT2_b; + uint32_t RESERVED38[32]; + stc_usbhs_dieptsiz2_bit_t DIEPTSIZ2_b; + uint32_t RESERVED39[32]; + stc_usbhs_dtxfsts2_bit_t DTXFSTS2_b; + uint32_t RESERVED40[32]; + stc_usbhs_diepctl3_bit_t DIEPCTL3_b; + uint32_t RESERVED41[32]; + stc_usbhs_diepint3_bit_t DIEPINT3_b; + uint32_t RESERVED42[32]; + stc_usbhs_dieptsiz3_bit_t DIEPTSIZ3_b; + uint32_t RESERVED43[32]; + stc_usbhs_dtxfsts3_bit_t DTXFSTS3_b; + uint32_t RESERVED44[32]; + stc_usbhs_diepctl4_bit_t DIEPCTL4_b; + uint32_t RESERVED45[32]; + stc_usbhs_diepint4_bit_t DIEPINT4_b; + uint32_t RESERVED46[32]; + stc_usbhs_dieptsiz4_bit_t DIEPTSIZ4_b; + uint32_t RESERVED47[32]; + stc_usbhs_dtxfsts4_bit_t DTXFSTS4_b; + uint32_t RESERVED48[32]; + stc_usbhs_diepctl5_bit_t DIEPCTL5_b; + uint32_t RESERVED49[32]; + stc_usbhs_diepint5_bit_t DIEPINT5_b; + uint32_t RESERVED50[32]; + stc_usbhs_dieptsiz5_bit_t DIEPTSIZ5_b; + uint32_t RESERVED51[32]; + stc_usbhs_dtxfsts5_bit_t DTXFSTS5_b; + uint32_t RESERVED52[32]; + stc_usbhs_diepctl6_bit_t DIEPCTL6_b; + uint32_t RESERVED53[32]; + stc_usbhs_diepint6_bit_t DIEPINT6_b; + uint32_t RESERVED54[32]; + stc_usbhs_dieptsiz6_bit_t DIEPTSIZ6_b; + uint32_t RESERVED55[32]; + stc_usbhs_dtxfsts6_bit_t DTXFSTS6_b; + uint32_t RESERVED56[32]; + stc_usbhs_diepctl7_bit_t DIEPCTL7_b; + uint32_t RESERVED57[32]; + stc_usbhs_diepint7_bit_t DIEPINT7_b; + uint32_t RESERVED58[32]; + stc_usbhs_dieptsiz7_bit_t DIEPTSIZ7_b; + uint32_t RESERVED59[32]; + stc_usbhs_dtxfsts7_bit_t DTXFSTS7_b; + uint32_t RESERVED60[32]; + stc_usbhs_diepctl8_bit_t DIEPCTL8_b; + uint32_t RESERVED61[32]; + stc_usbhs_diepint8_bit_t DIEPINT8_b; + uint32_t RESERVED62[32]; + stc_usbhs_dieptsiz8_bit_t DIEPTSIZ8_b; + uint32_t RESERVED63[32]; + stc_usbhs_dtxfsts8_bit_t DTXFSTS8_b; + uint32_t RESERVED64[32]; + stc_usbhs_diepctl9_bit_t DIEPCTL9_b; + uint32_t RESERVED65[32]; + stc_usbhs_diepint9_bit_t DIEPINT9_b; + uint32_t RESERVED66[32]; + stc_usbhs_dieptsiz9_bit_t DIEPTSIZ9_b; + uint32_t RESERVED67[32]; + stc_usbhs_dtxfsts9_bit_t DTXFSTS9_b; + uint32_t RESERVED68[32]; + stc_usbhs_diepctl10_bit_t DIEPCTL10_b; + uint32_t RESERVED69[32]; + stc_usbhs_diepint10_bit_t DIEPINT10_b; + uint32_t RESERVED70[32]; + stc_usbhs_dieptsiz10_bit_t DIEPTSIZ10_b; + uint32_t RESERVED71[32]; + stc_usbhs_dtxfsts10_bit_t DTXFSTS10_b; + uint32_t RESERVED72[32]; + stc_usbhs_diepctl11_bit_t DIEPCTL11_b; + uint32_t RESERVED73[32]; + stc_usbhs_diepint11_bit_t DIEPINT11_b; + uint32_t RESERVED74[32]; + stc_usbhs_dieptsiz11_bit_t DIEPTSIZ11_b; + uint32_t RESERVED75[32]; + stc_usbhs_dtxfsts11_bit_t DTXFSTS11_b; + uint32_t RESERVED76[32]; + stc_usbhs_diepctl12_bit_t DIEPCTL12_b; + uint32_t RESERVED77[32]; + stc_usbhs_diepint12_bit_t DIEPINT12_b; + uint32_t RESERVED78[32]; + stc_usbhs_dieptsiz12_bit_t DIEPTSIZ12_b; + uint32_t RESERVED79[32]; + stc_usbhs_dtxfsts12_bit_t DTXFSTS12_b; + uint32_t RESERVED80[32]; + stc_usbhs_diepctl13_bit_t DIEPCTL13_b; + uint32_t RESERVED81[32]; + stc_usbhs_diepint13_bit_t DIEPINT13_b; + uint32_t RESERVED82[32]; + stc_usbhs_dieptsiz13_bit_t DIEPTSIZ13_b; + uint32_t RESERVED83[32]; + stc_usbhs_dtxfsts13_bit_t DTXFSTS13_b; + uint32_t RESERVED84[32]; + stc_usbhs_diepctl14_bit_t DIEPCTL14_b; + uint32_t RESERVED85[32]; + stc_usbhs_diepint14_bit_t DIEPINT14_b; + uint32_t RESERVED86[32]; + stc_usbhs_dieptsiz14_bit_t DIEPTSIZ14_b; + uint32_t RESERVED87[32]; + stc_usbhs_dtxfsts14_bit_t DTXFSTS14_b; + uint32_t RESERVED88[32]; + stc_usbhs_diepctl15_bit_t DIEPCTL15_b; + uint32_t RESERVED89[32]; + stc_usbhs_diepint15_bit_t DIEPINT15_b; + uint32_t RESERVED90[32]; + stc_usbhs_dieptsiz15_bit_t DIEPTSIZ15_b; + uint32_t RESERVED91[32]; + stc_usbhs_dtxfsts15_bit_t DTXFSTS15_b; + uint32_t RESERVED92[32]; + stc_usbhs_doepctl0_bit_t DOEPCTL0_b; + uint32_t RESERVED93[32]; + stc_usbhs_doepint0_bit_t DOEPINT0_b; + uint32_t RESERVED94[32]; + stc_usbhs_doeptsiz0_bit_t DOEPTSIZ0_b; + uint32_t RESERVED95[96]; + stc_usbhs_doepctl1_bit_t DOEPCTL1_b; + uint32_t RESERVED96[32]; + stc_usbhs_doepint1_bit_t DOEPINT1_b; + uint32_t RESERVED97[32]; + stc_usbhs_doeptsiz1_bit_t DOEPTSIZ1_b; + uint32_t RESERVED98[96]; + stc_usbhs_doepctl2_bit_t DOEPCTL2_b; + uint32_t RESERVED99[32]; + stc_usbhs_doepint2_bit_t DOEPINT2_b; + uint32_t RESERVED100[32]; + stc_usbhs_doeptsiz2_bit_t DOEPTSIZ2_b; + uint32_t RESERVED101[96]; + stc_usbhs_doepctl3_bit_t DOEPCTL3_b; + uint32_t RESERVED102[32]; + stc_usbhs_doepint3_bit_t DOEPINT3_b; + uint32_t RESERVED103[32]; + stc_usbhs_doeptsiz3_bit_t DOEPTSIZ3_b; + uint32_t RESERVED104[96]; + stc_usbhs_doepctl4_bit_t DOEPCTL4_b; + uint32_t RESERVED105[32]; + stc_usbhs_doepint4_bit_t DOEPINT4_b; + uint32_t RESERVED106[32]; + stc_usbhs_doeptsiz4_bit_t DOEPTSIZ4_b; + uint32_t RESERVED107[96]; + stc_usbhs_doepctl5_bit_t DOEPCTL5_b; + uint32_t RESERVED108[32]; + stc_usbhs_doepint5_bit_t DOEPINT5_b; + uint32_t RESERVED109[32]; + stc_usbhs_doeptsiz5_bit_t DOEPTSIZ5_b; + uint32_t RESERVED110[96]; + stc_usbhs_doepctl6_bit_t DOEPCTL6_b; + uint32_t RESERVED111[32]; + stc_usbhs_doepint6_bit_t DOEPINT6_b; + uint32_t RESERVED112[32]; + stc_usbhs_doeptsiz6_bit_t DOEPTSIZ6_b; + uint32_t RESERVED113[96]; + stc_usbhs_doepctl7_bit_t DOEPCTL7_b; + uint32_t RESERVED114[32]; + stc_usbhs_doepint7_bit_t DOEPINT7_b; + uint32_t RESERVED115[32]; + stc_usbhs_doeptsiz7_bit_t DOEPTSIZ7_b; + uint32_t RESERVED116[96]; + stc_usbhs_doepctl8_bit_t DOEPCTL8_b; + uint32_t RESERVED117[32]; + stc_usbhs_doepint8_bit_t DOEPINT8_b; + uint32_t RESERVED118[32]; + stc_usbhs_doeptsiz8_bit_t DOEPTSIZ8_b; + uint32_t RESERVED119[96]; + stc_usbhs_doepctl9_bit_t DOEPCTL9_b; + uint32_t RESERVED120[32]; + stc_usbhs_doepint9_bit_t DOEPINT9_b; + uint32_t RESERVED121[32]; + stc_usbhs_doeptsiz9_bit_t DOEPTSIZ9_b; + uint32_t RESERVED122[96]; + stc_usbhs_doepctl10_bit_t DOEPCTL10_b; + uint32_t RESERVED123[32]; + stc_usbhs_doepint10_bit_t DOEPINT10_b; + uint32_t RESERVED124[32]; + stc_usbhs_doeptsiz10_bit_t DOEPTSIZ10_b; + uint32_t RESERVED125[96]; + stc_usbhs_doepctl11_bit_t DOEPCTL11_b; + uint32_t RESERVED126[32]; + stc_usbhs_doepint11_bit_t DOEPINT11_b; + uint32_t RESERVED127[32]; + stc_usbhs_doeptsiz11_bit_t DOEPTSIZ11_b; + uint32_t RESERVED128[96]; + stc_usbhs_doepctl12_bit_t DOEPCTL12_b; + uint32_t RESERVED129[32]; + stc_usbhs_doepint12_bit_t DOEPINT12_b; + uint32_t RESERVED130[32]; + stc_usbhs_doeptsiz12_bit_t DOEPTSIZ12_b; + uint32_t RESERVED131[96]; + stc_usbhs_doepctl13_bit_t DOEPCTL13_b; + uint32_t RESERVED132[32]; + stc_usbhs_doepint13_bit_t DOEPINT13_b; + uint32_t RESERVED133[32]; + stc_usbhs_doeptsiz13_bit_t DOEPTSIZ13_b; + uint32_t RESERVED134[96]; + stc_usbhs_doepctl14_bit_t DOEPCTL14_b; + uint32_t RESERVED135[32]; + stc_usbhs_doepint14_bit_t DOEPINT14_b; + uint32_t RESERVED136[32]; + stc_usbhs_doeptsiz14_bit_t DOEPTSIZ14_b; + uint32_t RESERVED137[96]; + stc_usbhs_doepctl15_bit_t DOEPCTL15_b; + uint32_t RESERVED138[32]; + stc_usbhs_doepint15_bit_t DOEPINT15_b; + uint32_t RESERVED139[32]; + stc_usbhs_doeptsiz15_bit_t DOEPTSIZ15_b; + uint32_t RESERVED140[2144]; + stc_usbhs_pcgcctl_bit_t PCGCCTL_b; +} bM4_USBHS_TypeDef; + +typedef struct +{ + stc_wdt_cr_bit_t CR_b; + stc_wdt_sr_bit_t SR_b; +} bM4_WDT_TypeDef; + + + +/******************************************************************************/ +/* Device Specific Peripheral bit_band declaration & memory map */ +/******************************************************************************/ + +#define bM4_ADC1 ((bM4_ADC_TypeDef *)0x42800000UL) +#define bM4_ADC2 ((bM4_ADC_TypeDef *)0x42808000UL) +#define bM4_ADC3 ((bM4_ADC_TypeDef *)0x42810000UL) +#define bM4_AES ((bM4_AES_TypeDef *)0x42100000UL) +#define bM4_AOS ((bM4_AOS_TypeDef *)0x42210000UL) +#define bM4_CAN1 ((bM4_CAN_TypeDef *)0x42120000UL) +#define bM4_CAN2 ((bM4_CAN_TypeDef *)0x42F00000UL) +#define bM4_CMP1 ((bM4_CMP_TypeDef *)0x42940000UL) +#define bM4_CMP2 ((bM4_CMP_TypeDef *)0x42940200UL) +#define bM4_CMP3 ((bM4_CMP_TypeDef *)0x42948000UL) +#define bM4_CMP4 ((bM4_CMP_TypeDef *)0x42948200UL) +#define bM4_CMU ((bM4_CMU_TypeDef *)0x42988000UL) +#define bM4_CRC ((bM4_CRC_TypeDef *)0x42118000UL) +#define bM4_CTC ((bM4_CTC_TypeDef *)0x42938000UL) +#define bM4_DAC1 ((bM4_DAC_TypeDef *)0x42820000UL) +#define bM4_DAC2 ((bM4_DAC_TypeDef *)0x42828000UL) +#define bM4_DCU1 ((bM4_DCU_TypeDef *)0x42AC0000UL) +#define bM4_DCU2 ((bM4_DCU_TypeDef *)0x42AC8000UL) +#define bM4_DCU3 ((bM4_DCU_TypeDef *)0x42AD0000UL) +#define bM4_DCU4 ((bM4_DCU_TypeDef *)0x42AD8000UL) +#define bM4_DCU5 ((bM4_DCU_TypeDef *)0x42AE0000UL) +#define bM4_DCU6 ((bM4_DCU_TypeDef *)0x42AE8000UL) +#define bM4_DCU7 ((bM4_DCU_TypeDef *)0x42AF0000UL) +#define bM4_DCU8 ((bM4_DCU_TypeDef *)0x42AF8000UL) +#define bM4_DMA1 ((bM4_DMA_TypeDef *)0x42A60000UL) +#define bM4_DMA2 ((bM4_DMA_TypeDef *)0x42A68000UL) +#define bM4_DVP ((bM4_DVP_TypeDef *)0x42AB0000UL) +#define bM4_EFM ((bM4_EFM_TypeDef *)0x42208000UL) +#define bM4_EMB0 ((bM4_EMB_TypeDef *)0x422F8000UL) +#define bM4_EMB1 ((bM4_EMB_TypeDef *)0x422F8400UL) +#define bM4_EMB2 ((bM4_EMB_TypeDef *)0x422F8800UL) +#define bM4_EMB3 ((bM4_EMB_TypeDef *)0x422F8C00UL) +#define bM4_EMB4 ((bM4_EMB_TypeDef *)0x422F9000UL) +#define bM4_EMB5 ((bM4_EMB_TypeDef *)0x422F9400UL) +#define bM4_EMB6 ((bM4_EMB_TypeDef *)0x422F9800UL) +#define bM4_ETH ((bM4_ETH_TypeDef *)0x42A00000UL) +#define bM4_FCM ((bM4_FCM_TypeDef *)0x42908000UL) +#define bM4_FMAC1 ((bM4_FMAC_TypeDef *)0x42B00000UL) +#define bM4_FMAC2 ((bM4_FMAC_TypeDef *)0x42B08000UL) +#define bM4_FMAC3 ((bM4_FMAC_TypeDef *)0x42B10000UL) +#define bM4_FMAC4 ((bM4_FMAC_TypeDef *)0x42B18000UL) +#define bM4_GPIO ((bM4_GPIO_TypeDef *)0x42A70000UL) +#define bM4_HASH ((bM4_HASH_TypeDef *)0x42108000UL) +#define bM4_HRPWM ((bM4_HRPWM_TypeDef *)0x42780000UL) +#define bM4_I2C1 ((bM4_I2C_TypeDef *)0x429C0000UL) +#define bM4_I2C2 ((bM4_I2C_TypeDef *)0x429C8000UL) +#define bM4_I2C3 ((bM4_I2C_TypeDef *)0x429D0000UL) +#define bM4_I2C4 ((bM4_I2C_TypeDef *)0x429D8000UL) +#define bM4_I2C5 ((bM4_I2C_TypeDef *)0x429E0000UL) +#define bM4_I2C6 ((bM4_I2C_TypeDef *)0x429F0000UL) +#define bM4_I2S1 ((bM4_I2S_TypeDef *)0x423C0000UL) +#define bM4_I2S2 ((bM4_I2S_TypeDef *)0x423C8000UL) +#define bM4_I2S3 ((bM4_I2S_TypeDef *)0x42440000UL) +#define bM4_I2S4 ((bM4_I2S_TypeDef *)0x42448000UL) +#define bM4_INTC ((bM4_INTC_TypeDef *)0x42A20000UL) +#define bM4_KEYSCAN ((bM4_KEYSCAN_TypeDef *)0x42A18000UL) +#define bM4_MAU ((bM4_MAU_TypeDef *)0x42AA0000UL) +#define bM4_MPU ((bM4_MPU_TypeDef *)0x42A00000UL) +#define bM4_OTS ((bM4_OTS_TypeDef *)0x42950000UL) +#define bM4_PERIC ((bM4_PERIC_TypeDef *)0x42AA8000UL) +#define bM4_PWC ((bM4_PWC_TypeDef *)0x42900000UL) +#define bM4_RMU ((bM4_RMU_TypeDef *)0x42998000UL) +#define bM4_RTC ((bM4_RTC_TypeDef *)0x42980000UL) +#define bM4_SDIOC1 ((bM4_SDIOC_TypeDef *)0x42E00000UL) +#define bM4_SDIOC2 ((bM4_SDIOC_TypeDef *)0x42F08000UL) +#define bM4_SPI1 ((bM4_SPI_TypeDef *)0x42380000UL) +#define bM4_SPI2 ((bM4_SPI_TypeDef *)0x42388000UL) +#define bM4_SPI3 ((bM4_SPI_TypeDef *)0x42390000UL) +#define bM4_SPI4 ((bM4_SPI_TypeDef *)0x42400000UL) +#define bM4_SPI5 ((bM4_SPI_TypeDef *)0x42408000UL) +#define bM4_SPI6 ((bM4_SPI_TypeDef *)0x42410000UL) +#define bM4_SRAMC ((bM4_SRAMC_TypeDef *)0x42A10000UL) +#define bM4_SWDT ((bM4_SWDT_TypeDef *)0x42928000UL) +#define bM4_TMR0_1 ((bM4_TMR0_TypeDef *)0x42480000UL) +#define bM4_TMR0_2 ((bM4_TMR0_TypeDef *)0x42488000UL) +#define bM4_TMR2_1 ((bM4_TMR2_TypeDef *)0x42490000UL) +#define bM4_TMR2_2 ((bM4_TMR2_TypeDef *)0x42498000UL) +#define bM4_TMR2_3 ((bM4_TMR2_TypeDef *)0x424A0000UL) +#define bM4_TMR2_4 ((bM4_TMR2_TypeDef *)0x424A8000UL) +#define bM4_TMR4_1 ((bM4_TMR4_TypeDef *)0x42700000UL) +#define bM4_TMR4_2 ((bM4_TMR4_TypeDef *)0x42708000UL) +#define bM4_TMR4_3 ((bM4_TMR4_TypeDef *)0x42710000UL) +#define bM4_TMR6_1 ((bM4_TMR6_TypeDef *)0x42300000UL) +#define bM4_TMR6_2 ((bM4_TMR6_TypeDef *)0x42308000UL) +#define bM4_TMR6_3 ((bM4_TMR6_TypeDef *)0x42310000UL) +#define bM4_TMR6_4 ((bM4_TMR6_TypeDef *)0x42318000UL) +#define bM4_TMR6_5 ((bM4_TMR6_TypeDef *)0x42320000UL) +#define bM4_TMR6_6 ((bM4_TMR6_TypeDef *)0x42328000UL) +#define bM4_TMR6_7 ((bM4_TMR6_TypeDef *)0x42330000UL) +#define bM4_TMR6_8 ((bM4_TMR6_TypeDef *)0x42338000UL) +#define bM4_TMRA_1 ((bM4_TMRA_TypeDef *)0x42740000UL) +#define bM4_TMRA_10 ((bM4_TMRA_TypeDef *)0x424E8000UL) +#define bM4_TMRA_11 ((bM4_TMRA_TypeDef *)0x424F0000UL) +#define bM4_TMRA_12 ((bM4_TMRA_TypeDef *)0x424F8000UL) +#define bM4_TMRA_2 ((bM4_TMRA_TypeDef *)0x42748000UL) +#define bM4_TMRA_3 ((bM4_TMRA_TypeDef *)0x42750000UL) +#define bM4_TMRA_4 ((bM4_TMRA_TypeDef *)0x42758000UL) +#define bM4_TMRA_5 ((bM4_TMRA_TypeDef *)0x424C0000UL) +#define bM4_TMRA_6 ((bM4_TMRA_TypeDef *)0x424C8000UL) +#define bM4_TMRA_7 ((bM4_TMRA_TypeDef *)0x424D0000UL) +#define bM4_TMRA_8 ((bM4_TMRA_TypeDef *)0x424D8000UL) +#define bM4_TMRA_9 ((bM4_TMRA_TypeDef *)0x424E0000UL) +#define bM4_TRNG ((bM4_TRNG_TypeDef *)0x42840000UL) +#define bM4_USART1 ((bM4_USART_TypeDef *)0x42398000UL) +#define bM4_USART10 ((bM4_USART_TypeDef *)0x42438000UL) +#define bM4_USART2 ((bM4_USART_TypeDef *)0x423A0000UL) +#define bM4_USART3 ((bM4_USART_TypeDef *)0x423A8000UL) +#define bM4_USART4 ((bM4_USART_TypeDef *)0x423B0000UL) +#define bM4_USART5 ((bM4_USART_TypeDef *)0x423B8000UL) +#define bM4_USART6 ((bM4_USART_TypeDef *)0x42418000UL) +#define bM4_USART7 ((bM4_USART_TypeDef *)0x42420000UL) +#define bM4_USART8 ((bM4_USART_TypeDef *)0x42428000UL) +#define bM4_USART9 ((bM4_USART_TypeDef *)0x42430000UL) +#define bM4_USBFS ((bM4_USBFS_TypeDef *)0x43000000UL) +#define bM4_USBHS ((bM4_USBHS_TypeDef *)0x43800000UL) +#define bM4_WDT ((bM4_WDT_TypeDef *)0x42920000UL) + + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_H__ */ + diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/system_hc32f4a0.h b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/system_hc32f4a0.h new file mode 100644 index 0000000000000000000000000000000000000000..985807c3471c45d671a58ed67b59a521e29626a0 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Include/system_hc32f4a0.h @@ -0,0 +1,154 @@ +/** + ******************************************************************************* + * @file system_hc32f4a0.h + * @brief This file contains all the functions prototypes of the HC32 System. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __SYSTEM_HC32F4A0_H__ +#define __SYSTEM_HC32F4A0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F4A0_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Macros + * @{ + */ + +/** + * @brief Clock setup macro definition + */ +#define CLOCK_SETTING_NONE 0U /*!< User provides own clock setting in application */ +#define CLOCK_SETTING_CMSIS 1U + +#define HRC_FREQ_MON() (*((volatile unsigned int*)(0x40010684UL))) + +/** + * @addtogroup HC32F4A0_System_Clock_Source + * @{ + */ +#if !defined (HRC_16MHz_VALUE) + #define HRC_16MHz_VALUE ((uint32_t)16000000UL) /*!< Internal high speed RC freq.(16MHz) */ +#endif + +#if !defined (HRC_20MHz_VALUE) + #define HRC_20MHz_VALUE ((uint32_t)20000000UL) /*!< Internal high speed RC freq.(20MHz) */ +#endif + +#if !defined (MRC_VALUE) +#define MRC_VALUE ((uint32_t)8000000UL) /*!< Internal middle speed RC freq.(8MHz) */ +#endif + +#if !defined (LRC_VALUE) + #define LRC_VALUE ((uint32_t)32768UL) /*!< Internal low speed RC freq.(32.768KHz) */ +#endif + +#if !defined (RTCLRC_VALUE) + #define RTCLRC_VALUE ((uint32_t)32768UL) /*!< Internal RTC low speed RC freq.(32.768KHz) */ +#endif + +#if !defined (SWDTLRC_VALUE) + #define SWDTLRC_VALUE ((uint32_t)10000UL) /*!< External low speed OSC freq.(10KHz) */ +#endif + +#if !defined (XTAL_VALUE) + #define XTAL_VALUE ((uint32_t)8000000UL) /*!< External high speed OSC freq.(8MHz) */ +#endif + +#if !defined (XTAL32_VALUE) + #define XTAL32_VALUE ((uint32_t)32768UL) /*!< External low speed OSC freq.(32.768KHz) */ +#endif + +#if !defined (HCLK_VALUE) +#define HCLK_VALUE (SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS)) +#endif + + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Exported_Variable + * @{ + */ +extern uint32_t SystemCoreClock; /*!< System clock frequency (Core clock) */ +extern uint32_t HRC_VALUE; /*!< HRC frequency */ + +/** + * @} + */ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Functions + * @{ + */ +extern void SystemInit(void); /*!< Initialize the system */ +extern void SystemCoreClockUpdate(void); /*!< Update SystemCoreClock variable */ + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __SYSTEM_HC32F4A0_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/ARM/HDSC_HC32F4A0.SFR b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/ARM/HDSC_HC32F4A0.SFR new file mode 100644 index 0000000000000000000000000000000000000000..348f86cca39c79c8238a3d1f5ad2155579a49e93 Binary files /dev/null and b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/ARM/HDSC_HC32F4A0.SFR differ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/ARM/startup_hc32f4a0.s b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/ARM/startup_hc32f4a0.s new file mode 100644 index 0000000000000000000000000000000000000000..a56f2ef00c4b879329cffce28a8a6ca791953fdd --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/ARM/startup_hc32f4a0.s @@ -0,0 +1,638 @@ +;/****************************************************************************** +;* Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +;* +;* This software is owned and published by: +;* Huada Semiconductor Co.,Ltd ("HDSC"). +;* +;* BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +;* BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +;* +;* This software contains source code for use with HDSC +;* components. This software is licensed by HDSC to be adapted only +;* for use in systems utilizing HDSC components. HDSC shall not be +;* responsible for misuse or illegal use of this software for devices not +;* supported herein. HDSC is providing this software "AS IS" and will +;* not be responsible for issues arising from incorrect user implementation +;* of the software. +;* +;* Disclaimer: +;* HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +;* REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS), +;* ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +;* WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +;* WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +;* WARRANTY OF NONINFRINGEMENT. +;* HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +;* NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +;* LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +;* LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +;* INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +;* INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +;* SAVINGS OR PROFITS, +;* EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +;* YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +;* INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +;* FROM, THE SOFTWARE. +;* +;* This software may be replicated in part or whole for the licensed use, +;* with the restriction that this Disclaimer and Copyright notice must be +;* included with each copy of this software, whether used in part or whole, +;* at all times. +;*/ +;/*****************************************************************************/ + +;/*****************************************************************************/ +;/* Startup for ARM */ +;/* Version V1.0 */ +;/* Date 2020-06-12 */ +;/* Target-mcu HC32F4A0 */ +;/*****************************************************************************/ + +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Stack_Size EQU 0x00002000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> + +Heap_Size EQU 0x00002000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + + + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT IRQ000_Handler [WEAK] + EXPORT IRQ001_Handler [WEAK] + EXPORT IRQ002_Handler [WEAK] + EXPORT IRQ003_Handler [WEAK] + EXPORT IRQ004_Handler [WEAK] + EXPORT IRQ005_Handler [WEAK] + EXPORT IRQ006_Handler [WEAK] + EXPORT IRQ007_Handler [WEAK] + EXPORT IRQ008_Handler [WEAK] + EXPORT IRQ009_Handler [WEAK] + EXPORT IRQ010_Handler [WEAK] + EXPORT IRQ011_Handler [WEAK] + EXPORT IRQ012_Handler [WEAK] + EXPORT IRQ013_Handler [WEAK] + EXPORT IRQ014_Handler [WEAK] + EXPORT IRQ015_Handler [WEAK] + EXPORT IRQ016_Handler [WEAK] + EXPORT IRQ017_Handler [WEAK] + EXPORT IRQ018_Handler [WEAK] + EXPORT IRQ019_Handler [WEAK] + EXPORT IRQ020_Handler [WEAK] + EXPORT IRQ021_Handler [WEAK] + EXPORT IRQ022_Handler [WEAK] + EXPORT IRQ023_Handler [WEAK] + EXPORT IRQ024_Handler [WEAK] + EXPORT IRQ025_Handler [WEAK] + EXPORT IRQ026_Handler [WEAK] + EXPORT IRQ027_Handler [WEAK] + EXPORT IRQ028_Handler [WEAK] + EXPORT IRQ029_Handler [WEAK] + EXPORT IRQ030_Handler [WEAK] + EXPORT IRQ031_Handler [WEAK] + EXPORT IRQ032_Handler [WEAK] + EXPORT IRQ033_Handler [WEAK] + EXPORT IRQ034_Handler [WEAK] + EXPORT IRQ035_Handler [WEAK] + EXPORT IRQ036_Handler [WEAK] + EXPORT IRQ037_Handler [WEAK] + EXPORT IRQ038_Handler [WEAK] + EXPORT IRQ039_Handler [WEAK] + EXPORT IRQ040_Handler [WEAK] + EXPORT IRQ041_Handler [WEAK] + EXPORT IRQ042_Handler [WEAK] + EXPORT IRQ043_Handler [WEAK] + EXPORT IRQ044_Handler [WEAK] + EXPORT IRQ045_Handler [WEAK] + EXPORT IRQ046_Handler [WEAK] + EXPORT IRQ047_Handler [WEAK] + EXPORT IRQ048_Handler [WEAK] + EXPORT IRQ049_Handler [WEAK] + EXPORT IRQ050_Handler [WEAK] + EXPORT IRQ051_Handler [WEAK] + EXPORT IRQ052_Handler [WEAK] + EXPORT IRQ053_Handler [WEAK] + EXPORT IRQ054_Handler [WEAK] + EXPORT IRQ055_Handler [WEAK] + EXPORT IRQ056_Handler [WEAK] + EXPORT IRQ057_Handler [WEAK] + EXPORT IRQ058_Handler [WEAK] + EXPORT IRQ059_Handler [WEAK] + EXPORT IRQ060_Handler [WEAK] + EXPORT IRQ061_Handler [WEAK] + EXPORT IRQ062_Handler [WEAK] + EXPORT IRQ063_Handler [WEAK] + EXPORT IRQ064_Handler [WEAK] + EXPORT IRQ065_Handler [WEAK] + EXPORT IRQ066_Handler [WEAK] + EXPORT IRQ067_Handler [WEAK] + EXPORT IRQ068_Handler [WEAK] + EXPORT IRQ069_Handler [WEAK] + EXPORT IRQ070_Handler [WEAK] + EXPORT IRQ071_Handler [WEAK] + EXPORT IRQ072_Handler [WEAK] + EXPORT IRQ073_Handler [WEAK] + EXPORT IRQ074_Handler [WEAK] + EXPORT IRQ075_Handler [WEAK] + EXPORT IRQ076_Handler [WEAK] + EXPORT IRQ077_Handler [WEAK] + EXPORT IRQ078_Handler [WEAK] + EXPORT IRQ079_Handler [WEAK] + EXPORT IRQ080_Handler [WEAK] + EXPORT IRQ081_Handler [WEAK] + EXPORT IRQ082_Handler [WEAK] + EXPORT IRQ083_Handler [WEAK] + EXPORT IRQ084_Handler [WEAK] + EXPORT IRQ085_Handler [WEAK] + EXPORT IRQ086_Handler [WEAK] + EXPORT IRQ087_Handler [WEAK] + EXPORT IRQ088_Handler [WEAK] + EXPORT IRQ089_Handler [WEAK] + EXPORT IRQ090_Handler [WEAK] + EXPORT IRQ091_Handler [WEAK] + EXPORT IRQ092_Handler [WEAK] + EXPORT IRQ093_Handler [WEAK] + EXPORT IRQ094_Handler [WEAK] + EXPORT IRQ095_Handler [WEAK] + EXPORT IRQ096_Handler [WEAK] + EXPORT IRQ097_Handler [WEAK] + EXPORT IRQ098_Handler [WEAK] + EXPORT IRQ099_Handler [WEAK] + EXPORT IRQ100_Handler [WEAK] + EXPORT IRQ101_Handler [WEAK] + EXPORT IRQ102_Handler [WEAK] + EXPORT IRQ103_Handler [WEAK] + EXPORT IRQ104_Handler [WEAK] + EXPORT IRQ105_Handler [WEAK] + EXPORT IRQ106_Handler [WEAK] + EXPORT IRQ107_Handler [WEAK] + EXPORT IRQ108_Handler [WEAK] + EXPORT IRQ109_Handler [WEAK] + EXPORT IRQ110_Handler [WEAK] + EXPORT IRQ111_Handler [WEAK] + EXPORT IRQ112_Handler [WEAK] + EXPORT IRQ113_Handler [WEAK] + EXPORT IRQ114_Handler [WEAK] + EXPORT IRQ115_Handler [WEAK] + EXPORT IRQ116_Handler [WEAK] + EXPORT IRQ117_Handler [WEAK] + EXPORT IRQ118_Handler [WEAK] + EXPORT IRQ119_Handler [WEAK] + EXPORT IRQ120_Handler [WEAK] + EXPORT IRQ121_Handler [WEAK] + EXPORT IRQ122_Handler [WEAK] + EXPORT IRQ123_Handler [WEAK] + EXPORT IRQ124_Handler [WEAK] + EXPORT IRQ125_Handler [WEAK] + EXPORT IRQ126_Handler [WEAK] + EXPORT IRQ127_Handler [WEAK] + EXPORT IRQ128_Handler [WEAK] + EXPORT IRQ129_Handler [WEAK] + EXPORT IRQ130_Handler [WEAK] + EXPORT IRQ131_Handler [WEAK] + EXPORT IRQ132_Handler [WEAK] + EXPORT IRQ133_Handler [WEAK] + EXPORT IRQ134_Handler [WEAK] + EXPORT IRQ135_Handler [WEAK] + EXPORT IRQ136_Handler [WEAK] + EXPORT IRQ137_Handler [WEAK] + EXPORT IRQ138_Handler [WEAK] + EXPORT IRQ139_Handler [WEAK] + EXPORT IRQ140_Handler [WEAK] + EXPORT IRQ141_Handler [WEAK] + EXPORT IRQ142_Handler [WEAK] + EXPORT IRQ143_Handler [WEAK] + +IRQ000_Handler +IRQ001_Handler +IRQ002_Handler +IRQ003_Handler +IRQ004_Handler +IRQ005_Handler +IRQ006_Handler +IRQ007_Handler +IRQ008_Handler +IRQ009_Handler +IRQ010_Handler +IRQ011_Handler +IRQ012_Handler +IRQ013_Handler +IRQ014_Handler +IRQ015_Handler +IRQ016_Handler +IRQ017_Handler +IRQ018_Handler +IRQ019_Handler +IRQ020_Handler +IRQ021_Handler +IRQ022_Handler +IRQ023_Handler +IRQ024_Handler +IRQ025_Handler +IRQ026_Handler +IRQ027_Handler +IRQ028_Handler +IRQ029_Handler +IRQ030_Handler +IRQ031_Handler +IRQ032_Handler +IRQ033_Handler +IRQ034_Handler +IRQ035_Handler +IRQ036_Handler +IRQ037_Handler +IRQ038_Handler +IRQ039_Handler +IRQ040_Handler +IRQ041_Handler +IRQ042_Handler +IRQ043_Handler +IRQ044_Handler +IRQ045_Handler +IRQ046_Handler +IRQ047_Handler +IRQ048_Handler +IRQ049_Handler +IRQ050_Handler +IRQ051_Handler +IRQ052_Handler +IRQ053_Handler +IRQ054_Handler +IRQ055_Handler +IRQ056_Handler +IRQ057_Handler +IRQ058_Handler +IRQ059_Handler +IRQ060_Handler +IRQ061_Handler +IRQ062_Handler +IRQ063_Handler +IRQ064_Handler +IRQ065_Handler +IRQ066_Handler +IRQ067_Handler +IRQ068_Handler +IRQ069_Handler +IRQ070_Handler +IRQ071_Handler +IRQ072_Handler +IRQ073_Handler +IRQ074_Handler +IRQ075_Handler +IRQ076_Handler +IRQ077_Handler +IRQ078_Handler +IRQ079_Handler +IRQ080_Handler +IRQ081_Handler +IRQ082_Handler +IRQ083_Handler +IRQ084_Handler +IRQ085_Handler +IRQ086_Handler +IRQ087_Handler +IRQ088_Handler +IRQ089_Handler +IRQ090_Handler +IRQ091_Handler +IRQ092_Handler +IRQ093_Handler +IRQ094_Handler +IRQ095_Handler +IRQ096_Handler +IRQ097_Handler +IRQ098_Handler +IRQ099_Handler +IRQ100_Handler +IRQ101_Handler +IRQ102_Handler +IRQ103_Handler +IRQ104_Handler +IRQ105_Handler +IRQ106_Handler +IRQ107_Handler +IRQ108_Handler +IRQ109_Handler +IRQ110_Handler +IRQ111_Handler +IRQ112_Handler +IRQ113_Handler +IRQ114_Handler +IRQ115_Handler +IRQ116_Handler +IRQ117_Handler +IRQ118_Handler +IRQ119_Handler +IRQ120_Handler +IRQ121_Handler +IRQ122_Handler +IRQ123_Handler +IRQ124_Handler +IRQ125_Handler +IRQ126_Handler +IRQ127_Handler +IRQ128_Handler +IRQ129_Handler +IRQ130_Handler +IRQ131_Handler +IRQ132_Handler +IRQ133_Handler +IRQ134_Handler +IRQ135_Handler +IRQ136_Handler +IRQ137_Handler +IRQ138_Handler +IRQ139_Handler +IRQ140_Handler +IRQ141_Handler +IRQ142_Handler +IRQ143_Handler + + B . + + ENDP + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + + END diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/GCC/startup_hc32f4a0.S b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/GCC/startup_hc32f4a0.S new file mode 100644 index 0000000000000000000000000000000000000000..16a5a540a7bdff23ec077f8b94d6bbf2cf93640c --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/GCC/startup_hc32f4a0.S @@ -0,0 +1,565 @@ +/* +;******************************************************************************* +; Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +; +; This software is owned and published by: +; Huada Semiconductor Co.,Ltd ("HDSC"). +; +; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +; +; This software contains source code for use with HDSC +; components. This software is licensed by HDSC to be adapted only +; for use in systems utilizing HDSC components. HDSC shall not be +; responsible for misuse or illegal use of this software for devices not +; supported herein. HDSC is providing this software "AS IS" and will +; not be responsible for issues arising from incorrect user implementation +; of the software. +; +; Disclaimer: +; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +; REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS), +; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +; WARRANTY OF NONINFRINGEMENT. +; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +; SAVINGS OR PROFITS, +; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +; FROM, THE SOFTWARE. +; +; This software may be replicated in part or whole for the licensed use, +; with the restriction that this Disclaimer and Copyright notice must be +; included with each copy of this software, whether used in part or whole, +; at all times. +;/ +*/ +/*****************************************************************************/ +/* Startup for GCC */ +/* Version V1.0 */ +/* Date 2020-06-12 */ +/* Target-mcu HC32F4A0 */ +/*****************************************************************************/ + +/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +*/ + + .syntax unified + .arch armv7e-m + .cpu cortex-m4 + .fpu softvfp + .thumb + +/* +; Stack Configuration +; Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Stack_Size, 0x00002000 + + .section .stack + .align 3 + .globl __StackTop + .globl __StackLimit +__StackLimit: + .space Stack_Size + .size __StackLimit, . - __StackLimit +__StackTop: + .size __StackTop, . - __StackTop + + +/* +; Heap Configuration +; Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; +*/ + .equ Heap_Size, 0x00002000 + + .if Heap_Size != 0 /* Heap is provided */ + .section .heap + .align 3 + .globl __HeapBase + .globl __HeapLimit +__HeapBase: + .space Heap_Size + .size __HeapBase, . - __HeapBase +__HeapLimit: + .size __HeapLimit, . - __HeapLimit + .endif + +/* +; Interrupt vector table start. +*/ + .section .vectors, "a", %progbits + .align 2 + .type __Vectors, %object + .globl __Vectors + .globl __Vectors_End + .globl __Vectors_Size +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* -14 NMI Handler */ + .long HardFault_Handler /* -13 Hard Fault Handler */ + .long MemManage_Handler /* -12 MPU Fault Handler */ + .long BusFault_Handler /* -11 Bus Fault Handler */ + .long UsageFault_Handler /* -10 Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* -5 SVCall Handler */ + .long DebugMon_Handler /* -4 Debug Monitor Handler */ + .long 0 /* Reserved */ + .long PendSV_Handler /* -2 PendSV Handler */ + .long SysTick_Handler /* -1 SysTick Handler */ + + /* Interrupts */ + .long IRQ000_Handler + .long IRQ001_Handler + .long IRQ002_Handler + .long IRQ003_Handler + .long IRQ004_Handler + .long IRQ005_Handler + .long IRQ006_Handler + .long IRQ007_Handler + .long IRQ008_Handler + .long IRQ009_Handler + .long IRQ010_Handler + .long IRQ011_Handler + .long IRQ012_Handler + .long IRQ013_Handler + .long IRQ014_Handler + .long IRQ015_Handler + .long IRQ016_Handler + .long IRQ017_Handler + .long IRQ018_Handler + .long IRQ019_Handler + .long IRQ020_Handler + .long IRQ021_Handler + .long IRQ022_Handler + .long IRQ023_Handler + .long IRQ024_Handler + .long IRQ025_Handler + .long IRQ026_Handler + .long IRQ027_Handler + .long IRQ028_Handler + .long IRQ029_Handler + .long IRQ030_Handler + .long IRQ031_Handler + .long IRQ032_Handler + .long IRQ033_Handler + .long IRQ034_Handler + .long IRQ035_Handler + .long IRQ036_Handler + .long IRQ037_Handler + .long IRQ038_Handler + .long IRQ039_Handler + .long IRQ040_Handler + .long IRQ041_Handler + .long IRQ042_Handler + .long IRQ043_Handler + .long IRQ044_Handler + .long IRQ045_Handler + .long IRQ046_Handler + .long IRQ047_Handler + .long IRQ048_Handler + .long IRQ049_Handler + .long IRQ050_Handler + .long IRQ051_Handler + .long IRQ052_Handler + .long IRQ053_Handler + .long IRQ054_Handler + .long IRQ055_Handler + .long IRQ056_Handler + .long IRQ057_Handler + .long IRQ058_Handler + .long IRQ059_Handler + .long IRQ060_Handler + .long IRQ061_Handler + .long IRQ062_Handler + .long IRQ063_Handler + .long IRQ064_Handler + .long IRQ065_Handler + .long IRQ066_Handler + .long IRQ067_Handler + .long IRQ068_Handler + .long IRQ069_Handler + .long IRQ070_Handler + .long IRQ071_Handler + .long IRQ072_Handler + .long IRQ073_Handler + .long IRQ074_Handler + .long IRQ075_Handler + .long IRQ076_Handler + .long IRQ077_Handler + .long IRQ078_Handler + .long IRQ079_Handler + .long IRQ080_Handler + .long IRQ081_Handler + .long IRQ082_Handler + .long IRQ083_Handler + .long IRQ084_Handler + .long IRQ085_Handler + .long IRQ086_Handler + .long IRQ087_Handler + .long IRQ088_Handler + .long IRQ089_Handler + .long IRQ090_Handler + .long IRQ091_Handler + .long IRQ092_Handler + .long IRQ093_Handler + .long IRQ094_Handler + .long IRQ095_Handler + .long IRQ096_Handler + .long IRQ097_Handler + .long IRQ098_Handler + .long IRQ099_Handler + .long IRQ100_Handler + .long IRQ101_Handler + .long IRQ102_Handler + .long IRQ103_Handler + .long IRQ104_Handler + .long IRQ105_Handler + .long IRQ106_Handler + .long IRQ107_Handler + .long IRQ108_Handler + .long IRQ109_Handler + .long IRQ110_Handler + .long IRQ111_Handler + .long IRQ112_Handler + .long IRQ113_Handler + .long IRQ114_Handler + .long IRQ115_Handler + .long IRQ116_Handler + .long IRQ117_Handler + .long IRQ118_Handler + .long IRQ119_Handler + .long IRQ120_Handler + .long IRQ121_Handler + .long IRQ122_Handler + .long IRQ123_Handler + .long IRQ124_Handler + .long IRQ125_Handler + .long IRQ126_Handler + .long IRQ127_Handler + .long IRQ128_Handler + .long IRQ129_Handler + .long IRQ130_Handler + .long IRQ131_Handler + .long IRQ132_Handler + .long IRQ133_Handler + .long IRQ134_Handler + .long IRQ135_Handler + .long IRQ136_Handler + .long IRQ137_Handler + .long IRQ138_Handler + .long IRQ139_Handler + .long IRQ140_Handler + .long IRQ141_Handler + .long IRQ142_Handler + .long IRQ143_Handler +__Vectors_End: + .equ __Vectors_Size, __Vectors_End - __Vectors + .size __Vectors, . - __Vectors +/* +; Interrupt vector table end. +*/ + +/* +; Reset handler start. +*/ + .section .text.Reset_Handler + .align 2 + .weak Reset_Handler + .type Reset_Handler, %function + .globl Reset_Handler +Reset_Handler: + /* Set stack top pointer. */ + ldr sp, =__StackTop +/* Single section scheme. + * + * The ranges of copy from/to are specified by following symbols + * __etext: LMA of start of the section to copy from. Usually end of text + * __data_start__: VMA of start of the section to copy to + * __data_end__: VMA of end of the section to copy to + * + * All addresses must be aligned to 4 bytes boundary. + */ +StackInit: + ldr r1, =__StackLimit + ldr r2, =__StackTop + + movs r0, 0 +StackInitLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt StackInitLoop + +ClrSramSR: + ldr r0, =0x40050810 + ldr r1, =0x1FF + str r1, [r0] + + /* Copy data from read only memory to RAM. */ +CopyData: + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ +CopyLoop: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop + +CopyData1: + ldr r1, =__etext_ramb + ldr r2, =__data_start_ramb__ + ldr r3, =__data_end_ramb__ +CopyLoop1: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt CopyLoop1 + +/* This part of work usually is done in C library startup code. + * Otherwise, define this macro to enable it in this startup. + * + * There are two schemes too. + * One can clear multiple BSS sections. Another can only clear one section. + * The former is more size expensive than the latter. + * + * Define macro __STARTUP_CLEAR_BSS_MULTIPLE to choose the former. + * Otherwise define macro __STARTUP_CLEAR_BSS to choose the later. + */ +/* Single BSS section scheme. + * + * The BSS section is specified by following symbols + * __bss_start__: start of the BSS section. + * __bss_end__: end of the BSS section. + * + * Both addresses must be aligned to 4 bytes boundary. + */ + /* Clear BSS section. */ +ClearBss: + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +ClearLoop: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop + +ClearBss1: + ldr r1, =__bss_start_ramb__ + ldr r2, =__bss_end_ramb__ + + movs r0, 0 +ClearLoop1: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt ClearLoop1 + + /* Call the clock system initialization function. */ + bl SystemInit + /* Call the application's entry point. */ + bl main + bx lr + .size Reset_Handler, . - Reset_Handler +/* +; Reset handler end. +*/ + +/* +; Default handler start. +*/ + .section .text.Default_Handler, "ax", %progbits + .align 2 +Default_Handler: + b . + .size Default_Handler, . - Default_Handler +/* +; Default handler end. +*/ + +/* Macro to define default exception/interrupt handlers. + * Default handler are weak symbols with an endless loop. + * They can be overwritten by real handlers. + */ + .macro Set_Default_Handler Handler_Name + .weak \Handler_Name + .set \Handler_Name, Default_Handler + .endm + +/* Default exception/interrupt handler */ + + Set_Default_Handler NMI_Handler + Set_Default_Handler HardFault_Handler + Set_Default_Handler MemManage_Handler + Set_Default_Handler BusFault_Handler + Set_Default_Handler UsageFault_Handler + Set_Default_Handler SVC_Handler + Set_Default_Handler DebugMon_Handler + Set_Default_Handler PendSV_Handler + Set_Default_Handler SysTick_Handler + + Set_Default_Handler IRQ000_Handler + Set_Default_Handler IRQ001_Handler + Set_Default_Handler IRQ002_Handler + Set_Default_Handler IRQ003_Handler + Set_Default_Handler IRQ004_Handler + Set_Default_Handler IRQ005_Handler + Set_Default_Handler IRQ006_Handler + Set_Default_Handler IRQ007_Handler + Set_Default_Handler IRQ008_Handler + Set_Default_Handler IRQ009_Handler + Set_Default_Handler IRQ010_Handler + Set_Default_Handler IRQ011_Handler + Set_Default_Handler IRQ012_Handler + Set_Default_Handler IRQ013_Handler + Set_Default_Handler IRQ014_Handler + Set_Default_Handler IRQ015_Handler + Set_Default_Handler IRQ016_Handler + Set_Default_Handler IRQ017_Handler + Set_Default_Handler IRQ018_Handler + Set_Default_Handler IRQ019_Handler + Set_Default_Handler IRQ020_Handler + Set_Default_Handler IRQ021_Handler + Set_Default_Handler IRQ022_Handler + Set_Default_Handler IRQ023_Handler + Set_Default_Handler IRQ024_Handler + Set_Default_Handler IRQ025_Handler + Set_Default_Handler IRQ026_Handler + Set_Default_Handler IRQ027_Handler + Set_Default_Handler IRQ028_Handler + Set_Default_Handler IRQ029_Handler + Set_Default_Handler IRQ030_Handler + Set_Default_Handler IRQ031_Handler + Set_Default_Handler IRQ032_Handler + Set_Default_Handler IRQ033_Handler + Set_Default_Handler IRQ034_Handler + Set_Default_Handler IRQ035_Handler + Set_Default_Handler IRQ036_Handler + Set_Default_Handler IRQ037_Handler + Set_Default_Handler IRQ038_Handler + Set_Default_Handler IRQ039_Handler + Set_Default_Handler IRQ040_Handler + Set_Default_Handler IRQ041_Handler + Set_Default_Handler IRQ042_Handler + Set_Default_Handler IRQ043_Handler + Set_Default_Handler IRQ044_Handler + Set_Default_Handler IRQ045_Handler + Set_Default_Handler IRQ046_Handler + Set_Default_Handler IRQ047_Handler + Set_Default_Handler IRQ048_Handler + Set_Default_Handler IRQ049_Handler + Set_Default_Handler IRQ050_Handler + Set_Default_Handler IRQ051_Handler + Set_Default_Handler IRQ052_Handler + Set_Default_Handler IRQ053_Handler + Set_Default_Handler IRQ054_Handler + Set_Default_Handler IRQ055_Handler + Set_Default_Handler IRQ056_Handler + Set_Default_Handler IRQ057_Handler + Set_Default_Handler IRQ058_Handler + Set_Default_Handler IRQ059_Handler + Set_Default_Handler IRQ060_Handler + Set_Default_Handler IRQ061_Handler + Set_Default_Handler IRQ062_Handler + Set_Default_Handler IRQ063_Handler + Set_Default_Handler IRQ064_Handler + Set_Default_Handler IRQ065_Handler + Set_Default_Handler IRQ066_Handler + Set_Default_Handler IRQ067_Handler + Set_Default_Handler IRQ068_Handler + Set_Default_Handler IRQ069_Handler + Set_Default_Handler IRQ070_Handler + Set_Default_Handler IRQ071_Handler + Set_Default_Handler IRQ072_Handler + Set_Default_Handler IRQ073_Handler + Set_Default_Handler IRQ074_Handler + Set_Default_Handler IRQ075_Handler + Set_Default_Handler IRQ076_Handler + Set_Default_Handler IRQ077_Handler + Set_Default_Handler IRQ078_Handler + Set_Default_Handler IRQ079_Handler + Set_Default_Handler IRQ080_Handler + Set_Default_Handler IRQ081_Handler + Set_Default_Handler IRQ082_Handler + Set_Default_Handler IRQ083_Handler + Set_Default_Handler IRQ084_Handler + Set_Default_Handler IRQ085_Handler + Set_Default_Handler IRQ086_Handler + Set_Default_Handler IRQ087_Handler + Set_Default_Handler IRQ088_Handler + Set_Default_Handler IRQ089_Handler + Set_Default_Handler IRQ090_Handler + Set_Default_Handler IRQ091_Handler + Set_Default_Handler IRQ092_Handler + Set_Default_Handler IRQ093_Handler + Set_Default_Handler IRQ094_Handler + Set_Default_Handler IRQ095_Handler + Set_Default_Handler IRQ096_Handler + Set_Default_Handler IRQ097_Handler + Set_Default_Handler IRQ098_Handler + Set_Default_Handler IRQ099_Handler + Set_Default_Handler IRQ100_Handler + Set_Default_Handler IRQ101_Handler + Set_Default_Handler IRQ102_Handler + Set_Default_Handler IRQ103_Handler + Set_Default_Handler IRQ104_Handler + Set_Default_Handler IRQ105_Handler + Set_Default_Handler IRQ106_Handler + Set_Default_Handler IRQ107_Handler + Set_Default_Handler IRQ108_Handler + Set_Default_Handler IRQ109_Handler + Set_Default_Handler IRQ110_Handler + Set_Default_Handler IRQ111_Handler + Set_Default_Handler IRQ112_Handler + Set_Default_Handler IRQ113_Handler + Set_Default_Handler IRQ114_Handler + Set_Default_Handler IRQ115_Handler + Set_Default_Handler IRQ116_Handler + Set_Default_Handler IRQ117_Handler + Set_Default_Handler IRQ118_Handler + Set_Default_Handler IRQ119_Handler + Set_Default_Handler IRQ120_Handler + Set_Default_Handler IRQ121_Handler + Set_Default_Handler IRQ122_Handler + Set_Default_Handler IRQ123_Handler + Set_Default_Handler IRQ124_Handler + Set_Default_Handler IRQ125_Handler + Set_Default_Handler IRQ126_Handler + Set_Default_Handler IRQ127_Handler + Set_Default_Handler IRQ128_Handler + Set_Default_Handler IRQ129_Handler + Set_Default_Handler IRQ130_Handler + Set_Default_Handler IRQ131_Handler + Set_Default_Handler IRQ132_Handler + Set_Default_Handler IRQ133_Handler + Set_Default_Handler IRQ134_Handler + Set_Default_Handler IRQ135_Handler + Set_Default_Handler IRQ136_Handler + Set_Default_Handler IRQ137_Handler + Set_Default_Handler IRQ138_Handler + Set_Default_Handler IRQ139_Handler + Set_Default_Handler IRQ140_Handler + Set_Default_Handler IRQ141_Handler + Set_Default_Handler IRQ142_Handler + Set_Default_Handler IRQ143_Handler + + .end diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/IAR/HDSC_HC32F4A0.svd b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/IAR/HDSC_HC32F4A0.svd new file mode 100644 index 0000000000000000000000000000000000000000..3633a20ab1e883218d5d77a485afd63c25e6d221 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/IAR/HDSC_HC32F4A0.svd @@ -0,0 +1,164956 @@ + + + HDSC Co.,Ltd. + HDSC + HDSC_HC32F4A0 + ARMCM4 + 1.0 + + CM4 + r0p1 + little + true + true + 4 + false + + 8 + 32 + 32 + read-write + 0x0 + 0x0 + + + ADC1 + desc ADC1 + 0x40040000 + + 0x0 + 0xC5 + + + + STR + desc STR + 0x0 + 8 + read-write + 0x0 + 0x1 + + + STRT + desc STRT + 0 + 0 + read-write + + + + + CR0 + desc CR0 + 0x2 + 16 + read-write + 0x0 + 0x7F3 + + + MS + desc MS + 1 + 0 + read-write + + + ACCSEL + desc ACCSEL + 5 + 4 + read-write + + + CLREN + desc CLREN + 6 + 6 + read-write + + + DFMT + desc DFMT + 7 + 7 + read-write + + + AVCNT + desc AVCNT + 10 + 8 + read-write + + + + + CR1 + desc CR1 + 0x4 + 16 + read-write + 0x0 + 0x4 + + + RSCHSEL + desc RSCHSEL + 2 + 2 + read-write + + + + + TRGSR + desc TRGSR + 0xA + 16 + read-write + 0x0 + 0x8383 + + + TRGSELA + desc TRGSELA + 1 + 0 + read-write + + + TRGENA + desc TRGENA + 7 + 7 + read-write + + + TRGSELB + desc TRGSELB + 9 + 8 + read-write + + + TRGENB + desc TRGENB + 15 + 15 + read-write + + + + + CHSELRA + desc CHSELRA + 0xC + 32 + read-write + 0x0 + 0xFFFF + + + CHSELA + desc CHSELA + 15 + 0 + read-write + + + + + CHSELRB + desc CHSELRB + 0x10 + 32 + read-write + 0x0 + 0xFFFF + + + CHSELB + desc CHSELB + 15 + 0 + read-write + + + + + AVCHSELR + desc AVCHSELR + 0x14 + 32 + read-write + 0x0 + 0xFFFF + + + AVCHSEL + desc AVCHSEL + 15 + 0 + read-write + + + + + EXCHSELR + desc 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PORTINST1 + 14 + 14 + read-only + + + PORTINST2 + desc PORTINST2 + 15 + 15 + read-only + + + PORTINST3 + desc PORTINST3 + 16 + 16 + read-only + + + PORTINST4 + desc PORTINST4 + 17 + 17 + read-only + + + + + STATCLR + desc STATCLR + 0x30 + 32 + write-only + 0x0 + 0xF0E + + + PWMSFCLR + desc PWMSFCLR + 1 + 1 + write-only + + + CMPFCLR + desc CMPFCLR + 2 + 2 + write-only + + + OSFCLR + desc OSFCLR + 3 + 3 + write-only + + + PORTINFCLR1 + desc PORTINFCLR1 + 8 + 8 + write-only + + + PORTINFCLR2 + desc PORTINFCLR2 + 9 + 9 + write-only + + + PORTINFCLR3 + desc PORTINFCLR3 + 10 + 10 + write-only + + + PORTINFCLR4 + desc PORTINFCLR4 + 11 + 11 + write-only + + + + + INTEN + desc INTEN + 0x34 + 32 + read-write + 0x0 + 0xF0E + + + PWMSINTEN + desc PWMSINTEN + 1 + 1 + read-write + + + CMPINTEN + desc CMPINTEN + 2 + 2 + read-write + + + OSINTEN + desc OSINTEN + 3 + 3 + read-write + + + PORTINTEN1 + desc PORTINTEN1 + 8 + 8 + read-write + + + PORTINTEN2 + desc PORTINTEN2 + 9 + 9 + read-write + + + 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0x93FF + + + SLADDR0 + desc SLADDR0 + 9 + 0 + read-write + + + SLADDR0EN + desc SLADDR0EN + 12 + 12 + read-write + + + ADDRMOD0 + desc ADDRMOD0 + 15 + 15 + read-write + + + + + SLR1 + desc SLR1 + 0x14 + 32 + read-write + 0x0 + 0x93FF + + + SLADDR1 + desc SLADDR1 + 9 + 0 + read-write + + + SLADDR1EN + desc SLADDR1EN + 12 + 12 + read-write + + + ADDRMOD1 + desc ADDRMOD1 + 15 + 15 + read-write + + + + + SLTR + desc SLTR + 0x18 + 32 + read-write + 0xFFFFFFFF + 0xFFFFFFFF + + + TOUTLOW + desc TOUTLOW + 15 + 0 + read-write + + + TOUTHIGH + desc TOUTHIGH + 31 + 16 + read-write + + + + + SR + desc SR + 0x1C + 32 + read-write + 0x0 + 0xF756DF + + + STARTF + desc STARTF + 0 + 0 + read-write + + + SLADDR0F + desc SLADDR0F + 1 + 1 + read-write + + + SLADDR1F + desc SLADDR1F + 2 + 2 + read-write + + + TENDF + desc TENDF + 3 + 3 + read-write + + + STOPF + desc STOPF + 4 + 4 + read-write + + + RFULLF + desc RFULLF + 6 + 6 + read-write + + + TEMPTYF + desc TEMPTYF + 7 + 7 + read-write + + + ARLOF + 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INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL114 + desc SEL114 + 0x224 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL115 + desc SEL115 + 0x228 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL116 + desc SEL116 + 0x22C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL117 + desc SEL117 + 0x230 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL118 + desc SEL118 + 0x234 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL119 + desc SEL119 + 0x238 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL120 + desc SEL120 + 0x23C + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + read-write + + + + + SEL121 + desc SEL121 + 0x240 + 32 + read-write + 0x1FF + 0x1FF + + + INTSEL + desc INTSEL + 8 + 0 + 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VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL129 + desc VSSEL129 + 0x260 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + VSEL0 + desc VSEL0 + 0 + 0 + read-write + + + VSEL1 + desc VSEL1 + 1 + 1 + read-write + + + VSEL2 + desc VSEL2 + 2 + 2 + read-write + + + VSEL3 + desc VSEL3 + 3 + 3 + read-write + + + VSEL4 + desc VSEL4 + 4 + 4 + read-write + + + VSEL5 + desc VSEL5 + 5 + 5 + read-write + + + VSEL6 + desc VSEL6 + 6 + 6 + read-write + + + VSEL7 + desc VSEL7 + 7 + 7 + read-write + + + VSEL8 + desc VSEL8 + 8 + 8 + read-write + + + VSEL9 + desc VSEL9 + 9 + 9 + read-write + + + VSEL10 + desc VSEL10 + 10 + 10 + read-write + + + VSEL11 + desc VSEL11 + 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VSEL13 + desc VSEL13 + 13 + 13 + read-write + + + VSEL14 + desc VSEL14 + 14 + 14 + read-write + + + VSEL15 + desc VSEL15 + 15 + 15 + read-write + + + VSEL16 + desc VSEL16 + 16 + 16 + read-write + + + VSEL17 + desc VSEL17 + 17 + 17 + read-write + + + VSEL18 + desc VSEL18 + 18 + 18 + read-write + + + VSEL19 + desc VSEL19 + 19 + 19 + read-write + + + VSEL20 + desc VSEL20 + 20 + 20 + read-write + + + VSEL21 + desc VSEL21 + 21 + 21 + read-write + + + VSEL22 + desc VSEL22 + 22 + 22 + read-write + + + VSEL23 + desc VSEL23 + 23 + 23 + read-write + + + VSEL24 + desc VSEL24 + 24 + 24 + read-write + + + VSEL25 + desc VSEL25 + 25 + 25 + read-write + + + VSEL26 + desc VSEL26 + 26 + 26 + read-write + + + VSEL27 + desc VSEL27 + 27 + 27 + read-write + + + VSEL28 + desc VSEL28 + 28 + 28 + read-write + + + VSEL29 + desc VSEL29 + 29 + 29 + read-write + + + VSEL30 + desc VSEL30 + 30 + 30 + read-write + + + VSEL31 + desc VSEL31 + 31 + 31 + read-write + + + + + VSSEL133 + desc VSSEL133 + 0x270 + 32 + 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BKR23 + desc BKR23 + 0x465C + 8 + read-write + 0x0 + 0xFF + + + BKR24 + desc BKR24 + 0x4660 + 8 + read-write + 0x0 + 0xFF + + + BKR25 + desc BKR25 + 0x4664 + 8 + read-write + 0x0 + 0xFF + + + BKR26 + desc BKR26 + 0x4668 + 8 + read-write + 0x0 + 0xFF + + + BKR27 + desc BKR27 + 0x466C + 8 + read-write + 0x0 + 0xFF + + + BKR28 + desc BKR28 + 0x4670 + 8 + read-write + 0x0 + 0xFF + + + BKR29 + desc BKR29 + 0x4674 + 8 + read-write + 0x0 + 0xFF + + + BKR30 + desc BKR30 + 0x4678 + 8 + read-write + 0x0 + 0xFF + + + BKR31 + desc BKR31 + 0x467C + 8 + read-write + 0x0 + 0xFF + + + BKR32 + desc BKR32 + 0x4680 + 8 + read-write + 0x0 + 0xFF + + + BKR33 + desc BKR33 + 0x4684 + 8 + read-write + 0x0 + 0xFF + + + BKR34 + desc BKR34 + 0x4688 + 8 + read-write + 0x0 + 0xFF + + + BKR35 + desc BKR35 + 0x468C + 8 + read-write + 0x0 + 0xFF + + + BKR36 + desc BKR36 + 0x4690 + 8 + read-write + 0x0 + 0xFF + + + BKR37 + desc BKR37 + 0x4694 + 8 + read-write + 0x0 + 0xFF + + + BKR38 + desc BKR38 + 0x4698 + 8 + read-write + 0x0 + 0xFF + + + BKR39 + desc BKR39 + 0x469C + 8 + read-write + 0x0 + 0xFF + + + BKR40 + desc BKR40 + 0x46A0 + 8 + read-write + 0x0 + 0xFF + + + BKR41 + desc BKR41 + 0x46A4 + 8 + read-write + 0x0 + 0xFF + + + BKR42 + desc BKR42 + 0x46A8 + 8 + read-write + 0x0 + 0xFF + + + BKR43 + desc BKR43 + 0x46AC + 8 + read-write + 0x0 + 0xFF + + + BKR44 + desc BKR44 + 0x46B0 + 8 + read-write + 0x0 + 0xFF + + + BKR45 + desc BKR45 + 0x46B4 + 8 + read-write + 0x0 + 0xFF + + + BKR46 + desc BKR46 + 0x46B8 + 8 + read-write + 0x0 + 0xFF + + + BKR47 + desc BKR47 + 0x46BC + 8 + read-write + 0x0 + 0xFF + + + BKR48 + desc BKR48 + 0x46C0 + 8 + read-write + 0x0 + 0xFF + + + BKR49 + desc BKR49 + 0x46C4 + 8 + read-write + 0x0 + 0xFF + + + BKR50 + desc BKR50 + 0x46C8 + 8 + read-write + 0x0 + 0xFF + + + BKR51 + desc BKR51 + 0x46CC + 8 + read-write + 0x0 + 0xFF + + + BKR52 + desc BKR52 + 0x46D0 + 8 + read-write + 0x0 + 0xFF + + + BKR53 + desc BKR53 + 0x46D4 + 8 + read-write + 0x0 + 0xFF + + + BKR54 + desc BKR54 + 0x46D8 + 8 + read-write + 0x0 + 0xFF + + + BKR55 + desc BKR55 + 0x46DC + 8 + read-write + 0x0 + 0xFF + + + BKR56 + desc BKR56 + 0x46E0 + 8 + read-write + 0x0 + 0xFF + + + BKR57 + desc BKR57 + 0x46E4 + 8 + read-write + 0x0 + 0xFF + + + BKR58 + desc BKR58 + 0x46E8 + 8 + read-write + 0x0 + 0xFF + + + BKR59 + desc BKR59 + 0x46EC + 8 + read-write + 0x0 + 0xFF + + + BKR60 + desc BKR60 + 0x46F0 + 8 + read-write + 0x0 + 0xFF + + + BKR61 + desc BKR61 + 0x46F4 + 8 + read-write + 0x0 + 0xFF + + + BKR62 + desc BKR62 + 0x46F8 + 8 + read-write + 0x0 + 0xFF + + + BKR63 + desc BKR63 + 0x46FC + 8 + read-write + 0x0 + 0xFF + + + BKR64 + desc BKR64 + 0x4700 + 8 + read-write + 0x0 + 0xFF + + + BKR65 + desc BKR65 + 0x4704 + 8 + read-write + 0x0 + 0xFF + + + BKR66 + desc BKR66 + 0x4708 + 8 + read-write + 0x0 + 0xFF + + + BKR67 + desc BKR67 + 0x470C + 8 + read-write + 0x0 + 0xFF + + + BKR68 + desc BKR68 + 0x4710 + 8 + read-write + 0x0 + 0xFF + + + BKR69 + desc BKR69 + 0x4714 + 8 + read-write + 0x0 + 0xFF + + + BKR70 + desc BKR70 + 0x4718 + 8 + read-write + 0x0 + 0xFF + + + BKR71 + desc BKR71 + 0x471C + 8 + read-write + 0x0 + 0xFF + + + BKR72 + desc BKR72 + 0x4720 + 8 + read-write + 0x0 + 0xFF + + + BKR73 + desc BKR73 + 0x4724 + 8 + read-write + 0x0 + 0xFF + + + BKR74 + desc BKR74 + 0x4728 + 8 + read-write + 0x0 + 0xFF + + + BKR75 + desc BKR75 + 0x472C + 8 + read-write + 0x0 + 0xFF + + + BKR76 + desc BKR76 + 0x4730 + 8 + read-write + 0x0 + 0xFF + + + BKR77 + desc BKR77 + 0x4734 + 8 + read-write + 0x0 + 0xFF + + + BKR78 + desc BKR78 + 0x4738 + 8 + read-write + 0x0 + 0xFF + + + BKR79 + desc BKR79 + 0x473C + 8 + read-write + 0x0 + 0xFF + + + BKR80 + desc BKR80 + 0x4740 + 8 + read-write + 0x0 + 0xFF + + + BKR81 + desc BKR81 + 0x4744 + 8 + read-write + 0x0 + 0xFF + + + BKR82 + desc BKR82 + 0x4748 + 8 + read-write + 0x0 + 0xFF + + + BKR83 + desc BKR83 + 0x474C + 8 + read-write + 0x0 + 0xFF + + + BKR84 + desc BKR84 + 0x4750 + 8 + read-write + 0x0 + 0xFF + + + BKR85 + desc BKR85 + 0x4754 + 8 + read-write + 0x0 + 0xFF + + + BKR86 + desc BKR86 + 0x4758 + 8 + read-write + 0x0 + 0xFF + + + BKR87 + desc BKR87 + 0x475C + 8 + read-write + 0x0 + 0xFF + + + BKR88 + desc BKR88 + 0x4760 + 8 + read-write + 0x0 + 0xFF + + + BKR89 + desc BKR89 + 0x4764 + 8 + read-write + 0x0 + 0xFF + + + BKR90 + desc BKR90 + 0x4768 + 8 + read-write + 0x0 + 0xFF + + + BKR91 + desc BKR91 + 0x476C + 8 + read-write + 0x0 + 0xFF + + + BKR92 + desc BKR92 + 0x4770 + 8 + read-write + 0x0 + 0xFF + + + BKR93 + desc BKR93 + 0x4774 + 8 + read-write + 0x0 + 0xFF + + + BKR94 + desc BKR94 + 0x4778 + 8 + read-write + 0x0 + 0xFF + + + BKR95 + desc BKR95 + 0x477C + 8 + read-write + 0x0 + 0xFF + + + BKR96 + desc BKR96 + 0x4780 + 8 + read-write + 0x0 + 0xFF + + + BKR97 + desc BKR97 + 0x4784 + 8 + read-write + 0x0 + 0xFF + + + BKR98 + desc BKR98 + 0x4788 + 8 + read-write + 0x0 + 0xFF + + + BKR99 + desc BKR99 + 0x478C + 8 + read-write + 0x0 + 0xFF + + + BKR100 + desc BKR100 + 0x4790 + 8 + read-write + 0x0 + 0xFF + + + BKR101 + desc BKR101 + 0x4794 + 8 + read-write + 0x0 + 0xFF + + + BKR102 + desc BKR102 + 0x4798 + 8 + read-write + 0x0 + 0xFF + + + BKR103 + desc BKR103 + 0x479C + 8 + read-write + 0x0 + 0xFF + + + BKR104 + desc BKR104 + 0x47A0 + 8 + read-write + 0x0 + 0xFF + + + BKR105 + desc BKR105 + 0x47A4 + 8 + read-write + 0x0 + 0xFF + + + BKR106 + desc BKR106 + 0x47A8 + 8 + read-write + 0x0 + 0xFF + + + BKR107 + desc BKR107 + 0x47AC + 8 + read-write + 0x0 + 0xFF + + + BKR108 + desc BKR108 + 0x47B0 + 8 + read-write + 0x0 + 0xFF + + + BKR109 + desc BKR109 + 0x47B4 + 8 + read-write + 0x0 + 0xFF + + + BKR110 + desc BKR110 + 0x47B8 + 8 + read-write + 0x0 + 0xFF + + + BKR111 + desc BKR111 + 0x47BC + 8 + read-write + 0x0 + 0xFF + + + BKR112 + desc BKR112 + 0x47C0 + 8 + read-write + 0x0 + 0xFF + + + BKR113 + desc BKR113 + 0x47C4 + 8 + read-write + 0x0 + 0xFF + + + BKR114 + desc BKR114 + 0x47C8 + 8 + read-write + 0x0 + 0xFF + + + BKR115 + desc BKR115 + 0x47CC + 8 + read-write + 0x0 + 0xFF + + + BKR116 + desc BKR116 + 0x47D0 + 8 + read-write + 0x0 + 0xFF + + + BKR117 + desc BKR117 + 0x47D4 + 8 + read-write + 0x0 + 0xFF + + + BKR118 + desc BKR118 + 0x47D8 + 8 + read-write + 0x0 + 0xFF + + + BKR119 + desc BKR119 + 0x47DC + 8 + read-write + 0x0 + 0xFF + + + BKR120 + desc BKR120 + 0x47E0 + 8 + read-write + 0x0 + 0xFF + + + BKR121 + desc BKR121 + 0x47E4 + 8 + read-write + 0x0 + 0xFF + + + BKR122 + desc BKR122 + 0x47E8 + 8 + read-write + 0x0 + 0xFF + + + BKR123 + desc BKR123 + 0x47EC + 8 + read-write + 0x0 + 0xFF + + + BKR124 + desc BKR124 + 0x47F0 + 8 + read-write + 0x0 + 0xFF + + + BKR125 + desc BKR125 + 0x47F4 + 8 + read-write + 0x0 + 0xFF + + + BKR126 + desc BKR126 + 0x47F8 + 8 + read-write + 0x0 + 0xFF + + + BKR127 + desc BKR127 + 0x47FC + 8 + read-write + 0x0 + 0xFF + + + PWRC0 + desc PWRC0 + 0x4C00 + 8 + read-write + 0x0 + 0xBB + + + PDMDS + desc PDMDS + 1 + 0 + read-write + + + IORTN + desc IORTN + 5 + 4 + read-write + + + PWDN + desc PWDN + 7 + 7 + read-write + + + + + PWRC1 + desc PWRC1 + 0x4C04 + 8 + read-write + 0x0 + 0xCF + + + VPLLSD + desc VPLLSD + 1 + 0 + read-write + + + VHRCSD + desc VHRCSD + 2 + 2 + read-write + + + PDTS + desc PDTS + 3 + 3 + read-write + + + STPDAS + desc STPDAS + 7 + 6 + read-write + + + + + PWRC2 + desc PWRC2 + 0x4C08 + 8 + read-write + 0xFF + 0x3F + + + DDAS + desc DDAS + 3 + 0 + read-write + + + DVS + desc DVS + 5 + 4 + read-write + + + + + PWRC3 + desc PWRC3 + 0x4C0C + 8 + read-write + 0xFF + 0xFF + + + DDAS + desc DDAS + 7 + 0 + read-write + + + + + PWRC4 + desc PWRC4 + 0x4C10 + 8 + read-write + 0x0 + 0xD3 + + + VBATREFSEL + desc VBATREFSEL + 0 + 0 + read-write + + + VBATME + desc VBATME + 1 + 1 + read-write + + + VBATMON + desc VBATMON + 4 + 4 + read-write + + + ADBUFS + desc ADBUFS + 6 + 6 + read-write + + + ADBUFE + desc ADBUFE + 7 + 7 + read-write + + + + + PVDCR0 + desc PVDCR0 + 0x4C14 + 8 + read-write + 0x0 + 0x61 + + + EXVCCINEN + desc EXVCCINEN + 0 + 0 + read-write + + + PVD1EN + desc PVD1EN + 5 + 5 + read-write + + + PVD2EN + desc PVD2EN + 6 + 6 + read-write + + + + + PVDCR1 + desc PVDCR1 + 0x4C18 + 8 + read-write + 0x0 + 0x77 + + + PVD1IRE + desc PVD1IRE + 0 + 0 + read-write + + + PVD1IRS + desc PVD1IRS + 1 + 1 + read-write + + + PVD1CMPOE + desc PVD1CMPOE + 2 + 2 + read-write + + + PVD2IRE + desc PVD2IRE + 4 + 4 + read-write + + + PVD2IRS + desc PVD2IRS + 5 + 5 + read-write + + + PVD2CMPOE + desc PVD2CMPOE + 6 + 6 + read-write + + + + + PVDFCR + desc PVDFCR + 0x4C1C + 8 + read-write + 0x11 + 0x77 + + + PVD1NFDIS + desc PVD1NFDIS + 0 + 0 + read-write + + + PVD1NFCKS + desc PVD1NFCKS + 2 + 1 + read-write + + + PVD2NFDIS + desc PVD2NFDIS + 4 + 4 + read-write + + + PVD2NFCKS + desc PVD2NFCKS + 6 + 5 + read-write + + + + + PVDLCR + desc PVDLCR + 0x4C20 + 8 + read-write + 0x0 + 0x77 + + + PVD1LVL + desc PVD1LVL + 2 + 0 + read-write + + + PVD2LVL + desc PVD2LVL + 6 + 4 + read-write + + + + + PDWKE0 + desc PDWKE0 + 0x4C28 + 8 + read-write + 0x0 + 0xFF + + + WKE0_0 + desc WKE0_0 + 0 + 0 + read-write + + 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read-write + + + RTCALMWKE + desc RTCALMWKE + 5 + 5 + read-write + + + XTAL32ERWKE + desc XTAL32ERWKE + 6 + 6 + read-write + + + WKTMWKE + desc WKTMWKE + 7 + 7 + read-write + + + + + PDWKES + desc PDWKES + 0x4C34 + 8 + read-write + 0x0 + 0x3F + + + WK0EGS + desc WK0EGS + 0 + 0 + read-write + + + WK1EGS + desc WK1EGS + 1 + 1 + read-write + + + WK2EGS + desc WK2EGS + 2 + 2 + read-write + + + WK3EGS + desc WK3EGS + 3 + 3 + read-write + + + VD1EGS + desc VD1EGS + 4 + 4 + read-write + + + VD2EGS + desc VD2EGS + 5 + 5 + read-write + + + + + PDWKF0 + desc PDWKF0 + 0x4C38 + 8 + read-write + 0x0 + 0x3F + + + PTWK0F + desc PTWK0F + 0 + 0 + read-write + + + PTWK1F + desc PTWK1F + 1 + 1 + read-write + + + PTWK2F + desc PTWK2F + 2 + 2 + read-write + + + PTWK3F + desc PTWK3F + 3 + 3 + read-write + + + VD1WKF + desc VD1WKF + 4 + 4 + read-write + + + VD2WKF + desc VD2WKF + 5 + 5 + read-write + + + + + PDWKF1 + desc PDWKF1 + 0x4C3C + 8 + read-write + 0x0 + 0xF8 + + + RXD0WKF + desc RXD0WKF + 3 + 3 + read-write + + + RTCPRDWKF + desc RTCPRDWKF + 4 + 4 + read-write + + + RTCALMWKF + desc RTCALMWKF + 5 + 5 + read-write + + + XTAL32ERWKF + desc XTAL32ERWKF + 6 + 6 + read-write + + + WKTMWKF + desc WKTMWKF + 7 + 7 + read-write + + + + + RAMPC0 + desc RAMPC0 + 0x4CE0 + 32 + read-write + 0x0 + 0x7FF + + + RAMPDC0 + desc RAMPDC0 + 0 + 0 + read-write + + + RAMPDC1 + desc RAMPDC1 + 1 + 1 + read-write + + + RAMPDC2 + desc RAMPDC2 + 2 + 2 + read-write + + + RAMPDC3 + desc RAMPDC3 + 3 + 3 + read-write + + + RAMPDC4 + desc RAMPDC4 + 4 + 4 + read-write + + + RAMPDC5 + desc RAMPDC5 + 5 + 5 + read-write + + + RAMPDC6 + desc RAMPDC6 + 6 + 6 + read-write + + + RAMPDC7 + desc RAMPDC7 + 7 + 7 + read-write + + + RAMPDC8 + desc RAMPDC8 + 8 + 8 + read-write + + + RAMPDC9 + desc RAMPDC9 + 9 + 9 + read-write + + + RAMPDC10 + desc RAMPDC10 + 10 + 10 + read-write + + + + + RAMOPM + desc RAMOPM + 0x4CE4 + 32 + read-write + 0x8043 + 0xFFFF + + + RAMOPM + desc RAMOPM + 15 + 0 + read-write + + + + + PRAMLPC + desc PRAMLPC + 0x4CE8 + 32 + read-write + 0x0 + 0x3FF + + + PRAMPDC0 + desc PRAMPDC0 + 0 + 0 + read-write + + + PRAMPDC1 + desc PRAMPDC1 + 1 + 1 + read-write + + + PRAMPDC2 + desc PRAMPDC2 + 2 + 2 + read-write + + + PRAMPDC3 + desc PRAMPDC3 + 3 + 3 + read-write + + + PRAMPDC4 + desc PRAMPDC4 + 4 + 4 + read-write + + + PRAMPDC5 + desc PRAMPDC5 + 5 + 5 + read-write + + + PRAMPDC6 + desc PRAMPDC6 + 6 + 6 + read-write + + + PRAMPDC7 + desc PRAMPDC7 + 7 + 7 + read-write + + + PRAMPDC8 + desc PRAMPDC8 + 8 + 8 + read-write + + + PRAMPDC9 + desc PRAMPDC9 + 9 + 9 + read-write + + + + + PVDICR + desc PVDICR + 0x4CF0 + 8 + read-write + 0x0 + 0x77 + + + PVD1NMIS + desc PVD1NMIS + 0 + 0 + read-write + + + PVD1EDGS + desc PVD1EDGS + 2 + 1 + read-write + + + PVD2NMIS + desc PVD2NMIS + 4 + 4 + read-write + + + PVD2EDGS + desc PVD2EDGS + 6 + 5 + read-write + + + + + PVDDSR + desc PVDDSR + 0x4CF4 + 8 + read-write + 0x11 + 0x33 + + + PVD1MON + desc PVD1MON + 0 + 0 + read-write + + + PVD1DETFLG + desc PVD1DETFLG + 1 + 1 + read-write + + + PVD2MON + desc PVD2MON + 4 + 4 + read-write + + + PVD2DETFLG + desc PVD2DETFLG + 5 + 5 + read-write + + + + + STPMCR + desc STPMCR + 0xC00C + 16 + read-write + 0x0 + 0xC003 + + + FLNWT + desc FLNWT + 0 + 0 + read-write + + + CKSMRC + desc CKSMRC + 1 + 1 + read-write + + + EXBUSOE + desc EXBUSOE + 14 + 14 + read-write + + + STOP + desc STOP + 15 + 15 + read-write + + + + + FPRC + desc FPRC + 0xC3FE + 16 + read-write + 0x0 + 0xFF0F + + + FPRCB0 + desc FPRCB0 + 0 + 0 + read-write + + + FPRCB1 + desc FPRCB1 + 1 + 1 + read-write + + + FPRCB2 + desc FPRCB2 + 2 + 2 + read-write + + + FPRCB3 + desc FPRCB3 + 3 + 3 + read-write + + + FPRCWE + desc FPRCWE + 15 + 8 + read-write + + + + + + + QSPI + desc QSPI + 0x9C000000 + + 0x0 + 0x808 + + + + CR + desc CR + 0x0 + 32 + read-write + 0x3F0000 + 0x3F3FFF + + + MDSEL + desc MDSEL + 2 + 0 + read-write + + + PFE + desc PFE + 3 + 3 + read-write + + + PFSAE + desc PFSAE + 4 + 4 + read-write + + + DCOME + desc DCOME + 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RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDLE + desc AHBIDLE + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xFFFEFCFF + + + CURMOD + desc CURMOD + 0 + 0 + read-only + + + MODEMIS + desc MODEMIS + 1 + 1 + read-write + + + OTGINT + desc OTGINT + 2 + 2 + read-only + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFLVL + desc RXFLVL + 4 + 4 + read-only + + + NPTXFEMP + desc NPTXFEMP + 5 + 5 + read-only + + + GINNAKEFF + desc GINNAKEFF + 6 + 6 + read-only + + + GOUTNAKEFF + desc GOUTNAKEFF + 7 + 7 + read-only + + + ERLYSUSP + desc ERLYSUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDONE + desc ENUMDONE + 13 + 13 + read-write + + + ISOOUTDROP + desc ISOOUTDROP + 14 + 14 + read-write + + + EOPF + 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PRTINTMSK + desc PRTINTMSK + 24 + 24 + read-write + + + HCHINTMSK + desc HCHINTMSK + 25 + 25 + read-write + + + PTXFEMPMSK + desc PTXFEMPMSK + 26 + 26 + read-write + + + LPM_INTMSK + desc LPM_INTMSK + 27 + 27 + read-write + + + CONIDSTSCHNGMSK + desc CONIDSTSCHNGMSK + 28 + 28 + read-write + + + DISCONNINTMSK + desc DISCONNINTMSK + 29 + 29 + read-write + + + SESSREQINTMSK + desc SESSREQINTMSK + 30 + 30 + read-write + + + WKUPINTMSK + desc WKUPINTMSK + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFFF + + + CHNUM + desc CHNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + FN + desc FN + 24 + 21 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFFF + + + CHNUM + desc CHNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + FN + desc FN + 24 + 21 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x280 + 0x3FF + + + RXFDEP + desc RXFDEP + 9 + 0 + read-write + + + + + GNPTXFSIZ + desc GNPTXFSIZ + 0x28 + 32 + read-write + 0x2800280 + 0x3FF03FF + + + NPTXFSTADDR + desc NPTXFSTADDR + 9 + 0 + read-write + + + NPTXFDEP + desc NPTXFDEP + 25 + 16 + read-write + + + + + GNPTXSTS + desc GNPTXSTS + 0x2C + 32 + read-only + 0x80280 + 0x7FFFFFFF + + + NPTXFSPCAVAIL + desc NPTXFSPCAVAIL + 15 + 0 + read-only + + + NPTXQSPCAVAIL + desc NPTXQSPCAVAIL + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + GUID + desc GUID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + GLPMCFG + desc GLPMCFG + 0x54 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + LPMCAP + desc LPMCAP + 0 + 0 + read-write + + + APPL1RES + desc APPL1RES + 1 + 1 + read-write + + + HIRD + desc HIRD + 5 + 2 + read-write + + + BREMOTEWAKE + desc BREMOTEWAKE + 6 + 6 + read-write + + + ENBLSLPM + desc ENBLSLPM + 7 + 7 + read-write + + + HIRD_THRES + desc HIRD_THRES + 12 + 8 + read-write + + + COREL1RES + desc COREL1RES + 14 + 13 + read-only + + + SLPSTS + desc SLPSTS + 15 + 15 + read-only + + + L1RESUMEOK + desc L1RESUMEOK + 16 + 16 + read-only + + + LPM_CHNL_INDX + desc LPM_CHNL_INDX + 20 + 17 + read-write + + + LPM_RETRY_CNT + desc LPM_RETRY_CNT + 23 + 21 + read-write + + + SNDLPM + desc SNDLPM + 24 + 24 + read-write + + + LPM_RETRYCNT_STS + desc LPM_RETRYCNT_STS + 27 + 25 + read-only + + + LPM_ENBESL + desc LPM_ENBESL + 28 + 28 + read-write + + + LPM_RESTORESLPSTS + desc LPM_RESTORESLPSTS + 29 + 29 + read-write + + + + + GDFIFOCFG + desc GDFIFOCFG + 0x5C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + GDFIFOCFG + desc GDFIFOCFG + 15 + 0 + read-write + + + EPINFOBASEADDR + desc EPINFOBASEADDR + 31 + 16 + read-write + + + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x2600280 + 0x3FF07FF + + + PTXFSTADDR + desc PTXFSTADDR + 10 + 0 + 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INEPNTXFSTADDR + desc INEPNTXFSTADDR + 11 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 25 + 16 + read-write + + + + + DIEPTXF6 + desc DIEPTXF6 + 0x118 + 32 + read-write + 0x2801180 + 0x3FF1FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 12 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 25 + 16 + read-write + + + + + DIEPTXF7 + desc DIEPTXF7 + 0x11C + 32 + read-write + 0x2801400 + 0x3FF1FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 12 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 25 + 16 + read-write + + + + + DIEPTXF8 + desc DIEPTXF8 + 0x120 + 32 + read-write + 0x2801680 + 0x3FF1FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 12 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 25 + 16 + read-write + + + + + DIEPTXF9 + desc DIEPTXF9 + 0x124 + 32 + read-write + 0x2801900 + 0x3FF1FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 12 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 25 + 16 + read-write + + + + + DIEPTXF10 + desc DIEPTXF10 + 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+ + HCINT15 + desc HCINT15 + 0x6E8 + 32 + read-write + 0x0 + 0x7FF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + CHHLTD + desc CHHLTD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + STALL + desc STALL + 3 + 3 + read-write + + + NAK + desc NAK + 4 + 4 + read-write + + + ACK + desc ACK + 5 + 5 + read-write + + + NYET + desc NYET + 6 + 6 + read-write + + + XACTERR + desc XACTERR + 7 + 7 + read-write + + + BBLERR + desc BBLERR + 8 + 8 + read-write + + + FRMOVRUN + desc FRMOVRUN + 9 + 9 + read-write + + + DATATGLERR + desc DATATGLERR + 10 + 10 + read-write + + + + + HCINTMSK15 + desc HCINTMSK15 + 0x6EC + 32 + read-write + 0x0 + 0x7FF + + + XFERCOMPLMSK + desc XFERCOMPLMSK + 0 + 0 + read-write + + + CHHLTDMSK + desc CHHLTDMSK + 1 + 1 + read-write + + + AHBERRMSK + desc AHBERRMSK + 2 + 2 + read-write + + + STALLMSK + desc STALLMSK + 3 + 3 + read-write + + + NAKMSK + desc NAKMSK + 4 + 4 + read-write + + + ACKMSK + desc ACKMSK + 5 + 5 + read-write + + + NYETMSK + desc NYETMSK + 6 + 6 + read-write + + + XACTERRMSK + desc XACTERRMSK + 7 + 7 + read-write + + + BBLERRMSK + desc BBLERRMSK + 8 + 8 + read-write + + + FRMOVRUNMSK + desc FRMOVRUNMSK + 9 + 9 + read-write + + + DATATGLERRMSK + desc DATATGLERRMSK + 10 + 10 + read-write + + + + + HCTSIZ15 + desc HCTSIZ15 + 0x6F0 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + PID + desc PID + 30 + 29 + read-write + + + DOPNG + desc DOPNG + 31 + 31 + read-write + + + + + HCDMA15 + desc HCDMA15 + 0x6F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DCFG + desc DCFG + 0x800 + 32 + read-write + 0x8220000 + 0xFF00DFFF + + + DEVSPD + desc DEVSPD + 1 + 0 + read-write + + + NZSTSOUTHSHK + desc NZSTSOUTHSHK + 2 + 2 + read-write + + + ENA32KHZSUSP + desc ENA32KHZSUSP + 3 + 3 + read-write + + + DEVADDR + desc DEVADDR + 10 + 4 + read-write + + + PERFRINT + desc PERFRINT + 12 + 11 + read-write + + + XCVRDLY + desc XCVRDLY + 14 + 14 + read-write + + + ERRATICINTMSK + desc ERRATICINTMSK + 15 + 15 + read-write + + + PERSCHINTVL + desc PERSCHINTVL + 25 + 24 + read-write + + + RESVALID + desc RESVALID + 31 + 26 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xD8FFF + + + RMTWKUPSIG + desc RMTWKUPSIG + 0 + 0 + read-write + + + SFTDISCON + desc SFTDISCON + 1 + 1 + read-write + + + GNPINNAKSTS + desc GNPINNAKSTS + 2 + 2 + read-only + + + GOUTNAKSTS + desc GOUTNAKSTS + 3 + 3 + read-only + + + TSTCTL + desc TSTCTL + 6 + 4 + read-write + + + SGNPINNAK + desc SGNPINNAK + 7 + 7 + write-only + + + CGNPINNAK + desc CGNPINNAK + 8 + 8 + write-only + + + SGOUTNAK + desc SGOUTNAK + 9 + 9 + write-only + + + CGOUTNAK + desc CGOUTNAK + 10 + 10 + write-only + + + PWRONPRGDONE + desc PWRONPRGDONE + 11 + 11 + read-write + + + IGNRFRMNUM + desc IGNRFRMNUM + 15 + 15 + read-write + + + NAKONBBLE + desc NAKONBBLE + 16 + 16 + read-write + + + DEEPSLEEPBESLREJECT + desc DEEPSLEEPBESLREJECT + 18 + 18 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INEPINT4 + 4 + 4 + read-only + + + INEPINT5 + desc INEPINT5 + 5 + 5 + read-only + + + INEPINT6 + desc INEPINT6 + 6 + 6 + read-only + + + INEPINT7 + desc INEPINT7 + 7 + 7 + read-only + + + INEPINT8 + desc INEPINT8 + 8 + 8 + read-only + + + INEPINT9 + desc INEPINT9 + 9 + 9 + read-only + + + INEPINT10 + desc INEPINT10 + 10 + 10 + read-only + + + INEPINT11 + desc INEPINT11 + 11 + 11 + read-only + + + INEPINT12 + desc INEPINT12 + 12 + 12 + read-only + + + INEPINT13 + desc INEPINT13 + 13 + 13 + read-only + + + INEPINT14 + desc INEPINT14 + 14 + 14 + read-only + + + INEPINT15 + desc INEPINT15 + 15 + 15 + read-only + + + OUTEPINT0 + desc OUTEPINT0 + 16 + 16 + read-only + + + OUTEPINT1 + desc OUTEPINT1 + 17 + 17 + read-only + + + OUTEPINT2 + desc OUTEPINT2 + 18 + 18 + read-only + + + OUTEPINT3 + desc OUTEPINT3 + 19 + 19 + read-only + + + OUTEPINT4 + desc OUTEPINT4 + 20 + 20 + read-only + + + OUTEPINT5 + desc OUTEPINT5 + 21 + 21 + read-only + + + OUTEPINT6 + desc OUTEPINT6 + 22 + 22 + read-only + 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DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL6 + desc DIEPCTL6 + 0x9C0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT6 + desc DIEPINT6 + 0x9C8 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ6 + desc DIEPTSIZ6 + 0x9D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA6 + desc DIEPDMA6 + 0x9D4 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS6 + desc DTXFSTS6 + 0x9D8 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL7 + desc DIEPCTL7 + 0x9E0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT7 + desc DIEPINT7 + 0x9E8 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ7 + desc DIEPTSIZ7 + 0x9F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA7 + desc DIEPDMA7 + 0x9F4 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS7 + desc DTXFSTS7 + 0x9F8 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL8 + desc DIEPCTL8 + 0xA00 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT8 + desc DIEPINT8 + 0xA08 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ8 + desc DIEPTSIZ8 + 0xA10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA8 + desc DIEPDMA8 + 0xA14 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS8 + desc DTXFSTS8 + 0xA18 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL9 + desc DIEPCTL9 + 0xA20 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT9 + desc DIEPINT9 + 0xA28 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ9 + desc DIEPTSIZ9 + 0xA30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA9 + desc DIEPDMA9 + 0xA34 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS9 + desc DTXFSTS9 + 0xA38 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL10 + desc DIEPCTL10 + 0xA40 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT10 + desc DIEPINT10 + 0xA48 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ10 + desc DIEPTSIZ10 + 0xA50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA10 + desc DIEPDMA10 + 0xA54 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS10 + desc DTXFSTS10 + 0xA58 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL11 + desc DIEPCTL11 + 0xA60 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT11 + desc DIEPINT11 + 0xA68 + 32 + read-write + 0x0 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ11 + desc DIEPTSIZ11 + 0xA70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA11 + desc DIEPDMA11 + 0xA74 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS11 + desc DTXFSTS11 + 0xA78 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL12 + desc DIEPCTL12 + 0xA80 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + 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read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA12 + desc DIEPDMA12 + 0xA94 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS12 + desc DTXFSTS12 + 0xA98 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL13 + desc DIEPCTL13 + 0xAA0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + 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read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA13 + desc DIEPDMA13 + 0xAB4 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS13 + desc DTXFSTS13 + 0xAB8 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL14 + desc DIEPCTL14 + 0xAC0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + 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read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA15 + desc DIEPDMA15 + 0xAF4 + 32 + read-write + 0x280 + 0xFFFFFFFF + + + DTXFSTS15 + desc DTXFSTS15 + 0xAF8 + 32 + read-only + 0x0 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-only + 0x8000 + 0xCC3E8003 + + + MPS + desc MPS + 1 + 0 + read-only + + + USBACTEP + desc USBACTEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-only + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + 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+ desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc 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6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + 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NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT10 + desc DOEPINT10 + 0xC48 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ10 + desc DOEPTSIZ10 + 0xC50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA10 + desc DOEPDMA10 + 0xC54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL11 + desc DOEPCTL11 + 0xC60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT11 + desc DOEPINT11 + 0xC68 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + 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0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA13 + desc DOEPDMA13 + 0xCB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL14 + desc DOEPCTL14 + 0xCC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT14 + desc DOEPINT14 + 0xCC8 + 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desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA14 + desc DOEPDMA14 + 0xCD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL15 + desc DOEPCTL15 + 0xCE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT15 + desc DOEPINT15 + 0xCE8 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ15 + desc DOEPTSIZ15 + 0xCF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA15 + desc DOEPDMA15 + 0xCF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PCGCCTL + desc PCGCCTL + 0xE00 + 32 + read-write + 0x0 + 0x1EF + + + STOPPCLK + desc STOPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + desc PWRCLMP + 2 + 2 + read-write + + + RSTPDWNMODULE + desc RSTPDWNMODULE + 3 + 3 + read-write + + + ENBL_L1GATING + desc ENBL_L1GATING + 5 + 5 + read-write + + + PHYSLEEP + desc PHYSLEEP + 6 + 6 + read-only + + + L1SUSPENDED + desc L1SUSPENDED + 7 + 7 + read-only + + + RESETAFTERSUSP + desc RESETAFTERSUSP + 8 + 8 + read-write + + + + + + + USBH + desc USBH + 0x400C0000 + + 0x0 + 0xE04 + + + + GOTGCTL + desc GOTGCTL + 0x0 + 32 + read-only + 0x10000 + 0x803F9FFF + + + SESREQSCS + desc SESREQSCS + 0 + 0 + read-only + + + SESREQ + desc SESREQ + 1 + 1 + read-write + + + VBVALIDOVEN + desc VBVALIDOVEN + 2 + 2 + read-write + + + VBVALIDOVVAL + desc VBVALIDOVVAL + 3 + 3 + read-write + + + AVALIDOVEN + desc AVALIDOVEN + 4 + 4 + read-write + + + AVALIDOVVAL + desc AVALIDOVVAL + 5 + 5 + read-write + + + BVALIDOVEN + desc BVALIDOVEN + 6 + 6 + read-write + + + BVALIDOVVAL + desc BVALIDOVVAL + 7 + 7 + read-write + + + HSTNEGSCS + desc HSTNEGSCS + 8 + 8 + read-only + + + HNPREQ + desc HNPREQ + 9 + 9 + read-write + + + HSTSETHNPEN + desc HSTSETHNPEN + 10 + 10 + read-write + + + DEVHNPEN + desc DEVHNPEN + 11 + 11 + read-write + + + EHEN + desc EHEN + 12 + 12 + read-write + + + DBNCEFLTRBYPASS + desc DBNCEFLTRBYPASS + 15 + 15 + read-write + + + CONIDSTS + desc CONIDSTS + 16 + 16 + read-only + + + DBNCTIME + desc DBNCTIME + 17 + 17 + read-only + + + ASESVLD + desc ASESVLD + 18 + 18 + read-only + + + BSESVLD + desc BSESVLD + 19 + 19 + read-only + + + OTGVER + desc OTGVER + 20 + 20 + read-write + + + CURMOD + desc CURMOD + 21 + 21 + read-only + + + TESTMODE_CORR_EUSB2 + desc TESTMODE_CORR_EUSB2 + 31 + 31 + read-write + + + + + GOTGINT + desc GOTGINT + 0x4 + 32 + read-write + 0x0 + 0xE0304 + + + SESENDDET + desc SESENDDET + 2 + 2 + read-write + + + SESREQSUCSTSCHNG + desc SESREQSUCSTSCHNG + 8 + 8 + read-write + + + HSTNEGSUCSTSCHNG + desc HSTNEGSUCSTSCHNG + 9 + 9 + read-write + + + HSTNEGDET + desc HSTNEGDET + 17 + 17 + read-write + + + ADEVTOUTCHG + desc ADEVTOUTCHG + 18 + 18 + read-write + + + DBNCEDONE + desc DBNCEDONE + 19 + 19 + read-write + + + + + GAHBCFG + desc GAHBCFG + 0x8 + 32 + read-write + 0x0 + 0xE001BF + + + GLBLINTRMSK + desc GLBLINTRMSK + 0 + 0 + read-write + + + HBSTLEN + desc HBSTLEN + 4 + 1 + read-write + + + DMAEN + desc DMAEN + 5 + 5 + read-write + + + NPTXFEMPLVL + desc NPTXFEMPLVL + 7 + 7 + read-write + + + PTXFEMPLVL + desc PTXFEMPLVL + 8 + 8 + read-write + + + REMMEMSUPP + desc REMMEMSUPP + 21 + 21 + read-write + + + NOTIALLDMAWRIT + desc NOTIALLDMAWRIT + 22 + 22 + read-write + + + AHBSINGLE + desc AHBSINGLE + 23 + 23 + read-write + + + + + GUSBCFG + desc GUSBCFG + 0xC + 32 + read-write + 0x1410 + 0xF7FE3FFF + + + TOUTCAL + desc TOUTCAL + 2 + 0 + read-write + + + PHYIF + desc PHYIF + 3 + 3 + read-write + + + ULPI_UTMI_SEL + desc ULPI_UTMI_SEL + 4 + 4 + read-write + + + FSINTF + desc FSINTF + 5 + 5 + read-write + + + PHYSEL + desc PHYSEL + 6 + 6 + read-write + + + DDRSEL + desc DDRSEL + 7 + 7 + read-write + + + SRPCAP + desc SRPCAP + 8 + 8 + read-write + + + HNPCAP + desc HNPCAP + 9 + 9 + read-write + + + USBTRDTIM + desc USBTRDTIM + 13 + 10 + read-write + + + ULPIFSLS + desc ULPIFSLS + 17 + 17 + read-write + + + ULPIAUTORES + desc ULPIAUTORES + 18 + 18 + read-write + + + ULPICLKSUSM + desc ULPICLKSUSM + 19 + 19 + read-write + + + ULPIEXTVBUSDRV + desc ULPIEXTVBUSDRV + 20 + 20 + read-write + + + ULPIEXTVBUSINDICATOR + desc ULPIEXTVBUSINDICATOR + 21 + 21 + read-write + + + TERMSELDLPULSE + desc TERMSELDLPULSE + 22 + 22 + read-write + + + COMPLEMENT + desc COMPLEMENT + 23 + 23 + read-write + + + INDICATOR + desc INDICATOR + 24 + 24 + read-write + + + ULPI + desc ULPI + 25 + 25 + read-write + + + IC_USBCAP + desc IC_USBCAP + 26 + 26 + read-write + + + TXENDDELAY + desc TXENDDELAY + 28 + 28 + read-write + + + FORCEHSTMODE + desc FORCEHSTMODE + 29 + 29 + read-write + + + FORCEDEVMODE + desc FORCEDEVMODE + 30 + 30 + read-write + + + CORRUPTTXPKT + desc CORRUPTTXPKT + 31 + 31 + write-only + + + + + GRSTCTL + desc GRSTCTL + 0x10 + 32 + read-write + 0x80000000 + 0xC00007F7 + + + CSFTRST + desc CSFTRST + 0 + 0 + read-write + + + PIUFSSFTRST + desc PIUFSSFTRST + 1 + 1 + read-write + + + FRMCNTRRST + desc FRMCNTRRST + 2 + 2 + read-write + + + RXFFLSH + desc RXFFLSH + 4 + 4 + read-write + + + TXFFLSH + desc TXFFLSH + 5 + 5 + read-write + + + TXFNUM + desc TXFNUM + 10 + 6 + read-write + + + DMAREQ + desc DMAREQ + 30 + 30 + read-only + + + AHBIDLE + desc AHBIDLE + 31 + 31 + read-only + + + + + GINTSTS + desc GINTSTS + 0x14 + 32 + read-only + 0x14000020 + 0xFFFEFCFF + + + CURMOD + desc CURMOD + 0 + 0 + read-only + + + MODEMIS + desc MODEMIS + 1 + 1 + read-write + + + OTGINT + desc OTGINT + 2 + 2 + read-only + + + SOF + desc SOF + 3 + 3 + read-write + + + RXFLVL + desc RXFLVL + 4 + 4 + read-only + + + NPTXFEMP + desc NPTXFEMP + 5 + 5 + read-only + + + GINNAKEFF + desc GINNAKEFF + 6 + 6 + read-only + + + GOUTNAKEFF + desc GOUTNAKEFF + 7 + 7 + read-only + + + ERLYSUSP + desc ERLYSUSP + 10 + 10 + read-write + + + USBSUSP + desc USBSUSP + 11 + 11 + read-write + + + USBRST + desc USBRST + 12 + 12 + read-write + + + ENUMDONE + desc ENUMDONE + 13 + 13 + read-write + + + ISOOUTDROP + desc ISOOUTDROP + 14 + 14 + read-write + + + EOPF + desc EOPF + 15 + 15 + read-write + + + EPMIS + desc EPMIS + 17 + 17 + read-write + + + IEPINT + desc IEPINT + 18 + 18 + read-only + + + OEPINT + desc OEPINT + 19 + 19 + read-only + + + INCOMPISOIN + desc INCOMPISOIN + 20 + 20 + read-write + + + INCOMPLP + desc INCOMPLP + 21 + 21 + read-write + + + FETSUSP + desc FETSUSP + 22 + 22 + read-write + + + RESETDET + desc RESETDET + 23 + 23 + read-write + + + PRTINT + desc PRTINT + 24 + 24 + read-only + + + HCHINT + desc HCHINT + 25 + 25 + read-only + + + PTXFEMP + desc PTXFEMP + 26 + 26 + read-only + + + LPM_INT + desc LPM_INT + 27 + 27 + read-write + + + CONIDSTSCHNG + desc CONIDSTSCHNG + 28 + 28 + read-write + + + DISCONNINT + desc DISCONNINT + 29 + 29 + read-write + + + SESSREQINT + desc SESSREQINT + 30 + 30 + read-write + + + WKUPINT + desc WKUPINT + 31 + 31 + read-write + + + + + GINTMSK + desc GINTMSK + 0x18 + 32 + read-write + 0x0 + 0xFFEEFCFE + + + MODEMISMSK + desc MODEMISMSK + 1 + 1 + read-write + + + OTGINTMSK + desc OTGINTMSK + 2 + 2 + read-write + + + SOFMSK + desc SOFMSK + 3 + 3 + read-write + + + RXFLVLMSK + desc RXFLVLMSK + 4 + 4 + read-write + + + NPTXFEMPMSK + desc NPTXFEMPMSK + 5 + 5 + read-write + + + GINNAKEFFMSK + desc GINNAKEFFMSK + 6 + 6 + read-write + + + GOUTNAKEFFMSK + desc GOUTNAKEFFMSK + 7 + 7 + read-write + + + ERLYSUSPMSK + desc ERLYSUSPMSK + 10 + 10 + read-write + + + USBSUSPMSK + desc USBSUSPMSK + 11 + 11 + read-write + + + USBRSTMSK + desc USBRSTMSK + 12 + 12 + read-write + + + ENUMDONEMSK + desc ENUMDONEMSK + 13 + 13 + read-write + + + ISOOUTDROPMSK + desc ISOOUTDROPMSK + 14 + 14 + read-write + + + EOPFMSK + desc EOPFMSK + 15 + 15 + read-write + + + EPMISMSK + desc EPMISMSK + 17 + 17 + read-write + + + IEPINTMSK + desc IEPINTMSK + 18 + 18 + read-write + + + OEPINTMSK + desc OEPINTMSK + 19 + 19 + read-write + + + INCOMPLPMSK + desc INCOMPLPMSK + 21 + 21 + read-write + + + FETSUSPMSK + desc FETSUSPMSK + 22 + 22 + read-write + + + RESETDETMSK + desc RESETDETMSK + 23 + 23 + read-write + + + PRTINTMSK + desc PRTINTMSK + 24 + 24 + read-write + + + HCHINTMSK + desc HCHINTMSK + 25 + 25 + read-write + + + PTXFEMPMSK + desc PTXFEMPMSK + 26 + 26 + read-write + + + LPM_INTMSK + desc LPM_INTMSK + 27 + 27 + read-write + + + CONIDSTSCHNGMSK + desc CONIDSTSCHNGMSK + 28 + 28 + read-write + + + DISCONNINTMSK + desc DISCONNINTMSK + 29 + 29 + read-write + + + SESSREQINTMSK + desc SESSREQINTMSK + 30 + 30 + read-write + + + WKUPINTMSK + desc WKUPINTMSK + 31 + 31 + read-write + + + + + GRXSTSR + desc GRXSTSR + 0x1C + 32 + read-only + 0x0 + 0x1FFFFFF + + + CHNUM + desc CHNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + FN + desc FN + 24 + 21 + read-only + + + + + GRXSTSP + desc GRXSTSP + 0x20 + 32 + read-only + 0x0 + 0x1FFFFFF + + + CHNUM + desc CHNUM + 3 + 0 + read-only + + + BCNT + desc BCNT + 14 + 4 + read-only + + + DPID + desc DPID + 16 + 15 + read-only + + + PKTSTS + desc PKTSTS + 20 + 17 + read-only + + + FN + desc FN + 24 + 21 + read-only + + + + + GRXFSIZ + desc GRXFSIZ + 0x24 + 32 + read-write + 0x800 + 0xFFF + + + RXFDEP + desc RXFDEP + 11 + 0 + read-write + + + + + GNPTXFSIZ + desc GNPTXFSIZ + 0x28 + 32 + read-write + 0x8000800 + 0xFFF0FFF + + + NPTXFSTADDR + desc NPTXFSTADDR + 11 + 0 + read-write + + + NPTXFDEP + desc NPTXFDEP + 27 + 16 + read-write + + + + + GNPTXSTS + desc GNPTXSTS + 0x2C + 32 + read-only + 0x8000800 + 0x7FFFFFFF + + + NPTXFSPCAVAIL + desc NPTXFSPCAVAIL + 15 + 0 + read-only + + + NPTXQSPCAVAIL + desc NPTXQSPCAVAIL + 23 + 16 + read-only + + + NPTXQTOP + desc NPTXQTOP + 30 + 24 + read-only + + + + + GPVNDCTL + desc GPVNDCTL + 0x34 + 32 + read-write + 0x0 + 0xE7FFFFF + + + REGDATA + desc REGDATA + 7 + 0 + read-write + + + VCTRL + desc VCTRL + 15 + 8 + read-write + + + REGADDR + desc REGADDR + 21 + 16 + read-write + + + REGWR + desc REGWR + 22 + 22 + read-write + + + NEWREGREQ + desc NEWREGREQ + 25 + 25 + read-write + + + VSTSBSY + desc VSTSBSY + 26 + 26 + read-only + + + VSTSDONE + desc VSTSDONE + 27 + 27 + read-write + + + + + GUID + desc GUID + 0x3C + 32 + read-write + 0x12345678 + 0xFFFFFFFF + + + GLPMCFG + desc GLPMCFG + 0x54 + 32 + read-write + 0x0 + 0x3FFFFFFF + + + LPMCAP + desc LPMCAP + 0 + 0 + read-write + + + APPL1RES + desc APPL1RES + 1 + 1 + read-write + + + HIRD + desc HIRD + 5 + 2 + read-write + + + BREMOTEWAKE + desc BREMOTEWAKE + 6 + 6 + read-write + + + ENBLSLPM + desc ENBLSLPM + 7 + 7 + read-write + + + HIRD_THRES + desc HIRD_THRES + 12 + 8 + read-write + + + COREL1RES + desc COREL1RES + 14 + 13 + read-only + + + SLPSTS + desc SLPSTS + 15 + 15 + read-only + + + L1RESUMEOK + desc L1RESUMEOK + 16 + 16 + read-only + + + LPM_CHNL_INDX + desc LPM_CHNL_INDX + 20 + 17 + read-write + + + LPM_RETRY_CNT + desc LPM_RETRY_CNT + 23 + 21 + read-write + + + SNDLPM + desc SNDLPM + 24 + 24 + read-write + + + LPM_RETRYCNT_STS + desc LPM_RETRYCNT_STS + 27 + 25 + read-only + + + LPM_ENBESL + desc LPM_ENBESL + 28 + 28 + read-write + + + LPM_RESTORESLPSTS + desc LPM_RESTORESLPSTS + 29 + 29 + read-write + + + + + GDFIFOCFG + desc GDFIFOCFG + 0x5C + 32 + read-write + 0x7E00800 + 0xFFFFFFFF + + + GDFIFOCFG + desc GDFIFOCFG + 15 + 0 + read-write + + + EPINFOBASEADDR + desc EPINFOBASEADDR + 31 + 16 + read-write + + + + + HPTXFSIZ + desc HPTXFSIZ + 0x100 + 32 + read-write + 0x0 + 0xFFF1FFF + + + PTXFSTADDR + desc PTXFSTADDR + 12 + 0 + read-write + + + PTXFSIZE + desc PTXFSIZE + 27 + 16 + read-write + + + + + DIEPTXF1 + desc DIEPTXF1 + 0x104 + 32 + read-write + 0x8001000 + 0xFFF1FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 12 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF2 + desc DIEPTXF2 + 0x108 + 32 + read-write + 0x8001800 + 0xFFF1FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 12 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF3 + desc DIEPTXF3 + 0x10C + 32 + read-write + 0x8002000 + 0xFFF3FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 13 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF4 + desc DIEPTXF4 + 0x110 + 32 + read-write + 0x8002800 + 0xFFF3FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 13 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF5 + desc DIEPTXF5 + 0x114 + 32 + read-write + 0x8003000 + 0xFFF3FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 13 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF6 + desc DIEPTXF6 + 0x118 + 32 + read-write + 0x8003800 + 0xFFF3FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 13 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF7 + desc DIEPTXF7 + 0x11C + 32 + read-write + 0x8004000 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF8 + desc DIEPTXF8 + 0x120 + 32 + read-write + 0x8004800 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF9 + desc DIEPTXF9 + 0x124 + 32 + read-write + 0x8005000 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF10 + desc DIEPTXF10 + 0x128 + 32 + read-write + 0x8005800 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF11 + desc DIEPTXF11 + 0x12C + 32 + read-write + 0x8006000 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF12 + desc DIEPTXF12 + 0x130 + 32 + read-write + 0x8006800 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF13 + desc DIEPTXF13 + 0x134 + 32 + read-write + 0x8007000 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF14 + desc DIEPTXF14 + 0x138 + 32 + read-write + 0x8007800 + 0xFFF7FFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 14 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + DIEPTXF15 + desc DIEPTXF15 + 0x13C + 32 + read-write + 0x8008000 + 0xFFFFFFF + + + INEPNTXFSTADDR + desc INEPNTXFSTADDR + 15 + 0 + read-write + + + INEPNTXFDEP + desc INEPNTXFDEP + 27 + 16 + read-write + + + + + HCFG + desc HCFG + 0x400 + 32 + read-write + 0x220000 + 0x8000FF87 + + + FSLSPCLKSEL + desc FSLSPCLKSEL + 1 + 0 + read-write + + + FSLSSUPP + desc FSLSSUPP + 2 + 2 + read-write + + + ENA32KHZS + desc ENA32KHZS + 7 + 7 + read-write + + + RESVALID + desc RESVALID + 15 + 8 + read-write + + + MODECHTIMEN + desc MODECHTIMEN + 31 + 31 + read-write + + + + + HFIR + desc HFIR + 0x404 + 32 + read-write + 0x17D7 + 0x1FFFF + + + FRINT + desc FRINT + 15 + 0 + read-write + + + HFIRRLDCTRL + desc HFIRRLDCTRL + 16 + 16 + read-write + + + + + HFNUM + desc HFNUM + 0x408 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + FRNUM + desc FRNUM + 15 + 0 + read-only + + + FRREM + desc FRREM + 31 + 16 + read-only + + + + + HPTXSTS + desc HPTXSTS + 0x410 + 32 + read-only + 0x0 + 0xFFFFFFFF + + + PTXFSPCAVAIL + desc PTXFSPCAVAIL + 15 + 0 + read-only + + + PTXQSPCAVAIL + desc PTXQSPCAVAIL + 23 + 16 + read-only + + + PTXQTOP + desc PTXQTOP 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PRTSPD + 18 + 17 + read-only + + + + + HCCHAR0 + desc HCCHAR0 + 0x500 + 32 + read-write + 0x0 + 0xFFFEFFFF + + + MPS + desc MPS + 10 + 0 + read-write + + + EPNUM + desc EPNUM + 14 + 11 + read-write + + + EPDIR + desc EPDIR + 15 + 15 + read-write + + + LSPDDEV + desc LSPDDEV + 17 + 17 + read-write + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + EC + desc EC + 21 + 20 + read-write + + + DEVADDR + desc DEVADDR + 28 + 22 + read-write + + + ODDFRM + desc ODDFRM + 29 + 29 + read-write + + + CHDIS + desc CHDIS + 30 + 30 + read-write + + + CHENA + desc CHENA + 31 + 31 + read-write + + + + + HCSPLT0 + desc HCSPLT0 + 0x504 + 32 + read-write + 0x0 + 0x8001FFFF + + + PRTADDR + desc PRTADDR + 6 + 0 + read-write + + + HUBADDR + desc HUBADDR + 13 + 7 + read-write + + + XACTPOS + desc XACTPOS + 15 + 14 + read-write + + + COMPSPLT + desc COMPSPLT + 16 + 16 + read-write + + + SPLTENA + desc SPLTENA + 31 + 31 + read-write + + + + + HCINT0 + desc HCINT0 + 0x508 + 32 + read-write + 0x0 + 0x7FF + + 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PERSCHINTVL + desc PERSCHINTVL + 25 + 24 + read-write + + + RESVALID + desc RESVALID + 31 + 26 + read-write + + + + + DCTL + desc DCTL + 0x804 + 32 + read-write + 0x2 + 0xD8FFF + + + RMTWKUPSIG + desc RMTWKUPSIG + 0 + 0 + read-write + + + SFTDISCON + desc SFTDISCON + 1 + 1 + read-write + + + GNPINNAKSTS + desc GNPINNAKSTS + 2 + 2 + read-only + + + GOUTNAKSTS + desc GOUTNAKSTS + 3 + 3 + read-only + + + TSTCTL + desc TSTCTL + 6 + 4 + read-write + + + SGNPINNAK + desc SGNPINNAK + 7 + 7 + write-only + + + CGNPINNAK + desc CGNPINNAK + 8 + 8 + write-only + + + SGOUTNAK + desc SGOUTNAK + 9 + 9 + write-only + + + CGOUTNAK + desc CGOUTNAK + 10 + 10 + write-only + + + PWRONPRGDONE + desc PWRONPRGDONE + 11 + 11 + read-write + + + IGNRFRMNUM + desc IGNRFRMNUM + 15 + 15 + read-write + + + NAKONBBLE + desc NAKONBBLE + 16 + 16 + read-write + + + DEEPSLEEPBESLREJECT + desc DEEPSLEEPBESLREJECT + 18 + 18 + read-write + + + SERVINT + desc SERVINT + 19 + 19 + read-write + + + + + DSTS + desc DSTS + 0x808 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INEPINT6 + 6 + 6 + read-only + + + INEPINT7 + desc INEPINT7 + 7 + 7 + read-only + + + INEPINT8 + desc INEPINT8 + 8 + 8 + read-only + + + INEPINT9 + desc INEPINT9 + 9 + 9 + read-only + + + INEPINT10 + desc INEPINT10 + 10 + 10 + read-only + + + INEPINT11 + desc INEPINT11 + 11 + 11 + read-only + + + INEPINT12 + desc INEPINT12 + 12 + 12 + read-only + + + INEPINT13 + desc INEPINT13 + 13 + 13 + read-only + + + INEPINT14 + desc INEPINT14 + 14 + 14 + read-only + + + INEPINT15 + desc INEPINT15 + 15 + 15 + read-only + + + OUTEPINT0 + desc OUTEPINT0 + 16 + 16 + read-only + + + OUTEPINT1 + desc OUTEPINT1 + 17 + 17 + read-only + + + OUTEPINT2 + desc OUTEPINT2 + 18 + 18 + read-only + + + OUTEPINT3 + desc OUTEPINT3 + 19 + 19 + read-only + + + OUTEPINT4 + desc OUTEPINT4 + 20 + 20 + read-only + + + OUTEPINT5 + desc OUTEPINT5 + 21 + 21 + read-only + + + OUTEPINT6 + desc OUTEPINT6 + 22 + 22 + read-only + + + OUTEPINT7 + desc OUTEPINT7 + 23 + 23 + read-only + + + OUTEPINT8 + desc OUTEPINT8 + 24 + 24 + read-only + + + OUTEPINT9 + desc OUTEPINT9 + 25 + 25 + read-only + + + OUTEPINT10 + desc OUTEPINT10 + 26 + 26 + read-only + + + OUTEPINT11 + desc OUTEPINT11 + 27 + 27 + read-only + + + OUTEPINT12 + desc OUTEPINT12 + 28 + 28 + read-only + + + OUTEPINT13 + desc OUTEPINT13 + 29 + 29 + read-only + + + OUTEPINT14 + desc OUTEPINT14 + 30 + 30 + read-only + + + OUTEPINT15 + desc OUTEPINT15 + 31 + 31 + read-only + + + + + DAINTMSK + desc DAINTMSK + 0x81C + 32 + read-write + 0x0 + 0xFFFFFFFF + + + INEPMSK0 + desc INEPMSK0 + 0 + 0 + read-write + + + INEPMSK1 + desc INEPMSK1 + 1 + 1 + read-write + + + INEPMSK2 + desc INEPMSK2 + 2 + 2 + read-write + + + INEPMSK3 + desc INEPMSK3 + 3 + 3 + read-write + + + INEPMSK4 + desc INEPMSK4 + 4 + 4 + read-write + + + INEPMSK5 + desc INEPMSK5 + 5 + 5 + read-write + + + INEPMSK6 + desc INEPMSK6 + 6 + 6 + read-write + + + INEPMSK7 + desc INEPMSK7 + 7 + 7 + read-write + + + INEPMSK8 + desc INEPMSK8 + 8 + 8 + read-write + + + INEPMSK9 + desc INEPMSK9 + 9 + 9 + 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ECHINEPMSK14 + 14 + 14 + read-write + + + ECHINEPMSK15 + desc ECHINEPMSK15 + 15 + 15 + read-write + + + ECHOUTEPMSK0 + desc ECHOUTEPMSK0 + 16 + 16 + read-write + + + ECHOUTEPMSK1 + desc ECHOUTEPMSK1 + 17 + 17 + read-write + + + ECHOUTEPMSK2 + desc ECHOUTEPMSK2 + 18 + 18 + read-write + + + ECHOUTEPMSK3 + desc ECHOUTEPMSK3 + 19 + 19 + read-write + + + ECHOUTEPMSK4 + desc ECHOUTEPMSK4 + 20 + 20 + read-write + + + ECHOUTEPMSK5 + desc ECHOUTEPMSK5 + 21 + 21 + read-write + + + ECHOUTEPMSK6 + desc ECHOUTEPMSK6 + 22 + 22 + read-write + + + ECHOUTEPMSK7 + desc ECHOUTEPMSK7 + 23 + 23 + read-write + + + ECHOUTEPMSK8 + desc ECHOUTEPMSK8 + 24 + 24 + read-write + + + ECHOUTEPMSK9 + desc ECHOUTEPMSK9 + 25 + 25 + read-write + + + ECHOUTEPMSK10 + desc ECHOUTEPMSK10 + 26 + 26 + read-write + + + ECHOUTEPMSK11 + desc ECHOUTEPMSK11 + 27 + 27 + read-write + + + ECHOUTEPMSK12 + desc ECHOUTEPMSK12 + 28 + 28 + read-write + + + ECHOUTEPMSK13 + desc ECHOUTEPMSK13 + 29 + 29 + read-write + + + ECHOUTEPMSK14 + desc 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read-write + + + + + DIEPINT0 + desc DIEPINT0 + 0x908 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ0 + desc DIEPTSIZ0 + 0x910 + 32 + read-write + 0x0 + 0x18007F + + + XFERSIZE + desc XFERSIZE + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 20 + 19 + read-write + + + + + DIEPDMA0 + desc DIEPDMA0 + 0x914 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS0 + desc DTXFSTS0 + 0x918 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL1 + desc DIEPCTL1 + 0x920 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT1 + desc DIEPINT1 + 0x928 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ1 + desc DIEPTSIZ1 + 0x930 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA1 + desc DIEPDMA1 + 0x934 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS1 + desc DTXFSTS1 + 0x938 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL2 + desc DIEPCTL2 + 0x940 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT2 + desc DIEPINT2 + 0x948 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ2 + desc DIEPTSIZ2 + 0x950 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA2 + desc DIEPDMA2 + 0x954 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS2 + desc DTXFSTS2 + 0x958 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL3 + desc DIEPCTL3 + 0x960 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT3 + desc DIEPINT3 + 0x968 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ3 + desc DIEPTSIZ3 + 0x970 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA3 + desc DIEPDMA3 + 0x974 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS3 + desc DTXFSTS3 + 0x978 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL4 + desc DIEPCTL4 + 0x980 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT4 + desc DIEPINT4 + 0x988 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ4 + desc DIEPTSIZ4 + 0x990 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA4 + desc DIEPDMA4 + 0x994 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS4 + desc DTXFSTS4 + 0x998 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL5 + desc DIEPCTL5 + 0x9A0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT5 + desc DIEPINT5 + 0x9A8 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ5 + desc DIEPTSIZ5 + 0x9B0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA5 + desc DIEPDMA5 + 0x9B4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS5 + desc DTXFSTS5 + 0x9B8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL6 + desc DIEPCTL6 + 0x9C0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT6 + desc DIEPINT6 + 0x9C8 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ6 + desc DIEPTSIZ6 + 0x9D0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA6 + desc DIEPDMA6 + 0x9D4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS6 + desc DTXFSTS6 + 0x9D8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL7 + desc DIEPCTL7 + 0x9E0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT7 + desc DIEPINT7 + 0x9E8 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ7 + desc DIEPTSIZ7 + 0x9F0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA7 + desc DIEPDMA7 + 0x9F4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS7 + desc DTXFSTS7 + 0x9F8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL8 + desc DIEPCTL8 + 0xA00 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT8 + desc DIEPINT8 + 0xA08 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ8 + desc DIEPTSIZ8 + 0xA10 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA8 + desc DIEPDMA8 + 0xA14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS8 + desc DTXFSTS8 + 0xA18 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL9 + desc DIEPCTL9 + 0xA20 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT9 + desc DIEPINT9 + 0xA28 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ9 + desc DIEPTSIZ9 + 0xA30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA9 + desc DIEPDMA9 + 0xA34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS9 + desc DTXFSTS9 + 0xA38 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL10 + desc DIEPCTL10 + 0xA40 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT10 + desc DIEPINT10 + 0xA48 + 32 + read-write + 0x80 + 0x7BFF + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + TIMEOUT + desc TIMEOUT + 3 + 3 + read-write + + + INTKNTXFEMP + desc INTKNTXFEMP + 4 + 4 + read-write + + + INTKNEPMIS + desc INTKNEPMIS + 5 + 5 + read-write + + + INEPNAKEFF + desc INEPNAKEFF + 6 + 6 + read-write + + + TXFEMP + desc TXFEMP + 7 + 7 + read-only + + + TXFIFOUNDRN + desc TXFIFOUNDRN + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + + + DIEPTSIZ10 + desc DIEPTSIZ10 + 0xA50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + MC + desc MC + 30 + 29 + read-write + + + + + DIEPDMA10 + desc DIEPDMA10 + 0xA54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS10 + desc DTXFSTS10 + 0xA58 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL11 + desc DIEPCTL11 + 0xA60 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT11 + desc DIEPINT11 + 0xA68 + 32 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read-write + + + + + DIEPDMA11 + desc DIEPDMA11 + 0xA74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS11 + desc DTXFSTS11 + 0xA78 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL12 + desc DIEPCTL12 + 0xA80 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT12 + desc DIEPINT12 + 0xA88 + 32 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read-write + + + + + DIEPDMA12 + desc DIEPDMA12 + 0xA94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS12 + desc DTXFSTS12 + 0xA98 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL13 + desc DIEPCTL13 + 0xAA0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT13 + desc DIEPINT13 + 0xAA8 + 32 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read-write + + + + + DIEPDMA13 + desc DIEPDMA13 + 0xAB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS13 + desc DTXFSTS13 + 0xAB8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL14 + desc DIEPCTL14 + 0xAC0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT14 + desc DIEPINT14 + 0xAC8 + 32 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read-write + + + + + DIEPDMA14 + desc DIEPDMA14 + 0xAD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS14 + desc DTXFSTS14 + 0xAD8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DIEPCTL15 + desc DIEPCTL15 + 0xAE0 + 32 + read-write + 0x0 + 0xFFEF87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + TXFNUM + desc TXFNUM + 25 + 22 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DIEPINT15 + desc DIEPINT15 + 0xAE8 + 32 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read-write + + + + + DIEPDMA15 + desc DIEPDMA15 + 0xAF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DTXFSTS15 + desc DTXFSTS15 + 0xAF8 + 32 + read-only + 0x800 + 0xFFFF + + + INEPTXFSPCAVAIL + desc INEPTXFSPCAVAIL + 15 + 0 + read-only + + + + + DOEPCTL0 + desc DOEPCTL0 + 0xB00 + 32 + read-only + 0x8000 + 0xCC3E8003 + + + MPS + desc MPS + 1 + 0 + read-only + + + USBACTEP + desc USBACTEP + 15 + 15 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-only + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-only + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT0 + desc DOEPINT0 + 0xB08 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ0 + desc DOEPTSIZ0 + 0xB10 + 32 + read-write + 0x0 + 0x6008007F + + + XFERSIZE + desc XFERSIZE + 6 + 0 + read-write + + + PKTCNT + desc PKTCNT + 19 + 19 + read-write + + + SUPCNT + desc SUPCNT + 30 + 29 + read-write + + + + + DOEPDMA0 + desc DOEPDMA0 + 0xB14 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL1 + desc DOEPCTL1 + 0xB20 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT1 + desc DOEPINT1 + 0xB28 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ1 + desc DOEPTSIZ1 + 0xB30 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA1 + desc DOEPDMA1 + 0xB34 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL2 + desc DOEPCTL2 + 0xB40 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID 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8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ2 + desc DOEPTSIZ2 + 0xB50 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA2 + desc DOEPDMA2 + 0xB54 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL3 + desc DOEPCTL3 + 0xB60 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc 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SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT4 + desc DOEPINT4 + 0xB88 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 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0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA5 + desc DOEPDMA5 + 0xBB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL6 + desc DOEPCTL6 + 0xBC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT6 + desc DOEPINT6 + 0xBC8 + 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+ NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ11 + desc DOEPTSIZ11 + 0xC70 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA11 + desc DOEPDMA11 + 0xC74 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL12 + desc DOEPCTL12 + 0xC80 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT12 + desc DOEPINT12 + 0xC88 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ12 + desc DOEPTSIZ12 + 0xC90 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA12 + desc DOEPDMA12 + 0xC94 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL13 + desc DOEPCTL13 + 0xCA0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT13 + desc DOEPINT13 + 0xCA8 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ13 + desc DOEPTSIZ13 + 0xCB0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA13 + desc DOEPDMA13 + 0xCB4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL14 + desc DOEPCTL14 + 0xCC0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT14 + desc DOEPINT14 + 0xCC8 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ14 + desc DOEPTSIZ14 + 0xCD0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA14 + desc DOEPDMA14 + 0xCD4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + DOEPCTL15 + desc DOEPCTL15 + 0xCE0 + 32 + read-write + 0x0 + 0xFC3F87FF + + + MPS + desc MPS + 10 + 0 + read-write + + + USBACTEP + desc USBACTEP + 15 + 15 + read-write + + + DPID + desc DPID + 16 + 16 + read-only + + + NAKSTS + desc NAKSTS + 17 + 17 + read-only + + + EPTYPE + desc EPTYPE + 19 + 18 + read-write + + + SNP + desc SNP + 20 + 20 + read-write + + + STALL + desc STALL + 21 + 21 + read-write + + + CNAK + desc CNAK + 26 + 26 + write-only + + + SNAK + desc SNAK + 27 + 27 + write-only + + + SETD0PID + desc SETD0PID + 28 + 28 + write-only + + + SETD1PID + desc SETD1PID + 29 + 29 + write-only + + + EPDIS + desc EPDIS + 30 + 30 + read-write + + + EPENA + desc EPENA + 31 + 31 + read-write + + + + + DOEPINT15 + desc DOEPINT15 + 0xCE8 + 32 + read-write + 0x0 + 0xFB7F + + + XFERCOMPL + desc XFERCOMPL + 0 + 0 + read-write + + + EPDISBLD + desc EPDISBLD + 1 + 1 + read-write + + + AHBERR + desc AHBERR + 2 + 2 + read-write + + + SETUP + desc SETUP + 3 + 3 + read-write + + + OUTTKNEPDIS + desc OUTTKNEPDIS + 4 + 4 + read-write + + + STSPHSERCVD + desc STSPHSERCVD + 5 + 5 + read-write + + + BACK2BACKSETUP + desc BACK2BACKSETUP + 6 + 6 + read-write + + + OUTPKTERR + desc OUTPKTERR + 8 + 8 + read-write + + + BNAINTR + desc BNAINTR + 9 + 9 + read-write + + + PKTDRPSTS + desc PKTDRPSTS + 11 + 11 + read-write + + + BBLEERR + desc BBLEERR + 12 + 12 + read-write + + + NAKINTRPT + desc NAKINTRPT + 13 + 13 + read-write + + + NYETINTRPT + desc NYETINTRPT + 14 + 14 + read-write + + + STUPPKTRCVD + desc STUPPKTRCVD + 15 + 15 + read-write + + + + + DOEPTSIZ15 + desc DOEPTSIZ15 + 0xCF0 + 32 + read-write + 0x0 + 0x7FFFFFFF + + + XFERSIZE + desc XFERSIZE + 18 + 0 + read-write + + + PKTCNT + desc PKTCNT + 28 + 19 + read-write + + + RXDPID + desc RXDPID + 30 + 29 + read-only + + + + + DOEPDMA15 + desc DOEPDMA15 + 0xCF4 + 32 + read-write + 0x0 + 0xFFFFFFFF + + + PCGCCTL + desc PCGCCTL + 0xE00 + 32 + read-write + 0x0 + 0x1EF + + + STOPPCLK + desc STOPPCLK + 0 + 0 + read-write + + + GATEHCLK + desc GATEHCLK + 1 + 1 + read-write + + + PWRCLMP + desc PWRCLMP + 2 + 2 + read-write + + + RSTPDWNMODULE + desc RSTPDWNMODULE + 3 + 3 + read-write + + + ENBL_L1GATING + desc ENBL_L1GATING + 5 + 5 + read-write + + + PHYSLEEP + desc PHYSLEEP + 6 + 6 + read-only + + + L1SUSPENDED + desc L1SUSPENDED + 7 + 7 + read-only + + + RESETAFTERSUSP + desc RESETAFTERSUSP + 8 + 8 + read-write + + + + + + + WDT + desc WDT + 0x40049000 + + 0x0 + 0xC + + + + CR + desc CR + 0x0 + 32 + read-write + 0x80010FF3 + 0x80010FF3 + + + PERI + desc PERI + 1 + 0 + read-write + + + CKS + desc CKS + 7 + 4 + read-write + + + WDPT + desc WDPT + 11 + 8 + read-write + + + SLPOFF + desc SLPOFF + 16 + 16 + read-write + + + ITS + desc ITS + 31 + 31 + read-write + + + + + SR + desc SR + 0x4 + 32 + read-only + 0x0 + 0x3FFFF + + + CNT + desc CNT + 15 + 0 + read-only + + + UDF + desc UDF + 16 + 16 + read-write + + + REF + desc REF + 17 + 17 + read-write + + + + + RR + desc RR + 0x8 + 32 + read-only + 0x0 + 0xFFFF + + + RF + desc RF + 15 + 0 + read-only + + + + + + + diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/IAR/startup_hc32f4a0.s b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/IAR/startup_hc32f4a0.s new file mode 100644 index 0000000000000000000000000000000000000000..a9ed8f4bd3f3e98b24c5a8876448f33e2802dbe5 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/IAR/startup_hc32f4a0.s @@ -0,0 +1,1039 @@ +;******************************************************************************* +; Copyright (C) 2016, Huada Semiconductor Co.,Ltd All rights reserved. +; +; This software is owned and published by: +; Huada Semiconductor Co.,Ltd ("HDSC"). +; +; BY DOWNLOADING, INSTALLING OR USING THIS SOFTWARE, YOU AGREE TO BE BOUND +; BY ALL THE TERMS AND CONDITIONS OF THIS AGREEMENT. +; +; This software contains source code for use with HDSC +; components. This software is licensed by HDSC to be adapted only +; for use in systems utilizing HDSC components. HDSC shall not be +; responsible for misuse or illegal use of this software for devices not +; supported herein. HDSC is providing this software "AS IS" and will +; not be responsible for issues arising from incorrect user implementation +; of the software. +; +; Disclaimer: +; HDSC MAKES NO WARRANTY, EXPRESS OR IMPLIED, ARISING BY LAW OR OTHERWISE, +; REGARDING THE SOFTWARE (INCLUDING ANY ACCOMPANYING WRITTEN MATERIALS), +; ITS PERFORMANCE OR SUITABILITY FOR YOUR INTENDED USE, INCLUDING, +; WITHOUT LIMITATION, THE IMPLIED WARRANTY OF MERCHANTABILITY, THE IMPLIED +; WARRANTY OF FITNESS FOR A PARTICULAR PURPOSE OR USE, AND THE IMPLIED +; WARRANTY OF NONINFRINGEMENT. +; HDSC SHALL HAVE NO LIABILITY (WHETHER IN CONTRACT, WARRANTY, TORT, +; NEGLIGENCE OR OTHERWISE) FOR ANY DAMAGES WHATSOEVER (INCLUDING, WITHOUT +; LIMITATION, DAMAGES FOR LOSS OF BUSINESS PROFITS, BUSINESS INTERRUPTION, +; LOSS OF BUSINESS INFORMATION, OR OTHER PECUNIARY LOSS) ARISING FROM USE OR +; INABILITY TO USE THE SOFTWARE, INCLUDING, WITHOUT LIMITATION, ANY DIRECT, +; INDIRECT, INCIDENTAL, SPECIAL OR CONSEQUENTIAL DAMAGES OR LOSS OF DATA, +; SAVINGS OR PROFITS, +; EVEN IF Disclaimer HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +; YOU ASSUME ALL RESPONSIBILITIES FOR SELECTION OF THE SOFTWARE TO ACHIEVE YOUR +; INTENDED RESULTS, AND FOR THE INSTALLATION OF, USE OF, AND RESULTS OBTAINED +; FROM, THE SOFTWARE. +; +; This software may be replicated in part or whole for the licensed use, +; with the restriction that this Disclaimer and Copyright notice must be +; included with each copy of this software, whether used in part or whole, +; at all times. +;/ +;/*****************************************************************************/ +;/* Startup for IAR */ +;/* Version V1.0 */ +;/* Date 2020-06-12 */ +;/* Target-mcu HC32F4A0 */ +;/*****************************************************************************/ + + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + SECTION .intvec:CODE:NOROOT(8) + DATA +__vector_table + DCD sfe(CSTACK) ; Top of Stack + DCD Reset_Handler ; Reset + DCD NMI_Handler ; NMI + DCD HardFault_Handler ; Hard Fault + DCD MemManage_Handler ; MemManage Fault + DCD BusFault_Handler ; Bus Fault + DCD UsageFault_Handler ; Usage Fault + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall + DCD DebugMon_Handler ; Debug Monitor + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV + DCD SysTick_Handler ; SysTick + +; Numbered IRQ handler vectors + +; Note: renaming to device dependent ISR function names are done in +; ddl.h (section "IRQ name definition for all type MCUs") + DCD IRQ000_Handler + DCD IRQ001_Handler + DCD IRQ002_Handler + DCD IRQ003_Handler + DCD IRQ004_Handler + DCD IRQ005_Handler + DCD IRQ006_Handler + DCD IRQ007_Handler + DCD IRQ008_Handler + DCD IRQ009_Handler + DCD IRQ010_Handler + DCD IRQ011_Handler + DCD IRQ012_Handler + DCD IRQ013_Handler + DCD IRQ014_Handler + DCD IRQ015_Handler + DCD IRQ016_Handler + DCD IRQ017_Handler + DCD IRQ018_Handler + DCD IRQ019_Handler + DCD IRQ020_Handler + DCD IRQ021_Handler + DCD IRQ022_Handler + DCD IRQ023_Handler + DCD IRQ024_Handler + DCD IRQ025_Handler + DCD IRQ026_Handler + DCD IRQ027_Handler + DCD IRQ028_Handler + DCD IRQ029_Handler + DCD IRQ030_Handler + DCD IRQ031_Handler + DCD IRQ032_Handler + DCD IRQ033_Handler + DCD IRQ034_Handler + DCD IRQ035_Handler + DCD IRQ036_Handler + DCD IRQ037_Handler + DCD IRQ038_Handler + DCD IRQ039_Handler + DCD IRQ040_Handler + DCD IRQ041_Handler + DCD IRQ042_Handler + DCD IRQ043_Handler + DCD IRQ044_Handler + DCD IRQ045_Handler + DCD IRQ046_Handler + DCD IRQ047_Handler + DCD IRQ048_Handler + DCD IRQ049_Handler + DCD IRQ050_Handler + DCD IRQ051_Handler + DCD IRQ052_Handler + DCD IRQ053_Handler + DCD IRQ054_Handler + DCD IRQ055_Handler + DCD IRQ056_Handler + DCD IRQ057_Handler + DCD IRQ058_Handler + DCD IRQ059_Handler + DCD IRQ060_Handler + DCD IRQ061_Handler + DCD IRQ062_Handler + DCD IRQ063_Handler + DCD IRQ064_Handler + DCD IRQ065_Handler + DCD IRQ066_Handler + DCD IRQ067_Handler + DCD IRQ068_Handler + DCD IRQ069_Handler + DCD IRQ070_Handler + DCD IRQ071_Handler + DCD IRQ072_Handler + DCD IRQ073_Handler + DCD IRQ074_Handler + DCD IRQ075_Handler + DCD IRQ076_Handler + DCD IRQ077_Handler + DCD IRQ078_Handler + DCD IRQ079_Handler + DCD IRQ080_Handler + DCD IRQ081_Handler + DCD IRQ082_Handler + DCD IRQ083_Handler + DCD IRQ084_Handler + DCD IRQ085_Handler + DCD IRQ086_Handler + DCD IRQ087_Handler + DCD IRQ088_Handler + DCD IRQ089_Handler + DCD IRQ090_Handler + DCD IRQ091_Handler + DCD IRQ092_Handler + DCD IRQ093_Handler + DCD IRQ094_Handler + DCD IRQ095_Handler + DCD IRQ096_Handler + DCD IRQ097_Handler + DCD IRQ098_Handler + DCD IRQ099_Handler + DCD IRQ100_Handler + DCD IRQ101_Handler + DCD IRQ102_Handler + DCD IRQ103_Handler + DCD IRQ104_Handler + DCD IRQ105_Handler + DCD IRQ106_Handler + DCD IRQ107_Handler + DCD IRQ108_Handler + DCD IRQ109_Handler + DCD IRQ110_Handler + DCD IRQ111_Handler + DCD IRQ112_Handler + DCD IRQ113_Handler + DCD IRQ114_Handler + DCD IRQ115_Handler + DCD IRQ116_Handler + DCD IRQ117_Handler + DCD IRQ118_Handler + DCD IRQ119_Handler + DCD IRQ120_Handler + DCD IRQ121_Handler + DCD IRQ122_Handler + DCD IRQ123_Handler + DCD IRQ124_Handler + DCD IRQ125_Handler + DCD IRQ126_Handler + DCD IRQ127_Handler + DCD IRQ128_Handler + DCD IRQ129_Handler + DCD IRQ130_Handler + DCD IRQ131_Handler + DCD IRQ132_Handler + DCD IRQ133_Handler + DCD IRQ134_Handler + DCD IRQ135_Handler + DCD IRQ136_Handler + DCD IRQ137_Handler + DCD IRQ138_Handler + DCD IRQ139_Handler + DCD IRQ140_Handler + DCD IRQ141_Handler + DCD IRQ142_Handler + DCD IRQ143_Handler + + THUMB +; Dummy Exception Handlers (infinite loops which can be modified) + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(4) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + + + PUBWEAK IRQ000_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ000_Handler + B IRQ000_Handler + + + PUBWEAK IRQ001_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ001_Handler + B IRQ001_Handler + + + PUBWEAK IRQ002_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ002_Handler + B IRQ002_Handler + + + PUBWEAK IRQ003_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ003_Handler + B IRQ003_Handler + + + PUBWEAK IRQ004_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ004_Handler + B IRQ004_Handler + + + PUBWEAK IRQ005_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ005_Handler + B IRQ005_Handler + + + PUBWEAK IRQ006_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ006_Handler + B IRQ006_Handler + + + PUBWEAK IRQ007_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ007_Handler + B IRQ007_Handler + + + PUBWEAK IRQ008_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ008_Handler + B IRQ008_Handler + + + PUBWEAK IRQ009_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ009_Handler + B IRQ009_Handler + + + PUBWEAK IRQ010_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ010_Handler + B IRQ010_Handler + + + PUBWEAK IRQ011_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ011_Handler + B IRQ011_Handler + + + PUBWEAK IRQ012_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ012_Handler + B IRQ012_Handler + + + PUBWEAK IRQ013_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ013_Handler + B IRQ013_Handler + + + PUBWEAK IRQ014_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ014_Handler + B IRQ014_Handler + + + PUBWEAK IRQ015_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ015_Handler + B IRQ015_Handler + + + PUBWEAK IRQ016_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ016_Handler + B IRQ016_Handler + + + PUBWEAK IRQ017_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ017_Handler + B IRQ017_Handler + + + PUBWEAK IRQ018_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ018_Handler + B IRQ018_Handler + + + PUBWEAK IRQ019_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ019_Handler + B IRQ019_Handler + + + PUBWEAK IRQ020_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ020_Handler + B IRQ020_Handler + + + PUBWEAK IRQ021_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ021_Handler + B IRQ021_Handler + + + PUBWEAK IRQ022_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ022_Handler + B IRQ022_Handler + + + PUBWEAK IRQ023_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ023_Handler + B IRQ023_Handler + + + PUBWEAK IRQ024_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ024_Handler + B IRQ024_Handler + + + PUBWEAK IRQ025_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ025_Handler + B IRQ025_Handler + + + PUBWEAK IRQ026_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ026_Handler + B IRQ026_Handler + + + PUBWEAK IRQ027_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ027_Handler + B IRQ027_Handler + + + PUBWEAK IRQ028_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ028_Handler + B IRQ028_Handler + + + PUBWEAK IRQ029_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ029_Handler + B IRQ029_Handler + + + PUBWEAK IRQ030_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ030_Handler + B IRQ030_Handler + + + PUBWEAK IRQ031_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ031_Handler + B IRQ031_Handler + + PUBWEAK IRQ032_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ032_Handler + B IRQ032_Handler + + PUBWEAK IRQ033_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ033_Handler + B IRQ033_Handler + + PUBWEAK IRQ034_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ034_Handler + B IRQ034_Handler + + PUBWEAK IRQ035_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ035_Handler + B IRQ035_Handler + + PUBWEAK IRQ036_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ036_Handler + B IRQ036_Handler + + PUBWEAK IRQ037_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ037_Handler + B IRQ037_Handler + + PUBWEAK IRQ038_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ038_Handler + B IRQ038_Handler + + PUBWEAK IRQ039_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ039_Handler + B IRQ039_Handler + + PUBWEAK IRQ040_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ040_Handler + B IRQ040_Handler + + PUBWEAK IRQ041_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ041_Handler + B IRQ041_Handler + + PUBWEAK IRQ042_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ042_Handler + B IRQ042_Handler + + PUBWEAK IRQ043_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ043_Handler + B IRQ043_Handler + + PUBWEAK IRQ044_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ044_Handler + B IRQ044_Handler + + PUBWEAK IRQ045_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ045_Handler + B IRQ045_Handler + + PUBWEAK IRQ046_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ046_Handler + B IRQ046_Handler + + PUBWEAK IRQ047_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ047_Handler + B IRQ047_Handler + + PUBWEAK IRQ048_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ048_Handler + B IRQ048_Handler + + PUBWEAK IRQ049_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ049_Handler + B IRQ049_Handler + + PUBWEAK IRQ050_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ050_Handler + B IRQ050_Handler + + PUBWEAK IRQ051_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ051_Handler + B IRQ051_Handler + + PUBWEAK IRQ052_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ052_Handler + B IRQ052_Handler + + PUBWEAK IRQ053_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ053_Handler + B IRQ053_Handler + + PUBWEAK IRQ054_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ054_Handler + B IRQ054_Handler + + PUBWEAK IRQ055_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ055_Handler + B IRQ055_Handler + + PUBWEAK IRQ056_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ056_Handler + B IRQ056_Handler + + PUBWEAK IRQ057_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ057_Handler + B IRQ057_Handler + + PUBWEAK IRQ058_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ058_Handler + B IRQ058_Handler + + PUBWEAK IRQ059_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ059_Handler + B IRQ059_Handler + + PUBWEAK IRQ060_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ060_Handler + B IRQ060_Handler + + PUBWEAK IRQ061_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ061_Handler + B IRQ061_Handler + + PUBWEAK IRQ062_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ062_Handler + B IRQ062_Handler + + PUBWEAK IRQ063_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ063_Handler + B IRQ063_Handler + + PUBWEAK IRQ064_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ064_Handler + B IRQ064_Handler + + PUBWEAK IRQ065_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ065_Handler + B IRQ065_Handler + + PUBWEAK IRQ066_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ066_Handler + B IRQ066_Handler + + PUBWEAK IRQ067_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ067_Handler + B IRQ067_Handler + + PUBWEAK IRQ068_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ068_Handler + B IRQ068_Handler + + PUBWEAK IRQ069_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ069_Handler + B IRQ069_Handler + + PUBWEAK IRQ070_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ070_Handler + B IRQ070_Handler + + PUBWEAK IRQ071_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ071_Handler + B IRQ071_Handler + + PUBWEAK IRQ072_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ072_Handler + B IRQ072_Handler + + PUBWEAK IRQ073_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ073_Handler + B IRQ073_Handler + + PUBWEAK IRQ074_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ074_Handler + B IRQ074_Handler + + PUBWEAK IRQ075_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ075_Handler + B IRQ075_Handler + + PUBWEAK IRQ076_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ076_Handler + B IRQ076_Handler + + PUBWEAK IRQ077_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ077_Handler + B IRQ077_Handler + + PUBWEAK IRQ078_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ078_Handler + B IRQ078_Handler + + PUBWEAK IRQ079_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ079_Handler + B IRQ079_Handler + + PUBWEAK IRQ080_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ080_Handler + B IRQ080_Handler + + PUBWEAK IRQ081_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ081_Handler + B IRQ081_Handler + + PUBWEAK IRQ082_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ082_Handler + B IRQ082_Handler + + PUBWEAK IRQ083_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ083_Handler + B IRQ083_Handler + + PUBWEAK IRQ084_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ084_Handler + B IRQ084_Handler + + PUBWEAK IRQ085_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ085_Handler + B IRQ085_Handler + + PUBWEAK IRQ086_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ086_Handler + B IRQ086_Handler + + PUBWEAK IRQ087_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ087_Handler + B IRQ087_Handler + + PUBWEAK IRQ088_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ088_Handler + B IRQ088_Handler + + PUBWEAK IRQ089_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ089_Handler + B IRQ089_Handler + + PUBWEAK IRQ090_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ090_Handler + B IRQ090_Handler + + PUBWEAK IRQ091_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ091_Handler + B IRQ091_Handler + + PUBWEAK IRQ092_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ092_Handler + B IRQ092_Handler + + PUBWEAK IRQ093_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ093_Handler + B IRQ093_Handler + + PUBWEAK IRQ094_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ094_Handler + B IRQ094_Handler + + PUBWEAK IRQ095_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ095_Handler + B IRQ095_Handler + + PUBWEAK IRQ096_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ096_Handler + B IRQ096_Handler + + PUBWEAK IRQ097_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ097_Handler + B IRQ097_Handler + + PUBWEAK IRQ098_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ098_Handler + B IRQ098_Handler + + PUBWEAK IRQ099_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ099_Handler + B IRQ099_Handler + + PUBWEAK IRQ100_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ100_Handler + B IRQ100_Handler + + PUBWEAK IRQ101_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ101_Handler + B IRQ101_Handler + + PUBWEAK IRQ102_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ102_Handler + B IRQ102_Handler + + PUBWEAK IRQ103_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ103_Handler + B IRQ103_Handler + + PUBWEAK IRQ104_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ104_Handler + B IRQ104_Handler + + PUBWEAK IRQ105_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ105_Handler + B IRQ105_Handler + + PUBWEAK IRQ106_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ106_Handler + B IRQ106_Handler + + PUBWEAK IRQ107_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ107_Handler + B IRQ107_Handler + + PUBWEAK IRQ108_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ108_Handler + B IRQ108_Handler + + PUBWEAK IRQ109_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ109_Handler + B IRQ109_Handler + + PUBWEAK IRQ110_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ110_Handler + B IRQ110_Handler + + PUBWEAK IRQ111_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ111_Handler + B IRQ111_Handler + + PUBWEAK IRQ112_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ112_Handler + B IRQ112_Handler + + PUBWEAK IRQ113_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ113_Handler + B IRQ113_Handler + + PUBWEAK IRQ114_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ114_Handler + B IRQ114_Handler + + PUBWEAK IRQ115_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ115_Handler + B IRQ115_Handler + + PUBWEAK IRQ116_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ116_Handler + B IRQ116_Handler + + PUBWEAK IRQ117_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ117_Handler + B IRQ117_Handler + + PUBWEAK IRQ118_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ118_Handler + B IRQ118_Handler + + PUBWEAK IRQ119_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ119_Handler + B IRQ119_Handler + + PUBWEAK IRQ120_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ120_Handler + B IRQ120_Handler + + PUBWEAK IRQ121_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ121_Handler + B IRQ121_Handler + + PUBWEAK IRQ122_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ122_Handler + B IRQ122_Handler + + PUBWEAK IRQ123_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ123_Handler + B IRQ123_Handler + + PUBWEAK IRQ124_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ124_Handler + B IRQ124_Handler + + PUBWEAK IRQ125_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ125_Handler + B IRQ125_Handler + + PUBWEAK IRQ126_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ126_Handler + B IRQ126_Handler + + PUBWEAK IRQ127_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ127_Handler + B IRQ127_Handler + + PUBWEAK IRQ128_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ128_Handler + B IRQ128_Handler + + PUBWEAK IRQ129_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ129_Handler + B IRQ129_Handler + + PUBWEAK IRQ130_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ130_Handler + B IRQ130_Handler + + PUBWEAK IRQ131_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ131_Handler + B IRQ131_Handler + + PUBWEAK IRQ132_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ132_Handler + B IRQ132_Handler + + PUBWEAK IRQ133_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ133_Handler + B IRQ133_Handler + + PUBWEAK IRQ134_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ134_Handler + B IRQ134_Handler + + PUBWEAK IRQ135_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ135_Handler + B IRQ135_Handler + + PUBWEAK IRQ136_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ136_Handler + B IRQ136_Handler + + PUBWEAK IRQ137_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ137_Handler + B IRQ137_Handler + + PUBWEAK IRQ138_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ138_Handler + B IRQ138_Handler + + PUBWEAK IRQ139_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ139_Handler + B IRQ139_Handler + + PUBWEAK IRQ140_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ140_Handler + B IRQ140_Handler + + PUBWEAK IRQ141_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ141_Handler + B IRQ141_Handler + + PUBWEAK IRQ142_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ142_Handler + B IRQ142_Handler + + PUBWEAK IRQ143_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +IRQ143_Handler + B IRQ143_Handler + + END diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/system_hc32f4a0.c b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/system_hc32f4a0.c new file mode 100644 index 0000000000000000000000000000000000000000..8ca8da5816aadd12bd011154d59ef03f984b6654 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Device/HDSC/HC32F4A0/Source/system_hc32f4a0.c @@ -0,0 +1,168 @@ +/** + ******************************************************************************* + * @file system_hc32f4a0.c + * @brief This file provides two functions and one global variable to be called + * from user application + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-07-03 Zhangxl Modify for 16MHz & 20MHz HRC + 2020-09-10 Zhangxl Simplify the declare + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" + +/** + * @addtogroup CMSIS + * @{ + */ + +/** + * @addtogroup HC32F4A0_System + * @{ + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Variable + * @{ + */ + +/*!< System clock frequency (Core clock) */ +__NO_INIT uint32_t SystemCoreClock; +/*!< High speed RC frequency (HCR clock) */ +__NO_INIT uint32_t HRC_VALUE; + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @addtogroup HC32F4A0_System_Global_Functions + * @{ + */ + +/** + * @brief Setup the microcontroller system. Initialize the System and update + * the SystemCoreClock variable. + * @param None + * @retval None + */ +void SystemInit(void) +{ + (*((volatile unsigned short*)(0x400543FEUL)))=0xA50BU; + (*((volatile unsigned int*)(0x4004CCE8UL)))=0x00040000UL; + (*((volatile unsigned short*)(0x400543FEUL)))=0xA500U; + /* FPU settings */ +#if (__FPU_PRESENT == 1) && (__FPU_USED == 1) + SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */ +#endif + SystemCoreClockUpdate(); +} + +/** + * @brief Update SystemCoreClock variable according to Clock Register Values. + * @param None + * @retval None + */ +void SystemCoreClockUpdate(void) +{ + uint8_t tmp; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + + /* Select proper HRC_VALUE according to ICG1.HRCFREQSEL bit */ + /* ICG1.HRCFREQSEL = '0' represent HRC_VALUE = 20000000UL */ + /* ICG1.HRCFREQSEL = '1' represent HRC_VALUE = 16000000UL */ + if (1UL == (HRC_FREQ_MON() & 1UL)) + { + HRC_VALUE = HRC_16MHz_VALUE; + } + else + { + HRC_VALUE = HRC_20MHz_VALUE; + } + + tmp = M4_CMU->CKSWR & CMU_CKSWR_CKSW; + switch(tmp) + { + case 0x00U: /* use internal high speed RC */ + SystemCoreClock = HRC_VALUE; + break; + case 0x01U: /* use internal middle speed RC */ + SystemCoreClock = MRC_VALUE; + break; + case 0x02U: /* use internal low speed RC */ + SystemCoreClock = LRC_VALUE; + break; + case 0x03U: /* use external high speed OSC */ + SystemCoreClock = XTAL_VALUE; + break; + case 0x04U: /* use external low speed OSC */ + SystemCoreClock = XTAL32_VALUE; + break; + case 0x05U: /* use PLLH */ + /* PLLCLK = ((pllsrc / pllm) * plln) / pllp */ + pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL); + plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL); + pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL); + + /* use external high speed OSC as PLL source */ + if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC) + { + SystemCoreClock = (XTAL_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + } + /* use internal high RC as PLL source */ + else + { + SystemCoreClock = (HRC_VALUE) / (pllm + 1UL) * (plln + 1UL) / (pllp + 1UL); + } + break; + default: + break; + } +} + +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armcc.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armcc.h new file mode 100644 index 0000000000000000000000000000000000000000..59f173ac71b996c8615e3c1804963c8b4c311cde --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armcc.h @@ -0,0 +1,894 @@ +/**************************************************************************//** + * @file cmsis_armcc.h + * @brief CMSIS compiler ARMCC (Arm Compiler 5) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_ARMCC_H +#define __CMSIS_ARMCC_H + + +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 400677) + #error "Please use Arm Compiler Toolchain V4.0.677 or later!" +#endif + +/* CMSIS compiler control architecture macros */ +#if ((defined (__TARGET_ARCH_6_M ) && (__TARGET_ARCH_6_M == 1)) || \ + (defined (__TARGET_ARCH_6S_M ) && (__TARGET_ARCH_6S_M == 1)) ) + #define __ARM_ARCH_6M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7_M ) && (__TARGET_ARCH_7_M == 1)) + #define __ARM_ARCH_7M__ 1 +#endif + +#if (defined (__TARGET_ARCH_7E_M) && (__TARGET_ARCH_7E_M == 1)) + #define __ARM_ARCH_7EM__ 1 +#endif + + /* __ARM_ARCH_8M_BASE__ not applicable */ + /* __ARM_ARCH_8M_MAIN__ not applicable */ + +/* CMSIS compiler control DSP macros */ +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __ARM_FEATURE_DSP 1 +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE static __forceinline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __declspec(noreturn) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed)) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT __packed struct +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION __packed union +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #define __UNALIGNED_UINT32(x) (*((__packed uint32_t *)(x))) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #define __UNALIGNED_UINT16_WRITE(addr, val) ((*((__packed uint16_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #define __UNALIGNED_UINT16_READ(addr) (*((const __packed uint16_t *)(addr))) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #define __UNALIGNED_UINT32_WRITE(addr, val) ((*((__packed uint32_t *)(addr))) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #define __UNALIGNED_UINT32_READ(addr) (*((const __packed uint32_t *)(addr))) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __memory_changed() +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); */ + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_INLINE uint32_t __get_CONTROL(void) +{ + register uint32_t __regControl __ASM("control"); + return(__regControl); +} + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_INLINE void __set_CONTROL(uint32_t control) +{ + register uint32_t __regControl __ASM("control"); + __regControl = control; +} + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_INLINE uint32_t __get_IPSR(void) +{ + register uint32_t __regIPSR __ASM("ipsr"); + return(__regIPSR); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_INLINE uint32_t __get_APSR(void) +{ + register uint32_t __regAPSR __ASM("apsr"); + return(__regAPSR); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_INLINE uint32_t __get_xPSR(void) +{ + register uint32_t __regXPSR __ASM("xpsr"); + return(__regXPSR); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_INLINE uint32_t __get_PSP(void) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + return(__regProcessStackPointer); +} + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_INLINE void __set_PSP(uint32_t topOfProcStack) +{ + register uint32_t __regProcessStackPointer __ASM("psp"); + __regProcessStackPointer = topOfProcStack; +} + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_INLINE uint32_t __get_MSP(void) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + return(__regMainStackPointer); +} + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_INLINE void __set_MSP(uint32_t topOfMainStack) +{ + register uint32_t __regMainStackPointer __ASM("msp"); + __regMainStackPointer = topOfMainStack; +} + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_INLINE uint32_t __get_PRIMASK(void) +{ + register uint32_t __regPriMask __ASM("primask"); + return(__regPriMask); +} + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_INLINE void __set_PRIMASK(uint32_t priMask) +{ + register uint32_t __regPriMask __ASM("primask"); + __regPriMask = (priMask); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_INLINE uint32_t __get_BASEPRI(void) +{ + register uint32_t __regBasePri __ASM("basepri"); + return(__regBasePri); +} + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI(uint32_t basePri) +{ + register uint32_t __regBasePri __ASM("basepri"); + __regBasePri = (basePri & 0xFFU); +} + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + register uint32_t __regBasePriMax __ASM("basepri_max"); + __regBasePriMax = (basePri & 0xFFU); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_INLINE uint32_t __get_FAULTMASK(void) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + return(__regFaultMask); +} + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask) +{ + register uint32_t __regFaultMask __ASM("faultmask"); + __regFaultMask = (faultMask & (uint32_t)1U); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_INLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + return(__regfpscr); +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_INLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + register uint32_t __regfpscr __ASM("fpscr"); + __regfpscr = (fpscr); +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __nop + + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() do {\ + __schedule_barrier();\ + __isb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() do {\ + __schedule_barrier();\ + __dsb(0xF);\ + __schedule_barrier();\ + } while (0U) + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() do {\ + __schedule_barrier();\ + __dmb(0xF);\ + __schedule_barrier();\ + } while (0U) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV __rev + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value) +{ + rev16 r0, r0 + bx lr +} +#endif + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int16_t __REVSH(int16_t value) +{ + revsh r0, r0 + bx lr +} +#endif + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +#define __ROR __ror + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __breakpoint(value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + #define __RBIT __rbit +#else +__attribute__((always_inline)) __STATIC_INLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ + return result; +} +#endif + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +#define __CLZ __clz + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr)) +#else + #define __LDREXB(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint8_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr)) +#else + #define __LDREXH(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint16_t) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr)) +#else + #define __LDREXW(ptr) _Pragma("push") _Pragma("diag_suppress 3731") ((uint32_t ) __ldrex(ptr)) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXB(value, ptr) __strex(value, ptr) +#else + #define __STREXB(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXH(value, ptr) __strex(value, ptr) +#else + #define __STREXH(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#if defined(__ARMCC_VERSION) && (__ARMCC_VERSION < 5060020) + #define __STREXW(value, ptr) __strex(value, ptr) +#else + #define __STREXW(value, ptr) _Pragma("push") _Pragma("diag_suppress 3731") __strex(value, ptr) _Pragma("pop") +#endif + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __clrex + + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +#ifndef __NO_EMBEDDED_ASM +__attribute__((section(".rrx_text"))) __STATIC_INLINE __ASM uint32_t __RRX(uint32_t value) +{ + rrx r0, r0 + bx lr +} +#endif + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDRBT(ptr) ((uint8_t ) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDRHT(ptr) ((uint16_t) __ldrt(ptr)) + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDRT(ptr) ((uint32_t ) __ldrt(ptr)) + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRBT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRHT(value, ptr) __strt(value, ptr) + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +#define __STRT(value, ptr) __strt(value, ptr) + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__attribute__((always_inline)) __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) + +#define __SADD8 __sadd8 +#define __QADD8 __qadd8 +#define __SHADD8 __shadd8 +#define __UADD8 __uadd8 +#define __UQADD8 __uqadd8 +#define __UHADD8 __uhadd8 +#define __SSUB8 __ssub8 +#define __QSUB8 __qsub8 +#define __SHSUB8 __shsub8 +#define __USUB8 __usub8 +#define __UQSUB8 __uqsub8 +#define __UHSUB8 __uhsub8 +#define __SADD16 __sadd16 +#define __QADD16 __qadd16 +#define __SHADD16 __shadd16 +#define __UADD16 __uadd16 +#define __UQADD16 __uqadd16 +#define __UHADD16 __uhadd16 +#define __SSUB16 __ssub16 +#define __QSUB16 __qsub16 +#define __SHSUB16 __shsub16 +#define __USUB16 __usub16 +#define __UQSUB16 __uqsub16 +#define __UHSUB16 __uhsub16 +#define __SASX __sasx +#define __QASX __qasx +#define __SHASX __shasx +#define __UASX __uasx +#define __UQASX __uqasx +#define __UHASX __uhasx +#define __SSAX __ssax +#define __QSAX __qsax +#define __SHSAX __shsax +#define __USAX __usax +#define __UQSAX __uqsax +#define __UHSAX __uhsax +#define __USAD8 __usad8 +#define __USADA8 __usada8 +#define __SSAT16 __ssat16 +#define __USAT16 __usat16 +#define __UXTB16 __uxtb16 +#define __UXTAB16 __uxtab16 +#define __SXTB16 __sxtb16 +#define __SXTAB16 __sxtab16 +#define __SMUAD __smuad +#define __SMUADX __smuadx +#define __SMLAD __smlad +#define __SMLADX __smladx +#define __SMLALD __smlald +#define __SMLALDX __smlaldx +#define __SMUSD __smusd +#define __SMUSDX __smusdx +#define __SMLSD __smlsd +#define __SMLSDX __smlsdx +#define __SMLSLD __smlsld +#define __SMLSLDX __smlsldx +#define __SEL __sel +#define __QADD __qadd +#define __QSUB __qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +#define __SMMLA(ARG1,ARG2,ARG3) ( (int32_t)((((int64_t)(ARG1) * (ARG2)) + \ + ((int64_t)(ARG3) << 32U) ) >> 32U)) + +#endif /* ((defined (__ARM_ARCH_7EM__) && (__ARM_ARCH_7EM__ == 1)) ) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCC_H */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armclang.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armclang.h new file mode 100644 index 0000000000000000000000000000000000000000..e917f357a328c66909aac8cefea5891211481e3e --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armclang.h @@ -0,0 +1,1444 @@ +/**************************************************************************//** + * @file cmsis_armclang.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +#define __SADD8 __builtin_arm_sadd8 +#define __QADD8 __builtin_arm_qadd8 +#define __SHADD8 __builtin_arm_shadd8 +#define __UADD8 __builtin_arm_uadd8 +#define __UQADD8 __builtin_arm_uqadd8 +#define __UHADD8 __builtin_arm_uhadd8 +#define __SSUB8 __builtin_arm_ssub8 +#define __QSUB8 __builtin_arm_qsub8 +#define __SHSUB8 __builtin_arm_shsub8 +#define __USUB8 __builtin_arm_usub8 +#define __UQSUB8 __builtin_arm_uqsub8 +#define __UHSUB8 __builtin_arm_uhsub8 +#define __SADD16 __builtin_arm_sadd16 +#define __QADD16 __builtin_arm_qadd16 +#define __SHADD16 __builtin_arm_shadd16 +#define __UADD16 __builtin_arm_uadd16 +#define __UQADD16 __builtin_arm_uqadd16 +#define __UHADD16 __builtin_arm_uhadd16 +#define __SSUB16 __builtin_arm_ssub16 +#define __QSUB16 __builtin_arm_qsub16 +#define __SHSUB16 __builtin_arm_shsub16 +#define __USUB16 __builtin_arm_usub16 +#define __UQSUB16 __builtin_arm_uqsub16 +#define __UHSUB16 __builtin_arm_uhsub16 +#define __SASX __builtin_arm_sasx +#define __QASX __builtin_arm_qasx +#define __SHASX __builtin_arm_shasx +#define __UASX __builtin_arm_uasx +#define __UQASX __builtin_arm_uqasx +#define __UHASX __builtin_arm_uhasx +#define __SSAX __builtin_arm_ssax +#define __QSAX __builtin_arm_qsax +#define __SHSAX __builtin_arm_shsax +#define __USAX __builtin_arm_usax +#define __UQSAX __builtin_arm_uqsax +#define __UHSAX __builtin_arm_uhsax +#define __USAD8 __builtin_arm_usad8 +#define __USADA8 __builtin_arm_usada8 +#define __SSAT16 __builtin_arm_ssat16 +#define __USAT16 __builtin_arm_usat16 +#define __UXTB16 __builtin_arm_uxtb16 +#define __UXTAB16 __builtin_arm_uxtab16 +#define __SXTB16 __builtin_arm_sxtb16 +#define __SXTAB16 __builtin_arm_sxtab16 +#define __SMUAD __builtin_arm_smuad +#define __SMUADX __builtin_arm_smuadx +#define __SMLAD __builtin_arm_smlad +#define __SMLADX __builtin_arm_smladx +#define __SMLALD __builtin_arm_smlald +#define __SMLALDX __builtin_arm_smlaldx +#define __SMUSD __builtin_arm_smusd +#define __SMUSDX __builtin_arm_smusdx +#define __SMLSD __builtin_arm_smlsd +#define __SMLSDX __builtin_arm_smlsdx +#define __SMLSLD __builtin_arm_smlsld +#define __SMLSLDX __builtin_arm_smlsldx +#define __SEL __builtin_arm_sel +#define __QADD __builtin_arm_qadd +#define __QSUB __builtin_arm_qsub + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armclang_ltm.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armclang_ltm.h new file mode 100644 index 0000000000000000000000000000000000000000..feec32405974c068e9baf77f6b1dcbf070755fec --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_armclang_ltm.h @@ -0,0 +1,1891 @@ +/**************************************************************************//** + * @file cmsis_armclang_ltm.h + * @brief CMSIS compiler armclang (Arm Compiler 6) header file + * @version V1.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +/*lint -esym(9058, IRQn)*/ /* disable MISRA 2012 Rule 2.4 for IRQn */ + +#ifndef __CMSIS_ARMCLANG_H +#define __CMSIS_ARMCLANG_H + +#pragma clang system_header /* treat file as system include file */ + +#ifndef __ARM_COMPAT_H +#include /* Compatibility header for Arm Compiler 5 intrinsics */ +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE __inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static __inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static __inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32 */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_WRITE */ + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT16_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT16_READ */ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_WRITE)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_WRITE */ + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma clang diagnostic push + #pragma clang diagnostic ignored "-Wpacked" +/*lint -esym(9058, T_UINT32_READ)*/ /* disable MISRA 2012 Rule 2.4 for T_UINT32_READ */ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma clang diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START +#define __PROGRAM_START __main +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP Image$$ARM_LIB_STACK$$ZI$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT Image$$ARM_LIB_STACK$$ZI$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section("RESET"))) +#endif + + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __enable_irq(); see arm_compat.h */ + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +/* intrinsic void __disable_irq(); see arm_compat.h */ + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __enable_fault_irq __enable_fiq /* see arm_compat.h */ + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +#define __disable_fault_irq __disable_fiq /* see arm_compat.h */ + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __get_FPSCR (uint32_t)__builtin_arm_get_fpscr +#else +#define __get_FPSCR() ((uint32_t)0U) +#endif + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#define __set_FPSCR __builtin_arm_set_fpscr +#else +#define __set_FPSCR(x) ((void)(x)) +#endif + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP __builtin_arm_nop + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI __builtin_arm_wfi + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE __builtin_arm_wfe + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV __builtin_arm_sev + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +#define __ISB() __builtin_arm_isb(0xF) + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +#define __DSB() __builtin_arm_dsb(0xF) + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +#define __DMB() __builtin_arm_dmb(0xF) + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV(value) __builtin_bswap32(value) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REV16(value) __ROR(__REV(value), 16) + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +#define __REVSH(value) (int16_t)__builtin_bswap16(value) + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +#define __RBIT __builtin_arm_rbit + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM Compiler 6.10 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDREXB (uint8_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDREXH (uint16_t)__builtin_arm_ldrex + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDREXW (uint32_t)__builtin_arm_ldrex + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXB (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXH (uint32_t)__builtin_arm_strex + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STREXW (uint32_t)__builtin_arm_strex + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +#define __CLREX __builtin_arm_clrex + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT __builtin_arm_ssat + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT __builtin_arm_usat + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +#define __LDAEXB (uint8_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +#define __LDAEXH (uint16_t)__builtin_arm_ldaex + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +#define __LDAEX (uint32_t)__builtin_arm_ldaex + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXB (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEXH (uint32_t)__builtin_arm_stlex + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +#define __STLEX (uint32_t)__builtin_arm_stlex + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#endif /* __CMSIS_ARMCLANG_H */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_compiler.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_compiler.h new file mode 100644 index 0000000000000000000000000000000000000000..adbf296f15a47a93e5058abddad6742bb4b9854d --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_compiler.h @@ -0,0 +1,283 @@ +/**************************************************************************//** + * @file cmsis_compiler.h + * @brief CMSIS compiler generic header file + * @version V5.1.0 + * @date 09. October 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_COMPILER_H +#define __CMSIS_COMPILER_H + +#include + +/* + * Arm Compiler 4/5 + */ +#if defined ( __CC_ARM ) + #include "cmsis_armcc.h" + + +/* + * Arm Compiler 6.6 LTM (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) && (__ARMCC_VERSION < 6100100) + #include "cmsis_armclang_ltm.h" + + /* + * Arm Compiler above 6.10.1 (armclang) + */ +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6100100) + #include "cmsis_armclang.h" + + +/* + * GNU Compiler + */ +#elif defined ( __GNUC__ ) + #include "cmsis_gcc.h" + + +/* + * IAR Compiler + */ +#elif defined ( __ICCARM__ ) + #include + + +/* + * TI Arm Compiler + */ +#elif defined ( __TI_ARM__ ) + #include + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __attribute__((packed)) + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed)) + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed)) + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void*)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) + #endif + #ifndef __RESTRICT + #define __RESTRICT __restrict + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * TASKING Compiler + */ +#elif defined ( __TASKING__ ) + /* + * The CMSIS functions have been implemented as intrinsics in the compiler. + * Please use "carm -?i" to get an up to date list of all intrinsics, + * Including the CMSIS ones. + */ + + #ifndef __ASM + #define __ASM __asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + #define __NO_RETURN __attribute__((noreturn)) + #endif + #ifndef __USED + #define __USED __attribute__((used)) + #endif + #ifndef __WEAK + #define __WEAK __attribute__((weak)) + #endif + #ifndef __PACKED + #define __PACKED __packed__ + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __packed__ + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION union __packed__ + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + struct __packed__ T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #define __ALIGNED(x) __align(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +/* + * COSMIC Compiler + */ +#elif defined ( __CSMC__ ) + #include + + #ifndef __ASM + #define __ASM _asm + #endif + #ifndef __INLINE + #define __INLINE inline + #endif + #ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline + #endif + #ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __STATIC_INLINE + #endif + #ifndef __NO_RETURN + // NO RETURN is automatically detected hence no warning here + #define __NO_RETURN + #endif + #ifndef __USED + #warning No compiler specific solution for __USED. __USED is ignored. + #define __USED + #endif + #ifndef __WEAK + #define __WEAK __weak + #endif + #ifndef __PACKED + #define __PACKED @packed + #endif + #ifndef __PACKED_STRUCT + #define __PACKED_STRUCT @packed struct + #endif + #ifndef __PACKED_UNION + #define __PACKED_UNION @packed union + #endif + #ifndef __UNALIGNED_UINT32 /* deprecated */ + @packed struct T_UINT32 { uint32_t v; }; + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) + #endif + #ifndef __UNALIGNED_UINT16_WRITE + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT16_READ + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) + #endif + #ifndef __UNALIGNED_UINT32_WRITE + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) + #endif + #ifndef __UNALIGNED_UINT32_READ + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) + #endif + #ifndef __ALIGNED + #warning No compiler specific solution for __ALIGNED. __ALIGNED is ignored. + #define __ALIGNED(x) + #endif + #ifndef __RESTRICT + #warning No compiler specific solution for __RESTRICT. __RESTRICT is ignored. + #define __RESTRICT + #endif + #ifndef __COMPILER_BARRIER + #warning No compiler specific solution for __COMPILER_BARRIER. __COMPILER_BARRIER is ignored. + #define __COMPILER_BARRIER() (void)0 + #endif + + +#else + #error Unknown compiler. +#endif + + +#endif /* __CMSIS_COMPILER_H */ + diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_gcc.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_gcc.h new file mode 100644 index 0000000000000000000000000000000000000000..3ddcc58b69f6a8d60f614df45fb98932b07ac9c2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_gcc.h @@ -0,0 +1,2168 @@ +/**************************************************************************//** + * @file cmsis_gcc.h + * @brief CMSIS compiler GCC header file + * @version V5.2.0 + * @date 08. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#ifndef __CMSIS_GCC_H +#define __CMSIS_GCC_H + +/* ignore some GCC warnings */ +#pragma GCC diagnostic push +#pragma GCC diagnostic ignored "-Wsign-conversion" +#pragma GCC diagnostic ignored "-Wconversion" +#pragma GCC diagnostic ignored "-Wunused-parameter" + +/* Fallback for __has_builtin */ +#ifndef __has_builtin + #define __has_builtin(x) (0) +#endif + +/* CMSIS compiler specific defines */ +#ifndef __ASM + #define __ASM __asm +#endif +#ifndef __INLINE + #define __INLINE inline +#endif +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __attribute__((always_inline)) static inline +#endif +#ifndef __NO_RETURN + #define __NO_RETURN __attribute__((__noreturn__)) +#endif +#ifndef __USED + #define __USED __attribute__((used)) +#endif +#ifndef __WEAK + #define __WEAK __attribute__((weak)) +#endif +#ifndef __PACKED + #define __PACKED __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_STRUCT + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) +#endif +#ifndef __PACKED_UNION + #define __PACKED_UNION union __attribute__((packed, aligned(1))) +#endif +#ifndef __UNALIGNED_UINT32 /* deprecated */ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + struct __attribute__((packed)) T_UINT32 { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32(x) (((struct T_UINT32 *)(x))->v) +#endif +#ifndef __UNALIGNED_UINT16_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_WRITE { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_WRITE(addr, val) (void)((((struct T_UINT16_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT16_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT16_READ { uint16_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT16_READ(addr) (((const struct T_UINT16_READ *)(const void *)(addr))->v) +#endif +#ifndef __UNALIGNED_UINT32_WRITE + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_WRITE { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_WRITE(addr, val) (void)((((struct T_UINT32_WRITE *)(void *)(addr))->v) = (val)) +#endif +#ifndef __UNALIGNED_UINT32_READ + #pragma GCC diagnostic push + #pragma GCC diagnostic ignored "-Wpacked" + #pragma GCC diagnostic ignored "-Wattributes" + __PACKED_STRUCT T_UINT32_READ { uint32_t v; }; + #pragma GCC diagnostic pop + #define __UNALIGNED_UINT32_READ(addr) (((const struct T_UINT32_READ *)(const void *)(addr))->v) +#endif +#ifndef __ALIGNED + #define __ALIGNED(x) __attribute__((aligned(x))) +#endif +#ifndef __RESTRICT + #define __RESTRICT __restrict +#endif +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +/* ######################### Startup and Lowlevel Init ######################## */ + +#ifndef __PROGRAM_START + +/** + \brief Initializes data and bss sections + \details This default implementations initialized all data and additional bss + sections relying on .copy.table and .zero.table specified properly + in the used linker script. + + */ +__STATIC_FORCEINLINE __NO_RETURN void __cmsis_start(void) +{ + extern void _start(void) __NO_RETURN; + + typedef struct { + uint32_t const* src; + uint32_t* dest; + uint32_t wlen; + } __copy_table_t; + + typedef struct { + uint32_t* dest; + uint32_t wlen; + } __zero_table_t; + + extern const __copy_table_t __copy_table_start__; + extern const __copy_table_t __copy_table_end__; + extern const __zero_table_t __zero_table_start__; + extern const __zero_table_t __zero_table_end__; + + for (__copy_table_t const* pTable = &__copy_table_start__; pTable < &__copy_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = pTable->src[i]; + } + } + + for (__zero_table_t const* pTable = &__zero_table_start__; pTable < &__zero_table_end__; ++pTable) { + for(uint32_t i=0u; iwlen; ++i) { + pTable->dest[i] = 0u; + } + } + + _start(); +} + +#define __PROGRAM_START __cmsis_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP __StackTop +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT __StackLimit +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __Vectors +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE __attribute((used, section(".vectors"))) +#endif + +/* ########################### Core Function Access ########################### */ +/** \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions + @{ + */ + +/** + \brief Enable IRQ Interrupts + \details Enables IRQ interrupts by clearing the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_irq(void) +{ + __ASM volatile ("cpsie i" : : : "memory"); +} + + +/** + \brief Disable IRQ Interrupts + \details Disables IRQ interrupts by setting the I-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_irq(void) +{ + __ASM volatile ("cpsid i" : : : "memory"); +} + + +/** + \brief Get Control Register + \details Returns the content of the Control Register. + \return Control Register value + */ +__STATIC_FORCEINLINE uint32_t __get_CONTROL(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Control Register (non-secure) + \details Returns the content of the non-secure Control Register when in secure mode. + \return non-secure Control Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_CONTROL_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, control_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Control Register + \details Writes the given value to the Control Register. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __set_CONTROL(uint32_t control) +{ + __ASM volatile ("MSR control, %0" : : "r" (control) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Control Register (non-secure) + \details Writes the given value to the non-secure Control Register when in secure state. + \param [in] control Control Register value to set + */ +__STATIC_FORCEINLINE void __TZ_set_CONTROL_NS(uint32_t control) +{ + __ASM volatile ("MSR control_ns, %0" : : "r" (control) : "memory"); +} +#endif + + +/** + \brief Get IPSR Register + \details Returns the content of the IPSR Register. + \return IPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_IPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, ipsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get APSR Register + \details Returns the content of the APSR Register. + \return APSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_APSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, apsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get xPSR Register + \details Returns the content of the xPSR Register. + \return xPSR Register value + */ +__STATIC_FORCEINLINE uint32_t __get_xPSR(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, xpsr" : "=r" (result) ); + return(result); +} + + +/** + \brief Get Process Stack Pointer + \details Returns the current value of the Process Stack Pointer (PSP). + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer (non-secure) + \details Returns the current value of the non-secure Process Stack Pointer (PSP) when in secure state. + \return PSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, psp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Process Stack Pointer + \details Assigns the given value to the Process Stack Pointer (PSP). + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_PSP(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp, %0" : : "r" (topOfProcStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Process Stack Pointer (PSP) when in secure state. + \param [in] topOfProcStack Process Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSP_NS(uint32_t topOfProcStack) +{ + __ASM volatile ("MSR psp_ns, %0" : : "r" (topOfProcStack) : ); +} +#endif + + +/** + \brief Get Main Stack Pointer + \details Returns the current value of the Main Stack Pointer (MSP). + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSP(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer (non-secure) + \details Returns the current value of the non-secure Main Stack Pointer (MSP) when in secure state. + \return MSP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, msp_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Main Stack Pointer + \details Assigns the given value to the Main Stack Pointer (MSP). + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __set_MSP(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp, %0" : : "r" (topOfMainStack) : ); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Main Stack Pointer (MSP) when in secure state. + \param [in] topOfMainStack Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSP_NS(uint32_t topOfMainStack) +{ + __ASM volatile ("MSR msp_ns, %0" : : "r" (topOfMainStack) : ); +} +#endif + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Stack Pointer (non-secure) + \details Returns the current value of the non-secure Stack Pointer (SP) when in secure state. + \return SP Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_SP_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, sp_ns" : "=r" (result) ); + return(result); +} + + +/** + \brief Set Stack Pointer (non-secure) + \details Assigns the given value to the non-secure Stack Pointer (SP) when in secure state. + \param [in] topOfStack Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_SP_NS(uint32_t topOfStack) +{ + __ASM volatile ("MSR sp_ns, %0" : : "r" (topOfStack) : ); +} +#endif + + +/** + \brief Get Priority Mask + \details Returns the current state of the priority mask bit from the Priority Mask Register. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __get_PRIMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask" : "=r" (result) :: "memory"); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Priority Mask (non-secure) + \details Returns the current state of the non-secure priority mask bit from the Priority Mask Register when in secure state. + \return Priority Mask value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PRIMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, primask_ns" : "=r" (result) :: "memory"); + return(result); +} +#endif + + +/** + \brief Set Priority Mask + \details Assigns the given value to the Priority Mask Register. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __set_PRIMASK(uint32_t priMask) +{ + __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Priority Mask (non-secure) + \details Assigns the given value to the non-secure Priority Mask Register when in secure state. + \param [in] priMask Priority Mask + */ +__STATIC_FORCEINLINE void __TZ_set_PRIMASK_NS(uint32_t priMask) +{ + __ASM volatile ("MSR primask_ns, %0" : : "r" (priMask) : "memory"); +} +#endif + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Enable FIQ + \details Enables FIQ interrupts by clearing the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __enable_fault_irq(void) +{ + __ASM volatile ("cpsie f" : : : "memory"); +} + + +/** + \brief Disable FIQ + \details Disables FIQ interrupts by setting the F-bit in the CPSR. + Can only be executed in Privileged modes. + */ +__STATIC_FORCEINLINE void __disable_fault_irq(void) +{ + __ASM volatile ("cpsid f" : : : "memory"); +} + + +/** + \brief Get Base Priority + \details Returns the current value of the Base Priority register. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __get_BASEPRI(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Base Priority (non-secure) + \details Returns the current value of the non-secure Base Priority register when in secure state. + \return Base Priority register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_BASEPRI_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, basepri_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Base Priority + \details Assigns the given value to the Base Priority register. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI(uint32_t basePri) +{ + __ASM volatile ("MSR basepri, %0" : : "r" (basePri) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Base Priority (non-secure) + \details Assigns the given value to the non-secure Base Priority register when in secure state. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __TZ_set_BASEPRI_NS(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_ns, %0" : : "r" (basePri) : "memory"); +} +#endif + + +/** + \brief Set Base Priority with condition + \details Assigns the given value to the Base Priority register only if BASEPRI masking is disabled, + or the new value increases the BASEPRI priority level. + \param [in] basePri Base Priority value to set + */ +__STATIC_FORCEINLINE void __set_BASEPRI_MAX(uint32_t basePri) +{ + __ASM volatile ("MSR basepri_max, %0" : : "r" (basePri) : "memory"); +} + + +/** + \brief Get Fault Mask + \details Returns the current value of the Fault Mask register. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __get_FAULTMASK(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask" : "=r" (result) ); + return(result); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Fault Mask (non-secure) + \details Returns the current value of the non-secure Fault Mask register when in secure state. + \return Fault Mask register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_FAULTMASK_NS(void) +{ + uint32_t result; + + __ASM volatile ("MRS %0, faultmask_ns" : "=r" (result) ); + return(result); +} +#endif + + +/** + \brief Set Fault Mask + \details Assigns the given value to the Fault Mask register. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __set_FAULTMASK(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory"); +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Fault Mask (non-secure) + \details Assigns the given value to the non-secure Fault Mask register when in secure state. + \param [in] faultMask Fault Mask value to set + */ +__STATIC_FORCEINLINE void __TZ_set_FAULTMASK_NS(uint32_t faultMask) +{ + __ASM volatile ("MSR faultmask_ns, %0" : : "r" (faultMask) : "memory"); +} +#endif + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + +/** + \brief Get Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Process Stack Pointer Limit (PSPLIM). + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_PSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim" : "=r" (result) ); + return result; +#endif +} + +#if (defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Process Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \return PSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_PSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, psplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Process Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Process Stack Pointer Limit (PSPLIM). + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_PSPLIM(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim, %0" : : "r" (ProcStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Process Stack Pointer (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Process Stack Pointer Limit (PSPLIM) when in secure state. + \param [in] ProcStackPtrLimit Process Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __TZ_set_PSPLIM_NS(uint32_t ProcStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)ProcStackPtrLimit; +#else + __ASM volatile ("MSR psplim_ns, %0\n" : : "r" (ProcStackPtrLimit)); +#endif +} +#endif + + +/** + \brief Get Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always in non-secure + mode. + + \details Returns the current value of the Main Stack Pointer Limit (MSPLIM). + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __get_MSPLIM(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim" : "=r" (result) ); + return result; +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Get Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence zero is returned always. + + \details Returns the current value of the non-secure Main Stack Pointer Limit(MSPLIM) when in secure state. + \return MSPLIM Register value + */ +__STATIC_FORCEINLINE uint32_t __TZ_get_MSPLIM_NS(void) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + return 0U; +#else + uint32_t result; + __ASM volatile ("MRS %0, msplim_ns" : "=r" (result) ); + return result; +#endif +} +#endif + + +/** + \brief Set Main Stack Pointer Limit + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored in non-secure + mode. + + \details Assigns the given value to the Main Stack Pointer Limit (MSPLIM). + \param [in] MainStackPtrLimit Main Stack Pointer Limit value to set + */ +__STATIC_FORCEINLINE void __set_MSPLIM(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim, %0" : : "r" (MainStackPtrLimit)); +#endif +} + + +#if (defined (__ARM_FEATURE_CMSE ) && (__ARM_FEATURE_CMSE == 3)) +/** + \brief Set Main Stack Pointer Limit (non-secure) + Devices without ARMv8-M Main Extensions (i.e. Cortex-M23) lack the non-secure + Stack Pointer Limit register hence the write is silently ignored. + + \details Assigns the given value to the non-secure Main Stack Pointer Limit (MSPLIM) when in secure state. + \param [in] MainStackPtrLimit Main Stack Pointer value to set + */ +__STATIC_FORCEINLINE void __TZ_set_MSPLIM_NS(uint32_t MainStackPtrLimit) +{ +#if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)MainStackPtrLimit; +#else + __ASM volatile ("MSR msplim_ns, %0" : : "r" (MainStackPtrLimit)); +#endif +} +#endif + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +/** + \brief Get FPSCR + \details Returns the current value of the Floating Point Status/Control register. + \return Floating Point Status/Control register value + */ +__STATIC_FORCEINLINE uint32_t __get_FPSCR(void) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_get_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + return __builtin_arm_get_fpscr(); +#else + uint32_t result; + + __ASM volatile ("VMRS %0, fpscr" : "=r" (result) ); + return(result); +#endif +#else + return(0U); +#endif +} + + +/** + \brief Set FPSCR + \details Assigns the given value to the Floating Point Status/Control register. + \param [in] fpscr Floating Point Status/Control value to set + */ +__STATIC_FORCEINLINE void __set_FPSCR(uint32_t fpscr) +{ +#if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) +#if __has_builtin(__builtin_arm_set_fpscr) +// Re-enable using built-in when GCC has been fixed +// || (__GNUC__ > 7) || (__GNUC__ == 7 && __GNUC_MINOR__ >= 2) + /* see https://gcc.gnu.org/ml/gcc-patches/2017-04/msg00443.html */ + __builtin_arm_set_fpscr(fpscr); +#else + __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc", "memory"); +#endif +#else + (void)fpscr; +#endif +} + + +/*@} end of CMSIS_Core_RegAccFunctions */ + + +/* ########################## Core Instruction Access ######################### */ +/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface + Access to dedicated instructions + @{ +*/ + +/* Define macros for porting to both thumb1 and thumb2. + * For thumb1, use low register (r0-r7), specified by constraint "l" + * Otherwise, use general registers, specified by constraint "r" */ +#if defined (__thumb__) && !defined (__thumb2__) +#define __CMSIS_GCC_OUT_REG(r) "=l" (r) +#define __CMSIS_GCC_RW_REG(r) "+l" (r) +#define __CMSIS_GCC_USE_REG(r) "l" (r) +#else +#define __CMSIS_GCC_OUT_REG(r) "=r" (r) +#define __CMSIS_GCC_RW_REG(r) "+r" (r) +#define __CMSIS_GCC_USE_REG(r) "r" (r) +#endif + +/** + \brief No Operation + \details No Operation does nothing. This instruction can be used for code alignment purposes. + */ +#define __NOP() __ASM volatile ("nop") + +/** + \brief Wait For Interrupt + \details Wait For Interrupt is a hint instruction that suspends execution until one of a number of events occurs. + */ +#define __WFI() __ASM volatile ("wfi") + + +/** + \brief Wait For Event + \details Wait For Event is a hint instruction that permits the processor to enter + a low-power state until one of a number of events occurs. + */ +#define __WFE() __ASM volatile ("wfe") + + +/** + \brief Send Event + \details Send Event is a hint instruction. It causes an event to be signaled to the CPU. + */ +#define __SEV() __ASM volatile ("sev") + + +/** + \brief Instruction Synchronization Barrier + \details Instruction Synchronization Barrier flushes the pipeline in the processor, + so that all instructions following the ISB are fetched from cache or memory, + after the instruction has been completed. + */ +__STATIC_FORCEINLINE void __ISB(void) +{ + __ASM volatile ("isb 0xF":::"memory"); +} + + +/** + \brief Data Synchronization Barrier + \details Acts as a special kind of Data Memory Barrier. + It completes when all explicit memory accesses before this instruction complete. + */ +__STATIC_FORCEINLINE void __DSB(void) +{ + __ASM volatile ("dsb 0xF":::"memory"); +} + + +/** + \brief Data Memory Barrier + \details Ensures the apparent order of the explicit memory operations before + and after the instruction, without ensuring their completion. + */ +__STATIC_FORCEINLINE void __DMB(void) +{ + __ASM volatile ("dmb 0xF":::"memory"); +} + + +/** + \brief Reverse byte order (32 bit) + \details Reverses the byte order in unsigned integer value. For example, 0x12345678 becomes 0x78563412. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV(uint32_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5) + return __builtin_bswap32(value); +#else + uint32_t result; + + __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order within each halfword of a word. For example, 0x12345678 becomes 0x34127856. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __REV16(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +} + + +/** + \brief Reverse byte order (16 bit) + \details Reverses the byte order in a 16-bit value and returns the signed 16-bit result. For example, 0x0080 becomes 0x8000. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE int16_t __REVSH(int16_t value) +{ +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + return (int16_t)__builtin_bswap16(value); +#else + int16_t result; + + __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return result; +#endif +} + + +/** + \brief Rotate Right in unsigned value (32 bit) + \details Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits. + \param [in] op1 Value to rotate + \param [in] op2 Number of Bits to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __ROR(uint32_t op1, uint32_t op2) +{ + op2 %= 32U; + if (op2 == 0U) + { + return op1; + } + return (op1 >> op2) | (op1 << (32U - op2)); +} + + +/** + \brief Breakpoint + \details Causes the processor to enter Debug state. + Debug tools can use this to investigate system state when the instruction at a particular address is reached. + \param [in] value is ignored by the processor. + If required, a debugger can use it to store additional information about the breakpoint. + */ +#define __BKPT(value) __ASM volatile ("bkpt "#value) + + +/** + \brief Reverse bit order of value + \details Reverses the bit order of the given value. + \param [in] value Value to reverse + \return Reversed value + */ +__STATIC_FORCEINLINE uint32_t __RBIT(uint32_t value) +{ + uint32_t result; + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) + __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) ); +#else + uint32_t s = (4U /*sizeof(v)*/ * 8U) - 1U; /* extra shift needed at end */ + + result = value; /* r will be reversed bits of v; first get LSB of v */ + for (value >>= 1U; value != 0U; value >>= 1U) + { + result <<= 1U; + result |= value & 1U; + s--; + } + result <<= s; /* shift when v's highest bits are zero */ +#endif + return result; +} + + +/** + \brief Count leading zeros + \details Counts the number of leading zeros of a data value. + \param [in] value Value to count the leading zeros + \return number of leading zeros in value + */ +__STATIC_FORCEINLINE uint8_t __CLZ(uint32_t value) +{ + /* Even though __builtin_clz produces a CLZ instruction on ARM, formally + __builtin_clz(0) is undefined behaviour, so handle this case specially. + This guarantees ARM-compatible results if happening to compile on a non-ARM + target, and ensures the compiler doesn't decide to activate any + optimisations using the logic "value was passed to __builtin_clz, so it + is non-zero". + ARM GCC 7.3 and possibly earlier will optimise this test away, leaving a + single CLZ instruction. + */ + if (value == 0U) + { + return 32U; + } + return __builtin_clz(value); +} + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief LDR Exclusive (8 bit) + \details Executes a exclusive LDR instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDREXB(volatile uint8_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (16 bit) + \details Executes a exclusive LDR instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDREXH(volatile uint16_t *addr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDR Exclusive (32 bit) + \details Executes a exclusive LDR instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDREXW(volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) ); + return(result); +} + + +/** + \brief STR Exclusive (8 bit) + \details Executes a exclusive STR instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (16 bit) + \details Executes a exclusive STR instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr) +{ + uint32_t result; + + __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief STR Exclusive (32 bit) + \details Executes a exclusive STR instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr) +{ + uint32_t result; + + __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) ); + return(result); +} + + +/** + \brief Remove the exclusive lock + \details Removes the exclusive lock which is created by LDREX. + */ +__STATIC_FORCEINLINE void __CLREX(void) +{ + __ASM volatile ("clrex" ::: "memory"); +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (1..32) + \return Saturated value + */ +#define __SSAT(ARG1,ARG2) \ +__extension__ \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] ARG1 Value to be saturated + \param [in] ARG2 Bit position to saturate to (0..31) + \return Saturated value + */ +#define __USAT(ARG1,ARG2) \ + __extension__ \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + + +/** + \brief Rotate Right with Extend (32 bit) + \details Moves each bit of a bitstring right by one bit. + The carry input is shifted in at the left end of the bitstring. + \param [in] value Value to rotate + \return Rotated value + */ +__STATIC_FORCEINLINE uint32_t __RRX(uint32_t value) +{ + uint32_t result; + + __ASM volatile ("rrx %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) ); + return(result); +} + + +/** + \brief LDRT Unprivileged (8 bit) + \details Executes a Unprivileged LDRT instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDRBT(volatile uint8_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrbt %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrbt %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint8_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (16 bit) + \details Executes a Unprivileged LDRT instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDRHT(volatile uint16_t *ptr) +{ + uint32_t result; + +#if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8) + __ASM volatile ("ldrht %0, %1" : "=r" (result) : "Q" (*ptr) ); +#else + /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not + accepted by assembler. So has to use following less efficient pattern. + */ + __ASM volatile ("ldrht %0, [%1]" : "=r" (result) : "r" (ptr) : "memory" ); +#endif + return ((uint16_t) result); /* Add explicit type cast here */ +} + + +/** + \brief LDRT Unprivileged (32 bit) + \details Executes a Unprivileged LDRT instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDRT(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldrt %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief STRT Unprivileged (8 bit) + \details Executes a Unprivileged STRT instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRBT(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("strbt %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (16 bit) + \details Executes a Unprivileged STRT instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRHT(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("strht %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief STRT Unprivileged (32 bit) + \details Executes a Unprivileged STRT instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STRT(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("strt %1, %0" : "=Q" (*ptr) : "r" (value) ); +} + +#else /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + +/** + \brief Signed Saturate + \details Saturates a signed value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (1..32) + \return Saturated value + */ +__STATIC_FORCEINLINE int32_t __SSAT(int32_t val, uint32_t sat) +{ + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; +} + +/** + \brief Unsigned Saturate + \details Saturates an unsigned value. + \param [in] value Value to be saturated + \param [in] sat Bit position to saturate to (0..31) + \return Saturated value + */ +__STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat) +{ + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; +} + +#endif /* ((defined (__ARM_ARCH_7M__ ) && (__ARM_ARCH_7M__ == 1)) || \ + (defined (__ARM_ARCH_7EM__ ) && (__ARM_ARCH_7EM__ == 1)) || \ + (defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) ) */ + + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) +/** + \brief Load-Acquire (8 bit) + \details Executes a LDAB instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldab %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire (16 bit) + \details Executes a LDAH instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldah %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire (32 bit) + \details Executes a LDA instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDA(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("lda %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release (8 bit) + \details Executes a STLB instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLB(uint8_t value, volatile uint8_t *ptr) +{ + __ASM volatile ("stlb %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (16 bit) + \details Executes a STLH instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STLH(uint16_t value, volatile uint16_t *ptr) +{ + __ASM volatile ("stlh %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Store-Release (32 bit) + \details Executes a STL instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + */ +__STATIC_FORCEINLINE void __STL(uint32_t value, volatile uint32_t *ptr) +{ + __ASM volatile ("stl %1, %0" : "=Q" (*ptr) : "r" ((uint32_t)value) ); +} + + +/** + \brief Load-Acquire Exclusive (8 bit) + \details Executes a LDAB exclusive instruction for 8 bit value. + \param [in] ptr Pointer to data + \return value of type uint8_t at (*ptr) + */ +__STATIC_FORCEINLINE uint8_t __LDAEXB(volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexb %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint8_t) result); +} + + +/** + \brief Load-Acquire Exclusive (16 bit) + \details Executes a LDAH exclusive instruction for 16 bit values. + \param [in] ptr Pointer to data + \return value of type uint16_t at (*ptr) + */ +__STATIC_FORCEINLINE uint16_t __LDAEXH(volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaexh %0, %1" : "=r" (result) : "Q" (*ptr) ); + return ((uint16_t) result); +} + + +/** + \brief Load-Acquire Exclusive (32 bit) + \details Executes a LDA exclusive instruction for 32 bit values. + \param [in] ptr Pointer to data + \return value of type uint32_t at (*ptr) + */ +__STATIC_FORCEINLINE uint32_t __LDAEX(volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("ldaex %0, %1" : "=r" (result) : "Q" (*ptr) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (8 bit) + \details Executes a STLB exclusive instruction for 8 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexb %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (16 bit) + \details Executes a STLH exclusive instruction for 16 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlexh %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + + +/** + \brief Store-Release Exclusive (32 bit) + \details Executes a STL exclusive instruction for 32 bit values. + \param [in] value Value to store + \param [in] ptr Pointer to location + \return 0 Function succeeded + \return 1 Function failed + */ +__STATIC_FORCEINLINE uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) +{ + uint32_t result; + + __ASM volatile ("stlex %0, %2, %1" : "=&r" (result), "=Q" (*ptr) : "r" ((uint32_t)value) ); + return(result); +} + +#endif /* ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) */ + +/*@}*/ /* end of group CMSIS_Core_InstructionInterface */ + + +/* ################### Compiler specific Intrinsics ########################### */ +/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics + Access to dedicated SIMD instructions + @{ +*/ + +#if (defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1)) + +__STATIC_FORCEINLINE uint32_t __SADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + + +__STATIC_FORCEINLINE uint32_t __SADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHASX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __QSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USAD8(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#define __SSAT16(ARG1,ARG2) \ +({ \ + int32_t __RES, __ARG1 = (ARG1); \ + __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +#define __USAT16(ARG1,ARG2) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1); \ + __ASM ("usat16 %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \ + __RES; \ + }) + +__STATIC_FORCEINLINE uint32_t __UXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTB16(uint32_t op1) +{ + uint32_t result; + + __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1)); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUAD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLALD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLALDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SMUSD (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3) +{ + uint32_t result; + + __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLD (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint64_t __SMLSLDX (uint32_t op1, uint32_t op2, uint64_t acc) +{ + union llreg_u{ + uint32_t w32[2]; + uint64_t w64; + } llr; + llr.w64 = acc; + +#ifndef __ARMEB__ /* Little endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[0]), "=r" (llr.w32[1]): "r" (op1), "r" (op2) , "0" (llr.w32[0]), "1" (llr.w32[1]) ); +#else /* Big endian */ + __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (llr.w32[1]), "=r" (llr.w32[0]): "r" (op1), "r" (op2) , "0" (llr.w32[1]), "1" (llr.w32[0]) ); +#endif + + return(llr.w64); +} + +__STATIC_FORCEINLINE uint32_t __SEL (uint32_t op1, uint32_t op2) +{ + uint32_t result; + + __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QADD( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +__STATIC_FORCEINLINE int32_t __QSUB( int32_t op1, int32_t op2) +{ + int32_t result; + + __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) ); + return(result); +} + +#if 0 +#define __PKHBT(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) + +#define __PKHTB(ARG1,ARG2,ARG3) \ +({ \ + uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \ + if (ARG3 == 0) \ + __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2) ); \ + else \ + __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) : "r" (__ARG1), "r" (__ARG2), "I" (ARG3) ); \ + __RES; \ + }) +#endif + +#define __PKHBT(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0x0000FFFFUL) | \ + ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL) ) + +#define __PKHTB(ARG1,ARG2,ARG3) ( ((((uint32_t)(ARG1)) ) & 0xFFFF0000UL) | \ + ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL) ) + +__STATIC_FORCEINLINE int32_t __SMMLA (int32_t op1, int32_t op2, int32_t op3) +{ + int32_t result; + + __ASM volatile ("smmla %0, %1, %2, %3" : "=r" (result): "r" (op1), "r" (op2), "r" (op3) ); + return(result); +} + +#endif /* (__ARM_FEATURE_DSP == 1) */ +/*@} end of group CMSIS_SIMD_intrinsics */ + + +#pragma GCC diagnostic pop + +#endif /* __CMSIS_GCC_H */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_iccarm.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_iccarm.h new file mode 100644 index 0000000000000000000000000000000000000000..12d68fd9a63b37d3a94c1114213cdd161dddbb6d --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_iccarm.h @@ -0,0 +1,964 @@ +/**************************************************************************//** + * @file cmsis_iccarm.h + * @brief CMSIS compiler ICCARM (IAR Compiler for Arm) header file + * @version V5.1.0 + * @date 08. May 2019 + ******************************************************************************/ + +//------------------------------------------------------------------------------ +// +// Copyright (c) 2017-2019 IAR Systems +// Copyright (c) 2017-2019 Arm Limited. All rights reserved. +// +// Licensed under the Apache License, Version 2.0 (the "License") +// you may not use this file except in compliance with the License. +// You may obtain a copy of the License at +// http://www.apache.org/licenses/LICENSE-2.0 +// +// Unless required by applicable law or agreed to in writing, software +// distributed under the License is distributed on an "AS IS" BASIS, +// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +// See the License for the specific language governing permissions and +// limitations under the License. +// +//------------------------------------------------------------------------------ + + +#ifndef __CMSIS_ICCARM_H__ +#define __CMSIS_ICCARM_H__ + +#ifndef __ICCARM__ + #error This file should only be compiled by ICCARM +#endif + +#pragma system_include + +#define __IAR_FT _Pragma("inline=forced") __intrinsic + +#if (__VER__ >= 8000000) + #define __ICCARM_V8 1 +#else + #define __ICCARM_V8 0 +#endif + +#ifndef __ALIGNED + #if __ICCARM_V8 + #define __ALIGNED(x) __attribute__((aligned(x))) + #elif (__VER__ >= 7080000) + /* Needs IAR language extensions */ + #define __ALIGNED(x) __attribute__((aligned(x))) + #else + #warning No compiler specific solution for __ALIGNED.__ALIGNED is ignored. + #define __ALIGNED(x) + #endif +#endif + + +/* Define compiler macros for CPU architecture, used in CMSIS 5. + */ +#if __ARM_ARCH_6M__ || __ARM_ARCH_7M__ || __ARM_ARCH_7EM__ || __ARM_ARCH_8M_BASE__ || __ARM_ARCH_8M_MAIN__ +/* Macros already defined */ +#else + #if defined(__ARM8M_MAINLINE__) || defined(__ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM_ARCH_PROFILE) && __ARM_ARCH_PROFILE == 'M' + #if __ARM_ARCH == 6 + #define __ARM_ARCH_6M__ 1 + #elif __ARM_ARCH == 7 + #if __ARM_FEATURE_DSP + #define __ARM_ARCH_7EM__ 1 + #else + #define __ARM_ARCH_7M__ 1 + #endif + #endif /* __ARM_ARCH */ + #endif /* __ARM_ARCH_PROFILE == 'M' */ +#endif + +/* Alternativ core deduction for older ICCARM's */ +#if !defined(__ARM_ARCH_6M__) && !defined(__ARM_ARCH_7M__) && !defined(__ARM_ARCH_7EM__) && \ + !defined(__ARM_ARCH_8M_BASE__) && !defined(__ARM_ARCH_8M_MAIN__) + #if defined(__ARM6M__) && (__CORE__ == __ARM6M__) + #define __ARM_ARCH_6M__ 1 + #elif defined(__ARM7M__) && (__CORE__ == __ARM7M__) + #define __ARM_ARCH_7M__ 1 + #elif defined(__ARM7EM__) && (__CORE__ == __ARM7EM__) + #define __ARM_ARCH_7EM__ 1 + #elif defined(__ARM8M_BASELINE__) && (__CORE == __ARM8M_BASELINE__) + #define __ARM_ARCH_8M_BASE__ 1 + #elif defined(__ARM8M_MAINLINE__) && (__CORE == __ARM8M_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #elif defined(__ARM8EM_MAINLINE__) && (__CORE == __ARM8EM_MAINLINE__) + #define __ARM_ARCH_8M_MAIN__ 1 + #else + #error "Unknown target." + #endif +#endif + + + +#if defined(__ARM_ARCH_6M__) && __ARM_ARCH_6M__==1 + #define __IAR_M0_FAMILY 1 +#elif defined(__ARM_ARCH_8M_BASE__) && __ARM_ARCH_8M_BASE__==1 + #define __IAR_M0_FAMILY 1 +#else + #define __IAR_M0_FAMILY 0 +#endif + + +#ifndef __ASM + #define __ASM __asm +#endif + +#ifndef __COMPILER_BARRIER + #define __COMPILER_BARRIER() __ASM volatile("":::"memory") +#endif + +#ifndef __INLINE + #define __INLINE inline +#endif + +#ifndef __NO_RETURN + #if __ICCARM_V8 + #define __NO_RETURN __attribute__((__noreturn__)) + #else + #define __NO_RETURN _Pragma("object_attribute=__noreturn") + #endif +#endif + +#ifndef __PACKED + #if __ICCARM_V8 + #define __PACKED __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED __packed + #endif +#endif + +#ifndef __PACKED_STRUCT + #if __ICCARM_V8 + #define __PACKED_STRUCT struct __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_STRUCT __packed struct + #endif +#endif + +#ifndef __PACKED_UNION + #if __ICCARM_V8 + #define __PACKED_UNION union __attribute__((packed, aligned(1))) + #else + /* Needs IAR language extensions */ + #define __PACKED_UNION __packed union + #endif +#endif + +#ifndef __RESTRICT + #if __ICCARM_V8 + #define __RESTRICT __restrict + #else + /* Needs IAR language extensions */ + #define __RESTRICT restrict + #endif +#endif + +#ifndef __STATIC_INLINE + #define __STATIC_INLINE static inline +#endif + +#ifndef __FORCEINLINE + #define __FORCEINLINE _Pragma("inline=forced") +#endif + +#ifndef __STATIC_FORCEINLINE + #define __STATIC_FORCEINLINE __FORCEINLINE __STATIC_INLINE +#endif + +#ifndef __UNALIGNED_UINT16_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint16_t __iar_uint16_read(void const *ptr) +{ + return *(__packed uint16_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT16_READ(PTR) __iar_uint16_read(PTR) +#endif + + +#ifndef __UNALIGNED_UINT16_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint16_write(void const *ptr, uint16_t val) +{ + *(__packed uint16_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT16_WRITE(PTR,VAL) __iar_uint16_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32_READ +#pragma language=save +#pragma language=extended +__IAR_FT uint32_t __iar_uint32_read(void const *ptr) +{ + return *(__packed uint32_t*)(ptr); +} +#pragma language=restore +#define __UNALIGNED_UINT32_READ(PTR) __iar_uint32_read(PTR) +#endif + +#ifndef __UNALIGNED_UINT32_WRITE +#pragma language=save +#pragma language=extended +__IAR_FT void __iar_uint32_write(void const *ptr, uint32_t val) +{ + *(__packed uint32_t*)(ptr) = val;; +} +#pragma language=restore +#define __UNALIGNED_UINT32_WRITE(PTR,VAL) __iar_uint32_write(PTR,VAL) +#endif + +#ifndef __UNALIGNED_UINT32 /* deprecated */ +#pragma language=save +#pragma language=extended +__packed struct __iar_u32 { uint32_t v; }; +#pragma language=restore +#define __UNALIGNED_UINT32(PTR) (((struct __iar_u32 *)(PTR))->v) +#endif + +#ifndef __USED + #if __ICCARM_V8 + #define __USED __attribute__((used)) + #else + #define __USED _Pragma("__root") + #endif +#endif + +#ifndef __WEAK + #if __ICCARM_V8 + #define __WEAK __attribute__((weak)) + #else + #define __WEAK _Pragma("__weak") + #endif +#endif + +#ifndef __PROGRAM_START +#define __PROGRAM_START __iar_program_start +#endif + +#ifndef __INITIAL_SP +#define __INITIAL_SP CSTACK$$Limit +#endif + +#ifndef __STACK_LIMIT +#define __STACK_LIMIT CSTACK$$Base +#endif + +#ifndef __VECTOR_TABLE +#define __VECTOR_TABLE __vector_table +#endif + +#ifndef __VECTOR_TABLE_ATTRIBUTE +#define __VECTOR_TABLE_ATTRIBUTE @".intvec" +#endif + +#ifndef __ICCARM_INTRINSICS_VERSION__ + #define __ICCARM_INTRINSICS_VERSION__ 0 +#endif + +#if __ICCARM_INTRINSICS_VERSION__ == 2 + + #if defined(__CLZ) + #undef __CLZ + #endif + #if defined(__REVSH) + #undef __REVSH + #endif + #if defined(__RBIT) + #undef __RBIT + #endif + #if defined(__SSAT) + #undef __SSAT + #endif + #if defined(__USAT) + #undef __USAT + #endif + + #include "iccarm_builtin.h" + + #define __disable_fault_irq __iar_builtin_disable_fiq + #define __disable_irq __iar_builtin_disable_interrupt + #define __enable_fault_irq __iar_builtin_enable_fiq + #define __enable_irq __iar_builtin_enable_interrupt + #define __arm_rsr __iar_builtin_rsr + #define __arm_wsr __iar_builtin_wsr + + + #define __get_APSR() (__arm_rsr("APSR")) + #define __get_BASEPRI() (__arm_rsr("BASEPRI")) + #define __get_CONTROL() (__arm_rsr("CONTROL")) + #define __get_FAULTMASK() (__arm_rsr("FAULTMASK")) + + #if ((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) ) + #define __get_FPSCR() (__arm_rsr("FPSCR")) + #define __set_FPSCR(VALUE) (__arm_wsr("FPSCR", (VALUE))) + #else + #define __get_FPSCR() ( 0 ) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #define __get_IPSR() (__arm_rsr("IPSR")) + #define __get_MSP() (__arm_rsr("MSP")) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __get_MSPLIM() (0U) + #else + #define __get_MSPLIM() (__arm_rsr("MSPLIM")) + #endif + #define __get_PRIMASK() (__arm_rsr("PRIMASK")) + #define __get_PSP() (__arm_rsr("PSP")) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __get_PSPLIM() (0U) + #else + #define __get_PSPLIM() (__arm_rsr("PSPLIM")) + #endif + + #define __get_xPSR() (__arm_rsr("xPSR")) + + #define __set_BASEPRI(VALUE) (__arm_wsr("BASEPRI", (VALUE))) + #define __set_BASEPRI_MAX(VALUE) (__arm_wsr("BASEPRI_MAX", (VALUE))) + #define __set_CONTROL(VALUE) (__arm_wsr("CONTROL", (VALUE))) + #define __set_FAULTMASK(VALUE) (__arm_wsr("FAULTMASK", (VALUE))) + #define __set_MSP(VALUE) (__arm_wsr("MSP", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + #define __set_MSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_MSPLIM(VALUE) (__arm_wsr("MSPLIM", (VALUE))) + #endif + #define __set_PRIMASK(VALUE) (__arm_wsr("PRIMASK", (VALUE))) + #define __set_PSP(VALUE) (__arm_wsr("PSP", (VALUE))) + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __set_PSPLIM(VALUE) ((void)(VALUE)) + #else + #define __set_PSPLIM(VALUE) (__arm_wsr("PSPLIM", (VALUE))) + #endif + + #define __TZ_get_CONTROL_NS() (__arm_rsr("CONTROL_NS")) + #define __TZ_set_CONTROL_NS(VALUE) (__arm_wsr("CONTROL_NS", (VALUE))) + #define __TZ_get_PSP_NS() (__arm_rsr("PSP_NS")) + #define __TZ_set_PSP_NS(VALUE) (__arm_wsr("PSP_NS", (VALUE))) + #define __TZ_get_MSP_NS() (__arm_rsr("MSP_NS")) + #define __TZ_set_MSP_NS(VALUE) (__arm_wsr("MSP_NS", (VALUE))) + #define __TZ_get_SP_NS() (__arm_rsr("SP_NS")) + #define __TZ_set_SP_NS(VALUE) (__arm_wsr("SP_NS", (VALUE))) + #define __TZ_get_PRIMASK_NS() (__arm_rsr("PRIMASK_NS")) + #define __TZ_set_PRIMASK_NS(VALUE) (__arm_wsr("PRIMASK_NS", (VALUE))) + #define __TZ_get_BASEPRI_NS() (__arm_rsr("BASEPRI_NS")) + #define __TZ_set_BASEPRI_NS(VALUE) (__arm_wsr("BASEPRI_NS", (VALUE))) + #define __TZ_get_FAULTMASK_NS() (__arm_rsr("FAULTMASK_NS")) + #define __TZ_set_FAULTMASK_NS(VALUE)(__arm_wsr("FAULTMASK_NS", (VALUE))) + + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + #define __TZ_get_PSPLIM_NS() (0U) + #define __TZ_set_PSPLIM_NS(VALUE) ((void)(VALUE)) + #else + #define __TZ_get_PSPLIM_NS() (__arm_rsr("PSPLIM_NS")) + #define __TZ_set_PSPLIM_NS(VALUE) (__arm_wsr("PSPLIM_NS", (VALUE))) + #endif + + #define __TZ_get_MSPLIM_NS() (__arm_rsr("MSPLIM_NS")) + #define __TZ_set_MSPLIM_NS(VALUE) (__arm_wsr("MSPLIM_NS", (VALUE))) + + #define __NOP __iar_builtin_no_operation + + #define __CLZ __iar_builtin_CLZ + #define __CLREX __iar_builtin_CLREX + + #define __DMB __iar_builtin_DMB + #define __DSB __iar_builtin_DSB + #define __ISB __iar_builtin_ISB + + #define __LDREXB __iar_builtin_LDREXB + #define __LDREXH __iar_builtin_LDREXH + #define __LDREXW __iar_builtin_LDREX + + #define __RBIT __iar_builtin_RBIT + #define __REV __iar_builtin_REV + #define __REV16 __iar_builtin_REV16 + + __IAR_FT int16_t __REVSH(int16_t val) + { + return (int16_t) __iar_builtin_REVSH(val); + } + + #define __ROR __iar_builtin_ROR + #define __RRX __iar_builtin_RRX + + #define __SEV __iar_builtin_SEV + + #if !__IAR_M0_FAMILY + #define __SSAT __iar_builtin_SSAT + #endif + + #define __STREXB __iar_builtin_STREXB + #define __STREXH __iar_builtin_STREXH + #define __STREXW __iar_builtin_STREX + + #if !__IAR_M0_FAMILY + #define __USAT __iar_builtin_USAT + #endif + + #define __WFE __iar_builtin_WFE + #define __WFI __iar_builtin_WFI + + #if __ARM_MEDIA__ + #define __SADD8 __iar_builtin_SADD8 + #define __QADD8 __iar_builtin_QADD8 + #define __SHADD8 __iar_builtin_SHADD8 + #define __UADD8 __iar_builtin_UADD8 + #define __UQADD8 __iar_builtin_UQADD8 + #define __UHADD8 __iar_builtin_UHADD8 + #define __SSUB8 __iar_builtin_SSUB8 + #define __QSUB8 __iar_builtin_QSUB8 + #define __SHSUB8 __iar_builtin_SHSUB8 + #define __USUB8 __iar_builtin_USUB8 + #define __UQSUB8 __iar_builtin_UQSUB8 + #define __UHSUB8 __iar_builtin_UHSUB8 + #define __SADD16 __iar_builtin_SADD16 + #define __QADD16 __iar_builtin_QADD16 + #define __SHADD16 __iar_builtin_SHADD16 + #define __UADD16 __iar_builtin_UADD16 + #define __UQADD16 __iar_builtin_UQADD16 + #define __UHADD16 __iar_builtin_UHADD16 + #define __SSUB16 __iar_builtin_SSUB16 + #define __QSUB16 __iar_builtin_QSUB16 + #define __SHSUB16 __iar_builtin_SHSUB16 + #define __USUB16 __iar_builtin_USUB16 + #define __UQSUB16 __iar_builtin_UQSUB16 + #define __UHSUB16 __iar_builtin_UHSUB16 + #define __SASX __iar_builtin_SASX + #define __QASX __iar_builtin_QASX + #define __SHASX __iar_builtin_SHASX + #define __UASX __iar_builtin_UASX + #define __UQASX __iar_builtin_UQASX + #define __UHASX __iar_builtin_UHASX + #define __SSAX __iar_builtin_SSAX + #define __QSAX __iar_builtin_QSAX + #define __SHSAX __iar_builtin_SHSAX + #define __USAX __iar_builtin_USAX + #define __UQSAX __iar_builtin_UQSAX + #define __UHSAX __iar_builtin_UHSAX + #define __USAD8 __iar_builtin_USAD8 + #define __USADA8 __iar_builtin_USADA8 + #define __SSAT16 __iar_builtin_SSAT16 + #define __USAT16 __iar_builtin_USAT16 + #define __UXTB16 __iar_builtin_UXTB16 + #define __UXTAB16 __iar_builtin_UXTAB16 + #define __SXTB16 __iar_builtin_SXTB16 + #define __SXTAB16 __iar_builtin_SXTAB16 + #define __SMUAD __iar_builtin_SMUAD + #define __SMUADX __iar_builtin_SMUADX + #define __SMMLA __iar_builtin_SMMLA + #define __SMLAD __iar_builtin_SMLAD + #define __SMLADX __iar_builtin_SMLADX + #define __SMLALD __iar_builtin_SMLALD + #define __SMLALDX __iar_builtin_SMLALDX + #define __SMUSD __iar_builtin_SMUSD + #define __SMUSDX __iar_builtin_SMUSDX + #define __SMLSD __iar_builtin_SMLSD + #define __SMLSDX __iar_builtin_SMLSDX + #define __SMLSLD __iar_builtin_SMLSLD + #define __SMLSLDX __iar_builtin_SMLSLDX + #define __SEL __iar_builtin_SEL + #define __QADD __iar_builtin_QADD + #define __QSUB __iar_builtin_QSUB + #define __PKHBT __iar_builtin_PKHBT + #define __PKHTB __iar_builtin_PKHTB + #endif + +#else /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #define __CLZ __cmsis_iar_clz_not_active + #define __SSAT __cmsis_iar_ssat_not_active + #define __USAT __cmsis_iar_usat_not_active + #define __RBIT __cmsis_iar_rbit_not_active + #define __get_APSR __cmsis_iar_get_APSR_not_active + #endif + + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #define __get_FPSCR __cmsis_iar_get_FPSR_not_active + #define __set_FPSCR __cmsis_iar_set_FPSR_not_active + #endif + + #ifdef __INTRINSICS_INCLUDED + #error intrinsics.h is already included previously! + #endif + + #include + + #if __IAR_M0_FAMILY + /* Avoid clash between intrinsics.h and arm_math.h when compiling for Cortex-M0. */ + #undef __CLZ + #undef __SSAT + #undef __USAT + #undef __RBIT + #undef __get_APSR + + __STATIC_INLINE uint8_t __CLZ(uint32_t data) + { + if (data == 0U) { return 32U; } + + uint32_t count = 0U; + uint32_t mask = 0x80000000U; + + while ((data & mask) == 0U) + { + count += 1U; + mask = mask >> 1U; + } + return count; + } + + __STATIC_INLINE uint32_t __RBIT(uint32_t v) + { + uint8_t sc = 31U; + uint32_t r = v; + for (v >>= 1U; v; v >>= 1U) + { + r <<= 1U; + r |= v & 1U; + sc--; + } + return (r << sc); + } + + __STATIC_INLINE uint32_t __get_APSR(void) + { + uint32_t res; + __asm("MRS %0,APSR" : "=r" (res)); + return res; + } + + #endif + + #if (!((defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U)) && \ + (defined (__FPU_USED ) && (__FPU_USED == 1U)) )) + #undef __get_FPSCR + #undef __set_FPSCR + #define __get_FPSCR() (0) + #define __set_FPSCR(VALUE) ((void)VALUE) + #endif + + #pragma diag_suppress=Pe940 + #pragma diag_suppress=Pe177 + + #define __enable_irq __enable_interrupt + #define __disable_irq __disable_interrupt + #define __NOP __no_operation + + #define __get_xPSR __get_PSR + + #if (!defined(__ARM_ARCH_6M__) || __ARM_ARCH_6M__==0) + + __IAR_FT uint32_t __LDREXW(uint32_t volatile *ptr) + { + return __LDREX((unsigned long *)ptr); + } + + __IAR_FT uint32_t __STREXW(uint32_t value, uint32_t volatile *ptr) + { + return __STREX(value, (unsigned long *)ptr); + } + #endif + + + /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + #if (__CORTEX_M >= 0x03) + + __IAR_FT uint32_t __RRX(uint32_t value) + { + uint32_t result; + __ASM("RRX %0, %1" : "=r"(result) : "r" (value) : "cc"); + return(result); + } + + __IAR_FT void __set_BASEPRI_MAX(uint32_t value) + { + __asm volatile("MSR BASEPRI_MAX,%0"::"r" (value)); + } + + + #define __enable_fault_irq __enable_fiq + #define __disable_fault_irq __disable_fiq + + + #endif /* (__CORTEX_M >= 0x03) */ + + __IAR_FT uint32_t __ROR(uint32_t op1, uint32_t op2) + { + return (op1 >> op2) | (op1 << ((sizeof(op1)*8)-op2)); + } + + #if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + __IAR_FT uint32_t __get_MSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,MSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_MSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure MSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR MSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __get_PSPLIM(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __set_PSPLIM(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_CONTROL_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,CONTROL_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_CONTROL_NS(uint32_t value) + { + __asm volatile("MSR CONTROL_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PSP_NS(uint32_t value) + { + __asm volatile("MSR PSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_MSP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSP_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSP_NS(uint32_t value) + { + __asm volatile("MSR MSP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_SP_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,SP_NS" : "=r" (res)); + return res; + } + __IAR_FT void __TZ_set_SP_NS(uint32_t value) + { + __asm volatile("MSR SP_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PRIMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,PRIMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_PRIMASK_NS(uint32_t value) + { + __asm volatile("MSR PRIMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_BASEPRI_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,BASEPRI_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_BASEPRI_NS(uint32_t value) + { + __asm volatile("MSR BASEPRI_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_FAULTMASK_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,FAULTMASK_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_FAULTMASK_NS(uint32_t value) + { + __asm volatile("MSR FAULTMASK_NS,%0" :: "r" (value)); + } + + __IAR_FT uint32_t __TZ_get_PSPLIM_NS(void) + { + uint32_t res; + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + res = 0U; + #else + __asm volatile("MRS %0,PSPLIM_NS" : "=r" (res)); + #endif + return res; + } + + __IAR_FT void __TZ_set_PSPLIM_NS(uint32_t value) + { + #if (!(defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) && \ + (!defined (__ARM_FEATURE_CMSE ) || (__ARM_FEATURE_CMSE < 3))) + // without main extensions, the non-secure PSPLIM is RAZ/WI + (void)value; + #else + __asm volatile("MSR PSPLIM_NS,%0" :: "r" (value)); + #endif + } + + __IAR_FT uint32_t __TZ_get_MSPLIM_NS(void) + { + uint32_t res; + __asm volatile("MRS %0,MSPLIM_NS" : "=r" (res)); + return res; + } + + __IAR_FT void __TZ_set_MSPLIM_NS(uint32_t value) + { + __asm volatile("MSR MSPLIM_NS,%0" :: "r" (value)); + } + + #endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#endif /* __ICCARM_INTRINSICS_VERSION__ == 2 */ + +#define __BKPT(value) __asm volatile ("BKPT %0" : : "i"(value)) + +#if __IAR_M0_FAMILY + __STATIC_INLINE int32_t __SSAT(int32_t val, uint32_t sat) + { + if ((sat >= 1U) && (sat <= 32U)) + { + const int32_t max = (int32_t)((1U << (sat - 1U)) - 1U); + const int32_t min = -1 - max ; + if (val > max) + { + return max; + } + else if (val < min) + { + return min; + } + } + return val; + } + + __STATIC_INLINE uint32_t __USAT(int32_t val, uint32_t sat) + { + if (sat <= 31U) + { + const uint32_t max = ((1U << sat) - 1U); + if (val > (int32_t)max) + { + return max; + } + else if (val < 0) + { + return 0U; + } + } + return (uint32_t)val; + } +#endif + +#if (__CORTEX_M >= 0x03) /* __CORTEX_M is defined in core_cm0.h, core_cm3.h and core_cm4.h. */ + + __IAR_FT uint8_t __LDRBT(volatile uint8_t *addr) + { + uint32_t res; + __ASM("LDRBT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDRHT(volatile uint16_t *addr) + { + uint32_t res; + __ASM("LDRHT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDRT(volatile uint32_t *addr) + { + uint32_t res; + __ASM("LDRT %0, [%1]" : "=r" (res) : "r" (addr) : "memory"); + return res; + } + + __IAR_FT void __STRBT(uint8_t value, volatile uint8_t *addr) + { + __ASM("STRBT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRHT(uint16_t value, volatile uint16_t *addr) + { + __ASM("STRHT %1, [%0]" : : "r" (addr), "r" ((uint32_t)value) : "memory"); + } + + __IAR_FT void __STRT(uint32_t value, volatile uint32_t *addr) + { + __ASM("STRT %1, [%0]" : : "r" (addr), "r" (value) : "memory"); + } + +#endif /* (__CORTEX_M >= 0x03) */ + +#if ((defined (__ARM_ARCH_8M_MAIN__ ) && (__ARM_ARCH_8M_MAIN__ == 1)) || \ + (defined (__ARM_ARCH_8M_BASE__ ) && (__ARM_ARCH_8M_BASE__ == 1)) ) + + + __IAR_FT uint8_t __LDAB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDA(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDA %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT void __STLB(uint8_t value, volatile uint8_t *ptr) + { + __ASM volatile ("STLB %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STLH(uint16_t value, volatile uint16_t *ptr) + { + __ASM volatile ("STLH %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT void __STL(uint32_t value, volatile uint32_t *ptr) + { + __ASM volatile ("STL %1, [%0]" :: "r" (ptr), "r" (value) : "memory"); + } + + __IAR_FT uint8_t __LDAEXB(volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXB %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint8_t)res); + } + + __IAR_FT uint16_t __LDAEXH(volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEXH %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return ((uint16_t)res); + } + + __IAR_FT uint32_t __LDAEX(volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("LDAEX %0, [%1]" : "=r" (res) : "r" (ptr) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXB(uint8_t value, volatile uint8_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXB %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEXH(uint16_t value, volatile uint16_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEXH %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + + __IAR_FT uint32_t __STLEX(uint32_t value, volatile uint32_t *ptr) + { + uint32_t res; + __ASM volatile ("STLEX %0, %2, [%1]" : "=r" (res) : "r" (ptr), "r" (value) : "memory"); + return res; + } + +#endif /* __ARM_ARCH_8M_MAIN__ or __ARM_ARCH_8M_BASE__ */ + +#undef __IAR_FT +#undef __IAR_M0_FAMILY +#undef __ICCARM_V8 + +#pragma diag_default=Pe940 +#pragma diag_default=Pe177 + +#endif /* __CMSIS_ICCARM_H__ */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_version.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_version.h new file mode 100644 index 0000000000000000000000000000000000000000..f2e2746626afefeebcc3435ef433895b5bcc4cdb --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/cmsis_version.h @@ -0,0 +1,39 @@ +/**************************************************************************//** + * @file cmsis_version.h + * @brief CMSIS Core(M) Version definitions + * @version V5.0.3 + * @date 24. June 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 ARM Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CMSIS_VERSION_H +#define __CMSIS_VERSION_H + +/* CMSIS Version definitions */ +#define __CM_CMSIS_VERSION_MAIN ( 5U) /*!< [31:16] CMSIS Core(M) main version */ +#define __CM_CMSIS_VERSION_SUB ( 3U) /*!< [15:0] CMSIS Core(M) sub version */ +#define __CM_CMSIS_VERSION ((__CM_CMSIS_VERSION_MAIN << 16U) | \ + __CM_CMSIS_VERSION_SUB ) /*!< CMSIS Core(M) version number */ +#endif diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv81mml.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv81mml.h new file mode 100644 index 0000000000000000000000000000000000000000..8441e57fb1b917bc669588a6cc94b439b565374d --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv81mml.h @@ -0,0 +1,2968 @@ +/**************************************************************************//** + * @file core_armv81mml.h + * @brief CMSIS Armv8.1-M Mainline Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 15. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2018-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV81MML_H_GENERIC +#define __CORE_ARMV81MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMV81MML + @{ + */ + +#include "cmsis_version.h" + +#define __ARM_ARCH_8M_MAIN__ 1 // patching for now +/* CMSIS ARMV81MML definitions */ +#define __ARMv81MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv81MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv81MML_CMSIS_VERSION ((__ARMv81MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv81MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV81MML_H_DEPENDANT +#define __CORE_ARMV81MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv81MML_REV + #define __ARMv81MML_REV 0x0000U + #warning "__ARMv81MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv81MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[29U]; + __OM uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */ + __IM uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */ + __IOM uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */ + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Integration Write Register Definitions */ +#define ITM_IWR_ATVALIDM_Pos 0U /*!< ITM IWR: ATVALIDM Position */ +#define ITM_IWR_ATVALIDM_Msk (1UL /*<< ITM_IWR_ATVALIDM_Pos*/) /*!< ITM IWR: ATVALIDM Mask */ + +/* ITM Integration Read Register Definitions */ +#define ITM_IRR_ATREADYM_Pos 0U /*!< ITM IRR: ATREADYM Position */ +#define ITM_IRR_ATREADYM_Msk (1UL /*<< ITM_IRR_ATREADYM_Pos*/) /*!< ITM IRR: ATREADYM Mask */ + +/* ITM Integration Mode Control Register Definitions */ +#define ITM_IMCR_INTEGRATION_Pos 0U /*!< ITM IMCR: INTEGRATION Position */ +#define ITM_IMCR_INTEGRATION_Msk (1UL /*<< ITM_IMCR_INTEGRATION_Pos*/) /*!< ITM IMCR: INTEGRATION Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY_Pos 0U /*!< TPI ITATBCTR2: ATREADY Position */ +#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY_Pos*/) /*!< TPI ITATBCTR2: ATREADY Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY_Pos 0U /*!< TPI ITATBCTR0: ATREADY Position */ +#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY_Pos*/) /*!< TPI ITATBCTR0: ATREADY Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x1UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_MajorType_Pos 4U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +#define TPI_DEVTYPE_SubType_Pos 0U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_PXN_Pos 4U /*!< MPU RLAR: PXN Position */ +#define MPU_RLAR_PXN_Msk (0x1UL << MPU_RLAR_PXN_Pos) /*!< MPU RLAR: PXN Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << 8U) ); /* Insert write key and priorty group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV81MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv8mbl.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv8mbl.h new file mode 100644 index 0000000000000000000000000000000000000000..344dca51483e7388f6681ea89b7508a29a276a25 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv8mbl.h @@ -0,0 +1,1921 @@ +/**************************************************************************//** + * @file core_armv8mbl.h + * @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MBL_H_GENERIC +#define __CORE_ARMV8MBL_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MBL + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MBL_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M ( 2U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MBL_H_DEPENDANT +#define __CORE_ARMV8MBL_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MBL_REV + #define __ARMv8MBL_REV 0x0000U + #warning "__ARMv8MBL_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MBL */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MBL_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv8mml.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv8mml.h new file mode 100644 index 0000000000000000000000000000000000000000..5ddb8aeda7f58da418da42f6da1403f4925fdc8c --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_armv8mml.h @@ -0,0 +1,2835 @@ +/**************************************************************************//** + * @file core_armv8mml.h + * @brief CMSIS Armv8-M Mainline Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. September 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_ARMV8MML_H_GENERIC +#define __CORE_ARMV8MML_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_ARMv8MML + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS Armv8MML definitions */ +#define __ARMv8MML_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __ARMv8MML_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __ARMv8MML_CMSIS_VERSION ((__ARMv8MML_CMSIS_VERSION_MAIN << 16U) | \ + __ARMv8MML_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (81U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined(__ARM_FEATURE_DSP) + #if defined(__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_ARMV8MML_H_DEPENDANT +#define __CORE_ARMV8MML_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __ARMv8MML_REV + #define __ARMv8MML_REV 0x0000U + #warning "__ARMv8MML_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group ARMv8MML */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Sizes Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Sizes Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[809U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) Software Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) Software Lock Status Register */ + uint32_t RESERVED4[4U]; + __IM uint32_t TYPE; /*!< Offset: 0xFC8 (R/ ) Device Identifier Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_SWOSCALER_Pos 0U /*!< TPI ACPR: SWOSCALER Position */ +#define TPI_ACPR_SWOSCALER_Msk (0xFFFFUL /*<< TPI_ACPR_SWOSCALER_Pos*/) /*!< TPI ACPR: SWOSCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI Periodic Synchronization Control Register Definitions */ +#define TPI_PSCR_PSCount_Pos 0U /*!< TPI PSCR: PSCount Position */ +#define TPI_PSCR_PSCount_Msk (0x1FUL /*<< TPI_PSCR_PSCount_Pos*/) /*!< TPI PSCR: TPSCount Mask */ + +/* TPI Software Lock Status Register Definitions */ +#define TPI_LSR_nTT_Pos 1U /*!< TPI LSR: Not thirty-two bit. Position */ +#define TPI_LSR_nTT_Msk (0x1UL << TPI_LSR_nTT_Pos) /*!< TPI LSR: Not thirty-two bit. Mask */ + +#define TPI_LSR_SLK_Pos 1U /*!< TPI LSR: Software Lock status Position */ +#define TPI_LSR_SLK_Msk (0x1UL << TPI_LSR_SLK_Pos) /*!< TPI LSR: Software Lock status Mask */ + +#define TPI_LSR_SLI_Pos 0U /*!< TPI LSR: Software Lock implemented Position */ +#define TPI_LSR_SLI_Msk (0x1UL /*<< TPI_LSR_SLI_Pos*/) /*!< TPI LSR: Software Lock implemented Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFO depth Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFO depth Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_ARMV8MML_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm0.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm0.h new file mode 100644 index 0000000000000000000000000000000000000000..cafae5a0a73644129a486644044b54eedee18d11 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm0.h @@ -0,0 +1,952 @@ +/**************************************************************************//** + * @file core_cm0.h + * @brief CMSIS Cortex-M0 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0_H_GENERIC +#define __CORE_CM0_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M0 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0 definitions */ +#define __CM0_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0_CMSIS_VERSION ((__CM0_CMSIS_VERSION_MAIN << 16U) | \ + __CM0_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0_H_DEPENDANT +#define __CORE_CM0_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0_REV + #define __CM0_REV 0x0000U + #warning "__CM0_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M0 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = 0x0U; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = 0x0U; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm0plus.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm0plus.h new file mode 100644 index 0000000000000000000000000000000000000000..d104965db5198d5b45737d48abb3981fc1936ba2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm0plus.h @@ -0,0 +1,1085 @@ +/**************************************************************************//** + * @file core_cm0plus.h + * @brief CMSIS Cortex-M0+ Core Peripheral Access Layer Header File + * @version V5.0.7 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM0PLUS_H_GENERIC +#define __CORE_CM0PLUS_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex-M0+ + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM0+ definitions */ +#define __CM0PLUS_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM0PLUS_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM0PLUS_CMSIS_VERSION ((__CM0PLUS_CMSIS_VERSION_MAIN << 16U) | \ + __CM0PLUS_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (0U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM0PLUS_H_DEPENDANT +#define __CORE_CM0PLUS_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM0PLUS_REV + #define __CM0PLUS_REV 0x0000U + #warning "__CM0PLUS_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex-M0+ */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 8U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0xFFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M0+ Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M0+ header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M0+ */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M0+ does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t vectors = SCB->VTOR; +#else + uint32_t vectors = 0x0U; +#endif + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM0PLUS_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm1.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm1.h new file mode 100644 index 0000000000000000000000000000000000000000..76b4569743a651d8c8188924c487c159ec3132a3 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm1.h @@ -0,0 +1,979 @@ +/**************************************************************************//** + * @file core_cm1.h + * @brief CMSIS Cortex-M1 Core Peripheral Access Layer Header File + * @version V1.0.1 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM1_H_GENERIC +#define __CORE_CM1_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M1 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM1 definitions */ +#define __CM1_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM1_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM1_CMSIS_VERSION ((__CM1_CMSIS_VERSION_MAIN << 16U) | \ + __CM1_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (1U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM1_H_DEPENDANT +#define __CORE_CM1_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM1_REV + #define __CM1_REV 0x0100U + #warning "__CM1_REV not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M1 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + uint32_t RESERVED0; + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_ITCMUAEN_Pos 4U /*!< ACTLR: Instruction TCM Upper Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMUAEN_Msk (1UL << SCnSCB_ACTLR_ITCMUAEN_Pos) /*!< ACTLR: Instruction TCM Upper Alias Enable Mask */ + +#define SCnSCB_ACTLR_ITCMLAEN_Pos 3U /*!< ACTLR: Instruction TCM Lower Alias Enable Position */ +#define SCnSCB_ACTLR_ITCMLAEN_Msk (1UL << SCnSCB_ACTLR_ITCMLAEN_Pos) /*!< ACTLR: Instruction TCM Lower Alias Enable Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Cortex-M1 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the Cortex-M1 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for Cortex-M1 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + Address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)0x0U; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M1 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)0x0U; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM1_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm23.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm23.h new file mode 100644 index 0000000000000000000000000000000000000000..b79c6af0b1edb390960a492a0fdd56cf0ac5e13f --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm23.h @@ -0,0 +1,1996 @@ +/**************************************************************************//** + * @file core_cm23.h + * @brief CMSIS Cortex-M23 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM23_H_GENERIC +#define __CORE_CM23_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M23 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS definitions */ +#define __CM23_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM23_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM23_CMSIS_VERSION ((__CM23_CMSIS_VERSION_MAIN << 16U) | \ + __CM23_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (23U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM23_H_DEPENDANT +#define __CORE_CM23_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM23_REV + #define __CM23_REV 0x0000U + #warning "__CM23_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __VTOR_PRESENT + #define __VTOR_PRESENT 0U + #warning "__VTOR_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif + + #ifndef __ETM_PRESENT + #define __ETM_PRESENT 0U + #warning "__ETM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MTB_PRESENT + #define __MTB_PRESENT 0U + #warning "__MTB_PRESENT not defined in device header file; using default!" + #endif + +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M23 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint32_t IPR[124U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ +#else + uint32_t RESERVED0; +#endif + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED1; + __IOM uint32_t SHPR[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + uint32_t RESERVED0[6U]; + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + uint32_t RESERVED0[7U]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 1U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: EN Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: EN Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#endif +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register */ +#define CoreDebug_DEMCR_DWTENA_Pos 24U /*!< CoreDebug DEMCR: DWTENA Position */ +#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /*!< CoreDebug DEMCR: DWTENA Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Cortex-M23 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Cortex-M23 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + +#define __NVIC_SetPriorityGrouping(X) (void)(X) +#define __NVIC_GetPriorityGrouping() (0U) + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + If VTOR is not present address 0 must be mapped to SRAM. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ +#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U) + uint32_t *vectors = (uint32_t *)SCB->VTOR; +#else + uint32_t *vectors = (uint32_t *)0x0U; +#endif + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM23_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm3.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm3.h new file mode 100644 index 0000000000000000000000000000000000000000..8157ca782da2c1d0515ec4be7252534f039ce562 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm3.h @@ -0,0 +1,1937 @@ +/**************************************************************************//** + * @file core_cm3.h + * @brief CMSIS Cortex-M3 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM3_H_GENERIC +#define __CORE_CM3_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M3 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM3 definitions */ +#define __CM3_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM3_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM3_CMSIS_VERSION ((__CM3_CMSIS_VERSION_MAIN << 16U) | \ + __CM3_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (3U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM3_H_DEPENDANT +#define __CORE_CM3_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM3_REV + #define __CM3_REV 0x0200U + #warning "__CM3_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M3 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV < 0x0201U) /* core r2p1 */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#else +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ +#endif + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +#else + uint32_t RESERVED1[1U]; +#endif +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#if defined (__CM3_REV) && (__CM3_REV >= 0x200U) +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ +#endif + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM3_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm33.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm33.h new file mode 100644 index 0000000000000000000000000000000000000000..7fed59a88e31707a7fc126bd96f5b9cb84d8b1fd --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm33.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm33.h + * @brief CMSIS Cortex-M33 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM33_H_GENERIC +#define __CORE_CM33_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M33 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM33 definitions */ +#define __CM33_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM33_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM33_CMSIS_VERSION ((__CM33_CMSIS_VERSION_MAIN << 16U) | \ + __CM33_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (33U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM33_H_DEPENDANT +#define __CORE_CM33_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM33_REV + #define __CM33_REV 0x0000U + #warning "__CM33_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M33 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM33_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm35p.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm35p.h new file mode 100644 index 0000000000000000000000000000000000000000..5579c823068095053751a108d29b2af612d8541e --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm35p.h @@ -0,0 +1,2910 @@ +/**************************************************************************//** + * @file core_cm35p.h + * @brief CMSIS Cortex-M35P Core Peripheral Access Layer Header File + * @version V1.0.0 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM35P_H_GENERIC +#define __CORE_CM35P_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M35P + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM35P definitions */ +#define __CM35P_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM35P_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM35P_CMSIS_VERSION ((__CM35P_CMSIS_VERSION_MAIN << 16U) | \ + __CM35P_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (35U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined (__TARGET_FPU_VFP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined (__ARM_FP) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined (__ARMVFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + + #if defined (__ARM_FEATURE_DSP) && (__ARM_FEATURE_DSP == 1U) + #if defined (__DSP_PRESENT) && (__DSP_PRESENT == 1U) + #define __DSP_USED 1U + #else + #error "Compiler generates DSP (SIMD) instructions for a devices without DSP extensions (check __DSP_PRESENT)" + #define __DSP_USED 0U + #endif + #else + #define __DSP_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined (__TI_VFP_SUPPORT__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined (__FPU_VFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM35P_H_DEPENDANT +#define __CORE_CM35P_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM35P_REV + #define __CM35P_REV 0x0000U + #warning "__CM35P_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __SAUREGION_PRESENT + #define __SAUREGION_PRESENT 0U + #warning "__SAUREGION_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DSP_PRESENT + #define __DSP_PRESENT 0U + #warning "__DSP_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M35P */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core SAU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_IT_Pos 25U /*!< xPSR: IT Position */ +#define xPSR_IT_Msk (3UL << xPSR_IT_Pos) /*!< xPSR: IT Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack-pointer select */ + uint32_t FPCA:1; /*!< bit: 2 Floating-point context active */ + uint32_t SFPA:1; /*!< bit: 3 Secure floating-point active */ + uint32_t _reserved1:28; /*!< bit: 4..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SFPA_Pos 3U /*!< CONTROL: SFPA Position */ +#define CONTROL_SFPA_Msk (1UL << CONTROL_SFPA_Pos) /*!< CONTROL: SFPA Mask */ + +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[16U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[16U]; + __IOM uint32_t ICER[16U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[16U]; + __IOM uint32_t ISPR[16U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[16U]; + __IOM uint32_t ICPR[16U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[16U]; + __IOM uint32_t IABR[16U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[16U]; + __IOM uint32_t ITNS[16U]; /*!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register */ + uint32_t RESERVED5[16U]; + __IOM uint8_t IPR[496U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED6[580U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[6U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + __IOM uint32_t NSACR; /*!< Offset: 0x08C (R/W) Non-Secure Access Control Register */ + uint32_t RESERVED3[92U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_PENDNMISET_Pos 31U /*!< SCB ICSR: PENDNMISET Position */ +#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /*!< SCB ICSR: PENDNMISET Mask */ + +#define SCB_ICSR_NMIPENDSET_Pos SCB_ICSR_PENDNMISET_Pos /*!< SCB ICSR: NMIPENDSET Position, backward compatibility */ +#define SCB_ICSR_NMIPENDSET_Msk SCB_ICSR_PENDNMISET_Msk /*!< SCB ICSR: NMIPENDSET Mask, backward compatibility */ + +#define SCB_ICSR_PENDNMICLR_Pos 30U /*!< SCB ICSR: PENDNMICLR Position */ +#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /*!< SCB ICSR: PENDNMICLR Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_STTNS_Pos 24U /*!< SCB ICSR: STTNS Position (Security Extension) */ +#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /*!< SCB ICSR: STTNS Mask (Security Extension) */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIS_Pos 14U /*!< SCB AIRCR: PRIS Position */ +#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /*!< SCB AIRCR: PRIS Mask */ + +#define SCB_AIRCR_BFHFNMINS_Pos 13U /*!< SCB AIRCR: BFHFNMINS Position */ +#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /*!< SCB AIRCR: BFHFNMINS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQS_Pos 3U /*!< SCB AIRCR: SYSRESETREQS Position */ +#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /*!< SCB AIRCR: SYSRESETREQS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEPS_Pos 3U /*!< SCB SCR: SLEEPDEEPS Position */ +#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /*!< SCB SCR: SLEEPDEEPS Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: BP Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: BP Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: IC Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: IC Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: DC Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: DC Mask */ + +#define SCB_CCR_STKOFHFNMIGN_Pos 10U /*!< SCB CCR: STKOFHFNMIGN Position */ +#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /*!< SCB CCR: STKOFHFNMIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /*!< SCB SHCSR: HARDFAULTPENDED Position */ +#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /*!< SCB SHCSR: HARDFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTPENDED_Pos 20U /*!< SCB SHCSR: SECUREFAULTPENDED Position */ +#define SCB_SHCSR_SECUREFAULTPENDED_Msk (1UL << SCB_SHCSR_SECUREFAULTPENDED_Pos) /*!< SCB SHCSR: SECUREFAULTPENDED Mask */ + +#define SCB_SHCSR_SECUREFAULTENA_Pos 19U /*!< SCB SHCSR: SECUREFAULTENA Position */ +#define SCB_SHCSR_SECUREFAULTENA_Msk (1UL << SCB_SHCSR_SECUREFAULTENA_Pos) /*!< SCB SHCSR: SECUREFAULTENA Mask */ + +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_NMIACT_Pos 5U /*!< SCB SHCSR: NMIACT Position */ +#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /*!< SCB SHCSR: NMIACT Mask */ + +#define SCB_SHCSR_SECUREFAULTACT_Pos 4U /*!< SCB SHCSR: SECUREFAULTACT Position */ +#define SCB_SHCSR_SECUREFAULTACT_Msk (1UL << SCB_SHCSR_SECUREFAULTACT_Pos) /*!< SCB SHCSR: SECUREFAULTACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_HARDFAULTACT_Pos 2U /*!< SCB SHCSR: HARDFAULTACT Position */ +#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /*!< SCB SHCSR: HARDFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_STKOF_Pos (SCB_CFSR_USGFAULTSR_Pos + 4U) /*!< SCB CFSR (UFSR): STKOF Position */ +#define SCB_CFSR_STKOF_Msk (1UL << SCB_CFSR_STKOF_Pos) /*!< SCB CFSR (UFSR): STKOF Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Non-Secure Access Control Register Definitions */ +#define SCB_NSACR_CP11_Pos 11U /*!< SCB NSACR: CP11 Position */ +#define SCB_NSACR_CP11_Msk (1UL << SCB_NSACR_CP11_Pos) /*!< SCB NSACR: CP11 Mask */ + +#define SCB_NSACR_CP10_Pos 10U /*!< SCB NSACR: CP10 Position */ +#define SCB_NSACR_CP10_Msk (1UL << SCB_NSACR_CP10_Pos) /*!< SCB NSACR: CP10 Mask */ + +#define SCB_NSACR_CPn_Pos 0U /*!< SCB NSACR: CPn Position */ +#define SCB_NSACR_CPn_Msk (1UL /*<< SCB_NSACR_CPn_Pos*/) /*!< SCB NSACR: CPn Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ + __IOM uint32_t CPPWR; /*!< Offset: 0x00C (R/W) Coprocessor Power Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) ITM Device Architecture Register */ + uint32_t RESERVED6[4U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Stimulus Port Register Definitions */ +#define ITM_STIM_DISABLED_Pos 1U /*!< ITM STIM: DISABLED Position */ +#define ITM_STIM_DISABLED_Msk (0x1UL << ITM_STIM_DISABLED_Pos) /*!< ITM STIM: DISABLED Mask */ + +#define ITM_STIM_FIFOREADY_Pos 0U /*!< ITM STIM: FIFOREADY Position */ +#define ITM_STIM_FIFOREADY_Msk (0x1UL /*<< ITM_STIM_FIFOREADY_Pos*/) /*!< ITM STIM: FIFOREADY Mask */ + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TRACEBUSID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TRACEBUSID_Msk (0x7FUL << ITM_TCR_TRACEBUSID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPRESCALE_Pos 8U /*!< ITM TCR: TSPRESCALE Position */ +#define ITM_TCR_TSPRESCALE_Msk (3UL << ITM_TCR_TSPRESCALE_Pos) /*!< ITM TCR: TSPRESCALE Mask */ + +#define ITM_TCR_STALLENA_Pos 5U /*!< ITM TCR: STALLENA Position */ +#define ITM_TCR_STALLENA_Msk (1UL << ITM_TCR_STALLENA_Pos) /*!< ITM TCR: STALLENA Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + uint32_t RESERVED3[1U]; + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED4[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + uint32_t RESERVED5[1U]; + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED6[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + uint32_t RESERVED7[1U]; + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED8[1U]; + __IOM uint32_t COMP4; /*!< Offset: 0x060 (R/W) Comparator Register 4 */ + uint32_t RESERVED9[1U]; + __IOM uint32_t FUNCTION4; /*!< Offset: 0x068 (R/W) Function Register 4 */ + uint32_t RESERVED10[1U]; + __IOM uint32_t COMP5; /*!< Offset: 0x070 (R/W) Comparator Register 5 */ + uint32_t RESERVED11[1U]; + __IOM uint32_t FUNCTION5; /*!< Offset: 0x078 (R/W) Function Register 5 */ + uint32_t RESERVED12[1U]; + __IOM uint32_t COMP6; /*!< Offset: 0x080 (R/W) Comparator Register 6 */ + uint32_t RESERVED13[1U]; + __IOM uint32_t FUNCTION6; /*!< Offset: 0x088 (R/W) Function Register 6 */ + uint32_t RESERVED14[1U]; + __IOM uint32_t COMP7; /*!< Offset: 0x090 (R/W) Comparator Register 7 */ + uint32_t RESERVED15[1U]; + __IOM uint32_t FUNCTION7; /*!< Offset: 0x098 (R/W) Function Register 7 */ + uint32_t RESERVED16[1U]; + __IOM uint32_t COMP8; /*!< Offset: 0x0A0 (R/W) Comparator Register 8 */ + uint32_t RESERVED17[1U]; + __IOM uint32_t FUNCTION8; /*!< Offset: 0x0A8 (R/W) Function Register 8 */ + uint32_t RESERVED18[1U]; + __IOM uint32_t COMP9; /*!< Offset: 0x0B0 (R/W) Comparator Register 9 */ + uint32_t RESERVED19[1U]; + __IOM uint32_t FUNCTION9; /*!< Offset: 0x0B8 (R/W) Function Register 9 */ + uint32_t RESERVED20[1U]; + __IOM uint32_t COMP10; /*!< Offset: 0x0C0 (R/W) Comparator Register 10 */ + uint32_t RESERVED21[1U]; + __IOM uint32_t FUNCTION10; /*!< Offset: 0x0C8 (R/W) Function Register 10 */ + uint32_t RESERVED22[1U]; + __IOM uint32_t COMP11; /*!< Offset: 0x0D0 (R/W) Comparator Register 11 */ + uint32_t RESERVED23[1U]; + __IOM uint32_t FUNCTION11; /*!< Offset: 0x0D8 (R/W) Function Register 11 */ + uint32_t RESERVED24[1U]; + __IOM uint32_t COMP12; /*!< Offset: 0x0E0 (R/W) Comparator Register 12 */ + uint32_t RESERVED25[1U]; + __IOM uint32_t FUNCTION12; /*!< Offset: 0x0E8 (R/W) Function Register 12 */ + uint32_t RESERVED26[1U]; + __IOM uint32_t COMP13; /*!< Offset: 0x0F0 (R/W) Comparator Register 13 */ + uint32_t RESERVED27[1U]; + __IOM uint32_t FUNCTION13; /*!< Offset: 0x0F8 (R/W) Function Register 13 */ + uint32_t RESERVED28[1U]; + __IOM uint32_t COMP14; /*!< Offset: 0x100 (R/W) Comparator Register 14 */ + uint32_t RESERVED29[1U]; + __IOM uint32_t FUNCTION14; /*!< Offset: 0x108 (R/W) Function Register 14 */ + uint32_t RESERVED30[1U]; + __IOM uint32_t COMP15; /*!< Offset: 0x110 (R/W) Comparator Register 15 */ + uint32_t RESERVED31[1U]; + __IOM uint32_t FUNCTION15; /*!< Offset: 0x118 (R/W) Function Register 15 */ + uint32_t RESERVED32[934U]; + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ + uint32_t RESERVED33[1U]; + __IM uint32_t DEVARCH; /*!< Offset: 0xFBC (R/ ) Device Architecture Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCDISS_Pos 23U /*!< DWT CTRL: CYCDISS Position */ +#define DWT_CTRL_CYCDISS_Msk (0x1UL << DWT_CTRL_CYCDISS_Pos) /*!< DWT CTRL: CYCDISS Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_ID_Pos 27U /*!< DWT FUNCTION: ID Position */ +#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /*!< DWT FUNCTION: ID Mask */ + +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_ACTION_Pos 4U /*!< DWT FUNCTION: ACTION Position */ +#define DWT_FUNCTION_ACTION_Msk (0x1UL << DWT_FUNCTION_ACTION_Pos) /*!< DWT FUNCTION: ACTION Mask */ + +#define DWT_FUNCTION_MATCH_Pos 0U /*!< DWT FUNCTION: MATCH Position */ +#define DWT_FUNCTION_MATCH_Msk (0xFUL /*<< DWT_FUNCTION_MATCH_Pos*/) /*!< DWT FUNCTION: MATCH Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IOM uint32_t PSCR; /*!< Offset: 0x308 (R/W) Periodic Synchronization Control Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t ITFTTD0; /*!< Offset: 0xEEC (R/ ) Integration Test FIFO Test Data 0 Register */ + __IOM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/W) Integration Test ATB Control Register 2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) Integration Test ATB Control Register 0 */ + __IM uint32_t ITFTTD1; /*!< Offset: 0xEFC (R/ ) Integration Test FIFO Test Data 1 Register */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) Device Configuration Register */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) Device Type Identifier Register */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_FOnMan_Pos 6U /*!< TPI FFCR: FOnMan Position */ +#define TPI_FFCR_FOnMan_Msk (0x1UL << TPI_FFCR_FOnMan_Pos) /*!< TPI FFCR: FOnMan Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration Test FIFO Test Data 0 Register Definitions */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD0: ATB Interface 2 ATVALIDPosition */ +#define TPI_ITFTTD0_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD0: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD0_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD0_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD0: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD0_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD0: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD0_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD0_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD0: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data2_Pos 16U /*!< TPI ITFTTD0: ATB Interface 1 data2 Position */ +#define TPI_ITFTTD0_ATB_IF1_data2_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data2 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data1_Pos 8U /*!< TPI ITFTTD0: ATB Interface 1 data1 Position */ +#define TPI_ITFTTD0_ATB_IF1_data1_Msk (0xFFUL << TPI_ITFTTD0_ATB_IF1_data1_Pos) /*!< TPI ITFTTD0: ATB Interface 1 data1 Mask */ + +#define TPI_ITFTTD0_ATB_IF1_data0_Pos 0U /*!< TPI ITFTTD0: ATB Interface 1 data0 Position */ +#define TPI_ITFTTD0_ATB_IF1_data0_Msk (0xFFUL /*<< TPI_ITFTTD0_ATB_IF1_data0_Pos*/) /*!< TPI ITFTTD0: ATB Interface 1 data0 Mask */ + +/* TPI Integration Test ATB Control Register 2 Register Definitions */ +#define TPI_ITATBCTR2_AFVALID2S_Pos 1U /*!< TPI ITATBCTR2: AFVALID2S Position */ +#define TPI_ITATBCTR2_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID2S_Pos) /*!< TPI ITATBCTR2: AFVALID2SS Mask */ + +#define TPI_ITATBCTR2_AFVALID1S_Pos 1U /*!< TPI ITATBCTR2: AFVALID1S Position */ +#define TPI_ITATBCTR2_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR2_AFVALID1S_Pos) /*!< TPI ITATBCTR2: AFVALID1SS Mask */ + +#define TPI_ITATBCTR2_ATREADY2S_Pos 0U /*!< TPI ITATBCTR2: ATREADY2S Position */ +#define TPI_ITATBCTR2_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2S_Pos*/) /*!< TPI ITATBCTR2: ATREADY2S Mask */ + +#define TPI_ITATBCTR2_ATREADY1S_Pos 0U /*!< TPI ITATBCTR2: ATREADY1S Position */ +#define TPI_ITATBCTR2_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1S_Pos*/) /*!< TPI ITATBCTR2: ATREADY1S Mask */ + +/* TPI Integration Test FIFO Test Data 1 Register Definitions */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Pos 29U /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF2_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 2 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF2_bytecount_Pos 27U /*!< TPI ITFTTD1: ATB Interface 2 byte count Position */ +#define TPI_ITFTTD1_ATB_IF2_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF2_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 2 byte count Mask */ + +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Pos 26U /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Position */ +#define TPI_ITFTTD1_ATB_IF1_ATVALID_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_ATVALID_Pos) /*!< TPI ITFTTD1: ATB Interface 1 ATVALID Mask */ + +#define TPI_ITFTTD1_ATB_IF1_bytecount_Pos 24U /*!< TPI ITFTTD1: ATB Interface 1 byte count Position */ +#define TPI_ITFTTD1_ATB_IF1_bytecount_Msk (0x3UL << TPI_ITFTTD1_ATB_IF1_bytecount_Pos) /*!< TPI ITFTTD1: ATB Interface 1 byte countt Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data2_Pos 16U /*!< TPI ITFTTD1: ATB Interface 2 data2 Position */ +#define TPI_ITFTTD1_ATB_IF2_data2_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data2 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data1_Pos 8U /*!< TPI ITFTTD1: ATB Interface 2 data1 Position */ +#define TPI_ITFTTD1_ATB_IF2_data1_Msk (0xFFUL << TPI_ITFTTD1_ATB_IF2_data1_Pos) /*!< TPI ITFTTD1: ATB Interface 2 data1 Mask */ + +#define TPI_ITFTTD1_ATB_IF2_data0_Pos 0U /*!< TPI ITFTTD1: ATB Interface 2 data0 Position */ +#define TPI_ITFTTD1_ATB_IF2_data0_Msk (0xFFUL /*<< TPI_ITFTTD1_ATB_IF2_data0_Pos*/) /*!< TPI ITFTTD1: ATB Interface 2 data0 Mask */ + +/* TPI Integration Test ATB Control Register 0 Definitions */ +#define TPI_ITATBCTR0_AFVALID2S_Pos 1U /*!< TPI ITATBCTR0: AFVALID2S Position */ +#define TPI_ITATBCTR0_AFVALID2S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID2S_Pos) /*!< TPI ITATBCTR0: AFVALID2SS Mask */ + +#define TPI_ITATBCTR0_AFVALID1S_Pos 1U /*!< TPI ITATBCTR0: AFVALID1S Position */ +#define TPI_ITATBCTR0_AFVALID1S_Msk (0x1UL << TPI_ITATBCTR0_AFVALID1S_Pos) /*!< TPI ITATBCTR0: AFVALID1SS Mask */ + +#define TPI_ITATBCTR0_ATREADY2S_Pos 0U /*!< TPI ITATBCTR0: ATREADY2S Position */ +#define TPI_ITATBCTR0_ATREADY2S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2S_Pos*/) /*!< TPI ITATBCTR0: ATREADY2S Mask */ + +#define TPI_ITATBCTR0_ATREADY1S_Pos 0U /*!< TPI ITATBCTR0: ATREADY1S Position */ +#define TPI_ITATBCTR0_ATREADY1S_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1S_Pos*/) /*!< TPI ITATBCTR0: ATREADY1S Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_FIFOSZ_Pos 6U /*!< TPI DEVID: FIFOSZ Position */ +#define TPI_DEVID_FIFOSZ_Msk (0x7UL << TPI_DEVID_FIFOSZ_Pos) /*!< TPI DEVID: FIFOSZ Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x3FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) MPU Region Limit Address Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Region Base Address Register Alias 1 */ + __IOM uint32_t RLAR_A1; /*!< Offset: 0x018 (R/W) MPU Region Limit Address Register Alias 1 */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Region Base Address Register Alias 2 */ + __IOM uint32_t RLAR_A2; /*!< Offset: 0x020 (R/W) MPU Region Limit Address Register Alias 2 */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Region Base Address Register Alias 3 */ + __IOM uint32_t RLAR_A3; /*!< Offset: 0x028 (R/W) MPU Region Limit Address Register Alias 3 */ + uint32_t RESERVED0[1]; + union { + __IOM uint32_t MAIR[2]; + struct { + __IOM uint32_t MAIR0; /*!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 */ + __IOM uint32_t MAIR1; /*!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 */ + }; + }; +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_BASE_Pos 5U /*!< MPU RBAR: BASE Position */ +#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /*!< MPU RBAR: BASE Mask */ + +#define MPU_RBAR_SH_Pos 3U /*!< MPU RBAR: SH Position */ +#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /*!< MPU RBAR: SH Mask */ + +#define MPU_RBAR_AP_Pos 1U /*!< MPU RBAR: AP Position */ +#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /*!< MPU RBAR: AP Mask */ + +#define MPU_RBAR_XN_Pos 0U /*!< MPU RBAR: XN Position */ +#define MPU_RBAR_XN_Msk (01UL /*<< MPU_RBAR_XN_Pos*/) /*!< MPU RBAR: XN Mask */ + +/* MPU Region Limit Address Register Definitions */ +#define MPU_RLAR_LIMIT_Pos 5U /*!< MPU RLAR: LIMIT Position */ +#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /*!< MPU RLAR: LIMIT Mask */ + +#define MPU_RLAR_AttrIndx_Pos 1U /*!< MPU RLAR: AttrIndx Position */ +#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /*!< MPU RLAR: AttrIndx Mask */ + +#define MPU_RLAR_EN_Pos 0U /*!< MPU RLAR: Region enable bit Position */ +#define MPU_RLAR_EN_Msk (1UL /*<< MPU_RLAR_EN_Pos*/) /*!< MPU RLAR: Region enable bit Disable Mask */ + +/* MPU Memory Attribute Indirection Register 0 Definitions */ +#define MPU_MAIR0_Attr3_Pos 24U /*!< MPU MAIR0: Attr3 Position */ +#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /*!< MPU MAIR0: Attr3 Mask */ + +#define MPU_MAIR0_Attr2_Pos 16U /*!< MPU MAIR0: Attr2 Position */ +#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /*!< MPU MAIR0: Attr2 Mask */ + +#define MPU_MAIR0_Attr1_Pos 8U /*!< MPU MAIR0: Attr1 Position */ +#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /*!< MPU MAIR0: Attr1 Mask */ + +#define MPU_MAIR0_Attr0_Pos 0U /*!< MPU MAIR0: Attr0 Position */ +#define MPU_MAIR0_Attr0_Msk (0xFFUL /*<< MPU_MAIR0_Attr0_Pos*/) /*!< MPU MAIR0: Attr0 Mask */ + +/* MPU Memory Attribute Indirection Register 1 Definitions */ +#define MPU_MAIR1_Attr7_Pos 24U /*!< MPU MAIR1: Attr7 Position */ +#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /*!< MPU MAIR1: Attr7 Mask */ + +#define MPU_MAIR1_Attr6_Pos 16U /*!< MPU MAIR1: Attr6 Position */ +#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /*!< MPU MAIR1: Attr6 Mask */ + +#define MPU_MAIR1_Attr5_Pos 8U /*!< MPU MAIR1: Attr5 Position */ +#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /*!< MPU MAIR1: Attr5 Mask */ + +#define MPU_MAIR1_Attr4_Pos 0U /*!< MPU MAIR1: Attr4 Position */ +#define MPU_MAIR1_Attr4_Msk (0xFFUL /*<< MPU_MAIR1_Attr4_Pos*/) /*!< MPU MAIR1: Attr4 Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SAU Security Attribution Unit (SAU) + \brief Type definitions for the Security Attribution Unit (SAU) + @{ + */ + +/** + \brief Structure type to access the Security Attribution Unit (SAU). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SAU Control Register */ + __IM uint32_t TYPE; /*!< Offset: 0x004 (R/ ) SAU Type Register */ +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) SAU Region Number Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) SAU Region Base Address Register */ + __IOM uint32_t RLAR; /*!< Offset: 0x010 (R/W) SAU Region Limit Address Register */ +#else + uint32_t RESERVED0[3]; +#endif + __IOM uint32_t SFSR; /*!< Offset: 0x014 (R/W) Secure Fault Status Register */ + __IOM uint32_t SFAR; /*!< Offset: 0x018 (R/W) Secure Fault Address Register */ +} SAU_Type; + +/* SAU Control Register Definitions */ +#define SAU_CTRL_ALLNS_Pos 1U /*!< SAU CTRL: ALLNS Position */ +#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /*!< SAU CTRL: ALLNS Mask */ + +#define SAU_CTRL_ENABLE_Pos 0U /*!< SAU CTRL: ENABLE Position */ +#define SAU_CTRL_ENABLE_Msk (1UL /*<< SAU_CTRL_ENABLE_Pos*/) /*!< SAU CTRL: ENABLE Mask */ + +/* SAU Type Register Definitions */ +#define SAU_TYPE_SREGION_Pos 0U /*!< SAU TYPE: SREGION Position */ +#define SAU_TYPE_SREGION_Msk (0xFFUL /*<< SAU_TYPE_SREGION_Pos*/) /*!< SAU TYPE: SREGION Mask */ + +#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) +/* SAU Region Number Register Definitions */ +#define SAU_RNR_REGION_Pos 0U /*!< SAU RNR: REGION Position */ +#define SAU_RNR_REGION_Msk (0xFFUL /*<< SAU_RNR_REGION_Pos*/) /*!< SAU RNR: REGION Mask */ + +/* SAU Region Base Address Register Definitions */ +#define SAU_RBAR_BADDR_Pos 5U /*!< SAU RBAR: BADDR Position */ +#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /*!< SAU RBAR: BADDR Mask */ + +/* SAU Region Limit Address Register Definitions */ +#define SAU_RLAR_LADDR_Pos 5U /*!< SAU RLAR: LADDR Position */ +#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /*!< SAU RLAR: LADDR Mask */ + +#define SAU_RLAR_NSC_Pos 1U /*!< SAU RLAR: NSC Position */ +#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /*!< SAU RLAR: NSC Mask */ + +#define SAU_RLAR_ENABLE_Pos 0U /*!< SAU RLAR: ENABLE Position */ +#define SAU_RLAR_ENABLE_Msk (1UL /*<< SAU_RLAR_ENABLE_Pos*/) /*!< SAU RLAR: ENABLE Mask */ + +#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */ + +/* Secure Fault Status Register Definitions */ +#define SAU_SFSR_LSERR_Pos 7U /*!< SAU SFSR: LSERR Position */ +#define SAU_SFSR_LSERR_Msk (1UL << SAU_SFSR_LSERR_Pos) /*!< SAU SFSR: LSERR Mask */ + +#define SAU_SFSR_SFARVALID_Pos 6U /*!< SAU SFSR: SFARVALID Position */ +#define SAU_SFSR_SFARVALID_Msk (1UL << SAU_SFSR_SFARVALID_Pos) /*!< SAU SFSR: SFARVALID Mask */ + +#define SAU_SFSR_LSPERR_Pos 5U /*!< SAU SFSR: LSPERR Position */ +#define SAU_SFSR_LSPERR_Msk (1UL << SAU_SFSR_LSPERR_Pos) /*!< SAU SFSR: LSPERR Mask */ + +#define SAU_SFSR_INVTRAN_Pos 4U /*!< SAU SFSR: INVTRAN Position */ +#define SAU_SFSR_INVTRAN_Msk (1UL << SAU_SFSR_INVTRAN_Pos) /*!< SAU SFSR: INVTRAN Mask */ + +#define SAU_SFSR_AUVIOL_Pos 3U /*!< SAU SFSR: AUVIOL Position */ +#define SAU_SFSR_AUVIOL_Msk (1UL << SAU_SFSR_AUVIOL_Pos) /*!< SAU SFSR: AUVIOL Mask */ + +#define SAU_SFSR_INVER_Pos 2U /*!< SAU SFSR: INVER Position */ +#define SAU_SFSR_INVER_Msk (1UL << SAU_SFSR_INVER_Pos) /*!< SAU SFSR: INVER Mask */ + +#define SAU_SFSR_INVIS_Pos 1U /*!< SAU SFSR: INVIS Position */ +#define SAU_SFSR_INVIS_Msk (1UL << SAU_SFSR_INVIS_Pos) /*!< SAU SFSR: INVIS Mask */ + +#define SAU_SFSR_INVEP_Pos 0U /*!< SAU SFSR: INVEP Position */ +#define SAU_SFSR_INVEP_Msk (1UL /*<< SAU_SFSR_INVEP_Pos*/) /*!< SAU SFSR: INVEP Mask */ + +/*@} end of group CMSIS_SAU */ +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_LSPENS_Pos 29U /*!< FPCCR: LSPENS Position */ +#define FPU_FPCCR_LSPENS_Msk (1UL << FPU_FPCCR_LSPENS_Pos) /*!< FPCCR: LSPENS bit Mask */ + +#define FPU_FPCCR_CLRONRET_Pos 28U /*!< FPCCR: CLRONRET Position */ +#define FPU_FPCCR_CLRONRET_Msk (1UL << FPU_FPCCR_CLRONRET_Pos) /*!< FPCCR: CLRONRET bit Mask */ + +#define FPU_FPCCR_CLRONRETS_Pos 27U /*!< FPCCR: CLRONRETS Position */ +#define FPU_FPCCR_CLRONRETS_Msk (1UL << FPU_FPCCR_CLRONRETS_Pos) /*!< FPCCR: CLRONRETS bit Mask */ + +#define FPU_FPCCR_TS_Pos 26U /*!< FPCCR: TS Position */ +#define FPU_FPCCR_TS_Msk (1UL << FPU_FPCCR_TS_Pos) /*!< FPCCR: TS bit Mask */ + +#define FPU_FPCCR_UFRDY_Pos 10U /*!< FPCCR: UFRDY Position */ +#define FPU_FPCCR_UFRDY_Msk (1UL << FPU_FPCCR_UFRDY_Pos) /*!< FPCCR: UFRDY bit Mask */ + +#define FPU_FPCCR_SPLIMVIOL_Pos 9U /*!< FPCCR: SPLIMVIOL Position */ +#define FPU_FPCCR_SPLIMVIOL_Msk (1UL << FPU_FPCCR_SPLIMVIOL_Pos) /*!< FPCCR: SPLIMVIOL bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_SFRDY_Pos 7U /*!< FPCCR: SFRDY Position */ +#define FPU_FPCCR_SFRDY_Msk (1UL << FPU_FPCCR_SFRDY_Pos) /*!< FPCCR: SFRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_S_Pos 2U /*!< FPCCR: Security status of the FP context bit Position */ +#define FPU_FPCCR_S_Msk (1UL << FPU_FPCCR_S_Pos) /*!< FPCCR: Security status of the FP context bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ + uint32_t RESERVED4[1U]; + __IOM uint32_t DAUTHCTRL; /*!< Offset: 0x014 (R/W) Debug Authentication Control Register */ + __IOM uint32_t DSCSR; /*!< Offset: 0x018 (R/W) Debug Security Control and Status Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /*!< CoreDebug DHCSR: S_RESTART_ST Position */ +#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /*!< CoreDebug DHCSR: S_RESTART_ST Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/* Debug Authentication Control Register Definitions */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position */ +#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask */ + +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /*!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask */ + +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /*!< CoreDebug DAUTHCTRL: INTSPIDEN Position */ +#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /*!< CoreDebug DAUTHCTRL: INTSPIDEN Mask */ + +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /*!< CoreDebug DAUTHCTRL: SPIDENSEL Position */ +#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /*<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos*/) /*!< CoreDebug DAUTHCTRL: SPIDENSEL Mask */ + +/* Debug Security Control and Status Register Definitions */ +#define CoreDebug_DSCSR_CDS_Pos 16U /*!< CoreDebug DSCSR: CDS Position */ +#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /*!< CoreDebug DSCSR: CDS Mask */ + +#define CoreDebug_DSCSR_SBRSEL_Pos 1U /*!< CoreDebug DSCSR: SBRSEL Position */ +#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /*!< CoreDebug DSCSR: SBRSEL Mask */ + +#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /*!< CoreDebug DSCSR: SBRSELEN Position */ +#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /*<< CoreDebug_DSCSR_SBRSELEN_Pos*/) /*!< CoreDebug DSCSR: SBRSELEN Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ + #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ + #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ + #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ + #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ + #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ + #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ + #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ + #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + + #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ + #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ + #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ + #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ + #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ + #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ + #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE ) /*!< Core Debug configuration struct */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ + #endif + + #if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SAU_BASE (SCS_BASE + 0x0DD0UL) /*!< Security Attribution Unit */ + #define SAU ((SAU_Type *) SAU_BASE ) /*!< Security Attribution Unit */ + #endif + + #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ + #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + #define SCS_BASE_NS (0xE002E000UL) /*!< System Control Space Base Address (non-secure address space) */ + #define CoreDebug_BASE_NS (0xE002EDF0UL) /*!< Core Debug Base Address (non-secure address space) */ + #define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /*!< SysTick Base Address (non-secure address space) */ + #define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /*!< NVIC Base Address (non-secure address space) */ + #define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /*!< System Control Block Base Address (non-secure address space) */ + + #define SCnSCB_NS ((SCnSCB_Type *) SCS_BASE_NS ) /*!< System control Register not in SCB(non-secure address space) */ + #define SCB_NS ((SCB_Type *) SCB_BASE_NS ) /*!< SCB configuration struct (non-secure address space) */ + #define SysTick_NS ((SysTick_Type *) SysTick_BASE_NS ) /*!< SysTick configuration struct (non-secure address space) */ + #define NVIC_NS ((NVIC_Type *) NVIC_BASE_NS ) /*!< NVIC configuration struct (non-secure address space) */ + #define CoreDebug_NS ((CoreDebug_Type *) CoreDebug_BASE_NS) /*!< Core Debug configuration struct (non-secure address space) */ + + #if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /*!< Memory Protection Unit (non-secure address space) */ + #define MPU_NS ((MPU_Type *) MPU_BASE_NS ) /*!< Memory Protection Unit (non-secure address space) */ + #endif + + #define FPU_BASE_NS (SCS_BASE_NS + 0x0F30UL) /*!< Floating Point Unit (non-secure address space) */ + #define FPU_NS ((FPU_Type *) FPU_BASE_NS ) /*!< Floating Point Unit (non-secure address space) */ + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* Special LR values for Secure/Non-Secure call handling and exception handling */ + +/* Function Return Payload (from ARMv8-M Architecture Reference Manual) LR value on entry from Secure BLXNS */ +#define FNC_RETURN (0xFEFFFFFFUL) /* bit [0] ignored when processing a branch */ + +/* The following EXC_RETURN mask values are used to evaluate the LR on exception entry */ +#define EXC_RETURN_PREFIX (0xFF000000UL) /* bits [31:24] set to indicate an EXC_RETURN value */ +#define EXC_RETURN_S (0x00000040UL) /* bit [6] stack used to push registers: 0=Non-secure 1=Secure */ +#define EXC_RETURN_DCRS (0x00000020UL) /* bit [5] stacking rules for called registers: 0=skipped 1=saved */ +#define EXC_RETURN_FTYPE (0x00000010UL) /* bit [4] allocate stack for floating-point context: 0=done 1=skipped */ +#define EXC_RETURN_MODE (0x00000008UL) /* bit [3] processor mode for return: 0=Handler mode 1=Thread mode */ +#define EXC_RETURN_SPSEL (0x00000004UL) /* bit [2] stack pointer used to restore context: 0=MSP 1=PSP */ +#define EXC_RETURN_ES (0x00000001UL) /* bit [0] security state exception was taken to: 0=Non-secure 1=Secure */ + +/* Integrity Signature (from ARMv8-M Architecture Reference Manual) for exception context stacking */ +#if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) /* Value for processors with floating-point extension: */ +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125AUL) /* bit [0] SFTC must match LR bit[4] EXC_RETURN_FTYPE */ +#else +#define EXC_INTEGRITY_SIGNATURE (0xFEFA125BUL) /* Value for processors without floating-point extension */ +#endif + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Get Interrupt Target State + \details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + \return 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Target State + \details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] |= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Clear Interrupt Target State + \details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 if interrupt is assigned to Secure + 1 if interrupt is assigned to Non Secure + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL))); + return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief Set Priority Grouping (non-secure) + \details Sets the non-secure priority grouping field when in secure state using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void TZ_NVIC_SetPriorityGrouping_NS(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB_NS->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB_NS->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping (non-secure) + \details Reads the priority grouping field from the non-secure NVIC when in secure state. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriorityGrouping_NS(void) +{ + return ((uint32_t)((SCB_NS->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt (non-secure) + \details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Interrupt Enable status (non-secure) + \details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt (non-secure) + \details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Pending Interrupt (non-secure) + \details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt (non-secure) + \details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt (non-secure) + \details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt (non-secure) + \details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority (non-secure) + \details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every non-secure processor exception. + */ +__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC_NS->IPR[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority (non-secure) + \details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC_NS->IPR[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB_NS->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} +#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_NVICFunctions */ + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv8.h" + +#endif + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## SAU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SAUFunctions SAU Functions + \brief Functions that configure the SAU. + @{ + */ + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) + +/** + \brief Enable SAU + \details Enables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Enable(void) +{ + SAU->CTRL |= (SAU_CTRL_ENABLE_Msk); +} + + + +/** + \brief Disable SAU + \details Disables the Security Attribution Unit (SAU). + */ +__STATIC_INLINE void TZ_SAU_Disable(void) +{ + SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk); +} + +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +/*@} end of CMSIS_Core_SAUFunctions */ + + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) +/** + \brief System Tick Configuration (non-secure) + \details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function TZ_SysTick_Config_NS is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + + */ +__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} +#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */ + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM35P_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm4.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm4.h new file mode 100644 index 0000000000000000000000000000000000000000..12c023b8017d9f712b2bdad1f27a0308310e14ba --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm4.h @@ -0,0 +1,2124 @@ +/**************************************************************************//** + * @file core_cm4.h + * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File + * @version V5.1.0 + * @date 13. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM4_H_GENERIC +#define __CORE_CM4_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M4 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM4 definitions */ +#define __CM4_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM4_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16U) | \ + __CM4_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (4U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM4_H_DEPENDANT +#define __CORE_CM4_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM4_REV + #define __CM4_REV 0x0000U + #warning "__CM4_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M4 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISOOFP_Pos 9U /*!< ACTLR: DISOOFP Position */ +#define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */ + +#define SCnSCB_ACTLR_DISFPCA_Pos 8U /*!< ACTLR: DISFPCA Position */ +#define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M4 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = FPU->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM4_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm7.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm7.h new file mode 100644 index 0000000000000000000000000000000000000000..c4515d8fa3196e587d820b521c27c30c580010c3 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_cm7.h @@ -0,0 +1,2725 @@ +/**************************************************************************//** + * @file core_cm7.h + * @brief CMSIS Cortex-M7 Core Peripheral Access Layer Header File + * @version V5.1.1 + * @date 28. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_CM7_H_GENERIC +#define __CORE_CM7_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup Cortex_M7 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS CM7 definitions */ +#define __CM7_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __CM7_CMSIS_VERSION_SUB ( __CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __CM7_CMSIS_VERSION ((__CM7_CMSIS_VERSION_MAIN << 16U) | \ + __CM7_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_M (7U) /*!< Cortex-M Core */ + +/** __FPU_USED indicates whether an FPU is used or not. + For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions. +*/ +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #if defined (__FPU_PRESENT) && (__FPU_PRESENT == 1U) + #define __FPU_USED 1U + #else + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #define __FPU_USED 0U + #endif + #else + #define __FPU_USED 0U + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_CM7_H_DEPENDANT +#define __CORE_CM7_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __CM7_REV + #define __CM7_REV 0x0000U + #warning "__CM7_REV not defined in device header file; using default!" + #endif + + #ifndef __FPU_PRESENT + #define __FPU_PRESENT 0U + #warning "__FPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __ICACHE_PRESENT + #define __ICACHE_PRESENT 0U + #warning "__ICACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DCACHE_PRESENT + #define __DCACHE_PRESENT 0U + #warning "__DCACHE_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __DTCM_PRESENT + #define __DTCM_PRESENT 0U + #warning "__DTCM_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group Cortex_M7 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + - Core FPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + +#define APSR_GE_Pos 16U /*!< APSR: GE Position */ +#define APSR_GE_Msk (0xFUL << APSR_GE_Pos) /*!< APSR: GE Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */ + uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_GE_Pos 16U /*!< xPSR: GE Position */ +#define xPSR_GE_Msk (0xFUL << xPSR_GE_Pos) /*!< xPSR: GE Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */ + uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_FPCA_Pos 2U /*!< CONTROL: FPCA Position */ +#define CONTROL_FPCA_Msk (1UL << CONTROL_FPCA_Pos) /*!< CONTROL: FPCA Mask */ + +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHPR[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t ID_PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t ID_DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ID_AFR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t ID_MFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ID_ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[1U]; + __IM uint32_t CLIDR; /*!< Offset: 0x078 (R/ ) Cache Level ID register */ + __IM uint32_t CTR; /*!< Offset: 0x07C (R/ ) Cache Type register */ + __IM uint32_t CCSIDR; /*!< Offset: 0x080 (R/ ) Cache Size ID Register */ + __IOM uint32_t CSSELR; /*!< Offset: 0x084 (R/W) Cache Size Selection Register */ + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED3[93U]; + __OM uint32_t STIR; /*!< Offset: 0x200 ( /W) Software Triggered Interrupt Register */ + uint32_t RESERVED4[15U]; + __IM uint32_t MVFR0; /*!< Offset: 0x240 (R/ ) Media and VFP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x244 (R/ ) Media and VFP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x248 (R/ ) Media and VFP Feature Register 2 */ + uint32_t RESERVED5[1U]; + __OM uint32_t ICIALLU; /*!< Offset: 0x250 ( /W) I-Cache Invalidate All to PoU */ + uint32_t RESERVED6[1U]; + __OM uint32_t ICIMVAU; /*!< Offset: 0x258 ( /W) I-Cache Invalidate by MVA to PoU */ + __OM uint32_t DCIMVAC; /*!< Offset: 0x25C ( /W) D-Cache Invalidate by MVA to PoC */ + __OM uint32_t DCISW; /*!< Offset: 0x260 ( /W) D-Cache Invalidate by Set-way */ + __OM uint32_t DCCMVAU; /*!< Offset: 0x264 ( /W) D-Cache Clean by MVA to PoU */ + __OM uint32_t DCCMVAC; /*!< Offset: 0x268 ( /W) D-Cache Clean by MVA to PoC */ + __OM uint32_t DCCSW; /*!< Offset: 0x26C ( /W) D-Cache Clean by Set-way */ + __OM uint32_t DCCIMVAC; /*!< Offset: 0x270 ( /W) D-Cache Clean and Invalidate by MVA to PoC */ + __OM uint32_t DCCISW; /*!< Offset: 0x274 ( /W) D-Cache Clean and Invalidate by Set-way */ + uint32_t RESERVED7[6U]; + __IOM uint32_t ITCMCR; /*!< Offset: 0x290 (R/W) Instruction Tightly-Coupled Memory Control Register */ + __IOM uint32_t DTCMCR; /*!< Offset: 0x294 (R/W) Data Tightly-Coupled Memory Control Registers */ + __IOM uint32_t AHBPCR; /*!< Offset: 0x298 (R/W) AHBP Control Register */ + __IOM uint32_t CACR; /*!< Offset: 0x29C (R/W) L1 Cache Control Register */ + __IOM uint32_t AHBSCR; /*!< Offset: 0x2A0 (R/W) AHB Slave Control Register */ + uint32_t RESERVED8[1U]; + __IOM uint32_t ABFSR; /*!< Offset: 0x2A8 (R/W) Auxiliary Bus Fault Status Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_BP_Pos 18U /*!< SCB CCR: Branch prediction enable bit Position */ +#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /*!< SCB CCR: Branch prediction enable bit Mask */ + +#define SCB_CCR_IC_Pos 17U /*!< SCB CCR: Instruction cache enable bit Position */ +#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /*!< SCB CCR: Instruction cache enable bit Mask */ + +#define SCB_CCR_DC_Pos 16U /*!< SCB CCR: Cache enable bit Position */ +#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /*!< SCB CCR: Cache enable bit Mask */ + +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MLSPERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 5U) /*!< SCB CFSR (MMFSR): MLSPERR Position */ +#define SCB_CFSR_MLSPERR_Msk (1UL << SCB_CFSR_MLSPERR_Pos) /*!< SCB CFSR (MMFSR): MLSPERR Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_LSPERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 5U) /*!< SCB CFSR (BFSR): LSPERR Position */ +#define SCB_CFSR_LSPERR_Msk (1UL << SCB_CFSR_LSPERR_Pos) /*!< SCB CFSR (BFSR): LSPERR Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/* SCB Cache Level ID Register Definitions */ +#define SCB_CLIDR_LOUU_Pos 27U /*!< SCB CLIDR: LoUU Position */ +#define SCB_CLIDR_LOUU_Msk (7UL << SCB_CLIDR_LOUU_Pos) /*!< SCB CLIDR: LoUU Mask */ + +#define SCB_CLIDR_LOC_Pos 24U /*!< SCB CLIDR: LoC Position */ +#define SCB_CLIDR_LOC_Msk (7UL << SCB_CLIDR_LOC_Pos) /*!< SCB CLIDR: LoC Mask */ + +/* SCB Cache Type Register Definitions */ +#define SCB_CTR_FORMAT_Pos 29U /*!< SCB CTR: Format Position */ +#define SCB_CTR_FORMAT_Msk (7UL << SCB_CTR_FORMAT_Pos) /*!< SCB CTR: Format Mask */ + +#define SCB_CTR_CWG_Pos 24U /*!< SCB CTR: CWG Position */ +#define SCB_CTR_CWG_Msk (0xFUL << SCB_CTR_CWG_Pos) /*!< SCB CTR: CWG Mask */ + +#define SCB_CTR_ERG_Pos 20U /*!< SCB CTR: ERG Position */ +#define SCB_CTR_ERG_Msk (0xFUL << SCB_CTR_ERG_Pos) /*!< SCB CTR: ERG Mask */ + +#define SCB_CTR_DMINLINE_Pos 16U /*!< SCB CTR: DminLine Position */ +#define SCB_CTR_DMINLINE_Msk (0xFUL << SCB_CTR_DMINLINE_Pos) /*!< SCB CTR: DminLine Mask */ + +#define SCB_CTR_IMINLINE_Pos 0U /*!< SCB CTR: ImInLine Position */ +#define SCB_CTR_IMINLINE_Msk (0xFUL /*<< SCB_CTR_IMINLINE_Pos*/) /*!< SCB CTR: ImInLine Mask */ + +/* SCB Cache Size ID Register Definitions */ +#define SCB_CCSIDR_WT_Pos 31U /*!< SCB CCSIDR: WT Position */ +#define SCB_CCSIDR_WT_Msk (1UL << SCB_CCSIDR_WT_Pos) /*!< SCB CCSIDR: WT Mask */ + +#define SCB_CCSIDR_WB_Pos 30U /*!< SCB CCSIDR: WB Position */ +#define SCB_CCSIDR_WB_Msk (1UL << SCB_CCSIDR_WB_Pos) /*!< SCB CCSIDR: WB Mask */ + +#define SCB_CCSIDR_RA_Pos 29U /*!< SCB CCSIDR: RA Position */ +#define SCB_CCSIDR_RA_Msk (1UL << SCB_CCSIDR_RA_Pos) /*!< SCB CCSIDR: RA Mask */ + +#define SCB_CCSIDR_WA_Pos 28U /*!< SCB CCSIDR: WA Position */ +#define SCB_CCSIDR_WA_Msk (1UL << SCB_CCSIDR_WA_Pos) /*!< SCB CCSIDR: WA Mask */ + +#define SCB_CCSIDR_NUMSETS_Pos 13U /*!< SCB CCSIDR: NumSets Position */ +#define SCB_CCSIDR_NUMSETS_Msk (0x7FFFUL << SCB_CCSIDR_NUMSETS_Pos) /*!< SCB CCSIDR: NumSets Mask */ + +#define SCB_CCSIDR_ASSOCIATIVITY_Pos 3U /*!< SCB CCSIDR: Associativity Position */ +#define SCB_CCSIDR_ASSOCIATIVITY_Msk (0x3FFUL << SCB_CCSIDR_ASSOCIATIVITY_Pos) /*!< SCB CCSIDR: Associativity Mask */ + +#define SCB_CCSIDR_LINESIZE_Pos 0U /*!< SCB CCSIDR: LineSize Position */ +#define SCB_CCSIDR_LINESIZE_Msk (7UL /*<< SCB_CCSIDR_LINESIZE_Pos*/) /*!< SCB CCSIDR: LineSize Mask */ + +/* SCB Cache Size Selection Register Definitions */ +#define SCB_CSSELR_LEVEL_Pos 1U /*!< SCB CSSELR: Level Position */ +#define SCB_CSSELR_LEVEL_Msk (7UL << SCB_CSSELR_LEVEL_Pos) /*!< SCB CSSELR: Level Mask */ + +#define SCB_CSSELR_IND_Pos 0U /*!< SCB CSSELR: InD Position */ +#define SCB_CSSELR_IND_Msk (1UL /*<< SCB_CSSELR_IND_Pos*/) /*!< SCB CSSELR: InD Mask */ + +/* SCB Software Triggered Interrupt Register Definitions */ +#define SCB_STIR_INTID_Pos 0U /*!< SCB STIR: INTID Position */ +#define SCB_STIR_INTID_Msk (0x1FFUL /*<< SCB_STIR_INTID_Pos*/) /*!< SCB STIR: INTID Mask */ + +/* SCB D-Cache Invalidate by Set-way Register Definitions */ +#define SCB_DCISW_WAY_Pos 30U /*!< SCB DCISW: Way Position */ +#define SCB_DCISW_WAY_Msk (3UL << SCB_DCISW_WAY_Pos) /*!< SCB DCISW: Way Mask */ + +#define SCB_DCISW_SET_Pos 5U /*!< SCB DCISW: Set Position */ +#define SCB_DCISW_SET_Msk (0x1FFUL << SCB_DCISW_SET_Pos) /*!< SCB DCISW: Set Mask */ + +/* SCB D-Cache Clean by Set-way Register Definitions */ +#define SCB_DCCSW_WAY_Pos 30U /*!< SCB DCCSW: Way Position */ +#define SCB_DCCSW_WAY_Msk (3UL << SCB_DCCSW_WAY_Pos) /*!< SCB DCCSW: Way Mask */ + +#define SCB_DCCSW_SET_Pos 5U /*!< SCB DCCSW: Set Position */ +#define SCB_DCCSW_SET_Msk (0x1FFUL << SCB_DCCSW_SET_Pos) /*!< SCB DCCSW: Set Mask */ + +/* SCB D-Cache Clean and Invalidate by Set-way Register Definitions */ +#define SCB_DCCISW_WAY_Pos 30U /*!< SCB DCCISW: Way Position */ +#define SCB_DCCISW_WAY_Msk (3UL << SCB_DCCISW_WAY_Pos) /*!< SCB DCCISW: Way Mask */ + +#define SCB_DCCISW_SET_Pos 5U /*!< SCB DCCISW: Set Position */ +#define SCB_DCCISW_SET_Msk (0x1FFUL << SCB_DCCISW_SET_Pos) /*!< SCB DCCISW: Set Mask */ + +/* Instruction Tightly-Coupled Memory Control Register Definitions */ +#define SCB_ITCMCR_SZ_Pos 3U /*!< SCB ITCMCR: SZ Position */ +#define SCB_ITCMCR_SZ_Msk (0xFUL << SCB_ITCMCR_SZ_Pos) /*!< SCB ITCMCR: SZ Mask */ + +#define SCB_ITCMCR_RETEN_Pos 2U /*!< SCB ITCMCR: RETEN Position */ +#define SCB_ITCMCR_RETEN_Msk (1UL << SCB_ITCMCR_RETEN_Pos) /*!< SCB ITCMCR: RETEN Mask */ + +#define SCB_ITCMCR_RMW_Pos 1U /*!< SCB ITCMCR: RMW Position */ +#define SCB_ITCMCR_RMW_Msk (1UL << SCB_ITCMCR_RMW_Pos) /*!< SCB ITCMCR: RMW Mask */ + +#define SCB_ITCMCR_EN_Pos 0U /*!< SCB ITCMCR: EN Position */ +#define SCB_ITCMCR_EN_Msk (1UL /*<< SCB_ITCMCR_EN_Pos*/) /*!< SCB ITCMCR: EN Mask */ + +/* Data Tightly-Coupled Memory Control Register Definitions */ +#define SCB_DTCMCR_SZ_Pos 3U /*!< SCB DTCMCR: SZ Position */ +#define SCB_DTCMCR_SZ_Msk (0xFUL << SCB_DTCMCR_SZ_Pos) /*!< SCB DTCMCR: SZ Mask */ + +#define SCB_DTCMCR_RETEN_Pos 2U /*!< SCB DTCMCR: RETEN Position */ +#define SCB_DTCMCR_RETEN_Msk (1UL << SCB_DTCMCR_RETEN_Pos) /*!< SCB DTCMCR: RETEN Mask */ + +#define SCB_DTCMCR_RMW_Pos 1U /*!< SCB DTCMCR: RMW Position */ +#define SCB_DTCMCR_RMW_Msk (1UL << SCB_DTCMCR_RMW_Pos) /*!< SCB DTCMCR: RMW Mask */ + +#define SCB_DTCMCR_EN_Pos 0U /*!< SCB DTCMCR: EN Position */ +#define SCB_DTCMCR_EN_Msk (1UL /*<< SCB_DTCMCR_EN_Pos*/) /*!< SCB DTCMCR: EN Mask */ + +/* AHBP Control Register Definitions */ +#define SCB_AHBPCR_SZ_Pos 1U /*!< SCB AHBPCR: SZ Position */ +#define SCB_AHBPCR_SZ_Msk (7UL << SCB_AHBPCR_SZ_Pos) /*!< SCB AHBPCR: SZ Mask */ + +#define SCB_AHBPCR_EN_Pos 0U /*!< SCB AHBPCR: EN Position */ +#define SCB_AHBPCR_EN_Msk (1UL /*<< SCB_AHBPCR_EN_Pos*/) /*!< SCB AHBPCR: EN Mask */ + +/* L1 Cache Control Register Definitions */ +#define SCB_CACR_FORCEWT_Pos 2U /*!< SCB CACR: FORCEWT Position */ +#define SCB_CACR_FORCEWT_Msk (1UL << SCB_CACR_FORCEWT_Pos) /*!< SCB CACR: FORCEWT Mask */ + +#define SCB_CACR_ECCEN_Pos 1U /*!< SCB CACR: ECCEN Position */ +#define SCB_CACR_ECCEN_Msk (1UL << SCB_CACR_ECCEN_Pos) /*!< SCB CACR: ECCEN Mask */ + +#define SCB_CACR_SIWT_Pos 0U /*!< SCB CACR: SIWT Position */ +#define SCB_CACR_SIWT_Msk (1UL /*<< SCB_CACR_SIWT_Pos*/) /*!< SCB CACR: SIWT Mask */ + +/* AHBS Control Register Definitions */ +#define SCB_AHBSCR_INITCOUNT_Pos 11U /*!< SCB AHBSCR: INITCOUNT Position */ +#define SCB_AHBSCR_INITCOUNT_Msk (0x1FUL << SCB_AHBPCR_INITCOUNT_Pos) /*!< SCB AHBSCR: INITCOUNT Mask */ + +#define SCB_AHBSCR_TPRI_Pos 2U /*!< SCB AHBSCR: TPRI Position */ +#define SCB_AHBSCR_TPRI_Msk (0x1FFUL << SCB_AHBPCR_TPRI_Pos) /*!< SCB AHBSCR: TPRI Mask */ + +#define SCB_AHBSCR_CTL_Pos 0U /*!< SCB AHBSCR: CTL Position*/ +#define SCB_AHBSCR_CTL_Msk (3UL /*<< SCB_AHBPCR_CTL_Pos*/) /*!< SCB AHBSCR: CTL Mask */ + +/* Auxiliary Bus Fault Status Register Definitions */ +#define SCB_ABFSR_AXIMTYPE_Pos 8U /*!< SCB ABFSR: AXIMTYPE Position*/ +#define SCB_ABFSR_AXIMTYPE_Msk (3UL << SCB_ABFSR_AXIMTYPE_Pos) /*!< SCB ABFSR: AXIMTYPE Mask */ + +#define SCB_ABFSR_EPPB_Pos 4U /*!< SCB ABFSR: EPPB Position*/ +#define SCB_ABFSR_EPPB_Msk (1UL << SCB_ABFSR_EPPB_Pos) /*!< SCB ABFSR: EPPB Mask */ + +#define SCB_ABFSR_AXIM_Pos 3U /*!< SCB ABFSR: AXIM Position*/ +#define SCB_ABFSR_AXIM_Msk (1UL << SCB_ABFSR_AXIM_Pos) /*!< SCB ABFSR: AXIM Mask */ + +#define SCB_ABFSR_AHBP_Pos 2U /*!< SCB ABFSR: AHBP Position*/ +#define SCB_ABFSR_AHBP_Msk (1UL << SCB_ABFSR_AHBP_Pos) /*!< SCB ABFSR: AHBP Mask */ + +#define SCB_ABFSR_DTCM_Pos 1U /*!< SCB ABFSR: DTCM Position*/ +#define SCB_ABFSR_DTCM_Msk (1UL << SCB_ABFSR_DTCM_Pos) /*!< SCB ABFSR: DTCM Mask */ + +#define SCB_ABFSR_ITCM_Pos 0U /*!< SCB ABFSR: ITCM Position*/ +#define SCB_ABFSR_ITCM_Msk (1UL /*<< SCB_ABFSR_ITCM_Pos*/) /*!< SCB ABFSR: ITCM Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISDYNADD_Pos 26U /*!< ACTLR: DISDYNADD Position */ +#define SCnSCB_ACTLR_DISDYNADD_Msk (1UL << SCnSCB_ACTLR_DISDYNADD_Pos) /*!< ACTLR: DISDYNADD Mask */ + +#define SCnSCB_ACTLR_DISISSCH1_Pos 21U /*!< ACTLR: DISISSCH1 Position */ +#define SCnSCB_ACTLR_DISISSCH1_Msk (0x1FUL << SCnSCB_ACTLR_DISISSCH1_Pos) /*!< ACTLR: DISISSCH1 Mask */ + +#define SCnSCB_ACTLR_DISDI_Pos 16U /*!< ACTLR: DISDI Position */ +#define SCnSCB_ACTLR_DISDI_Msk (0x1FUL << SCnSCB_ACTLR_DISDI_Pos) /*!< ACTLR: DISDI Mask */ + +#define SCnSCB_ACTLR_DISCRITAXIRUR_Pos 15U /*!< ACTLR: DISCRITAXIRUR Position */ +#define SCnSCB_ACTLR_DISCRITAXIRUR_Msk (1UL << SCnSCB_ACTLR_DISCRITAXIRUR_Pos) /*!< ACTLR: DISCRITAXIRUR Mask */ + +#define SCnSCB_ACTLR_DISBTACALLOC_Pos 14U /*!< ACTLR: DISBTACALLOC Position */ +#define SCnSCB_ACTLR_DISBTACALLOC_Msk (1UL << SCnSCB_ACTLR_DISBTACALLOC_Pos) /*!< ACTLR: DISBTACALLOC Mask */ + +#define SCnSCB_ACTLR_DISBTACREAD_Pos 13U /*!< ACTLR: DISBTACREAD Position */ +#define SCnSCB_ACTLR_DISBTACREAD_Msk (1UL << SCnSCB_ACTLR_DISBTACREAD_Pos) /*!< ACTLR: DISBTACREAD Mask */ + +#define SCnSCB_ACTLR_DISITMATBFLUSH_Pos 12U /*!< ACTLR: DISITMATBFLUSH Position */ +#define SCnSCB_ACTLR_DISITMATBFLUSH_Msk (1UL << SCnSCB_ACTLR_DISITMATBFLUSH_Pos) /*!< ACTLR: DISITMATBFLUSH Mask */ + +#define SCnSCB_ACTLR_DISRAMODE_Pos 11U /*!< ACTLR: DISRAMODE Position */ +#define SCnSCB_ACTLR_DISRAMODE_Msk (1UL << SCnSCB_ACTLR_DISRAMODE_Pos) /*!< ACTLR: DISRAMODE Mask */ + +#define SCnSCB_ACTLR_FPEXCODIS_Pos 10U /*!< ACTLR: FPEXCODIS Position */ +#define SCnSCB_ACTLR_FPEXCODIS_Msk (1UL << SCnSCB_ACTLR_FPEXCODIS_Pos) /*!< ACTLR: FPEXCODIS Mask */ + +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFFFFFFFFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ + uint32_t RESERVED3[981U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( W) Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R ) Lock Status Register */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +#define MPU_TYPE_RALIASES 4U + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif /* defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_FPU Floating Point Unit (FPU) + \brief Type definitions for the Floating Point Unit (FPU) + @{ + */ + +/** + \brief Structure type to access the Floating Point Unit (FPU). + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IOM uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */ + __IOM uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */ + __IOM uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */ + __IM uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */ + __IM uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */ + __IM uint32_t MVFR2; /*!< Offset: 0x018 (R/ ) Media and FP Feature Register 2 */ +} FPU_Type; + +/* Floating-Point Context Control Register Definitions */ +#define FPU_FPCCR_ASPEN_Pos 31U /*!< FPCCR: ASPEN bit Position */ +#define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */ + +#define FPU_FPCCR_LSPEN_Pos 30U /*!< FPCCR: LSPEN Position */ +#define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */ + +#define FPU_FPCCR_MONRDY_Pos 8U /*!< FPCCR: MONRDY Position */ +#define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */ + +#define FPU_FPCCR_BFRDY_Pos 6U /*!< FPCCR: BFRDY Position */ +#define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */ + +#define FPU_FPCCR_MMRDY_Pos 5U /*!< FPCCR: MMRDY Position */ +#define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */ + +#define FPU_FPCCR_HFRDY_Pos 4U /*!< FPCCR: HFRDY Position */ +#define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */ + +#define FPU_FPCCR_THREAD_Pos 3U /*!< FPCCR: processor mode bit Position */ +#define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */ + +#define FPU_FPCCR_USER_Pos 1U /*!< FPCCR: privilege level bit Position */ +#define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */ + +#define FPU_FPCCR_LSPACT_Pos 0U /*!< FPCCR: Lazy state preservation active bit Position */ +#define FPU_FPCCR_LSPACT_Msk (1UL /*<< FPU_FPCCR_LSPACT_Pos*/) /*!< FPCCR: Lazy state preservation active bit Mask */ + +/* Floating-Point Context Address Register Definitions */ +#define FPU_FPCAR_ADDRESS_Pos 3U /*!< FPCAR: ADDRESS bit Position */ +#define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */ + +/* Floating-Point Default Status Control Register Definitions */ +#define FPU_FPDSCR_AHP_Pos 26U /*!< FPDSCR: AHP bit Position */ +#define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */ + +#define FPU_FPDSCR_DN_Pos 25U /*!< FPDSCR: DN bit Position */ +#define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */ + +#define FPU_FPDSCR_FZ_Pos 24U /*!< FPDSCR: FZ bit Position */ +#define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */ + +#define FPU_FPDSCR_RMode_Pos 22U /*!< FPDSCR: RMode bit Position */ +#define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */ + +/* Media and FP Feature Register 0 Definitions */ +#define FPU_MVFR0_FP_rounding_modes_Pos 28U /*!< MVFR0: FP rounding modes bits Position */ +#define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */ + +#define FPU_MVFR0_Short_vectors_Pos 24U /*!< MVFR0: Short vectors bits Position */ +#define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */ + +#define FPU_MVFR0_Square_root_Pos 20U /*!< MVFR0: Square root bits Position */ +#define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */ + +#define FPU_MVFR0_Divide_Pos 16U /*!< MVFR0: Divide bits Position */ +#define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */ + +#define FPU_MVFR0_FP_excep_trapping_Pos 12U /*!< MVFR0: FP exception trapping bits Position */ +#define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */ + +#define FPU_MVFR0_Double_precision_Pos 8U /*!< MVFR0: Double-precision bits Position */ +#define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */ + +#define FPU_MVFR0_Single_precision_Pos 4U /*!< MVFR0: Single-precision bits Position */ +#define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */ + +#define FPU_MVFR0_A_SIMD_registers_Pos 0U /*!< MVFR0: A_SIMD registers bits Position */ +#define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL /*<< FPU_MVFR0_A_SIMD_registers_Pos*/) /*!< MVFR0: A_SIMD registers bits Mask */ + +/* Media and FP Feature Register 1 Definitions */ +#define FPU_MVFR1_FP_fused_MAC_Pos 28U /*!< MVFR1: FP fused MAC bits Position */ +#define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */ + +#define FPU_MVFR1_FP_HPFP_Pos 24U /*!< MVFR1: FP HPFP bits Position */ +#define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */ + +#define FPU_MVFR1_D_NaN_mode_Pos 4U /*!< MVFR1: D_NaN mode bits Position */ +#define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */ + +#define FPU_MVFR1_FtZ_mode_Pos 0U /*!< MVFR1: FtZ mode bits Position */ +#define FPU_MVFR1_FtZ_mode_Msk (0xFUL /*<< FPU_MVFR1_FtZ_mode_Pos*/) /*!< MVFR1: FtZ mode bits Mask */ + +/* Media and FP Feature Register 2 Definitions */ + +#define FPU_MVFR2_VFP_Misc_Pos 4U /*!< MVFR2: VFP Misc bits Position */ +#define FPU_MVFR2_VFP_Misc_Msk (0xFUL << FPU_MVFR2_VFP_Misc_Pos) /*!< MVFR2: VFP Misc bits Mask */ + +/*@} end of group CMSIS_FPU */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +#define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */ +#define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */ + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ +#define EXC_RETURN_HANDLER_FPU (0xFFFFFFE1UL) /* return to Handler mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_MSP_FPU (0xFFFFFFE9UL) /* return to Thread mode, uses MSP after return, restore floating-point state */ +#define EXC_RETURN_THREAD_PSP_FPU (0xFFFFFFEDUL) /* return to Thread mode, uses PSP after return, restore floating-point state */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHPR[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + __DSB(); +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## MPU functions #################################### */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + +#include "mpu_armv7.h" + +#endif + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + uint32_t mvfr0; + + mvfr0 = SCB->MVFR0; + if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x220U) + { + return 2U; /* Double + Single precision FPU */ + } + else if ((mvfr0 & (FPU_MVFR0_Single_precision_Msk | FPU_MVFR0_Double_precision_Msk)) == 0x020U) + { + return 1U; /* Single precision FPU */ + } + else + { + return 0U; /* No FPU */ + } +} + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ########################## Cache functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_CacheFunctions Cache Functions + \brief Functions that configure Instruction and Data cache. + @{ + */ + +/* Cache Size ID Register Macros */ +#define CCSIDR_WAYS(x) (((x) & SCB_CCSIDR_ASSOCIATIVITY_Msk) >> SCB_CCSIDR_ASSOCIATIVITY_Pos) +#define CCSIDR_SETS(x) (((x) & SCB_CCSIDR_NUMSETS_Msk ) >> SCB_CCSIDR_NUMSETS_Pos ) + +#define __SCB_DCACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ +#define __SCB_ICACHE_LINE_SIZE 32U /*!< Cortex-M7 cache line size is fixed to 32 bytes (8 words). See also register SCB_CCSIDR */ + +/** + \brief Enable I-Cache + \details Turns on I-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if (SCB->CCR & SCB_CCR_IC_Msk) return; /* return if ICache is already enabled */ + + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + SCB->CCR |= (uint32_t)SCB_CCR_IC_Msk; /* enable I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable I-Cache + \details Turns off I-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->CCR &= ~(uint32_t)SCB_CCR_IC_Msk; /* disable I-Cache */ + SCB->ICIALLU = 0UL; /* invalidate I-Cache */ + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate I-Cache + \details Invalidates I-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateICache (void) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + __DSB(); + __ISB(); + SCB->ICIALLU = 0UL; + __DSB(); + __ISB(); + #endif +} + + +/** + \brief I-Cache Invalidate by address + \details Invalidates I-Cache for the given address. + I-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + I-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] isize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateICache_by_Addr (void *addr, int32_t isize) +{ + #if defined (__ICACHE_PRESENT) && (__ICACHE_PRESENT == 1U) + if ( isize > 0 ) { + int32_t op_size = isize + (((uint32_t)addr) & (__SCB_ICACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_ICACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->ICIMVAU = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_ICACHE_LINE_SIZE; + op_size -= __SCB_ICACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief Enable D-Cache + \details Turns on D-Cache + */ +__STATIC_FORCEINLINE void SCB_EnableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + if (SCB->CCR & SCB_CCR_DC_Msk) return; /* return if DCache is already enabled */ + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + __DSB(); + + SCB->CCR |= (uint32_t)SCB_CCR_DC_Msk; /* enable D-Cache */ + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Disable D-Cache + \details Turns off D-Cache + */ +__STATIC_FORCEINLINE void SCB_DisableDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + SCB->CCR &= ~(uint32_t)SCB_CCR_DC_Msk; /* disable D-Cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Invalidate D-Cache + \details Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_InvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCISW = (((sets << SCB_DCISW_SET_Pos) & SCB_DCISW_SET_Msk) | + ((ways << SCB_DCISW_WAY_Pos) & SCB_DCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean D-Cache + \details Cleans D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCSW = (((sets << SCB_DCCSW_SET_Pos) & SCB_DCCSW_SET_Msk) | + ((ways << SCB_DCCSW_WAY_Pos) & SCB_DCCSW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief Clean & Invalidate D-Cache + \details Cleans and Invalidates D-Cache + */ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache (void) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + uint32_t ccsidr; + uint32_t sets; + uint32_t ways; + + SCB->CSSELR = 0U; /* select Level 1 data cache */ + __DSB(); + + ccsidr = SCB->CCSIDR; + + /* clean & invalidate D-Cache */ + sets = (uint32_t)(CCSIDR_SETS(ccsidr)); + do { + ways = (uint32_t)(CCSIDR_WAYS(ccsidr)); + do { + SCB->DCCISW = (((sets << SCB_DCCISW_SET_Pos) & SCB_DCCISW_SET_Msk) | + ((ways << SCB_DCCISW_WAY_Pos) & SCB_DCCISW_WAY_Msk) ); + #if defined ( __CC_ARM ) + __schedule_barrier(); + #endif + } while (ways-- != 0U); + } while(sets-- != 0U); + + __DSB(); + __ISB(); + #endif +} + + +/** + \brief D-Cache Invalidate by address + \details Invalidates D-Cache for the given address. + D-Cache is invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are invalidated. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_InvalidateDCache_by_Addr (void *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean by address + \details Cleans D-Cache for the given address + D-Cache is cleaned starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned. + \param[in] addr address + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + + +/** + \brief D-Cache Clean and Invalidate by address + \details Cleans and invalidates D_Cache for the given address + D-Cache is cleaned and invalidated starting from a 32 byte aligned address in 32 byte granularity. + D-Cache memory blocks which are part of given address + given size are cleaned and invalidated. + \param[in] addr address (aligned to 32-byte boundary) + \param[in] dsize size of memory block (in number of bytes) +*/ +__STATIC_FORCEINLINE void SCB_CleanInvalidateDCache_by_Addr (uint32_t *addr, int32_t dsize) +{ + #if defined (__DCACHE_PRESENT) && (__DCACHE_PRESENT == 1U) + if ( dsize > 0 ) { + int32_t op_size = dsize + (((uint32_t)addr) & (__SCB_DCACHE_LINE_SIZE - 1U)); + uint32_t op_addr = (uint32_t)addr /* & ~(__SCB_DCACHE_LINE_SIZE - 1U) */; + + __DSB(); + + do { + SCB->DCCIMVAC = op_addr; /* register accepts only 32byte aligned values, only bits 31..5 are valid */ + op_addr += __SCB_DCACHE_LINE_SIZE; + op_size -= __SCB_DCACHE_LINE_SIZE; + } while ( op_size > 0 ); + + __DSB(); + __ISB(); + } + #endif +} + +/*@} end of CMSIS_Core_CacheFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_CM7_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_sc000.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_sc000.h new file mode 100644 index 0000000000000000000000000000000000000000..cf92577b63e45ccdf3f42cf1d179999aee41c9bd --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_sc000.h @@ -0,0 +1,1025 @@ +/**************************************************************************//** + * @file core_sc000.h + * @brief CMSIS SC000 Core Peripheral Access Layer Header File + * @version V5.0.6 + * @date 12. November 2018 + ******************************************************************************/ +/* + * Copyright (c) 2009-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC000_H_GENERIC +#define __CORE_SC000_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC000 definitions */ +#define __SC000_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC000_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC000_CMSIS_VERSION ((__SC000_CMSIS_VERSION_MAIN << 16U) | \ + __SC000_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (000U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC000_H_DEPENDANT +#define __CORE_SC000_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC000_REV + #define __SC000_REV 0x0000U + #warning "__SC000_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 2U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC000 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:28; /*!< bit: 0..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */ + uint32_t _reserved1:3; /*!< bit: 25..27 Reserved */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t _reserved0:1; /*!< bit: 0 Reserved */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[1U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[31U]; + __IOM uint32_t ICER[1U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RSERVED1[31U]; + __IOM uint32_t ISPR[1U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[31U]; + __IOM uint32_t ICPR[1U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[31U]; + uint32_t RESERVED4[64U]; + __IOM uint32_t IP[8U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register */ +} NVIC_Type; + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + uint32_t RESERVED0[1U]; + __IOM uint32_t SHP[2U]; /*!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + uint32_t RESERVED1[154U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 8U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0xFFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief SC000 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP and not via processor. + Therefore they are not covered by the SC000 header file. + @{ + */ +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else +/*#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for SC000 */ +/*#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for SC000 */ + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ +/*#define NVIC_GetActive __NVIC_GetActive not available for SC000 */ + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/* Interrupt Priorities are WORD accessible only under Armv6-M */ +/* The following MACROS handle generation of the register offset and byte masks */ +#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL) +#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) ) +#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) ) + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[0U] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[0U] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IP[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } + else + { + SCB->SHP[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) | + (((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn))); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return((uint32_t)(((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector; + /* ARM Application Note 321 states that the M0 and M0+ do not require the architectural barrier - assume SC000 is the same */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t *vectors = (uint32_t *)SCB->VTOR; + return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET]; +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + SCB_AIRCR_SYSRESETREQ_Msk); + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC000_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/core_sc300.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_sc300.h new file mode 100644 index 0000000000000000000000000000000000000000..40f3af81becf238f2ed2a3cf3e3cfa4b78dffa16 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/core_sc300.h @@ -0,0 +1,1912 @@ +/**************************************************************************//** + * @file core_sc300.h + * @brief CMSIS SC300 Core Peripheral Access Layer Header File + * @version V5.0.8 + * @date 31. May 2019 + ******************************************************************************/ +/* + * Copyright (c) 2009-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef __CORE_SC300_H_GENERIC +#define __CORE_SC300_H_GENERIC + +#include + +#ifdef __cplusplus + extern "C" { +#endif + +/** + \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions + CMSIS violates the following MISRA-C:2004 rules: + + \li Required Rule 8.5, object/function definition in header file.
+ Function definitions in header files are used to allow 'inlining'. + + \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.
+ Unions are used for effective representation of core registers. + + \li Advisory Rule 19.7, Function-like macro defined.
+ Function-like macros are used to allow more efficient code. + */ + + +/******************************************************************************* + * CMSIS definitions + ******************************************************************************/ +/** + \ingroup SC3000 + @{ + */ + +#include "cmsis_version.h" + +/* CMSIS SC300 definitions */ +#define __SC300_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /*!< \deprecated [31:16] CMSIS HAL main version */ +#define __SC300_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /*!< \deprecated [15:0] CMSIS HAL sub version */ +#define __SC300_CMSIS_VERSION ((__SC300_CMSIS_VERSION_MAIN << 16U) | \ + __SC300_CMSIS_VERSION_SUB ) /*!< \deprecated CMSIS HAL version number */ + +#define __CORTEX_SC (300U) /*!< Cortex secure core */ + +/** __FPU_USED indicates whether an FPU is used or not. + This core does not support an FPU at all +*/ +#define __FPU_USED 0U + +#if defined ( __CC_ARM ) + #if defined __TARGET_FPU_VFP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) + #if defined __ARM_FP + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __GNUC__ ) + #if defined (__VFP_FP__) && !defined(__SOFTFP__) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __ICCARM__ ) + #if defined __ARMVFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TI_ARM__ ) + #if defined __TI_VFP_SUPPORT__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __TASKING__ ) + #if defined __FPU_VFP__ + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#elif defined ( __CSMC__ ) + #if ( __CSMC__ & 0x400U) + #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)" + #endif + +#endif + +#include "cmsis_compiler.h" /* CMSIS compiler specific defines */ + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_GENERIC */ + +#ifndef __CMSIS_GENERIC + +#ifndef __CORE_SC300_H_DEPENDANT +#define __CORE_SC300_H_DEPENDANT + +#ifdef __cplusplus + extern "C" { +#endif + +/* check device defines and use defaults */ +#if defined __CHECK_DEVICE_DEFINES + #ifndef __SC300_REV + #define __SC300_REV 0x0000U + #warning "__SC300_REV not defined in device header file; using default!" + #endif + + #ifndef __MPU_PRESENT + #define __MPU_PRESENT 0U + #warning "__MPU_PRESENT not defined in device header file; using default!" + #endif + + #ifndef __NVIC_PRIO_BITS + #define __NVIC_PRIO_BITS 3U + #warning "__NVIC_PRIO_BITS not defined in device header file; using default!" + #endif + + #ifndef __Vendor_SysTickConfig + #define __Vendor_SysTickConfig 0U + #warning "__Vendor_SysTickConfig not defined in device header file; using default!" + #endif +#endif + +/* IO definitions (access restrictions to peripheral registers) */ +/** + \defgroup CMSIS_glob_defs CMSIS Global Defines + + IO Type Qualifiers are used + \li to specify the access to peripheral variables. + \li for automatic generation of peripheral register debug information. +*/ +#ifdef __cplusplus + #define __I volatile /*!< Defines 'read only' permissions */ +#else + #define __I volatile const /*!< Defines 'read only' permissions */ +#endif +#define __O volatile /*!< Defines 'write only' permissions */ +#define __IO volatile /*!< Defines 'read / write' permissions */ + +/* following defines should be used for structure members */ +#define __IM volatile const /*! Defines 'read only' structure member permissions */ +#define __OM volatile /*! Defines 'write only' structure member permissions */ +#define __IOM volatile /*! Defines 'read / write' structure member permissions */ + +/*@} end of group SC300 */ + + + +/******************************************************************************* + * Register Abstraction + Core Register contain: + - Core Register + - Core NVIC Register + - Core SCB Register + - Core SysTick Register + - Core Debug Register + - Core MPU Register + ******************************************************************************/ +/** + \defgroup CMSIS_core_register Defines and Type Definitions + \brief Type definitions and defines for Cortex-M processor based devices. +*/ + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CORE Status and Control Registers + \brief Core Register type definitions. + @{ + */ + +/** + \brief Union type to access the Application Program Status Register (APSR). + */ +typedef union +{ + struct + { + uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} APSR_Type; + +/* APSR Register Definitions */ +#define APSR_N_Pos 31U /*!< APSR: N Position */ +#define APSR_N_Msk (1UL << APSR_N_Pos) /*!< APSR: N Mask */ + +#define APSR_Z_Pos 30U /*!< APSR: Z Position */ +#define APSR_Z_Msk (1UL << APSR_Z_Pos) /*!< APSR: Z Mask */ + +#define APSR_C_Pos 29U /*!< APSR: C Position */ +#define APSR_C_Msk (1UL << APSR_C_Pos) /*!< APSR: C Mask */ + +#define APSR_V_Pos 28U /*!< APSR: V Position */ +#define APSR_V_Msk (1UL << APSR_V_Pos) /*!< APSR: V Mask */ + +#define APSR_Q_Pos 27U /*!< APSR: Q Position */ +#define APSR_Q_Msk (1UL << APSR_Q_Pos) /*!< APSR: Q Mask */ + + +/** + \brief Union type to access the Interrupt Program Status Register (IPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} IPSR_Type; + +/* IPSR Register Definitions */ +#define IPSR_ISR_Pos 0U /*!< IPSR: ISR Position */ +#define IPSR_ISR_Msk (0x1FFUL /*<< IPSR_ISR_Pos*/) /*!< IPSR: ISR Mask */ + + +/** + \brief Union type to access the Special-Purpose Program Status Registers (xPSR). + */ +typedef union +{ + struct + { + uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */ + uint32_t _reserved0:1; /*!< bit: 9 Reserved */ + uint32_t ICI_IT_1:6; /*!< bit: 10..15 ICI/IT part 1 */ + uint32_t _reserved1:8; /*!< bit: 16..23 Reserved */ + uint32_t T:1; /*!< bit: 24 Thumb bit */ + uint32_t ICI_IT_2:2; /*!< bit: 25..26 ICI/IT part 2 */ + uint32_t Q:1; /*!< bit: 27 Saturation condition flag */ + uint32_t V:1; /*!< bit: 28 Overflow condition code flag */ + uint32_t C:1; /*!< bit: 29 Carry condition code flag */ + uint32_t Z:1; /*!< bit: 30 Zero condition code flag */ + uint32_t N:1; /*!< bit: 31 Negative condition code flag */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} xPSR_Type; + +/* xPSR Register Definitions */ +#define xPSR_N_Pos 31U /*!< xPSR: N Position */ +#define xPSR_N_Msk (1UL << xPSR_N_Pos) /*!< xPSR: N Mask */ + +#define xPSR_Z_Pos 30U /*!< xPSR: Z Position */ +#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /*!< xPSR: Z Mask */ + +#define xPSR_C_Pos 29U /*!< xPSR: C Position */ +#define xPSR_C_Msk (1UL << xPSR_C_Pos) /*!< xPSR: C Mask */ + +#define xPSR_V_Pos 28U /*!< xPSR: V Position */ +#define xPSR_V_Msk (1UL << xPSR_V_Pos) /*!< xPSR: V Mask */ + +#define xPSR_Q_Pos 27U /*!< xPSR: Q Position */ +#define xPSR_Q_Msk (1UL << xPSR_Q_Pos) /*!< xPSR: Q Mask */ + +#define xPSR_ICI_IT_2_Pos 25U /*!< xPSR: ICI/IT part 2 Position */ +#define xPSR_ICI_IT_2_Msk (3UL << xPSR_ICI_IT_2_Pos) /*!< xPSR: ICI/IT part 2 Mask */ + +#define xPSR_T_Pos 24U /*!< xPSR: T Position */ +#define xPSR_T_Msk (1UL << xPSR_T_Pos) /*!< xPSR: T Mask */ + +#define xPSR_ICI_IT_1_Pos 10U /*!< xPSR: ICI/IT part 1 Position */ +#define xPSR_ICI_IT_1_Msk (0x3FUL << xPSR_ICI_IT_1_Pos) /*!< xPSR: ICI/IT part 1 Mask */ + +#define xPSR_ISR_Pos 0U /*!< xPSR: ISR Position */ +#define xPSR_ISR_Msk (0x1FFUL /*<< xPSR_ISR_Pos*/) /*!< xPSR: ISR Mask */ + + +/** + \brief Union type to access the Control Registers (CONTROL). + */ +typedef union +{ + struct + { + uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */ + uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */ + uint32_t _reserved1:30; /*!< bit: 2..31 Reserved */ + } b; /*!< Structure used for bit access */ + uint32_t w; /*!< Type used for word access */ +} CONTROL_Type; + +/* CONTROL Register Definitions */ +#define CONTROL_SPSEL_Pos 1U /*!< CONTROL: SPSEL Position */ +#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /*!< CONTROL: SPSEL Mask */ + +#define CONTROL_nPRIV_Pos 0U /*!< CONTROL: nPRIV Position */ +#define CONTROL_nPRIV_Msk (1UL /*<< CONTROL_nPRIV_Pos*/) /*!< CONTROL: nPRIV Mask */ + +/*@} end of group CMSIS_CORE */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC) + \brief Type definitions for the NVIC Registers + @{ + */ + +/** + \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC). + */ +typedef struct +{ + __IOM uint32_t ISER[8U]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */ + uint32_t RESERVED0[24U]; + __IOM uint32_t ICER[8U]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */ + uint32_t RESERVED1[24U]; + __IOM uint32_t ISPR[8U]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */ + uint32_t RESERVED2[24U]; + __IOM uint32_t ICPR[8U]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */ + uint32_t RESERVED3[24U]; + __IOM uint32_t IABR[8U]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */ + uint32_t RESERVED4[56U]; + __IOM uint8_t IP[240U]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */ + uint32_t RESERVED5[644U]; + __OM uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */ +} NVIC_Type; + +/* Software Triggered Interrupt Register Definitions */ +#define NVIC_STIR_INTID_Pos 0U /*!< STIR: INTLINESNUM Position */ +#define NVIC_STIR_INTID_Msk (0x1FFUL /*<< NVIC_STIR_INTID_Pos*/) /*!< STIR: INTLINESNUM Mask */ + +/*@} end of group CMSIS_NVIC */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCB System Control Block (SCB) + \brief Type definitions for the System Control Block Registers + @{ + */ + +/** + \brief Structure type to access the System Control Block (SCB). + */ +typedef struct +{ + __IM uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */ + __IOM uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */ + __IOM uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */ + __IOM uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */ + __IOM uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */ + __IOM uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */ + __IOM uint8_t SHP[12U]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */ + __IOM uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */ + __IOM uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */ + __IOM uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */ + __IOM uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */ + __IOM uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */ + __IOM uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */ + __IOM uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */ + __IM uint32_t PFR[2U]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */ + __IM uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */ + __IM uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */ + __IM uint32_t MMFR[4U]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */ + __IM uint32_t ISAR[5U]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */ + uint32_t RESERVED0[5U]; + __IOM uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */ + uint32_t RESERVED1[129U]; + __IOM uint32_t SFCR; /*!< Offset: 0x290 (R/W) Security Features Control Register */ +} SCB_Type; + +/* SCB CPUID Register Definitions */ +#define SCB_CPUID_IMPLEMENTER_Pos 24U /*!< SCB CPUID: IMPLEMENTER Position */ +#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */ + +#define SCB_CPUID_VARIANT_Pos 20U /*!< SCB CPUID: VARIANT Position */ +#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */ + +#define SCB_CPUID_ARCHITECTURE_Pos 16U /*!< SCB CPUID: ARCHITECTURE Position */ +#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */ + +#define SCB_CPUID_PARTNO_Pos 4U /*!< SCB CPUID: PARTNO Position */ +#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */ + +#define SCB_CPUID_REVISION_Pos 0U /*!< SCB CPUID: REVISION Position */ +#define SCB_CPUID_REVISION_Msk (0xFUL /*<< SCB_CPUID_REVISION_Pos*/) /*!< SCB CPUID: REVISION Mask */ + +/* SCB Interrupt Control State Register Definitions */ +#define SCB_ICSR_NMIPENDSET_Pos 31U /*!< SCB ICSR: NMIPENDSET Position */ +#define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */ + +#define SCB_ICSR_PENDSVSET_Pos 28U /*!< SCB ICSR: PENDSVSET Position */ +#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */ + +#define SCB_ICSR_PENDSVCLR_Pos 27U /*!< SCB ICSR: PENDSVCLR Position */ +#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */ + +#define SCB_ICSR_PENDSTSET_Pos 26U /*!< SCB ICSR: PENDSTSET Position */ +#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */ + +#define SCB_ICSR_PENDSTCLR_Pos 25U /*!< SCB ICSR: PENDSTCLR Position */ +#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */ + +#define SCB_ICSR_ISRPREEMPT_Pos 23U /*!< SCB ICSR: ISRPREEMPT Position */ +#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */ + +#define SCB_ICSR_ISRPENDING_Pos 22U /*!< SCB ICSR: ISRPENDING Position */ +#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */ + +#define SCB_ICSR_VECTPENDING_Pos 12U /*!< SCB ICSR: VECTPENDING Position */ +#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */ + +#define SCB_ICSR_RETTOBASE_Pos 11U /*!< SCB ICSR: RETTOBASE Position */ +#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */ + +#define SCB_ICSR_VECTACTIVE_Pos 0U /*!< SCB ICSR: VECTACTIVE Position */ +#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /*<< SCB_ICSR_VECTACTIVE_Pos*/) /*!< SCB ICSR: VECTACTIVE Mask */ + +/* SCB Vector Table Offset Register Definitions */ +#define SCB_VTOR_TBLBASE_Pos 29U /*!< SCB VTOR: TBLBASE Position */ +#define SCB_VTOR_TBLBASE_Msk (1UL << SCB_VTOR_TBLBASE_Pos) /*!< SCB VTOR: TBLBASE Mask */ + +#define SCB_VTOR_TBLOFF_Pos 7U /*!< SCB VTOR: TBLOFF Position */ +#define SCB_VTOR_TBLOFF_Msk (0x3FFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */ + +/* SCB Application Interrupt and Reset Control Register Definitions */ +#define SCB_AIRCR_VECTKEY_Pos 16U /*!< SCB AIRCR: VECTKEY Position */ +#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */ + +#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /*!< SCB AIRCR: VECTKEYSTAT Position */ +#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */ + +#define SCB_AIRCR_ENDIANESS_Pos 15U /*!< SCB AIRCR: ENDIANESS Position */ +#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */ + +#define SCB_AIRCR_PRIGROUP_Pos 8U /*!< SCB AIRCR: PRIGROUP Position */ +#define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */ + +#define SCB_AIRCR_SYSRESETREQ_Pos 2U /*!< SCB AIRCR: SYSRESETREQ Position */ +#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */ + +#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /*!< SCB AIRCR: VECTCLRACTIVE Position */ +#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */ + +#define SCB_AIRCR_VECTRESET_Pos 0U /*!< SCB AIRCR: VECTRESET Position */ +#define SCB_AIRCR_VECTRESET_Msk (1UL /*<< SCB_AIRCR_VECTRESET_Pos*/) /*!< SCB AIRCR: VECTRESET Mask */ + +/* SCB System Control Register Definitions */ +#define SCB_SCR_SEVONPEND_Pos 4U /*!< SCB SCR: SEVONPEND Position */ +#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */ + +#define SCB_SCR_SLEEPDEEP_Pos 2U /*!< SCB SCR: SLEEPDEEP Position */ +#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */ + +#define SCB_SCR_SLEEPONEXIT_Pos 1U /*!< SCB SCR: SLEEPONEXIT Position */ +#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */ + +/* SCB Configuration Control Register Definitions */ +#define SCB_CCR_STKALIGN_Pos 9U /*!< SCB CCR: STKALIGN Position */ +#define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */ + +#define SCB_CCR_BFHFNMIGN_Pos 8U /*!< SCB CCR: BFHFNMIGN Position */ +#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */ + +#define SCB_CCR_DIV_0_TRP_Pos 4U /*!< SCB CCR: DIV_0_TRP Position */ +#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */ + +#define SCB_CCR_UNALIGN_TRP_Pos 3U /*!< SCB CCR: UNALIGN_TRP Position */ +#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */ + +#define SCB_CCR_USERSETMPEND_Pos 1U /*!< SCB CCR: USERSETMPEND Position */ +#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */ + +#define SCB_CCR_NONBASETHRDENA_Pos 0U /*!< SCB CCR: NONBASETHRDENA Position */ +#define SCB_CCR_NONBASETHRDENA_Msk (1UL /*<< SCB_CCR_NONBASETHRDENA_Pos*/) /*!< SCB CCR: NONBASETHRDENA Mask */ + +/* SCB System Handler Control and State Register Definitions */ +#define SCB_SHCSR_USGFAULTENA_Pos 18U /*!< SCB SHCSR: USGFAULTENA Position */ +#define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */ + +#define SCB_SHCSR_BUSFAULTENA_Pos 17U /*!< SCB SHCSR: BUSFAULTENA Position */ +#define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */ + +#define SCB_SHCSR_MEMFAULTENA_Pos 16U /*!< SCB SHCSR: MEMFAULTENA Position */ +#define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */ + +#define SCB_SHCSR_SVCALLPENDED_Pos 15U /*!< SCB SHCSR: SVCALLPENDED Position */ +#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */ + +#define SCB_SHCSR_BUSFAULTPENDED_Pos 14U /*!< SCB SHCSR: BUSFAULTPENDED Position */ +#define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */ + +#define SCB_SHCSR_MEMFAULTPENDED_Pos 13U /*!< SCB SHCSR: MEMFAULTPENDED Position */ +#define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */ + +#define SCB_SHCSR_USGFAULTPENDED_Pos 12U /*!< SCB SHCSR: USGFAULTPENDED Position */ +#define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */ + +#define SCB_SHCSR_SYSTICKACT_Pos 11U /*!< SCB SHCSR: SYSTICKACT Position */ +#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */ + +#define SCB_SHCSR_PENDSVACT_Pos 10U /*!< SCB SHCSR: PENDSVACT Position */ +#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */ + +#define SCB_SHCSR_MONITORACT_Pos 8U /*!< SCB SHCSR: MONITORACT Position */ +#define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */ + +#define SCB_SHCSR_SVCALLACT_Pos 7U /*!< SCB SHCSR: SVCALLACT Position */ +#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */ + +#define SCB_SHCSR_USGFAULTACT_Pos 3U /*!< SCB SHCSR: USGFAULTACT Position */ +#define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */ + +#define SCB_SHCSR_BUSFAULTACT_Pos 1U /*!< SCB SHCSR: BUSFAULTACT Position */ +#define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */ + +#define SCB_SHCSR_MEMFAULTACT_Pos 0U /*!< SCB SHCSR: MEMFAULTACT Position */ +#define SCB_SHCSR_MEMFAULTACT_Msk (1UL /*<< SCB_SHCSR_MEMFAULTACT_Pos*/) /*!< SCB SHCSR: MEMFAULTACT Mask */ + +/* SCB Configurable Fault Status Register Definitions */ +#define SCB_CFSR_USGFAULTSR_Pos 16U /*!< SCB CFSR: Usage Fault Status Register Position */ +#define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */ + +#define SCB_CFSR_BUSFAULTSR_Pos 8U /*!< SCB CFSR: Bus Fault Status Register Position */ +#define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */ + +#define SCB_CFSR_MEMFAULTSR_Pos 0U /*!< SCB CFSR: Memory Manage Fault Status Register Position */ +#define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL /*<< SCB_CFSR_MEMFAULTSR_Pos*/) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */ + +/* MemManage Fault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_MMARVALID_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 7U) /*!< SCB CFSR (MMFSR): MMARVALID Position */ +#define SCB_CFSR_MMARVALID_Msk (1UL << SCB_CFSR_MMARVALID_Pos) /*!< SCB CFSR (MMFSR): MMARVALID Mask */ + +#define SCB_CFSR_MSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 4U) /*!< SCB CFSR (MMFSR): MSTKERR Position */ +#define SCB_CFSR_MSTKERR_Msk (1UL << SCB_CFSR_MSTKERR_Pos) /*!< SCB CFSR (MMFSR): MSTKERR Mask */ + +#define SCB_CFSR_MUNSTKERR_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 3U) /*!< SCB CFSR (MMFSR): MUNSTKERR Position */ +#define SCB_CFSR_MUNSTKERR_Msk (1UL << SCB_CFSR_MUNSTKERR_Pos) /*!< SCB CFSR (MMFSR): MUNSTKERR Mask */ + +#define SCB_CFSR_DACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 1U) /*!< SCB CFSR (MMFSR): DACCVIOL Position */ +#define SCB_CFSR_DACCVIOL_Msk (1UL << SCB_CFSR_DACCVIOL_Pos) /*!< SCB CFSR (MMFSR): DACCVIOL Mask */ + +#define SCB_CFSR_IACCVIOL_Pos (SCB_SHCSR_MEMFAULTACT_Pos + 0U) /*!< SCB CFSR (MMFSR): IACCVIOL Position */ +#define SCB_CFSR_IACCVIOL_Msk (1UL /*<< SCB_CFSR_IACCVIOL_Pos*/) /*!< SCB CFSR (MMFSR): IACCVIOL Mask */ + +/* BusFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_BFARVALID_Pos (SCB_CFSR_BUSFAULTSR_Pos + 7U) /*!< SCB CFSR (BFSR): BFARVALID Position */ +#define SCB_CFSR_BFARVALID_Msk (1UL << SCB_CFSR_BFARVALID_Pos) /*!< SCB CFSR (BFSR): BFARVALID Mask */ + +#define SCB_CFSR_STKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 4U) /*!< SCB CFSR (BFSR): STKERR Position */ +#define SCB_CFSR_STKERR_Msk (1UL << SCB_CFSR_STKERR_Pos) /*!< SCB CFSR (BFSR): STKERR Mask */ + +#define SCB_CFSR_UNSTKERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 3U) /*!< SCB CFSR (BFSR): UNSTKERR Position */ +#define SCB_CFSR_UNSTKERR_Msk (1UL << SCB_CFSR_UNSTKERR_Pos) /*!< SCB CFSR (BFSR): UNSTKERR Mask */ + +#define SCB_CFSR_IMPRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 2U) /*!< SCB CFSR (BFSR): IMPRECISERR Position */ +#define SCB_CFSR_IMPRECISERR_Msk (1UL << SCB_CFSR_IMPRECISERR_Pos) /*!< SCB CFSR (BFSR): IMPRECISERR Mask */ + +#define SCB_CFSR_PRECISERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 1U) /*!< SCB CFSR (BFSR): PRECISERR Position */ +#define SCB_CFSR_PRECISERR_Msk (1UL << SCB_CFSR_PRECISERR_Pos) /*!< SCB CFSR (BFSR): PRECISERR Mask */ + +#define SCB_CFSR_IBUSERR_Pos (SCB_CFSR_BUSFAULTSR_Pos + 0U) /*!< SCB CFSR (BFSR): IBUSERR Position */ +#define SCB_CFSR_IBUSERR_Msk (1UL << SCB_CFSR_IBUSERR_Pos) /*!< SCB CFSR (BFSR): IBUSERR Mask */ + +/* UsageFault Status Register (part of SCB Configurable Fault Status Register) */ +#define SCB_CFSR_DIVBYZERO_Pos (SCB_CFSR_USGFAULTSR_Pos + 9U) /*!< SCB CFSR (UFSR): DIVBYZERO Position */ +#define SCB_CFSR_DIVBYZERO_Msk (1UL << SCB_CFSR_DIVBYZERO_Pos) /*!< SCB CFSR (UFSR): DIVBYZERO Mask */ + +#define SCB_CFSR_UNALIGNED_Pos (SCB_CFSR_USGFAULTSR_Pos + 8U) /*!< SCB CFSR (UFSR): UNALIGNED Position */ +#define SCB_CFSR_UNALIGNED_Msk (1UL << SCB_CFSR_UNALIGNED_Pos) /*!< SCB CFSR (UFSR): UNALIGNED Mask */ + +#define SCB_CFSR_NOCP_Pos (SCB_CFSR_USGFAULTSR_Pos + 3U) /*!< SCB CFSR (UFSR): NOCP Position */ +#define SCB_CFSR_NOCP_Msk (1UL << SCB_CFSR_NOCP_Pos) /*!< SCB CFSR (UFSR): NOCP Mask */ + +#define SCB_CFSR_INVPC_Pos (SCB_CFSR_USGFAULTSR_Pos + 2U) /*!< SCB CFSR (UFSR): INVPC Position */ +#define SCB_CFSR_INVPC_Msk (1UL << SCB_CFSR_INVPC_Pos) /*!< SCB CFSR (UFSR): INVPC Mask */ + +#define SCB_CFSR_INVSTATE_Pos (SCB_CFSR_USGFAULTSR_Pos + 1U) /*!< SCB CFSR (UFSR): INVSTATE Position */ +#define SCB_CFSR_INVSTATE_Msk (1UL << SCB_CFSR_INVSTATE_Pos) /*!< SCB CFSR (UFSR): INVSTATE Mask */ + +#define SCB_CFSR_UNDEFINSTR_Pos (SCB_CFSR_USGFAULTSR_Pos + 0U) /*!< SCB CFSR (UFSR): UNDEFINSTR Position */ +#define SCB_CFSR_UNDEFINSTR_Msk (1UL << SCB_CFSR_UNDEFINSTR_Pos) /*!< SCB CFSR (UFSR): UNDEFINSTR Mask */ + +/* SCB Hard Fault Status Register Definitions */ +#define SCB_HFSR_DEBUGEVT_Pos 31U /*!< SCB HFSR: DEBUGEVT Position */ +#define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */ + +#define SCB_HFSR_FORCED_Pos 30U /*!< SCB HFSR: FORCED Position */ +#define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */ + +#define SCB_HFSR_VECTTBL_Pos 1U /*!< SCB HFSR: VECTTBL Position */ +#define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */ + +/* SCB Debug Fault Status Register Definitions */ +#define SCB_DFSR_EXTERNAL_Pos 4U /*!< SCB DFSR: EXTERNAL Position */ +#define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */ + +#define SCB_DFSR_VCATCH_Pos 3U /*!< SCB DFSR: VCATCH Position */ +#define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */ + +#define SCB_DFSR_DWTTRAP_Pos 2U /*!< SCB DFSR: DWTTRAP Position */ +#define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */ + +#define SCB_DFSR_BKPT_Pos 1U /*!< SCB DFSR: BKPT Position */ +#define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */ + +#define SCB_DFSR_HALTED_Pos 0U /*!< SCB DFSR: HALTED Position */ +#define SCB_DFSR_HALTED_Msk (1UL /*<< SCB_DFSR_HALTED_Pos*/) /*!< SCB DFSR: HALTED Mask */ + +/*@} end of group CMSIS_SCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB) + \brief Type definitions for the System Control and ID Register not in the SCB + @{ + */ + +/** + \brief Structure type to access the System Control and ID Register not in the SCB. + */ +typedef struct +{ + uint32_t RESERVED0[1U]; + __IM uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */ + __IOM uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */ +} SCnSCB_Type; + +/* Interrupt Controller Type Register Definitions */ +#define SCnSCB_ICTR_INTLINESNUM_Pos 0U /*!< ICTR: INTLINESNUM Position */ +#define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL /*<< SCnSCB_ICTR_INTLINESNUM_Pos*/) /*!< ICTR: INTLINESNUM Mask */ + +/* Auxiliary Control Register Definitions */ +#define SCnSCB_ACTLR_DISFOLD_Pos 2U /*!< ACTLR: DISFOLD Position */ +#define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */ + +#define SCnSCB_ACTLR_DISDEFWBUF_Pos 1U /*!< ACTLR: DISDEFWBUF Position */ +#define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */ + +#define SCnSCB_ACTLR_DISMCYCINT_Pos 0U /*!< ACTLR: DISMCYCINT Position */ +#define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL /*<< SCnSCB_ACTLR_DISMCYCINT_Pos*/) /*!< ACTLR: DISMCYCINT Mask */ + +/*@} end of group CMSIS_SCnotSCB */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_SysTick System Tick Timer (SysTick) + \brief Type definitions for the System Timer Registers. + @{ + */ + +/** + \brief Structure type to access the System Timer (SysTick). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */ + __IOM uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */ + __IOM uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */ + __IM uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */ +} SysTick_Type; + +/* SysTick Control / Status Register Definitions */ +#define SysTick_CTRL_COUNTFLAG_Pos 16U /*!< SysTick CTRL: COUNTFLAG Position */ +#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */ + +#define SysTick_CTRL_CLKSOURCE_Pos 2U /*!< SysTick CTRL: CLKSOURCE Position */ +#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */ + +#define SysTick_CTRL_TICKINT_Pos 1U /*!< SysTick CTRL: TICKINT Position */ +#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */ + +#define SysTick_CTRL_ENABLE_Pos 0U /*!< SysTick CTRL: ENABLE Position */ +#define SysTick_CTRL_ENABLE_Msk (1UL /*<< SysTick_CTRL_ENABLE_Pos*/) /*!< SysTick CTRL: ENABLE Mask */ + +/* SysTick Reload Register Definitions */ +#define SysTick_LOAD_RELOAD_Pos 0U /*!< SysTick LOAD: RELOAD Position */ +#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /*<< SysTick_LOAD_RELOAD_Pos*/) /*!< SysTick LOAD: RELOAD Mask */ + +/* SysTick Current Register Definitions */ +#define SysTick_VAL_CURRENT_Pos 0U /*!< SysTick VAL: CURRENT Position */ +#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /*<< SysTick_VAL_CURRENT_Pos*/) /*!< SysTick VAL: CURRENT Mask */ + +/* SysTick Calibration Register Definitions */ +#define SysTick_CALIB_NOREF_Pos 31U /*!< SysTick CALIB: NOREF Position */ +#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */ + +#define SysTick_CALIB_SKEW_Pos 30U /*!< SysTick CALIB: SKEW Position */ +#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */ + +#define SysTick_CALIB_TENMS_Pos 0U /*!< SysTick CALIB: TENMS Position */ +#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /*<< SysTick_CALIB_TENMS_Pos*/) /*!< SysTick CALIB: TENMS Mask */ + +/*@} end of group CMSIS_SysTick */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM) + \brief Type definitions for the Instrumentation Trace Macrocell (ITM) + @{ + */ + +/** + \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM). + */ +typedef struct +{ + __OM union + { + __OM uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */ + __OM uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */ + __OM uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */ + } PORT [32U]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */ + uint32_t RESERVED0[864U]; + __IOM uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */ + uint32_t RESERVED1[15U]; + __IOM uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */ + uint32_t RESERVED2[15U]; + __IOM uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */ + uint32_t RESERVED3[32U]; + uint32_t RESERVED4[43U]; + __OM uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */ + __IM uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */ + uint32_t RESERVED5[6U]; + __IM uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */ + __IM uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */ + __IM uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */ + __IM uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */ + __IM uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */ + __IM uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */ + __IM uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */ + __IM uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */ + __IM uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */ + __IM uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */ + __IM uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */ + __IM uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */ +} ITM_Type; + +/* ITM Trace Privilege Register Definitions */ +#define ITM_TPR_PRIVMASK_Pos 0U /*!< ITM TPR: PRIVMASK Position */ +#define ITM_TPR_PRIVMASK_Msk (0xFUL /*<< ITM_TPR_PRIVMASK_Pos*/) /*!< ITM TPR: PRIVMASK Mask */ + +/* ITM Trace Control Register Definitions */ +#define ITM_TCR_BUSY_Pos 23U /*!< ITM TCR: BUSY Position */ +#define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */ + +#define ITM_TCR_TraceBusID_Pos 16U /*!< ITM TCR: ATBID Position */ +#define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */ + +#define ITM_TCR_GTSFREQ_Pos 10U /*!< ITM TCR: Global timestamp frequency Position */ +#define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */ + +#define ITM_TCR_TSPrescale_Pos 8U /*!< ITM TCR: TSPrescale Position */ +#define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */ + +#define ITM_TCR_SWOENA_Pos 4U /*!< ITM TCR: SWOENA Position */ +#define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */ + +#define ITM_TCR_DWTENA_Pos 3U /*!< ITM TCR: DWTENA Position */ +#define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */ + +#define ITM_TCR_SYNCENA_Pos 2U /*!< ITM TCR: SYNCENA Position */ +#define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */ + +#define ITM_TCR_TSENA_Pos 1U /*!< ITM TCR: TSENA Position */ +#define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */ + +#define ITM_TCR_ITMENA_Pos 0U /*!< ITM TCR: ITM Enable bit Position */ +#define ITM_TCR_ITMENA_Msk (1UL /*<< ITM_TCR_ITMENA_Pos*/) /*!< ITM TCR: ITM Enable bit Mask */ + +/* ITM Lock Status Register Definitions */ +#define ITM_LSR_ByteAcc_Pos 2U /*!< ITM LSR: ByteAcc Position */ +#define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */ + +#define ITM_LSR_Access_Pos 1U /*!< ITM LSR: Access Position */ +#define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */ + +#define ITM_LSR_Present_Pos 0U /*!< ITM LSR: Present Position */ +#define ITM_LSR_Present_Msk (1UL /*<< ITM_LSR_Present_Pos*/) /*!< ITM LSR: Present Mask */ + +/*@}*/ /* end of group CMSIS_ITM */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT) + \brief Type definitions for the Data Watchpoint and Trace (DWT) + @{ + */ + +/** + \brief Structure type to access the Data Watchpoint and Trace Register (DWT). + */ +typedef struct +{ + __IOM uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */ + __IOM uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */ + __IOM uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */ + __IOM uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */ + __IOM uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */ + __IOM uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */ + __IOM uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */ + __IM uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */ + __IOM uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */ + __IOM uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */ + __IOM uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */ + uint32_t RESERVED0[1U]; + __IOM uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */ + __IOM uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */ + __IOM uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */ + uint32_t RESERVED1[1U]; + __IOM uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */ + __IOM uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */ + __IOM uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */ + uint32_t RESERVED2[1U]; + __IOM uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */ + __IOM uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */ + __IOM uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */ +} DWT_Type; + +/* DWT Control Register Definitions */ +#define DWT_CTRL_NUMCOMP_Pos 28U /*!< DWT CTRL: NUMCOMP Position */ +#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */ + +#define DWT_CTRL_NOTRCPKT_Pos 27U /*!< DWT CTRL: NOTRCPKT Position */ +#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */ + +#define DWT_CTRL_NOEXTTRIG_Pos 26U /*!< DWT CTRL: NOEXTTRIG Position */ +#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */ + +#define DWT_CTRL_NOCYCCNT_Pos 25U /*!< DWT CTRL: NOCYCCNT Position */ +#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */ + +#define DWT_CTRL_NOPRFCNT_Pos 24U /*!< DWT CTRL: NOPRFCNT Position */ +#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */ + +#define DWT_CTRL_CYCEVTENA_Pos 22U /*!< DWT CTRL: CYCEVTENA Position */ +#define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */ + +#define DWT_CTRL_FOLDEVTENA_Pos 21U /*!< DWT CTRL: FOLDEVTENA Position */ +#define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */ + +#define DWT_CTRL_LSUEVTENA_Pos 20U /*!< DWT CTRL: LSUEVTENA Position */ +#define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */ + +#define DWT_CTRL_SLEEPEVTENA_Pos 19U /*!< DWT CTRL: SLEEPEVTENA Position */ +#define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */ + +#define DWT_CTRL_EXCEVTENA_Pos 18U /*!< DWT CTRL: EXCEVTENA Position */ +#define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */ + +#define DWT_CTRL_CPIEVTENA_Pos 17U /*!< DWT CTRL: CPIEVTENA Position */ +#define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */ + +#define DWT_CTRL_EXCTRCENA_Pos 16U /*!< DWT CTRL: EXCTRCENA Position */ +#define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */ + +#define DWT_CTRL_PCSAMPLENA_Pos 12U /*!< DWT CTRL: PCSAMPLENA Position */ +#define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */ + +#define DWT_CTRL_SYNCTAP_Pos 10U /*!< DWT CTRL: SYNCTAP Position */ +#define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */ + +#define DWT_CTRL_CYCTAP_Pos 9U /*!< DWT CTRL: CYCTAP Position */ +#define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */ + +#define DWT_CTRL_POSTINIT_Pos 5U /*!< DWT CTRL: POSTINIT Position */ +#define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */ + +#define DWT_CTRL_POSTPRESET_Pos 1U /*!< DWT CTRL: POSTPRESET Position */ +#define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */ + +#define DWT_CTRL_CYCCNTENA_Pos 0U /*!< DWT CTRL: CYCCNTENA Position */ +#define DWT_CTRL_CYCCNTENA_Msk (0x1UL /*<< DWT_CTRL_CYCCNTENA_Pos*/) /*!< DWT CTRL: CYCCNTENA Mask */ + +/* DWT CPI Count Register Definitions */ +#define DWT_CPICNT_CPICNT_Pos 0U /*!< DWT CPICNT: CPICNT Position */ +#define DWT_CPICNT_CPICNT_Msk (0xFFUL /*<< DWT_CPICNT_CPICNT_Pos*/) /*!< DWT CPICNT: CPICNT Mask */ + +/* DWT Exception Overhead Count Register Definitions */ +#define DWT_EXCCNT_EXCCNT_Pos 0U /*!< DWT EXCCNT: EXCCNT Position */ +#define DWT_EXCCNT_EXCCNT_Msk (0xFFUL /*<< DWT_EXCCNT_EXCCNT_Pos*/) /*!< DWT EXCCNT: EXCCNT Mask */ + +/* DWT Sleep Count Register Definitions */ +#define DWT_SLEEPCNT_SLEEPCNT_Pos 0U /*!< DWT SLEEPCNT: SLEEPCNT Position */ +#define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL /*<< DWT_SLEEPCNT_SLEEPCNT_Pos*/) /*!< DWT SLEEPCNT: SLEEPCNT Mask */ + +/* DWT LSU Count Register Definitions */ +#define DWT_LSUCNT_LSUCNT_Pos 0U /*!< DWT LSUCNT: LSUCNT Position */ +#define DWT_LSUCNT_LSUCNT_Msk (0xFFUL /*<< DWT_LSUCNT_LSUCNT_Pos*/) /*!< DWT LSUCNT: LSUCNT Mask */ + +/* DWT Folded-instruction Count Register Definitions */ +#define DWT_FOLDCNT_FOLDCNT_Pos 0U /*!< DWT FOLDCNT: FOLDCNT Position */ +#define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL /*<< DWT_FOLDCNT_FOLDCNT_Pos*/) /*!< DWT FOLDCNT: FOLDCNT Mask */ + +/* DWT Comparator Mask Register Definitions */ +#define DWT_MASK_MASK_Pos 0U /*!< DWT MASK: MASK Position */ +#define DWT_MASK_MASK_Msk (0x1FUL /*<< DWT_MASK_MASK_Pos*/) /*!< DWT MASK: MASK Mask */ + +/* DWT Comparator Function Register Definitions */ +#define DWT_FUNCTION_MATCHED_Pos 24U /*!< DWT FUNCTION: MATCHED Position */ +#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */ + +#define DWT_FUNCTION_DATAVADDR1_Pos 16U /*!< DWT FUNCTION: DATAVADDR1 Position */ +#define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */ + +#define DWT_FUNCTION_DATAVADDR0_Pos 12U /*!< DWT FUNCTION: DATAVADDR0 Position */ +#define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */ + +#define DWT_FUNCTION_DATAVSIZE_Pos 10U /*!< DWT FUNCTION: DATAVSIZE Position */ +#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */ + +#define DWT_FUNCTION_LNK1ENA_Pos 9U /*!< DWT FUNCTION: LNK1ENA Position */ +#define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */ + +#define DWT_FUNCTION_DATAVMATCH_Pos 8U /*!< DWT FUNCTION: DATAVMATCH Position */ +#define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */ + +#define DWT_FUNCTION_CYCMATCH_Pos 7U /*!< DWT FUNCTION: CYCMATCH Position */ +#define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */ + +#define DWT_FUNCTION_EMITRANGE_Pos 5U /*!< DWT FUNCTION: EMITRANGE Position */ +#define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */ + +#define DWT_FUNCTION_FUNCTION_Pos 0U /*!< DWT FUNCTION: FUNCTION Position */ +#define DWT_FUNCTION_FUNCTION_Msk (0xFUL /*<< DWT_FUNCTION_FUNCTION_Pos*/) /*!< DWT FUNCTION: FUNCTION Mask */ + +/*@}*/ /* end of group CMSIS_DWT */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_TPI Trace Port Interface (TPI) + \brief Type definitions for the Trace Port Interface (TPI) + @{ + */ + +/** + \brief Structure type to access the Trace Port Interface Register (TPI). + */ +typedef struct +{ + __IM uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */ + __IOM uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */ + uint32_t RESERVED0[2U]; + __IOM uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */ + uint32_t RESERVED1[55U]; + __IOM uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */ + uint32_t RESERVED2[131U]; + __IM uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */ + __IOM uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */ + __IM uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */ + uint32_t RESERVED3[759U]; + __IM uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER Register */ + __IM uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */ + __IM uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */ + uint32_t RESERVED4[1U]; + __IM uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */ + __IM uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */ + __IOM uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */ + uint32_t RESERVED5[39U]; + __IOM uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */ + __IOM uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */ + uint32_t RESERVED7[8U]; + __IM uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */ + __IM uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */ +} TPI_Type; + +/* TPI Asynchronous Clock Prescaler Register Definitions */ +#define TPI_ACPR_PRESCALER_Pos 0U /*!< TPI ACPR: PRESCALER Position */ +#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /*<< TPI_ACPR_PRESCALER_Pos*/) /*!< TPI ACPR: PRESCALER Mask */ + +/* TPI Selected Pin Protocol Register Definitions */ +#define TPI_SPPR_TXMODE_Pos 0U /*!< TPI SPPR: TXMODE Position */ +#define TPI_SPPR_TXMODE_Msk (0x3UL /*<< TPI_SPPR_TXMODE_Pos*/) /*!< TPI SPPR: TXMODE Mask */ + +/* TPI Formatter and Flush Status Register Definitions */ +#define TPI_FFSR_FtNonStop_Pos 3U /*!< TPI FFSR: FtNonStop Position */ +#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */ + +#define TPI_FFSR_TCPresent_Pos 2U /*!< TPI FFSR: TCPresent Position */ +#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */ + +#define TPI_FFSR_FtStopped_Pos 1U /*!< TPI FFSR: FtStopped Position */ +#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */ + +#define TPI_FFSR_FlInProg_Pos 0U /*!< TPI FFSR: FlInProg Position */ +#define TPI_FFSR_FlInProg_Msk (0x1UL /*<< TPI_FFSR_FlInProg_Pos*/) /*!< TPI FFSR: FlInProg Mask */ + +/* TPI Formatter and Flush Control Register Definitions */ +#define TPI_FFCR_TrigIn_Pos 8U /*!< TPI FFCR: TrigIn Position */ +#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */ + +#define TPI_FFCR_EnFCont_Pos 1U /*!< TPI FFCR: EnFCont Position */ +#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */ + +/* TPI TRIGGER Register Definitions */ +#define TPI_TRIGGER_TRIGGER_Pos 0U /*!< TPI TRIGGER: TRIGGER Position */ +#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /*<< TPI_TRIGGER_TRIGGER_Pos*/) /*!< TPI TRIGGER: TRIGGER Mask */ + +/* TPI Integration ETM Data Register Definitions (FIFO0) */ +#define TPI_FIFO0_ITM_ATVALID_Pos 29U /*!< TPI FIFO0: ITM_ATVALID Position */ +#define TPI_FIFO0_ITM_ATVALID_Msk (0x1UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */ + +#define TPI_FIFO0_ITM_bytecount_Pos 27U /*!< TPI FIFO0: ITM_bytecount Position */ +#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */ + +#define TPI_FIFO0_ETM_ATVALID_Pos 26U /*!< TPI FIFO0: ETM_ATVALID Position */ +#define TPI_FIFO0_ETM_ATVALID_Msk (0x1UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */ + +#define TPI_FIFO0_ETM_bytecount_Pos 24U /*!< TPI FIFO0: ETM_bytecount Position */ +#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */ + +#define TPI_FIFO0_ETM2_Pos 16U /*!< TPI FIFO0: ETM2 Position */ +#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */ + +#define TPI_FIFO0_ETM1_Pos 8U /*!< TPI FIFO0: ETM1 Position */ +#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */ + +#define TPI_FIFO0_ETM0_Pos 0U /*!< TPI FIFO0: ETM0 Position */ +#define TPI_FIFO0_ETM0_Msk (0xFFUL /*<< TPI_FIFO0_ETM0_Pos*/) /*!< TPI FIFO0: ETM0 Mask */ + +/* TPI ITATBCTR2 Register Definitions */ +#define TPI_ITATBCTR2_ATREADY2_Pos 0U /*!< TPI ITATBCTR2: ATREADY2 Position */ +#define TPI_ITATBCTR2_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY2_Pos*/) /*!< TPI ITATBCTR2: ATREADY2 Mask */ + +#define TPI_ITATBCTR2_ATREADY1_Pos 0U /*!< TPI ITATBCTR2: ATREADY1 Position */ +#define TPI_ITATBCTR2_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR2_ATREADY1_Pos*/) /*!< TPI ITATBCTR2: ATREADY1 Mask */ + +/* TPI Integration ITM Data Register Definitions (FIFO1) */ +#define TPI_FIFO1_ITM_ATVALID_Pos 29U /*!< TPI FIFO1: ITM_ATVALID Position */ +#define TPI_FIFO1_ITM_ATVALID_Msk (0x1UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */ + +#define TPI_FIFO1_ITM_bytecount_Pos 27U /*!< TPI FIFO1: ITM_bytecount Position */ +#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */ + +#define TPI_FIFO1_ETM_ATVALID_Pos 26U /*!< TPI FIFO1: ETM_ATVALID Position */ +#define TPI_FIFO1_ETM_ATVALID_Msk (0x1UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */ + +#define TPI_FIFO1_ETM_bytecount_Pos 24U /*!< TPI FIFO1: ETM_bytecount Position */ +#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */ + +#define TPI_FIFO1_ITM2_Pos 16U /*!< TPI FIFO1: ITM2 Position */ +#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */ + +#define TPI_FIFO1_ITM1_Pos 8U /*!< TPI FIFO1: ITM1 Position */ +#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */ + +#define TPI_FIFO1_ITM0_Pos 0U /*!< TPI FIFO1: ITM0 Position */ +#define TPI_FIFO1_ITM0_Msk (0xFFUL /*<< TPI_FIFO1_ITM0_Pos*/) /*!< TPI FIFO1: ITM0 Mask */ + +/* TPI ITATBCTR0 Register Definitions */ +#define TPI_ITATBCTR0_ATREADY2_Pos 0U /*!< TPI ITATBCTR0: ATREADY2 Position */ +#define TPI_ITATBCTR0_ATREADY2_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY2_Pos*/) /*!< TPI ITATBCTR0: ATREADY2 Mask */ + +#define TPI_ITATBCTR0_ATREADY1_Pos 0U /*!< TPI ITATBCTR0: ATREADY1 Position */ +#define TPI_ITATBCTR0_ATREADY1_Msk (0x1UL /*<< TPI_ITATBCTR0_ATREADY1_Pos*/) /*!< TPI ITATBCTR0: ATREADY1 Mask */ + +/* TPI Integration Mode Control Register Definitions */ +#define TPI_ITCTRL_Mode_Pos 0U /*!< TPI ITCTRL: Mode Position */ +#define TPI_ITCTRL_Mode_Msk (0x3UL /*<< TPI_ITCTRL_Mode_Pos*/) /*!< TPI ITCTRL: Mode Mask */ + +/* TPI DEVID Register Definitions */ +#define TPI_DEVID_NRZVALID_Pos 11U /*!< TPI DEVID: NRZVALID Position */ +#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */ + +#define TPI_DEVID_MANCVALID_Pos 10U /*!< TPI DEVID: MANCVALID Position */ +#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */ + +#define TPI_DEVID_PTINVALID_Pos 9U /*!< TPI DEVID: PTINVALID Position */ +#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */ + +#define TPI_DEVID_MinBufSz_Pos 6U /*!< TPI DEVID: MinBufSz Position */ +#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */ + +#define TPI_DEVID_AsynClkIn_Pos 5U /*!< TPI DEVID: AsynClkIn Position */ +#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */ + +#define TPI_DEVID_NrTraceInput_Pos 0U /*!< TPI DEVID: NrTraceInput Position */ +#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /*<< TPI_DEVID_NrTraceInput_Pos*/) /*!< TPI DEVID: NrTraceInput Mask */ + +/* TPI DEVTYPE Register Definitions */ +#define TPI_DEVTYPE_SubType_Pos 4U /*!< TPI DEVTYPE: SubType Position */ +#define TPI_DEVTYPE_SubType_Msk (0xFUL /*<< TPI_DEVTYPE_SubType_Pos*/) /*!< TPI DEVTYPE: SubType Mask */ + +#define TPI_DEVTYPE_MajorType_Pos 0U /*!< TPI DEVTYPE: MajorType Position */ +#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */ + +/*@}*/ /* end of group CMSIS_TPI */ + + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_MPU Memory Protection Unit (MPU) + \brief Type definitions for the Memory Protection Unit (MPU) + @{ + */ + +/** + \brief Structure type to access the Memory Protection Unit (MPU). + */ +typedef struct +{ + __IM uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */ + __IOM uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */ + __IOM uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */ + __IOM uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */ + __IOM uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */ + __IOM uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */ + __IOM uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */ + __IOM uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */ + __IOM uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */ + __IOM uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */ +} MPU_Type; + +/* MPU Type Register Definitions */ +#define MPU_TYPE_IREGION_Pos 16U /*!< MPU TYPE: IREGION Position */ +#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */ + +#define MPU_TYPE_DREGION_Pos 8U /*!< MPU TYPE: DREGION Position */ +#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */ + +#define MPU_TYPE_SEPARATE_Pos 0U /*!< MPU TYPE: SEPARATE Position */ +#define MPU_TYPE_SEPARATE_Msk (1UL /*<< MPU_TYPE_SEPARATE_Pos*/) /*!< MPU TYPE: SEPARATE Mask */ + +/* MPU Control Register Definitions */ +#define MPU_CTRL_PRIVDEFENA_Pos 2U /*!< MPU CTRL: PRIVDEFENA Position */ +#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */ + +#define MPU_CTRL_HFNMIENA_Pos 1U /*!< MPU CTRL: HFNMIENA Position */ +#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */ + +#define MPU_CTRL_ENABLE_Pos 0U /*!< MPU CTRL: ENABLE Position */ +#define MPU_CTRL_ENABLE_Msk (1UL /*<< MPU_CTRL_ENABLE_Pos*/) /*!< MPU CTRL: ENABLE Mask */ + +/* MPU Region Number Register Definitions */ +#define MPU_RNR_REGION_Pos 0U /*!< MPU RNR: REGION Position */ +#define MPU_RNR_REGION_Msk (0xFFUL /*<< MPU_RNR_REGION_Pos*/) /*!< MPU RNR: REGION Mask */ + +/* MPU Region Base Address Register Definitions */ +#define MPU_RBAR_ADDR_Pos 5U /*!< MPU RBAR: ADDR Position */ +#define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */ + +#define MPU_RBAR_VALID_Pos 4U /*!< MPU RBAR: VALID Position */ +#define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */ + +#define MPU_RBAR_REGION_Pos 0U /*!< MPU RBAR: REGION Position */ +#define MPU_RBAR_REGION_Msk (0xFUL /*<< MPU_RBAR_REGION_Pos*/) /*!< MPU RBAR: REGION Mask */ + +/* MPU Region Attribute and Size Register Definitions */ +#define MPU_RASR_ATTRS_Pos 16U /*!< MPU RASR: MPU Region Attribute field Position */ +#define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */ + +#define MPU_RASR_XN_Pos 28U /*!< MPU RASR: ATTRS.XN Position */ +#define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */ + +#define MPU_RASR_AP_Pos 24U /*!< MPU RASR: ATTRS.AP Position */ +#define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */ + +#define MPU_RASR_TEX_Pos 19U /*!< MPU RASR: ATTRS.TEX Position */ +#define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */ + +#define MPU_RASR_S_Pos 18U /*!< MPU RASR: ATTRS.S Position */ +#define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */ + +#define MPU_RASR_C_Pos 17U /*!< MPU RASR: ATTRS.C Position */ +#define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */ + +#define MPU_RASR_B_Pos 16U /*!< MPU RASR: ATTRS.B Position */ +#define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */ + +#define MPU_RASR_SRD_Pos 8U /*!< MPU RASR: Sub-Region Disable Position */ +#define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */ + +#define MPU_RASR_SIZE_Pos 1U /*!< MPU RASR: Region Size Field Position */ +#define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */ + +#define MPU_RASR_ENABLE_Pos 0U /*!< MPU RASR: Region enable bit Position */ +#define MPU_RASR_ENABLE_Msk (1UL /*<< MPU_RASR_ENABLE_Pos*/) /*!< MPU RASR: Region enable bit Disable Mask */ + +/*@} end of group CMSIS_MPU */ +#endif + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug) + \brief Type definitions for the Core Debug Registers + @{ + */ + +/** + \brief Structure type to access the Core Debug Register (CoreDebug). + */ +typedef struct +{ + __IOM uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */ + __OM uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */ + __IOM uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */ + __IOM uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */ +} CoreDebug_Type; + +/* Debug Halting Control and Status Register Definitions */ +#define CoreDebug_DHCSR_DBGKEY_Pos 16U /*!< CoreDebug DHCSR: DBGKEY Position */ +#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */ + +#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /*!< CoreDebug DHCSR: S_RESET_ST Position */ +#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */ + +#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /*!< CoreDebug DHCSR: S_RETIRE_ST Position */ +#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */ + +#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /*!< CoreDebug DHCSR: S_LOCKUP Position */ +#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */ + +#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /*!< CoreDebug DHCSR: S_SLEEP Position */ +#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */ + +#define CoreDebug_DHCSR_S_HALT_Pos 17U /*!< CoreDebug DHCSR: S_HALT Position */ +#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */ + +#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /*!< CoreDebug DHCSR: S_REGRDY Position */ +#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */ + +#define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5U /*!< CoreDebug DHCSR: C_SNAPSTALL Position */ +#define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */ + +#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /*!< CoreDebug DHCSR: C_MASKINTS Position */ +#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */ + +#define CoreDebug_DHCSR_C_STEP_Pos 2U /*!< CoreDebug DHCSR: C_STEP Position */ +#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */ + +#define CoreDebug_DHCSR_C_HALT_Pos 1U /*!< CoreDebug DHCSR: C_HALT Position */ +#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */ + +#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /*!< CoreDebug DHCSR: C_DEBUGEN Position */ +#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /*<< CoreDebug_DHCSR_C_DEBUGEN_Pos*/) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */ + +/* Debug Core Register Selector Register Definitions */ +#define CoreDebug_DCRSR_REGWnR_Pos 16U /*!< CoreDebug DCRSR: REGWnR Position */ +#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */ + +#define CoreDebug_DCRSR_REGSEL_Pos 0U /*!< CoreDebug DCRSR: REGSEL Position */ +#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /*<< CoreDebug_DCRSR_REGSEL_Pos*/) /*!< CoreDebug DCRSR: REGSEL Mask */ + +/* Debug Exception and Monitor Control Register Definitions */ +#define CoreDebug_DEMCR_TRCENA_Pos 24U /*!< CoreDebug DEMCR: TRCENA Position */ +#define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */ + +#define CoreDebug_DEMCR_MON_REQ_Pos 19U /*!< CoreDebug DEMCR: MON_REQ Position */ +#define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */ + +#define CoreDebug_DEMCR_MON_STEP_Pos 18U /*!< CoreDebug DEMCR: MON_STEP Position */ +#define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */ + +#define CoreDebug_DEMCR_MON_PEND_Pos 17U /*!< CoreDebug DEMCR: MON_PEND Position */ +#define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */ + +#define CoreDebug_DEMCR_MON_EN_Pos 16U /*!< CoreDebug DEMCR: MON_EN Position */ +#define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */ + +#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /*!< CoreDebug DEMCR: VC_HARDERR Position */ +#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */ + +#define CoreDebug_DEMCR_VC_INTERR_Pos 9U /*!< CoreDebug DEMCR: VC_INTERR Position */ +#define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */ + +#define CoreDebug_DEMCR_VC_BUSERR_Pos 8U /*!< CoreDebug DEMCR: VC_BUSERR Position */ +#define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */ + +#define CoreDebug_DEMCR_VC_STATERR_Pos 7U /*!< CoreDebug DEMCR: VC_STATERR Position */ +#define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */ + +#define CoreDebug_DEMCR_VC_CHKERR_Pos 6U /*!< CoreDebug DEMCR: VC_CHKERR Position */ +#define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */ + +#define CoreDebug_DEMCR_VC_NOCPERR_Pos 5U /*!< CoreDebug DEMCR: VC_NOCPERR Position */ +#define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */ + +#define CoreDebug_DEMCR_VC_MMERR_Pos 4U /*!< CoreDebug DEMCR: VC_MMERR Position */ +#define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */ + +#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /*!< CoreDebug DEMCR: VC_CORERESET Position */ +#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /*<< CoreDebug_DEMCR_VC_CORERESET_Pos*/) /*!< CoreDebug DEMCR: VC_CORERESET Mask */ + +/*@} end of group CMSIS_CoreDebug */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_bitfield Core register bit field macros + \brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk). + @{ + */ + +/** + \brief Mask and shift a bit field value for use in a register bit range. + \param[in] field Name of the register bit field. + \param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type. + \return Masked and shifted value. +*/ +#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk) + +/** + \brief Mask and shift a register value to extract a bit filed value. + \param[in] field Name of the register bit field. + \param[in] value Value of register. This parameter is interpreted as an uint32_t type. + \return Masked and shifted bit field value. +*/ +#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos) + +/*@} end of group CMSIS_core_bitfield */ + + +/** + \ingroup CMSIS_core_register + \defgroup CMSIS_core_base Core Definitions + \brief Definitions for base addresses, unions, and structures. + @{ + */ + +/* Memory mapping of Core Hardware */ +#define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */ +#define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */ +#define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */ +#define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */ +#define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */ +#define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */ +#define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */ +#define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */ + +#define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */ +#define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */ +#define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */ +#define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */ +#define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */ +#define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */ +#define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */ +#define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */ + +#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U) + #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */ + #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */ +#endif + +/*@} */ + + + +/******************************************************************************* + * Hardware Abstraction Layer + Core Function Interface contains: + - Core NVIC Functions + - Core SysTick Functions + - Core Debug Functions + - Core Register Access Functions + ******************************************************************************/ +/** + \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference +*/ + + + +/* ########################## NVIC functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_NVICFunctions NVIC Functions + \brief Functions that manage interrupts and exceptions via the NVIC. + @{ + */ + +#ifdef CMSIS_NVIC_VIRTUAL + #ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE + #define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h" + #endif + #include CMSIS_NVIC_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping + #define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping + #define NVIC_EnableIRQ __NVIC_EnableIRQ + #define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ + #define NVIC_DisableIRQ __NVIC_DisableIRQ + #define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ + #define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ + #define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ + #define NVIC_GetActive __NVIC_GetActive + #define NVIC_SetPriority __NVIC_SetPriority + #define NVIC_GetPriority __NVIC_GetPriority + #define NVIC_SystemReset __NVIC_SystemReset +#endif /* CMSIS_NVIC_VIRTUAL */ + +#ifdef CMSIS_VECTAB_VIRTUAL + #ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE + #define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h" + #endif + #include CMSIS_VECTAB_VIRTUAL_HEADER_FILE +#else + #define NVIC_SetVector __NVIC_SetVector + #define NVIC_GetVector __NVIC_GetVector +#endif /* (CMSIS_VECTAB_VIRTUAL) */ + +#define NVIC_USER_IRQ_OFFSET 16 + + +/* The following EXC_RETURN values are saved the LR on exception entry */ +#define EXC_RETURN_HANDLER (0xFFFFFFF1UL) /* return to Handler mode, uses MSP after return */ +#define EXC_RETURN_THREAD_MSP (0xFFFFFFF9UL) /* return to Thread mode, uses MSP after return */ +#define EXC_RETURN_THREAD_PSP (0xFFFFFFFDUL) /* return to Thread mode, uses PSP after return */ + + +/** + \brief Set Priority Grouping + \details Sets the priority grouping field using the required unlock sequence. + The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field. + Only values from 0..7 are used. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Priority grouping field. + */ +__STATIC_INLINE void __NVIC_SetPriorityGrouping(uint32_t PriorityGroup) +{ + uint32_t reg_value; + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + + reg_value = SCB->AIRCR; /* read old register configuration */ + reg_value &= ~((uint32_t)(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk)); /* clear bits to change */ + reg_value = (reg_value | + ((uint32_t)0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (PriorityGroupTmp << SCB_AIRCR_PRIGROUP_Pos) ); /* Insert write key and priority group */ + SCB->AIRCR = reg_value; +} + + +/** + \brief Get Priority Grouping + \details Reads the priority grouping field from the NVIC Interrupt Controller. + \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field). + */ +__STATIC_INLINE uint32_t __NVIC_GetPriorityGrouping(void) +{ + return ((uint32_t)((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos)); +} + + +/** + \brief Enable Interrupt + \details Enables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + __COMPILER_BARRIER(); + NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __COMPILER_BARRIER(); + } +} + + +/** + \brief Get Interrupt Enable status + \details Returns a device specific interrupt enable status from the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt is not enabled. + \return 1 Interrupt is enabled. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Disable Interrupt + \details Disables a device specific interrupt in the NVIC interrupt controller. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + __DSB(); + __ISB(); + } +} + + +/** + \brief Get Pending Interrupt + \details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not pending. + \return 1 Interrupt status is pending. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Pending Interrupt + \details Sets the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Clear Pending Interrupt + \details Clears the pending bit of a device specific interrupt in the NVIC pending register. + \param [in] IRQn Device specific interrupt number. + \note IRQn must not be negative. + */ +__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)); + } +} + + +/** + \brief Get Active Interrupt + \details Reads the active register in the NVIC and returns the active bit for the device specific interrupt. + \param [in] IRQn Device specific interrupt number. + \return 0 Interrupt status is not active. + \return 1 Interrupt status is active. + \note IRQn must not be negative. + */ +__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn) +{ + if ((int32_t)(IRQn) >= 0) + { + return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL)); + } + else + { + return(0U); + } +} + + +/** + \brief Set Interrupt Priority + \details Sets the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \param [in] priority Priority to set. + \note The priority cannot be set for every processor exception. + */ +__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority) +{ + if ((int32_t)(IRQn) >= 0) + { + NVIC->IP[((uint32_t)IRQn)] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } + else + { + SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] = (uint8_t)((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL); + } +} + + +/** + \brief Get Interrupt Priority + \details Reads the priority of a device specific interrupt or a processor exception. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Interrupt Priority. + Value is aligned automatically to the implemented priority bits of the microcontroller. + */ +__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn) +{ + + if ((int32_t)(IRQn) >= 0) + { + return(((uint32_t)NVIC->IP[((uint32_t)IRQn)] >> (8U - __NVIC_PRIO_BITS))); + } + else + { + return(((uint32_t)SCB->SHP[(((uint32_t)IRQn) & 0xFUL)-4UL] >> (8U - __NVIC_PRIO_BITS))); + } +} + + +/** + \brief Encode Priority + \details Encodes the priority for an interrupt with the given priority group, + preemptive priority value, and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set. + \param [in] PriorityGroup Used priority group. + \param [in] PreemptPriority Preemptive priority value (starting from 0). + \param [in] SubPriority Subpriority value (starting from 0). + \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority(). + */ +__STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + return ( + ((PreemptPriority & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL)) << SubPriorityBits) | + ((SubPriority & (uint32_t)((1UL << (SubPriorityBits )) - 1UL))) + ); +} + + +/** + \brief Decode Priority + \details Decodes an interrupt priority value with a given priority group to + preemptive priority value and subpriority value. + In case of a conflict between priority grouping and available + priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set. + \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority(). + \param [in] PriorityGroup Used priority group. + \param [out] pPreemptPriority Preemptive priority value (starting from 0). + \param [out] pSubPriority Subpriority value (starting from 0). + */ +__STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* const pPreemptPriority, uint32_t* const pSubPriority) +{ + uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07UL); /* only values 0..7 are used */ + uint32_t PreemptPriorityBits; + uint32_t SubPriorityBits; + + PreemptPriorityBits = ((7UL - PriorityGroupTmp) > (uint32_t)(__NVIC_PRIO_BITS)) ? (uint32_t)(__NVIC_PRIO_BITS) : (uint32_t)(7UL - PriorityGroupTmp); + SubPriorityBits = ((PriorityGroupTmp + (uint32_t)(__NVIC_PRIO_BITS)) < (uint32_t)7UL) ? (uint32_t)0UL : (uint32_t)((PriorityGroupTmp - 7UL) + (uint32_t)(__NVIC_PRIO_BITS)); + + *pPreemptPriority = (Priority >> SubPriorityBits) & (uint32_t)((1UL << (PreemptPriorityBits)) - 1UL); + *pSubPriority = (Priority ) & (uint32_t)((1UL << (SubPriorityBits )) - 1UL); +} + + +/** + \brief Set Interrupt Vector + \details Sets an interrupt vector in SRAM based interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + VTOR must been relocated to SRAM before. + \param [in] IRQn Interrupt number + \param [in] vector Address of interrupt handler function + */ +__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + (* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)) = vector; + /* ARM Application Note 321 states that the M3 does not require the architectural barrier */ +} + + +/** + \brief Get Interrupt Vector + \details Reads an interrupt vector from interrupt vector table. + The interrupt number can be positive to specify a device specific interrupt, + or negative to specify a processor exception. + \param [in] IRQn Interrupt number. + \return Address of interrupt handler function + */ +__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn) +{ + uint32_t vectors = (uint32_t )SCB->VTOR; + return (uint32_t)(* (int *) (vectors + ((int32_t)IRQn + NVIC_USER_IRQ_OFFSET) * 4)); +} + + +/** + \brief System Reset + \details Initiates a system reset request to reset the MCU. + */ +__NO_RETURN __STATIC_INLINE void __NVIC_SystemReset(void) +{ + __DSB(); /* Ensure all outstanding memory accesses included + buffered write are completed before reset */ + SCB->AIRCR = (uint32_t)((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) | + (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) | + SCB_AIRCR_SYSRESETREQ_Msk ); /* Keep priority group unchanged */ + __DSB(); /* Ensure completion of memory access */ + + for(;;) /* wait until reset */ + { + __NOP(); + } +} + +/*@} end of CMSIS_Core_NVICFunctions */ + + +/* ########################## FPU functions #################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_FpuFunctions FPU Functions + \brief Function that provides FPU type. + @{ + */ + +/** + \brief get FPU type + \details returns the FPU type + \returns + - \b 0: No FPU + - \b 1: Single precision FPU + - \b 2: Double + Single precision FPU + */ +__STATIC_INLINE uint32_t SCB_GetFPUType(void) +{ + return 0U; /* No FPU */ +} + + +/*@} end of CMSIS_Core_FpuFunctions */ + + + +/* ################################## SysTick function ############################################ */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_Core_SysTickFunctions SysTick Functions + \brief Functions that configure the System. + @{ + */ + +#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U) + +/** + \brief System Tick Configuration + \details Initializes the System Timer and its interrupt, and starts the System Tick Timer. + Counter is in free running mode to generate periodic interrupts. + \param [in] ticks Number of ticks between two interrupts. + \return 0 Function succeeded. + \return 1 Function failed. + \note When the variable __Vendor_SysTickConfig is set to 1, then the + function SysTick_Config is not included. In this case, the file device.h + must contain a vendor-specific implementation of this function. + */ +__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks) +{ + if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk) + { + return (1UL); /* Reload value impossible */ + } + + SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */ + NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */ + SysTick->VAL = 0UL; /* Load the SysTick Counter Value */ + SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk | + SysTick_CTRL_TICKINT_Msk | + SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */ + return (0UL); /* Function successful */ +} + +#endif + +/*@} end of CMSIS_Core_SysTickFunctions */ + + + +/* ##################################### Debug In/Output function ########################################### */ +/** + \ingroup CMSIS_Core_FunctionInterface + \defgroup CMSIS_core_DebugFunctions ITM Functions + \brief Functions that access the ITM debug interface. + @{ + */ + +extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */ +#define ITM_RXBUFFER_EMPTY ((int32_t)0x5AA55AA5U) /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */ + + +/** + \brief ITM Send Character + \details Transmits a character via the ITM channel 0, and + \li Just returns when no debugger is connected that has booked the output. + \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted. + \param [in] ch Character to transmit. + \returns Character to transmit. + */ +__STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch) +{ + if (((ITM->TCR & ITM_TCR_ITMENA_Msk) != 0UL) && /* ITM enabled */ + ((ITM->TER & 1UL ) != 0UL) ) /* ITM Port #0 enabled */ + { + while (ITM->PORT[0U].u32 == 0UL) + { + __NOP(); + } + ITM->PORT[0U].u8 = (uint8_t)ch; + } + return (ch); +} + + +/** + \brief ITM Receive Character + \details Inputs a character via the external variable \ref ITM_RxBuffer. + \return Received character. + \return -1 No character pending. + */ +__STATIC_INLINE int32_t ITM_ReceiveChar (void) +{ + int32_t ch = -1; /* no character available */ + + if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) + { + ch = ITM_RxBuffer; + ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */ + } + + return (ch); +} + + +/** + \brief ITM Check Character + \details Checks whether a character is pending for reading in the variable \ref ITM_RxBuffer. + \return 0 No character available. + \return 1 Character available. + */ +__STATIC_INLINE int32_t ITM_CheckChar (void) +{ + + if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) + { + return (0); /* no character available */ + } + else + { + return (1); /* character available */ + } +} + +/*@} end of CMSIS_core_DebugFunctions */ + + + + +#ifdef __cplusplus +} +#endif + +#endif /* __CORE_SC300_H_DEPENDANT */ + +#endif /* __CMSIS_GENERIC */ diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/mpu_armv7.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/mpu_armv7.h new file mode 100644 index 0000000000000000000000000000000000000000..66ef59b4a0bff6e7f2d077cbaa235b55f5e1bfb2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/mpu_armv7.h @@ -0,0 +1,272 @@ +/****************************************************************************** + * @file mpu_armv7.h + * @brief CMSIS MPU API for Armv7-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV7_H +#define ARM_MPU_ARMV7_H + +#define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes +#define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes +#define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes +#define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes +#define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes +#define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte +#define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes +#define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes +#define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes +#define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes +#define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes +#define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes +#define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes +#define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes +#define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes +#define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte +#define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes +#define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes +#define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes +#define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes +#define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes +#define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes +#define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes +#define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes +#define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes +#define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte +#define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes +#define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes + +#define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access +#define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only +#define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only +#define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access +#define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only +#define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access + +/** MPU Region Base Address Register Value +* +* \param Region The region to be configured, number 0 to 15. +* \param BaseAddress The base address for the region. +*/ +#define ARM_MPU_RBAR(Region, BaseAddress) \ + (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \ + ((Region) & MPU_RBAR_REGION_Msk) | \ + (MPU_RBAR_VALID_Msk)) + +/** +* MPU Memory Access Attributes +* +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +*/ +#define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \ + ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \ + (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \ + (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \ + (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk)) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \ + ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \ + (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \ + (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \ + (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \ + (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \ + (((MPU_RASR_ENABLE_Msk)))) + +/** +* MPU Region Attribute and Size Register Value +* +* \param DisableExec Instruction access disable bit, 1= disable instruction fetches. +* \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode. +* \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral. +* \param IsShareable Region is shareable between multiple bus masters. +* \param IsCacheable Region is cacheable, i.e. its value may be kept in cache. +* \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy. +* \param SubRegionDisable Sub-region disable field. +* \param Size Region size of the region to be configured, for example 4K, 8K. +*/ +#define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \ + ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size) + +/** +* MPU Memory Access Attribute for strongly ordered memory. +* - TEX: 000b +* - Shareable +* - Non-cacheable +* - Non-bufferable +*/ +#define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U) + +/** +* MPU Memory Access Attribute for device memory. +* - TEX: 000b (if shareable) or 010b (if non-shareable) +* - Shareable or non-shareable +* - Non-cacheable +* - Bufferable (if shareable) or non-bufferable (if non-shareable) +* +* \param IsShareable Configures the device memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U)) + +/** +* MPU Memory Access Attribute for normal memory. +* - TEX: 1BBb (reflecting outer cacheability rules) +* - Shareable or non-shareable +* - Cacheable or non-cacheable (reflecting inner cacheability rules) +* - Bufferable or non-bufferable (reflecting inner cacheability rules) +* +* \param OuterCp Configures the outer cache policy. +* \param InnerCp Configures the inner cache policy. +* \param IsShareable Configures the memory as shareable or non-shareable. +*/ +#define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U)) + +/** +* MPU Memory Access Attribute non-cacheable policy. +*/ +#define ARM_MPU_CACHEP_NOCACHE 0U + +/** +* MPU Memory Access Attribute write-back, write and read allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_WRA 1U + +/** +* MPU Memory Access Attribute write-through, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WT_NWA 2U + +/** +* MPU Memory Access Attribute write-back, no write allocate policy. +*/ +#define ARM_MPU_CACHEP_WB_NWA 3U + + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; //!< The region base address register value (RBAR) + uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + MPU->RNR = rnr; + MPU->RASR = 0U; +} + +/** Configure an MPU region. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr) +{ + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rsar Value for RSAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr) +{ + MPU->RNR = rnr; + MPU->RBAR = rbar; + MPU->RASR = rasr; +} + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + while (cnt > MPU_TYPE_RALIASES) { + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize); + table += MPU_TYPE_RALIASES; + cnt -= MPU_TYPE_RALIASES; + } + ARM_MPU_OrderedMemcpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize); +} + +#endif diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/mpu_armv8.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/mpu_armv8.h new file mode 100644 index 0000000000000000000000000000000000000000..0041d4dc6ff536afb59c5863d21f6ced2b42531f --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/mpu_armv8.h @@ -0,0 +1,346 @@ +/****************************************************************************** + * @file mpu_armv8.h + * @brief CMSIS MPU API for Armv8-M and Armv8.1-M MPU + * @version V5.1.0 + * @date 08. March 2019 + ******************************************************************************/ +/* + * Copyright (c) 2017-2019 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef ARM_MPU_ARMV8_H +#define ARM_MPU_ARMV8_H + +/** \brief Attribute for device memory (outer only) */ +#define ARM_MPU_ATTR_DEVICE ( 0U ) + +/** \brief Attribute for non-cacheable, normal memory */ +#define ARM_MPU_ATTR_NON_CACHEABLE ( 4U ) + +/** \brief Attribute for normal memory (outer and inner) +* \param NT Non-Transient: Set to 1 for non-transient data. +* \param WB Write-Back: Set to 1 to use write-back update policy. +* \param RA Read Allocation: Set to 1 to use cache allocation on read miss. +* \param WA Write Allocation: Set to 1 to use cache allocation on write miss. +*/ +#define ARM_MPU_ATTR_MEMORY_(NT, WB, RA, WA) \ + (((NT & 1U) << 3U) | ((WB & 1U) << 2U) | ((RA & 1U) << 1U) | (WA & 1U)) + +/** \brief Device memory type non Gathering, non Re-ordering, non Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRnE (0U) + +/** \brief Device memory type non Gathering, non Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGnRE (1U) + +/** \brief Device memory type non Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_nGRE (2U) + +/** \brief Device memory type Gathering, Re-ordering, Early Write Acknowledgement */ +#define ARM_MPU_ATTR_DEVICE_GRE (3U) + +/** \brief Memory Attribute +* \param O Outer memory attributes +* \param I O == ARM_MPU_ATTR_DEVICE: Device memory attributes, else: Inner memory attributes +*/ +#define ARM_MPU_ATTR(O, I) (((O & 0xFU) << 4U) | (((O & 0xFU) != 0U) ? (I & 0xFU) : ((I & 0x3U) << 2U))) + +/** \brief Normal memory non-shareable */ +#define ARM_MPU_SH_NON (0U) + +/** \brief Normal memory outer shareable */ +#define ARM_MPU_SH_OUTER (2U) + +/** \brief Normal memory inner shareable */ +#define ARM_MPU_SH_INNER (3U) + +/** \brief Memory access permissions +* \param RO Read-Only: Set to 1 for read-only memory. +* \param NP Non-Privileged: Set to 1 for non-privileged memory. +*/ +#define ARM_MPU_AP_(RO, NP) (((RO & 1U) << 1U) | (NP & 1U)) + +/** \brief Region Base Address Register value +* \param BASE The base address bits [31:5] of a memory region. The value is zero extended. Effective address gets 32 byte aligned. +* \param SH Defines the Shareability domain for this memory region. +* \param RO Read-Only: Set to 1 for a read-only memory region. +* \param NP Non-Privileged: Set to 1 for a non-privileged memory region. +* \oaram XN eXecute Never: Set to 1 for a non-executable memory region. +*/ +#define ARM_MPU_RBAR(BASE, SH, RO, NP, XN) \ + ((BASE & MPU_RBAR_BASE_Msk) | \ + ((SH << MPU_RBAR_SH_Pos) & MPU_RBAR_SH_Msk) | \ + ((ARM_MPU_AP_(RO, NP) << MPU_RBAR_AP_Pos) & MPU_RBAR_AP_Msk) | \ + ((XN << MPU_RBAR_XN_Pos) & MPU_RBAR_XN_Msk)) + +/** \brief Region Limit Address Register value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR(LIMIT, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#if defined(MPU_RLAR_PXN_Pos) + +/** \brief Region Limit Address Register with PXN value +* \param LIMIT The limit address bits [31:5] for this memory region. The value is one extended. +* \param PXN Privileged execute never. Defines whether code can be executed from this privileged region. +* \param IDX The attribute index to be associated with this memory region. +*/ +#define ARM_MPU_RLAR_PXN(LIMIT, PXN, IDX) \ + ((LIMIT & MPU_RLAR_LIMIT_Msk) | \ + ((PXN << MPU_RLAR_PXN_Pos) & MPU_RLAR_PXN_Msk) | \ + ((IDX << MPU_RLAR_AttrIndx_Pos) & MPU_RLAR_AttrIndx_Msk) | \ + (MPU_RLAR_EN_Msk)) + +#endif + +/** +* Struct for a single MPU Region +*/ +typedef struct { + uint32_t RBAR; /*!< Region Base Address Register value */ + uint32_t RLAR; /*!< Region Limit Address Register value */ +} ARM_MPU_Region_t; + +/** Enable the MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control) +{ + MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} + +#ifdef MPU_NS +/** Enable the Non-secure MPU. +* \param MPU_Control Default access permissions for unconfigured regions. +*/ +__STATIC_INLINE void ARM_MPU_Enable_NS(uint32_t MPU_Control) +{ + MPU_NS->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk; +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk; +#endif + __DSB(); + __ISB(); +} + +/** Disable the Non-secure MPU. +*/ +__STATIC_INLINE void ARM_MPU_Disable_NS(void) +{ + __DMB(); +#ifdef SCB_SHCSR_MEMFAULTENA_Msk + SCB_NS->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk; +#endif + MPU_NS->CTRL &= ~MPU_CTRL_ENABLE_Msk; +} +#endif + +/** Set the memory attribute encoding to the given MPU. +* \param mpu Pointer to the MPU to be configured. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttrEx(MPU_Type* mpu, uint8_t idx, uint8_t attr) +{ + const uint8_t reg = idx / 4U; + const uint32_t pos = ((idx % 4U) * 8U); + const uint32_t mask = 0xFFU << pos; + + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { + return; // invalid index + } + + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); +} + +/** Set the memory attribute encoding. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU, idx, attr); +} + +#ifdef MPU_NS +/** Set the memory attribute encoding to the Non-secure MPU. +* \param idx The attribute index to be set [0-7] +* \param attr The attribute value to be set. +*/ +__STATIC_INLINE void ARM_MPU_SetMemAttr_NS(uint8_t idx, uint8_t attr) +{ + ARM_MPU_SetMemAttrEx(MPU_NS, idx, attr); +} +#endif + +/** Clear and disable the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) +{ + mpu->RNR = rnr; + mpu->RLAR = 0U; +} + +/** Clear and disable the given MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU, rnr); +} + +#ifdef MPU_NS +/** Clear and disable the given Non-secure MPU region. +* \param rnr Region number to be cleared. +*/ +__STATIC_INLINE void ARM_MPU_ClrRegion_NS(uint32_t rnr) +{ + ARM_MPU_ClrRegionEx(MPU_NS, rnr); +} +#endif + +/** Configure the given MPU region of the given MPU. +* \param mpu Pointer to MPU to be used. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; +} + +/** Configure the given MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU, rnr, rbar, rlar); +} + +#ifdef MPU_NS +/** Configure the given Non-secure MPU region. +* \param rnr Region number to be configured. +* \param rbar Value for RBAR register. +* \param rlar Value for RLAR register. +*/ +__STATIC_INLINE void ARM_MPU_SetRegion_NS(uint32_t rnr, uint32_t rbar, uint32_t rlar) +{ + ARM_MPU_SetRegionEx(MPU_NS, rnr, rbar, rlar); +} +#endif + +/** Memcopy with strictly ordered memory access, e.g. for register targets. +* \param dst Destination data is copied to. +* \param src Source data is copied from. +* \param len Amount of data words to be copied. +*/ +__STATIC_INLINE void ARM_MPU_OrderedMemcpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len) +{ + uint32_t i; + for (i = 0U; i < len; ++i) + { + dst[i] = src[i]; + } +} + +/** Load the given number of MPU regions from a table to the given MPU. +* \param mpu Pointer to the MPU registers to be used. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + if (cnt == 1U) { + mpu->RNR = rnr; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); + } else { + uint32_t rnrBase = rnr & ~(MPU_TYPE_RALIASES-1U); + uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; + + mpu->RNR = rnrBase; + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + uint32_t c = MPU_TYPE_RALIASES - rnrOffset; + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; + } + + ARM_MPU_OrderedMemcpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + } +} + +/** Load the given number of MPU regions from a table. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU, rnr, table, cnt); +} + +#ifdef MPU_NS +/** Load the given number of MPU regions from a table to the Non-secure MPU. +* \param rnr First region number to be configured. +* \param table Pointer to the MPU configuration table. +* \param cnt Amount of regions to be configured. +*/ +__STATIC_INLINE void ARM_MPU_Load_NS(uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) +{ + ARM_MPU_LoadEx(MPU_NS, rnr, table, cnt); +} +#endif + +#endif + diff --git a/bsp/hc32f4a0/Libraries/CMSIS/Include/tz_context.h b/bsp/hc32f4a0/Libraries/CMSIS/Include/tz_context.h new file mode 100644 index 0000000000000000000000000000000000000000..0d09749f3a5066f0e061783a1e67972b72ab61a7 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/CMSIS/Include/tz_context.h @@ -0,0 +1,70 @@ +/****************************************************************************** + * @file tz_context.h + * @brief Context Management for Armv8-M TrustZone + * @version V1.0.1 + * @date 10. January 2018 + ******************************************************************************/ +/* + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Licensed under the Apache License, Version 2.0 (the License); you may + * not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an AS IS BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + +#ifndef TZ_CONTEXT_H +#define TZ_CONTEXT_H + +#include + +#ifndef TZ_MODULEID_T +#define TZ_MODULEID_T +/// \details Data type that identifies secure software modules called by a process. +typedef uint32_t TZ_ModuleId_t; +#endif + +/// \details TZ Memory ID identifies an allocated memory slot. +typedef uint32_t TZ_MemoryId_t; + +/// Initialize secure context memory system +/// \return execution status (1: success, 0: error) +uint32_t TZ_InitContextSystem_S (void); + +/// Allocate context memory for calling secure software modules in TrustZone +/// \param[in] module identifies software modules called from non-secure mode +/// \return value != 0 id TrustZone memory slot identifier +/// \return value 0 no memory available or internal error +TZ_MemoryId_t TZ_AllocModuleContext_S (TZ_ModuleId_t module); + +/// Free context memory that was previously allocated with \ref TZ_AllocModuleContext_S +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_FreeModuleContext_S (TZ_MemoryId_t id); + +/// Load secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_LoadContext_S (TZ_MemoryId_t id); + +/// Store secure context (called on RTOS thread context switch) +/// \param[in] id TrustZone memory slot identifier +/// \return execution status (1: success, 0: error) +uint32_t TZ_StoreContext_S (TZ_MemoryId_t id); + +#endif // TZ_CONTEXT_H diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_adc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_adc.h new file mode 100644 index 0000000000000000000000000000000000000000..7d5610fcbecc163ec1a08153e5e6565bec6fe632 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_adc.h @@ -0,0 +1,601 @@ +/** + ******************************************************************************* + * @file hc32f4a0_adc.h + * @brief This file contains all the functions prototypes of the ADC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-12-15 Wuze ADC_ComTriggerCmd() refine. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_ADC_H__ +#define __HC32F4A0_ADC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_ADC + * @{ + */ + +#if (DDL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Types ADC Global Types + * @{ + */ + +/** + * @brief Structure definition of ADC initialization. + */ +typedef struct +{ + uint16_t u16ScanMode; /*!< Configures the scan convert mode of ADC. + This parameter can be a value of @ref ADC_Scan_Convert_Mode */ + uint16_t u16Resolution; /*!< Configures the ADC resolution. + This parameter can be a value of @ref ADC_Resolution */ + uint16_t u16AutoClrCmd; /*!< Configures whether the ADC data register is + automatically cleared after the data is read. + This parameter can be a value of @ref ADC_Data_Auto_Clear_Cmd */ + uint16_t u16DataAlign; /*!< Specifies ADC data alignment to right or to left. + This parameter can be a value of @ref ADC_Data_Alignment */ + uint16_t u16SAResumePos; /*!< Specifies the resume channel position of sequence A. + Sequence A can be interrupted by sequence B. After the + the ending of sequence B, sequence A resumes from the + specified channel position. + This parameter can be a value of @ref ADC_Sequence_A_Resume_Channel_Position */ +} stc_adc_init_t; + +/** + * @brief Structure definition of ADC trigger source configuration. + */ +typedef struct +{ + uint16_t u16TrigSrc; /*!< Specifies the trigger source type for the specified sequence. + This parameter can be a value of @ref ADC_Trigger_Source_Type */ + en_event_src_t enEvent0; /*!< An @ref en_event_src_t enumeration value. */ + en_event_src_t enEvent1; /*!< An @ref en_event_src_t enumeration value. */ +} stc_adc_trig_cfg_t; + +/** + * @brief Structure definition of AWD(analog watchdog) configuration. + */ +typedef struct +{ + uint8_t u8ChNum; /*!< The number of the ADC channel which to be configured as an AWD channel. + This parameter can be a value of range [ADC_CH_NUM_0, ADC_CH_NUM_15] of @ref ADC_Channel_Number */ + uint16_t u16CmpMode; /*!< The comparison mode of AWD. + This parameter can be a value of @ref ADC_AWD_Comparison_Mode */ + uint16_t u16LowerLimit; /*!< Threshold lower limit value(to register ADC_AWDxDR0). */ + uint16_t u16UpperLimit; /*!< Threshold upper limit value(to register ADC_AWDxDR1). */ +} stc_adc_awd_cfg_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Macros ADC Global Macros + * @{ + */ + +/** + * @defgroup ADC_Sequence ADC Sequence + * @{ + */ +#define ADC_SEQ_A (0U) +#define ADC_SEQ_B (1U) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Unit ADC Analog Watchdog Unit + * @{ + */ +#define ADC_AWD_0 (0U) +#define ADC_AWD_1 (1U) +/** + * @} + */ + +/** + * @defgroup ADC_Scan_Convert_Mode ADC Scan Convert Mode + * @{ + */ +#define ADC_MODE_SA_SSHOT (0x0U) /*!< Sequence A single shot. */ +#define ADC_MODE_SA_CONT (ADC_CR0_MS_0) /*!< Sequence A continuous. */ +#define ADC_MODE_SA_SB_SSHOT (ADC_CR0_MS_1) /*!< Sequence A and B both single shot. */ +#define ADC_MODE_SA_CONT_SB_SSHOT (ADC_CR0_MS_1 | \ + ADC_CR0_MS_0) /*!< Sequence A continuous and sequence B single shot. */ +/** + * @} + */ + +/** + * @defgroup ADC_Resolution ADC Resolution + * @{ + */ +#define ADC_RESOLUTION_12BIT (0x0U) /*!< Resolution is 12 bit. */ +#define ADC_RESOLUTION_10BIT (ADC_CR0_ACCSEL_0) /*!< Resolution is 10 bit. */ +#define ADC_RESOLUTION_8BIT (ADC_CR0_ACCSEL_1) /*!< Resolution is 8 bit. */ +/** + * @} + */ + +/** + * @defgroup ADC_Data_Auto_Clear_Cmd ADC Data Auto Clear Cmd + * @{ + */ +#define ADC_AUTO_CLR_DISABLE (0x0U) +#define ADC_AUTO_CLR_ENABLE (ADC_CR0_CLREN) /*!< ADC data register is automatically cleared after the data is read. */ +/** + * @} + */ + +/** + * @defgroup ADC_Data_Alignment ADC Data Alignment + * @{ + */ +#define ADC_DATA_ALIGN_RIGHT (0x0U) +#define ADC_DATA_ALIGN_LEFT (ADC_CR0_DFMT) +/** + * @} + */ + +/** + * @defgroup ADC_Average_Count ADC Average Count + * @{ + */ +#define ADC_AVG_CNT_2 (0x0U) +#define ADC_AVG_CNT_4 (ADC_CR0_AVCNT_0) +#define ADC_AVG_CNT_8 (ADC_CR0_AVCNT_1) +#define ADC_AVG_CNT_16 (ADC_CR0_AVCNT_1 | ADC_CR0_AVCNT_0) +#define ADC_AVG_CNT_32 (ADC_CR0_AVCNT_2) +#define ADC_AVG_CNT_64 (ADC_CR0_AVCNT_2 | ADC_CR0_AVCNT_0) +#define ADC_AVG_CNT_128 (ADC_CR0_AVCNT_2 | ADC_CR0_AVCNT_1) +#define ADC_AVG_CNT_256 (ADC_CR0_AVCNT_2 | ADC_CR0_AVCNT_1 | ADC_CR0_AVCNT_0) +/** + * @} + */ + +/** + * @defgroup ADC_Sequence_A_Resume_Channel_Position ADC Sequence A Resume Channel Position + * @{ + */ +#define ADC_SA_RESUME_POS_INT_CH (0x0U) /*!< Resumes from the interrupt channel of the sequence. */ +#define ADC_SA_RESUME_POS_FIRST_CH (ADC_CR1_RSCHSEL) /*!< Resumes from the first channel of the sequence. */ +/** + * @} + */ + +/** + * @defgroup ADC_Trigger_Source_Type ADC Trigger Source Type + * @{ + */ +#define ADC_TRIG_SRC_ADTRG (0x0U) /*!< The trigger source is the falling edge(the low level of the should \ + hold at least 1.5*PCLK cycle) of external pin ADTRGx(x=1, 2, 3). */ +#define ADC_TRIG_SRC_EVENT0 (ADC_TRGSR_TRGSELA_0) /*!< The trigger source is a internal event from other peripheral. \ + Only one event can be configured to trigger ADC. */ +#define ADC_TRIG_SRC_EVENT1 (ADC_TRGSR_TRGSELA_1) /*!< The trigger source is a internal event from other peripheral. \ + Only one event can be configured to trigger ADC. */ +#define ADC_TRIG_SRC_EVENT0_EVENT1 (ADC_TRGSR_TRGSELA_0 | \ + ADC_TRGSR_TRGSELA_1) /*!< The trigger source are two internal events from other peripheral(s). \ + Two events can be configured to trigger ADC and one of which can trigger the ADC. */ +/** + * @} + */ + +/** + * @defgroup ADC_Channel_Number ADC Channel Number + * @{ + */ +#define ADC_CH_NUM_0 (0U) +#define ADC_CH_NUM_1 (1U) +#define ADC_CH_NUM_2 (2U) +#define ADC_CH_NUM_3 (3U) +#define ADC_CH_NUM_4 (4U) +#define ADC_CH_NUM_5 (5U) +#define ADC_CH_NUM_6 (6U) +#define ADC_CH_NUM_7 (7U) +#define ADC_CH_NUM_8 (8U) +#define ADC_CH_NUM_9 (9U) +#define ADC_CH_NUM_10 (10U) +#define ADC_CH_NUM_11 (11U) +#define ADC_CH_NUM_12 (12U) +#define ADC_CH_NUM_13 (13U) +#define ADC_CH_NUM_14 (14U) +#define ADC_CH_NUM_15 (15U) +#define ADC_CH_NUM_16 (16U) +#define ADC_CH_NUM_17 (17U) +#define ADC_CH_NUM_18 (18U) +#define ADC_CH_NUM_19 (19U) +/** + * @} + */ + +/** + * @defgroup ADC_Channel ADC Channel + * @{ + */ +#define ADC_CH0 (0x1UL << ADC_CH_NUM_0) +#define ADC_CH1 (0x1UL << ADC_CH_NUM_1) +#define ADC_CH2 (0x1UL << ADC_CH_NUM_2) +#define ADC_CH3 (0x1UL << ADC_CH_NUM_3) +#define ADC_CH4 (0x1UL << ADC_CH_NUM_4) +#define ADC_CH5 (0x1UL << ADC_CH_NUM_5) +#define ADC_CH6 (0x1UL << ADC_CH_NUM_6) +#define ADC_CH7 (0x1UL << ADC_CH_NUM_7) +#define ADC_CH8 (0x1UL << ADC_CH_NUM_8) +#define ADC_CH9 (0x1UL << ADC_CH_NUM_9) +#define ADC_CH10 (0x1UL << ADC_CH_NUM_10) +#define ADC_CH11 (0x1UL << ADC_CH_NUM_11) +#define ADC_CH12 (0x1UL << ADC_CH_NUM_12) +#define ADC_CH13 (0x1UL << ADC_CH_NUM_13) +#define ADC_CH14 (0x1UL << ADC_CH_NUM_14) +#define ADC_CH15 (0x1UL << ADC_CH_NUM_15) +#define ADC_CH16 (0x1UL << ADC_CH_NUM_16) +#define ADC_CH17 (0x1UL << ADC_CH_NUM_17) +#define ADC_CH18 (0x1UL << ADC_CH_NUM_18) +#define ADC_CH19 (0x1UL << ADC_CH_NUM_19) +#define ADC_EXT_CH (ADC_CH15) +/** + * @} + */ + +/** + * @defgroup ADC_Pin_Number ADC Pin Number + * @{ + */ +#define ADC123_IN0 (0U) /*!< PA0 */ +#define ADC123_IN1 (1U) /*!< PA1 */ +#define ADC123_IN2 (2U) /*!< PA2 */ +#define ADC123_IN3 (3U) /*!< PA3 */ +#define ADC12_IN4 (4U) /*!< PA4 */ +#define ADC12_IN5 (5U) /*!< PA5 */ +#define ADC12_IN6 (6U) /*!< PA6 */ +#define ADC12_IN7 (7U) /*!< PA7 */ +#define ADC12_IN8 (8U) /*!< PB0 */ +#define ADC12_IN9 (9U) /*!< PB1 */ +#define ADC123_IN10 (10U) /*!< PC0 */ +#define ADC123_IN11 (11U) /*!< PC1 */ +#define ADC123_IN12 (12U) /*!< PC2 */ +#define ADC123_IN13 (13U) /*!< PC3 */ +#define ADC12_IN14 (14U) /*!< PC4 */ +#define ADC12_IN15 (15U) /*!< PC5 */ + +#define ADC3_IN4 (4U) /*!< PF6 */ +#define ADC3_IN5 (5U) /*!< PF7 */ +#define ADC3_IN6 (6U) /*!< PF8 */ +#define ADC3_IN7 (7U) /*!< PF9 */ +#define ADC3_IN8 (8U) /*!< PF10 */ +#define ADC3_IN9 (9U) /*!< PF3 */ +#define ADC3_IN14 (14U) /*!< PF4 */ +#define ADC3_IN15 (15U) /*!< PF5 */ +#define ADC3_IN16 (16U) /*!< PH2 */ +#define ADC3_IN17 (17U) /*!< PH3 */ +#define ADC3_IN18 (18U) /*!< PH4 */ +#define ADC3_IN19 (19U) /*!< PH5 */ +/** + * @} + */ + +/** + * @defgroup ADC_All_Channels_Mask ADC All Channels Mask + * @{ + */ +#define ADC1_CH_ALL (0xFFFFUL) +#define ADC2_CH_ALL (0xFFFFUL) +#define ADC3_CH_ALL (0xFFFFFUL) +#define ADC_CH_REMAP_ALL (0xFFFFUL) +/** + * @} + */ + +/** + * @defgroup ADC_Channel_Count ADC Channel Count + * @{ + */ +#define ADC1_CH_COUNT (16U) +#define ADC2_CH_COUNT (16U) +#define ADC3_CH_COUNT (20U) +/** + * @} + */ + +/** + * @defgroup ADC_Invalid_Value ADC Invalid Value + * @{ + */ +#define ADC_INVALID_VAL (0xFFFFU) +/** + * @} + */ + +/** + * @defgroup ADC_Extend_Channel_Source ADC Extend Channel Source + * @{ + */ +#define ADC_EXCH_SRC_ADC_PIN (0x0U) /*!< The input source of the extended channel is analog input pin. */ +#define ADC_EXCH_SRC_INTERNAL (ADC_EXCHSELR_EXCHSEL) /*!< The input source of the extended channel is internal analog signal. */ +/** + * @} + */ + +/** + * @defgroup ADC_Sequence_Status_Flag ADC Sequence Status Flag + * @{ + */ +#define ADC_SEQ_FLAG_EOCA (ADC_ISR_EOCAF) /*!< Status flag of the end of conversion of sequence A. */ +#define ADC_SEQ_FLAG_EOCB (ADC_ISR_EOCBF) /*!< Status flag of the end of conversion of sequence B. */ +#define ADC_SEQ_FLAG_NESTED (ADC_ISR_SASTPDF) /*!< Status flag of sequence A was interrupted by sequence B. */ + +#define ADC_SEQ_FLAG_ALL (ADC_SEQ_FLAG_EOCA | \ + ADC_SEQ_FLAG_EOCB | \ + ADC_SEQ_FLAG_NESTED) +/** + * @} + */ + +/** + * @defgroup ADC_Synchronous_Unit ADC Synchronous Unit + * @{ + */ +#define ADC_SYNC_ADC1_ADC2 (0U) /*!< ADC1 and ADC2 work synchronously. */ +#define ADC_SYNC_ADC1_ADC2_ADC3 (ADC_SYNCCR_SYNCMD_0) /*!< ADC1, ADC2 and ADC3 work synchronously. */ +/** + * @} + */ + +/** + * @defgroup ADC_Synchronous_Mode ADC Synchronous Mode + * @{ + */ +#define ADC_SYNC_SSHOT_SEQUENTIAL (0U) /*!< Single shot trigger, sequentially trigger. \ + When the trigger condition occurs, ADC1 starts before ADC2, \ + and ADC1 and ADC2 only perform one sample conversion. */ +#define ADC_SYNC_SSHOT_SIMULTANEOUS (ADC_SYNCCR_SYNCMD_1) /*!< Single shot trigger, simultaneously trigger. \ + When the trigger condition occurs, ADC1 and ADC2 start at the same time, \ + and ADC1 and ADC2 only perform one sample conversion. */ +#define ADC_SYNC_CONT_SEQUENTIAL (ADC_SYNCCR_SYNCMD_2) /*!< Continuously trigger, sequentially trigger. \ + When the trigger condition occurs, ADC1 starts before ADC2, \ + and ADC1 and ADC2 will continue to sample conversion until stoped by software. */ +#define ADC_SYNC_CONT_SIMULTANEOUS (ADC_SYNCCR_SYNCMD_2 | \ + ADC_SYNCCR_SYNCMD_1) /*!< Continuously trigger, simultaneously trigger. \ + When the trigger condition occurs, ADC1 and ADC2 start at the same time, \ + and ADC1 and ADC2 will continue to sample conversion until stoped by software. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Comparison_Mode ADC AWD(Analog Watchdog) Comparison Mode + * @{ + */ +#define ADC_AWD_CMP_OUT_RANGE (0x0U) /*!< ADCVal > UpperLimit or ADCVal < LowerLimit */ +#define ADC_AWD_CMP_IN_RANGE (0x1U) /*!< LowerLimit < ADCVal < UpperLimit */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Combination_Mode ADC AWD(Analog Watchdog) Combination Mode + * @note If combination mode is valid(ADC_AWD_COMB_OR/ADC_AWD_COMB_AND/ADC_AWD_COMB_XOR) and + the Channels selected by the AWD0 and AWD1 are deferent, make sure that the channel + of AWD1 is converted after the channel conversion of AWD0 ends. + * @{ + */ +#define ADC_AWD_COMB_OR (ADC_AWDCR_AWDCM_0) /*!< The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. */ +#define ADC_AWD_COMB_AND (ADC_AWDCR_AWDCM_1) /*!< The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. */ +#define ADC_AWD_COMB_XOR (ADC_AWDCR_AWDCM_1 | \ + ADC_AWDCR_AWDCM_0) /*!< Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. */ +/** + * @} + */ + +/** + * @defgroup ADC_AWD_Status_Flag ADC AWD Status Flag + * @{ + */ +#define ADC_AWD_FLAG_AWD0 (ADC_AWDSR_AWD0F) /*!< Flag of AWD0. */ +#define ADC_AWD_FLAG_AWD1 (ADC_AWDSR_AWD1F) /*!< Flag of AWD1. */ +#define ADC_AWD_FLAG_COMB (ADC_AWDSR_AWDCMF) /*!< Flag of combination of mode. */ + +#define ADC_AWD_FLAG_ALL (ADC_AWD_FLAG_AWD0 | \ + ADC_AWD_FLAG_AWD1 | \ + ADC_AWD_FLAG_COMB) +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Gain_Factor ADC PGA Gain Factor + * @{ + */ +#define ADC_PGA_GAIN_2 (0U) /*!< PGA gain factor is 2. */ +#define ADC_PGA_GAIN_2P133 (ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 2.133. */ +#define ADC_PGA_GAIN_2P286 (ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 2.286. */ +#define ADC_PGA_GAIN_2P667 (ADC_PGACR3_PGAGAIN_1 | \ + ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 2.667. */ +#define ADC_PGA_GAIN_2P909 (ADC_PGACR3_PGAGAIN_2) /*!< PGA gain factor is 2.909. */ +#define ADC_PGA_GAIN_3P2 (ADC_PGACR3_PGAGAIN_2 | \ + ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 3.2. */ +#define ADC_PGA_GAIN_3P556 (ADC_PGACR3_PGAGAIN_2 | \ + ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 2.556. */ +#define ADC_PGA_GAIN_4 (ADC_PGACR3_PGAGAIN_2 | \ + ADC_PGACR3_PGAGAIN_1 | \ + ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 4. */ +#define ADC_PGA_GAIN_4P571 (ADC_PGACR3_PGAGAIN_3) /*!< PGA gain factor is 4.571. */ +#define ADC_PGA_GAIN_5P333 (ADC_PGACR3_PGAGAIN_3 | \ + ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 5.333. */ +#define ADC_PGA_GAIN_6P4 (ADC_PGACR3_PGAGAIN_3 | \ + ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 6.4. */ +#define ADC_PGA_GAIN_8 (ADC_PGACR3_PGAGAIN_3 | \ + ADC_PGACR3_PGAGAIN_1 | \ + ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 8. */ +#define ADC_PGA_GAIN_10P667 (ADC_PGACR3_PGAGAIN_3 | \ + ADC_PGACR3_PGAGAIN_2) /*!< PGA gain factor is 10.667. */ +#define ADC_PGA_GAIN_16 (ADC_PGACR3_PGAGAIN_3 | \ + ADC_PGACR3_PGAGAIN_2 | \ + ADC_PGACR3_PGAGAIN_0) /*!< PGA gain factor is 16. */ +#define ADC_PGA_GAIN_32 (ADC_PGACR3_PGAGAIN_3 | \ + ADC_PGACR3_PGAGAIN_2 | \ + ADC_PGACR3_PGAGAIN_1) /*!< PGA gain factor is 32. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_VSS ADC PGA VSS + * @{ + */ +#define ADC_PGA_VSS_PGAVSS (0U) /*!< Use pin PGAx_VSS as the reference GND of PGAx */ +#define ADC_PGA_VSS_AVSS (1U) /*!< Use AVSS as the reference GND of PGAx. */ +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Unit ADC PGA Unit + * @{ + */ +#define ADC_PGA_1 (0U) /*!< PGA1, belongs to ADC1. Input pin is ADC123_IN0. */ +#define ADC_PGA_2 (1U) /*!< PGA2, belongs to ADC1. Input pin is ADC123_IN1. */ +#define ADC_PGA_3 (2U) /*!< PGA3, belongs to ADC1. Input pin is ADC123_IN2. */ +#define ADC_PGA_4 (3U) /*!< PGA4, belongs to ADC2. Input pin is ADC12_IN6. */ +/** + * @} + */ + +/** + * @defgroup ADC_Common_Trigger_Sel ADC Common Trigger Source Select + * @{ + */ +#define ADC_COM_TRIG1 (AOS_ADC_1_ITRGSELR_COMTRG_EN_0) +#define ADC_COM_TRIG2 (AOS_ADC_1_ITRGSELR_COMTRG_EN_1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ADC_Global_Functions + * @{ + */ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit); +void ADC_DeInit(M4_ADC_TypeDef *ADCx); + +en_result_t ADC_StructInit(stc_adc_init_t *pstcInit); + +void ADC_SetScanMode(M4_ADC_TypeDef *ADCx, uint16_t u16Mode); +en_result_t ADC_ChannelCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, \ + uint32_t u32AdcCh, const uint8_t pu8SplTime[], \ + en_functional_state_t enNewState); + +void ADC_AvgChannelConfig(M4_ADC_TypeDef *ADCx, uint16_t u16AvgCnt); +void ADC_AvgChannelCmd(M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh, en_functional_state_t enNewState); +void ADC_SetExChannelSrc(M4_ADC_TypeDef *ADCx, uint8_t u8ExChSrc); + +en_result_t ADC_TrigSrcStructInit(stc_adc_trig_cfg_t *pstcCfg); +en_result_t ADC_TrigSrcConfig(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, const stc_adc_trig_cfg_t *pstcCfg); +void ADC_TrigSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState); +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, uint16_t u16TrigSrc, \ + uint32_t u32ComTrig, en_functional_state_t enNewState); + +void ADC_SeqIntCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState); +en_flag_status_t ADC_SeqGetStatus(const M4_ADC_TypeDef *ADCx, uint8_t u8Flag); +void ADC_SeqClrStatus(M4_ADC_TypeDef *ADCx, uint8_t u8Flag); + +en_result_t ADC_AWD_Config(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, const stc_adc_awd_cfg_t *pstcCfg); +void ADC_AWD_CombModeCmd(M4_ADC_TypeDef *ADCx, uint16_t u16CombMode, en_functional_state_t enNewState); +void ADC_AWD_Cmd(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, en_functional_state_t enNewState); +void ADC_AWD_IntCmd(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, en_functional_state_t enNewState); +en_flag_status_t ADC_AWD_GetStatus(const M4_ADC_TypeDef *ADCx, uint8_t u8Flag); +void ADC_AWD_ClrStatus(M4_ADC_TypeDef *ADCx, uint8_t u8Flag); + +void ADC_PGA_Config(uint8_t u8PGAx, uint8_t u8GainFactor, uint8_t u8PgaVss); +void ADC_PGA_Cmd(uint8_t u8PGAx, en_functional_state_t enNewState); + +void ADC_SYNC_Config(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TrigDelay); +void ADC_SYNC_Cmd(en_functional_state_t enNewState); + +void ADC_SH_Config(uint8_t u8SplTime); +void ADC_SH_ChannelCmd(uint32_t u32AdcCh, en_functional_state_t enNewState); + +void ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh, uint8_t u8AdcPinNum); +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh); + +en_result_t ADC_PollingSA(M4_ADC_TypeDef *ADCx, uint16_t pu16AdcVal[], uint8_t u8Length, uint32_t u32Timeout); + +void ADC_Start(M4_ADC_TypeDef *ADCx); +void ADC_Stop(M4_ADC_TypeDef *ADCx); +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t pu16AdcVal[], uint8_t u8Length); +en_result_t ADC_GetChannelData(const M4_ADC_TypeDef *ADCx, uint32_t u32TargetCh, \ + uint16_t pu16AdcVal[], uint8_t u8Length); +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChNum); + +/** + * @} + */ + +#endif /* DDL_ADC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_ADC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_aes.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_aes.h new file mode 100644 index 0000000000000000000000000000000000000000..1802901603a561d6ff09556be150ac3566f55531 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_aes.h @@ -0,0 +1,132 @@ +/** + ******************************************************************************* + * @file hc32f4a0_aes.h + * @brief This file contains all the functions prototypes of the AES driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_AES_H__ +#define __HC32F4A0_AES_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_AES + * @{ + */ + +#if (DDL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Global_Macros AES Global Macros + * @{ + */ + +/* AES key length in bytes is 16. */ +#define AES_BLOCK_LEN (16U) + +/** + * @defgroup AES_STATUS AES Start or Stop + * @{ + */ +#define AES_START (AES_CR_START) +#define AES_STOP (0x0UL) +/** + * @} + */ + +/** + * @defgroup AES_KEY_SIZE AES Key Size + * @{ + */ +#define AES_KEY_SIZE_128BIT (0UL << AES_CR_KEYSIZE_POS) +#define AES_KEY_SIZE_192BIT (1UL << AES_CR_KEYSIZE_POS) +#define AES_KEY_SIZE_256BIT (2UL << AES_CR_KEYSIZE_POS) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup AES_Global_Functions + * @{ + */ +en_result_t AES_Encrypt(uint8_t au8Plaintext[], + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t u8KeyLength, + uint8_t au8Ciphertext[]); + +en_result_t AES_Decrypt(uint8_t au8Ciphertext[], + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t u8KeyLength, + uint8_t au8Plaintext[]); +/** + * @} + */ + +#endif /* DDL_AES_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_AES_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_can.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_can.h new file mode 100644 index 0000000000000000000000000000000000000000..6895a6fb20b905f9678cb594dc6aba0b4b34d90f --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_can.h @@ -0,0 +1,723 @@ +/** + ******************************************************************************* + * @file hc32f4a0_can.h + * @brief This file contains all the functions prototypes of the CAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-12-14 Wuze Modified comment of structure stc_can_bt_cfg_t + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_CAN_H__ +#define __HC32F4A0_CAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_CAN + * @{ + */ + +#if (DDL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Types CAN Global Types + * @{ + */ + +/** + * @brief CAN bit timing configuration structure. See 11898-1 for details. + * @note 1. Restrictions: u32SEG1 >= u32SEG2 + 1, u32SEG2 >= u32SJW. + * @note 2. TQ = u32Prescaler / CANClock. + * @note 3. Bit time = (u32SEG2 + u32SEG2) x TQ. + * @note 4. Baudrate = CANClock/(u32Prescaler*(u32SEG1 + u32SEG2)) + */ +typedef struct +{ + uint32_t u32SEG1; /*!< TQs of segment 1. Contains synchronization segment, \ + propagation time segment and phase buffer segment 1. */ + uint32_t u32SEG2; /*!< TQs of segment 2. Phase buffer segment 2. */ + uint32_t u32SJW; /*!< TQs of synchronization jump width. */ + uint32_t u32Prescaler; /*!< Range [1, 256]. */ +} stc_can_bt_cfg_t; + +/** + * @brief CAN acceptance filter structure. + */ +typedef struct +{ + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + uint32_t u32IDMsk; /*!< ID mask. The mask bits of ID will be ignored by the acceptance filter. */ + uint32_t u32MskType; /*!< Acceptance filter mask type. This parameter can be a value of @ref CAN_AF_Mask_Type */ +} stc_can_af_cfg_t; + +/** + * @brief CAN FD configuration structure. + */ +typedef struct +{ + uint8_t u8CANFDMode; /*!< CAN-FD mode, Bosch CAN-FD or 11898-1:2015 CAN-FD. + This parameter can be a value of @ref CAN_FD_Mode */ + stc_can_bt_cfg_t stcFBT; /*!< Bit timing configuration of fast bit timing. */ + uint8_t u8TDCCmd; /*!< Transmiter delay compensation function control. + This parameter can be a value of @ref CAN_FD_TDC_Command */ + uint8_t u8TDCSSP; /*!< Specify secondary sample point(SSP) of transmitter delay compensatin(TDC). Number of TQ. */ +} stc_can_fd_cfg_t; + +/** + * @brief CAN time-triggered communication configuration structure. + */ +typedef struct +{ + uint8_t u8TransBufMode; /*!< TTCAN Transmit Buffer Mode. + This parameter can be a value of @ref CAN_TTC_Transmit_Buffer_Mode */ + uint8_t u8NTUPrescaler; /*!< Prescaler of NTU(network time unit). The source is the bit time which is defined by SBT. + This parameter can be a value of @ref CAN_TTC_NTU_Prescaler */ + uint32_t u32RefMsgIDE; /*!< Reference message identifier extension bit. + '1' to set the ID which is specified by parameter 'u32RefMsgID' as an extended ID while \ + '0' to set it as a standard ID. */ + uint32_t u32RefMsgID; /*!< Reference message identifier. */ + uint16_t u16TrigType; /*!< Trigger type of TTC. + This parameter can be a value of @ref CAN_TTC_Trigger_Type */ + uint16_t u16TxEnWindow; /*!< Tx_Enable window. Time period within which the transmission of a message may be started. Range is [1, 16U] */ + uint16_t u16TxTrigTime; /*!< Specifies for the referred message the time window of the matrix cycle at which it is to be transmitted. */ + uint16_t u16WatchTrigTime; /*!< Time mark used to check whether the time since the last valid reference message has been too long. */ +} stc_can_ttc_cfg_t; + +/** + * @brief CAN initialization structure. + */ +typedef struct +{ + uint8_t u8WorkMode; /*!< Specify the work mode of CAN. + This parameter can be a value of @ref CAN_Work_Mode */ + stc_can_bt_cfg_t stcSBT; /*!< Bit timing configuration of slow bit timing. */ + + en_functional_state_t enCANFDCmd; /*!< Enable or Disable CAN-FD. If Disable, the following configuration valuse will not \ + be written to the registers. */ + + stc_can_fd_cfg_t stcFDCfg; /*!< CAN-FD configuration structure. */ + + uint8_t u8TransMode; /*!< Transmission mode of PTB and STB. + This parameter can be a value of @ref CAN_Trans_Mode */ + uint8_t u8STBPrioMode; /*!< Priority mode of STB. First in first transmit. OR the priority is determined by ID. Smaller ID higher priority. + Whatever the priority mode of STB is, PTB always has the highest priority. + This parameter can be a value of @ref CAN_STB_Priority_Mode */ + uint8_t u8RBSWarnLimit; /*!< Specify receive buffer almost full warning limit. Rang is [1, 8]. \ + Each CAN unit has 8 receive buffer slots. When the number of received frames reaches \ + the set value of u8RBSWarnLimit, register bit RTIF.RAFIF is set and the interrupt occurred \ + if it was enabled. */ + uint8_t u8ErrWarnLimit; /*!< Specify programmable error warning limit. Range is [0, 15]. \ + Error warning limit = (u8ErrWarnLimit + 1) * 8. */ + stc_can_af_cfg_t *pstcAFCfg; /*!< Points to a stc_can_af_cfg_t structure type pointer value that + contains the configuration informations for the acceptance filters. */ + uint16_t u16AFSel; /*!< Specify acceptance filter for receive buffer. + This parameter can be values of @ref CAN_AF */ + uint8_t u8RBStoreSel; /*!< Receive buffer stores all data frames, includes error data. + This parameter can be a value of @ref CAN_RB_Store_Selection */ + uint8_t u8RBOvfOp; /*!< Operation when receive buffer overflow. + This parameter can be a value of @ref CAN_RB_Overflow_Operation */ + uint8_t u8SelfACKCmd; /*!< Self ACK. Only for external loopback mode. + This parameter can be a value of @ref CAN_Self_ACK_Command */ +} stc_can_init_t; + +/** + * @brief CAN transmit data structure. + */ +typedef struct +{ + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union + { + uint32_t u32Ctrl; + struct + { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. \ + It should be zero while the frame is remote frame. \ + This parameter can be a value of @ref CAN_DLC */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be a 1 or 0. */ + uint32_t RSVD: 24; /*!< Reserved bits. */ + }; + }; + uint8_t *pu8Data; /*!< Pointer to data filed of data frame. */ +} stc_can_tx_t; + +/** + * @brief CAN receive data structure. + */ +typedef struct +{ + uint32_t u32ID; /*!< 11 bits standard ID or 29 bits extended ID, depending on IDE. */ + union + { + uint32_t u32Ctrl; + struct + { + uint32_t DLC: 4; /*!< Data length code. Length of the data segment of data frame. \ + It should be zero while the frame is remote frame. \ + This parameter can be a value of @ref CAN_DLC */ + uint32_t BRS: 1; /*!< Bit rate switch. */ + uint32_t FDF: 1; /*!< CAN FD frame. */ + uint32_t RTR: 1; /*!< Remote transmission request bit. + It is used to distinguish between data frames and remote frames. */ + uint32_t IDE: 1; /*!< Identifier extension flag. + It is used to distinguish between standard format and extended format. + This parameter can be 1 or 0. */ + uint32_t RSVD: 4; /*!< Reserved bits. */ + uint32_t TX: 1; /*!< This bit is set to 1 when receiving self-transmitted data in loopback mode. */ + uint32_t ERRT: 3; /*!< Error type. */ + uint32_t CYCLE_TIME: 16; /*!< Cycle time of time-triggered communication(TTC). */ + }; + }; + uint8_t *pu8Data; /*!< Pointer to data filed of data frame. */ +} stc_can_rx_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Macros CAN Global Macros + * @{ + */ + +/** + * @defgroup CAN_Work_Mode CAN Work Mode + * @{ + */ +#define CAN_MODE_NORMAL (0U) /*!< Normal work mode. */ +#define CAN_MODE_SILENT (1U) /*!< Silent work mode. Prohibit data transmission. */ +#define CAN_MODE_ILB (2U) /*!< Internal loopback mode, just for self-test while developing. */ +#define CAN_MODE_ELB (3U) /*!< External loopback mode, just for self-test while developing. */ +#define CAN_MODE_ELB_SILENT (4U) /*!< External loppback silent mode, just for self-test while developing. \ + It is forbidden to respond to received frames and error frames, but data can be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_Transmit_Buffer_Type CAN Transmit Buffer Type + * @{ + */ +#define CAN_BUF_PTB (0U) /*!< Primary transmit buffer. */ +#define CAN_BUF_STB (1U) /*!< Secondary transmit buffer. */ +/** + * @} + */ + +/** + * @defgroup CAN_DLC CAN Data_Length_Code + * @{ + */ +#define CAN_DLC_0 (0x0U) /*!< CAN2.0 and CAN FD: payload is 0 in bytes. */ +#define CAN_DLC_1 (0x1U) /*!< CAN2.0 and CAN FD: payload is 1 in bytes. */ +#define CAN_DLC_2 (0x2U) /*!< CAN2.0 and CAN FD: payload is 2 in bytes. */ +#define CAN_DLC_3 (0x3U) /*!< CAN2.0 and CAN FD: payload is 3 in bytes. */ +#define CAN_DLC_4 (0x4U) /*!< CAN2.0 and CAN FD: payload is 4 in bytes. */ +#define CAN_DLC_5 (0x5U) /*!< CAN2.0 and CAN FD: payload is 5 in bytes. */ +#define CAN_DLC_6 (0x6U) /*!< CAN2.0 and CAN FD: payload is 6 in bytes. */ +#define CAN_DLC_7 (0x7U) /*!< CAN2.0 and CAN FD: payload is 7 in bytes. */ +#define CAN_DLC_8 (0x8U) /*!< CAN2.0 and CAN FD: payload is 8 in bytes. */ +#define CAN_DLC_12 (0x9U) /*!< CAN FD: payload is 12 in bytes. CAN2.0: payload is 8 in bytes. */ +#define CAN_DLC_16 (0xAU) /*!< CAN FD: payload is 16 in bytes. CAN2.0: payload is 8 in bytes. */ +#define CAN_DLC_20 (0xBU) /*!< CAN FD: payload is 20 in bytes. CAN2.0: payload is 8 in bytes. */ +#define CAN_DLC_24 (0xCU) /*!< CAN FD: payload is 24 in bytes. CAN2.0: payload is 8 in bytes. */ +#define CAN_DLC_32 (0xDU) /*!< CAN FD: payload is 32 in bytes. CAN2.0: payload is 8 in bytes. */ +#define CAN_DLC_48 (0xEU) /*!< CAN FD: payload is 48 in bytes. CAN2.0: payload is 8 in bytes. */ +#define CAN_DLC_64 (0xFU) /*!< CAN FD: payload is 64 in bytes. CAN2.0: payload is 8 in bytes. */ +/** + * @} + */ + +/** + * @defgroup CAN_Trans_Mode CAN Transmission Mode + * @{ + */ +#define CAN_TRANS_PTB_STB_AUTO_RETX (0x0U) /*!< Both PTB and STB automatically retransmit. */ +#define CAN_TRANS_PTB_SSHOT (CAN_CFG_STAT_TPSS) /*!< PTB single shot transmission mode. */ +#define CAN_TRANS_STB_SSHOT (CAN_CFG_STAT_TSSS) /*!< STB single shot transmission mode. */ +#define CAN_TRANS_PTB_STB_SSHOT (CAN_CFG_STAT_TPSS | \ + CAN_CFG_STAT_TSSS) /*!< STB single shot, PTB single shot. */ +/** + * @} + */ + +/** + * @defgroup CAN_STB_Trans_Control CAN STB Transmission Control + * @{ + */ +#define CAN_STB_TRANS_ALL (0U) /*!< Transmit all of STB slots. */ +#define CAN_STB_TRANS_ONE (1U) /*!< Transmit one STB slot. */ +/** + * @} + */ + +/** + * @defgroup CAN_STB_Priority_Mode CAN STB Priority Mode + * @{ + */ +#define CAN_STB_PRIO_FIFO (0x0U) /*!< Data first in and first be transmitted. */ +#define CAN_STB_PRIO_ID (CAN_TCTRL_TSMODE) /*!< Data with smallest ID first be transmitted. */ +/** + * @} + */ + +/** + * @defgroup CAN_TB_Status CAN Transmit Buffer Status + * @{ + */ +#define CAN_TB_STAT_EMPTY (0x0U) /*!< TTCAN is disabled(TTEN == 0): STB is empty. \ + TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): \ + PTB and STB are both empty. */ +#define CAN_TB_STAT_LESS_HALF (0x1U) /*!< TTEN == 0: STB is not less than half full; \ + TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. */ +#define CAN_TB_STAT_MORE_HALF (0x2U) /*!< TTEN == 0: STB is more than half full; \ + TTEN == 1 && TTTBM == 1: reserved value. */ +#define CAN_TB_STAT_FULL (0x3U) /*!< TTEN == 0: STB is full; \ + TTEN == 1 && TTTBM == 1: PTB and STB are both full. */ +/** + * @} + */ + +/** + * @defgroup CAN_RB_Status CAN Receive Buffer Status + * @{ + */ +#define CAN_RB_STAT_EMPTY (0x0U) /*!< Receive buffer(RB) is empty. */ +#define CAN_RB_STAT_LESS_WARN_LIMIT (0x1U) /*!< RB is not empty, but is less than almost full warning limit. */ +#define CAN_RB_STAT_MORE_WARN_LIMIT (0x2U) /*!< RB is not full, but is more than or equal to almost full warning limit. */ +#define CAN_RB_STAT_FULL (0x3U) /*!< RB is full. */ +/** + * @} + */ + +/** + * @defgroup CAN_FD_Mode CAN FD Mode + * @{ + */ +#define CAN_FD_MODE_BOSCH (0x0U) +#define CAN_FD_MODE_ISO_11898 (CAN_TCTRL_FD_ISO) +/** + * @} + */ + +/** + * @defgroup CAN_RB_Store_Selection CAN Receive Buffer Store Selection + * @{ + */ +#define CAN_RB_STORE_CORRECT_DATA (0x0U) /*!< Receive buffer stores correct data frames only. */ +#define CAN_RB_STORE_ALL_DATA (CAN_RCTRL_RBALL) /*!< Receive buffer stores all data frames, includes error data. */ +/** + * @} + */ + +/** + * @defgroup CAN_RB_Overflow_Operation CAN Receive Buffer Overflow Operation + * @{ + */ +#define CAN_RB_OVF_SAVE_NEW (0x0U) /*!< Saves the newly received data and the first received data will be overwritten. */ +#define CAN_RB_OVF_DISCARD_NEW (CAN_RCTRL_ROM) /*!< Discard the newly received data. */ +/** + * @} + */ + +/** + * @defgroup CAN_Self_ACK_Command CAN Self ACK Command + * @{ + */ +#define CAN_SELF_ACK_DISABLE (0x0U) +#define CAN_SELF_ACK_ENABLE (CAN_RCTRL_SACK) +/** + * @} + */ + +/** + * @defgroup CAN_FD_TDC_Command CAN-FD Transmiter Delay Compensation Command + * @{ + */ +#define CAN_FD_TDC_DISABLE (0x0U) +#define CAN_FD_TDC_ENABLE (CAN_TDC_TDCEN) +/** + * @} + */ + +/** + * @defgroup CAN_Interrupt_Type CAN Interrupt Type + * @{ + */ +#define CAN_INT_ERR_INT (1UL << 1U) /*!< Register bit RTIE.EIE. Error interrupt. */ +#define CAN_INT_STB_TRANS_OK (1UL << 2U) /*!< Register bit RTIE.TSIE. Secondary transmit buffer was transmitted successfully. */ +#define CAN_INT_PTB_TRANS_OK (1UL << 3U) /*!< Register bit RTIE.TPIE. Primary transmit buffer was transmitted successfully. */ +#define CAN_INT_RB_ALMOST_FULL (1UL << 4U) /*!< Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_INT_RB_FIFO_FULL (1UL << 5U) /*!< Register bit RTIE.RFIE. The FIFO of receive buffer is full. */ +#define CAN_INT_RX_OVERRUN (1UL << 6U) /*!< Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. */ +#define CAN_INT_RX (1UL << 7U) /*!< Register bit RTIE.RIE. Received a valid data frame or remote frame. */ +#define CAN_INT_BUS_ERR (1UL << 9U) /*!< Register bit ERRINT.BEIE. Arbitration lost caused bus error */ +#define CAN_INT_ARB_LOST (1UL << 11U) /*!< Register bit ERRINT.ALIE. Arbitration lost. */ +#define CAN_INT_ERR_PASSIVE (1UL << 13U) /*!< Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. */ + +#define CAN_INT_ALL (CAN_INT_ERR_INT | \ + CAN_INT_STB_TRANS_OK | \ + CAN_INT_PTB_TRANS_OK | \ + CAN_INT_RB_ALMOST_FULL | \ + CAN_INT_RB_FIFO_FULL | \ + CAN_INT_RX_OVERRUN | \ + CAN_INT_RX | \ + CAN_INT_BUS_ERR | \ + CAN_INT_ARB_LOST | \ + CAN_INT_ERR_PASSIVE) +/** + * @} + */ + +/** + * @defgroup CAN_Common_Status_Flag CAN Common Status Flag + * @{ + */ +#define CAN_FLAG_BUS_OFF (1UL << 0U) /*!< Register bit CFG_STAT.BUSOFF. CAN bus off. */ +#define CAN_FLAG_BUS_TX (1UL << 1U) /*!< Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. */ +#define CAN_FLAG_BUS_RX (1UL << 2U) /*!< Register bit CFG_STAT.RACTIVE. CAN bus is receiving. */ +#define CAN_FLAG_RB_OVF (1UL << 5U) /*!< Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. */ +#define CAN_FLAG_TB_FULL (1UL << 8U) /*!< Register bit RTIE.TSFF. Transmit buffers are all full. \ + TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. \ + TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled.*/ +#define CAN_FLAG_TRANS_ABORTED (1UL << 16U) /*!< Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. */ +#define CAN_FLAG_ERR_INT (1UL << 17U) /*!< Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the \ + set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than \ + the set value to greater than the set value, or from greater than the set value to less than the set value. */ +#define CAN_FLAG_STB_TRANS_OK (1UL << 18U) /*!< Register bit RTIF.TSIF. STB was transmitted successfully. */ +#define CAN_FLAG_PTB_TRANS_OK (1UL << 19U) /*!< Register bit RTIF.TPIF. PTB was transmitted successfully. */ +#define CAN_FLAG_RB_ALMOST_FULL (1UL << 20U) /*!< Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. */ +#define CAN_FLAG_RB_FIFO_FULL (1UL << 21U) /*!< Register bit RTIF.RFIF. The FIFO of receive buffer is full. */ +#define CAN_FLAG_RX_OVERRUN (1UL << 22U) /*!< Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. */ +#define CAN_FLAG_RX_OK (1UL << 23U) /*!< Register bit RTIF.RIF. Received a valid data frame or remote frame. */ +#define CAN_FLAG_BUS_ERR (1UL << 24U) /*!< Register bit ERRINT.BEIF. Arbitration lost caused bus error. */ +#define CAN_FLAG_ARB_LOST (1UL << 26U) /*!< Register bit ERRINT.ALIF. Arbitration lost. */ +#define CAN_FLAG_ERR_PASSIVE (1UL << 28U) /*!< Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. */ +#define CAN_FLAG_ERR_PASSIVE_NODE (1UL << 30U) /*!< Register bit ERRINT.EPASS. The node is an error-passive node. */ +#define CAN_FLAG_REACH_WARN_LIMIT (1UL << 31U) /*!< Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. */ + +#define CAN_FLAG_ALL (CAN_FLAG_BUS_OFF | \ + CAN_FLAG_BUS_TX | \ + CAN_FLAG_BUS_RX | \ + CAN_FLAG_RB_OVF | \ + CAN_FLAG_TB_FULL | \ + CAN_FLAG_TRANS_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TRANS_OK | \ + CAN_FLAG_PTB_TRANS_OK | \ + CAN_FLAG_RB_ALMOST_FULL | \ + CAN_FLAG_RB_FIFO_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX_OK | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARB_LOST | \ + CAN_FLAG_ERR_PASSIVE | \ + CAN_FLAG_ERR_PASSIVE_NODE | \ + CAN_FLAG_REACH_WARN_LIMIT) + +#define CAN_FLAG_CLR_MSK (CAN_FLAG_RB_OVF | \ + CAN_FLAG_TRANS_ABORTED | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_STB_TRANS_OK | \ + CAN_FLAG_PTB_TRANS_OK | \ + CAN_FLAG_RB_ALMOST_FULL | \ + CAN_FLAG_RB_FIFO_FULL | \ + CAN_FLAG_RX_OVERRUN | \ + CAN_FLAG_RX_OK | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARB_LOST | \ + CAN_FLAG_ERR_PASSIVE | \ + CAN_FLAG_ERR_PASSIVE_NODE | \ + CAN_FLAG_REACH_WARN_LIMIT) + +#define CAN_FLAG_TX_ERR_MSK (CAN_FLAG_BUS_OFF | \ + CAN_FLAG_TB_FULL | \ + CAN_FLAG_ERR_INT | \ + CAN_FLAG_BUS_ERR | \ + CAN_FLAG_ARB_LOST | \ + CAN_FLAG_ERR_PASSIVE | \ + CAN_FLAG_ERR_PASSIVE_NODE | \ + CAN_FLAG_REACH_WARN_LIMIT) + +/** + * @} + */ + +/** + * @defgroup CAN_AF_Mask_Type CAN AF Mask Type + * @{ + */ +#define CAN_AF_MSK_STD_EXT (0x0U) /*!< Acceptance filter accept standard ID mask and extended ID mask. */ +#define CAN_AF_MSK_STD (CAN_ACF_AIDEE) /*!< Acceptance filter accept standard ID mask. */ +#define CAN_AF_MSK_EXT (CAN_ACF_AIDEE | \ + CAN_ACF_AIDE) /*!< Acceptance filter accept extended ID mask. */ +/** + * @} + */ + +/** + * @defgroup CAN_Error_Type CAN Error Type + * @{ + */ +#define CAN_ERR_NO (0U) /*!< No error. */ +#define CAN_ERR_BIT (CAN_EALCAP_KOER_0) /*!< Error is bit error. */ +#define CAN_ERR_FORM (CAN_EALCAP_KOER_1) /*!< Error is form error. */ +#define CAN_ERR_STUFF (CAN_EALCAP_KOER_1 | \ + CAN_EALCAP_KOER_0) /*!< Error is stuff error. */ +#define CAN_ERR_ACK (CAN_EALCAP_KOER_2) /*!< Error is ACK error. */ +#define CAN_ERR_CRC (CAN_EALCAP_KOER_2 | \ + CAN_EALCAP_KOER_0) /*!< Error is CRC error. */ +#define CAN_ERR_OTHER (CAN_EALCAP_KOER_2 | \ + CAN_EALCAP_KOER_1) /*!< Error is other error. */ +/** + * @} + */ + +/** + * @defgroup CAN_AF CAN Acceptance Filter + * @{ + */ +#define CAN_AF1 (CAN_ACFEN_AE_1) /*!< Acceptance filter 1 select bit. */ +#define CAN_AF2 (CAN_ACFEN_AE_2) /*!< Acceptance filter 2 select bit. */ +#define CAN_AF3 (CAN_ACFEN_AE_3) /*!< Acceptance filter 3 select bit. */ +#define CAN_AF4 (CAN_ACFEN_AE_4) /*!< Acceptance filter 4 select bit. */ +#define CAN_AF5 (CAN_ACFEN_AE_5) /*!< Acceptance filter 5 select bit. */ +#define CAN_AF6 (CAN_ACFEN_AE_6) /*!< Acceptance filter 6 select bit. */ +#define CAN_AF7 (CAN_ACFEN_AE_7) /*!< Acceptance filter 7 select bit. */ +#define CAN_AF8 (CAN_ACFEN_AE_8) /*!< Acceptance filter 8 select bit. */ +#define CAN_AF9 (CAN_ACFEN_AE_9) /*!< Acceptance filter 9 select bit. */ +#define CAN_AF10 (CAN_ACFEN_AE_10) /*!< Acceptance filter 10 select bit. */ +#define CAN_AF11 (CAN_ACFEN_AE_11) /*!< Acceptance filter 11 select bit. */ +#define CAN_AF12 (CAN_ACFEN_AE_12) /*!< Acceptance filter 12 select bit. */ +#define CAN_AF13 (CAN_ACFEN_AE_13) /*!< Acceptance filter 13 select bit. */ +#define CAN_AF14 (CAN_ACFEN_AE_14) /*!< Acceptance filter 14 select bit. */ +#define CAN_AF15 (CAN_ACFEN_AE_15) /*!< Acceptance filter 15 select bit. */ +#define CAN_AF16 (CAN_ACFEN_AE_16) /*!< Acceptance filter 16 select bit. */ +#define CAN_AF_ALL (0xFFFFU) +/** + * @} + */ + +/** + * @defgroup CAN_TTC_Transmit_Buffer_Mode CAN Time-triggered Communication Transmit Buffer Mode + * @{ + */ +#define CAN_TTC_TB_MODE_NORMAL (0x0U) /*!< TTC transmit buffer depends on the priority of STB which is defined by @ref CAN_STB_Priority_Mode */ +#define CAN_TTC_TB_MODE_PTR (CAN_TCTRL_TTTBM) /*!< TTC transmit buffer is pointed by TBSLOT.TBPTR(for data filling) and \ + TRG_CFG.TTPTR(for data transmission). */ +/** + * @} + */ + +/** + * @defgroup CAN_TTC_TBS_Pointer CAN Time-triggered Communication Transmit Buffer Slot Pointer + * @{ + */ +#define CAN_TTC_TBS_PTB (0x0U) /*!< Point to PTB. */ +#define CAN_TTC_TBS_STB1 (0x1U) /*!< Point to STB slot 1. */ +#define CAN_TTC_TBS_STB2 (0x2U) /*!< Point to STB slot 2. */ +#define CAN_TTC_TBS_STB3 (0x3U) /*!< Point to STB slot 3. */ +/** + * @} + */ + +/** + * @defgroup CAN_TTC_Status_Flag CAN Time-triggered Communication Status Flag + * @{ + */ +#define CAN_TTC_FLAG_TTI (CAN_TTCFG_TTIF) /*!< Time trigger interrupt flag. */ +#define CAN_TTC_FLAG_TEI (CAN_TTCFG_TEIF) /*!< Trigger error interrupt flag. */ +#define CAN_TTC_FLAG_WTI (CAN_TTCFG_WTIF) /*!< Watch trigger interrupt flag. */ + +#define CAN_TTC_FLAG_ALL (CAN_TTC_FLAG_TTI | \ + CAN_TTC_FLAG_TEI | \ + CAN_TTC_FLAG_WTI) +/** + * @} + */ + +/** + * @defgroup CAN_TTC_Interrupt_Type CAN Time-triggered Communication Interrupt Type + * @{ + */ +#define CAN_TTC_INT_TTI (CAN_TTCFG_TTIE) /*!< Time trigger interrupt. */ +#define CAN_TTC_INT_WTI (CAN_TTCFG_WTIE) /*!< Watch trigger interrupt. */ +#define CAN_TTC_INT_ALL (CAN_TTC_INT_TTI | CAN_TTC_INT_WTI) +/** + * @} + */ + +/** + * @defgroup CAN_TTC_NTU_Prescaler CAN Time-triggered Communication Network Time Unit Prescaler + * @{ + */ +#define CAN_TTC_NTU_PRESC_1 (0x0U) /*!< NTU is SBT bit time * 1. */ +#define CAN_TTC_NTU_PRESC_2 (CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 2. */ +#define CAN_TTC_NTU_PRESC_4 (CAN_TTCFG_T_PRESC_1) /*!< NTU is SBT bit time * 4. */ +#define CAN_TTC_NTU_PRESC_8 (CAN_TTCFG_T_PRESC_1 | \ + CAN_TTCFG_T_PRESC_0) /*!< NTU is SBT bit time * 8. */ +/** + * @} + */ + +/** + * @defgroup CAN_TTC_Trigger_Type CAN Time-triggered Communication Trigger Type + * @{ + */ +#define CAN_TTC_TRIG_IMMED_TRIG (0x0U) /*!< Immediate trigger for immediate transmission. */ +#define CAN_TTC_TRIG_TIME_TRIG (CAN_TRG_CFG_TTYPE_0) /*!< Time trigger for receive triggers. */ +#define CAN_TTC_TRIG_SSHOT_TRANS_TRIG (CAN_TRG_CFG_TTYPE_1) /*!< Single shot transmit trigger for exclusive time windows. */ +#define CAN_TTC_TRIG_TRANS_START_TRIG (CAN_TRG_CFG_TTYPE_1 | \ + CAN_TRG_CFG_TTYPE_0) /*!< Transmit start trigger for merged arbitrating time windows. */ +#define CAN_TTC_TRIG_TRANS_STOP_TRIG (CAN_TRG_CFG_TTYPE_2) /*!< Transmit stop trigger for merged arbitrating time windows. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CAN_Global_Functions + * @{ + */ + en_result_t CAN_Init(M4_CAN_TypeDef *CANx, const stc_can_init_t *pstcInit); + en_result_t CAN_StructInit(stc_can_init_t *pstcInit); + void CAN_DeInit(M4_CAN_TypeDef *CANx); + + void CAN_SWReset(M4_CAN_TypeDef *CANx); + void CAN_EnterNormalComm(M4_CAN_TypeDef *CANx); + + void CAN_SetWorkMode(M4_CAN_TypeDef *CANx, uint8_t u8WorkMode); + void CAN_SetTransMode(M4_CAN_TypeDef *CANx, uint8_t u8TransMode); + void CAN_SetSTBPrioMode(M4_CAN_TypeDef *CANx, uint8_t u8STBPrioMode); + void CAN_SetRBStoreSel(M4_CAN_TypeDef *CANx, uint8_t u8RBStoreSel); + void CAN_SetRBOvfOp(M4_CAN_TypeDef *CANx, uint8_t u8RBOvfOperation); + + void CAN_IntCmd(M4_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState); + en_result_t CAN_SBTConfig(M4_CAN_TypeDef *CANx, const stc_can_bt_cfg_t *pstcCfg); + uint8_t CAN_GetArbLostPos(const M4_CAN_TypeDef *CANx); + uint8_t CAN_GetErrType(const M4_CAN_TypeDef *CANx); + void CAN_SetRBSWarnLimit(M4_CAN_TypeDef *CANx, uint8_t u8RBSWarnLimit); + void CAN_SetErrWarnLimit(M4_CAN_TypeDef *CANx, uint8_t u8ErrWarnLimit); + uint8_t CAN_GetREC(const M4_CAN_TypeDef *CANx); + uint8_t CAN_GetTEC(const M4_CAN_TypeDef *CANx); + void CAN_ClrErrCount(M4_CAN_TypeDef *CANx); + en_result_t CAN_AFConfig(M4_CAN_TypeDef *CANx, uint16_t u16AFSel, const stc_can_af_cfg_t pstcAFCfg[]); + void CAN_AFCmd(M4_CAN_TypeDef *CANx, uint16_t u16AFSel, en_functional_state_t enNewState); + + uint8_t CAN_GetTBType(const M4_CAN_TypeDef *CANx); + void CAN_AbortTrans(M4_CAN_TypeDef *CANx, uint8_t u8TBType); + +en_flag_status_t CAN_GetStatus(const M4_CAN_TypeDef *CANx, uint32_t u32Flag); + void CAN_ClrStatus(M4_CAN_TypeDef *CANx, uint32_t u32Flag); + uint32_t CAN_GetStatusVal(const M4_CAN_TypeDef *CANx); + uint8_t CAN_GetTBFullStatus(const M4_CAN_TypeDef *CANx); + uint8_t CAN_GetRBFullStatus(const M4_CAN_TypeDef *CANx); + + en_result_t CAN_FD_Config(M4_CAN_TypeDef *CANx, const stc_can_fd_cfg_t *pstcCfg); + en_result_t CAN_FD_StructInit(stc_can_fd_cfg_t *pstcCfg); + void CAN_FD_Cmd(const M4_CAN_TypeDef *CANx, en_functional_state_t enNewState); + + en_result_t CAN_TTC_StructInit(stc_can_ttc_cfg_t *pstcCfg); + en_result_t CAN_TTC_Config(M4_CAN_TypeDef *CANx, const stc_can_ttc_cfg_t *pstcCfg); + void CAN_TTC_Cmd(M4_CAN_TypeDef *CANx, en_functional_state_t enNewState); + + void CAN_TTC_SetTBSToBeFilled(M4_CAN_TypeDef *CANx, uint8_t u8SlotPtr); + void CAN_TTC_SetTBSFilled(M4_CAN_TypeDef *CANx); + void CAN_TTC_SetNTUPrescaler(M4_CAN_TypeDef *CANx, uint8_t u8NTUPrescaler); + void CAN_TTC_IntCmd(M4_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState); +en_flag_status_t CAN_TTC_GetStatus(const M4_CAN_TypeDef *CANx, uint8_t u8Flag); + void CAN_TTC_ClrStatus(M4_CAN_TypeDef *CANx, uint8_t u8Flag); + uint8_t CAN_TTC_GetStatusVal(const M4_CAN_TypeDef *CANx); + void CAN_TTC_SetRefMsgID(M4_CAN_TypeDef *CANx, uint32_t u32ID); + void CAN_TTC_SetRefMsgIDE(M4_CAN_TypeDef *CANx, uint32_t u32IDE); + uint32_t CAN_TTC_GetRefMsgID(const M4_CAN_TypeDef *CANx); + uint32_t CAN_TTC_GetRefMsgIDE(const M4_CAN_TypeDef *CANx); + void CAN_TTC_SetTxTrigTBS(M4_CAN_TypeDef *CANx, uint8_t u8TBSlotPtr); + uint8_t CAN_TTC_GetTxTrigTBS(const M4_CAN_TypeDef *CANx); + void CAN_TTC_SetTrigType(M4_CAN_TypeDef *CANx, uint16_t u16TrigType); + uint16_t CAN_TTC_GetTrigType(const M4_CAN_TypeDef *CANx); + void CAN_TTC_SetTxEnableWindow(M4_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow); + uint16_t CAN_TTC_GetTxEnableWindow(const M4_CAN_TypeDef *CANx); + void CAN_TTC_SetTxTrigTime(M4_CAN_TypeDef *CANx, uint16_t u16TxTrigTime); + uint16_t CAN_TTC_GetTxTrigTime(const M4_CAN_TypeDef *CANx); + void CAN_TTC_SetWatchTrigTime(M4_CAN_TypeDef *CANx, uint16_t u16WatchTrigTime); + uint16_t CAN_TTC_GetWatchTrigTime(const M4_CAN_TypeDef *CANx); + + en_result_t CAN_TransData(M4_CAN_TypeDef *CANx, const stc_can_tx_t *pstcTx, + uint8_t u8TxBufType, uint8_t u8STBTxCtrl, uint32_t u32Timeout); + en_result_t CAN_TTC_TransData(M4_CAN_TypeDef *CANx, const stc_can_tx_t *pstcTx, uint8_t u8TBSlot); + + en_result_t CAN_ReceiveData(M4_CAN_TypeDef *CANx, stc_can_rx_t *pstcRx, uint8_t *pu8RxFrameCnt, uint8_t u8RxFrameBufLength); + +/** + * @} + */ + +#endif /* DDL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_CAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_clk.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_clk.h new file mode 100644 index 0000000000000000000000000000000000000000..471938bde6be1a2ab2708d8aa8a4bcf79c068caa --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_clk.h @@ -0,0 +1,1003 @@ +/** + ******************************************************************************* + * @file hc32f4a0_clk.h + * @brief This file contains all the functions prototypes of the CLK driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-07-03 Zhangxl _DIV64 definition for BUS clock division + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_CLK_H__ +#define __HC32F4A0_CLK_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_CLK + * @{ + */ + +#if (DDL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Types CLK Global Types + * @{ + */ +/** + * @brief CLK XTAL configuration structure definition + */ +typedef struct +{ + uint8_t u8XtalState; /*!< The new state of the XTAL. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8XtalDrv; /*!< The XTAL drive ability. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8XtalMode; /*!< The XTAL mode selection osc or exclk. + This parameter can be a value of @ref CLK_XTAL_Config */ + + uint8_t u8XtalStb; /*!< The XTAL stable time selection. + This parameter can be a value of @ref CLK_XTAL_Config */ +} stc_clk_xtal_init_t; + +/** + * @brief CLK XTALSTD configuration structure definition + */ +typedef struct +{ + uint8_t u8XtalStdState; /*!< Specifies the new state of XTALSTD. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8XtalStdMode; /*!< Specifies the XTALSTD mode. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8XtalStdInt; /*!< Specifies the XTALSTD interrupt on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ + + uint8_t u8XtalStdRst; /*!< Specifies the XTALSTD reset on or off. + This parameter can be a value of @ref CLK_XTALSTD_Config */ +} stc_clk_xtalstd_init_t; + +/** + * @brief CLK XTAL32 configuration structure definition + */ +typedef struct +{ + uint8_t u8Xtal32State; /*!< Xtal32 new state, + @ref CLK_XTAL32_Config for details */ + + uint8_t u8Xtal32Drv; /*!< Xtal32 drive capacity setting, + @ref CLK_XTAL32_Config for details */ + + uint8_t u8Xtal32NF; /*!< Xtal32 noise filter setting, + @ref CLK_XTAL32_Config for details */ +} stc_clk_xtal32_init_t; + +/** + * @brief CLK PLLH configuration structure definition + */ +typedef struct +{ + uint8_t u8PLLState; /*!< PLLH new state, + @ref CLK_PLLH_Config for details */ + union + { + uint32_t PLLCFGR; /* PLLH config register */ + struct + { + uint32_t PLLM :2; /*! PLLH M divide */ + uint32_t resvd0 :5; /*! reserved */ + uint32_t PLLSRC :1; /*! PLLH/PLLA source clock select */ + uint32_t PLLN :8; /*! PLLH N multi- */ + uint32_t resvd1 :4; /*! reserved */ + uint32_t PLLR :4; /*! PLLH R divide */ + uint32_t PLLQ :4; /*! PLLH Q divide */ + uint32_t PLLP :4; /*! PLLH P divide */ + } PLLCFGR_f; + }; +} stc_clk_pllh_init_t; + +/** + * @brief CLK PLLA configuration structure definition + */ +typedef struct +{ + uint8_t u8PLLState; /*!< PLLA new state, + @ref CLK_PLLA_Config for details */ + union + { + uint32_t PLLCFGR; /* PLLA config register */ + struct + { + uint32_t PLLM :5; /*!< PLLA M divide */ + uint32_t resvd0 :3; /*! reserved */ + uint32_t PLLN :9; /*!< PLLA N multi- */ + uint32_t resvd1 :3; /*!< reserved */ + uint32_t PLLR :4; /*!< PLLA R divide */ + uint32_t PLLQ :4; /*!< PLLA Q divide */ + uint32_t PLLP :4; /*!< PLLA P divide */ + } PLLCFGR_f; + }; +} stc_clk_plla_init_t; + +/** + * @brief CLK bus frequency structure definition + */ +typedef struct +{ + uint32_t sysclkFreq; /*!< System clock frequency. */ + uint32_t hclkFreq; /*!< Hclk frequency. */ + uint32_t exckFreq; /*!< Exclk frequency. */ + uint32_t pclk0Freq; /*!< Pclk0 frequency. */ + uint32_t pclk1Freq; /*!< Pclk1 frequency. */ + uint32_t pclk2Freq; /*!< Pclk2 frequency. */ + uint32_t pclk3Freq; /*!< Pclk3 frequency. */ + uint32_t pclk4Freq; /*!< Pclk4 frequency. */ +} stc_clk_freq_t; + +/** + * @brief CLK PLL clock frequency structure definition + */ +typedef struct +{ + uint32_t pllhvcin; /*!< pllh vcin clock frequency. */ + uint32_t pllhvco; /*!< pllh vco clock frequency. */ + uint32_t pllhp; /*!< pllhp clock frequency. */ + uint32_t pllhq; /*!< pllhq clock frequency. */ + uint32_t pllhr; /*!< pllhr clock frequency. */ + uint32_t pllavcin; /*!< plla vcin clock frequency. */ + uint32_t pllavco; /*!< plla vco clock frequency. */ + uint32_t pllap; /*!< pllap clock frequency. */ + uint32_t pllaq; /*!< pllaq clock frequency. */ + uint32_t pllar; /*!< pllar clock frequency. */ +} stc_pll_clk_freq_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Macros CLK Global Macros + * @{ + */ +/** + * @defgroup CLK_PLLH_FREQ PLLH P/Q/R frequency range definition + * @{ + */ +#define CLK_PLLH_FREQ_MIN (40UL*1000UL*1000UL) +#define CLK_PLLH_FREQ_MAX (240UL*1000UL*1000UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLH_VCO_IN PLLH VCO in frequency range definition + * @{ + */ +#define CLK_PLLH_VCO_IN_MIN (8UL*1000UL*1000UL) +#define CLK_PLLH_VCO_IN_MAX (24UL*1000UL*1000UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLH_VCO_OUT PLLH VCO out frequency range definition + * @{ + */ +#define CLK_PLLH_VCO_OUT_MIN (600UL*1000UL*1000UL) +#define CLK_PLLH_VCO_OUT_MAX (1200UL*1000UL*1000UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLHM_Div_Sel PLLH M divide range definition + * @{ + */ +#define CLK_PLLHM_DIV_MIN (1UL) +#define CLK_PLLHM_DIV_MAX (4UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLHN_Div_Sel PLLH N multi- range definition + * @{ + */ +#define CLK_PLLHN_MULTI_MIN (25UL) +#define CLK_PLLHN_MULTI_MAX (150UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLHR_Div_Sel PLLH R divide range definition + * @{ + */ +#define CLK_PLLHR_DIV_MIN (2UL) +#define CLK_PLLHR_DIV_MAX (16UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLHQ_Div_Sel PLLH Q divide range definition + * @{ + */ +#define CLK_PLLHQ_DIV_MIN (2UL) +#define CLK_PLLHQ_DIV_MAX (16UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLHP_Div_Sel PLLH P divide range definition + * @{ + */ +#define CLK_PLLHP_DIV_MIN (2UL) +#define CLK_PLLHP_DIV_MAX (16UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLA_FREQ PLLA P/Q/R frequency range definition + * @{ + */ +#define CLK_PLLA_FREQ_MIN (15UL*1000UL*1000UL) +#define CLK_PLLA_FREQ_MAX (240UL*1000UL*1000UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLA_VCO_IN PLLA VCO in frequency range definition + * @{ + */ +#define CLK_PLLA_VCO_IN_MIN (1UL*1000UL*1000UL) +#define CLK_PLLA_VCO_IN_MAX (24UL*1000UL*1000UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLA_VCO_OUT PLLA VCO out frequency range definition + * @{ + */ +#define CLK_PLLA_VCO_OUT_MIN (240UL*1000UL*1000UL) +#define CLK_PLLA_VCO_OUT_MAX (480UL*1000UL*1000UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLAM_Div_Sel PLLA M divide range definition + * @{ + */ +#define CLK_PLLAM_DIV_MIN (1UL) +#define CLK_PLLAM_DIV_MAX (24UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLAN_Div_Sel PLLA N multi- range definition + * @{ + */ +#define CLK_PLLAN_MULTI_MIN (20UL) +#define CLK_PLLAN_MULTI_MAX (480UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLAR_Div_Sel PLLA R divide range definition + * @{ + */ +#define CLK_PLLAR_DIV_MIN (2UL) +#define CLK_PLLAR_DIV_MAX (16UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLAQ_Div_Sel PLLA Q divide range definition + * @{ + */ +#define CLK_PLLAQ_DIV_MIN (2UL) +#define CLK_PLLAQ_DIV_MAX (16UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLAP_Div_Sel PLLA P divide range definition + * @{ + */ +#define CLK_PLLAP_DIV_MIN (2UL) +#define CLK_PLLAP_DIV_MAX (16UL) +/** + * @} + */ + +/** + * @defgroup CLK_Switch_Config Congigureation for system clock switching + * @{ + */ +/** + * @brief Stable waiting time while switching system clock. + * @note Approx. 1us based on 168M frequency. + */ +#define CLK_SYSCLK_SW_STABLE (0xB0UL) + +/** + * @brief FCGx default value. + */ +#define CLK_FCG0_DEFAULT (0xFFFFFA0EUL) +#define CLK_FCG1_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG2_DEFAULT (0xFFFFFFFFUL) +#define CLK_FCG3_DEFAULT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLA_Config PLLA Config + * @{ + */ +/** + * @brief PLLH function config. + */ +#define CLK_PLLA_OFF (CMU_PLLACR_PLLAOFF) +#define CLK_PLLA_ON (0x00U) + +/** + * @brief PLLH default config. + */ +#define CLK_PLLAP_DFT (0x01UL) +#define CLK_PLLAQ_DFT (0x01UL) +#define CLK_PLLAR_DFT (0x01UL) +#define CLK_PLLAN_DFT (0x13UL) +#define CLK_PLLAM_DFT (0x01UL) +/** + * @} + */ + +/** + * @defgroup CLK_PLLH_Config PLLH Config + * @{ + */ +/** + * @brief PLLH function config. + */ +#define CLK_PLLH_OFF (CMU_PLLHCR_PLLHOFF) +#define CLK_PLLH_ON (0x00U) + +/** + * @brief PLLH default config. + */ +#define CLK_PLLHP_DFT (0x01UL) +#define CLK_PLLHQ_DFT (0x01UL) +#define CLK_PLLHR_DFT (0x01UL) +#define CLK_PLLHN_DFT (0x13UL) +#define CLK_PLLHM_DFT (0x01UL) + +/** + * @brief PLLH/A source clock selction. + */ +#define CLK_PLLSRC_XTAL (0x00UL) +#define CLK_PLLSRC_HRC (0x01UL) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL_Config XTAL Config + * @{ + */ +/** + * @brief XTAL function config. + */ +#define CLK_XTAL_OFF (CMU_XTALCR_XTALSTP) +#define CLK_XTAL_ON (0x00U) + +/** + * @brief XTAL driver ability + * @note High: 20 ~ 24MHz, Mid: 16~20MHz, Low: 8~16MHz, ULow 4 ~ 8MHz. + */ +#define CLK_XTALDRV_HIGH (0x00U) +#define CLK_XTALDRV_MID (0x01U) +#define CLK_XTALDRV_LOW (0x02U) +#define CLK_XTALDRV_ULOW (0x03U) + +/** + * @brief XTAL mode selection osc or exclk + */ +#define CLK_XTALMODE_OSC (0x00U) +#define CLK_XTALMODE_EXCLK (0x01U) + +/** + * @brief XTAL stable time selection. + * @note a cycle of stable counter = a cycle of LRC divide by 8 + */ +#define CLK_XTALSTB_133US (0x01U) /*!< 35 stable count cycle, approx. 133us */ +#define CLK_XTALSTB_255US (0x02U) /*!< 67 stable count cycle, approx. 255us */ +#define CLK_XTALSTB_499US (0x03U) /*!< 131 stable count cycle, approx. 499us */ +#define CLK_XTALSTB_988US (0x04U) /*!< 259 stable count cycle, approx. 988us */ +#define CLK_XTALSTB_2MS (0x05U) /*!< 547 stable count cycle, approx. 2ms */ +#define CLK_XTALSTB_4MS (0x06U) /*!< 1059 stable count cycle, approx. 4ms */ +#define CLK_XTALSTB_8MS (0x07U) /*!< 2147 stable count cycle, approx. 8ms */ +#define CLK_XTALSTB_16MS (0x08U) /*!< 4291 stable count cycle, approx. 16ms */ +#define CLK_XTALSTB_31MS (0x09U) /*!< 8163 stable count cycle, approx. 32ms */ +/** + * @} + */ + +/** + * @defgroup CLK_XTALSTD_Config XTALSTD Config + * @{ + */ + +/** + * @brief XTAL error detection on or off + */ +#define CLK_XTALSTD_OFF (0x00U) +#define CLK_XTALSTD_ON (CMU_XTALSTDCR_XTALSTDE) + +/** + * @brief XTALSTD mode selection + */ +#define CLK_XTALSTD_MODE_RST (CMU_XTALSTDCR_XTALSTDRIS) +#define CLK_XTALSTD_MODE_INT (0x00U) + +/** + * @brief XTALSTD reset on or off + */ +#define CLK_XTALSTD_RST_OFF (0x00U) +#define CLK_XTALSTD_RST_ON (CMU_XTALSTDCR_XTALSTDRE) + +/** + * @brief XTALSTD interrupt on or off + */ +#define CLK_XTALSTD_INT_OFF (0x00U) +#define CLK_XTALSTD_INT_ON (CMU_XTALSTDCR_XTALSTDIE) +/** + * @} + */ + +/** + * @defgroup CLK_XTAL32_Config XTAL32 Config + * @{ + */ +/** + * @brief XTAL32 function config. + */ +#define CLK_XTAL32_OFF (CMU_XTAL32CR_XTAL32STP) +#define CLK_XTAL32_ON (0x00U) + +/** + * @brief XTAL32 driver ability. + */ +#define CLK_XTAL32DRV_MID (0x00U) +#define CLK_XTAL32DRV_HIGH (0x01U) + +/** + * @brief XTAL32 filtering seletion. + */ +#define CLK_XTAL32NF_FULL (0x00U) /*!< Valid in run,stop,power down mode. */ +#define CLK_XTAL32NF_PART (0x02U) /*!< Valid in run mode. */ +#define CLK_XTAL32NF_NONE (0x03U) /*!< Invalid in run,stop,power down mode. */ +/** + * @} + */ + +/** + * @defgroup CLK_HRC_Config HRC Config + * @{ + */ +#define CLK_HRC_OFF (CMU_HRCCR_HRCSTP) +#define CLK_HRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_MRC_Config HRC Config + * @{ + */ +#define CLK_MRC_OFF (CMU_MRCCR_MRCSTP) +#define CLK_MRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_LRC_Config LRC Config + * @{ + */ +#define CLK_LRC_OFF (CMU_LRCCR_LRCSTP) +#define CLK_LRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_RTCLRC_Config LRC Config + * @{ + */ +#define CLK_RTCLRC_OFF (CMU_RTCLRCCR_RTCLRCSTP) +#define CLK_RTCLRC_ON (0x00U) +/** + * @} + */ + +/** + * @defgroup CLK_STB_Flag CLK stable Flags + * @{ + */ +#define CLK_STB_FLAG_HRCSTB (CMU_OSCSTBSR_HRCSTBF) +#define CLK_STB_FLAG_XTALSTB (CMU_OSCSTBSR_XTALSTBF) +#define CLK_STB_FLAG_PLLASTB (CMU_OSCSTBSR_PLLASTBF) +#define CLK_STB_FLAG_PLLHSTB (CMU_OSCSTBSR_PLLHSTBF) +#define CLK_STB_FLAG_MASK ((CMU_OSCSTBSR_HRCSTBF) | \ + (CMU_OSCSTBSR_XTALSTBF)| \ + (CMU_OSCSTBSR_PLLASTBF)| \ + (CMU_OSCSTBSR_PLLHSTBF)) + +/** + * @} + */ + +/** + * @defgroup CLK_System_Clock_Source System Clock Source + * @{ + */ +#define CLK_SYSCLKSOURCE_HRC (0x00U) +#define CLK_SYSCLKSOURCE_MRC (0x01U) +#define CLK_SYSCLKSOURCE_LRC (0x02U) +#define CLK_SYSCLKSOURCE_XTAL (0x03U) +#define CLK_SYSCLKSOURCE_XTAL32 (0x04U) +#define CLK_SYSCLKSOURCE_PLLH (0x05U) +/** + * @} + */ + +/** + * @defgroup CLK_CATE_Sel Clock category selection + * @{ + */ +#define CLK_CATE_PCLK0 (0x01U) +#define CLK_CATE_PCLK1 (0x02U) +#define CLK_CATE_PCLK2 (0x04U) +#define CLK_CATE_PCLK3 (0x08U) +#define CLK_CATE_PCLK4 (0x10U) +#define CLK_CATE_EXCLK (0x20U) +#define CLK_CATE_HCLK (0x40U) +#define CLK_CATE_ALL (CLK_CATE_PCLK0 | CLK_CATE_PCLK1 | \ + CLK_CATE_PCLK2 | CLK_CATE_PCLK3 | \ + CLK_CATE_PCLK4 | CLK_CATE_EXCLK | \ + CLK_CATE_HCLK) +/** + * @} + */ + +/** + * @defgroup CLK_HCLK_Divider HCLK divider + * @{ + */ +#define CLK_HCLK_DIV1 (0x00U << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV2 (0x01U << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV4 (0x02U << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV8 (0x03U << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV16 (0x04U << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV32 (0x05U << CMU_SCFGR_HCLKS_POS) +#define CLK_HCLK_DIV64 (0x06U << CMU_SCFGR_HCLKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_EXCLK_Divider EXCLK divider + * @{ + */ +#define CLK_EXCLK_DIV1 (0x00U << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV2 (0x01U << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV4 (0x02U << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV8 (0x03U << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV16 (0x04U << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV32 (0x05U << CMU_SCFGR_EXCKS_POS) +#define CLK_EXCLK_DIV64 (0x06U << CMU_SCFGR_EXCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK4_Divider PCLK4 divider + * @{ + */ +#define CLK_PCLK4_DIV1 (0x00U << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV2 (0x01U << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV4 (0x02U << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV8 (0x03U << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV16 (0x04U << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV32 (0x05U << CMU_SCFGR_PCLK4S_POS) +#define CLK_PCLK4_DIV64 (0x06U << CMU_SCFGR_PCLK4S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK3_Divider PCLK3 divider + * @{ + */ +#define CLK_PCLK3_DIV1 (0x00U << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV2 (0x01U << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV4 (0x02U << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV8 (0x03U << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV16 (0x04U << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV32 (0x05U << CMU_SCFGR_PCLK3S_POS) +#define CLK_PCLK3_DIV64 (0x06U << CMU_SCFGR_PCLK3S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK2_Divider PCLK2 divider + * @{ + */ +#define CLK_PCLK2_DIV1 (0x00U << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV2 (0x01U << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV4 (0x02U << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV8 (0x03U << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV16 (0x04U << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV32 (0x05U << CMU_SCFGR_PCLK2S_POS) +#define CLK_PCLK2_DIV64 (0x06U << CMU_SCFGR_PCLK2S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK1_Divider PCLK1 divider + * @{ + */ +#define CLK_PCLK1_DIV1 (0x00U << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV2 (0x01U << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV4 (0x02U << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV8 (0x03U << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV16 (0x04U << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV32 (0x05U << CMU_SCFGR_PCLK1S_POS) +#define CLK_PCLK1_DIV64 (0x06U << CMU_SCFGR_PCLK1S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK0_Divider PCLK0 divider + * @{ + */ +#define CLK_PCLK0_DIV1 (0x00U << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV2 (0x01U << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV4 (0x02U << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV8 (0x03U << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV16 (0x04U << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV32 (0x05U << CMU_SCFGR_PCLK0S_POS) +#define CLK_PCLK0_DIV64 (0x06U << CMU_SCFGR_PCLK0S_POS) +/** + * @} + */ + +/** + * @defgroup CLK_USB_CLK_Sel USB clock selection + * @{ + */ +#define CLK_USB_CLK_MCLK_DIV2 (0x01U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_MCLK_DIV3 (0x02U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_MCLK_DIV4 (0x03U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_MCLK_DIV5 (0x04U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_MCLK_DIV6 (0x05U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_MCLK_DIV7 (0x06U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_MCLK_DIV8 (0x07U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_PLLHQ (0x08U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_PLLHR (0x09U << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_PLLAP (0x0AU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_PLLAQ (0x0BU << CMU_USBCKCFGR_USBCKS_POS) +#define CLK_USB_CLK_PLLAR (0x0CU << CMU_USBCKCFGR_USBCKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_CAN_CLK_Sel CAN clock selection + * @{ + */ +#define CLK_CAN_CLK_MCLK_DIV2 (0x01U) +#define CLK_CAN_CLK_MCLK_DIV3 (0x02U) +#define CLK_CAN_CLK_MCLK_DIV4 (0x03U) +#define CLK_CAN_CLK_MCLK_DIV5 (0x04U) +#define CLK_CAN_CLK_MCLK_DIV6 (0x05U) +#define CLK_CAN_CLK_MCLK_DIV7 (0x06U) +#define CLK_CAN_CLK_MCLK_DIV8 (0x07U) +#define CLK_CAN_CLK_PLLHQ (0x08U) +#define CLK_CAN_CLK_PLLHR (0x09U) +#define CLK_CAN_CLK_PLLAP (0x0AU) +#define CLK_CAN_CLK_PLLAQ (0x0BU) +#define CLK_CAN_CLK_PLLAR (0x0CU) +#define CLK_CAN_CLK_XTAL (0x0DU) +#define CLK_CAN1_CLK_MCLK_DIV2 (CLK_CAN_CLK_MCLK_DIV2) +#define CLK_CAN1_CLK_MCLK_DIV3 (CLK_CAN_CLK_MCLK_DIV3) +#define CLK_CAN1_CLK_MCLK_DIV4 (CLK_CAN_CLK_MCLK_DIV4) +#define CLK_CAN1_CLK_MCLK_DIV5 (CLK_CAN_CLK_MCLK_DIV5) +#define CLK_CAN1_CLK_MCLK_DIV6 (CLK_CAN_CLK_MCLK_DIV6) +#define CLK_CAN1_CLK_MCLK_DIV7 (CLK_CAN_CLK_MCLK_DIV7) +#define CLK_CAN1_CLK_MCLK_DIV8 (CLK_CAN_CLK_MCLK_DIV8) +#define CLK_CAN1_CLK_PLLHQ (CLK_CAN_CLK_PLLHQ) +#define CLK_CAN1_CLK_PLLHR (CLK_CAN_CLK_PLLHR) +#define CLK_CAN1_CLK_PLLAP (CLK_CAN_CLK_PLLAP) +#define CLK_CAN1_CLK_PLLAQ (CLK_CAN_CLK_PLLAQ) +#define CLK_CAN1_CLK_PLLAR (CLK_CAN_CLK_PLLAR) +#define CLK_CAN1_CLK_XTAL (CLK_CAN_CLK_XTAL) +#define CLK_CAN2_CLK_MCLK_DIV2 (CLK_CAN_CLK_MCLK_DIV2 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_MCLK_DIV3 (CLK_CAN_CLK_MCLK_DIV3 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_MCLK_DIV4 (CLK_CAN_CLK_MCLK_DIV4 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_MCLK_DIV5 (CLK_CAN_CLK_MCLK_DIV5 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_MCLK_DIV6 (CLK_CAN_CLK_MCLK_DIV6 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_MCLK_DIV7 (CLK_CAN_CLK_MCLK_DIV7 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_MCLK_DIV8 (CLK_CAN_CLK_MCLK_DIV8 << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_PLLHQ (CLK_CAN_CLK_PLLHQ << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_PLLHR (CLK_CAN_CLK_PLLHR << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_PLLAP (CLK_CAN_CLK_PLLAP << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_PLLAQ (CLK_CAN_CLK_PLLAQ << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_PLLAR (CLK_CAN_CLK_PLLAR << CMU_CANCKCFGR_CAN2CKS_POS) +#define CLK_CAN2_CLK_XTAL (CLK_CAN_CLK_XTAL << CMU_CANCKCFGR_CAN2CKS_POS) +/** + * @} + */ + +/** + * @defgroup CLK_CAN_CH_Sel CAN channel for clock selection + * @{ + */ +#define CLK_CAN_CH1 (0x01U) +#define CLK_CAN_CH2 (0x02U) +#define CLK_CAN_CH_ALL (CLK_CAN_CH1 | CLK_CAN_CH2) +/** + * @} + */ + +/** + * @defgroup CLK_I2S_CLK_Sel I2S clock selection + * @{ + */ +#define CLK_I2S_CLK_PCLK (0x0000U) +#define CLK_I2S_CLK_PLLHQ (0x0008U) +#define CLK_I2S_CLK_PLLHR (0x0009U) +#define CLK_I2S_CLK_PLLAP (0x000AU) +#define CLK_I2S_CLK_PLLAQ (0x000BU) +#define CLK_I2S_CLK_PLLAR (0x000CU) +#define CLK_I2S1_CLK_PCLK (CLK_I2S_CLK_PCLK) +#define CLK_I2S1_CLK_PLLHQ (CLK_I2S_CLK_PLLHQ) +#define CLK_I2S1_CLK_PLLHR (CLK_I2S_CLK_PLLHR) +#define CLK_I2S1_CLK_PLLAP (CLK_I2S_CLK_PLLAP) +#define CLK_I2S1_CLK_PLLAQ (CLK_I2S_CLK_PLLAQ) +#define CLK_I2S1_CLK_PLLAR (CLK_I2S_CLK_PLLAR) +#define CLK_I2S2_CLK_PCLK (CLK_I2S_CLK_PCLK << CMU_I2SCKSEL_I2S2CKSEL_POS) +#define CLK_I2S2_CLK_PLLHQ (CLK_I2S_CLK_PLLHQ << CMU_I2SCKSEL_I2S2CKSEL_POS) +#define CLK_I2S2_CLK_PLLHR (CLK_I2S_CLK_PLLHR << CMU_I2SCKSEL_I2S2CKSEL_POS) +#define CLK_I2S2_CLK_PLLAP (CLK_I2S_CLK_PLLAP << CMU_I2SCKSEL_I2S2CKSEL_POS) +#define CLK_I2S2_CLK_PLLAQ (CLK_I2S_CLK_PLLAQ << CMU_I2SCKSEL_I2S2CKSEL_POS) +#define CLK_I2S2_CLK_PLLAR (CLK_I2S_CLK_PLLAR << CMU_I2SCKSEL_I2S2CKSEL_POS) +#define CLK_I2S3_CLK_PCLK (CLK_I2S_CLK_PCLK << CMU_I2SCKSEL_I2S3CKSEL_POS) +#define CLK_I2S3_CLK_PLLHQ (CLK_I2S_CLK_PLLHQ << CMU_I2SCKSEL_I2S3CKSEL_POS) +#define CLK_I2S3_CLK_PLLHR (CLK_I2S_CLK_PLLHR << CMU_I2SCKSEL_I2S3CKSEL_POS) +#define CLK_I2S3_CLK_PLLAP (CLK_I2S_CLK_PLLAP << CMU_I2SCKSEL_I2S3CKSEL_POS) +#define CLK_I2S3_CLK_PLLAQ (CLK_I2S_CLK_PLLAQ << CMU_I2SCKSEL_I2S3CKSEL_POS) +#define CLK_I2S3_CLK_PLLAR (CLK_I2S_CLK_PLLAR << CMU_I2SCKSEL_I2S3CKSEL_POS) +#define CLK_I2S4_CLK_PCLK (CLK_I2S_CLK_PCLK << CMU_I2SCKSEL_I2S4CKSEL_POS) +#define CLK_I2S4_CLK_PLLHQ (CLK_I2S_CLK_PLLHQ << CMU_I2SCKSEL_I2S4CKSEL_POS) +#define CLK_I2S4_CLK_PLLHR (CLK_I2S_CLK_PLLHR << CMU_I2SCKSEL_I2S4CKSEL_POS) +#define CLK_I2S4_CLK_PLLAP (CLK_I2S_CLK_PLLAP << CMU_I2SCKSEL_I2S4CKSEL_POS) +#define CLK_I2S4_CLK_PLLAQ (CLK_I2S_CLK_PLLAQ << CMU_I2SCKSEL_I2S4CKSEL_POS) +#define CLK_I2S4_CLK_PLLAR (CLK_I2S_CLK_PLLAR << CMU_I2SCKSEL_I2S4CKSEL_POS) +/** + * @} + */ + +/** + * @defgroup CLK_I2S_CH_Sel I2S channel for clock selection + * @{ + */ +#define CLK_I2S_CH1 (0x01U) +#define CLK_I2S_CH2 (0x02U) +#define CLK_I2S_CH3 (0x04U) +#define CLK_I2S_CH4 (0x08U) +#define CLK_I2S_CH_ALL (CLK_I2S_CH1 | CLK_I2S_CH2 | CLK_I2S_CH3 | CLK_I2S_CH4) +/** + * @} + */ + +/** + * @defgroup CLK_PCLK24_Sel PCLK2/4 selection + * @{ + */ +#define CLK_PERI_CLK_PCLK (0x0000U) +#define CLK_PERI_CLK_PLLHQ (0x0008U) +#define CLK_PERI_CLK_PLLHR (0x0009U) +#define CLK_PERI_CLK_PLLAP (0x000AU) +#define CLK_PERI_CLK_PLLAQ (0x000BU) +#define CLK_PERI_CLK_PLLAR (0x000CU) +/** + * @} + */ + +/** + * @defgroup CLK_TPIU_Divider TPIU clock divider + * @{ + */ +#define CLK_TPIU_CLK_DIV1 (0x00U) +#define CLK_TPIU_CLK_DIV2 (0x01U) +#define CLK_TPIU_CLK_DIV4 (0x02U) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Source CLK MCO Clock Source + * @{ + */ +#define CLK_MCOSOURCCE_HRC (0x00U) +#define CLK_MCOSOURCCE_MRC (0x01U) +#define CLK_MCOSOURCCE_LRC (0x02U) +#define CLK_MCOSOURCCE_XTAL (0x03U) +#define CLK_MCOSOURCCE_XTAL32 (0x04U) +#define CLK_MCOSOURCCE_PLLHP (0x06U) +#define CLK_MCOSOURCCE_PLLAP (0x07U) +#define CLK_MCOSOURCCE_PLLHQ (0x08U) +#define CLK_MCOSOURCCE_PLLAQ (0x09U) +#define CLK_MCOSOURCCE_PLLAR (0x0AU) +#define CLK_MCOSOURCCE_SYSCLK (0x0BU) +/** + * @} + */ + +/** + * @defgroup CLK_MCO_Clock_Prescaler CLK MCO Clock Prescaler + * @{ + */ +#define CLK_MCO_DIV1 (0x00U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV2 (0x01U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV4 (0x02U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV8 (0x03U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV16 (0x04U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV32 (0x05U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV64 (0x06U << CMU_MCO2CFGR_MCO2DIV_POS) +#define CLK_MCO_DIV128 (0x07U << CMU_MCO2CFGR_MCO2DIV_POS) +/** + * @} + */ + + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CLK_Global_Functions + * @{ + */ +en_result_t CLK_XtalStdStrucInit(stc_clk_xtalstd_init_t* pstcXtalStdInit); +en_result_t CLK_XtalStdInit(const stc_clk_xtalstd_init_t* pstcXtalStdInit); +void CLK_ClearXtalStdStatus(void); +en_flag_status_t CLK_GetXtalStdStatus(void); + +void CLK_HrcTrim(int8_t i8TrimVal); +void CLK_MrcTrim(int8_t i8TrimVal); +void CLK_LrcTrim(int8_t i8TrimVal); +void CLK_RtcLrcTrim(int8_t i8TrimVal); + +en_result_t CLK_XtalCmd(en_functional_state_t enNewState); +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState); +en_result_t CLK_HrcCmd(en_functional_state_t enNewState); +en_result_t CLK_MrcCmd(en_functional_state_t enNewState); +en_result_t CLK_LrcCmd(en_functional_state_t enNewState); +en_result_t CLK_PLLACmd(en_functional_state_t enNewState); +en_result_t CLK_PLLHCmd(en_functional_state_t enNewState); + +en_result_t CLK_PLLAStrucInit(stc_clk_plla_init_t* pstcPLLAInit); +en_result_t CLK_PLLAInit(const stc_clk_plla_init_t *pstcPLLAInit); + +en_result_t CLK_PLLHStrucInit(stc_clk_pllh_init_t* pstcPLLHInit); +en_result_t CLK_PLLHInit(const stc_clk_pllh_init_t *pstcPLLHInit); + +en_result_t CLK_XtalStrucInit(stc_clk_xtal_init_t* pstcXtalInit); +en_result_t CLK_XtalInit(const stc_clk_xtal_init_t *pstcXtalInit); + +en_result_t CLK_Xtal32StrucInit(stc_clk_xtal32_init_t* pstcXtal32Init); +en_result_t CLK_Xtal32Init(const stc_clk_xtal32_init_t *pstcXtal32Init); + +en_flag_status_t CLK_GetStableStatus(uint8_t u8StableFlag); + +void CLK_SetSysClkSrc(uint8_t u8Src); +void CLK_ClkDiv(uint8_t u8ClkCate, uint32_t u32Div); + +void CLK_USB_ClkConfig(uint8_t u8UsbClk); +void CLK_CAN_ClkConfig(uint8_t u8CanCh, uint8_t u8CanClk); +void CLK_I2S_ClkConfig(uint8_t u8I2sCh, uint16_t u16I2sClk); +void CLK_PERI_ClkConfig(uint16_t u16Periclk); + +void CLK_TpiuClkCmd(en_functional_state_t enNewState); +void CLK_TpiuClkConfig(uint8_t u8TpiuDiv); + +void CLK_MCO1Config(uint8_t CLK_MCOSource, uint8_t CLK_MCODiv); +void CLK_MCO1Cmd(en_functional_state_t enNewState); +void CLK_MCO2Config(uint8_t CLK_MCOSource, uint8_t CLK_MCODiv); +void CLK_MCO2Cmd(en_functional_state_t enNewState); + +en_result_t CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq); +en_result_t CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq); +void CLK_SetPLLSrc(uint32_t u32PllSrc); + + +/** + * @} + */ + +#endif /* DDL_CLK_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_CLK_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_cmp.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_cmp.h new file mode 100644 index 0000000000000000000000000000000000000000..6e4b1ec98f3398ef92286283b263f481cacae9fa --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_cmp.h @@ -0,0 +1,374 @@ +/** + ******************************************************************************* + * @file hc32f4a0_cmp.h + * @brief Head file for CMP module. + * + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_CMP_H__ +#define __HC32F4A0_CMP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_CMP + * @{ + */ + +#if (DDL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CMP_Global_Types CMP Global Types + * @{ + */ + +/** + * @brief CMP configuration structure + */ +typedef struct +{ + uint8_t u8CmpCh; /*!< Select the compare voltage channel for normal mode + @ref CMP_CVSL_Channal */ + uint16_t u16CmpVol; /*!< Select the compare voltage source for normal mode + (Config the parameter when use CMP1 or CMP3)@ref CMP1_3_CVSL_Source */ + uint8_t u8RefVol; /*!< Reference voltage for normal mode, @ref CMP_RVSL_Source*/ + + uint8_t u8OutPolarity; /*!< Output polarity select, @ref CMP_Out_Polarity_Select */ + + uint8_t u8OutDetectEdges; /*!< Output detecte edge, @ref CMP_Out_Detect_Edge */ + + uint8_t u8OutFilter; /*!< Output Filter, @ref CMP_Out_Filter */ +}stc_cmp_init_t; + +/** + * @brief CMP reference voltage for window mode configuration structure + */ +typedef struct +{ + uint8_t u8CmpCh1; /*!< Select the compare voltage channel for window mode + @ref CMP_CVSL_Channal */ + uint16_t u16CmpVol; /*!< Select the compare voltage source for window mode + (Config the parameter when use CMP1 or CMP3)@ref CMP1_3_CVSL_Source */ + uint8_t u8CmpCh2; /*!< Select the compare voltage channel for window mode + @ref CMP_CVSL_Channal */ + uint8_t u8WinVolLow; /*!< CMP reference low voltage for window mode + @ref CMP_RVSL_Source */ + uint8_t u8WinVolHigh; /*!< CMP reference high voltage for window mode + @ref CMP_RVSL_Source */ +}stc_cmp_win_ref_t; + +/** + * @brief CMP timer windows function configuration structure + */ +typedef struct +{ + uint16_t u16TWSelect; /*!< Timer window source select + @ref CMP_TimerWin_Select */ + uint8_t u8TWOutLevel; /*!< Timer window mode output level + @ref CMP_TimerWin_output_Level*/ + uint8_t u8TWInvalidLevel; /*!< Output level when timer window invalid + @ref CMP_TimerWin_Invalid_Level */ +}stc_cmp_timerwindow_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup CMP_Global_Macros CMP Global Macros + * @{ + */ + +/** @defgroup CMP_Mode CMP compare mode + * @{ + */ +#define CMP_MODE_NORMAL (0x00U) /*!< Normal mode */ +#define CMP_MODE_WINDOW (CMP_MDR_CWDE) /*!< Window mode */ +/** + * @} + */ + +/** @defgroup CMP_CVSL_Channal CMP compare voltage channel selection + * @{ + */ +#define CMP_CVSL_NONE (0x0U) /*!< No input compare voltage */ +#define CMP_CVSL_INP1 (CMP_PMSR_CVSL_0) /*!< Select INP1 as compare voltage */ +#define CMP_CVSL_INP2 (CMP_PMSR_CVSL_1) /*!< Select INP2 as compare voltage */ +#define CMP_CVSL_INP3 (CMP_PMSR_CVSL_2) /*!< Select INP3 as compare voltage */ +#define CMP_CVSL_INP4 (CMP_PMSR_CVSL_3) /*!< Select INP4 as compare voltage */ +/** + * @} + */ + +/** @defgroup CMP_RVSL_Source CMP reference voltage selection + * @{ + */ +#define CMP_RVSL_NONE (0x0U) /*!< No input reference voltage */ +#define CMP_RVSL_INM1 (CMP_PMSR_RVSL_0) /*!< Select INM1 as reference voltage */ +#define CMP_RVSL_INM2 (CMP_PMSR_RVSL_1) /*!< Select INM2 as reference voltage */ +#define CMP_RVSL_INM3 (CMP_PMSR_RVSL_2) /*!< Select INM3 as reference voltage */ +#define CMP_RVSL_INM4 (CMP_PMSR_RVSL_3) /*!< Select INM4 as reference voltage */ +/** + * @} + */ + +/** @defgroup CMP1_3_CVSL_Source CMP1 CMP3 compare voltage selection + * @{ + */ +#define CMP1_INP3_NONE (0x0U) /*!< No input voltage to CMP1 INP3 */ +#define CMP1_INP3_CMP1_INP3 (CMP_VISR_P3SL_0) /*!< Select CMP1_INP3 as CMP1 INP3 input */ +#define CMP1_INP3_CMP2_INP3 (CMP_VISR_P3SL_1) /*!< Select CMP2_INP3 as CMP1 INP3 input */ +#define CMP1_INP2_NONE (0x0U) /*!< No input voltage to CMP1 INP2 */ +#define CMP1_INP2_PGA1 (CMP_VISR_P2SL_0) /*!< Select PGA1 as CMP1 INP2 input */ +#define CMP1_INP2_PGA2 (CMP_VISR_P2SL_1) /*!< Select PGA2 as CMP1 INP2 input */ +#define CMP1_INP2_CMP1_INP2 (CMP_VISR_P2SL_2) /*!< Select CMP1_INP2 as CMP1 INP2 input */ +#define CMP3_INP3_NONE (0x0U) /*!< No input voltage to CMP3 INP3 */ +#define CMP3_INP3_CMP3_INP3 (CMP_VISR_P3SL_0) /*!< Select CMP3_INP3 as CMP3 INP3 input */ +#define CMP3_INP3_CMP4_INP3 (CMP_VISR_P3SL_1) /*!< Select CMP4_INP3 as CMP3 INP3 input */ +#define CMP3_INP2_NONE (0x0U) /*!< No input voltage to CMP3 INP2 */ +#define CMP3_INP2_PGA3 (CMP_VISR_P2SL_0) /*!< Select PGA3 as CMP3 INP2 input */ +#define CMP3_INP2_PGA4 (CMP_VISR_P2SL_1) /*!< Select PGA4 as CMP3 INP2 input */ +#define CMP3_INP2_CMP3_INP2 (CMP_VISR_P2SL_2) /*!< Select CMP3_INP2 as CMp3 INP2 input */ +/** + * @} + */ + +/** @defgroup CMP_Out_Polarity_Select CMP output polarity selection + * @{ + */ +#define CMP_OUT_REVERSE_OFF (0x0U) /*!< CMP output don't reverse */ +#define CMP_OUT_REVERSE_ON (CMP_OCR_COPS) /*!< CMP output level reverse */ +/** + * @} + */ + +/** @defgroup CMP_Out_Detect_Edge CMP output detect edge selection + * @{ + */ +#define CMP_DETECT_EDGS_NONE (0U) /*!< Do not detect edge */ +#define CMP_DETECT_EDGS_RISING (1U << CMP_FIR_EDGS_POS) /*!< Detect rising edge */ +#define CMP_DETECT_EDGS_FALLING (2U << CMP_FIR_EDGS_POS) /*!< Detect falling edge */ +#define CMP_DETECT_EDGS_BOTH (3U << CMP_FIR_EDGS_POS) /*!< Detect rising and falling edges */ +/** + * @} + */ + +/** @defgroup CMP_Out_Filter CMP output filter configuration + * @{ + */ +#define CMP_OUT_FILTER_NONE (0U) /*!< Do not filter */ +#define CMP_OUT_FILTER_PCLK3 (1U) /*!< Use pclk3 */ +#define CMP_OUT_FILTER_PCLK3_DIV8 (2U) /*!< Use pclk3/8 */ +#define CMP_OUT_FILTER_PCLK3_DIV32 (3U) /*!< Use pclk3/32 */ +/** + * @} + */ + +/** @defgroup CMP_TimerWin_func CMP timer window function configuration + * @{ + */ +#define CMP_TIMERWIN_OFF (0x0U) /*!< Disable Timer Window function */ +#define CMP_TIMERWIN_ON (CMP_OCR_TWOE) /*!< Enable Timer Window function */ +/** + * @} + */ + +/** @defgroup CMP_TimerWin_Select CMP output timer window function control signal definition for CMP + * @{ + */ +#define CMP_1_TIMERWIN_TIMA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_1_PWM1 as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIMA_3_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_3_PWM1 as timer window signal for CMP2*/ +#define CMP_3_TIMERWIN_TIMA_1_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_1_PWM1 as timer window signal for CMP3*/ +#define CMP_4_TIMERWIN_TIMA_2_PWM1 (CMP_TWSR_CTWS0) /*!< Selection TIMA_2_PWM1 as timer window signal for CMP4*/ + +#define CMP_1_TIMERWIN_TIMA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_1_PWM2 as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIMA_3_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_3_PWM2 as timer window signal for CMP2*/ +#define CMP_3_TIMERWIN_TIMA_1_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_1_PWM2 as timer window signal for CMP3*/ +#define CMP_4_TIMERWIN_TIMA_2_PWM2 (CMP_TWSR_CTWS1) /*!< Selection TIMA_2_PWM2 as timer window signal for CMP4*/ + +#define CMP_1_TIMERWIN_TIMA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_1_PWM3 as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIMA_3_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_3_PWM3 as timer window signal for CMP2*/ +#define CMP_3_TIMERWIN_TIMA_1_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_1_PWM3 as timer window signal for CMP3*/ +#define CMP_4_TIMERWIN_TIMA_2_PWM3 (CMP_TWSR_CTWS2) /*!< Selection TIMA_2_PWM3 as timer window signal for CMP3*/ + +#define CMP_1_TIMERWIN_TIMA_2_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_2_PWM1 as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIMA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_4_PWM1 as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIMA_3_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_3_PWM1 as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIMA_4_PWM1 (CMP_TWSR_CTWS3) /*!< Selection TIMA_4_PWM1 as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIMA_2_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_2_PWM2 as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIMA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_4_PWM2 as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIMA_3_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_3_PWM2 as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIMA_4_PWM2 (CMP_TWSR_CTWS4) /*!< Selection TIMA_4_PWM2 as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIMA_2_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_2_PWM3 as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIMA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_4_PWM3 as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIMA_3_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_3_PWM3 as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIMA_4_PWM3 (CMP_TWSR_CTWS5) /*!< Selection TIMA_4_PWM3 as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM6_1_PWMA (CMP_TWSR_CTWS6) /*!< Selection TIM6_1_PWMA as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM6_5_PWMA (CMP_TWSR_CTWS6) /*!< Selection TIM6_5_PWMA as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM6_1_PWMB (CMP_TWSR_CTWS6) /*!< Selection TIM6_1_PWMB as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM6_5_PWMB (CMP_TWSR_CTWS6) /*!< Selection TIM6_5_PWMB as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM6_2_PWMA (CMP_TWSR_CTWS7) /*!< Selection TIM6_2_PWMA as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM6_6_PWMA (CMP_TWSR_CTWS7) /*!< Selection TIM6_6_PWMA as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM6_2_PWMB (CMP_TWSR_CTWS7) /*!< Selection TIM6_2_PWMB as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM6_6_PWMB (CMP_TWSR_CTWS7) /*!< Selection TIM6_6_PWMB as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM6_3_PWMA (CMP_TWSR_CTWS8) /*!< Selection TIM6_3_PWMA as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM6_7_PWMA (CMP_TWSR_CTWS8) /*!< Selection TIM6_7_PWMA as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM6_3_PWMB (CMP_TWSR_CTWS8) /*!< Selection TIM6_3_PWMB as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM6_7_PWMB (CMP_TWSR_CTWS8) /*!< Selection TIM6_7_PWMB as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM6_4_PWMA (CMP_TWSR_CTWS9) /*!< Selection TIM6_4_PWMA as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM6_8_PWMA (CMP_TWSR_CTWS9) /*!< Selection TIM6_8_PWMA as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM6_4_PWMB (CMP_TWSR_CTWS9) /*!< Selection TIM6_4_PWMB as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM6_8_PWMB (CMP_TWSR_CTWS9) /*!< Selection TIM6_8_PWMB as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM4_1_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_1_OUH as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM4_2_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_2_OUH as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM4_3_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_3_OUH as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM4_3_OUH (CMP_TWSR_CTWS10) /*!< Selection TIM4_4_OUH as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM4_1_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_1_OUL as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM4_2_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_2_OUL as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM4_3_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_3_OUL as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM4_3_OUL (CMP_TWSR_CTWS11) /*!< Selection TIM4_4_OUL as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM4_1_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_1_OVH as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM4_2_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_2_OVH as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM4_3_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_3_OVH as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM4_3_OVH (CMP_TWSR_CTWS12) /*!< Selection TIM4_4_OVH as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM4_1_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_1_OVL as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM4_2_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_2_OVL as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM4_3_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_3_OVL as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM4_3_OVL (CMP_TWSR_CTWS13) /*!< Selection TIM4_4_OVL as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM4_1_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_1_OWH as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM4_2_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_2_OWH as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM4_3_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_3_OWH as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM4_3_OWH (CMP_TWSR_CTWS14) /*!< Selection TIM4_4_OWH as timer window signal for CMP4 */ + +#define CMP_1_TIMERWIN_TIM4_1_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_1_OWL as timer window signal for CMP1 */ +#define CMP_2_TIMERWIN_TIM4_2_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_2_OWL as timer window signal for CMP2 */ +#define CMP_3_TIMERWIN_TIM4_3_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_3_OWL as timer window signal for CMP3 */ +#define CMP_4_TIMERWIN_TIM4_3_OWL (CMP_TWSR_CTWS15) /*!< Selection TIM4_4_OWL as timer window signal for CMP4 */ +/** + * @} + */ + +/** @defgroup CMP_TimerWin_Invalid_Level CMP output level when timer window invalid + * @{ + */ +#define CMP_TIMERWIN_INVALID_LEVEL_LOW (0x0U) /*!< Output Low when timer window invalid */ +#define CMP_TIMERWIN_INVALID_LEVEL_HIGH (CMP_OCR_TWOL) /*!< Output High when timer window invalid */ +/** + * @} + */ + +/** @defgroup CMP_TimerWin_output_Level CMP output level in timer windows mode + * @{ + */ +#define CMP_TIMERWIN_OUT_LEVEL_LOW (0U) /*!< Output Low in timer windows mode */ +#define CMP_TIMERWIN_OUT_LEVEL_HIGH (1U) /*!< Output High in timer windows mode */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CMP_Global_Functions + * @{ + */ +en_result_t CMP_StructInit(stc_cmp_init_t *pstcCMP_InitStruct); +en_result_t CMP_NormalModeInit(M4_CMP_TypeDef *CMPx, + const stc_cmp_init_t *pstcCmpInit); +en_result_t CMP_WindowModeInit(const M4_CMP_TypeDef *CMPx, + const stc_cmp_init_t *pstcCmpInit, + const stc_cmp_win_ref_t *pstcCmpWinRef); +en_result_t CMP_TimerWindowConfig(M4_CMP_TypeDef *CMPx, + const stc_cmp_timerwindow_t *pstcCMP_TimerWinStruct); + +void CMP_FuncCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus); +void CMP_IntCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus); +void CMP_OutputCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus); +void CMP_VCOUTCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus); +void CMP_SetOutDetectEdges(M4_CMP_TypeDef *CMPx, uint8_t u8CmpEdges); +void CMP_SetOutputFilter(M4_CMP_TypeDef *CMPx, uint8_t u8CmpFilter); +void CMP_SetOutputPolarity(M4_CMP_TypeDef *CMPx, uint8_t u8CmpPolarity); +void CMP_SetCompareVol(M4_CMP_TypeDef *CMPx, uint8_t u8CmpCh, uint8_t u8CmpVol); +void CMP_SetRefVol(M4_CMP_TypeDef *CMPx, uint8_t u8RefVol); +void CMP_DeInit(M4_CMP_TypeDef *CMPx); +void CMP_SetTimerWinSignal(M4_CMP_TypeDef *CMPx, \ + uint16_t u16TWSignal, en_functional_state_t enNewStatus); +en_flag_status_t CMP_GetResult(const M4_CMP_TypeDef *CMPx); +/** + * @} + */ + +#endif /* DDL_CMP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_CMP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_crc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_crc.h new file mode 100644 index 0000000000000000000000000000000000000000..255866ecd4c9a8ecef56cf329ed495abab448016 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_crc.h @@ -0,0 +1,143 @@ +/** + ******************************************************************************* + * @file hc32f4a0_crc.h + * @brief This file contains all the functions prototypes of the CRC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_CRC_H__ +#define __HC32F4A0_CRC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_CRC + * @{ + */ + +#if (DDL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* Bits definitions of CRC control register(CRC_CR). */ +/** + * @defgroup CRC_Global_Macros CRC Global Macros + * @{ + */ + +/** + * @defgroup CRC_Protocol_Control_Bit CRC Protocol Control Bit + * @note: - CRC16 polynomial is X16 + X12 + X5 + 1 + * - CRC32 polynomial is X32 + X26 + X23 + X22 + X16 + X12 + X11 + X10 + \ + * X8 + X7 + X5 + X4 + X2 + X + 1 + * @{ + */ +#define CRC_CRC16 (0x0UL) +#define CRC_CRC32 (CRC_CR_CR) +/** + * @} + */ + +/** + * @defgroup CRC_Flag_Bit_Mask CRC Flag Bit Mask + * @{ + */ +#define CRC_FLAG_MASK (CRC_CR_FLAG) +/** + * @} + */ + +/** + * @defgroup CRC_Bit_Width CRC Bit Width + * @{ + */ +#define CRC_BW_8 (8U) +#define CRC_BW_16 (16U) +#define CRC_BW_32 (32U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CRC_Global_Functions + * @{ + */ +uint32_t CRC_Calculate(uint32_t u32CrcProtocol, + const void *pvData, + uint32_t u32InitVal, + uint32_t u32Length, + uint8_t u8BitWidth); + +en_flag_status_t CRC_Check(uint32_t u32CrcProtocol, + uint32_t u32CheckSum, + const void *pvData, + uint32_t u32InitVal, + uint32_t u32Length, + uint8_t u8BitWidth); +/** + * @} + */ + +#endif /* DDL_CRC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_CRC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_ctc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_ctc.h new file mode 100644 index 0000000000000000000000000000000000000000..d2c4cdc788204a3cf7128e7171bf7c4d8e3740e6 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_ctc.h @@ -0,0 +1,210 @@ +/** + ******************************************************************************* + * @file hc32f4a0_ctc.h + * @brief This file contains all the functions prototypes of the Clock Trimming + * Controller(CTC) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-09-01 Hongjh First version + 2020-10-30 Hongjh Refine CTC initialization structure + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_CTC_H__ +#define __HC32F4A0_CTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_CTC + * @{ + */ + +#if (DDL_CTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Types CTC Global Types + * @{ + */ + +/** + * @brief CTC initialization structure definition + */ +typedef struct +{ + uint32_t u32RefClockFreq; /*!< Reference clock frequency + This parameter should refer user manual recommended values */ + uint32_t u32RefClockSrc; /*!< Reference clock source selection + This parameter can be a value of @ref CTC_Reference_Clock_Source */ + uint32_t u32RefClockDiv; /*!< Reference clock division + This parameter can be a value of @ref CTC_Reference_Clock_Division */ + float32_t f32ToleranceDeviation; /*!< CTC Tolerance bias. + This parameter can be a value between Min_Data=0.0 and Max_Data=1.0(100%) */ + uint32_t u32TrimValue; /*!< CTC TRMVAL value + This parameter can be a value between Min_Data=0 and Max_Data=0x3F */ +} stc_ctc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Macros CTC Global Macros + * @{ + */ + +/** + * @defgroup CTC_Reference_Clock_Source CTC Reference Clock Source + * @{ + */ +#define CTC_REF_CLK_CTCREF (0UL) /*!< Clock source: CTCREF */ +#define CTC_REF_CLK_XTAL32 (CTC_CR1_REFCKS_1) /*!< Clock source: XTAL32 */ +#define CTC_REF_CLK_XTAL (CTC_CR1_REFCKS) /*!< Clock source: XTAL */ +/** + * @} + */ + +/** + * @defgroup CTC_Tolerance_Deviation_Max CTC Tolerance Deviation Max + * @{ + */ +#define CTC_TOLERANCE_DEVIATION_MAX (1.0F) +/** + * @} + */ + +/** + * @defgroup CTC_Flag CTC Flag + * @{ + */ +#define CTC_FLAG_TRIM_OK (CTC_STR_TRIMOK) /*!< Trimming OK flag */ +#define CTC_FLAG_TRIM_OVF (CTC_STR_TRMOVF) /*!< Trimming overflow flag */ +#define CTC_FLAG_TRIM_UDF (CTC_STR_TRMUDF) /*!< Trimming underflow flag */ +#define CTC_FLAG_BUSY (CTC_STR_CTCBSY) /*!< CTC busy flag */ +#define CTC_FLAG_ALL (CTC_FLAG_TRIM_OK | \ + CTC_FLAG_TRIM_OVF | \ + CTC_FLAG_TRIM_UDF | \ + CTC_FLAG_BUSY) +/** + * @} + */ + +/** + * @defgroup CTC_Reference_Clock_Division CTC Reference Clock Division + * @{ + */ +#define CTC_REF_CLK_DIV8 (0UL) /*!< REFCLK/8 */ +#define CTC_REF_CLK_DIV32 (1UL) /*!< REFCLK/32 */ +#define CTC_REF_CLK_DIV128 (2UL) /*!< REFCLK/128 */ +#define CTC_REF_CLK_DIV256 (3UL) /*!< REFCLK/256 */ +#define CTC_REF_CLK_DIV512 (4UL) /*!< REFCLK/512 */ +#define CTC_REF_CLK_DIV1024 (5UL) /*!< REFCLK/1024 */ +#define CTC_REF_CLK_DIV2048 (6UL) /*!< REFCLK/2048 */ +#define CTC_REF_CLK_DIV4096 (7UL) /*!< REFCLK/4096 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup CTC_Global_Functions + * @{ + */ + +/** + * @brief Start CTC trimming. + * @param None + * @retval None + */ +__STATIC_INLINE void CTC_Start(void) +{ + WRITE_REG32(bM4_CTC->CR1_b.CTCEN, 1UL); +} + +/** + * @brief Stop CTC trimming. + * @param None + * @retval None + */ +__STATIC_INLINE void CTC_Stop(void) +{ + WRITE_REG32(bM4_CTC->CR1_b.CTCEN, 0UL); +} + +en_result_t CTC_Init(const stc_ctc_init_t *pstcCtcInit); +en_result_t CTC_StructInit(stc_ctc_init_t *pstcCtcInit); +en_result_t CTC_DeInit(void); +void CTC_SetRefClockDiv(uint32_t u32Div); +void CTC_SetRefClockSrc(uint32_t u32ClockSrc); +void CTC_IntCmd(en_functional_state_t enNewState); +en_flag_status_t CTC_GetStatus(uint32_t u32Flag); +void CTC_SetTrimValue(uint32_t u32TrimValue); +uint32_t CTC_GetTrimValue(void); +void CTC_SetReloadValue(uint32_t u32ReloadValue); +uint16_t CTC_GetReloadValue(void); +void CTC_SetOffsetValue(uint32_t u32OffsetValue); +uint32_t CTC_GetOffsetValue(void); + +/** + * @} + */ + +#endif /* DDL_CTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_CTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dac.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dac.h new file mode 100644 index 0000000000000000000000000000000000000000..92be0b9121818e48b65b82a1d650572f3c66990f --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dac.h @@ -0,0 +1,189 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dac.h + * @brief This file contains all the functions prototypes of the DAC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hexiao First version + 2020-07-15 Hexiao 1. Modify DAC_ChannelCmd to DAC_Start and DAC_Stop + 2. Modify DAC_DualChannelCmd to DAC_DualChannelStart + and DAC_DualChannelStop + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_DAC_H__ +#define __HC32F4A0_DAC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_DAC + * @{ + */ + +#if (DDL_DAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DAC_Global_Types DAC Global Types + * @{ + */ + +/** + * @brief Structure definition of DAC initialization. + */ +typedef struct +{ + uint16_t u16Src; /*!< Data source to be converted + This parameter can be a value of @ref DAC_DATA_SRC */ + + en_functional_state_t enOutput; /*!< Enable or disable analog output + This parameter can be a value of @ref en_functional_state_t */ + +} stc_dac_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup DAC_Global_Macros DAC Global Macros + * @{ + */ + +/** + * @defgroup DAC_CH DAC channel + * @{ + */ +#define DAC_CH_1 (0U) +#define DAC_CH_2 (1U) +/** + * @} + */ + +/** + * @defgroup DAC_DATA_SRC DAC data source + * @{ + */ +#define DAC_DATA_SRC_DATAREG (0U) +#define DAC_DATA_SRC_DCU (1U) +/** + * @} + */ + +/** + * @defgroup DAC_DATAREG_ALIGN_PATTERN DAC data register alignment pattern + * @{ + */ +#define DAC_DATA_ALIGN_L (DAC_DACR_DPSEL) +#define DAC_DATA_ALIGN_R (0U) +/** + * @} + */ + +#define DAC_DATAREG_VALUE_MAX (4096UL) + +/** + * @defgroup DAC_ADP_SELECT DAC ADCx priority select + * @{ + */ +#define DAC_ADP_SELECT_ADC1 (DAC_DAADPCR_ADPSL1) +#define DAC_ADP_SELECT_ADC2 (DAC_DAADPCR_ADPSL2) +#define DAC_ADP_SELECT_ADC3 (DAC_DAADPCR_ADPSL3) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DAC_Global_Functions + * @{ + */ + +en_result_t DAC_StructInit(stc_dac_init_t * pstcInit); +en_result_t DAC_Init(M4_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcInit); +void DAC_DeInit(M4_DAC_TypeDef *DACx); + +void DAC_SetDataSource(M4_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src); +void DAC_DataRegAlignConfig(M4_DAC_TypeDef *DACx, uint16_t u16Align); +void DAC_OutputCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState); +en_result_t DAC_AMPCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState); +void DAC_ADCPrioCmd(M4_DAC_TypeDef *DACx, en_functional_state_t enNewState); +void DAC_ADCPrioConfig(M4_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState); + +en_result_t DAC_Start(M4_DAC_TypeDef *DACx, uint16_t u16Ch); +en_result_t DAC_Stop(M4_DAC_TypeDef *DACx, uint16_t u16Ch); +void DAC_DualChannelStart(M4_DAC_TypeDef *DACx); +void DAC_DualChannelStop(M4_DAC_TypeDef *DACx); + +void DAC_SetChannel1Data(M4_DAC_TypeDef *DACx, uint16_t data); +void DAC_SetChannel2Data(M4_DAC_TypeDef *DACx, uint16_t data); +void DAC_SetDualChannelData(M4_DAC_TypeDef *DACx, uint16_t data2, uint16_t data1); +en_result_t DAC_GetChannel1ConvState(const M4_DAC_TypeDef *DACx); +en_result_t DAC_GetChannel2ConvState(const M4_DAC_TypeDef *DACx); + +/** + * @} + */ + +#endif /* DDL_DAC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_DAC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dcu.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dcu.h new file mode 100644 index 0000000000000000000000000000000000000000..45d8f54b0a6daf50e9d792c8527b95d652840b12 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dcu.h @@ -0,0 +1,347 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dcu.h + * @brief This file contains all the functions prototypes of the DCU(Data + * Computing Unit) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-23 Hongjh 1. Correct the macro define: DCU_CMP_TRIG_DATA01; + 2. Refine the macro define for interrupt, flag and mode; + 3. Modify API: from DCU_IntFuncCmd to DCU_GlobalIntCmd; + 4. Delete API: DCU_SetCmpIntMode; + 5. Modify DCU DATA read/write API. + 2020-09-07 Hongjh Refine API: DCU_SetTriggerSrc + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_DCU_H__ +#define __HC32F4A0_DCU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_DCU + * @{ + */ + +#if (DDL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Types DCU Global Types + * @{ + */ + +/** + * @brief DCU initialization structure definition + */ +typedef struct +{ + uint32_t u32IntEn; /*!< Select DCU interrupt function. + This parameter can be a value of @ref DCU_Interrupt_Configure */ + + uint32_t u32DataSize; /*!< Specifies DCU data size. + This parameter can be a value of @ref DCU_Data_Size */ + + uint32_t u32Mode; /*!< Specifies DCU operation. + This parameter can be a value of @ref DCU_Mode */ + + uint32_t u32CmpTriggerMode; /*!< Specifies DCU compare operation trigger mode size. + This parameter can be a value of @ref DCU_Compare_Trigger_Mode */ +} stc_dcu_init_t; + +/** + * @brief DCU wave output configure structure definition + */ +typedef struct +{ + uint32_t u32LowerLimit; /*!< Defines the wave lower limit of the wave amplitude. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ + + uint32_t u32UpperLimit; /*!< Defines the upper limit of the wave amplitude. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ + + uint32_t u32Step; /*!< Defines the increasing/decreasing step. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFF */ +} stc_dcu_wave_cfg_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Macros DCU Global Macros + * @{ + */ + +/** + * @defgroup DCU_Data_Size DCU Data Size + * @{ + */ +#define DCU_DATA_SIZE_8BIT (0UL) /*!< DCU data size: 8 bit */ +#define DCU_DATA_SIZE_16BIT (DCU_CTL_DATASIZE_0) /*!< DCU data size: 16 bit */ +#define DCU_DATA_SIZE_32BIT (DCU_CTL_DATASIZE_1) /*!< DCU data size: 32 bit */ +/** + * @} + */ + +/** + * @defgroup DCU_Compare_Trigger_Mode DCU Compare Trigger Mode + * @{ + */ +#define DCU_CMP_TRIG_DATA0 (0UL) /*!< DCU compare triggered by DATA0 */ +#define DCU_CMP_TRIG_DATA012 (DCU_CTL_COMP_TRG) /*!< DCU compare triggered by DATA0 or DATA1 or DATA2 */ +/** + * @} + */ + +/** + * @defgroup DCU_Mode DCU Mode + * @{ + */ +#define DCU_INVALID (0UL) /*!< DCU invalid */ +#define DCU_ADD (DCU_CTL_MODE_0) /*!< DCU add operation */ +#define DCU_SUB (DCU_CTL_MODE_1) /*!< DCU sub operation */ +#define DCU_HW_ADD (DCU_CTL_MODE_1 | \ + DCU_CTL_MODE_0) /*!< Hardware trigger DCU add */ +#define DCU_HW_SUB (DCU_CTL_MODE_2) /*!< Hardware trigger DCU sub */ +#define DCU_CMP (DCU_CTL_MODE_2 | \ + DCU_CTL_MODE_0) /*!< DCU compare */ +#define DCU_TRIANGLE_WAVE (DCU_CTL_MODE_3) /*!< DCU triangle wave output mode */ +#define DCU_SAWTOOTH_WAVE_INC (DCU_CTL_MODE_3 | \ + DCU_CTL_MODE_0) /*!< DCU increasing sawtooth wave output mode */ +#define DCU_SAWTOOTH_WAVE_DEC (DCU_CTL_MODE_3 | \ + DCU_CTL_MODE_1) /*!< DCU decreasing sawtooth wave output mode */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Configure DCU Interrupt Configure + * @{ + */ +#define DCU_INT_DISABLE (0UL) /*!< Disable DCU interrupt */ +#define DCU_INT_ENABLE (DCU_CTL_INTEN) /*!< Enable DCU interrupt */ +/** + * @} + */ + +/** + * @defgroup DCU_Flag DCU Flag + * @{ + */ +#define DCU_FLAG_OPERATION (DCU_FLAG_FLAG_OP) /*!< DCU addition overflow or subtraction underflow flag */ +#define DCU_FLAG_DATA0_LS_DATA2 (DCU_FLAG_FLAG_LS2) /*!< DCU DATA0 < DATA2 flag */ +#define DCU_FLAG_DATA0_EQ_DATA2 (DCU_FLAG_FLAG_EQ2) /*!< DCU DATA0 = DATA2 flag */ +#define DCU_FLAG_DATA0_GT_DATA2 (DCU_FLAG_FLAG_GT2) /*!< DCU DATA0 > DATA2 flag */ +#define DCU_FLAG_DATA0_LS_DATA1 (DCU_FLAG_FLAG_LS1) /*!< DCU DATA0 < DATA1 flag */ +#define DCU_FLAG_DATA0_EQ_DATA1 (DCU_FLAG_FLAG_EQ1) /*!< DCU DATA0 = DATA1 flag */ +#define DCU_FLAG_DATA0_GT_DATA1 (DCU_FLAG_FLAG_GT1) /*!< DCU DATA0 > DATA1 flag */ +#define DCU_FLAG_WAVE_SAWTOOTH_RELOAD (DCU_FLAG_FLAG_RLD) /*!< DCU sawtooth wave mode reload interrupt */ +#define DCU_FLAG_WAVE_TRIANGLE_BOTTOM (DCU_FLAG_FLAG_BTM) /*!< DCU triangle wave mode bottom interrupt */ +#define DCU_FLAG_WAVE_TRIANGLE_TOP (DCU_FLAG_FLAG_TOP) /*!< DCU triangle wave mode top interrupt */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Category DCU Interrupt Category + * @{ + */ +#define DCU_INT_OP (0UL) /*!< DCU operation result(overflow/underflow) interrupt */ +#define DCU_INT_WAVE_MD (1UL) /*!< DCU wave mode(sawtooth/triangle wave mode) interrupt */ +#define DCU_INT_CMP_WIN (2UL) /*!< DCU comparison(window) interrupt */ +#define DCU_INT_CMP_NON_WIN (3UL) /*!< DCU comparison(non-window) interrupt */ +/** + * @} + */ + +/** + * @defgroup DCU_Interrupt_Type DCU Interrupt Type + * @{ + */ +/** + * @defgroup DCU_Compare_Interrupt DCU Compare(Non-window) Interrupt + * @{ + * @note Compare interrupt selection is valid only when select DCU comparison(non-window) interrupt(DCU_INTSEL.INT_WIN=0) under DCU compare mode + */ +#define DCU_INT_CMP_DATA0_LS_DATA2 (DCU_INTEVTSEL_SEL_LS2) /*!< DCU DATA0 < DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA2 (DCU_INTEVTSEL_SEL_EQ2) /*!< DCU DATA0 = DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA2 (DCU_INTEVTSEL_SEL_GT2) /*!< DCU DATA0 > DATA2 interrupt */ +#define DCU_INT_CMP_DATA0_LS_DATA1 (DCU_INTEVTSEL_SEL_LS1) /*!< DCU DATA0 < DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_EQ_DATA1 (DCU_INTEVTSEL_SEL_EQ1) /*!< DCU DATA0 = DATA1 interrupt */ +#define DCU_INT_CMP_DATA0_GT_DATA1 (DCU_INTEVTSEL_SEL_GT1) /*!< DCU DATA0 > DATA1 interrupt */ +#define DCU_INT_CMP_NON_WIN_ALL (DCU_INT_CMP_DATA0_LS_DATA2 | \ + DCU_INT_CMP_DATA0_EQ_DATA2 | \ + DCU_INT_CMP_DATA0_GT_DATA2 | \ + DCU_INT_CMP_DATA0_LS_DATA1 | \ + DCU_INT_CMP_DATA0_EQ_DATA1 | \ + DCU_INT_CMP_DATA0_GT_DATA1) +/** + * @} + */ + +/** + * @defgroup DCU_Window_Compare_Interrupt DCU Window Compare Interrupt + * @{ + */ +#define DCU_INT_CMP_WIN_INSIDE (DCU_INTEVTSEL_SEL_WIN_0) /*!< DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt */ +#define DCU_INT_CMP_WIN_OUTSIDE (DCU_INTEVTSEL_SEL_WIN_1) /*!< DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt */ +#define DCU_INT_CMP_WIN_ALL (DCU_INT_CMP_WIN_INSIDE | \ + DCU_INT_CMP_WIN_OUTSIDE) +/** + * @} + */ + +/** + * @defgroup DCU_Wave_Mode_Interrupt DCU Wave Mode Interrupt + * @{ + */ +#define DCU_INT_WAVE_SAWTOOTH_RELOAD (DCU_INTEVTSEL_SEL_RLD) /*!< DCU sawtooth wave mode reload interrupt */ +#define DCU_INT_WAVE_TRIANGLE_BOTTOM (DCU_INTEVTSEL_SEL_BTM) /*!< DCU triangle wave mode bottom interrupt */ +#define DCU_INT_WAVE_TRIANGLE_TOP (DCU_INTEVTSEL_SEL_TOP) /*!< DCU triangle wave mode top interrupt */ +#define DCU_INT_WAVE_MD_ALL (DCU_INT_WAVE_TRIANGLE_TOP |\ + DCU_INT_WAVE_TRIANGLE_BOTTOM |\ + DCU_INT_WAVE_SAWTOOTH_RELOAD) +/** + * @} + */ + +/** + * @defgroup DCU_Operation_Interrupt DCU Operation Interrupt + * @{ + */ +#define DCU_INT_OP_UDF_OVF (DCU_INTEVTSEL_SEL_OP) /*!< DCU addition overflow or subtraction underflow interrupt */ +/** + * @} + */ +/** + * @} + */ + +/** + * @defgroup DCU_Data_Register_Index DCU Data Register Index + * @{ + */ +#define DCU_DATA0_IDX (0UL) /*!< DCU DATA0 */ +#define DCU_DATA1_IDX (1UL) /*!< DCU DATA1 */ +#define DCU_DATA2_IDX (2UL) /*!< DCU DATA2 */ +/** + * @} + */ + +/** + * @defgroup DCU_Common_Trigger_Source_Configure DCU common Trigger Source Configure + * @{ + */ +#define DCU_COM_TRIG1 (AOS_DCU_1_TRGSEL_COMTRG_EN_0) +#define DCU_COM_TRIG2 (AOS_DCU_1_TRGSEL_COMTRG_EN_1) +#define DCU_COM_TRIG_MASK (AOS_DCU_1_TRGSEL_COMTRG_EN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DCU_Global_Functions + * @{ + */ + +/* Initialization and configuration DCU functions */ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInit); +en_result_t DCU_StructInit(stc_dcu_init_t *pstcInit); +void DCU_DeInit(M4_DCU_TypeDef *DCUx); + +en_result_t DCU_WaveCfg(M4_DCU_TypeDef *DCUx, const stc_dcu_wave_cfg_t *pstcCfg); +void DCU_SetMode(M4_DCU_TypeDef *DCUx, uint32_t u32Mode); +uint32_t DCU_GetMode(const M4_DCU_TypeDef *DCUx); +void DCU_SetDataSize(M4_DCU_TypeDef *DCUx, uint32_t u32DataSize); +uint32_t DCU_GetDataSize(const M4_DCU_TypeDef *DCUx); +en_flag_status_t DCU_GetStatus(const M4_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_ClearStatus(M4_DCU_TypeDef *DCUx, uint32_t u32Flag); +void DCU_IntCmd(M4_DCU_TypeDef *DCUx, + uint32_t u32IntCategory, + uint32_t u32IntType, + en_functional_state_t enNewState); +void DCU_GlobalIntCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enNewState); +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + uint32_t u32ComTrig, + en_functional_state_t enNewState); +void DCU_SetTriggerSrc(const M4_DCU_TypeDef *DCUx, en_event_src_t enEventSrc); + +uint8_t DCU_ReadData8(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData8(M4_DCU_TypeDef *DCUx, + uint32_t u32DataIndex, + uint8_t u8Data); +uint16_t DCU_ReadData16(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData16(M4_DCU_TypeDef *DCUx, + uint32_t u32DataIndex, + uint16_t u16Data); +uint32_t DCU_ReadData32(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex); +void DCU_WriteData32(M4_DCU_TypeDef *DCUx, + uint32_t u32DataIndex, + uint32_t u32Data); + +/** + * @} + */ + +#endif /* DDL_DCU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_DCU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dma.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..72a19e274e728b1fe2fea929fdb226845cd706e3 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dma.h @@ -0,0 +1,553 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dma.h + * @brief This file contains all the functions prototypes of the DMA driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_DMA_H__ +#define __HC32F4A0_DMA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_DMA + * @{ + */ + +#if (DDL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Types DMA Global Types + * @{ + */ + +/** + * @brief DMA basic configuration + */ +typedef struct +{ + uint32_t u32IntEn; /*!< Specifies the DMA interrupt function. + This parameter can be a value of @ref DMA_Int_Config */ + + uint32_t u32SrcAddr; /*!< Specifies the DMA source address. */ + + uint32_t u32DestAddr; /*!< Specifies the DMA destination address. */ + + uint32_t u32DataWidth; /*!< Specifies the DMA transfer data width. + This parameter can be a value of @ref DMA_DataWidth_Sel */ + + uint32_t u32BlockSize; /*!< Specifies the DMA block size. */ + + uint32_t u32TransCnt; /*!< Specifies the DMA transfer count. */ + + uint32_t u32SrcInc; /*!< Specifies the source address increment mode. + This parameter can be a value of @ref DMA_SrcAddr_Incremented_Mode */ + + uint32_t u32DestInc; /*!< Specifies the destination address increment mode. + This parameter can be a value of @ref DMA_DesAddr_Incremented_Mode */ + +} stc_dma_init_t; + +/** + * @brief DMA repeat mode configuration + */ +typedef struct +{ + uint32_t u32SrcRptEn; /*!< Specifies the DMA source repeat function. + This parameter can be a value of @ref DMA_Repeat_Config */ + + uint32_t u32SrcRptSize; /*!< Specifies the DMA source repeat size. */ + + uint32_t u32DestRptEn; /*!< Specifies the DMA destination repeat function. + This parameter can be a value of @ref DMA_Repeat_Config */ + + uint32_t u32DestRptSize; /*!< Specifies the DMA destination repeat size. */ + +} stc_dma_rpt_init_t; + +/** + * @brief DMA non-sequence mode configuration + */ +typedef struct +{ + uint32_t u32SrcNonSeqEn; /*!< Specifies the DMA source non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + + uint32_t u32SrcNonSeqCnt; /*!< Specifies the DMA source non-sequence function count. */ + + uint32_t u32SrcNonSeqOfs; /*!< Specifies the DMA source non-sequence function offset. */ + + uint32_t u32DestNonSeqEn; /*!< Specifies the DMA destination non-sequence function. + This parameter can be a value of @ref DMA_NonSeq_Config */ + + uint32_t u32DestNonSeqCnt; /*!< Specifies the DMA destination non-sequence function count. */ + + uint32_t u32DestNonSeqOfs; /*!< Specifies the DMA destination non-sequence function offset. */ + +} stc_dma_nonseq_init_t; + +/** + * @brief DMA Link List Pointer (LLP) mode configuration + */ +typedef struct +{ + uint32_t u32LlpEn; /*!< Specifies the DMA LLP function. + This parameter can be a value of @ref DMA_Llp_En */ + + uint32_t u32LlpRun; /*!< Specifies the DMA LLP auto or wait REQ. + This parameter can be a value of @ref DMA_Llp_Mode */ + + uint32_t u32LlpAddr; /*!< Specifies the DMA list pointer address for LLP function. */ + +} stc_dma_llp_init_t; + +/** + * @brief DMA re-config function configuration + */ +typedef struct +{ + uint32_t u32CntMode; /*!< Specifies the DMA reconfig function count mode. + This parameter can be a value of @ref DMA_ReConfig_Cnt_Sel */ + + uint32_t u32DestAddrMode; /*!< Specifies the DMA reconfig function destination address mode. + This parameter can be a value of @ref DMA_ReConfig_DestAddr_Sel */ + + uint32_t u32SrcAddrMode; /*!< Specifies the DMA reconfig function source address mode. + This parameter can be a value of @ref DMA_ReConfig_SrcAddr_Sel */ + +} stc_dma_reconfig_init_t; + +/** + * @brief Dma LLP(linked list pointer) descriptor structure definition + */ +typedef struct +{ + uint32_t SARx; /*!< LLP source address */ + uint32_t DARx; /*!< LLP destination address */ + uint32_t DTCTLx; /*!< LLP transfer count and block size */ + uint32_t RPTx; /*!< LLP source & destination repeat size */ + uint32_t SNSEQCTLx; /*!< LLP source non-seq count and offset */ + uint32_t DNSEQCTLx; /*!< LLP destination non-seq count and offset */ + uint32_t LLPx; /*!< LLP next list pointer */ + uint32_t CHCTLx; /*!< LLP channel control */ +} stc_dma_llp_descriptor_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Macros DMA Global Macros + * @{ + */ + +/** + * @defgroup DMA_Channel_selection DMA Channel Position selection + * @{ + */ +#define DMA_CH0 (0x00U) /*!< DMA Channel 0 */ +#define DMA_CH1 (0x01U) /*!< DMA Channel 1 */ +#define DMA_CH2 (0x02U) /*!< DMA Channel 2 */ +#define DMA_CH3 (0x03U) /*!< DMA Channel 3 */ +#define DMA_CH4 (0x04U) /*!< DMA Channel 4 */ +#define DMA_CH5 (0x05U) /*!< DMA Channel 5 */ +#define DMA_CH6 (0x06U) /*!< DMA Channel 6 */ +#define DMA_CH7 (0x07U) /*!< DMA Channel 7 */ +/** + * @} + */ + +/** + * @defgroup DMA_Mx_Channel_selection DMA Multiplex Channel selection + * @{ + */ +#define DMA_MX_CH0 (0x01UL) /*!< DMA Channel 0 position */ +#define DMA_MX_CH1 (0x02UL) /*!< DMA Channel 1 position */ +#define DMA_MX_CH2 (0x04UL) /*!< DMA Channel 2 position */ +#define DMA_MX_CH3 (0x08UL) /*!< DMA Channel 3 position */ +#define DMA_MX_CH4 (0x10UL) /*!< DMA Channel 4 position */ +#define DMA_MX_CH5 (0x20UL) /*!< DMA Channel 5 position */ +#define DMA_MX_CH6 (0x40UL) /*!< DMA Channel 6 position */ +#define DMA_MX_CH7 (0x80UL) /*!< DMA Channel 7 position */ +#define DMA_MX_CH_ALL (0xFFUL) /*!< DMA Channel mask position */ +/** + * @} + */ + +/** + * @defgroup DMA_ReqErrIrq_Sel DMA request error interrupt selection + * @{ + */ +#define DMA_REQ_ERR_CH0 (DMA_INTSTAT0_REQERR_0) /*!< DMA request error interrupt CH.0 */ +#define DMA_REQ_ERR_CH1 (DMA_INTSTAT0_REQERR_1) /*!< DMA request error interrupt CH.1 */ +#define DMA_REQ_ERR_CH2 (DMA_INTSTAT0_REQERR_2) /*!< DMA request error interrupt CH.2 */ +#define DMA_REQ_ERR_CH3 (DMA_INTSTAT0_REQERR_3) /*!< DMA request error interrupt CH.3 */ +#define DMA_REQ_ERR_CH4 (DMA_INTSTAT0_REQERR_4) /*!< DMA request error interrupt CH.4 */ +#define DMA_REQ_ERR_CH5 (DMA_INTSTAT0_REQERR_5) /*!< DMA request error interrupt CH.5 */ +#define DMA_REQ_ERR_CH6 (DMA_INTSTAT0_REQERR_6) /*!< DMA request error interrupt CH.6 */ +#define DMA_REQ_ERR_CH7 (DMA_INTSTAT0_REQERR_7) /*!< DMA request error interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_TransErrIrq_Sel DMA transfer error interrupt selection + * @{ + */ +#define DMA_TRANS_ERR_CH0 (DMA_INTSTAT0_TRNERR_0) /*!< DMA transfer error interrupt CH.0 */ +#define DMA_TRANS_ERR_CH1 (DMA_INTSTAT0_TRNERR_1) /*!< DMA transfer error interrupt CH.1 */ +#define DMA_TRANS_ERR_CH2 (DMA_INTSTAT0_TRNERR_2) /*!< DMA transfer error interrupt CH.2 */ +#define DMA_TRANS_ERR_CH3 (DMA_INTSTAT0_TRNERR_3) /*!< DMA transfer error interrupt CH.3 */ +#define DMA_TRANS_ERR_CH4 (DMA_INTSTAT0_TRNERR_4) /*!< DMA transfer error interrupt CH.4 */ +#define DMA_TRANS_ERR_CH5 (DMA_INTSTAT0_TRNERR_5) /*!< DMA transfer error interrupt CH.5 */ +#define DMA_TRANS_ERR_CH6 (DMA_INTSTAT0_TRNERR_6) /*!< DMA transfer error interrupt CH.6 */ +#define DMA_TRANS_ERR_CH7 (DMA_INTSTAT0_TRNERR_7) /*!< DMA transfer error interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_BtcIrq_Sel DMA block transfer completed interrupt selection + * @{ + */ +#define DMA_BTC_INT_CH0 (DMA_INTSTAT1_BTC_0) /*!< DMA block transfer completed interrupt CH.0 */ +#define DMA_BTC_INT_CH1 (DMA_INTSTAT1_BTC_1) /*!< DMA block transfer completed interrupt CH.1 */ +#define DMA_BTC_INT_CH2 (DMA_INTSTAT1_BTC_2) /*!< DMA block transfer completed interrupt CH.2 */ +#define DMA_BTC_INT_CH3 (DMA_INTSTAT1_BTC_3) /*!< DMA block transfer completed interrupt CH.3 */ +#define DMA_BTC_INT_CH4 (DMA_INTSTAT1_BTC_4) /*!< DMA block transfer completed interrupt CH.4 */ +#define DMA_BTC_INT_CH5 (DMA_INTSTAT1_BTC_5) /*!< DMA block transfer completed interrupt CH.5 */ +#define DMA_BTC_INT_CH6 (DMA_INTSTAT1_BTC_6) /*!< DMA block transfer completed interrupt CH.6 */ +#define DMA_BTC_INT_CH7 (DMA_INTSTAT1_BTC_7) /*!< DMA block transfer completed interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_TcIrq_Sel DMA transfer completed interrupt selection + * @{ + */ +#define DMA_TC_INT_CH0 (DMA_INTSTAT1_TC_0) /*!< DMA transfer completed interrupt CH.0 */ +#define DMA_TC_INT_CH1 (DMA_INTSTAT1_TC_1) /*!< DMA transfer completed interrupt CH.1 */ +#define DMA_TC_INT_CH2 (DMA_INTSTAT1_TC_2) /*!< DMA transfer completed interrupt CH.2 */ +#define DMA_TC_INT_CH3 (DMA_INTSTAT1_TC_3) /*!< DMA transfer completed interrupt CH.3 */ +#define DMA_TC_INT_CH4 (DMA_INTSTAT1_TC_4) /*!< DMA transfer completed interrupt CH.4 */ +#define DMA_TC_INT_CH5 (DMA_INTSTAT1_TC_5) /*!< DMA transfer completed interrupt CH.5 */ +#define DMA_TC_INT_CH6 (DMA_INTSTAT1_TC_6) /*!< DMA transfer completed interrupt CH.6 */ +#define DMA_TC_INT_CH7 (DMA_INTSTAT1_TC_7) /*!< DMA transfer completed interrupt CH.7 */ +/** + * @} + */ + +/** + * @defgroup DMA_IntMsk_Sel DMA interrupt mask selection + * @{ + */ +#define DMA_ERR_INT_MASK (0x00FF00FFUL) /*!< DMA error interrupt mask */ +#define DMA_TRANS_INT_MASK (0x00FF00FFUL) /*!< DMA transfer interrupt mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Req_Status_Sel DMA request status + * @{ + */ +#define DMA_REQ_CH0 (DMA_REQSTAT_CHREQ_0) /*!< DMA request from CH.0 */ +#define DMA_REQ_CH1 (DMA_REQSTAT_CHREQ_1) /*!< DMA request from CH.1 */ +#define DMA_REQ_CH2 (DMA_REQSTAT_CHREQ_2) /*!< DMA request from CH.2 */ +#define DMA_REQ_CH3 (DMA_REQSTAT_CHREQ_3) /*!< DMA request from CH.3 */ +#define DMA_REQ_CH4 (DMA_REQSTAT_CHREQ_4) /*!< DMA request from CH.4 */ +#define DMA_REQ_CH5 (DMA_REQSTAT_CHREQ_5) /*!< DMA request from CH.5 */ +#define DMA_REQ_CH6 (DMA_REQSTAT_CHREQ_6) /*!< DMA request from CH.6 */ +#define DMA_REQ_CH7 (DMA_REQSTAT_CHREQ_7) /*!< DMA request from CH.7 */ +#define DMA_REQ_RECONFIG (DMA_REQSTAT_RCFGREQ) /*!< DMA request from reconfig */ +#define DMA_REQ_STAT_MASK (0x000080FFUL) /*!< DMA request mask */ +/** + * @} + */ + +/** + * @defgroup DMA_Trans_Status_Sel DMA transfer status + * @{ + */ +#define DMA_TRANS_CH0 (DMA_CHSTAT_CHACT_0) /*!< DMA transfer status of CH.0 */ +#define DMA_TRANS_CH1 (DMA_CHSTAT_CHACT_1) /*!< DMA transfer status of CH.1 */ +#define DMA_TRANS_CH2 (DMA_CHSTAT_CHACT_2) /*!< DMA transfer status of CH.2 */ +#define DMA_TRANS_CH3 (DMA_CHSTAT_CHACT_3) /*!< DMA transfer status of CH.3 */ +#define DMA_TRANS_CH4 (DMA_CHSTAT_CHACT_4) /*!< DMA transfer status of CH.4 */ +#define DMA_TRANS_CH5 (DMA_CHSTAT_CHACT_5) /*!< DMA transfer status of CH.5 */ +#define DMA_TRANS_CH6 (DMA_CHSTAT_CHACT_6) /*!< DMA transfer status of CH.6 */ +#define DMA_TRANS_CH7 (DMA_CHSTAT_CHACT_7) /*!< DMA transfer status of CH.7 */ +#define DMA_TRANS_RECONFIG (DMA_CHSTAT_RCFGACT) /*!< DMA reconfig status */ +#define DMA_TRANS_DMA (DMA_CHSTAT_DMAACT) /*!< DMA transfer status of the DMA */ +#define DMA_TRANS_STAT_MASK (0x0000FF03UL) /*!< DMA request mask */ +/** + * @} + */ + +/** + * @defgroup DMA_DataWidth_Sel DMA transfer data width + * @{ + */ +#define DMA_DATAWIDTH_8BIT (0x00000000UL) /*!< DMA transfer data width 8bit */ +#define DMA_DATAWIDTH_16BIT (DMA_CHCTL_HSIZE_0) /*!< DMA transfer data width 16bit */ +#define DMA_DATAWIDTH_32BIT (DMA_CHCTL_HSIZE_1) /*!< DMA transfer data width 32bit */ +/** + * @} + */ + +/** + * @defgroup DMA_Llp_En DMA LLP(linked list pinter) enable or disable + * @{ + */ +#define DMA_LLP_ENABLE (DMA_CHCTL_LLPEN) /*!< DMA LLP(linked list pinter) enable */ +#define DMA_LLP_DISABLE (0x00000000UL) /*!< DMA LLP(linked list pinter) disable */ +/** + * @} + */ + +/** + * @defgroup DMA_Llp_Mode DMA linked list pinter mode while transferring complete + * @{ + */ +#define DMA_LLP_RUN (DMA_CHCTL_LLPRUN) /*!< DMA Llp run right now while transfering complete */ +#define DMA_LLP_WAIT (0x00000000UL) /*!< DMA Llp wait next request while transfering complete */ +/** + * @} + */ + +/** + * @defgroup DMA_SrcAddr_Incremented_Mode DMA source address increment mode + * @{ + */ +#define DMA_SRC_ADDR_FIX (0x00000000UL) /*!< DMA source address fix */ +#define DMA_SRC_ADDR_INC (DMA_CHCTL_SINC_0) /*!< DMA source address increment */ +#define DMA_SRC_ADDR_DEC (DMA_CHCTL_SINC_1) /*!< DMA source address decrement */ +/** + * @} + */ + +/** + * @defgroup DMA_DesAddr_Incremented_Mode DMA destination address increment mode + * @{ + */ +#define DMA_DEST_ADDR_FIX (0x00000000UL) /*!< DMA destination address fix */ +#define DMA_DEST_ADDR_INC (DMA_CHCTL_DINC_0) /*!< DMA destination address increment */ +#define DMA_DEST_ADDR_DEC (DMA_CHCTL_DINC_1) /*!< DMA destination address decrement */ +/** + * @} + */ + +/** + * @defgroup DMA_Int_Config DMA interrupt function config + * @{ + */ +#define DMA_INT_ENABLE (DMA_CHCTL_IE) /*!< DMA interrupt enable */ +#define DMA_INT_DISABLE (0x00000000UL) /*!< DMA interrupt disable */ +/** + * @} + */ + +/** + * @defgroup DMA_Repeat_Config DMA repeat mode function config + * @{ + */ +#define DMA_SRC_RPT_ENABLE (DMA_CHCTL_SRTPEN) /*!< DMA source repeat enable */ +#define DMA_SRC_RPT_DISABLE (0x00000000UL) /*!< DMA source repeat disable */ +#define DMA_DEST_RPT_ENABLE (DMA_CHCTL_DRPTEN) /*!< DMA destination repeat enable */ +#define DMA_DEST_RPT_DISABLE (0x00000000UL) /*!< DMA destination repeat disable */ +/** + * @} + */ + +/** + * @defgroup DMA_NonSeq_Config DMA non-sequence mode function config + * @{ + */ +#define DMA_SRC_NS_ENABLE (DMA_CHCTL_SNSEQEN) /*!< DMA source non-sequence enable */ +#define DMA_SRC_NS_DISABLE (0x00000000UL) /*!< DMA source non-sequence disable */ +#define DMA_DEST_NS_ENABLE (DMA_CHCTL_DNSEQEN) /*!< DMA destination non-sequence enable */ +#define DMA_DEST_NS_DISABLE (0x00000000UL) /*!< DMA destination non-sequence disable */ +/** + * @} + */ + +/** + * @defgroup DMA_ReConfig_Cnt_Sel DMA reconfig count mode selection + * @{ + */ +#define DMA_RC_CNT_FIX (0x00UL) /*!< Keep the original counting method */ +#define DMA_RC_CNT_SRC (DMA_RCFGCTL_CNTMD_0) /*!< Use source address counting method */ +#define DMA_RC_CNT_DEST (DMA_RCFGCTL_CNTMD_1) /*!< Use destination address counting method */ +/** + * @} + */ + +/** + * @defgroup DMA_ReConfig_DestAddr_Sel DMA reconfig destination address mode selection + * @{ + */ +#define DMA_RC_DA_FIX (0x00000000UL) /*!< Destination address fixed */ +#define DMA_RC_DA_NS (DMA_RCFGCTL_DARMD_0) /*!< Destination address non-sequence */ +#define DMA_RC_DA_RPT (DMA_RCFGCTL_DARMD_1) /*!< Destination address repeat */ +/** + * @} + */ + +/** + * @defgroup DMA_ReConfig_SrcAddr_Sel DMA reconfig source address mode selection + * @{ + */ +#define DMA_RC_SA_FIX (0x00000000UL) /*!< Source address fixed */ +#define DMA_RC_SA_NS (DMA_RCFGCTL_SARMD_0) /*!< Source address non-sequence */ +#define DMA_RC_SA_RPT (DMA_RCFGCTL_SARMD_1) /*!< Source address repeat */ +/** + * @} + */ + +/** + * @defgroup DMA_Common_Trigger_Source_Config DMA common Trigger Source Config + * @{ + */ +#define DMA_COM_TRIG1 (AOS_DMA_1_TRGSEL_COMTRG_EN_0) +#define DMA_COM_TRIG2 (AOS_DMA_1_TRGSEL_COMTRG_EN_1) +#define DMA_COM_TRIG_MASK (AOS_DMA_1_TRGSEL_COMTRG_EN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DMA_Global_Functions + * @{ + */ +void DMA_Cmd(M4_DMA_TypeDef *DMAx, en_functional_state_t enNewState); + +void DMA_ErrIntCmd(M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetErrIntStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt); +void DMA_ClearErrIntStatus(M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt); + +void DMA_TransIntCmd(M4_DMA_TypeDef *DMAx, uint32_t u32TransInt, en_functional_state_t enNewState); +en_flag_status_t DMA_GetTransIntStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32TransInt); +void DMA_ClearTransIntStatus(M4_DMA_TypeDef *DMAx, uint32_t u32TransInt); + +void DMA_MxChannelCmd(M4_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState); +void DMA_ChannelCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc); +void DMA_RCComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState); +void DMA_SetTriggerSrc(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_event_src_t enSrc); +void DMA_ComTriggerCmd(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32ComTrig, en_functional_state_t enNewState); + +en_flag_status_t DMA_GetReqStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32Status); +en_flag_status_t DMA_GetTransStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32Status); + +void DMA_SetSrcAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +void DMA_SetDestAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr); +void DMA_SetTransCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Cnt); +void DMA_SetBlockSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); + +void DMA_SetSrcRptSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +void DMA_SetDestRptSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size); +void DMA_SetNonSeqSrcCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Cnt); +void DMA_SetNonSeqDestCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Cnt); +void DMA_SetNonSeqSrcOffset(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Ofs); +void DMA_SetNonSeqDestOffset(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Ofs); + +void DMA_SetLlpAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32LlpAddr); + +en_result_t DMA_Init(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit); +en_result_t DMA_RepeatInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rpt_init_t *pstcDmaRptInit); +en_result_t DMA_NonSeqInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit); +en_result_t DMA_LlpInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit); +en_result_t DMA_ReConfigInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit); + +en_result_t DMA_StructInit(stc_dma_init_t *pstcDmaInit); +en_result_t DMA_RepeatStructInit(stc_dma_rpt_init_t *pstcDmaRptInit); +en_result_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit); +en_result_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit); +en_result_t DMA_ReConfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit); + + +void DMA_LlpCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); +void DMA_ReConfigCmd(M4_DMA_TypeDef *DMAx, en_functional_state_t enNewState); +void DMA_ReConfigLlpCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState); + +uint32_t DMA_GetSrcAddr(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestAddr(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetTransCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetBlockSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetSrcRptSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetDestRptSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqSrcOffset(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +uint32_t DMA_GetNonSeqDestOffset(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch); +/** + * @} + */ + +#endif /* DDL_DMA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_DMA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dmc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dmc.h new file mode 100644 index 0000000000000000000000000000000000000000..46dbf8b38c1ce92321fd789aac7ceb1654fdca15 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dmc.h @@ -0,0 +1,439 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dmc.h + * @brief This file contains all the functions prototypes of the EXMC DMC + * (External Memory Controller: Dynamic Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-14 Hongjh Merge API from EXMC_DMC_Enable/Disable to EXMC_DMC_Cmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_DMC_H__ +#define __HC32F4A0_DMC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_EXMC_DMC + * @{ + */ + +#if (DDL_DMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Global_Types Dynamic Memory Controller Global Types + * @{ + */ + +/** + * @brief EXMC DMC CS Configuration Structure definition + */ +typedef struct +{ + uint32_t u32AddrMask; /*!< Defines the address mask. + This parameter can be a value of @ref EXMC_DMC_Mask_Address. */ + + uint32_t u32AddrMatch; /*!< Defines the address match. + This parameter can be a value of @ref EXMC_DMC_Match_Address. */ + + uint32_t u32AddrDecodeMode; /*!< Defines the address decode mode. + This parameter can be a value of @ref EXMC_DMC_CS_Decode_Mode. */ +} stc_exmc_dmc_cs_cfg_t; + +/** + * @brief EXMC DMC Chip Configuration Structure definition + */ +typedef struct +{ + + uint32_t u32ColumnBitsNumber; /*!< Defines the number of bits of column address. + This parameter can be a value of @ref EXMC_DMC_Column_Bits_Number. */ + + uint32_t u32RowBitsNumber; /*!< Defines the number of bits of row address. + This parameter can be a value of @ref EXMC_DMC_Row_Bits_Number. */ + + uint32_t u32AutoPrechargePin; /*!< Defines the auto-precharge pin. + This parameter can be a value of @ref EXMC_DMC_Auto_Precharge_Pin. */ + + uint32_t u32MemClkSel; /*!< Defines the memory clock selection. + This parameter can be a value of @ref EXMC_DMC_MemClock_Selection */ + + uint32_t u32CkeOutputSel; /*!< Defines the CKE output selection. + This parameter can be a value of @ref EXMC_DMC_CKE_Output_Selection */ + + uint32_t u32CkeDisablePeriod; /*!< Defines the CKE disable period. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x3F */ + + uint32_t u32MemBurst; /*!< Defines the number of data accesses. + This parameter can be a value of @ref EXMC_DMC_Memory_Burst. */ + + uint32_t u32AutoRefreshChips; /*!< Defines the refresh command generation for the number of memory chips. + This parameter can be a value of @ref EXMC_DMC_Auto_Refresh_Chips. */ +}stc_exmc_dmc_chip_cfg_t; + +/** + * @brief EXMC DMC Timing Configuration Structure definition + */ +typedef struct +{ + uint32_t u32CASL; /*!< Defines the CAS latency in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32DQSS; /*!< Defines the DQSS in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 3 */ + uint32_t u32MRD; /*!< Defines the the mode register command time in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x7F */ + uint32_t u32RAS; /*!< Defines the RAS in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint32_t u32RC; /*!< Defines the RC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint32_t u32RCD; /*!< Defines the RCD in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32RFC; /*!< Defines the RFC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x1F */ + uint32_t u32RP; /*!< Defines the RP in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32RRD; /*!< Defines the RRD in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + uint32_t u32WR; /*!< Defines the WR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32WTR; /*!< Defines the WTR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + uint32_t u32XP; /*!< Defines the XP in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32XSR; /*!< Defines the XSR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + uint32_t u32ESR; /*!< Defines the ESR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_dmc_timing_cfg_t; + +/** + * @brief EXMC DMC Initialization Structure definition + */ +typedef struct +{ + uint32_t u32DmcMemWidth; /*!< DMC memory width. + This parameter can be a value of @ref EXMC_DMC_Memory_Width. */ + + uint32_t u32RefreshPeriod; /*!< DMC memory refresh period. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFF */ + + stc_exmc_dmc_chip_cfg_t stcChipCfg; /*!< DMC memory chip configure. + This structure details refer @ref stc_exmc_dmc_chip_cfg_t. */ + + stc_exmc_dmc_timing_cfg_t stcTimingCfg; /*!< DMC memory timing configure. + This structure details refer @ref stc_exmc_dmc_timing_cfg_t. */ +} stc_exmc_dmc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Global_Macros Dynamic Memory Controller Global Macros + * @{ + */ + +/** + * @defgroup EXMC_DMC_Memory_Width EXMC DMC Memory Width + * @{ + */ +#define EXMC_DMC_MEMORY_WIDTH_16BIT (0UL) +#define EXMC_DMC_MEMORY_WIDTH_32BIT (DMC_BACR_DMCMW_0) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Chip EXMC DMC Chip + * @{ + */ +#define EXMC_DMC_CHIP_0 (0UL) /*!< Chip 0 */ +#define EXMC_DMC_CHIP_1 (1UL) /*!< Chip 1 */ +#define EXMC_DMC_CHIP_2 (2UL) /*!< Chip 2 */ +#define EXMC_DMC_CHIP_3 (3UL) /*!< Chip 3 */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Bank EXMC DMC Bank + * @{ + */ +#define EXMC_DMC_BANK_0 (0UL) /*!< Bank 0 */ +#define EXMC_DMC_BANK_1 (1UL) /*!< Bank 1 */ +#define EXMC_DMC_BANK_2 (2UL) /*!< Bank 2 */ +#define EXMC_DMC_BANK_3 (3UL) /*!< Bank 3 */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Current_Status EXMC DMC Current Status + * @{ + */ +#define EXMC_DMC_CURR_STATUS_CONFIGURE (0UL) +#define EXMC_DMC_CURR_STATUS_READY (DMC_STSR_STATUS_0) +#define EXMC_DMC_CURR_STATUS_PAUSED (DMC_STSR_STATUS_1) +#define EXMC_DMC_CURR_STATUS_LOWPOWER (DMC_STSR_STATUS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Control_State EXMC DMC Control State + * @{ + */ +#define EXMC_DMC_CTL_STATE_GO (0UL) +#define EXMC_DMC_CTL_STATE_SLEEP (1UL) +#define EXMC_DMC_CTL_STATE_WAKEUP (2UL) +#define EXMC_DMC_CTL_STATE_PAUSE (3UL) +#define EXMC_DMC_CTL_STATE_CONFIGURE (4UL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Command EXMC DMC Command + * @{ + */ +#define EXMC_DMC_CMD_PRECHARGEALL (0UL) /*!< Precharge all */ +#define EXMC_DMC_CMD_AUTOREFRESH (DMC_CMDR_CMD_0) /*!< Auto refresh */ +#define EXMC_DMC_CMD_MDREGCONFIG (DMC_CMDR_CMD_1) /*!< Set memory device mode register */ +#define EXMC_DMC_CMD_NOP (DMC_CMDR_CMD) /*!< NOP */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Refresh_Period_Max EXMC DMC Refresh Period Max + * @{ + */ +#define EXMC_DMC_REFRESH_PERIOD_MAX (0x00007FFFUL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_CS_Decode_Mode EXMC DMC CS Decode Mode + * @{ + */ +#define EXMC_DMC_CS_DECODE_ROWBANKCOL (0UL) /*!< Row -> Bank -> Column */ +#define EXMC_DMC_CS_DECODE_BANKROWCOL (DMC_CSCR_BRC) /*!< Bank -> Row -> Column */ +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Column_Bits_Number EXMC DMC Column Bits Number + * @{ + */ +#define EXMC_DMC_COLUMN_BITS_NUM_8 (0UL) +#define EXMC_DMC_COLUMN_BITS_NUM_9 (DMC_CPCR_COLBS_0) +#define EXMC_DMC_COLUMN_BITS_NUM_10 (DMC_CPCR_COLBS_1) +#define EXMC_DMC_COLUMN_BITS_NUM_11 (DMC_CPCR_COLBS_1 | \ + DMC_CPCR_COLBS_0) +#define EXMC_DMC_COLUMN_BITS_NUM_12 (DMC_CPCR_COLBS_2) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Row_Bits_Number EXMC DMC Row Bits Number + * @{ + */ +#define EXMC_DMC_ROW_BITS_NUM_11 (0UL) +#define EXMC_DMC_ROW_BITS_NUM_12 (DMC_CPCR_ROWBS_0) +#define EXMC_DMC_ROW_BITS_NUM_13 (DMC_CPCR_ROWBS_1) +#define EXMC_DMC_ROW_BITS_NUM_14 (DMC_CPCR_ROWBS_1 | \ + DMC_CPCR_ROWBS_0) +#define EXMC_DMC_ROW_BITS_NUM_15 (DMC_CPCR_ROWBS_2) +#define EXMC_DMC_ROW_BITS_NUM_16 (DMC_CPCR_ROWBS_2 | \ + DMC_CPCR_ROWBS_0) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Auto_Precharge_Pin EXMC DMC Auto Pre-charge Pin + * @{ + */ +#define EXMC_DMC_AUTO_PRECHARGE_A8 (DMC_CPCR_APBS) +#define EXMC_DMC_AUTO_PRECHARGE_A10 (0UL) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_CKE_Output_Selection EXMC DMC CKE Output Selection + * @{ + */ +#define EXMC_DMC_CKE_OUTPUT_ENABLE (0UL) +#define EXMC_DMC_CKE_OUTPUT_DISABLE (DMC_CPCR_CKEDIS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_MemClock_Selection EXMC DMC MemClock Selection + * @{ + */ +#define EXMC_DMC_MEMCLK_NORMAL_OUTPUT (0UL) +#define EXMC_DMC_MEMCLK_NOP_STOP_OUTPUT (DMC_CPCR_CKSTOP) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Memory_Burst EXMC DMC Memory Burst + * @{ + */ +#define EXMC_DMC_MEM_BURST_1 (0UL) +#define EXMC_DMC_MEM_BURST_2 (DMC_CPCR_BURST_0) +#define EXMC_DMC_MEM_BURST_4 (DMC_CPCR_BURST_1) +#define EXMC_DMC_MEM_BURST_8 (DMC_CPCR_BURST_1 | \ + DMC_CPCR_BURST_0) +#define EXMC_DMC_MEM_BURST_16 (DMC_CPCR_BURST_2) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Auto_Refresh_Chips EXMC DMC Auto Refresh + * @{ + */ +#define EXMC_DMC_AUTO_REFRESH_CHIP_0 (0UL) +#define EXMC_DMC_AUTO_REFRESH_CHIPS_01 (DMC_CPCR_ACTCP_0) +#define EXMC_DMC_AUTO_REFRESH_CHIPS_012 (DMC_CPCR_ACTCP_1) +#define EXMC_DMC_AUTO_REFRESH_CHIPS_0123 (DMC_CPCR_ACTCP) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Match_Address EXMC DMC Match Address + * @{ + */ +#define EXMC_DMC_ADDR_MATCH_0X80000000 (0x80UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X81000000 (0x81UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X82000000 (0x82UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X83000000 (0x83UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X84000000 (0x84UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X85000000 (0x85UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X86000000 (0x86UL << DMC_CSCR_ADDMAT_POS) +#define EXMC_DMC_ADDR_MATCH_0X87000000 (0x87UL << DMC_CSCR_ADDMAT_POS) +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Mask_Address EXMC DMC Mask Address + * @{ + */ +#define EXMC_DMC_ADDR_MASK_16MB (0xFFUL) +#define EXMC_DMC_ADDR_MASK_32MB (0xFEUL) +#define EXMC_DMC_ADDR_MASK_64MB (0xFCUL) +#define EXMC_DMC_ADDR_MASK_128MB (0xF8UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_DMC_Global_Functions + * @{ + */ + +/** + * @brief Get DMC status. + * @param None + * @retval Returned value can be one of the following values: + * @arg EXMC_DMC_CURR_STATUS_CONFIGURE: Configure status + * @arg EXMC_DMC_CURR_STATUS_READY: Ready status + * @arg EXMC_DMC_CURR_STATUS_PAUSED: Pause status + * @arg EXMC_DMC_CURR_STATUS_LOWPOWER: Sleep for low power status + */ +__STATIC_INLINE uint32_t EXMC_DMC_GetStatus(void) +{ + return READ_REG32_BIT(M4_DMC->STSR, DMC_STSR_STATUS); +} + +/* Initialization and configuration EXMC DMC functions */ +en_result_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcInit); +void EXMC_DMC_DeInit(void); +en_result_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcInit); +void EXMC_DMC_Cmd(en_functional_state_t enNewState); +en_result_t EXMC_DMC_CsConfig(uint32_t u32Chip, + const stc_exmc_dmc_cs_cfg_t *pstcCfg); +uint32_t EXMC_DMC_ChipStartAddress(uint32_t u32Chip); +uint32_t EXMC_DMC_ChipEndAddress(uint32_t u32Chip); +en_result_t EXMC_DMC_SetCommand(uint32_t u32Chip, + uint32_t u32Bank, + uint32_t u32Cmd, + uint32_t u32Address); +void EXMC_DMC_SetState(uint32_t u32State); + +/** + * @} + */ + +#endif /* DDL_DMC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_DMC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dvp.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dvp.h new file mode 100644 index 0000000000000000000000000000000000000000..572807f3494dd27e0cc4587c019b4c7c706aa4bd --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_dvp.h @@ -0,0 +1,293 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dvp.h + * @brief This file contains all the functions prototypes of the DVP(Digital + * Video Processor) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-08-20 Hongjh First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_DVP_H__ +#define __HC32F4A0_DVP_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_DVP + * @{ + */ + +#if (DDL_DVP_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup DVP_Global_Types DVP Global Types + * @{ + */ + +/** + * @brief DVP Initialization Structure definition + */ +typedef struct +{ + uint32_t u32SyncMode; /*!< The DVP sync mode. + This parameter can be a value of @ref DVP_Sync_Mode. */ + uint32_t u32DataWidth; /*!< The DVP data interface width. + This parameter can be a value of @ref DVP_Data_Width. */ + uint32_t u32CaptureMode; /*!< The DVP capture mode. + This parameter can be a value of @ref DVP_Capture_Mode. */ + uint32_t u32CaptureFreq; /*!< The DVP capture frequence. + This parameter can be a value of @ref DVP_Capture_Frequence. */ + uint32_t u32PIXCLKPolarity; /*!< The DVP_PIXCLK Polarity. + This parameter can be a value of @ref DVP_PIXCLK_Polarity. */ + uint32_t u32HSYNCPolarity; /*!< The DVP_HSYNC Polarity. + This parameter can be a value of @ref DVP_HSYNC_Polarity. */ + uint32_t u32VSYNCPolarity; /*!< The DVP_VSYNC Polarity. + This parameter can be a value of @ref DVP_VSYNC_Polarity. */ +} stc_dvp_init_t; + +/** + * @brief DVP Crop Window Configure definition + */ +typedef struct +{ + uint32_t u32X; /*!< The DVP window X offset + This parameter can be a value between 0x00 and 0x3FFF */ + uint32_t u32Y; /*!< The DVP window Y offset + This parameter can be a value between 0x00 and 0x3FFF */ + uint32_t u32XSize; /*!< The DVP window pixel per line + This parameter can be a value between 0x00 and 0x3FFF */ + uint32_t u32YSize; /*!< The DVP window line number. + This parameter can be a value between 0x00 and 0x3FFF */ +} stc_dvp_crop_window_config_t; + +/** + * @brief DVP Software Sync Code definition + */ +typedef struct +{ + uint32_t u32FrameStartSyncCode; /*!< The sync code of the frame start delimiter. + This parameter can be a value between 0x00 and 0xFF */ + uint32_t u32LineStartSyncCode; /*!< The sync code of the line start delimiter. + This parameter can be a value between 0x00 and 0xFF */ + uint32_t u32LineEndSyncCode; /*!< The sync code of the line end delimiter. + This parameter can be a value between 0x00 and 0xFF */ + uint32_t u32FrameEndSyncCode; /*!< The sync code of the frame end delimiter. + This parameter can be a value between 0x00 and 0xFF */ +} stc_dvp_sw_sync_code_t; + +/** + * @brief DVP Software Mask Code definition + */ +typedef struct +{ + uint32_t u32FrameStartMaskCode; /*!< The mask code of the frame start delimiter. + This parameter can be a value between between 0x00 and 0xFF */ + uint32_t u32LineStartMaskCode; /*!< The mask code of the line start delimiter. + This parameter can be a value between between 0x00 and 0xFF */ + uint32_t u32LineEndMaskCode; /*!< The mask code of the line end delimiter. + This parameter can be a value between between 0x00 and 0xFF */ + uint32_t u32FrameEndMaskCode; /*!< The mask code of the frame end delimiter. + This parameter can be a value between between 0x00 and 0xFF */ +} stc_dvp_sw_mask_code_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DVP_Global_Macros DVP Global Macros + * @{ + */ + +/** @defgroup DVP_Capture_Mode DVP Capture Mode + * @{ + */ +#define DVP_CAPT_MD_CONTINUOS_FRAME (0UL) +#define DVP_CAPT_MD_SINGLE_FRAME (DVP_CTR_CAPMD) +/** + * @} + */ + +/** @defgroup DVP_Sync_Mode DVP Sync Mode + * @{ + */ +#define DVP_SYNC_MD_HW (0UL) /*!< Hardware sync */ +#define DVP_SYNC_MD_SW (DVP_CTR_SWSYNC) /*!< Software sync */ +/** + * @} + */ + +/** @defgroup DVP_PIXCLK_Polarity DVP PIXCLK Polarity + * @{ + */ +#define DVP_PIXCLK_FALLING (0UL) /*!< DVP_PIXCLK active on Falling edge */ +#define DVP_PIXCLK_RISING (DVP_CTR_PIXCKSEL) /*!< DVP_PIXCLK active on Rising edge */ +/** + * @} + */ + +/** @defgroup DVP_HSYNC_Polarity DVP HSYNC Polarity + * @{ + */ +#define DVP_HSYNC_LOW (0UL) /*!< DVP_HSYNC active Low */ +#define DVP_HSYNC_HIGH (DVP_CTR_HSYNCSEL) /*!< DVP_HSYNC active High */ +/** + * @} + */ + +/** @defgroup DVP_VSYNC_Polarity DVP VSYNC Polarity + * @{ + */ +#define DVP_VSYNC_LOW (0UL) /*!< DVP_VSYNC active Low */ +#define DVP_VSYNC_HIGH (DVP_CTR_VSYNCSEL) /*!< DVP_VSYNC active High */ +/** + * @} + */ + +/** + * @defgroup DVP_Capture_Frequence DVP Capture Frequence + * @{ + */ +#define DVP_CAPT_FREQ_ALL_FRAME (0UL) /*!< All frames are captured */ +#define DVP_CAPT_FREQ_ONT_TIME_2FRAME (DVP_CTR_CAPFRC_0) /*!< One frame per 2 frames captured */ +#define DVP_CAPT_FREQ_ONT_TIME_4FRAME (DVP_CTR_CAPFRC_1) /*!< One frame per 4 frames captured */ +/** + * @} + */ + +/** + * @defgroup DVP_Data_Width DVP Data Width + * @{ + */ +#define DVP_DATA_WIDTH_8BIT (0UL) /*!< DVP captures 8-bit data on every DVP_PIXCLK clock */ +#define DVP_DATA_WIDTH_10BIT (DVP_CTR_BITSEL_0) /*!< DVP captures 10-bit data on every DVP_PIXCLK clock */ +#define DVP_DATA_WIDTH_12BIT (DVP_CTR_BITSEL_1) /*!< DVP captures 12-bit data on every DVP_PIXCLK clock */ +#define DVP_DATA_WIDTH_14BIT (DVP_CTR_BITSEL) /*!< DVP captures 14-bit data on every DVP_PIXCLK clock */ +/** + * @} + */ + +/** + * @defgroup DVP_Flag DVP Flag + * @{ + */ +#define DVP_FLAG_FRAME_START (DVP_STR_FSF) /*!< Frame start flag */ +#define DVP_FLAG_LINE_START (DVP_STR_LSF) /*!< Line start flag */ +#define DVP_FLAG_LINE_END (DVP_STR_LEF) /*!< Line end flag */ +#define DVP_FLAG_FRAME_END (DVP_STR_FEF) /*!< Frame end flag */ +#define DVP_FLAG_FIFO_OVF (DVP_STR_FIFOERF) /*!< FIFO overflow error flag */ +#define DVP_FLAG_SYNC_ERR (DVP_STR_SQUERF) /*!< Sync error flag */ +#define DVP_FLAG_ALL (DVP_FLAG_SYNC_ERR | \ + DVP_FLAG_FIFO_OVF | \ + DVP_FLAG_LINE_END | \ + DVP_FLAG_LINE_START | \ + DVP_FLAG_FRAME_END | \ + DVP_FLAG_FRAME_START) +/** + * @} + */ + +/** + * @defgroup DVP_Interrupt DVP Interrupt + * @{ + */ +#define DVP_INT_FRAME_START (DVP_IER_FSIEN) /*!< Frame start interrupt */ +#define DVP_INT_LINE_START (DVP_IER_LSIEN) /*!< Line start interrupt */ +#define DVP_INT_LINE_END (DVP_IER_LEIEN) /*!< Line end interrupt */ +#define DVP_INT_FRAME_END (DVP_IER_FEIEN) /*!< Frame end interrupt */ +#define DVP_INT_FIFO_OVF (DVP_IER_FIFOERIEN) /*!< FIFO overflow error interrupt */ +#define DVP_INT_SYNC_ERR (DVP_IER_SQUERIEN) /*!< Sync error interrupt */ +#define DVP_INT_ALL (DVP_INT_SYNC_ERR | \ + DVP_INT_FIFO_OVF | \ + DVP_INT_LINE_END | \ + DVP_INT_LINE_START | \ + DVP_INT_FRAME_END | \ + DVP_INT_FRAME_START) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup DVP_Global_Functions + * @{ + */ +en_result_t DVP_Init(const stc_dvp_init_t *pstcDvpInit); +void DVP_DeInit(void); +en_result_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit); +void DVP_Cmd(en_functional_state_t enNewState); +void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState); +void DVP_CropCmd(en_functional_state_t enNewState); +void DVP_JPEGCmd(en_functional_state_t enNewState); +void DVP_CaptrueCmd(en_functional_state_t enNewState); +en_functional_state_t DVP_GetCaptrueCmdState(void); +en_flag_status_t DVP_GetStatus(uint32_t u32Flag); +void DVP_ClearStatus(uint32_t u32Flag); +en_result_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode); +en_result_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode); +en_result_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig); +/** + * @} + */ + +#endif /* DDL_DVP_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_DVP_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_efm.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_efm.h new file mode 100644 index 0000000000000000000000000000000000000000..8d8b9dbc03fdd67bd8cf8f6b82345d068ab8d4e7 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_efm.h @@ -0,0 +1,1158 @@ +/** + ******************************************************************************* + * @file hc32f4a0_efm.h + * @brief This file contains all the functions prototypes of the EFM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + 2020-07-03 Heqb Add flag judgment when operate SWAP + 2020-07-07 Heqb Modify the return value type of the function + EFM_SetOperateMode from void to en_result_t + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_EFM_H__ +#define __HC32F4A0_EFM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_EFM + * @{ + */ + +#if (DDL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Types EFM Global Types + * @{ + */ + +/** + * @brief EFM configure structure + */ +typedef struct +{ + uint32_t u32WaitCycle; /*!< Specifies the efm read wait cycles. + This parameter can be a value of @ref EFM_Wait_Cycle. */ + + uint32_t u32CacheRst; /*!< Specifies the data cache reset on or off. + This parameter can be a value of @ref EFM_CacheRst_Func. */ + + uint32_t u32Prefetch; /*!< Specifies the prefetch on or off. + This parameter can be a value of @ref EFM_Prefetch_Func. */ + + uint32_t u32InsCache; /*!< Specifies the instruction cache on or off. + This parameter can be a value of @ref EFM_INSCache_Func. */ + + uint32_t u32DataCache; /*!< Specifies the data cache on or off. + This parameter can be a value of @ref EFM_DCache_Func. */ + + uint32_t u32LowVolRead; /*!< Specifies the read of low-voltage mode on or off. + This parameter can be a value of @ref EFM_LowVolRead_Mode. */ + + uint32_t u32BusStatus; /*!< Specifies the bus status busy or release while program & erase. + This parameter can be a value of @ref EFM_Bus_Status. */ + + uint32_t u32OperateMode; /*!< Specifies the operate mode. + This parameter can be a value of @ref EFM_OperateMode_Definition. */ + + uint32_t u32FlashStatus; /*!< Specifies the Flash status. + This parameter can be a value of @ref EFM_Status. */ +} stc_efm_cfg_t; + +/** + * @brief EFM unique ID definition + */ +typedef struct +{ + uint32_t u32UniqueID0; /*!< unique ID 0. */ + uint32_t u32UniqueID1; /*!< unique ID 1. */ + uint32_t u32UniqueID2; /*!< unique ID 2. */ +} stc_efm_unique_id_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Macros EFM Global Macros + * @{ + */ +#define EFM_SWAP_ADDR (0x03002000UL) +#define EFM_SWAP_DATA (0x005A5A5AUL) +/** + * @defgroup EFM_Address EFM address area + * @{ + */ +#define EFM_START_ADDR (0x00000000UL) /*!< Flash start address */ +#define EFM_END_ADDR (0x001FFFFFUL) /*!< Flash end address */ +/** + * @} + */ + +/** + * @defgroup EFM_Sector_Address EFM Sector Address + * @{ + */ +#define EFM_ADDR_SECTOR0 (0x00000000UL) /*!< Sector 0 */ +#define EFM_ADDR_SECTOR1 (0x00002000UL) /*!< Sector 1 */ +#define EFM_ADDR_SECTOR2 (0x00004000UL) /*!< Sector 2 */ +#define EFM_ADDR_SECTOR3 (0x00006000UL) /*!< Sector 3 */ +#define EFM_ADDR_SECTOR4 (0x00008000UL) /*!< Sector 4 */ +#define EFM_ADDR_SECTOR5 (0x0000A000UL) /*!< Sector 5 */ +#define EFM_ADDR_SECTOR6 (0x0000C000UL) /*!< Sector 6 */ +#define EFM_ADDR_SECTOR7 (0x0000E000UL) /*!< Sector 7 */ +#define EFM_ADDR_SECTOR8 (0x00010000UL) /*!< Sector 8 */ +#define EFM_ADDR_SECTOR9 (0x00012000UL) /*!< Sector 9 */ +#define EFM_ADDR_SECTOR10 (0x00014000UL) /*!< Sector 10 */ +#define EFM_ADDR_SECTOR11 (0x00016000UL) /*!< Sector 11 */ +#define EFM_ADDR_SECTOR12 (0x00018000UL) /*!< Sector 12 */ +#define EFM_ADDR_SECTOR13 (0x0001A000UL) /*!< Sector 13 */ +#define EFM_ADDR_SECTOR14 (0x0001C000UL) /*!< Sector 14 */ +#define EFM_ADDR_SECTOR15 (0x0001E000UL) /*!< Sector 15 */ +#define EFM_ADDR_SECTOR16 (0x00020000UL) /*!< Sector 16 */ +#define EFM_ADDR_SECTOR17 (0x00022000UL) /*!< Sector 17 */ +#define EFM_ADDR_SECTOR18 (0x00024000UL) /*!< Sector 18 */ +#define EFM_ADDR_SECTOR19 (0x00026000UL) /*!< Sector 19 */ +#define EFM_ADDR_SECTOR20 (0x00028000UL) /*!< Sector 20 */ +#define EFM_ADDR_SECTOR21 (0x0002A000UL) /*!< Sector 21 */ +#define EFM_ADDR_SECTOR22 (0x0002C000UL) /*!< Sector 22 */ +#define EFM_ADDR_SECTOR23 (0x0002E000UL) /*!< Sector 23 */ +#define EFM_ADDR_SECTOR24 (0x00030000UL) /*!< Sector 24 */ +#define EFM_ADDR_SECTOR25 (0x00032000UL) /*!< Sector 25 */ +#define EFM_ADDR_SECTOR26 (0x00034000UL) /*!< Sector 26 */ +#define EFM_ADDR_SECTOR27 (0x00036000UL) /*!< Sector 27 */ +#define EFM_ADDR_SECTOR28 (0x00038000UL) /*!< Sector 28 */ +#define EFM_ADDR_SECTOR29 (0x0003A000UL) /*!< Sector 29 */ +#define EFM_ADDR_SECTOR30 (0x0003C000UL) /*!< Sector 30 */ +#define EFM_ADDR_SECTOR31 (0x0003E000UL) /*!< Sector 31 */ +#define EFM_ADDR_SECTOR32 (0x00040000UL) /*!< Sector 32 */ +#define EFM_ADDR_SECTOR33 (0x00042000UL) /*!< Sector 33 */ +#define EFM_ADDR_SECTOR34 (0x00044000UL) /*!< Sector 34 */ +#define EFM_ADDR_SECTOR35 (0x00046000UL) /*!< Sector 35 */ +#define EFM_ADDR_SECTOR36 (0x00048000UL) /*!< Sector 36 */ +#define EFM_ADDR_SECTOR37 (0x0004A000UL) /*!< Sector 37 */ +#define EFM_ADDR_SECTOR38 (0x0004C000UL) /*!< Sector 38 */ +#define EFM_ADDR_SECTOR39 (0x0004E000UL) /*!< Sector 39 */ +#define EFM_ADDR_SECTOR40 (0x00050000UL) /*!< Sector 40 */ +#define EFM_ADDR_SECTOR41 (0x00052000UL) /*!< Sector 41 */ +#define EFM_ADDR_SECTOR42 (0x00054000UL) /*!< Sector 42 */ +#define EFM_ADDR_SECTOR43 (0x00056000UL) /*!< Sector 43 */ +#define EFM_ADDR_SECTOR44 (0x00058000UL) /*!< Sector 44 */ +#define EFM_ADDR_SECTOR45 (0x0005A000UL) /*!< Sector 45 */ +#define EFM_ADDR_SECTOR46 (0x0005C000UL) /*!< Sector 46 */ +#define EFM_ADDR_SECTOR47 (0x0005E000UL) /*!< Sector 47 */ +#define EFM_ADDR_SECTOR48 (0x00060000UL) /*!< Sector 48 */ +#define EFM_ADDR_SECTOR49 (0x00062000UL) /*!< Sector 49 */ +#define EFM_ADDR_SECTOR50 (0x00064000UL) /*!< Sector 50 */ +#define EFM_ADDR_SECTOR51 (0x00066000UL) /*!< Sector 51 */ +#define EFM_ADDR_SECTOR52 (0x00068000UL) /*!< Sector 52 */ +#define EFM_ADDR_SECTOR53 (0x0006A000UL) /*!< Sector 53 */ +#define EFM_ADDR_SECTOR54 (0x0006C000UL) /*!< Sector 54 */ +#define EFM_ADDR_SECTOR55 (0x0006E000UL) /*!< Sector 55 */ +#define EFM_ADDR_SECTOR56 (0x00070000UL) /*!< Sector 56 */ +#define EFM_ADDR_SECTOR57 (0x00072000UL) /*!< Sector 57 */ +#define EFM_ADDR_SECTOR58 (0x00074000UL) /*!< Sector 58 */ +#define EFM_ADDR_SECTOR59 (0x00076000UL) /*!< Sector 59 */ +#define EFM_ADDR_SECTOR60 (0x00078000UL) /*!< Sector 60 */ +#define EFM_ADDR_SECTOR61 (0x0007A000UL) /*!< Sector 61 */ +#define EFM_ADDR_SECTOR62 (0x0007C000UL) /*!< Sector 62 */ +#define EFM_ADDR_SECTOR63 (0x0007E000UL) /*!< Sector 63 */ +#define EFM_ADDR_SECTOR64 (0x00080000UL) /*!< Sector 64 */ +#define EFM_ADDR_SECTOR65 (0x00082000UL) /*!< Sector 65 */ +#define EFM_ADDR_SECTOR66 (0x00084000UL) /*!< Sector 66 */ +#define EFM_ADDR_SECTOR67 (0x00086000UL) /*!< Sector 67 */ +#define EFM_ADDR_SECTOR68 (0x00088000UL) /*!< Sector 68 */ +#define EFM_ADDR_SECTOR69 (0x0008A000UL) /*!< Sector 69 */ +#define EFM_ADDR_SECTOR70 (0x0008C000UL) /*!< Sector 70 */ +#define EFM_ADDR_SECTOR71 (0x0008E000UL) /*!< Sector 71 */ +#define EFM_ADDR_SECTOR72 (0x00090000UL) /*!< Sector 72 */ +#define EFM_ADDR_SECTOR73 (0x00092000UL) /*!< Sector 73 */ +#define EFM_ADDR_SECTOR74 (0x00094000UL) /*!< Sector 74 */ +#define EFM_ADDR_SECTOR75 (0x00096000UL) /*!< Sector 75 */ +#define EFM_ADDR_SECTOR76 (0x00098000UL) /*!< Sector 76 */ +#define EFM_ADDR_SECTOR77 (0x0009A000UL) /*!< Sector 77 */ +#define EFM_ADDR_SECTOR78 (0x0009C000UL) /*!< Sector 78 */ +#define EFM_ADDR_SECTOR79 (0x0009E000UL) /*!< Sector 79 */ +#define EFM_ADDR_SECTOR80 (0x000A0000UL) /*!< Sector 80 */ +#define EFM_ADDR_SECTOR81 (0x000A2000UL) /*!< Sector 81 */ +#define EFM_ADDR_SECTOR82 (0x000A4000UL) /*!< Sector 82 */ +#define EFM_ADDR_SECTOR83 (0x000A6000UL) /*!< Sector 83 */ +#define EFM_ADDR_SECTOR84 (0x000A8000UL) /*!< Sector 84 */ +#define EFM_ADDR_SECTOR85 (0x000AA000UL) /*!< Sector 85 */ +#define EFM_ADDR_SECTOR86 (0x000AC000UL) /*!< Sector 86 */ +#define EFM_ADDR_SECTOR87 (0x000AE000UL) /*!< Sector 87 */ +#define EFM_ADDR_SECTOR88 (0x000B0000UL) /*!< Sector 88 */ +#define EFM_ADDR_SECTOR89 (0x000B2000UL) /*!< Sector 89 */ +#define EFM_ADDR_SECTOR90 (0x000B4000UL) /*!< Sector 90 */ +#define EFM_ADDR_SECTOR91 (0x000B6000UL) /*!< Sector 91 */ +#define EFM_ADDR_SECTOR92 (0x000B8000UL) /*!< Sector 92 */ +#define EFM_ADDR_SECTOR93 (0x000BA000UL) /*!< Sector 93 */ +#define EFM_ADDR_SECTOR94 (0x000BC000UL) /*!< Sector 94 */ +#define EFM_ADDR_SECTOR95 (0x000BE000UL) /*!< Sector 95 */ +#define EFM_ADDR_SECTOR96 (0x000C0000UL) /*!< Sector 96 */ +#define EFM_ADDR_SECTOR97 (0x000C2000UL) /*!< Sector 97 */ +#define EFM_ADDR_SECTOR98 (0x000C4000UL) /*!< Sector 98 */ +#define EFM_ADDR_SECTOR99 (0x000C6000UL) /*!< Sector 99 */ +#define EFM_ADDR_SECTOR100 (0x000C8000UL) /*!< Sector 100 */ +#define EFM_ADDR_SECTOR101 (0x000CA000UL) /*!< Sector 101 */ +#define EFM_ADDR_SECTOR102 (0x000CC000UL) /*!< Sector 102 */ +#define EFM_ADDR_SECTOR103 (0x000CE000UL) /*!< Sector 103 */ +#define EFM_ADDR_SECTOR104 (0x000D0000UL) /*!< Sector 104 */ +#define EFM_ADDR_SECTOR105 (0x000D2000UL) /*!< Sector 105 */ +#define EFM_ADDR_SECTOR106 (0x000D4000UL) /*!< Sector 106 */ +#define EFM_ADDR_SECTOR107 (0x000D6000UL) /*!< Sector 107 */ +#define EFM_ADDR_SECTOR108 (0x000D8000UL) /*!< Sector 108 */ +#define EFM_ADDR_SECTOR109 (0x000DA000UL) /*!< Sector 109 */ +#define EFM_ADDR_SECTOR110 (0x000DC000UL) /*!< Sector 110 */ +#define EFM_ADDR_SECTOR111 (0x000DE000UL) /*!< Sector 111 */ +#define EFM_ADDR_SECTOR112 (0x000E0000UL) /*!< Sector 112 */ +#define EFM_ADDR_SECTOR113 (0x000E2000UL) /*!< Sector 113 */ +#define EFM_ADDR_SECTOR114 (0x000E4000UL) /*!< Sector 114 */ +#define EFM_ADDR_SECTOR115 (0x000E6000UL) /*!< Sector 115 */ +#define EFM_ADDR_SECTOR116 (0x000E8000UL) /*!< Sector 116 */ +#define EFM_ADDR_SECTOR117 (0x000EA000UL) /*!< Sector 117 */ +#define EFM_ADDR_SECTOR118 (0x000EC000UL) /*!< Sector 118 */ +#define EFM_ADDR_SECTOR119 (0x000EE000UL) /*!< Sector 119 */ +#define EFM_ADDR_SECTOR120 (0x000F0000UL) /*!< Sector 120 */ +#define EFM_ADDR_SECTOR121 (0x000F2000UL) /*!< Sector 121 */ +#define EFM_ADDR_SECTOR122 (0x000F4000UL) /*!< Sector 122 */ +#define EFM_ADDR_SECTOR123 (0x000F6000UL) /*!< Sector 123 */ +#define EFM_ADDR_SECTOR124 (0x000F8000UL) /*!< Sector 124 */ +#define EFM_ADDR_SECTOR125 (0x000FA000UL) /*!< Sector 125 */ +#define EFM_ADDR_SECTOR126 (0x000FC000UL) /*!< Sector 126 */ +#define EFM_ADDR_SECTOR127 (0x000FE000UL) /*!< Sector 127 */ +#define EFM_ADDR_SECTOR128 (0x00100000UL) /*!< Sector 128 */ +#define EFM_ADDR_SECTOR129 (0x00102000UL) /*!< Sector 129 */ +#define EFM_ADDR_SECTOR130 (0x00104000UL) /*!< Sector 130 */ +#define EFM_ADDR_SECTOR131 (0x00106000UL) /*!< Sector 131 */ +#define EFM_ADDR_SECTOR132 (0x00108000UL) /*!< Sector 132 */ +#define EFM_ADDR_SECTOR133 (0x0010A000UL) /*!< Sector 133 */ +#define EFM_ADDR_SECTOR134 (0x0010C000UL) /*!< Sector 134 */ +#define EFM_ADDR_SECTOR135 (0x0010E000UL) /*!< Sector 135 */ +#define EFM_ADDR_SECTOR136 (0x00110000UL) /*!< Sector 136 */ +#define EFM_ADDR_SECTOR137 (0x00112000UL) /*!< Sector 137 */ +#define EFM_ADDR_SECTOR138 (0x00114000UL) /*!< Sector 138 */ +#define EFM_ADDR_SECTOR139 (0x00116000UL) /*!< Sector 139 */ +#define EFM_ADDR_SECTOR140 (0x00118000UL) /*!< Sector 140 */ +#define EFM_ADDR_SECTOR141 (0x0011A000UL) /*!< Sector 141 */ +#define EFM_ADDR_SECTOR142 (0x0011C000UL) /*!< Sector 142 */ +#define EFM_ADDR_SECTOR143 (0x0011E000UL) /*!< Sector 143 */ +#define EFM_ADDR_SECTOR144 (0x00120000UL) /*!< Sector 144 */ +#define EFM_ADDR_SECTOR145 (0x00122000UL) /*!< Sector 145 */ +#define EFM_ADDR_SECTOR146 (0x00124000UL) /*!< Sector 146 */ +#define EFM_ADDR_SECTOR147 (0x00126000UL) /*!< Sector 147 */ +#define EFM_ADDR_SECTOR148 (0x00128000UL) /*!< Sector 148 */ +#define EFM_ADDR_SECTOR149 (0x0012A000UL) /*!< Sector 149 */ +#define EFM_ADDR_SECTOR150 (0x0012C000UL) /*!< Sector 150 */ +#define EFM_ADDR_SECTOR151 (0x0012E000UL) /*!< Sector 151 */ +#define EFM_ADDR_SECTOR152 (0x00130000UL) /*!< Sector 152 */ +#define EFM_ADDR_SECTOR153 (0x00132000UL) /*!< Sector 153 */ +#define EFM_ADDR_SECTOR154 (0x00134000UL) /*!< Sector 154 */ +#define EFM_ADDR_SECTOR155 (0x00136000UL) /*!< Sector 155 */ +#define EFM_ADDR_SECTOR156 (0x00138000UL) /*!< Sector 156 */ +#define EFM_ADDR_SECTOR157 (0x0013A000UL) /*!< Sector 157 */ +#define EFM_ADDR_SECTOR158 (0x0013C000UL) /*!< Sector 158 */ +#define EFM_ADDR_SECTOR159 (0x0013E000UL) /*!< Sector 159 */ +#define EFM_ADDR_SECTOR160 (0x00140000UL) /*!< Sector 160 */ +#define EFM_ADDR_SECTOR161 (0x00142000UL) /*!< Sector 161 */ +#define EFM_ADDR_SECTOR162 (0x00144000UL) /*!< Sector 162 */ +#define EFM_ADDR_SECTOR163 (0x00146000UL) /*!< Sector 163 */ +#define EFM_ADDR_SECTOR164 (0x00148000UL) /*!< Sector 164 */ +#define EFM_ADDR_SECTOR165 (0x0014A000UL) /*!< Sector 165 */ +#define EFM_ADDR_SECTOR166 (0x0014C000UL) /*!< Sector 166 */ +#define EFM_ADDR_SECTOR167 (0x0014E000UL) /*!< Sector 167 */ +#define EFM_ADDR_SECTOR168 (0x00150000UL) /*!< Sector 168 */ +#define EFM_ADDR_SECTOR169 (0x00152000UL) /*!< Sector 169 */ +#define EFM_ADDR_SECTOR170 (0x00154000UL) /*!< Sector 170 */ +#define EFM_ADDR_SECTOR171 (0x00156000UL) /*!< Sector 171 */ +#define EFM_ADDR_SECTOR172 (0x00158000UL) /*!< Sector 172 */ +#define EFM_ADDR_SECTOR173 (0x0015A000UL) /*!< Sector 173 */ +#define EFM_ADDR_SECTOR174 (0x0015C000UL) /*!< Sector 174 */ +#define EFM_ADDR_SECTOR175 (0x0015E000UL) /*!< Sector 175 */ +#define EFM_ADDR_SECTOR176 (0x00160000UL) /*!< Sector 176 */ +#define EFM_ADDR_SECTOR177 (0x00162000UL) /*!< Sector 177 */ +#define EFM_ADDR_SECTOR178 (0x00164000UL) /*!< Sector 178 */ +#define EFM_ADDR_SECTOR179 (0x00166000UL) /*!< Sector 179 */ +#define EFM_ADDR_SECTOR180 (0x00168000UL) /*!< Sector 180 */ +#define EFM_ADDR_SECTOR181 (0x0016A000UL) /*!< Sector 181 */ +#define EFM_ADDR_SECTOR182 (0x0016C000UL) /*!< Sector 182 */ +#define EFM_ADDR_SECTOR183 (0x0016E000UL) /*!< Sector 183 */ +#define EFM_ADDR_SECTOR184 (0x00170000UL) /*!< Sector 184 */ +#define EFM_ADDR_SECTOR185 (0x00172000UL) /*!< Sector 185 */ +#define EFM_ADDR_SECTOR186 (0x00174000UL) /*!< Sector 186 */ +#define EFM_ADDR_SECTOR187 (0x00176000UL) /*!< Sector 187 */ +#define EFM_ADDR_SECTOR188 (0x00178000UL) /*!< Sector 188 */ +#define EFM_ADDR_SECTOR189 (0x0017A000UL) /*!< Sector 189 */ +#define EFM_ADDR_SECTOR190 (0x0017C000UL) /*!< Sector 190 */ +#define EFM_ADDR_SECTOR191 (0x0017E000UL) /*!< Sector 191 */ +#define EFM_ADDR_SECTOR192 (0x00180000UL) /*!< Sector 192 */ +#define EFM_ADDR_SECTOR193 (0x00182000UL) /*!< Sector 193 */ +#define EFM_ADDR_SECTOR194 (0x00184000UL) /*!< Sector 194 */ +#define EFM_ADDR_SECTOR195 (0x00186000UL) /*!< Sector 195 */ +#define EFM_ADDR_SECTOR196 (0x00188000UL) /*!< Sector 196 */ +#define EFM_ADDR_SECTOR197 (0x0018A000UL) /*!< Sector 197 */ +#define EFM_ADDR_SECTOR198 (0x0018C000UL) /*!< Sector 198 */ +#define EFM_ADDR_SECTOR199 (0x0018E000UL) /*!< Sector 199 */ +#define EFM_ADDR_SECTOR200 (0x00190000UL) /*!< Sector 200 */ +#define EFM_ADDR_SECTOR201 (0x00192000UL) /*!< Sector 201 */ +#define EFM_ADDR_SECTOR202 (0x00194000UL) /*!< Sector 202 */ +#define EFM_ADDR_SECTOR203 (0x00196000UL) /*!< Sector 203 */ +#define EFM_ADDR_SECTOR204 (0x00198000UL) /*!< Sector 204 */ +#define EFM_ADDR_SECTOR205 (0x0019A000UL) /*!< Sector 205 */ +#define EFM_ADDR_SECTOR206 (0x0019C000UL) /*!< Sector 206 */ +#define EFM_ADDR_SECTOR207 (0x0019E000UL) /*!< Sector 207 */ +#define EFM_ADDR_SECTOR208 (0x001A0000UL) /*!< Sector 208 */ +#define EFM_ADDR_SECTOR209 (0x001A2000UL) /*!< Sector 209 */ +#define EFM_ADDR_SECTOR210 (0x001A4000UL) /*!< Sector 210 */ +#define EFM_ADDR_SECTOR211 (0x001A6000UL) /*!< Sector 211 */ +#define EFM_ADDR_SECTOR212 (0x001A8000UL) /*!< Sector 212 */ +#define EFM_ADDR_SECTOR213 (0x001AA000UL) /*!< Sector 213 */ +#define EFM_ADDR_SECTOR214 (0x001AC000UL) /*!< Sector 214 */ +#define EFM_ADDR_SECTOR215 (0x001AE000UL) /*!< Sector 215 */ +#define EFM_ADDR_SECTOR216 (0x001B0000UL) /*!< Sector 216 */ +#define EFM_ADDR_SECTOR217 (0x001B2000UL) /*!< Sector 217 */ +#define EFM_ADDR_SECTOR218 (0x001B4000UL) /*!< Sector 218 */ +#define EFM_ADDR_SECTOR219 (0x001B6000UL) /*!< Sector 219 */ +#define EFM_ADDR_SECTOR220 (0x001B8000UL) /*!< Sector 220 */ +#define EFM_ADDR_SECTOR221 (0x001BA000UL) /*!< Sector 221 */ +#define EFM_ADDR_SECTOR222 (0x001BC000UL) /*!< Sector 222 */ +#define EFM_ADDR_SECTOR223 (0x001BE000UL) /*!< Sector 223 */ +#define EFM_ADDR_SECTOR224 (0x001C0000UL) /*!< Sector 224 */ +#define EFM_ADDR_SECTOR225 (0x001C2000UL) /*!< Sector 225 */ +#define EFM_ADDR_SECTOR226 (0x001C4000UL) /*!< Sector 226 */ +#define EFM_ADDR_SECTOR227 (0x001C6000UL) /*!< Sector 227 */ +#define EFM_ADDR_SECTOR228 (0x001C8000UL) /*!< Sector 228 */ +#define EFM_ADDR_SECTOR229 (0x001CA000UL) /*!< Sector 229 */ +#define EFM_ADDR_SECTOR230 (0x001CC000UL) /*!< Sector 230 */ +#define EFM_ADDR_SECTOR231 (0x001CE000UL) /*!< Sector 231 */ +#define EFM_ADDR_SECTOR232 (0x001D0000UL) /*!< Sector 232 */ +#define EFM_ADDR_SECTOR233 (0x001D2000UL) /*!< Sector 233 */ +#define EFM_ADDR_SECTOR234 (0x001D4000UL) /*!< Sector 234 */ +#define EFM_ADDR_SECTOR235 (0x001D6000UL) /*!< Sector 235 */ +#define EFM_ADDR_SECTOR236 (0x001D8000UL) /*!< Sector 236 */ +#define EFM_ADDR_SECTOR237 (0x001DA000UL) /*!< Sector 237 */ +#define EFM_ADDR_SECTOR238 (0x001DC000UL) /*!< Sector 238 */ +#define EFM_ADDR_SECTOR239 (0x001DE000UL) /*!< Sector 239 */ +#define EFM_ADDR_SECTOR240 (0x001E0000UL) /*!< Sector 240 */ +#define EFM_ADDR_SECTOR241 (0x001E2000UL) /*!< Sector 241 */ +#define EFM_ADDR_SECTOR242 (0x001E4000UL) /*!< Sector 242 */ +#define EFM_ADDR_SECTOR243 (0x001E6000UL) /*!< Sector 243 */ +#define EFM_ADDR_SECTOR244 (0x001E8000UL) /*!< Sector 244 */ +#define EFM_ADDR_SECTOR245 (0x001EA000UL) /*!< Sector 245 */ +#define EFM_ADDR_SECTOR246 (0x001EC000UL) /*!< Sector 246 */ +#define EFM_ADDR_SECTOR247 (0x001EE000UL) /*!< Sector 247 */ +#define EFM_ADDR_SECTOR248 (0x001F0000UL) /*!< Sector 248 */ +#define EFM_ADDR_SECTOR249 (0x001F2000UL) /*!< Sector 249 */ +#define EFM_ADDR_SECTOR250 (0x001F4000UL) /*!< Sector 250 */ +#define EFM_ADDR_SECTOR251 (0x001F6000UL) /*!< Sector 251 */ +#define EFM_ADDR_SECTOR252 (0x001F8000UL) /*!< Sector 252 */ +#define EFM_ADDR_SECTOR253 (0x001FA000UL) /*!< Sector 253 */ +#define EFM_ADDR_SECTOR254 (0x001FC000UL) /*!< Sector 254 */ +#define EFM_ADDR_SECTOR255 (0x001FE000UL) /*!< Sector 255 */ +/** + * @} + */ + +/** + * @defgroup EFM_OTP_Address EFM otp address + * @{ + */ +#define EFM_OTP_BLOCK0 (0x00000000UL) /*!< OTP block0 8K Bytes */ +#define EFM_OTP_BLOCK1 (0x00002000UL) /*!< OTP block1 8K Bytes */ +#define EFM_OTP_BLOCK2 (0x00004000UL) /*!< OTP block2 8K Bytes */ +#define EFM_OTP_BLOCK3 (0x00006000UL) /*!< OTP block3 8K Bytes */ +#define EFM_OTP_BLOCK4 (0x00008000UL) /*!< OTP block4 8K Bytes */ +#define EFM_OTP_BLOCK5 (0x0000A000UL) /*!< OTP block5 8K Bytes */ +#define EFM_OTP_BLOCK6 (0x0000C000UL) /*!< OTP block6 8K Bytes */ +#define EFM_OTP_BLOCK7 (0x0000E000UL) /*!< OTP block7 8K Bytes */ +#define EFM_OTP_BLOCK8 (0x00010000UL) /*!< OTP block8 8K Bytes */ +#define EFM_OTP_BLOCK9 (0x00012000UL) /*!< OTP block9 8K Bytes */ +#define EFM_OTP_BLOCK10 (0x00014000UL) /*!< OTP block10 8K Bytes */ +#define EFM_OTP_BLOCK11 (0x00016000UL) /*!< OTP block11 8K Bytes */ +#define EFM_OTP_BLOCK12 (0x00018000UL) /*!< OTP block12 8K Bytes */ +#define EFM_OTP_BLOCK13 (0x0001A000UL) /*!< OTP block13 8K Bytes */ +#define EFM_OTP_BLOCK14 (0x0001C000UL) /*!< OTP block14 8K Bytes */ +#define EFM_OTP_BLOCK15 (0x0001E000UL) /*!< OTP block15 8K Bytes */ + +#define EFM_OTP_BLOCK16 (0x03000000UL) /*!< OTP block16 2K Bytes */ +#define EFM_OTP_BLOCK17 (0x03000800UL) /*!< OTP block17 2K Bytes */ + +#define EFM_OTP_BLOCK18 (0x03001000UL) /*!< OTP block18 256 Bytes */ +#define EFM_OTP_BLOCK19 (0x03001100UL) /*!< OTP block19 256 Bytes */ +#define EFM_OTP_BLOCK20 (0x03001200UL) /*!< OTP block20 256 Bytes */ +#define EFM_OTP_BLOCK21 (0x03001300UL) /*!< OTP block21 256 Bytes */ + +#define EFM_OTP_BLOCK22 (0x03001400UL) /*!< OTP block22 16 Bytes */ +#define EFM_OTP_BLOCK23 (0x03001410UL) /*!< OTP block23 16 Bytes */ +#define EFM_OTP_BLOCK24 (0x03001420UL) /*!< OTP block24 16 Bytes */ +#define EFM_OTP_BLOCK25 (0x03001430UL) /*!< OTP block25 16 Bytes */ +#define EFM_OTP_BLOCK26 (0x03001440UL) /*!< OTP block26 16 Bytes */ +#define EFM_OTP_BLOCK27 (0x03001450UL) /*!< OTP block27 16 Bytes */ +#define EFM_OTP_BLOCK28 (0x03001460UL) /*!< OTP block28 16 Bytes */ +#define EFM_OTP_BLOCK29 (0x03001470UL) /*!< OTP block29 16 Bytes */ +#define EFM_OTP_BLOCK30 (0x03001480UL) /*!< OTP block30 16 Bytes */ +#define EFM_OTP_BLOCK31 (0x03001490UL) /*!< OTP block31 16 Bytes */ +#define EFM_OTP_BLOCK32 (0x030014A0UL) /*!< OTP block32 16 Bytes */ +#define EFM_OTP_BLOCK33 (0x030014B0UL) /*!< OTP block33 16 Bytes */ +#define EFM_OTP_BLOCK34 (0x030014C0UL) /*!< OTP block34 16 Bytes */ +#define EFM_OTP_BLOCK35 (0x030014D0UL) /*!< OTP block35 16 Bytes */ +#define EFM_OTP_BLOCK36 (0x030014E0UL) /*!< OTP block36 16 Bytes */ +#define EFM_OTP_BLOCK37 (0x030014F0UL) /*!< OTP block37 16 Bytes */ +#define EFM_OTP_BLOCK38 (0x03001500UL) /*!< OTP block38 16 Bytes */ +#define EFM_OTP_BLOCK39 (0x03001510UL) /*!< OTP block39 16 Bytes */ +#define EFM_OTP_BLOCK40 (0x03001520UL) /*!< OTP block40 16 Bytes */ +#define EFM_OTP_BLOCK41 (0x03001530UL) /*!< OTP block41 16 Bytes */ +#define EFM_OTP_BLOCK42 (0x03001540UL) /*!< OTP block42 16 Bytes */ +#define EFM_OTP_BLOCK43 (0x03001550UL) /*!< OTP block43 16 Bytes */ +#define EFM_OTP_BLOCK44 (0x03001560UL) /*!< OTP block44 16 Bytes */ +#define EFM_OTP_BLOCK45 (0x03001570UL) /*!< OTP block45 16 Bytes */ +#define EFM_OTP_BLOCK46 (0x03001580UL) /*!< OTP block46 16 Bytes */ +#define EFM_OTP_BLOCK47 (0x03001590UL) /*!< OTP block47 16 Bytes */ +#define EFM_OTP_BLOCK48 (0x030015A0UL) /*!< OTP block48 16 Bytes */ +#define EFM_OTP_BLOCK49 (0x030015B0UL) /*!< OTP block49 16 Bytes */ +#define EFM_OTP_BLOCK50 (0x030015C0UL) /*!< OTP block50 16 Bytes */ +#define EFM_OTP_BLOCK51 (0x030015D0UL) /*!< OTP block51 16 Bytes */ +#define EFM_OTP_BLOCK52 (0x030015E0UL) /*!< OTP block52 16 Bytes */ +#define EFM_OTP_BLOCK53 (0x030015F0UL) /*!< OTP block53 16 Bytes */ + +#define EFM_OTP_BLOCK54 (0x03001600UL) /*!< OTP block54 4 Bytes */ +#define EFM_OTP_BLOCK55 (0x03001604UL) /*!< OTP block55 4 Bytes */ +#define EFM_OTP_BLOCK56 (0x03001608UL) /*!< OTP block56 4 Bytes */ +#define EFM_OTP_BLOCK57 (0x0300160CUL) /*!< OTP block57 4 Bytes */ +#define EFM_OTP_BLOCK58 (0x03001610UL) /*!< OTP block58 4 Bytes */ +#define EFM_OTP_BLOCK59 (0x03001614UL) /*!< OTP block59 4 Bytes */ +#define EFM_OTP_BLOCK60 (0x03001618UL) /*!< OTP block60 4 Bytes */ +#define EFM_OTP_BLOCK61 (0x0300161CUL) /*!< OTP block61 4 Bytes */ +#define EFM_OTP_BLOCK62 (0x03001620UL) /*!< OTP block62 4 Bytes */ +#define EFM_OTP_BLOCK63 (0x03001624UL) /*!< OTP block63 4 Bytes */ +#define EFM_OTP_BLOCK64 (0x03001628UL) /*!< OTP block64 4 Bytes */ +#define EFM_OTP_BLOCK65 (0x0300162CUL) /*!< OTP block65 4 Bytes */ +#define EFM_OTP_BLOCK66 (0x03001630UL) /*!< OTP block66 4 Bytes */ +#define EFM_OTP_BLOCK67 (0x03001634UL) /*!< OTP block67 4 Bytes */ +#define EFM_OTP_BLOCK68 (0x03001638UL) /*!< OTP block68 4 Bytes */ +#define EFM_OTP_BLOCK69 (0x0300163CUL) /*!< OTP block69 4 Bytes */ +#define EFM_OTP_BLOCK70 (0x03001640UL) /*!< OTP block70 4 Bytes */ +#define EFM_OTP_BLOCK71 (0x03001644UL) /*!< OTP block71 4 Bytes */ +#define EFM_OTP_BLOCK72 (0x03001648UL) /*!< OTP block72 4 Bytes */ +#define EFM_OTP_BLOCK73 (0x0300164CUL) /*!< OTP block73 4 Bytes */ +#define EFM_OTP_BLOCK74 (0x03001650UL) /*!< OTP block74 4 Bytes */ +#define EFM_OTP_BLOCK75 (0x03001654UL) /*!< OTP block75 4 Bytes */ +#define EFM_OTP_BLOCK76 (0x03001658UL) /*!< OTP block76 4 Bytes */ +#define EFM_OTP_BLOCK77 (0x0300165CUL) /*!< OTP block77 4 Bytes */ +#define EFM_OTP_BLOCK78 (0x03001660UL) /*!< OTP block78 4 Bytes */ +#define EFM_OTP_BLOCK79 (0x03001664UL) /*!< OTP block79 4 Bytes */ +#define EFM_OTP_BLOCK80 (0x03001668UL) /*!< OTP block80 4 Bytes */ +#define EFM_OTP_BLOCK81 (0x0300166CUL) /*!< OTP block81 4 Bytes */ +#define EFM_OTP_BLOCK82 (0x03001670UL) /*!< OTP block82 4 Bytes */ +#define EFM_OTP_BLOCK83 (0x03001674UL) /*!< OTP block83 4 Bytes */ +#define EFM_OTP_BLOCK84 (0x03001678UL) /*!< OTP block84 4 Bytes */ +#define EFM_OTP_BLOCK85 (0x0300167CUL) /*!< OTP block85 4 Bytes */ +#define EFM_OTP_BLOCK86 (0x03001680UL) /*!< OTP block86 4 Bytes */ +#define EFM_OTP_BLOCK87 (0x03001684UL) /*!< OTP block87 4 Bytes */ +#define EFM_OTP_BLOCK88 (0x03001688UL) /*!< OTP block88 4 Bytes */ +#define EFM_OTP_BLOCK89 (0x0300168CUL) /*!< OTP block89 4 Bytes */ +#define EFM_OTP_BLOCK90 (0x03001690UL) /*!< OTP block90 4 Bytes */ +#define EFM_OTP_BLOCK91 (0x03001694UL) /*!< OTP block91 4 Bytes */ +#define EFM_OTP_BLOCK92 (0x03001698UL) /*!< OTP block92 4 Bytes */ +#define EFM_OTP_BLOCK93 (0x0300169CUL) /*!< OTP block93 4 Bytes */ +#define EFM_OTP_BLOCK94 (0x030016A0UL) /*!< OTP block94 4 Bytes */ +#define EFM_OTP_BLOCK95 (0x030016A4UL) /*!< OTP block95 4 Bytes */ +#define EFM_OTP_BLOCK96 (0x030016A8UL) /*!< OTP block96 4 Bytes */ +#define EFM_OTP_BLOCK97 (0x030016ACUL) /*!< OTP block97 4 Bytes */ +#define EFM_OTP_BLOCK98 (0x030016B0UL) /*!< OTP block98 4 Bytes */ +#define EFM_OTP_BLOCK99 (0x030016B4UL) /*!< OTP block99 4 Bytes */ +#define EFM_OTP_BLOCK100 (0x030016B8UL) /*!< OTP block100 4 Bytes */ +#define EFM_OTP_BLOCK101 (0x030016BCUL) /*!< OTP block101 4 Bytes */ +#define EFM_OTP_BLOCK102 (0x030016C0UL) /*!< OTP block102 4 Bytes */ +#define EFM_OTP_BLOCK103 (0x030016C4UL) /*!< OTP block103 4 Bytes */ +#define EFM_OTP_BLOCK104 (0x030016C8UL) /*!< OTP block104 4 Bytes */ +#define EFM_OTP_BLOCK105 (0x030016CCUL) /*!< OTP block105 4 Bytes */ +#define EFM_OTP_BLOCK106 (0x030016D0UL) /*!< OTP block106 4 Bytes */ +#define EFM_OTP_BLOCK107 (0x030016D4UL) /*!< OTP block107 4 Bytes */ +#define EFM_OTP_BLOCK108 (0x030016D8UL) /*!< OTP block108 4 Bytes */ +#define EFM_OTP_BLOCK109 (0x030016DCUL) /*!< OTP block109 4 Bytes */ +#define EFM_OTP_BLOCK110 (0x030016E0UL) /*!< OTP block110 4 Bytes */ +#define EFM_OTP_BLOCK111 (0x030016E4UL) /*!< OTP block111 4 Bytes */ +#define EFM_OTP_BLOCK112 (0x030016E8UL) /*!< OTP block112 4 Bytes */ +#define EFM_OTP_BLOCK113 (0x030016ECUL) /*!< OTP block113 4 Bytes */ +#define EFM_OTP_BLOCK114 (0x030016F0UL) /*!< OTP block114 4 Bytes */ +#define EFM_OTP_BLOCK115 (0x030016F4UL) /*!< OTP block115 4 Bytes */ +#define EFM_OTP_BLOCK116 (0x030016F8UL) /*!< OTP block116 4 Bytes */ +#define EFM_OTP_BLOCK117 (0x030016FCUL) /*!< OTP block117 4 Bytes */ +#define EFM_OTP_BLOCK118 (0x03001700UL) /*!< OTP block118 4 Bytes */ +#define EFM_OTP_BLOCK119 (0x03001704UL) /*!< OTP block119 4 Bytes */ +#define EFM_OTP_BLOCK120 (0x03001708UL) /*!< OTP block120 4 Bytes */ +#define EFM_OTP_BLOCK121 (0x0300170CUL) /*!< OTP block121 4 Bytes */ +#define EFM_OTP_BLOCK122 (0x03001710UL) /*!< OTP block122 4 Bytes */ +#define EFM_OTP_BLOCK123 (0x03001714UL) /*!< OTP block123 4 Bytes */ +#define EFM_OTP_BLOCK124 (0x03001718UL) /*!< OTP block124 4 Bytes */ +#define EFM_OTP_BLOCK125 (0x0300171CUL) /*!< OTP block125 4 Bytes */ +#define EFM_OTP_BLOCK126 (0x03001720UL) /*!< OTP block126 4 Bytes */ +#define EFM_OTP_BLOCK127 (0x03001724UL) /*!< OTP block127 4 Bytes */ +#define EFM_OTP_BLOCK128 (0x03001728UL) /*!< OTP block128 4 Bytes */ +#define EFM_OTP_BLOCK129 (0x0300172CUL) /*!< OTP block129 4 Bytes */ +#define EFM_OTP_BLOCK130 (0x03001730UL) /*!< OTP block130 4 Bytes */ +#define EFM_OTP_BLOCK131 (0x03001734UL) /*!< OTP block131 4 Bytes */ +#define EFM_OTP_BLOCK132 (0x03001738UL) /*!< OTP block132 4 Bytes */ +#define EFM_OTP_BLOCK133 (0x0300173CUL) /*!< OTP block133 4 Bytes */ +#define EFM_OTP_BLOCK134 (0x03001740UL) /*!< OTP block134 4 Bytes */ +#define EFM_OTP_BLOCK135 (0x03001744UL) /*!< OTP block135 4 Bytes */ +#define EFM_OTP_BLOCK136 (0x03001748UL) /*!< OTP block136 4 Bytes */ +#define EFM_OTP_BLOCK137 (0x0300174CUL) /*!< OTP block137 4 Bytes */ +#define EFM_OTP_BLOCK138 (0x03001750UL) /*!< OTP block138 4 Bytes */ +#define EFM_OTP_BLOCK139 (0x03001754UL) /*!< OTP block139 4 Bytes */ +#define EFM_OTP_BLOCK140 (0x03001758UL) /*!< OTP block140 4 Bytes */ +#define EFM_OTP_BLOCK141 (0x0300175CUL) /*!< OTP block141 4 Bytes */ +#define EFM_OTP_BLOCK142 (0x03001760UL) /*!< OTP block142 4 Bytes */ +#define EFM_OTP_BLOCK143 (0x03001764UL) /*!< OTP block143 4 Bytes */ +#define EFM_OTP_BLOCK144 (0x03001768UL) /*!< OTP block144 4 Bytes */ +#define EFM_OTP_BLOCK145 (0x0300176CUL) /*!< OTP block145 4 Bytes */ +#define EFM_OTP_BLOCK146 (0x03001770UL) /*!< OTP block146 4 Bytes */ +#define EFM_OTP_BLOCK147 (0x03001774UL) /*!< OTP block147 4 Bytes */ +#define EFM_OTP_BLOCK148 (0x03001778UL) /*!< OTP block148 4 Bytes */ +#define EFM_OTP_BLOCK149 (0x0300177CUL) /*!< OTP block149 4 Bytes */ +#define EFM_OTP_BLOCK150 (0x03001780UL) /*!< OTP block150 4 Bytes */ +#define EFM_OTP_BLOCK151 (0x03001784UL) /*!< OTP block151 4 Bytes */ +#define EFM_OTP_BLOCK152 (0x03001788UL) /*!< OTP block152 4 Bytes */ +#define EFM_OTP_BLOCK153 (0x0300178CUL) /*!< OTP block153 4 Bytes */ +#define EFM_OTP_BLOCK154 (0x03001790UL) /*!< OTP block154 4 Bytes */ +#define EFM_OTP_BLOCK155 (0x03001794UL) /*!< OTP block155 4 Bytes */ +#define EFM_OTP_BLOCK156 (0x03001798UL) /*!< OTP block156 4 Bytes */ +#define EFM_OTP_BLOCK157 (0x0300179CUL) /*!< OTP block157 4 Bytes */ +#define EFM_OTP_BLOCK158 (0x030017A0UL) /*!< OTP block158 4 Bytes */ +#define EFM_OTP_BLOCK159 (0x030017A4UL) /*!< OTP block159 4 Bytes */ +#define EFM_OTP_BLOCK160 (0x030017A8UL) /*!< OTP block160 4 Bytes */ +#define EFM_OTP_BLOCK161 (0x030017ACUL) /*!< OTP block161 4 Bytes */ +#define EFM_OTP_BLOCK162 (0x030017B0UL) /*!< OTP block162 4 Bytes */ +#define EFM_OTP_BLOCK163 (0x030017B4UL) /*!< OTP block163 4 Bytes */ +#define EFM_OTP_BLOCK164 (0x030017B8UL) /*!< OTP block164 4 Bytes */ +#define EFM_OTP_BLOCK165 (0x030017BCUL) /*!< OTP block165 4 Bytes */ +#define EFM_OTP_BLOCK166 (0x030017C0UL) /*!< OTP block166 4 Bytes */ +#define EFM_OTP_BLOCK167 (0x030017C4UL) /*!< OTP block167 4 Bytes */ +#define EFM_OTP_BLOCK168 (0x030017C8UL) /*!< OTP block168 4 Bytes */ +#define EFM_OTP_BLOCK169 (0x030017CCUL) /*!< OTP block169 4 Bytes */ +#define EFM_OTP_BLOCK170 (0x030017D0UL) /*!< OTP block170 4 Bytes */ +#define EFM_OTP_BLOCK171 (0x030017D4UL) /*!< OTP block171 4 Bytes */ +#define EFM_OTP_BLOCK172 (0x030017D8UL) /*!< OTP block172 4 Bytes */ +#define EFM_OTP_BLOCK173 (0x030017DCUL) /*!< OTP block173 4 Bytes */ +#define EFM_OTP_BLOCK174 (0x030017E0UL) /*!< OTP block174 4 Bytes */ +#define EFM_OTP_BLOCK175 (0x030017E4UL) /*!< OTP block175 4 Bytes */ +#define EFM_OTP_BLOCK176 (0x030017E8UL) /*!< OTP block176 4 Bytes */ +#define EFM_OTP_BLOCK177 (0x030017ECUL) /*!< OTP block177 4 Bytes */ +#define EFM_OTP_BLOCK178 (0x030017F0UL) /*!< OTP block178 4 Bytes */ +#define EFM_OTP_BLOCK179 (0x030017F4UL) /*!< OTP block179 4 Bytes */ +#define EFM_OTP_BLOCK180 (0x030017F8UL) /*!< OTP block180 4 Bytes */ +#define EFM_OTP_BLOCK181 (0x030017FCUL) /*!< OTP block181 4 Bytes */ +/** + * @} + */ + +/** + * @defgroup EFM_Sectot_Num Efm sector number + * @{ + */ +#define EFM_SECTOR_0 (0U) +#define EFM_SECTOR_1 (1U) +#define EFM_SECTOR_2 (2U) +#define EFM_SECTOR_3 (3U) +#define EFM_SECTOR_4 (4U) +#define EFM_SECTOR_5 (5U) +#define EFM_SECTOR_6 (6U) +#define EFM_SECTOR_7 (7U) +#define EFM_SECTOR_8 (8U) +#define EFM_SECTOR_9 (9U) +#define EFM_SECTOR_10 (10U) +#define EFM_SECTOR_11 (11U) +#define EFM_SECTOR_12 (12U) +#define EFM_SECTOR_13 (13U) +#define EFM_SECTOR_14 (14U) +#define EFM_SECTOR_15 (15U) +#define EFM_SECTOR_16 (16U) +#define EFM_SECTOR_17 (17U) +#define EFM_SECTOR_18 (18U) +#define EFM_SECTOR_19 (19U) +#define EFM_SECTOR_20 (20U) +#define EFM_SECTOR_21 (21U) +#define EFM_SECTOR_22 (22U) +#define EFM_SECTOR_23 (23U) +#define EFM_SECTOR_24 (24U) +#define EFM_SECTOR_25 (25U) +#define EFM_SECTOR_26 (26U) +#define EFM_SECTOR_27 (27U) +#define EFM_SECTOR_28 (28U) +#define EFM_SECTOR_29 (29U) +#define EFM_SECTOR_30 (30U) +#define EFM_SECTOR_31 (31U) +#define EFM_SECTOR_32 (32U) +#define EFM_SECTOR_33 (33U) +#define EFM_SECTOR_34 (34U) +#define EFM_SECTOR_35 (35U) +#define EFM_SECTOR_36 (36U) +#define EFM_SECTOR_37 (37U) +#define EFM_SECTOR_38 (38U) +#define EFM_SECTOR_39 (39U) +#define EFM_SECTOR_40 (40U) +#define EFM_SECTOR_41 (41U) +#define EFM_SECTOR_42 (42U) +#define EFM_SECTOR_43 (43U) +#define EFM_SECTOR_44 (44U) +#define EFM_SECTOR_45 (45U) +#define EFM_SECTOR_46 (46U) +#define EFM_SECTOR_47 (47U) +#define EFM_SECTOR_48 (48U) +#define EFM_SECTOR_49 (49U) +#define EFM_SECTOR_50 (50U) +#define EFM_SECTOR_51 (51U) +#define EFM_SECTOR_52 (52U) +#define EFM_SECTOR_53 (53U) +#define EFM_SECTOR_54 (54U) +#define EFM_SECTOR_55 (55U) +#define EFM_SECTOR_56 (56U) +#define EFM_SECTOR_57 (57U) +#define EFM_SECTOR_58 (58U) +#define EFM_SECTOR_59 (59U) +#define EFM_SECTOR_60 (60U) +#define EFM_SECTOR_61 (61U) +#define EFM_SECTOR_62 (62U) +#define EFM_SECTOR_63 (63U) +#define EFM_SECTOR_64 (64U) +#define EFM_SECTOR_65 (65U) +#define EFM_SECTOR_66 (66U) +#define EFM_SECTOR_67 (67U) +#define EFM_SECTOR_68 (68U) +#define EFM_SECTOR_69 (69U) +#define EFM_SECTOR_70 (70U) +#define EFM_SECTOR_71 (71U) +#define EFM_SECTOR_72 (72U) +#define EFM_SECTOR_73 (73U) +#define EFM_SECTOR_74 (74U) +#define EFM_SECTOR_75 (75U) +#define EFM_SECTOR_76 (76U) +#define EFM_SECTOR_77 (77U) +#define EFM_SECTOR_78 (78U) +#define EFM_SECTOR_79 (79U) +#define EFM_SECTOR_80 (80U) +#define EFM_SECTOR_81 (81U) +#define EFM_SECTOR_82 (82U) +#define EFM_SECTOR_83 (83U) +#define EFM_SECTOR_84 (84U) +#define EFM_SECTOR_85 (85U) +#define EFM_SECTOR_86 (86U) +#define EFM_SECTOR_87 (87U) +#define EFM_SECTOR_88 (88U) +#define EFM_SECTOR_89 (89U) +#define EFM_SECTOR_90 (90U) +#define EFM_SECTOR_91 (91U) +#define EFM_SECTOR_92 (92U) +#define EFM_SECTOR_93 (93U) +#define EFM_SECTOR_94 (94U) +#define EFM_SECTOR_95 (95U) +#define EFM_SECTOR_96 (96U) +#define EFM_SECTOR_97 (97U) +#define EFM_SECTOR_98 (98U) +#define EFM_SECTOR_99 (99U) +#define EFM_SECTOR_100 (100U) +#define EFM_SECTOR_101 (101U) +#define EFM_SECTOR_102 (102U) +#define EFM_SECTOR_103 (103U) +#define EFM_SECTOR_104 (104U) +#define EFM_SECTOR_105 (105U) +#define EFM_SECTOR_106 (106U) +#define EFM_SECTOR_107 (107U) +#define EFM_SECTOR_108 (108U) +#define EFM_SECTOR_109 (109U) +#define EFM_SECTOR_110 (110U) +#define EFM_SECTOR_111 (111U) +#define EFM_SECTOR_112 (112U) +#define EFM_SECTOR_113 (113U) +#define EFM_SECTOR_114 (114U) +#define EFM_SECTOR_115 (115U) +#define EFM_SECTOR_116 (116U) +#define EFM_SECTOR_117 (117U) +#define EFM_SECTOR_118 (118U) +#define EFM_SECTOR_119 (119U) +#define EFM_SECTOR_120 (120U) +#define EFM_SECTOR_121 (121U) +#define EFM_SECTOR_122 (122U) +#define EFM_SECTOR_123 (123U) +#define EFM_SECTOR_124 (124U) +#define EFM_SECTOR_125 (125U) +#define EFM_SECTOR_126 (126U) +#define EFM_SECTOR_127 (127U) +#define EFM_SECTOR_128 (128U) +#define EFM_SECTOR_129 (129U) +#define EFM_SECTOR_130 (130U) +#define EFM_SECTOR_131 (131U) +#define EFM_SECTOR_132 (132U) +#define EFM_SECTOR_133 (133U) +#define EFM_SECTOR_134 (134U) +#define EFM_SECTOR_135 (135U) +#define EFM_SECTOR_136 (136U) +#define EFM_SECTOR_137 (137U) +#define EFM_SECTOR_138 (138U) +#define EFM_SECTOR_139 (139U) +#define EFM_SECTOR_140 (140U) +#define EFM_SECTOR_141 (141U) +#define EFM_SECTOR_142 (142U) +#define EFM_SECTOR_143 (143U) +#define EFM_SECTOR_144 (144U) +#define EFM_SECTOR_145 (145U) +#define EFM_SECTOR_146 (146U) +#define EFM_SECTOR_147 (147U) +#define EFM_SECTOR_148 (148U) +#define EFM_SECTOR_149 (149U) +#define EFM_SECTOR_150 (150U) +#define EFM_SECTOR_151 (151U) +#define EFM_SECTOR_152 (152U) +#define EFM_SECTOR_153 (153U) +#define EFM_SECTOR_154 (154U) +#define EFM_SECTOR_155 (155U) +#define EFM_SECTOR_156 (156U) +#define EFM_SECTOR_157 (157U) +#define EFM_SECTOR_158 (158U) +#define EFM_SECTOR_159 (159U) +#define EFM_SECTOR_160 (160U) +#define EFM_SECTOR_161 (161U) +#define EFM_SECTOR_162 (162U) +#define EFM_SECTOR_163 (163U) +#define EFM_SECTOR_164 (164U) +#define EFM_SECTOR_165 (165U) +#define EFM_SECTOR_166 (166U) +#define EFM_SECTOR_167 (167U) +#define EFM_SECTOR_168 (168U) +#define EFM_SECTOR_169 (169U) +#define EFM_SECTOR_170 (170U) +#define EFM_SECTOR_171 (171U) +#define EFM_SECTOR_172 (172U) +#define EFM_SECTOR_173 (173U) +#define EFM_SECTOR_174 (174U) +#define EFM_SECTOR_175 (175U) +#define EFM_SECTOR_176 (176U) +#define EFM_SECTOR_177 (177U) +#define EFM_SECTOR_178 (178U) +#define EFM_SECTOR_179 (179U) +#define EFM_SECTOR_180 (180U) +#define EFM_SECTOR_181 (181U) +#define EFM_SECTOR_182 (182U) +#define EFM_SECTOR_183 (183U) +#define EFM_SECTOR_184 (184U) +#define EFM_SECTOR_185 (185U) +#define EFM_SECTOR_186 (186U) +#define EFM_SECTOR_187 (187U) +#define EFM_SECTOR_188 (188U) +#define EFM_SECTOR_189 (189U) +#define EFM_SECTOR_190 (190U) +#define EFM_SECTOR_191 (191U) +#define EFM_SECTOR_192 (192U) +#define EFM_SECTOR_193 (193U) +#define EFM_SECTOR_194 (194U) +#define EFM_SECTOR_195 (195U) +#define EFM_SECTOR_196 (196U) +#define EFM_SECTOR_197 (197U) +#define EFM_SECTOR_198 (198U) +#define EFM_SECTOR_199 (199U) +#define EFM_SECTOR_200 (200U) +#define EFM_SECTOR_201 (201U) +#define EFM_SECTOR_202 (202U) +#define EFM_SECTOR_203 (203U) +#define EFM_SECTOR_204 (204U) +#define EFM_SECTOR_205 (205U) +#define EFM_SECTOR_206 (206U) +#define EFM_SECTOR_207 (207U) +#define EFM_SECTOR_208 (208U) +#define EFM_SECTOR_209 (209U) +#define EFM_SECTOR_210 (210U) +#define EFM_SECTOR_211 (211U) +#define EFM_SECTOR_212 (212U) +#define EFM_SECTOR_213 (213U) +#define EFM_SECTOR_214 (214U) +#define EFM_SECTOR_215 (215U) +#define EFM_SECTOR_216 (216U) +#define EFM_SECTOR_217 (217U) +#define EFM_SECTOR_218 (218U) +#define EFM_SECTOR_219 (219U) +#define EFM_SECTOR_220 (220U) +#define EFM_SECTOR_221 (221U) +#define EFM_SECTOR_222 (222U) +#define EFM_SECTOR_223 (223U) +#define EFM_SECTOR_224 (224U) +#define EFM_SECTOR_225 (225U) +#define EFM_SECTOR_226 (226U) +#define EFM_SECTOR_227 (227U) +#define EFM_SECTOR_228 (228U) +#define EFM_SECTOR_229 (229U) +#define EFM_SECTOR_230 (230U) +#define EFM_SECTOR_231 (231U) +#define EFM_SECTOR_232 (232U) +#define EFM_SECTOR_233 (233U) +#define EFM_SECTOR_234 (234U) +#define EFM_SECTOR_235 (235U) +#define EFM_SECTOR_236 (236U) +#define EFM_SECTOR_237 (237U) +#define EFM_SECTOR_238 (238U) +#define EFM_SECTOR_239 (239U) +#define EFM_SECTOR_240 (240U) +#define EFM_SECTOR_241 (241U) +#define EFM_SECTOR_242 (242U) +#define EFM_SECTOR_243 (243U) +#define EFM_SECTOR_244 (244U) +#define EFM_SECTOR_245 (245U) +#define EFM_SECTOR_246 (246U) +#define EFM_SECTOR_247 (247U) +#define EFM_SECTOR_248 (248U) +#define EFM_SECTOR_249 (249U) +#define EFM_SECTOR_250 (250U) +#define EFM_SECTOR_251 (251U) +#define EFM_SECTOR_252 (252U) +#define EFM_SECTOR_253 (253U) +#define EFM_SECTOR_254 (254U) +#define EFM_SECTOR_255 (255U) +/** + * @} + */ + +/** + * @defgroup EFM_Wait_Cycle EFM Wait Cycle + * @{ + */ +#define EFM_WAIT_CYCLE_0 (0U) /*!< Don't insert read wait cycle */ +#define EFM_WAIT_CYCLE_1 (1U) /*!< Insert 1 read wait cycle */ +#define EFM_WAIT_CYCLE_2 (2U) /*!< Insert 2 read wait cycles */ +#define EFM_WAIT_CYCLE_3 (3U) /*!< Insert 3 read wait cycles */ +#define EFM_WAIT_CYCLE_4 (4U) /*!< Insert 4 read wait cycles */ +#define EFM_WAIT_CYCLE_5 (5U) /*!< Insert 5 read wait cycles */ +#define EFM_WAIT_CYCLE_6 (6U) /*!< Insert 6 read wait cycles */ +#define EFM_WAIT_CYCLE_7 (7U) /*!< Insert 7 read wait cycles */ +#define EFM_WAIT_CYCLE_8 (8U) /*!< Insert 8 read wait cycles */ +#define EFM_WAIT_CYCLE_9 (9U) /*!< Insert 9 read wait cycles */ +#define EFM_WAIT_CYCLE_10 (10U) /*!< Insert 10 read wait cycles */ +#define EFM_WAIT_CYCLE_11 (11U) /*!< Insert 11 read wait cycles */ +#define EFM_WAIT_CYCLE_12 (12U) /*!< Insert 12 read wait cycles */ +#define EFM_WAIT_CYCLE_13 (13U) /*!< Insert 13 read wait cycles */ +#define EFM_WAIT_CYCLE_14 (14U) /*!< Insert 14 read wait cycles */ +#define EFM_WAIT_CYCLE_15 (15U) /*!< Insert 15 read wait cycles */ +/** + * @} + */ + +/** + * @defgroup EFM_CacheRst_Func EFM data cache reset function + * @{ + */ +#define EFM_CACHERST_ON (EFM_FRMC_CRST) /*!< Enable data cache reset function */ +#define EFM_CACHERST_OFF (0x0UL) /*!< Disable data cache reset function */ +/** + * @} + */ + +/** + * @defgroup EFM_Prefetch_Func EFM prefetch function + * @{ + */ +#define EFM_PREFETCH_ON (EFM_FRMC_PREFE) /*!< Enable prefetch function */ +#define EFM_PREFETCH_OFF (0x0UL) /*!< Disable prefetch function */ +/** + * @} + */ + +/** + * @defgroup EFM_DCache_Func EFM data cache function + * @{ + */ +#define EFM_DATACACHE_ON (EFM_FRMC_DCACHE) /*!< Enable data cache function */ +#define EFM_DATACACHE_OFF (0x0UL) /*!< Disable data cache function */ +/** + * @} + */ + +/** + * @defgroup EFM_INSCache_Func EFM instruction cache function + * @{ + */ +#define EFM_INSCACHE_ON (EFM_FRMC_ICACHE) /*!< Enable instruction cache function */ +#define EFM_INSCACHE_OFF (0x0UL) /*!< Disable instruction cache function */ +/** + * @} + */ + +/** + * @defgroup EFM_LowVolRead_Mode EFM read of low-voltage mode + * @{ + */ +#define EFM_LOWVOLREAD_ON (EFM_FRMC_LVM) /*!< Read of low-voltage mode */ +#define EFM_LOWVOLREAD_OFF (0x0UL) +/** + * @} + */ + +/** + * @defgroup EFM_Key2Lock_Status EFM key2 lock status + * @{ + */ +#define EFM_KEY2_LOCK (EFM_FWMC_KEY2LOCK) +#define EFM_KEY2_UNLOCK (0x0UL) +/** + * @} + */ + +/** + * @defgroup EFM_Key1Lock_Status EFM key1 lock status + * @{ + */ +#define EFM_KEY1_LOCK (EFM_FWMC_KEY1LOCK) +#define EFM_KEY1_UNLOCK (0x0UL) +/** + * @} + */ + +/** + * @defgroup EFM_Bus_Status EFM Bus status while flash program or erase + * @{ + */ +#define EFM_BUS_BUSY (0x0UL) /*!< Bus busy while flash program or erase */ +#define EFM_BUS_RELEASE (EFM_FWMC_BUSHLDCTL) /*!< Bus release while flash program or erase */ +/** + * @} + */ + +/** + * @defgroup EFM_OperateMode_Definition EFM program or erase mode definition + * @{ + */ +#define EFM_MODE_PROGRAMSINGLE (0x1UL) /*!< Program single mode */ +#define EFM_MODE_PROGRAMREADBACK (0x2UL) /*!< Program and read back mode */ +#define EFM_MODE_PROGRAMSEQUENCE (0x3UL) /*!< Program sequence mode */ +#define EFM_MODE_ERASESECTOR (0x4UL) /*!< Sector erase mode */ +#define EFM_MODE_ERASECHIP1 (0x5UL) /*!< A flash Chip erase mode */ +#define EFM_MODE_ERASEFULL (0x6UL) /*!< Full erase mode */ +#define EFM_MODE_READONLY (0x0UL) /*!< Read only mode */ +/** + * @} + */ + +/** + * @defgroup EFM_Flag_definition EFM Flag definition + * @{ + */ +#define EFM_FLAG_OTPWERR0 (EFM_FSR_OTPWERR0) /*!< EFM Flash0 otp Programming/erase error flag. */ +#define EFM_FLAG_PRTWERR0 (EFM_FSR_PRTWERR0) /*!< EFM Flash0 write protect address error flag. */ +#define EFM_FLAG_PGSZERR0 (EFM_FSR_PGSZERR0) /*!< EFM Flash0 programming size error flag. */ +#define EFM_FLAG_MISMTCH0 (EFM_FSR_MISMTCH0) /*!< EFM Flash0 programming missing match error flag. */ +#define EFM_FLAG_OPTEND0 (EFM_FSR_OPTEND0) /*!< EFM Flash0 end of operation flag. */ +#define EFM_FLAG_CLOLERR0 (EFM_FSR_COLERR0) /*!< EFM Flash0 read collide error flag. */ +#define EFM_FLAG_RDY0 (EFM_FSR_RDY0) /*!< EFM Flash0 ready flag. */ +#define EFM_FLAG_PRTWERR1 (EFM_FSR_PRTWERR1) /*!< EFM Flash1 write protect address error flag. */ +#define EFM_FLAG_PGSZERR1 (EFM_FSR_PGSZERR1) /*!< EFM Flash1 programming size error flag. */ +#define EFM_FLAG_MISMTCH1 (EFM_FSR_MISMTCH1) /*!< EFM Flash1 programming missing match error flag. */ +#define EFM_FLAG_OPTEND1 (EFM_FSR_OPTEND1) /*!< EFM Flash1 end of operation flag. */ +#define EFM_FLAG_CLOLERR1 (EFM_FSR_COLERR1) /*!< EFM Flash1 read collide error flag. */ +#define EFM_FLAG_RDY1 (EFM_FSR_RDY1) /*!< EFM Flash1 ready flag. */ + +#define EFM_FLAG_CLR_OTPWERR0 (EFM_FSCLR_OTPWERRCLR0) /*!< EFM Clear Flash0 otp Programming/erase error flag. */ +#define EFM_FLAG_CLR_PRTWERR0 (EFM_FSCLR_PRTWERRCLR0) /*!< EFM Clear Flash0 write protect address error flag. */ +#define EFM_FLAG_CLR_PGSZERR0 (EFM_FSCLR_PGSZERRCLR0) /*!< EFM Clear Flash0 programming size error flag. */ +#define EFM_FLAG_CLR_MISMTCH0 (EFM_FSCLR_MISMTCHCLR0) /*!< EFM Clear Flash0 programming miss match error flag.*/ +#define EFM_FLAG_CLR_OPTEND0 (EFM_FSCLR_OPTENDCLR0) /*!< EFM Clear Flash0 end of operation flag. */ +#define EFM_FLAG_CLR_CLOLERR0 (EFM_FSCLR_COLERRCLR0) /*!< EFM Clear Flash0 read collide error flag. */ +#define EFM_FLAG_CLR_PRTWERR1 (EFM_FSCLR_PRTWERRCLR1) /*!< EFM Clear Flash1 write protect address error flag. */ +#define EFM_FLAG_CLR_PGSZERR1 (EFM_FSCLR_PGSZERRCLR1) /*!< EFM Clear Flash1 programming size error flag. */ +#define EFM_FLAG_CLR_MISMTCH1 (EFM_FSCLR_MISMTCHCLR1) /*!< EFM Clear Flash1 programming miss match error flag.*/ +#define EFM_FLAG_CLR_OPTEND1 (EFM_FSCLR_OPTENDCLR1) /*!< EFM Clear Flash1 end of operation flag. */ +#define EFM_FLAG_CLR_CLOLERR1 (EFM_FSCLR_COLERRCLR1) /*!< EFM Clear Flash1 read collide error flag. */ +/** + * @} + */ + +/** + * @defgroup EFM_Interrupt_definition EFM Interrupt definition + * @{ + */ +#define EFM_INT_PEERR (EFM_FITE_PEERRITE) /*!< Program/erase error Interrupt source */ +#define EFM_INT_OPTEND (EFM_FITE_OPTENDITE) /*!< End of EFM operation Interrupt source */ +#define EFM_INT_RDCOLERR (EFM_FITE_COLERRITE) /*!< Read collide error Interrupt source */ + +#define EFM_INT_MASK (EFM_FITE_PEERRITE | \ + EFM_FITE_OPTENDITE | \ + EFM_FITE_COLERRITE) /*!< Program/erase error and End of EFM operation \ + and Read collide error Interrupt source */ +/** + * @} + */ + +/** + * @defgroup EFM_WriteLock_Definition EFM Write protect lock definition + * @{ + */ +#define EFM_WRLOCK0 (EFM_WLOCK_WLOCK0) /*!< F0NWPRT0 controlled sector lock */ +#define EFM_WRLOCK1 (EFM_WLOCK_WLOCK1) /*!< F0NWPRT1 controlled sector lock */ +#define EFM_WRLOCK2 (EFM_WLOCK_WLOCK2) /*!< F0NWPRT2 controlled sector lock */ +#define EFM_WRLOCK3 (EFM_WLOCK_WLOCK3) /*!< F0NWPRT3 controlled sector lock */ +#define EFM_WRLOCK4 (EFM_WLOCK_WLOCK4) /*!< F1NWPRT0 controlled sector lock */ +#define EFM_WRLOCK5 (EFM_WLOCK_WLOCK5) /*!< F1NWPRT1 controlled sector lock */ +#define EFM_WRLOCK6 (EFM_WLOCK_WLOCK6) /*!< F1NWPRT2 controlled sector lock */ +#define EFM_WRLOCK7 (EFM_WLOCK_WLOCK7) /*!< F1NWPRT3 controlled sector lock */ +/** + * @} + */ + + +/** + * @defgroup EFM_Keys EFM Keys + * @{ + */ +#define EFM_SECRET_KEY1 (0x0123U) +#define EFM_SECRET_KEY2 (0x3210U) +/** + * @} + */ + +/** + * @defgroup EFM_Status EFM Status + * @{ + */ +#define EFM_FLASH0_ACT_FLASH1_ACT (0x00000000UL) /*!< Flash 0 and 1 activity */ +#define EFM_FLASH0_STP_FLASH1_ACT (0x00000001UL) /*!< Flash 0 stop,Flash 1 activity */ +#define EFM_FLASH0_ACT_FLASH1_STP (0x00000002UL) /*!< Flash 0 activity,Flash 1 stop */ +#define EFM_FLASH0_STP_FLASH1_STP (0x00000003UL) /*!< Flash 0 and 1 stop */ +/** + * @} + */ + +/** + * @defgroup EFM_ProtectReg_definition EFM Write protect for register definition + * @{ + */ +#define EFM_PROTECT_FWMC (0U) +#define EFM_PROTECT_OTP (1U) +/** + * @} + */ + + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EFM_Global_Functions + * @{ + */ + +/** + * @brief EFM Protect Unlock. + * @param None + * @retval None + */ + +__STATIC_INLINE void EFM_Unlock(void) +{ + WRITE_REG16(M4_EFM->FAPRT, EFM_SECRET_KEY1); + WRITE_REG16(M4_EFM->FAPRT, EFM_SECRET_KEY2); +} + +/** + * @brief EFM Protect Lock. + * @param None + * @retval None + */ +__STATIC_INLINE void EFM_Lock(void) +{ + WRITE_REG16(M4_EFM->FAPRT, 0x1111U); +} + +void EFM_FWMC_Unlock(void); +void EFM_FWMC_Lock(void); +void EFM_OTP_WP_Unlock(void); +void EFM_OTP_WP_Lock(void); + +void EFM_Cmd(uint32_t u32EfmStatus); +void EFM_SetWaitCycle(uint32_t u32WaitCycle); +void EFM_SetBusStatus(uint32_t u32Status); +void EFM_DataCacheCmd(en_functional_state_t enNewState); +void EFM_InsCacheCmd(en_functional_state_t enNewState); +void EFM_DataCacheRstCmd(en_functional_state_t enNewState); +void EFM_PrefetchCmd(en_functional_state_t enNewState); +void EFM_InterruptCmd(uint32_t u32EfmInt, en_functional_state_t enNewState); +void EFM_LowVolReadCmd(en_functional_state_t enNewState); +void EFM_SectorRegLock(uint32_t u32EfmRegLock); +void EFM_ClearFlag(uint32_t u32Flag); +void EFM_SectorCmd_Single(uint8_t u8SectorNum, en_functional_state_t enNewState); +en_result_t EFM_StructInit(stc_efm_cfg_t *pstcEfmCfg); +en_result_t EFM_Init(const stc_efm_cfg_t *pstcEfmCfg); +en_result_t EFM_SectorCmd_Sequential(uint32_t u32StartAddr, uint16_t u16SectorCnt, + en_functional_state_t enNewState); +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_ProgramReadBack(uint32_t u32Addr, uint32_t u32Data); +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, const uint32_t *pu32Buf); +en_result_t EFM_SectorErase(uint32_t u32Addr); +en_result_t EFM_OTPLock(uint32_t u32Addr); +en_result_t EFM_ChipErase(uint32_t EraseMode, uint32_t u32Addr); +en_result_t EFM_SwapCmd(en_functional_state_t enNewState); +en_result_t EFM_SetOperateMode(uint32_t u32PgmMode); + +en_flag_status_t EFM_GetFlagStatus(uint32_t u32Flag); +void EFM_GetUID(stc_efm_unique_id_t *stcUID); +uint32_t EFM_GetCID(void); +/** + * @} + */ + +#endif /* DDL_EFM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_EFM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_emb.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_emb.h new file mode 100644 index 0000000000000000000000000000000000000000..0091cb9fff64cd1a338948067d1f1343b1c1005f --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_emb.h @@ -0,0 +1,722 @@ +/** + ******************************************************************************* + * @file hc32f4a0_emb.h + * @brief This file contains all the functions prototypes of the EMB + * (Emergency Brake) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-07 Hongjh 1. Modify structure member comments for + stc_emb_monitor_port_t/stc_emb_monitor_tmr_pwm_t + 2. Replace the word Timer with TMR abbreviation + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_EMB_H__ +#define __HC32F4A0_EMB_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_EMB + * @{ + */ + +#if (DDL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Types EMB Global Types + * @{ + */ + +/** + * @brief EMB monitor EMB port configuration + */ +typedef struct +{ + uint32_t u32PortSel; /*!< Enable or disable EMB detect port in control function + This parameter can be a value of EMB_Portx_Selection(x=1~4) */ + + uint32_t u32PortLevel; /*!< EMB detect port level + This parameter can be a value of EMB_Detect_Portx_Level(x=1~4) */ + + uint32_t u32PortFilterDiv; /*!< EMB port filter division + This parameter can be a value of EMB_Portx_Filter_Clock_Division(x=1~4) */ +} stc_emb_monitor_port_t; + +/** + * @brief EMB monitor TMR4 or TMR6 PWM configuration + */ +typedef struct +{ + uint32_t u32PwmSel; /*!< Enable or disable EMB detect TMR4/6 PWM x channel same phase function + This parameter can be a value of EMB_TMR4_PWM_x_Selection(x=U/V/W) or + EMB_TMR6_x_PWM_Selection(x=1~8) */ + + uint32_t u32PwmLevel; /*!< Detect TMR4/6 PWM x channel polarity level + This parameter can be a value of EMB_Detect_TMR4_PWM_x_Level(x=U/V/W) or + EMB_Detect_TMR6_x_PWM_Level(x=1~8) */ +} stc_emb_monitor_tmr_pwm_t; + +/** + * @brief EMB control TMR4 initialization configuration + */ +typedef struct +{ + uint32_t u32Cmp1; /*!< Enable or disable EMB detect CMP1 result function + This parameter can be a value of @ref EMB_CMP1_Selection */ + + uint32_t u32Cmp2; /*!< Enable or disable EMB detect CMP2 result function + This parameter can be a value of @ref EMB_CMP2_Selection */ + + uint32_t u32Cmp3; /*!< Enable or disable EMB detect CMP3 result function + This parameter can be a value of @ref EMB_CMP3_Selection */ + + uint32_t u32Cmp4; /*!< Enable or disable EMB detect CMP4 result function + This parameter can be a value of @ref EMB_CMP4_Selection */ + + uint32_t u32Osc; /*!< EMB detect OSC failure function + This parameter can be a value of @ref EMB_OSC_Stop_Selection */ + + stc_emb_monitor_port_t stcPort1; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_port_t stcPort2; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_port_t stcPort3; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_port_t stcPort4; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr4PwmU; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr4PwmV; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr4PwmW; /*!< EMB detect TMR4 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_tmr4_init_t; + +/** + * @brief EMB control TMR6 initialization configuration + */ +typedef struct +{ + uint32_t u32Cmp1; /*!< Enable or disable EMB detect CMP1 result function + This parameter can be a value of @ref EMB_CMP1_Selection */ + + uint32_t u32Cmp2; /*!< Enable or disable EMB detect CMP2 result function + This parameter can be a value of @ref EMB_CMP2_Selection */ + + uint32_t u32Cmp3; /*!< Enable or disable EMB detect CMP3 result function + This parameter can be a value of @ref EMB_CMP3_Selection */ + + uint32_t u32Cmp4; /*!< Enable or disable EMB detect CMP4 result function + This parameter can be a value of @ref EMB_CMP4_Selection */ + + uint32_t u32Osc; /*!< EMB detect OSC failure function + This parameter can be a value of @ref EMB_OSC_Stop_Selection */ + + stc_emb_monitor_port_t stcPort1; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_port_t stcPort2; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_port_t stcPort3; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_port_t stcPort4; /*!< EMB detect port EMBIN1 function + This parameter details refer @ref stc_emb_monitor_port_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_1; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_2; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_3; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_4; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_5; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_6; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_7; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ + + stc_emb_monitor_tmr_pwm_t stcTmr6_8; /*!< EMB detect TMR6 function + This parameter details refer @ref stc_emb_monitor_tmr_pwm_t structure */ +} stc_emb_tmr6_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Global_Macros EMB Global Macros + * @{ + */ + +/** + * @defgroup EMB_CMP1_Selection EMB CMP1 Selection + * @{ + */ +#define EMB_CMP1_DISABLE (0UL) +#define EMB_CMP1_ENABLE (EMB_CTL1_CMPEN_0) +/** + * @} + */ + +/** + * @defgroup EMB_CMP2_Selection EMB CMP2 Selection + * @{ + */ +#define EMB_CMP2_DISABLE (0UL) +#define EMB_CMP2_ENABLE (EMB_CTL1_CMPEN_1) +/** + * @} + */ + +/** + * @defgroup EMB_CMP3_Selection EMB CMP3 Selection + * @{ + */ +#define EMB_CMP3_DISABLE (0UL) +#define EMB_CMP3_ENABLE (EMB_CTL1_CMPEN_2) +/** + * @} + */ + +/** + * @defgroup EMB_CMP4_Selection EMB CMP4 Selection + * @{ + */ +#define EMB_CMP4_DISABLE (0UL) +#define EMB_CMP4_ENABLE (EMB_CTL1_CMPEN_3) +/** + * @} + */ + +/** + * @defgroup EMB_OSC_Stop_Selection EMB OSC Stop Selection + * @{ + */ +#define EMB_OSC_DISABLE (0UL) +#define EMB_OSC_ENABLE (EMB_CTL1_OSCSTPEN) +/** + * @} + */ + +/** + * @defgroup EMB_TMR4_PWM_W_Selection EMB TMR4 PWM W Selection + * @{ + */ +#define EMB_TMR4_PWM_W_DISABLE (0UL) +#define EMB_TMR4_PWM_W_ENABLE (EMB_CTL1_PWMSEN_0) +/** + * @} + */ + +/** + * @defgroup EMB_TMR4_PWM_V_Selection EMB TMR4 PWM V Selection + * @{ + */ +#define EMB_TMR4_PWM_V_DISABLE (0UL) +#define EMB_TMR4_PWM_V_ENABLE (EMB_CTL1_PWMSEN_1) +/** + * @} + */ + +/** + * @defgroup EMB_TMR4_PWM_U_Selection EMB TMR4 PWM U Selection + * @{ + */ +#define EMB_TMR4_PWM_U_DISABLE (0UL) +#define EMB_TMR4_PWM_U_ENABLE (EMB_CTL1_PWMSEN_2) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_1_PWM_Selection EMB TMR6_1 PWM Selection + * @{ + */ +#define EMB_TMR6_1_PWM_DISABLE (0UL) +#define EMB_TMR6_1_PWM_ENABLE (EMB_CTL1_PWMSEN_0) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_2_PWM_Selection EMB TMR6_2 PWM Selection + * @{ + */ +#define EMB_TMR6_2_PWM_DISABLE (0UL) +#define EMB_TMR6_2_PWM_ENABLE (EMB_CTL1_PWMSEN_1) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_3_PWM_Selection EMB TMR6_3 PWM Selection + * @{ + */ +#define EMB_TMR6_3_PWM_DISABLE (0UL) +#define EMB_TMR6_3_PWM_ENABLE (EMB_CTL1_PWMSEN_2) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_4_PWM_Selection EMB TMR6_4 PWM Selection + * @{ + */ +#define EMB_TMR6_4_PWM_DISABLE (0UL) +#define EMB_TMR6_4_PWM_ENABLE (EMB_CTL1_PWMSEN_3) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_5_PWM_Selection EMB TMR6_5 PWM Selection + * @{ + */ +#define EMB_TMR6_5_PWM_DISABLE (0UL) +#define EMB_TMR6_5_PWM_ENABLE (EMB_CTL1_PWMSEN_4) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_6_PWM_Selection EMB TMR6_6 PWM Selection + * @{ + */ +#define EMB_TMR6_6_PWM_DISABLE (0UL) +#define EMB_TMR6_6_PWM_ENABLE (EMB_CTL1_PWMSEN_5) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_7_PWM_Selection EMB TMR6_7 PWM Selection + * @{ + */ +#define EMB_TMR6_7_PWM_DISABLE (0UL) +#define EMB_TMR6_7_PWM_ENABLE (EMB_CTL1_PWMSEN_6) +/** + * @} + */ + +/** + * @defgroup EMB_TMR6_8_PWM_Selection EMB TMR6_8 PWM Selection + * @{ + */ +#define EMB_TMR6_8_PWM_DISABLE (0UL) +#define EMB_TMR6_8_PWM_ENABLE (EMB_CTL1_PWMSEN_7) +/** + * @} + */ + +/** + * @defgroup EMB_Port1_Selection EMB Port1 Selection + * @{ + */ +#define EMB_PORT1_ENABLE (EMB_CTL1_PORTINEN1) +#define EMB_PORT1_DISABLE (0UL) +/** + * @} + */ + +/** + * @defgroup EMB_Port2_Selection EMB Port2 Selection + * @{ + */ +#define EMB_PORT2_ENABLE (EMB_CTL1_PORTINEN2) +#define EMB_PORT2_DISABLE (0UL) +/** + * @} + */ + +/** + * @defgroup EMB_Port3_Selection EMB Port3 Selection + * @{ + */ +#define EMB_PORT3_ENABLE (EMB_CTL1_PORTINEN3) +#define EMB_PORT3_DISABLE (0UL) +/** + * @} + */ + +/** + * @defgroup EMB_Port4_Selection EMB Port4 Selection + * @{ + */ +#define EMB_PORT4_ENABLE (EMB_CTL1_PORTINEN2) +#define EMB_PORT4_DISABLE (0UL) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port1_Level EMB Detect Port1 Level + * @{ + */ +#define EMB_DETECT_PORT1_LEVEL_HIGH (0UL) +#define EMB_DETECT_PORT1_LEVEL_LOW (EMB_CTL1_INVSEL1) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port2_Level EMB Detect Port2 Level + * @{ + */ +#define EMB_DETECT_PORT2_LEVEL_HIGH (0UL) +#define EMB_DETECT_PORT2_LEVEL_LOW (EMB_CTL1_INVSEL2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port3_Level EMB Detect Port3 Level + * @{ + */ +#define EMB_DETECT_PORT3_LEVEL_HIGH (0UL) +#define EMB_DETECT_PORT3_LEVEL_LOW (EMB_CTL1_INVSEL3) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_Port4_Level EMB Detect Port4 Level + * @{ + */ +#define EMB_DETECT_PORT4_LEVEL_HIGH (0UL) +#define EMB_DETECT_PORT4_LEVEL_LOW (EMB_CTL1_INVSEL4) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR4_PWM_W_Level EMB Detect TMR4 PWM W Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_W_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_W_BOTH_HIGH (EMB_CTL2_PWMLV_0) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR4_PWM_V_Level EMB Detect TMR4 PWM V Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_V_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_V_BOTH_HIGH (EMB_CTL2_PWMLV_1) +/** + * @} + */ +/** + * @defgroup EMB_Detect_TMR4_PWM_U_Level EMB Detect TMR4 PWM U Level + * @{ + */ +#define EMB_DETECT_TMR4_PWM_U_BOTH_LOW (0UL) +#define EMB_DETECT_TMR4_PWM_U_BOTH_HIGH (EMB_CTL2_PWMLV_2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_1_PWM_Level EMB Detect TMR6_1 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_1_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_1_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_0) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_2_PWM_Level EMB Detect TMR6_2 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_2_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_2_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_1) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_3_PWM_Level EMB Detect TMR6_3 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_3_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_3_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_2) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_4_PWM_Level EMB Detect TMR6_4 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_4_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_4_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_3) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_5_PWM_Level EMB Detect TMR6_5 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_5_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_5_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_4) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_6_PWM_Level EMB Detect TMR6_6 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_6_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_6_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_5) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_7_PWM_Level EMB Detect TMR6_7 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_7_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_7_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_6) +/** + * @} + */ + +/** + * @defgroup EMB_Detect_TMR6_8_PWM_Level EMB Detect TMR6_8 PWM Level + * @{ + */ +#define EMB_DETECT_TMR6_8_PWM_BOTH_LOW (0UL) +#define EMB_DETECT_TMR6_8_PWM_BOTH_HIGH (EMB_CTL2_PWMLV_7) +/** + * @} + */ + +/** @defgroup EMB_Port1_Filter_Clock_Division EMB Port1 Filter Clock Division + * @{ + */ +#define EMB_PORT1_FILTER_NONE (0UL) +#define EMB_PORT1_FILTER_CLK_DIV1 (EMB_CTL2_NFEN1) +#define EMB_PORT1_FILTER_CLK_DIV8 (EMB_CTL2_NFEN1 | EMB_CTL2_NFSEL1_0) +#define EMB_PORT1_FILTER_CLK_DIV32 (EMB_CTL2_NFEN1 | EMB_CTL2_NFSEL1_1) +#define EMB_PORT1_FILTER_CLK_DIV128 (EMB_CTL2_NFEN1 | EMB_CTL2_NFSEL1) +/** + * @} + */ + +/** @defgroup EMB_Port2_Filter_Clock_Division EMB Port2 Filter Clock Division + * @{ + */ +#define EMB_PORT2_FILTER_NONE (0UL) +#define EMB_PORT2_FILTER_CLK_DIV1 (EMB_CTL2_NFEN2) +#define EMB_PORT2_FILTER_CLK_DIV8 (EMB_CTL2_NFEN2 | EMB_CTL2_NFSEL2_0) +#define EMB_PORT2_FILTER_CLK_DIV32 (EMB_CTL2_NFEN2 | EMB_CTL2_NFSEL2_1) +#define EMB_PORT2_FILTER_CLK_DIV128 (EMB_CTL2_NFEN2 | EMB_CTL2_NFSEL2) +/** + * @} + */ + +/** @defgroup EMB_Port3_Filter_Clock_Division EMB Port3 Filter Clock Division + * @{ + */ +#define EMB_PORT3_FILTER_NONE (0UL) +#define EMB_PORT3_FILTER_CLK_DIV1 (EMB_CTL2_NFEN3) +#define EMB_PORT3_FILTER_CLK_DIV8 (EMB_CTL2_NFEN3 | EMB_CTL2_NFSEL3_0) +#define EMB_PORT3_FILTER_CLK_DIV32 (EMB_CTL2_NFEN3 | EMB_CTL2_NFSEL3_1) +#define EMB_PORT3_FILTER_CLK_DIV128 (EMB_CTL2_NFEN3 | EMB_CTL2_NFSEL3) +/** + * @} + */ + +/** @defgroup EMB_Port4_Filter_Clock_Division EMB Port4 Filter Clock Division + * @{ + */ +#define EMB_PORT4_FILTER_NONE (0UL) +#define EMB_PORT4_FILTER_CLK_DIV1 (EMB_CTL2_NFEN4) +#define EMB_PORT4_FILTER_CLK_DIV8 (EMB_CTL2_NFEN4 | EMB_CTL2_NFSEL4_0) +#define EMB_PORT4_FILTER_CLK_DIV32 (EMB_CTL2_NFEN4 | EMB_CTL2_NFSEL4_1) +#define EMB_PORT4_FILTER_CLK_DIV128 (EMB_CTL2_NFEN4 | EMB_CTL2_NFSEL4) +/** + * @} + */ + +/** + * @defgroup EMB_Flag EMB Flag + * @{ + */ +#define EMB_FLAG_PWMS (EMB_STAT_PWMSF) +#define EMB_FLAG_CMP (EMB_STAT_CMPF) +#define EMB_FLAG_OSC (EMB_STAT_OSF) +#define EMB_FLAG_PORT1 (EMB_STAT_PORTINF1) +#define EMB_FLAG_PORT2 (EMB_STAT_PORTINF2) +#define EMB_FLAG_PORT3 (EMB_STAT_PORTINF3) +#define EMB_FLAG_PORT4 (EMB_STAT_PORTINF4) +/** + * @} + */ + +/** + * @defgroup EMB_State EMB State + * @{ + */ +#define EMB_STATE_PWMS (EMB_STAT_PWMST) +#define EMB_STATE_CMP (EMB_STAT_CMPST) +#define EMB_STATE_OSC (EMB_STAT_OSST) +#define EMB_STATE_PORT1 (EMB_STAT_PORTINST1) +#define EMB_STATE_PORT2 (EMB_STAT_PORTINST2) +#define EMB_STATE_PORT3 (EMB_STAT_PORTINST3) +#define EMB_STATE_PORT4 (EMB_STAT_PORTINST4) +/** + * @} + */ + +/** + * @defgroup EMB_Interrupt EMB Interrupt + * @{ + */ +#define EMB_INT_PWMS (EMB_INTEN_PWMSINTEN) +#define EMB_INT_CMP (EMB_INTEN_CMPINTEN) +#define EMB_INT_OSC (EMB_INTEN_OSINTEN) +#define EMB_INT_PORT1 (EMB_INTEN_PORTINTEN1) +#define EMB_INT_PORT2 (EMB_INTEN_PORTINTEN2) +#define EMB_INT_PORT3 (EMB_INTEN_PORTINTEN3) +#define EMB_INT_PORT4 (EMB_INTEN_PORTINTEN4) +/** + * @} + */ + +/** + * @defgroup EMB_Release_TMR_PWM_Selection EMB Release TMR PWM Selection + * @{ + */ +#define EMB_RELEASE_PWM_SEL_FLAG_ZERO (0UL) +#define EMB_RELEASE_PWM_SEL_STATE_ZERO (1UL) +/** + * @} + */ + +/** + * @defgroup EMB_Monitor_Event EMB Monitor Event + * @{ + */ +#define EMB_EVENT_PWMS (EMB_RLSSEL_PWMRSEL) +#define EMB_EVENT_CMP (EMB_RLSSEL_CMPRSEL) +#define EMB_EVENT_OSC (EMB_RLSSEL_OSRSEL) +#define EMB_EVENT_PORT1 (EMB_RLSSEL_PORTINRSEL1) +#define EMB_EVENT_PORT2 (EMB_RLSSEL_PORTINRSEL2) +#define EMB_EVENT_PORT3 (EMB_RLSSEL_PORTINRSEL3) +#define EMB_EVENT_PORT4 (EMB_RLSSEL_PORTINRSEL4) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EMB_Global_Functions + * @{ + */ +en_result_t EMB_Tmr4Init(M4_EMB_TypeDef *EMBx, + const stc_emb_tmr4_init_t *pstcInit); +en_result_t EMB_Tmr4StructInit(stc_emb_tmr4_init_t *pstcInit); +en_result_t EMB_Tmr6Init(M4_EMB_TypeDef *EMBx, + const stc_emb_tmr6_init_t *pstcInit); +en_result_t EMB_Tmr6StructInit(stc_emb_tmr6_init_t *pstcInit); +void EMB_DeInit(M4_EMB_TypeDef *EMBx); +void EMB_IntCmd(M4_EMB_TypeDef *EMBx, + uint32_t u32IntSource, + en_functional_state_t enNewState); +void EMB_SetReleasePwmMode(M4_EMB_TypeDef *EMBx, + uint32_t u32Event, + uint32_t u32Mode); +en_flag_status_t EMB_GetFlag(const M4_EMB_TypeDef *EMBx, uint32_t u32Flag); +void EMB_ClearFlag(M4_EMB_TypeDef *EMBx, uint32_t u32Flag); +en_flag_status_t EMB_GetStatus(const M4_EMB_TypeDef *EMBx, + uint32_t u32Status); +void EMB_SwBrake(M4_EMB_TypeDef *EMBx, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* DDL_EMB_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_EMB_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_eth.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_eth.h new file mode 100644 index 0000000000000000000000000000000000000000..0a127f79b22d2f05e570a15775c9139c53557473 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_eth.h @@ -0,0 +1,2506 @@ +/** + ******************************************************************************* + * @file hc32f4a0_eth.h + * @brief This file contains all the Macro Definitions of the ETH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-07-03 Yangjp Optimize stc_eth_mac_init_t structure + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_ETH_H__ +#define __HC32F4A0_ETH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_ETH + * @{ + */ + +#if (DDL_ETH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup ETH_Global_Types ETH Global Types + * @{ + */ + +/** + * @brief ETH Common Initialization Structure Definition + */ +typedef struct +{ + uint16_t u16AutoNegotiation; /*!< Specifies the Auto Negotiation mode for the external PHY. + This parameter can be a value of @ref ETH_Auto_Negotiation */ + + uint16_t u16PHYAddress; /*!< Specifies the Ethernet PHY address. + This parameter must be a number between Min_Data = 0 and Max_Data = 31 */ + + uint8_t au8MACAddr[6]; /*!< Specifies the MAC Address of used Hardware */ + + uint32_t u32MediaInterface; /*!< Specifies the media interface. + This parameter can be a value of @ref ETH_Media_Interface */ + + uint32_t u32Speed; /*!< Specifies the Ethernet speed. + This parameter can be a value of @ref ETH_Speed */ + + uint32_t u32DuplexMode; /*!< Specifies the MAC duplex mode. + This parameter can be a value of @ref ETH_Duplex_Mode */ + + uint32_t u32ChecksumMode; /*!< Specifies the checksum check by hardware or by software. + This parameter can be a value of @ref ETH_Checksum_Mode */ + + uint32_t u32RxMode; /*!< Specifies the Ethernet Rx mode. + This parameter can be a value of @ref ETH_Rx_Mode */ +} stc_eth_comm_init_t; + +/** + * @brief ETH MAC Initialization Structure Definition + */ +typedef struct +{ + uint32_t u32TxClkPolarity; /*!< Specifies the Tx clock polarity. + This parameter can be a value of @ref ETH_TX_CLK_POLARITY */ + + uint32_t u32RxRefClkPolarity; /*!< Specifies the Rx/Ref clock polarity. + This parameter can be a value of @ref ETH_RX_REF_CLK_POLARITY */ + + uint32_t u32SAInsertMode; /*!< Specifies the Source Address Insert or Replace Mode. + This parameter can be a value of @ref ETH_SA_Insert_Mode */ + + uint32_t u32TypeFrameStripFCS; /*!< Specifies the validity of stripping FCS for type frame. + This parameter can be a value of @ref ETH_TypeFrame_Strip_FCS */ + + uint32_t u32Watchdog; /*!< Specifies the validity of the Watchdog timer. + This parameter can be a value of @ref ETH_Watchdog */ + + uint32_t u32Jabber; /*!< Specifies the validity of the Jabber timer. + This parameter can be a value of @ref ETH_Jabber */ + + uint32_t u32InterFrameGap; /*!< Specifies the minimum gap between frames during transmission. + This parameter can be a value of @ref ETH_Inter_Frame_Gap */ + + uint32_t u32CarrierSense; /*!< Specifies the validity of the Carrier Sense (Half-Duplex mode). + This parameter can be a value of @ref ETH_Carrier_Sense */ + + uint32_t u32ReceiveOwn; /*!< Specifies the validity of the Receive Own (Half-Duplex mode). + This parameter can be a value of @ref ETH_Receive_Own */ + + uint32_t u32ChecksumOffload; /*!< Specifies the validity of the IPv4 checksum Offload. + This parameter can be a value of @ref ETH_Checksum_Offload */ + + uint32_t u32RetryTransmit; /*!< Specifies the validity of the MAC attempt to retry Transmit (Half-Duplex mode). + This parameter can be a value of @ref ETH_Retry_Transmit */ + + uint32_t u32AutoStripPadFCS; /*!< Specifies the validity of the Automatic Stripping Pad/FCS of MAC. + This parameter can be a value of @ref ETH_Auto_Strip_Pad_FCS */ + + uint32_t u32BackOffLimit; /*!< Specifies the BackOff limit value (Half-Duplex mode). + This parameter can be a value of @ref ETH_Back_Off_Limit */ + + uint32_t u32DeferralCheck; /*!< Specifies the validity of the deferral check (Half-Duplex mode). + This parameter can be a value of @ref ETH_Deferral_Check */ + + uint16_t u16PauseTime; /*!< Specifies the Pause Time in the transmit control frame. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + + uint32_t u32ZeroQuantaPause; /*!< Specifies the validity of the automatic generation Zero-Quanta Pause Control frame. + This parameter can be a value of @ref ETH_Zero_Quanta_Pause */ + + uint32_t u32PauseLowThreshold; /*!< Specifies the PAUSE Frame threshold. + This parameter can be a value of @ref ETH_Pause_Low_Threshold */ + + uint32_t u32UnicastPauseFrameDetect; /*!< Specifies the validity of the detection unicast Pause frame. + This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */ + + uint32_t u32ReceiveFlowControl; /*!< Specifies the validity of the decoding function that receive Pause frame. + This parameter can be a value of @ref ETH_Receive_Flow_Control */ + + uint32_t u32TransmitFlowControl; /*!< Specifies the validity of the MAC transmit Pause frame (Full-Duplex mode) or the MAC back-pressure operation (Half-Duplex mode). + This parameter can be a value of @ref ETH_Transmit_Flow_Control */ + + uint32_t u32ReceiveAll; /*!< Specifies the validity of the all frames reception by the MAC (No filtering). + This parameter can be a value of @ref ETH_Receive_All */ + + uint32_t u32DropNotTcpUdp; /*!< Specifies the validity of Dropping all IP datagram without TCP/UDP field. + This parameter can be a value of @ref ETH_Drop_Not_TcpUdp */ + + uint32_t u32VlanTagFilter; /*!< Specifies the validity of the VLAN Tag Filter. + This parameter can be a value of @ref ETH_VLAN_Tag_Filter */ + + uint32_t u32SAFilter; /*!< Specifies the Source Address Filter mode. + This parameter can be a value of @ref ETH_Source_Addr_Filter */ + + uint32_t u32PassControlFrame; /*!< Specifies the forwarding mode of the control frame. + This parameter can be a value of @ref ETH_Pass_Control_Frame */ + + uint32_t u32BroadcastFrameReception; /*!< Specifies the validity of the reception Broadcast Frame. + This parameter can be a value of @ref ETH_Broadcast_Frame_Reception */ + + uint32_t u32DAFilter; /*!< Specifies the destination filter mode for both unicast and multicast frame. + This parameter can be a value of @ref ETH_Destination_Addr_Filter */ + + uint32_t u32MulticastFrameFilter; /*!< Specifies the Multicast Frame filter mode. + This parameter can be a value of @ref ETH_Multicast_Frame_Filter */ + + uint32_t u32UnicastFrameFilter; /*!< Specifies the Unicast Frame filter mode. + This parameter can be a value of @ref ETH_Unicast_Frame_Filter */ + + uint32_t u32PromiscuousMode; /*!< Specifies the validity of the Promiscuous Mode. + This parameter can be a value of @ref ETH_Promiscuous_Mode */ + + uint32_t u32HashTableHigh; /*!< Specifies the higher 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t u32HashTableLow; /*!< Specifies the lower 32 bits of Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t u32TxVlanInsertMode; /*!< Specifies the VLAN insert mode in Transmit frame. + This parameter can be a value of @ref ETH_Tx_VLAN_Insert_Mode */ + + uint16_t u16TxVlanTag; /*!< Specifies the VLAN tag value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + + uint32_t u32RxVlanFilter; /*!< Specifies the VLAN filter mode in Receive frame. + This parameter can be a value of @ref ETH_Rx_VLAN_Filter */ + + uint32_t u32RxVlanComparison; /*!< Specifies the bits for comparison VLAN tag. + This parameter can be a value of @ref ETH_Rx_VLAN_Comparison */ + + uint16_t u16RxVlanTag; /*!< Specifies the VLAN tag value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + + uint16_t u16RxVlanHashTable; /*!< Specifies the lower 16 bits of VLAN Hash table. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ +} stc_eth_mac_init_t; + +/** + * @brief ETH DMA Initialization Structure Definition + */ +typedef struct +{ + uint32_t u32BurstMode; /*!< Specifies the AHB Master interface burst transmission Mode. + This parameter can be a value of @ref ETH_Burst_Mode */ + + uint32_t u32AddressAlign; /*!< Specifies the validity of the Address Align. + This parameter can be a value of @ref ETH_Address_Align */ + + uint32_t u32RxDMABurstLength; /*!< Specifies the maximum number of beats to be transferred in one Rx DMA transaction. + This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */ + + uint32_t u32TxDMABurstLength; /*!< Specifies the maximum number of beats to be transferred in one Tx DMA transaction. + This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */ + + uint32_t u32EnhanceDescriptor; /*!< Specifies the validity of the enhance descriptor format. + This parameter can be a value of @ref ETH_DMA_Enhance_Descriptor */ + + uint32_t u32DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchain descriptors (Ring mode) + This parameter must be a number between Min_Data = 0 and Max_Data = 31 */ + + uint32_t u32DMAArbitration; /*!< Specifies the DMA Tx/Rx arbitration. + This parameter can be a value of @ref ETH_DMA_Arbitration */ + + uint32_t u32DropChecksumErrorFrame; /*!< Specifies the validity of Dropping TCP/IP Checksum Error Frame. + This parameter can be a value of @ref ETH_Drop_TCPIP_Checksum_Error_Frame */ + + uint32_t u32ReceiveStoreForward; /*!< Specifies the validity of the Receive store and forward mode. + This parameter can be a value of @ref ETH_Receive_Store_Forward */ + + uint32_t u32FlushReceiveFrame; /*!< Specifies the validity of the flushing receive frame. + This parameter can be a value of @ref ETH_Flush_Receive_Frame */ + + uint32_t u32TransmitStoreForward; /*!< Specifies the validity of the Transmit store and forward mode. + This parameter can be a value of @ref ETH_Transmit_Store_Forward */ + + uint32_t u32TransmitThreshold; /*!< Specifies the Transmit Threshold. + This parameter can be a value of @ref ETH_Transmit_Threshold */ + + uint32_t u32ForwardErrorFrame; /*!< Specifies the validity of the forward erroneous frame. + This parameter can be a value of @ref ETH_Forward_Error_Frame */ + + uint32_t u32ForwardUndersizeGoodFrame; /*!< Specifies the validity of the Rx FIFO to forward Undersize frame. + This parameter can be a value of @ref ETH_Forward_Undersize_Good_Frame */ + + uint32_t u32DropJumboFrame; /*!< Specifies the validity of Dropping jumbo Frame. + This parameter can be a value of @ref ETH_Drop_Jumbo_Frame */ + + uint32_t u32ReceiveThreshold; /*!< Specifies the threshold level of the Receive FIFO. + This parameter can be a value of @ref ETH_Receive_Threshold */ + + uint32_t u32SecondFrameOperate; /*!< Specifies the validity of the Operate on second frame mode. + This parameter can be a value of @ref ETH_Second_Frame_Operate */ +} stc_eth_dma_init_t; + +/** + * @brief ETH MMC Initialization Structure Definition + */ +typedef struct +{ + uint32_t u32PresetMode; /*!< Specifies the MMC Counter preset mode. + This parameter can be a value of @ref ETH_MMC_Counter_Preset_Mode */ + + uint32_t u32ReadReset; /*!< Specifies the validity of the MMC Reset on read. + This parameter can be a value of @ref ETH_MMC_Read_Reset */ + + uint32_t u32ReloadMode; /*!< Specifies the validity of the MMC Counter reload. + This parameter can be a value of @ref ETH_MMC_Counter_Reload */ +} stc_eth_mmc_init_t; + +/** + * @brief ETH PTP Initialization Structure Definition + */ +typedef struct +{ + uint32_t u32DAFilter; /*!< Specifies the validity of the DA filter for the PTP frame. + This parameter can be a value of @ref ETH_PTP_Frame_DA_Filter */ + + uint32_t u32SnapDatagramType; /*!< Specifies the PTP snapshot datagram type. + This parameter can be a value of @ref ETH_PTP_Snapshot_Datagram_Type */ + + uint32_t u32SnapFrameType; /*!< Specifies the PTP snapshot frame type. + This parameter can be any combination of @ref ETH_PTP_Snapshot_Frame_Type */ + + uint32_t u32DatagramVersion; /*!< Specifies the PTP datagram version. + This parameter can be a value of @ref ETH_PTP_Datagram_Version */ + + uint32_t u32SubSecScale; /*!< Specifies the PTP Time Stamp subsecond scale. + This parameter can be a value of @ref ETH_PTP_Subsecond_Scale */ + + uint32_t u32CalibMode; /*!< Specifies the PTP Time Stamp calibration mode. + This parameter can be a value of @ref ETH_PTP_Calibration_Mode */ + + uint32_t u32IncValueBasic; /*!< Specifies the PTP Time Stamp Basic increase value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint8_t u8IncValueSubSec; /*!< Specifies the PTP Time Stamp Subsecond increase value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFF */ + + uint32_t u32InitValueSec; /*!< Specifies the PTP Time Stamp Second Initial value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t u32InitValueSubSec; /*!< Specifies the PTP Time Stamp Subsecond Initial value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0x7FFFFFFF */ +} stc_eth_ptp_init_t; + +/** + * @brief ETH PPS Configuration Structure Definition + */ +typedef struct +{ + uint32_t u32TargetTimeFunc; /*!< Specifies the arrival time trigger the function. + This parameter can be a value of @ref ETH_PPS_Target_Time_Function */ + + uint32_t u32OutputMode; /*!< Specifies the PPS output mode. + This parameter can be a value of @ref ETH_PPS_Output_Mode */ + + uint32_t u32OutputFreq; /*!< Specifies the PPS outout frequency. + This parameter can be any combination of @ref ETH_PPS_Output_Frequency */ + + uint32_t u32TargetTimeSec; /*!< Specifies the PPS Target Time for Second. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t u32TargetTimeSubSec; /*!< Specifies the PPS Target Time for Subsecond. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0x7FFFFFFF */ +} stc_eth_pps_config_t; + +/** + * @brief ETH DMA Descriptor Structure Definition + */ +typedef struct +{ + __IO uint32_t u32ControlStatus; /*!< Control and Status */ + uint32_t u32ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */ + uint32_t u32Buffer1Addr; /*!< Buffer1 address pointer */ + uint32_t u32Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */ + /*!< Enhance Ethernet DMA Descriptors */ + __IO uint32_t u32ExtendStatus; /*!< Extend status */ + uint32_t Reserved; /*!< Reserved */ + uint32_t u32TimeStampLow; /*!< Time Stamp Low value for transmit and receive */ + uint32_t u32TimeStampHigh; /*!< Time Stamp High value for transmit and receive */ +} stc_eth_dma_desc_t; + +/** + * @brief ETH DMA Received Frame Structure Definition + */ +typedef struct +{ + stc_eth_dma_desc_t *pstcFSDesc; /*!< First Segment Rx Desc */ + stc_eth_dma_desc_t *pstcLSDesc; /*!< Last Segment Rx Desc */ + uint32_t u32SegCount; /*!< Segment count */ + uint32_t u32Length; /*!< Frame length */ + uint32_t u32Buffer; /*!< Frame buffer */ +} stc_eth_dma_rx_frame_t; + +/** + * @brief ETH Initialization Structure Definition + */ +typedef struct +{ + stc_eth_mac_init_t stcMacInit; /*!< Ethernet MAC Initialization */ + stc_eth_dma_init_t stcDmaInit; /*!< Ethernet DMA Initialization */ +} stc_eth_init_t; + +/** + * @brief ETH Handle Structure Definition + */ +typedef struct +{ + stc_eth_comm_init_t stcCommInit; /*!< ETH Common Initialization */ + stc_eth_dma_desc_t *stcRxDesc; /*!< Rx descriptor to Get */ + stc_eth_dma_desc_t *stcTxDesc; /*!< Tx descriptor to Set */ + stc_eth_dma_rx_frame_t stcRxFrame; /*!< last Rx frame */ +} stc_eth_handle_t; + +/** + * @brief ETH MAC Address Configuration Structure Definition + */ +typedef struct +{ + uint32_t u32MacAddrFilter; /*!< Specifies the MAC Address filter mode. + This parameter can be a value of @ref ETH_MAC_Address_Filter */ + + uint32_t u32MacAddrMask; /*!< Specifies the MAC Address filter Mask. + This parameter can be a value of @ref ETH_MAC_Address_Filter_Mask */ + + uint8_t au8MACAddr[6]; /*!< Specifies the MAC Address of used Hardware */ +} stc_eth_mac_addr_config_t; + +/** + * @brief ETH L3L4 Filter Configuration Structure Definition + */ +typedef struct +{ + uint32_t u32L4DestPortFilter; /*!< Specifies the L4 Destination port filter mode. + This parameter can be a value of @ref ETH_L4_Dest_Port_Filter */ + + uint32_t u32L4SourcePortFilter; /*!< Specifies the L4 Source port filter mode. + This parameter can be a value of @ref ETH_L4_Source_Port_Filter */ + + uint32_t u32L4PortFilterProtocol; /*!< Specifies the L4 protocol for port filter operation. + This parameter can be a value of @ref ETH_L4_Port_Filter_Protocol */ + + uint32_t u32L3Ipv4DAFilterMask; /*!< Specifies the L3 Destination Address filter mask in IPv4. + This parameter can be a value of @ref ETH_L3_Dest_Addr_Filter_Mask */ + + uint32_t u32L3Ipv4SAFilterMask; /*!< Specifies the L3 Source Address filter Mask in IPv4. + This parameter can be a value of @ref ETH_L3_Source_Addr_Filter_Mask */ + + uint32_t u32L3Ipv6AddrFilterMask; /*!< Specifies the L3 Destination/Source Address filter Mask in IPv6. + This parameter can be a value of @ref ETH_L3_DA_SA_Filter_Mask */ + + uint32_t u32L3DAFilter; /*!< Specifies the L3 Destination Address filter mode. + This parameter can be a value of @ref ETH_L3_Dest_Addr_Filter */ + + uint32_t u32L3SAFilter; /*!< Specifies the L3 Source Address filter mode. + This parameter can be a value of @ref ETH_L3_Source_Addr_Filter */ + + uint32_t u32L3AddrFilterProtocol; /*!< Specifies the L3 protocol for address filter operation. + This parameter can be a value of @ref ETH_L3_Addr_Filter_Protocol */ + + uint16_t u16L4DestProtFilterValue; /*!< Specifies the L4 Destination port filter value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + + uint16_t u16L4SourceProtFilterValue; /*!< Specifies the L4 Source port filter value. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */ + + uint32_t u32L3Ipv4DAFilterValue; /*!< Specifies the L3 Destination Address filter value in IPv4. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t u32L3Ipv4SAFilterValue; /*!< Specifies the L3 Source Address filter value in IPv4. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ + + uint32_t au32L3Ipv6AddrFilterValue[4]; /*!< Specifies the L3 Destination/Source Address filter value in IPv6. + This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */ +} stc_eth_l3l4_filter_config_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ETH_Global_Macros ETH Global Macros + * @{ + */ + +/** + * @defgroup ETH_Buffer_Define ETH Buffer Define + * @{ + */ +#define ETH_PACKET_MAX_SIZE (1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_PAYLOAD + ETH_CRC */ +#define ETH_HEADER (14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ +#define ETH_CRC (4U) /*!< Ethernet CRC */ +#define ETH_EXTRA (2U) /*!< Extra bytes in some cases */ +#define ETH_VLAN_TAG (4U) /*!< Optional 802.1Q VLAN Tag */ +#define ETH_MIN_PAYLOAD (46U) /*!< Ethernet minimum payload size */ +#define ETH_MAX_PAYLOAD (1500U) /*!< Ethernet maximum payload size */ +#define ETH_JUMBO_FRAME_PAYLOAD (9000U) /*!< Jumbo frame payload size */ + +/* In below are defined the size of one Ethernet driver transmit buffer ETH_TXBUF_SIZE + and the total count of the driver transmit buffers ETH_TXBUF_NUMBER. + + The configured value for ETH_TXBUF_SIZE and ETH_TXBUF_NUMBER are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Configure the transmit buffer size for each Ethernet driver */ +#ifndef ETH_TXBUF_SIZE + #define ETH_TXBUF_SIZE ETH_PACKET_MAX_SIZE +#endif + +/* Configure the number of Ethernet driver transmit buffers (in a chained linked list)*/ +#ifndef ETH_TXBUF_NUMBER + #define ETH_TXBUF_NUMBER (5U) /* 5 Tx buffers of size ETH_TXBUF_SIZE */ +#endif + +/* In below are defined the size of one Ethernet driver receive buffer ETH_RXBUF_SIZE + and the total count of the driver receive buffers ETH_RXBUF_NUMBER. + + The configured value for ETH_RXBUF_SIZE and ETH_RXBUF_NUMBER are only provided as + example, they can be reconfigured in the application layer to fit the application + needs */ + +/* Configure the receive buffer size for each Ethernet driver */ +#ifndef ETH_RXBUF_SIZE + #define ETH_RXBUF_SIZE ETH_PACKET_MAX_SIZE +#endif + +/* Configure the number of Ethernet drive receive buffers (in a chained linked list)*/ +#ifndef ETH_RXBUF_NUMBER + #define ETH_RXBUF_NUMBER (5U) /* 5 Rx buffers of size ETH_RXBUF_SIZE */ +#endif + +/** + * @} + */ + +/** + * @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor + * @{ + */ + +/* + Normal DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES0 | OWN(31) | CTRL[30:26] | TTSE(25) | CTRL[24:18] | TTSS(17) | Status[16:0] | + ----------------------------------------------------------------------------------------------- + TDES1 | CTRL[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] | + ----------------------------------------------------------------------------------------------- + TDES2 | Buffer1 Address [31:0] | + ----------------------------------------------------------------------------------------------- + TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + ----------------------------------------------------------------------------------------------- + */ + +/** + * @brief Bit definition of TDES0 register + */ +#define ETH_DMATXDESC_OWN (0x80000000UL) /*!< OWN bit */ +#define ETH_DMATXDESC_IOC (0x40000000UL) /*!< Interrupt on Completion */ +#define ETH_DMATXDESC_TLS (0x20000000UL) /*!< Transmit Last Segment */ +#define ETH_DMATXDESC_TFS (0x10000000UL) /*!< Transmit First Segment */ +#define ETH_DMATXDESC_DCRC (0x08000000UL) /*!< Disable CRC */ +#define ETH_DMATXDESC_DPAD (0x04000000UL) /*!< Disable Padding */ +#define ETH_DMATXDESC_TTSE (0x02000000UL) /*!< Transmit Time Stamp Enable */ +#define ETH_DMATXDESC_CRCR (0x01000000UL) /*!< CRC Replace Control */ +#define ETH_DMATXDESC_CIC (0x00C00000UL) /*!< Checksum Insertion Control: 4 cases */ +#define ETH_DMATXDESC_CIC_BYPASS (0x00000000UL) /*!< Do Nothing: Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CIC_IPV4HEADER (0x00400000UL) /*!< IPV4 header Checksum Insertion */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT (0x00800000UL) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL (0x00C00000UL) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +#define ETH_DMATXDESC_TER (0x00200000UL) /*!< Transmit End of Ring */ +#define ETH_DMATXDESC_TSAC (0x00100000UL) /*!< Second Address Chained */ +#define ETH_DMATXDESC_VLANC (0x000C0000UL) /*!< VLAN Insertion Control: 4 cases */ +#define ETH_DMATXDESC_VLANC_BYPASS (0x00000000UL) /*!< Do Nothing: VLAN Insertion is bypassed */ +#define ETH_DMATXDESC_VLANC_REMOVE_TAG (0x00040000UL) /*!< Remove Tag and Type fields in VLAN frame */ +#define ETH_DMATXDESC_VLANC_INSERT_TAG (0x00080000UL) /*!< Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame */ +#define ETH_DMATXDESC_VLANC_REPLACE_TAG (0x000C0000UL) /*!< Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register */ +#define ETH_DMATXDESC_TTSS (0x00020000UL) /*!< Tx Time Stamp Status */ +#define ETH_DMATXDESC_IHE (0x00010000UL) /*!< IP Header Error */ +#define ETH_DMATXDESC_ETSUM (0x00008000UL) /*!< Tx Error summary: OR of the following bits: IHE || JTE || FFF || TPCE || LOCE || NCE || TLCE || ECE || EDE || UDE */ +#define ETH_DMATXDESC_JTE (0x00004000UL) /*!< Jabber Timeout Error */ +#define ETH_DMATXDESC_FFF (0x00002000UL) /*!< Frame Flushed */ +#define ETH_DMATXDESC_TPCE (0x00001000UL) /*!< Payload Checksum Error */ +#define ETH_DMATXDESC_LOCE (0x00000800UL) /*!< Loss Carrier Error */ +#define ETH_DMATXDESC_NCE (0x00000400UL) /*!< No Carrier Error */ +#define ETH_DMATXDESC_TLCE (0x00000200UL) /*!< Late Collision Error */ +#define ETH_DMATXDESC_ECE (0x00000100UL) /*!< Excessive Collision Error */ +#define ETH_DMATXDESC_VLF (0x00000080UL) /*!< VLAN Frame */ +#define ETH_DMATXDESC_COC (0x00000078UL) /*!< Collision Count */ +#define ETH_DMATXDESC_EDE (0x00000004UL) /*!< Excessive Deferral Error */ +#define ETH_DMATXDESC_UDE (0x00000002UL) /*!< Underflow Error */ +#define ETH_DMATXDESC_DEE (0x00000001UL) /*!< Deferred Error */ + +/** + * @brief Bit definition of TDES1 register + */ +#define ETH_DMATXDESC_SAIRC (0xE0000000UL) /*!< Source Address Insertion or Replace Control: 5 cases */ +#define ETH_DMATXDESC_SAIRC_BYPASS (0x00000000UL) /*!< Do Nothing: Source Address Insertion or Replace Control is bypassed */ +#define ETH_DMATXDESC_SAIRC_INSTER_MACADDR0 (0x20000000UL) /*!< Insert address value in MAC address register 0 into transmit frame as SA address */ +#define ETH_DMATXDESC_SAIRC_REPLACE_MACADDR0 (0x40000000UL) /*!< Replace SA address in transmit frame with address value in MAC address register 0 */ +#define ETH_DMATXDESC_SAIRC_INSTER_MACADDR1 (0xA0000000UL) /*!< Insert address value in MAC address register 1 into transmit frame as SA address */ +#define ETH_DMATXDESC_SAIRC_REPLACE_MACADDR1 (0xC0000000UL) /*!< Replace SA address in transmit frame with address value in MAC address register 1 */ +#define ETH_DMATXDESC_TBS2 (0x1FFF0000UL) /*!< Transmit Buffer2 Size */ +#define ETH_DMATXDESC_TBS1 (0x00001FFFUL) /*!< Transmit Buffer1 Size */ + +/** + * @brief Bit definition of TDES2 register + */ +#define ETH_DMATXDESC_TBAP1 (0xFFFFFFFFUL) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of TDES3 register + */ +#define ETH_DMATXDESC_TBAP2 (0xFFFFFFFFUL) /*!< Buffer2 Address Pointer */ + +/* + Enhance DMA Tx Descriptor + ----------------------------------------------------------------------------------------------- + TDES4 | Reserved[31:0] | + ----------------------------------------------------------------------------------------------- + TDES5 | Reserved[31:0] | + ----------------------------------------------------------------------------------------------- + TDES6 | Transmit Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + TDES7 | Transmit Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------- + */ + +/** + * @brief Bit definition of TDES6 register + */ + #define ETH_DMATXDESC_TTSL (0xFFFFFFFFUL) /*!< Transmit Time Stamp Low */ + +/** + * @brief Bit definition of TDES7 register + */ + #define ETH_DMATXDESC_TTSH (0xFFFFFFFFUL) /*!< Transmit Time Stamp High */ + +/** + * @} + */ + +/** + * @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor + * @{ + */ + +/* + Normal DMA Rx Descriptor + -------------------------------------------------------------------------------------------------------------------- + RDES0 | OWN(31) | Status [30:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES2 | Buffer1 Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- + RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] | + --------------------------------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RDES0 register + */ +#define ETH_DMARXDESC_OWN (0x80000000UL) /*!< OWN bit */ +#define ETH_DMARXDESC_DAF (0x40000000UL) /*!< DA Filter Fail for the received frame */ +#define ETH_DMARXDESC_FRAL (0x3FFF0000UL) /*!< Receive frame length */ +#define ETH_DMARXDESC_ERSUM (0x00008000UL) /*!< Rx Error summary: OR of the following bits: DPE || OVE || IPE_TSPA_GF || RLCE || WTE || REE || CRE in RDES0, or IPPE || IPHE in RDES4 */ +#define ETH_DMARXDESC_DPE (0x00004000UL) /*!< Descriptor Error: no more descriptors for receive frame */ +#define ETH_DMARXDESC_SAF (0x00002000UL) /*!< SA Filter Fail for the received frame */ +#define ETH_DMARXDESC_LEE (0x00001000UL) /*!< Length Error: Frame size not matching with length field */ +#define ETH_DMARXDESC_OVE (0x00000800UL) /*!< Overflow Error: Frame was damaged due to buffer overflow */ +#define ETH_DMARXDESC_VLAT (0x00000400UL) /*!< VLAN Tag: received frame is a VLAN frame */ +#define ETH_DMARXDESC_RFS (0x00000200UL) /*!< First descriptor */ +#define ETH_DMARXDESC_RLS (0x00000100UL) /*!< Last descriptor */ +#define ETH_DMARXDESC_IPE_TSPA_GF (0x00000080UL) /*!< COE Error or Time stamp valid or jumbo frame */ +#define ETH_DMARXDESC_RLCE (0x00000040UL) /*!< Late collision Error */ +#define ETH_DMARXDESC_FRAT (0x00000020UL) /*!< Frame type: Ethernet or PTP */ +#define ETH_DMARXDESC_WTE (0x00000010UL) /*!< Receive Watchdog Timeout */ +#define ETH_DMARXDESC_REE (0x00000008UL) /*!< Receive error: error reported by PHY RX_ER */ +#define ETH_DMARXDESC_DBE (0x00000004UL) /*!< Dribble bit error: frame contains non int multiple of 8 bits */ +#define ETH_DMARXDESC_CRE (0x00000002UL) /*!< CRC error */ +#define ETH_DMARXDESC_DAS_ESA (0x00000001UL) /*!< MAC Address Filter/Status bit extension */ + +/** + * @brief Bit definition of RDES1 register + */ +#define ETH_DMARXDESC_DIC (0x80000000UL) /*!< Disable Interrupt on Completion */ +#define ETH_DMARXDESC_RBS2 (0x1FFF0000UL) /*!< Receive Buffer2 Size */ +#define ETH_DMARXDESC_RER (0x00008000UL) /*!< Receive End of Ring */ +#define ETH_DMARXDESC_RSAC (0x00004000UL) /*!< Second Address Chained */ +#define ETH_DMARXDESC_RBS1 (0x00001FFFUL) /*!< Receive Buffer1 Size */ + +/** + * @brief Bit definition of RDES2 register + */ +#define ETH_DMARXDESC_RBAP1 (0xFFFFFFFFUL) /*!< Buffer1 Address Pointer */ + +/** + * @brief Bit definition of RDES3 register + */ +#define ETH_DMARXDESC_RBAP2 (0xFFFFFFFFUL) /*!< Buffer2 Address Pointer */ + +/* + Enhance DMA Rx Descriptor + ----------------------------------------------------------------------------------------------- + RDES4 | Reserved[31:26] | Extend Status [25:24] | Reserved[23:15] | Extend Status [14:0] | + ----------------------------------------------------------------------------------------------- + RDES5 | Reserved[31:0] | + ----------------------------------------------------------------------------------------------- + RDES6 | Receive Time Stamp Low [31:0] | + ----------------------------------------------------------------------------------------------- + RDES7 | Receive Time Stamp High [31:0] | + ----------------------------------------------------------------------------------------------- +*/ + +/** + * @brief Bit definition of RDES4 register + */ +#define ETH_DMARXDESC_L4FMS (0x02000000UL) /*!< L4 Port Filter Status */ +#define ETH_DMARXDESC_L3FMS (0x01000000UL) /*!< L3 Address Filter Status */ +#define ETH_DMARXDESC_TSPD (0x00004000UL) /*!< Discard Time Stamp */ +#define ETH_DMARXDESC_PTPV (0x00002000UL) /*!< PTP Version */ +#define ETH_DMARXDESC_PTPFT (0x00001000UL) /*!< PTP Frame Type */ +#define ETH_DMARXDESC_MTP (0x00000F00UL) /*!< PTP Datagram Type */ +#define ETH_DMARXDESC_MTP_NONE (0x00000000UL) /*!< No PTP messages */ +#define ETH_DMARXDESC_MTP_SYNC (0x00000100UL) /*!< SYNC message (all clock types) */ +#define ETH_DMARXDESC_MTP_FOLLOWUP (0x00000200UL) /*!< Follow_Up message (all clock types) */ +#define ETH_DMARXDESC_MTP_DELAYREQ (0x00000300UL) /*!< Delay_Req message (all clock types) */ +#define ETH_DMARXDESC_MTP_DELAYRESP (0x00000400UL) /*!< Delay_Resp message (all clock types) */ +#define ETH_DMARXDESC_MTP_PDELAYREQ (0x00000500UL) /*!< Pdelay_Req message (peer-to-peer transparent clock) */ +#define ETH_DMARXDESC_MTP_PDELAYRESP (0x00000600UL) /*!< Pdelay_Resp message (peer-to-peer transparent clock) */ +#define ETH_DMARXDESC_MTP_PDELAYRESP_FOLLOWUP (0x00000700UL) /*!< Pdelay_Resp_Follow_Up message (peer-to-peer transparent clock) */ +#define ETH_DMARXDESC_MTP_ANNOUNCE (0x00000800UL) /*!< Announce message (Ordinary or Boundary clock) */ +#define ETH_DMARXDESC_MTP_MANAGEMENT (0x00000900UL) /*!< Management message (Ordinary or Boundary clock) */ +#define ETH_DMARXDESC_MTP_SIGNALING (0x00000A00UL) /*!< Signaling message (Ordinary or Boundary clock) */ +#define ETH_DMARXDESC_MTP_DEFAULT (0x00000F00UL) /*!< Default Datagram Type */ +#define ETH_DMARXDESC_IPV6DR (0x00000080UL) /*!< IPv6 Packet Received */ +#define ETH_DMARXDESC_IPV4DR (0x00000040UL) /*!< IPv4 Packet Received */ +#define ETH_DMARXDESC_IPCB (0x00000020UL) /*!< COE engine Bypassed */ +#define ETH_DMARXDESC_IPPE (0x00000010UL) /*!< IP Payload Error */ +#define ETH_DMARXDESC_IPHE (0x00000008UL) /*!< IP Header Error */ +#define ETH_DMARXDESC_IPPT (0x00000007UL) /*!< IP Payload Type: 4 cases */ +#define ETH_DMARXDESC_IPPT_UNKNOWN (0x00000000UL) /*!< Unknown */ +#define ETH_DMARXDESC_IPPT_UDP (0x00000001UL) /*!< UDP */ +#define ETH_DMARXDESC_IPPT_TCP (0x00000002UL) /*!< TCP */ +#define ETH_DMARXDESC_IPPT_ICMP (0x00000003UL) /*!< ICMP */ + +/** + * @brief Bit definition of RDES6 register + */ +#define ETH_DMARXDESC_RTSL (0xFFFFFFFFUL) /*!< Receive Time Stamp Low */ + +/** + * @brief Bit definition of RDES7 register + */ +#define ETH_DMARXDESC_RTSH (0xFFFFFFFFUL) /*!< Receive Time Stamp High */ + +/** + * @} + */ + +/** + * @defgroup ETH_Auto_Negotiation ETH Auto Negotiation + * @{ + */ +#define ETH_AUTO_NEGOTIATION_DISABLE (0x0000U) +#define ETH_AUTO_NEGOTIATION_ENABLE (0x0001U) +/** + * @} + */ + +/** + * @defgroup ETH_Media_Interface ETH Media Interface + * @{ + */ +#define ETH_MAC_MEDIA_INTERFACE_MII (0UL) +#define ETH_MAC_MEDIA_INTERFACE_RMII (ETH_MAC_IFCONFR_IFSEL) +/** + * @} + */ + +/** + * @defgroup ETH_Speed ETH Speed + * @{ + */ +#define ETH_MAC_SPEED_10M (0UL) +#define ETH_MAC_SPEED_100M (ETH_MAC_CONFIGR_FES) +/** + * @} + */ + +/** + * @defgroup ETH_Duplex_Mode ETH Duplex Mode + * @{ + */ +#define ETH_MAC_MODE_HALFDUPLEX (0UL) +#define ETH_MAC_MODE_FULLDUPLEX (ETH_MAC_CONFIGR_DM) +/** + * @} + */ + +/** + * @defgroup ETH_Checksum_Mode ETH Checksum Mode + * @{ + */ +#define ETH_MAC_CHECKSUM_MODE_SOFTWARE (0UL) +#define ETH_MAC_CHECKSUM_MODE_HARDWARE (0x00000001UL) +/** + * @} + */ + +/** + * @defgroup ETH_Rx_Mode ETH Rx Mode + * @{ + */ +#define ETH_RX_MODE_POLLING (0UL) +#define ETH_RX_MODE_INTERRUPT (0x00000001UL) +/** + * @} + */ + +/** + * @defgroup ETH_TX_CLK_POLARITY ETH TX Clock Polarity + * @{ + */ +#define ETH_MAC_TX_CLK_POLARITY_KEEP (0UL) +#define ETH_MAC_TX_CLK_POLARITY_INVERSE (ETH_MAC_IFCONFR_TCKINV) +/** + * @} + */ + +/** + * @defgroup ETH_RX_REF_CLK_POLARITY ETH RX/REF Clock Polarity + * @{ + */ +#define ETH_MAC_RX_REF_CLK_POLARITY_KEEP (0UL) +#define ETH_MAC_RX_REF_CLK_POLARITY_INVERSE (ETH_MAC_IFCONFR_RCKINV) +/** + * @} + */ + +/** + * @defgroup ETH_SA_Insert_Mode ETH SA Insert Mode + * @{ + */ +#define ETH_MAC_SA_MODE_BY_DMATXDESC (0UL) /*!< Configure the Insert mode by Tx Descriptor of DMA */ +#define ETH_MAC_SA_MODE_INSTER_MACADDR0 (ETH_MAC_CONFIGR_SAIRC_1) /*!< Insert address value in MAC address register 0 into transmit frame as SA address */ +#define ETH_MAC_SA_MODE_REPLACE_MACADDR0 (ETH_MAC_CONFIGR_SAIRC_1 | ETH_MAC_CONFIGR_SAIRC_0) /*!< Replace SA address in transmit frame with address value in MAC address register 0 */ +#define ETH_MAC_SA_MODE_INSTER_MACADDR1 (ETH_MAC_CONFIGR_SAIRC_2 | ETH_MAC_CONFIGR_SAIRC_1) /*!< Insert address value in MAC address register 1 into transmit frame as SA address */ +#define ETH_MAC_SA_MODE_REPLACE_MACADDR1 (ETH_MAC_CONFIGR_SAIRC) /*!< Replace SA address in transmit frame with address value in MAC address register 1 */ +/** + * @} + */ + +/** + * @defgroup ETH_TypeFrame_Strip_FCS ETH Type Frame Strip FCS + * @{ + */ +#define ETH_MAC_TYPEFRAME_STRIP_FCS_DISABLE (0UL) +#define ETH_MAC_TYPEFRAME_STRIP_FCS_ENABLE (ETH_MAC_CONFIGR_CST) +/** + * @} + */ + +/** + * @defgroup ETH_Watchdog ETH Watchdog + * @{ + */ +#define ETH_MAC_WATCHDOG_DISABLE (ETH_MAC_CONFIGR_MWD) +#define ETH_MAC_WATCHDOG_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Jabber ETH Jabber + * @{ + */ +#define ETH_MAC_JABBER_DISABLE (ETH_MAC_CONFIGR_MJB) +#define ETH_MAC_JABBER_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap + * @{ + */ +#define ETH_MAC_INTERFRAME_GAP_96BIT (0UL) +#define ETH_MAC_INTERFRAME_GAP_88BIT (ETH_MAC_CONFIGR_IFG_0) +#define ETH_MAC_INTERFRAME_GAP_80BIT (ETH_MAC_CONFIGR_IFG_1) +#define ETH_MAC_INTERFRAME_GAP_72BIT (ETH_MAC_CONFIGR_IFG_1 | ETH_MAC_CONFIGR_IFG_0) +#define ETH_MAC_INTERFRAME_GAP_64BIT (ETH_MAC_CONFIGR_IFG_2) +#define ETH_MAC_INTERFRAME_GAP_56BIT (ETH_MAC_CONFIGR_IFG_2 | ETH_MAC_CONFIGR_IFG_0) +#define ETH_MAC_INTERFRAME_GAP_48BIT (ETH_MAC_CONFIGR_IFG_2 | ETH_MAC_CONFIGR_IFG_1) +#define ETH_MAC_INTERFRAME_GAP_40BIT (ETH_MAC_CONFIGR_IFG) +/** + * @} + */ + +/** + * @defgroup ETH_Carrier_Sense ETH Carrier Sense + * @{ + */ +#define ETH_MAC_CARRIER_SENCE_DISABLE (ETH_MAC_CONFIGR_DCRS) +#define ETH_MAC_CARRIER_SENCE_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Own ETH Receive Own + * @{ + */ +#define ETH_MAC_RECEIVE_OWN_DISABLE (ETH_MAC_CONFIGR_DO) +#define ETH_MAC_RECEIVE_OWN_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Checksum_Offload ETH Checksum Offload + * @{ + */ +#define ETH_MAC_CHECKSUM_OFFLAOD_DISABLE (0UL) +#define ETH_MAC_CHECKSUM_OFFLAOD_ENABLE (ETH_MAC_CONFIGR_IPCO) +/** + * @} + */ + +/** + * @defgroup ETH_Retry_Transmit ETH Retry Transmit + * @{ + */ +#define ETH_MAC_RETRY_TRANSMIT_DISABLE (ETH_MAC_CONFIGR_DRTY) +#define ETH_MAC_RETRY_TRANSMIT_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Auto_Strip_Pad_FCS ETH Auto Strip Pad FCS + * @{ + */ +#define ETH_MAC_AUTO_STRIP_PAD_FCS_DISABLE (0UL) +#define ETH_MAC_AUTO_STRIP_PAD_FCS_ENABLE (ETH_MAC_CONFIGR_ACS) +/** + * @} + */ + +/** + * @defgroup ETH_Back_Off_Limit ETH Back Off Limit + * @{ + */ +#define ETH_MAC_BACKOFF_LIMIT_10 (0UL) +#define ETH_MAC_BACKOFF_LIMIT_8 (ETH_MAC_CONFIGR_BL_0) +#define ETH_MAC_BACKOFF_LIMIT_4 (ETH_MAC_CONFIGR_BL_1) +#define ETH_MAC_BACKOFF_LIMIT_1 (ETH_MAC_CONFIGR_BL) +/**_ + * @} + */ + +/** + * @defgroup ETH_Deferral_Check ETH Deferral Check + * @{ + */ +#define ETH_MAC_DEFFERRAL_CHECK_DISABLE (0UL) +#define ETH_MAC_DEFFERRAL_CHECK_ENABLE (ETH_MAC_CONFIGR_DC) +/** + * @} + */ + +/** + * @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause + * @{ + */ +#define ETH_MAC_ZERO_QUANTA_PAUSE_DISABLE (ETH_MAC_FLOCTLR_DZPQ) +#define ETH_MAC_ZERO_QUANTA_PAUSE_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold + * @{ + */ +#define ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS4 (0UL) /*!< Pause time minus 4 slot times */ +#define ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS28 (ETH_MAC_FLOCTLR_PLT_0) /*!< Pause time minus 28 slot times */ +#define ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS144 (ETH_MAC_FLOCTLR_PLT_1) /*!< Pause time minus 144 slot times */ +#define ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS256 (ETH_MAC_FLOCTLR_PLT) /*!< Pause time minus 256 slot times */ +/** + * @} + */ + +/** + * @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect + * @{ + */ +#define ETH_MAC_UNICAST_PAUSEFRAME_DETECT_DISABLE (0UL) +#define ETH_MAC_UNICAST_PAUSEFRAME_DETECT_ENABLE (ETH_MAC_FLOCTLR_UNP) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control + * @{ + */ +#define ETH_MAC_RECEIVE_FLOWCONTROL_DISABLE (0UL) +#define ETH_MAC_RECEIVE_FLOWCONTROL_ENABLE (ETH_MAC_FLOCTLR_RFE) +/** + * @} + */ + +/** + * @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control + * @{ + */ +#define ETH_MAC_TRANSMIT_FLOWCONTROL_DISABLE (0UL) +#define ETH_MAC_TRANSMIT_FLOWCONTROL_ENABLE (ETH_MAC_FLOCTLR_TFE) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_All ETH Receive All + * @{ + */ +#define ETH_MAC_RECEIVE_All_DISABLE (0UL) +#define ETH_MAC_RECEIVE_ALL_ENABLE (ETH_MAC_FLTCTLR_RA) +/** + * @} + */ + +/** + * @defgroup ETH_Drop_Not_TcpUdp ETH Drop Not TcpUdp + * @{ + */ +#define ETH_MAC_DROP_NOT_TCPUDP_DISABLE (0UL) +#define ETH_MAC_DROP_NOT_TCPUDP_ENABLE (ETH_MAC_FLTCTLR_DNTU) +/** + * @} + */ + +/** + * @defgroup ETH_VLAN_Tag_Filter ETH VLAN Tag Filter + * @{ + */ +#define ETH_MAC_VLAN_TAG_FILTER_DISABLE (0UL) +#define ETH_MAC_VLAN_TAG_FILTER_ENABLE (ETH_MAC_FLTCTLR_VTFE) +/** + * @} + */ + +/** + * @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter + * @{ + */ +#define ETH_MAC_SOURCE_ADDR_FILTER_DISABLE (0UL) +#define ETH_MAC_SOURCE_ADDR_FILTER_NORMAL (ETH_MAC_FLTCTLR_SAF) +#define ETH_MAC_SOURCE_ADDR_FILTER_INVERSE (ETH_MAC_FLTCTLR_SAF | ETH_MAC_FLTCTLR_SAIF) +/** + * @} + */ + +/** + * @defgroup ETH_Pass_Control_Frame ETH Pass Control Frame + * @{ + */ +#define ETH_MAC_PASS_CTRLFRAME_BLOCK_ALL (0UL) /*!< MAC filter all control frame from reaching the application */ +#define ETH_MAC_PASS_CTRLFRAME_FORWARD_NOTPAUSE_ALL (ETH_MAC_FLTCTLR_PCF_0) /*!< MAC forward all control frame except pause control frame to application even if they fail the address filter */ +#define ETH_MAC_PASS_CTRLFRAME_FORWARD_ALL (ETH_MAC_FLTCTLR_PCF_1) /*!< MAC forward all control frame to application even if they fail the address filter */ +#define ETH_MAC_PASS_CTRLFRAME_FORWARD_PASSADDRFILTER (ETH_MAC_FLTCTLR_PCF) /*!< MAC forward control frame that pass the address filter. */ +/** + * @} + */ + +/** + * @defgroup ETH_Broadcast_Frame_Reception ETH Broadcast Frame Reception + * @{ + */ +#define ETH_MAC_BROADCASTFRAME_RECEPTION_DISABLE (ETH_MAC_FLTCTLR_DBF) +#define ETH_MAC_BROADCASTFRAME_RECEPTION_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter + * @{ + */ +#define ETH_MAC_DESTINATION_ADDR_FILTER_NORMAL (0UL) +#define ETH_MAC_DESTINATION_ADDR_FILTER_INVERSE (ETH_MAC_FLTCTLR_DAIF) +/** + * @} + */ + +/** + * @defgroup ETH_Multicast_Frame_Filter ETH Multicast Frame Filter + * @{ + */ +#define ETH_MAC_MULTICASTFRAME_FILTER_NONE (ETH_MAC_FLTCTLR_PMF) +#define ETH_MAC_MULTICASTFRAME_FILTER_PERFECT (0UL) +#define ETH_MAC_MULTICASTFRAME_FILTER_HASHTABLE (ETH_MAC_FLTCTLR_HMC) +#define ETH_MAC_MULTICASTFRAME_FILTER_PERFECTHASHTABLE (ETH_MAC_FLTCTLR_HPF | ETH_MAC_FLTCTLR_HMC) +/** + * @} + */ + +/** + * @defgroup ETH_Unicast_Frame_Filter ETH Unicast Frame Filter + * @{ + */ +#define ETH_MAC_UNICASTFRAME_FILTER_PERFECT (0UL) +#define ETH_MAC_UNICASTFRAME_FILTER_HASHTABLE (ETH_MAC_FLTCTLR_HUC) +#define ETH_MAC_UNICASTFRAME_FILTER_PERFECTHASHTABLE (ETH_MAC_FLTCTLR_HPF | ETH_MAC_FLTCTLR_HUC) +/** + * @} + */ + +/** + * @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode + * @{ + */ +#define ETH_MAC_PROMISCUOUS_MODE_DISABLE (0UL) +#define ETH_MAC_PROMISCUOUS_MODE_ENABLE (ETH_MAC_FLTCTLR_PR) +/** + * @} + */ + +/** + * @defgroup ETH_Tx_VLAN_Insert_Mode ETH Tx VLAN Insert Mode + * @{ + */ +#define ETH_MAC_TXVLAN_MODE_BY_DMATXDESC (0UL) /*!< Configure the Tx VLAN mode by Tx Descriptor of DMA */ +#define ETH_MAC_TXVLAN_MODE_BYPASS (ETH_MAC_VTACTLR_VLANS) /*!< Do Nothing: VLAN Insertion is bypassed */ +#define ETH_MAC_TXVLAN_MODE_REMOVE_TAG (ETH_MAC_VTACTLR_VLANS | ETH_MAC_VTACTLR_VLANC_0) /*!< Remove Tag and Type fields in VLAN frame */ +#define ETH_MAC_TXVLAN_MODE_INSERT_TAG (ETH_MAC_VTACTLR_VLANS | ETH_MAC_VTACTLR_VLANC_1) /*!< Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame */ +#define ETH_MAC_TXVLAN_MODE_REPLACE_TAG (ETH_MAC_VTACTLR_VLANS | ETH_MAC_VTACTLR_VLANC) /*!< Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register */ +/** + * @} + */ + +/** + * @defgroup ETH_Rx_VLAN_Filter ETH Rx VLAN Filter + * @{ + */ +#define ETH_MAC_RXVLAN_FILTER_NORMAL (0UL) +#define ETH_MAC_RXVLAN_FILTER_INVERSE (ETH_MAC_VTAFLTR_VTIM) +#define ETH_MAC_RXVLAN_FILTER_NORMAL_HASHTABLE (ETH_MAC_VTAFLTR_VTHM) +#define ETH_MAC_RXVLAN_FILTER_INVERSE_HASHTABLE (ETH_MAC_VTAFLTR_VTHM | ETH_MAC_VTAFLTR_VTIM) +/** + * @} + */ + +/** + * @defgroup ETH_Rx_VLAN_Comparison ETH Rx VLAN Comparison + * @{ + */ +#define ETH_MAC_RXVLAN_COMPARISON_16BIT (0UL) +#define ETH_MAC_RXVLAN_COMPARISON_12BIT (ETH_MAC_VTAFLTR_VTAL) +/** + * @} + */ + +/** + * @defgroup ETH_L4_Dest_Port_Filter ETH L4 Dest Port Filter + * @{ + */ +#define ETH_MAC_L4_DESTPORT_FILTER_DISABLE (0UL) +#define ETH_MAC_L4_DESTPORT_FILTER_NORMAL (ETH_MAC_L34CTLR_L4DPM) +#define ETH_MAC_L4_DESTPORT_FILTER_INVERSE (ETH_MAC_L34CTLR_L4DPIM | ETH_MAC_L34CTLR_L4DPM) +/** + * @} + */ + +/** + * @defgroup ETH_L4_Source_Port_Filter ETH L4 Source Port Filter + * @{ + */ +#define ETH_MAC_L4_SOURCEPORT_FILTER_DISABLE (0UL) +#define ETH_MAC_L4_SOURCEPORT_FILTER_NORMAL (ETH_MAC_L34CTLR_L4SPM) +#define ETH_MAC_L4_SOURCEPORT_FILTER_INVERSE (ETH_MAC_L34CTLR_L4SPIM | ETH_MAC_L34CTLR_L4SPM) +/** + * @} + */ + +/** + * @defgroup ETH_L4_Port_Filter_Protocol ETH L4 Port Filter Protocol + * @{ + */ +#define ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP (0UL) /*!< Port filter for TCP frame */ +#define ETH_MAC_L4_PORT_FILTER_PROTOCOL_UDP (ETH_MAC_L34CTLR_L4PEN) /*!< Port filter for UDP frame */ +/** + * @} + */ + +/** + * @defgroup ETH_L3_Dest_Addr_Filter_Mask ETH L3 Destination Addr Filter Mask + * @note The following definitions apply to IPv4 + * @{ + */ +#define ETH_MAC_L3_DA_FILTER_MASK_NONE (0x00000000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT0 (0x00000800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT1_0 (0x00001000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT2_0 (0x00001800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT3_0 (0x00002000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT4_0 (0x00002800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT5_0 (0x00003000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT6_0 (0x00003800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT7_0 (0x00004000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT8_0 (0x00004800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT9_0 (0x00005000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT10_0 (0x00005800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT11_0 (0x00006000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT12_0 (0x00006800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT13_0 (0x00007000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT14_0 (0x00007800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT15_0 (0x00008000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT16_0 (0x00008800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT17_0 (0x00009000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT18_0 (0x00009800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT19_0 (0x0000A000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT20_0 (0x0000A800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT21_0 (0x0000B000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT22_0 (0x0000B800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT23_0 (0x0000C000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT24_0 (0x0000C800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT25_0 (0x0000D000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT26_0 (0x0000D800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT27_0 (0x0000E000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT28_0 (0x0000E800UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT29_0 (0x0000F000UL) +#define ETH_MAC_L3_DA_FILTER_MASK_BIT30_0 (0x0000F800UL) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Source_Addr_Filter_Mask ETH L3 Source Addr Filter Mask + * @note The following definitions apply to IPv4 + * @{ + */ +#define ETH_MAC_L3_SA_FILTER_MASK_NONE (0x00000000UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT0 (0x00000040UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT1_0 (0x00000080UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT2_0 (0x000000C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT3_0 (0x00000100UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT4_0 (0x00000140UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT5_0 (0x00000180UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT6_0 (0x000001C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT7_0 (0x00000200UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT8_0 (0x00000240UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT9_0 (0x00000280UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT10_0 (0x000002C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT11_0 (0x00000300UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT12_0 (0x00000340UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT13_0 (0x00000380UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT14_0 (0x000003C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT15_0 (0x00000400UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT16_0 (0x00000440UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT17_0 (0x00000480UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT18_0 (0x000004C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT19_0 (0x00000500UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT20_0 (0x00000540UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT21_0 (0x00000580UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT22_0 (0x000005C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT23_0 (0x00000600UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT24_0 (0x00000640UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT25_0 (0x00000680UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT26_0 (0x000006C0UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT27_0 (0x00000700UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT28_0 (0x00000740UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT29_0 (0x00000780UL) +#define ETH_MAC_L3_SA_FILTER_MASK_BIT30_0 (0x000007C0UL) +/** + * @} + */ + +/** + * @defgroup ETH_L3_DA_SA_Filter_Mask ETH L3 DA SA Filter Mask + * @note The following definitions apply to IPv6. + * @{ + */ +#define ETH_MAC_L3_DA_SA_FILTER_MASK_NONE (0x00000000UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT0 (0x00000040UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT1_0 (0x00000080UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT2_0 (0x000000C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT3_0 (0x00000100UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT4_0 (0x00000140UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT5_0 (0x00000180UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT6_0 (0x000001C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT7_0 (0x00000200UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT8_0 (0x00000240UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT9_0 (0x00000280UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT10_0 (0x000002C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT11_0 (0x00000300UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT12_0 (0x00000340UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT13_0 (0x00000380UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT14_0 (0x000003C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT15_0 (0x00000400UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT16_0 (0x00000440UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT17_0 (0x00000480UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT18_0 (0x000004C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT19_0 (0x00000500UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT20_0 (0x00000540UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT21_0 (0x00000580UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT22_0 (0x000005C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT23_0 (0x00000600UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT24_0 (0x00000640UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT25_0 (0x00000680UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT26_0 (0x000006C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT27_0 (0x00000700UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT28_0 (0x00000740UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT29_0 (0x00000780UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT30_0 (0x000007C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT31_0 (0x00000800UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT32_0 (0x00000840UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT33_0 (0x00000880UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT34_0 (0x000008C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT35_0 (0x00000900UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT36_0 (0x00000940UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT37_0 (0x00000980UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT38_0 (0x000009C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT39_0 (0x00000A00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT40_0 (0x00000A40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT41_0 (0x00000A80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT42_0 (0x00000AC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT43_0 (0x00000B00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT44_0 (0x00000B40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT45_0 (0x00000B80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT46_0 (0x00000BC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT47_0 (0x00000C00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT48_0 (0x00000C40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT49_0 (0x00000C80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT50_0 (0x00000CC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT51_0 (0x00000D00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT52_0 (0x00000D40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT53_0 (0x00000D80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT54_0 (0x00000DC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT55_0 (0x00000E00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT56_0 (0x00000E40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT57_0 (0x00000E80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT58_0 (0x00000EC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT59_0 (0x00000F00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT60_0 (0x00000F40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT61_0 (0x00000F80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT62_0 (0x00000FC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT63_0 (0x00001000UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT64_0 (0x00001040UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT65_0 (0x00001080UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT66_0 (0x000010C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT67_0 (0x00001100UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT68_0 (0x00001140UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT69_0 (0x00001180UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT70_0 (0x000011C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT71_0 (0x00001200UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT72_0 (0x00001240UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT73_0 (0x00001280UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT74_0 (0x000012C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT75_0 (0x00001300UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT76_0 (0x00001340UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT77_0 (0x00001380UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT78_0 (0x000013C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT79_0 (0x00001400UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT80_0 (0x00001440UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT81_0 (0x00001480UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT82_0 (0x000014C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT83_0 (0x00001500UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT84_0 (0x00001540UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT85_0 (0x00001580UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT86_0 (0x000015C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT87_0 (0x00001600UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT88_0 (0x00001640UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT89_0 (0x00001680UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT90_0 (0x000016C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT91_0 (0x00001700UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT92_0 (0x00001740UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT93_0 (0x00001780UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT94_0 (0x000017C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT95_0 (0x00001800UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT96_0 (0x00001840UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT97_0 (0x00001880UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT98_0 (0x000018C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT99_0 (0x00001900UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT100_0 (0x00001940UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT101_0 (0x00001980UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT102_0 (0x000019C0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT103_0 (0x00001A00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT104_0 (0x00001A40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT105_0 (0x00001A80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT106_0 (0x00001AC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT107_0 (0x00001B00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT108_0 (0x00001B40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT109_0 (0x00001B80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT110_0 (0x00001BC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT111_0 (0x00001C00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT112_0 (0x00001C40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT113_0 (0x00001C80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT114_0 (0x00001CC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT115_0 (0x00001D00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT116_0 (0x00001D40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT117_0 (0x00001D80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT118_0 (0x00001DC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT119_0 (0x00001E00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT120_0 (0x00001E40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT121_0 (0x00001E80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT122_0 (0x00001EC0UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT123_0 (0x00001F00UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT124_0 (0x00001F40UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT125_0 (0x00001F80UL) +#define ETH_MAC_L3_DA_SA_FILTER_MASK_BIT126_0 (0x00001FC0UL) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Dest_Addr_Filter ETH L3 Destination Addr Filter + * @{ + */ +#define ETH_MAC_L3_DA_FILTER_DISABLE (0UL) +#define ETH_MAC_L3_DA_FILTER_NORMAL (ETH_MAC_L34CTLR_L3DAM) +#define ETH_MAC_L3_DA_FILTER_INVERSE (ETH_MAC_L34CTLR_L3DAIM | ETH_MAC_L34CTLR_L3DAM) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Source_Addr_Filter ETH L3 Source Addr Filter + * @{ + */ +#define ETH_MAC_L3_SA_FILTER_DISABLE (0UL) +#define ETH_MAC_L3_SA_FILTER_NORMAL (ETH_MAC_L34CTLR_L3SAM) +#define ETH_MAC_L3_SA_FILTER_INVERSE (ETH_MAC_L34CTLR_L3SAIM | ETH_MAC_L34CTLR_L3SAM) +/** + * @} + */ + +/** + * @defgroup ETH_L3_Addr_Filter_Protocol ETH L3 Addr Filter Protocol + * @{ + */ +#define ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4 (0UL) /*!< Ip Address filter for IPv4 */ +#define ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV6 (ETH_MAC_L34CTLR_L3PEN) /*!< Ip Address filter for IPv6 */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Address_Index ETH MAC Address Index + * @{ + */ +#define ETH_MAC_ADDRESS0 (0x00000000UL) +#define ETH_MAC_ADDRESS1 (0x00000008UL) +#define ETH_MAC_ADDRESS2 (0x00000010UL) +#define ETH_MAC_ADDRESS3 (0x00000018UL) +#define ETH_MAC_ADDRESS4 (0x00000020UL) +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Address_Filter ETH MAC Address Filter + * @note The parameter is invalid in ETH_MAC_ADDRESS0. + * @{ + */ +#define ETH_MAC_ADDRESS_FILTER_DISABLE (0UL) /*!< Disable perfect filter with MAC address. */ +#define ETH_MAC_ADDRESS_FILTER_PERFECT_DA (ETH_MAC_MACADHR1_AE1) /*!< Filter the DA address of the received frame with MAC address. */ +#define ETH_MAC_ADDRESS_FILTER_PERFECT_SA (ETH_MAC_MACADHR1_AE1 | ETH_MAC_MACADHR1_SA1) /*!< Filter the SA address of the received frame with MAC address. */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Address_Filter_Mask ETH MAC Address Filter Mask + * @note The parameter is invalid in ETH_MAC_ADDRESS0. + * @{ + */ +#define ETH_MAC_ADDRESS_MASK_DISABLE (0UL) /*!< Disable MAC Address Mask */ +#define ETH_MAC_ADDRESS_MASK_BYTE6 (ETH_MAC_MACADHR1_MBC1_5) /*!< Mask MAC Address high reg bits [15:8] */ +#define ETH_MAC_ADDRESS_MASK_BYTE5 (ETH_MAC_MACADHR1_MBC1_4) /*!< Mask MAC Address high reg bits [7:0] */ +#define ETH_MAC_ADDRESS_MASK_BYTE4 (ETH_MAC_MACADHR1_MBC1_3) /*!< Mask MAC Address low reg bits [31:24] */ +#define ETH_MAC_ADDRESS_MASK_BYTE3 (ETH_MAC_MACADHR1_MBC1_2) /*!< Mask MAC Address low reg bits [23:16] */ +#define ETH_MAC_ADDRESS_MASK_BYTE2 (ETH_MAC_MACADHR1_MBC1_1) /*!< Mask MAC Address low reg bits [15:8] */ +#define ETH_MAC_ADDRESS_MASK_BYTE1 (ETH_MAC_MACADHR1_MBC1_0) /*!< Mask MAC Address low reg bits [7:0] */ +#define ETH_MAC_ADDRESS_MASK_ALL (ETH_MAC_MACADHR1_MBC1) /*!< Mask MAC Address low reg bits [31:0] and low high bits [15:0] */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_INT_Flag ETH MAC Interrupt Flag + * @{ + */ +#define ETH_MAC_INT_FLAG_TSPIS (ETH_MAC_INTSTSR_TSPIS) /*!< Time stamp trigger flag (on MAC) */ +#define ETH_MAC_INT_FLAG_MMCTXIS (ETH_MAC_INTSTSR_MMCTXIS) /*!< MMC transmit flag */ +#define ETH_MAC_INT_FLAG_MMCRXIS (ETH_MAC_INTSTSR_MMCRXIS) /*!< MMC receive flag */ +#define ETH_MAC_INT_FLAG_MMCIS (ETH_MAC_INTSTSR_MMCIS) /*!< MMC flag (on MAC) */ +#define ETH_MAC_INT_FLAG_PMTIS (ETH_MAC_INTSTSR_PMTIS) /*!< PMT flag (on MAC) */ +/** + * @} + */ + +/** + * @defgroup ETH_MAC_Interrupt ETH MAC Interrupt + * @{ + */ +#define ETH_MAC_INT_TSPIM (ETH_MAC_INTMSKR_TSPIM) /*!< Time stamp trigger interrupt (on MAC) */ +#define ETH_MAC_INT_PMTIM (ETH_MAC_INTMSKR_PMTIM) /*!< PMT interrupt (on MAC) */ +/** + * @} + */ + +/** + * @defgroup ETH_Burst_Mode ETH Burst Mode + * @{ + */ +#define ETH_DMA_BURST_MODE_NORMAL (0UL) /*!< DMA master interface only use SINGLE and INCR access type */ +#define ETH_DMA_BURST_MODE_FIXED (ETH_DMA_BUSMODR_FBST) /*!< DMA master interface use SINGLE and INCR, INCR8, INCR16 access type */ +#define ETH_DMA_BURST_MODE_MIXED (ETH_DMA_BUSMODR_MBST) /*!< DMA master interface will start all burst transmission with INCR length greater than 16 */ +/** + * @} + */ + +/** + * @defgroup ETH_Address_Align ETH Address Align + * @{ + */ +#define ETH_DMA_ADDRESS_ALIGN_DISABLE (0UL) +#define ETH_DMA_ADDRESS_ALIGN_ENABLE (ETH_DMA_BUSMODR_AAL) +/** + * @} + */ + +/** + * @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length + * @{ + */ +#define ETH_DMA_RX_BURST_LENGTH_1BEAT (ETH_DMA_BUSMODR_RPBL_0) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 1 */ +#define ETH_DMA_RX_BURST_LENGTH_2BEAT (ETH_DMA_BUSMODR_RPBL_1) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 2 */ +#define ETH_DMA_RX_BURST_LENGTH_4BEAT (ETH_DMA_BUSMODR_RPBL_2) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 4 */ +#define ETH_DMA_RX_BURST_LENGTH_8BEAT (ETH_DMA_BUSMODR_RPBL_3) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMA_RX_BURST_LENGTH_16BEAT (ETH_DMA_BUSMODR_RPBL_4) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMA_RX_BURST_LENGTH_32BEAT (ETH_DMA_BUSMODR_RPBL_5) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMA_RX_BURST_LENGTH_8XPBL_8BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_0) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 8 */ +#define ETH_DMA_RX_BURST_LENGTH_8XPBL_16BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_1) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 16 */ +#define ETH_DMA_RX_BURST_LENGTH_8XPBL_32BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_2) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 32 */ +#define ETH_DMA_RX_BURST_LENGTH_8XPBL_64BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_3) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 64 */ +#define ETH_DMA_RX_BURST_LENGTH_8XPBL_128BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_4) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 128 */ +#define ETH_DMA_RX_BURST_LENGTH_8XPBL_256BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_RPBL_5) /*!< Maximum number of beats to be transferred in one RxDMA transaction is 256 */ +/** + * @} + */ + +/** + * @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length + * @{ + */ +#define ETH_DMA_TX_BURST_LENGTH_1BEAT (ETH_DMA_BUSMODR_TPBL_0) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */ +#define ETH_DMA_TX_BURST_LENGTH_2BEAT (ETH_DMA_BUSMODR_TPBL_1) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */ +#define ETH_DMA_TX_BURST_LENGTH_4BEAT (ETH_DMA_BUSMODR_TPBL_2) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */ +#define ETH_DMA_TX_BURST_LENGTH_8BEAT (ETH_DMA_BUSMODR_TPBL_3) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMA_TX_BURST_LENGTH_16BEAT (ETH_DMA_BUSMODR_TPBL_4) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMA_TX_BURST_LENGTH_32BEAT (ETH_DMA_BUSMODR_TPBL_5) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMA_TX_BURST_LENGTH_8XPBL_8BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_0) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */ +#define ETH_DMA_TX_BURST_LENGTH_8XPBL_16BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_1) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */ +#define ETH_DMA_TX_BURST_LENGTH_8XPBL_32BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_2) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */ +#define ETH_DMA_TX_BURST_LENGTH_8XPBL_64BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_3) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */ +#define ETH_DMA_TX_BURST_LENGTH_8XPBL_128BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_4) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */ +#define ETH_DMA_TX_BURST_LENGTH_8XPBL_256BEAT (ETH_DMA_BUSMODR_M8PBL | ETH_DMA_BUSMODR_TPBL_5) /*!< Maximum number of beats to be transferred in one TxDMA (or both) transaction is 256 */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Enhance_Descriptor ETH DMA Enhance Descriptor + * @{ + */ +#define ETH_DMA_ENHANCE_DESCRIPTOR_DISABLE (0UL) +#define ETH_DMA_ENHANCE_DESCRIPTOR_ENABLE (ETH_DMA_BUSMODR_DSEN) +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Arbitration ETH DMA Arbitration + * @{ + */ +#define ETH_DMA_ARBITRATION_LOOP_RXTX_1_1 (0UL) +#define ETH_DMA_ARBITRATION_LOOP_RXTX_2_1 (ETH_DMA_BUSMODR_PRAT_0) +#define ETH_DMA_ARBITRATION_LOOP_RXTX_3_1 (ETH_DMA_BUSMODR_PRAT_1) +#define ETH_DMA_ARBITRATION_LOOP_RXTX_4_1 (ETH_DMA_BUSMODR_PRAT) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_1_1 (ETH_DMA_BUSMODR_TXPR) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_2_1 (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT_0) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_3_1 (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT_1) +#define ETH_DMA_ARBITRATION_LOOP_TXRX_4_1 (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT) +#define ETH_DMA_ARBITRATION_FIXED_RXPRIORTX (ETH_DMA_BUSMODR_DMAA) +#define ETH_DMA_ARBITRATION_FIXED_TXPRIORRX (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_DMAA) +/** + * @} + */ + +/** + * @defgroup ETH_Drop_TCPIP_Checksum_Error_Frame ETH Drop TCPIP Checksum Error Frame + * @{ + */ +#define ETH_DMA_DROP_CHECKSUM_ERRORFRAME_DISABLE (ETH_DMA_OPRMODR_DTCOE) +#define ETH_DMA_DROP_CHECKSUM_ERRORFRAME_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward + * @{ + */ +#define ETH_DMA_RECEIVE_STORE_FORWARD_DISABLE (0UL) +#define ETH_DMA_RECEIVE_STORE_FORWARD_ENABLE (ETH_DMA_OPRMODR_RSF) +/** + * @} + */ + +/** + * @defgroup ETH_Flush_Receive_Frame ETH Flush Receive Frame + * @{ + */ +#define ETH_DMA_FLUSH_RECEIVEDFRAME_DISABLE (ETH_DMA_OPRMODR_DFRF) +#define ETH_DMA_FLUSH_RECEIVEDFRAME_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward + * @{ + */ +#define ETH_DMA_TRANSMIT_STORE_FORWARD_DISABLE (0UL) +#define ETH_DMA_TRANSMIT_STORE_FORWARD_ENABLE (ETH_DMA_OPRMODR_TSF) +/** + * @} + */ + +/** + * @defgroup ETH_Transmit_Threshold ETH Transmit Threshold + * @{ + */ +#define ETH_DMA_TRANSMIT_THRESHOLD_64BYTE (0UL) /*!< Threshold level of the Transmit FIFO is 64 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_128BYTE (ETH_DMA_OPRMODR_TTC_0) /*!< Threshold level of the Transmit FIFO is 128 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_192BYTE (ETH_DMA_OPRMODR_TTC_1) /*!< Threshold level of the Transmit FIFO is 192 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_256BYTE (ETH_DMA_OPRMODR_TTC_1 | ETH_DMA_OPRMODR_TTC_0) /*!< Threshold level of the Transmit FIFO is 256 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_40BYTE (ETH_DMA_OPRMODR_TTC_2) /*!< Threshold level of the Transmit FIFO is 40 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_32BYTE (ETH_DMA_OPRMODR_TTC_2 | ETH_DMA_OPRMODR_TTC_0) /*!< Threshold level of the Transmit FIFO is 32 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_24BYTE (ETH_DMA_OPRMODR_TTC_2 | ETH_DMA_OPRMODR_TTC_1) /*!< Threshold level of the Transmit FIFO is 24 Bytes */ +#define ETH_DMA_TRANSMIT_THRESHOLD_16BYTE (ETH_DMA_OPRMODR_TTC) /*!< Threshold level of the Transmit FIFO is 16 Bytes */ +/** + * @} + */ + +/** + * @defgroup ETH_Forward_Error_Frame ETH Forward Error Frame + * @{ + */ +#define ETH_DMA_FORWARD_ERRORFRAME_DISABLE (0UL) +#define ETH_DMA_FORWARD_ERRORFRAME_ENABLE (ETH_DMA_OPRMODR_FEF) +/** + * @} + */ + +/** + * @defgroup ETH_Forward_Undersize_Good_Frame ETH Forward Undersize Good Frame + * @{ + */ +#define ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME_DISABLE (0UL) +#define ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME_ENABLE (ETH_DMA_OPRMODR_FUF) +/** + * @} + */ + +/** + * @defgroup ETH_Drop_Jumbo_Frame ETH Drop Jumbo Frame + * @{ + */ +#define ETH_DMA_DROP_JUMBO_FRAME_DISABLE (0UL) +#define ETH_DMA_DROP_JUMBO_FRAME_ENABLE (ETH_DMA_OPRMODR_DGF) +/** + * @} + */ + +/** + * @defgroup ETH_Receive_Threshold ETH Receive Threshold + * @{ + */ +#define ETH_DMA_RECEIVE_THRESHOLD_64BYTE (0UL) /*!< Threshold level of the Receive FIFO is 64 Bytes */ +#define ETH_DMA_RECEIVE_THRESHOLD_32BYTE (ETH_DMA_OPRMODR_RTC_0) /*!< Threshold level of the Receive FIFO is 32 Bytes */ +#define ETH_DMA_RECEIVE_THRESHOLD_96BYTE (ETH_DMA_OPRMODR_RTC_1) /*!< Threshold level of the Receive FIFO is 96 Bytes */ +#define ETH_DMA_RECEIVE_THRESHOLD_128BYTE (ETH_DMA_OPRMODR_RTC) /*!< Threshold level of the Receive FIFO is 128 Bytes */ +/** + * @} + */ + +/** + * @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate + * @{ + */ +#define ETH_DMA_SECONDFRAME_OPERARTE_DISABLE (0UL) +#define ETH_DMA_SECONDFRAME_OPERARTE_ENABLE (ETH_DMA_OPRMODR_OSF) +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Flag ETH DMA Flag + * @{ + */ +#define ETH_DMA_FLAG_PTPS (ETH_DMA_DMASTSR_PTPS) /*!< Time-stamp trigger status */ +#define ETH_DMA_FLAG_PMTS (ETH_DMA_DMASTSR_PMTS) /*!< PMT trigger status */ +#define ETH_DMA_FLAG_MMCS (ETH_DMA_DMASTSR_MMCS) /*!< MMC trigger status */ +#define ETH_DMA_FLAG_EBUS (ETH_DMA_DMASTSR_EBUS) /*!< Error state bits */ +#define ETH_DMA_FLAG_TSTS (ETH_DMA_DMASTSR_TSTS) /*!< Transmit state */ +#define ETH_DMA_FLAG_RSTS (ETH_DMA_DMASTSR_RSTS) /*!< Receive state */ +#define ETH_DMA_FLAG_NIS (ETH_DMA_DMASTSR_NIS) /*!< Normal interrupt summary flag */ +#define ETH_DMA_FLAG_AIS (ETH_DMA_DMASTSR_AIS) /*!< Abnormal interrupt summary flag */ +#define ETH_DMA_FLAG_ERS (ETH_DMA_DMASTSR_ERS) /*!< Early receive flag */ +#define ETH_DMA_FLAG_FBS (ETH_DMA_DMASTSR_FBS) /*!< Fatal bus error flag */ +#define ETH_DMA_FLAG_ETS (ETH_DMA_DMASTSR_ETS) /*!< Early transmit flag */ +#define ETH_DMA_FLAG_RWS (ETH_DMA_DMASTSR_RWS) /*!< Receive watchdog timeout flag */ +#define ETH_DMA_FLAG_RSS (ETH_DMA_DMASTSR_RSS) /*!< Receive stopped flag */ +#define ETH_DMA_FLAG_RUS (ETH_DMA_DMASTSR_RUS) /*!< Receive buffer unavailable flag */ +#define ETH_DMA_FLAG_RIS (ETH_DMA_DMASTSR_RIS) /*!< Receive flag */ +#define ETH_DMA_FLAG_UNS (ETH_DMA_DMASTSR_UNS) /*!< Transmit Underflow flag */ +#define ETH_DMA_FLAG_OVS (ETH_DMA_DMASTSR_OVS) /*!< Receive Overflow flag */ +#define ETH_DMA_FLAG_TJS (ETH_DMA_DMASTSR_TJS) /*!< Transmit jabber timeout flag */ +#define ETH_DMA_FLAG_TUS (ETH_DMA_DMASTSR_TUS) /*!< Transmit buffer unavailable flag */ +#define ETH_DMA_FLAG_TSS (ETH_DMA_DMASTSR_TSS) /*!< Transmit stopped flag */ +#define ETH_DMA_FLAG_TIS (ETH_DMA_DMASTSR_TIS) /*!< Transmit interrupt flag */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Error_State ETH DMA Error State + * @{ + */ +#define ETH_DMA_ERRORSTATE_RX_WRITEDATA (0UL) /*!< RxDMA generates error while writing data */ +#define ETH_DMA_ERRORSTATE_TX_READDATA (ETH_DMA_DMASTSR_EBUS_1 | ETH_DMA_DMASTSR_EBUS_0) /*!< TxDMA generates error while reading data */ +#define ETH_DMA_ERRORSTATE_RX_WRITEDESC (ETH_DMA_DMASTSR_EBUS_2) /*!< RxDMA generates error while writing descriptor */ +#define ETH_DMA_ERRORSTATE_TX_WRITEDESC (ETH_DMA_DMASTSR_EBUS_2 | ETH_DMA_DMASTSR_EBUS_0) /*!< TxDMA generates error while writing descriptor */ +#define ETH_DMA_ERRORSTATE_RX_READDESC (ETH_DMA_DMASTSR_EBUS_2 | ETH_DMA_DMASTSR_EBUS_1) /*!< RxDMA generates error while reading descriptor */ +#define ETH_DMA_ERRORSTATE_TX_READDESC (ETH_DMA_DMASTSR_EBUS) /*!< TxDMA generates error while reading descriptor */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Transmit_State ETH DMA Transmit State + * @{ + */ +#define ETH_DMA_TRANSMITSTATE_STOPPED (0UL) /*!< Stopped - Reset or Stop Tx Command issued */ +#define ETH_DMA_TRANSMITSTATE_FETCHING (ETH_DMA_DMASTSR_TSTS_0) /*!< Running - Fetching the Tx descriptor */ +#define ETH_DMA_TRANSMITSTATE_WAITING (ETH_DMA_DMASTSR_TSTS_1) /*!< Running - Waiting for status */ +#define ETH_DMA_TRANSMITSTATE_READING (ETH_DMA_DMASTSR_TSTS_1 | ETH_DMA_DMASTSR_TSTS_0) /*!< Running - Reading the data from host memory */ +#define ETH_DMA_TRANSMITSTATE_WRITING (ETH_DMA_DMASTSR_TSTS_2) /*!< Running - Writing the time stamp */ +#define ETH_DMA_TRANSMITSTATE_SUSPENDED (ETH_DMA_DMASTSR_TSTS_2 | ETH_DMA_DMASTSR_TSTS_1) /*!< Suspended - Tx Descriptor unavailable */ +#define ETH_DMA_TRANSMITSTATE_CLOSING (ETH_DMA_DMASTSR_TSTS) /*!< Running - Closing Rx descriptor */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Receive_State ETH DMA Receive State + * @{ + */ +#define ETH_DMA_RECEIVESTATE_STOPPED (0UL) /*!< Stopped - Reset or Stop Rx Command issued */ +#define ETH_DMA_RECEIVESTATE_FETCHING (ETH_DMA_DMASTSR_RSTS_0) /*!< Running - Fetching the Rx descriptor */ +#define ETH_DMA_RECEIVESTATE_WAITING (ETH_DMA_DMASTSR_RSTS_1 | ETH_DMA_DMASTSR_RSTS_0) /*!< Running - Waiting for packet */ +#define ETH_DMA_RECEIVESTATE_SUSPENDED (ETH_DMA_DMASTSR_RSTS_2) /*!< Suspended - Rx Descriptor unavailable */ +#define ETH_DMA_RECEIVESTATE_CLOSING (ETH_DMA_DMASTSR_RSTS_2 | ETH_DMA_DMASTSR_RSTS_0) /*!< Running - Closing descriptor */ +#define ETH_DMA_RECEIVESTATE_WRITING (ETH_DMA_DMASTSR_RSTS_2 | ETH_DMA_DMASTSR_RSTS_1) /*!< Running - Writing the time stamp */ +#define ETH_DMA_RECEIVESTATE_QUEUING (ETH_DMA_DMASTSR_RSTS) /*!< Running - Queuing the receive frame into host memory */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Interrupt ETH DMA Interrupt + * @{ + */ +#define ETH_DMA_INT_NIE (ETH_DMA_INTENAR_NIE) /*!< Normal interrupt summary */ +#define ETH_DMA_INT_AIE (ETH_DMA_INTENAR_AIE) /*!< Abnormal interrupt summary */ +#define ETH_DMA_INT_ERE (ETH_DMA_INTENAR_ERE) /*!< Early receive interrupt */ +#define ETH_DMA_INT_FBE (ETH_DMA_INTENAR_FBE) /*!< Fatal bus error interrupt */ +#define ETH_DMA_INT_ETE (ETH_DMA_INTENAR_ETE) /*!< Early transmit interrupt */ +#define ETH_DMA_INT_RWE (ETH_DMA_INTENAR_RWE) /*!< Receive watchdog timeout interrupt */ +#define ETH_DMA_INT_RSE (ETH_DMA_INTENAR_RSE) /*!< Receive process stopped interrupt */ +#define ETH_DMA_INT_RUE (ETH_DMA_INTENAR_RUE) /*!< Receive buffer unavailable interrupt */ +#define ETH_DMA_INT_RIE (ETH_DMA_INTENAR_RIE) /*!< Receive interrupt */ +#define ETH_DMA_INT_UNE (ETH_DMA_INTENAR_UNE) /*!< Transmit Underflow interrupt */ +#define ETH_DMA_INT_OVE (ETH_DMA_INTENAR_OVE) /*!< Receive Overflow interrupt */ +#define ETH_DMA_INT_TJE (ETH_DMA_INTENAR_TJE) /*!< Transmit jabber timeout interrupt */ +#define ETH_DMA_INT_TUE (ETH_DMA_INTENAR_TUE) /*!< Transmit buffer unavailable interrupt */ +#define ETH_DMA_INT_TSE (ETH_DMA_INTENAR_TSE) /*!< Transmit process stopped interrupt */ +#define ETH_DMA_INT_TIE (ETH_DMA_INTENAR_TIE) /*!< Transmit interrupt */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Overflow ETH DMA Overflow + * @{ + */ +#define ETH_DMA_OVERFLOW_RXFIFO_COUNTER (ETH_DMA_RFRCNTR_OVFOVF) /*!< Overflow bit for FIFO overflow counter */ +#define ETH_DMA_OVERFLOW_MISSFRAME_COUNTER (ETH_DMA_RFRCNTR_UNAOVF) /*!< Overflow bit for miss frame counter */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Descriptor_Own ETH DMA Descriptor Own + * @{ + */ +#define ETH_DMADESC_OWN_CPU (0UL) /*!< The descriptor is owned by CPU */ +#define ETH_DMADESC_OWN_DMA (ETH_DMATXDESC_OWN) /*!< The descriptor is owned by DMA */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Descriptor_Buffer ETH DMA Descriptor Buffer + * @{ + */ +#define ETH_DMADESC_BUFFER1 ((uint8_t)0x00UL) /*!< DMA Desc Buffer1 */ +#define ETH_DMADESC_BUFFER2 ((uint8_t)0x01UL) /*!< DMA Desc Buffer2 */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control + * @{ + */ +#define ETH_DMATXDESC_CHECKSUM_BYPASS (ETH_DMATXDESC_CIC_BYPASS) /*!< Checksum Engine is bypassed */ +#define ETH_DMATXDESC_CHECKSUM_IPV4HEADER (ETH_DMATXDESC_CIC_IPV4HEADER) /*!< IPv4 header checksum insertion */ +#define ETH_DMATXDESC_CHECKSUM_TCPUDPICMP_SEGMENT (ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */ +#define ETH_DMATXDESC_CHECKSUM_TCPUDPICMP_FULL (ETH_DMATXDESC_CIC_TCPUDPICMP_FULL) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Tx_Descriptor_VLAN_Insertion_Control ETH DMA Tx Descriptor VLAN Insertion Control + * @{ + */ +#define ETH_DMATXDESC_VLAN_BYPASS (ETH_DMATXDESC_VLANC_BYPASS) /*!< VLAN Insertion is bypassed */ +#define ETH_DMATXDESC_VLAN_REMOVE_TAG (ETH_DMATXDESC_VLANC_REMOVE_TAG) /*!< Remove Tag and Type fields in VLAN frame */ +#define ETH_DMATXDESC_VLAN_INSERT_TAG (ETH_DMATXDESC_VLANC_INSERT_TAG) /*!< Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame */ +#define ETH_DMATXDESC_VLAN_REPLACE_TAG (ETH_DMATXDESC_VLANC_REPLACE_TAG) /*!< Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register */ +/** + * @} + */ + +/** + * @defgroup ETH_DMA_Tx_Descriptor_SA_Insertion_Control ETH DMA Tx Descriptor SA Insertion Control + * @{ + */ +#define ETH_DMATXDESC_SA_BYPASS (ETH_DMATXDESC_SAIRC_BYPASS) /*!< Source Address Insertion or Replace Control is bypassed */ +#define ETH_DMATXDESC_SA_INSTER_MACADDR0 (ETH_DMATXDESC_SAIRC_INSTER_MACADDR0) /*!< Insert address value in MAC address register 0 into transmit frame as SA address */ +#define ETH_DMATXDESC_SA_REPLACE_MACADDR0 (ETH_DMATXDESC_SAIRC_REPLACE_MACADDR0) /*!< Replace SA address in transmit frame with address value in MAC address register 0 */ +#define ETH_DMATXDESC_SA_INSTER_MACADDR1 (ETH_DMATXDESC_SAIRC_INSTER_MACADDR1) /*!< Insert address value in MAC address register 1 into transmit frame as SA address */ +#define ETH_DMATXDESC_SA_REPLACE_MACADDR1 (ETH_DMATXDESC_SAIRC_REPLACE_MACADDR1) /*!< Replace SA address in transmit frame with address value in MAC address register 1 */ +/** + * @} + */ + +/** + * @defgroup ETH_PMT_Flag ETH PMT Flag + * @{ + */ +#define ETH_PMT_FLAG_RTWKFR (ETH_MAC_PMTCTLR_RTWKFR) /*!< Wake-Up Frame Filter Register Pointer Reset */ +#define ETH_PMT_FLAG_WKFR (ETH_MAC_PMTCTLR_WKFR) /*!< Wake-Up Frame Received */ +#define ETH_PMT_FLAG_MPFR (ETH_MAC_PMTCTLR_MPFR) /*!< Magic Packet Received */ +/** + * @} + */ + +/** + * @defgroup ETH_PMT_Wakeup_Source ETH PMT Wakeup Source + * @{ + */ +#define ETH_PMT_WAKEUP_GLOBAL_UNICAST (ETH_MAC_PMTCTLR_GLUB) /*!< Global unicast */ +#define ETH_PMT_WAKEUP_WAKEUP_FRAME (ETH_MAC_PMTCTLR_WKEN) /*!< Wake-Up Frame */ +#define ETH_PMT_WAKEUP_MAGIC_PACKET (ETH_MAC_PMTCTLR_MPEN) /*!< Magic Packet */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Counter_Preset_Mode ETH MMC Counter Preset Mode + * @{ + */ +#define ETH_MMC_COUNTER_PRESETMODE_DISABLE (0UL) /*!< Disable preset */ +#define ETH_MMC_COUNTER_PRESETMODE_HALFVALUE (ETH_MMC_MMCCTLR_MCPSET) /*!< Half-Value preset: 0x7FF0 */ +#define ETH_MMC_COUNTER_PRESETMODE_FULLVALUE (ETH_MMC_MMCCTLR_MCPSEL | ETH_MMC_MMCCTLR_MCPSET) /*!< Full-Value preset: 0xFFF0 */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Read_Reset ETH MMC Read Reset + * @{ + */ +#define ETH_MMC_READ_RESET_DISABLE (0UL) +#define ETH_MMC_READ_RESET_ENABLE (ETH_MMC_MMCCTLR_ROR) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Counter_Reload ETH MMC Counter Reload + * @{ + */ +#define ETH_MMC_COUNTER_RELOAD_DISABLE (ETH_MMC_MMCCTLR_COS) +#define ETH_MMC_COUNTER_RELOAD_ENABLE (0UL) +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Tx_Flag ETH MMC Tx Flag + * @{ + */ +#define ETH_MMC_FLAG_TXEDEIS (ETH_MMC_TRSSTSR_TXEDEIS) /*!< When Tx excessive deferral error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXUGIS (ETH_MMC_TRSSTSR_TXUGIS) /*!< When Tx unicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXCAEIS (ETH_MMC_TRSSTSR_TXCAEIS) /*!< When Tx carrier error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXECEIS (ETH_MMC_TRSSTSR_TXECEIS) /*!< When Tx excessive collision error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXLCEIS (ETH_MMC_TRSSTSR_TXLCEIS) /*!< When Tx deferral collision error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXDEEIS (ETH_MMC_TRSSTSR_TXDEEIS) /*!< When Tx deferral error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXMGIS (ETH_MMC_TRSSTSR_TXMGIS) /*!< When Tx multicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_TXBGIS (ETH_MMC_TRSSTSR_TXBGIS) /*!< When Tx broadcast good frame counter reaches half or all the maximum value */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Rx_Flag ETH MMC Rx Flag + * @{ + */ +#define ETH_MMC_FLAG_RXOEIS (ETH_MMC_REVSTSR_RXOEIS) /*!< When Rx out of scope error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXLEIS (ETH_MMC_REVSTSR_RXLEIS) /*!< When Rx length error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXUGIS (ETH_MMC_REVSTSR_RXUGIS) /*!< When Rx unicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXREIS (ETH_MMC_REVSTSR_RXREIS) /*!< When Rx short error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXAEIS (ETH_MMC_REVSTSR_RXAEIS) /*!< When Rx alignment error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXCEIS (ETH_MMC_REVSTSR_RXCEIS) /*!< When Rx crc error frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXMGIS (ETH_MMC_REVSTSR_RXMGIS) /*!< When Rx multicast good frame counter reaches half or all the maximum value */ +#define ETH_MMC_FLAG_RXBGIS (ETH_MMC_REVSTSR_RXBGIS) /*!< When Rx broadcast good frame counter reaches half or all the maximum value */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Tx_Interrupt ETH MMC Tx Interrupt + * @{ + */ +#define ETH_MMC_INT_TXEDEIM (ETH_MMC_TITCTLR_TXEDEIM) /*!< Tx excessive deferral error frame interrupt */ +#define ETH_MMC_INT_TXUGIM (ETH_MMC_TITCTLR_TXUGIM) /*!< Tx unicast good frame interrupt */ +#define ETH_MMC_INT_TXCAEIM (ETH_MMC_TITCTLR_TXCAEIM) /*!< Tx carrier error frame interrupt */ +#define ETH_MMC_INT_TXECEIM (ETH_MMC_TITCTLR_TXECEIM) /*!< Tx excessive collision error frame interrupt */ +#define ETH_MMC_INT_TXLCEIM (ETH_MMC_TITCTLR_TXLCEIM) /*!< Tx deferral collision error frame interrupt */ +#define ETH_MMC_INT_TXDEEIM (ETH_MMC_TITCTLR_TXDEEIM) /*!< Tx deferral error frame interrupt */ +#define ETH_MMC_INT_TXMGIM (ETH_MMC_TITCTLR_TXMGIM) /*!< Tx multicast good frame interrupt */ +#define ETH_MMC_INT_TXBGIM (ETH_MMC_TITCTLR_TXBGIM) /*!< Tx broadcast good frame interrupt */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Rx_Interrupt ETH MMC Rx Interrupt + * @{ + */ +#define ETH_MMC_INT_RXOEIM (ETH_MMC_RITCTLR_RXOEIM) /*!< Rx out of scope error frame interrupt */ +#define ETH_MMC_INT_RXLEIM (ETH_MMC_RITCTLR_RXLEIM) /*!< Rx length error frame interrupt */ +#define ETH_MMC_INT_RXUGIM (ETH_MMC_RITCTLR_RXUGIM) /*!< Rx unicast good frame interrupt */ +#define ETH_MMC_INT_RXREIM (ETH_MMC_RITCTLR_RXREIM) /*!< Rx short error frame interrupt */ +#define ETH_MMC_INT_RXAEIM (ETH_MMC_RITCTLR_RXAEIM) /*!< Rx alignment error frame interrupt */ +#define ETH_MMC_INT_RXCEIM (ETH_MMC_RITCTLR_RXCEIM) /*!< Rx crc error frame interrupt */ +#define ETH_MMC_INT_RXMGIM (ETH_MMC_RITCTLR_RXMGIM) /*!< Rx multicast good frame interrupt */ +#define ETH_MMC_INT_RXBGIM (ETH_MMC_RITCTLR_RXBGIM) /*!< Rx broadcast good frame interrupt */ +/** + * @} + */ + +/** + * @defgroup ETH_MMC_Statistical_Register ETH MMC Statistical Register + * @{ + */ +#define ETH_MMC_REG_TXBRGFR (0x011CU) /*!< Tx broadcast good frame Statistical Register */ +#define ETH_MMC_REG_TXMUGFR (0x0120U) /*!< Tx multicast good frame Statistical Register */ +#define ETH_MMC_REG_TXDEEFR (0x0154U) /*!< Tx deferral error frame Statistical Register */ +#define ETH_MMC_REG_TXLCEFR (0x0158U) /*!< Tx deferral collision error frame Statistical Register */ +#define ETH_MMC_REG_TXECEFR (0x015CU) /*!< Tx excessive collision error frame Statistical Register */ +#define ETH_MMC_REG_TXCAEFR (0x0160U) /*!< Tx carrier error frame Statistical Register */ +#define ETH_MMC_REG_TXUNGFR (0x0168U) /*!< Tx unicast good frame Statistical Register */ +#define ETH_MMC_REG_TXEDEFR (0x016CU) /*!< Tx excessive deferral error frame Statistical Register */ +#define ETH_MMC_REG_RXBRGFR (0x018CU) /*!< Rx broadcast good frame Statistical Register */ +#define ETH_MMC_REG_RXMUGFR (0x0190U) /*!< Rx multicast good frame Statistical Register */ +#define ETH_MMC_REG_RXCREFR (0x0194U) /*!< Rx crc error frame Statistical Register */ +#define ETH_MMC_REG_RXALEFR (0x0198U) /*!< Rx alignment error frame Statistical Register */ +#define ETH_MMC_REG_RXRUEFR (0x019CU) /*!< Rx short error frame Statistical Register */ +#define ETH_MMC_REG_RXUNGFR (0x01C4U) /*!< Rx unicast good frame Statistical Register */ +#define ETH_MMC_REG_RXLEEFR (0x01C8U) /*!< Rx length error frame Statistical Register */ +#define ETH_MMC_REG_RXOREFR (0x01CCU) /*!< Rx out of scope error frame Statistical Register */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Frame_DA_Filter ETH PTP Frame DA Filter + * @{ + */ +#define ETH_PTP_FRAME_DA_FILTER_DISABLE (0x00800000UL) +#define ETH_PTP_FRAME_DA_FILTER_ENABLE (ETH_PTP_TSPCTLR_TSPADF) +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Snapshot_Datagram_Type ETH PTP Snapshot Datagram Type + * @{ + */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY (0UL) /*!< SYNC Follow_Up Delay_Req Delay_Resp */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC (ETH_PTP_TSPCTLR_TSPMTSEL_0) /*!< SYNC */ +#define ETH_PTP_DATAGRAM_TYPE_DELAY (ETH_PTP_TSPCTLR_TSPMTSEL_1 | ETH_PTP_TSPCTLR_TSPMTSEL_0) /*!< Delay_Req */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY_PDELAY (ETH_PTP_TSPCTLR_TSPMTSEL_2) /*!< SYNC Follow_Up Delay_Req Delay_Resp Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_PDELAY (ETH_PTP_TSPCTLR_TSPMTSEL_2 | ETH_PTP_TSPCTLR_TSPMTSEL_0) /*!< SYNC Pdelay_Req Pdelay_Resp */ +#define ETH_PTP_DATAGRAM_TYPE_DELAY_PDEALY (ETH_PTP_TSPCTLR_TSPMTSEL_2 | ETH_PTP_TSPCTLR_TSPMTSEL_1 | ETH_PTP_TSPCTLR_TSPMTSEL_0) /*!< Delay_Req Pdelay_Req Pdelay_Resp */ +#define ETH_PTP_DATAGRAM_TYPE_SYNC_DELAY (ETH_PTP_TSPCTLR_TSPMTSEL_3) /*!< SYNC Delay_Req */ +#define ETH_PTP_DATAGRAM_TYPE_PDELAY (ETH_PTP_TSPCTLR_TSPMTSEL_3 | ETH_PTP_TSPCTLR_TSPMTSEL_2) /*!< Pdelay_Req Pdelay_Resp */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Snapshot_Frame_Type ETH PTP Snapshot Frame Type + * @{ + */ +#define ETH_PTP_FRAME_TYPE_IPV4FRAME (ETH_PTP_TSPCTLR_TSPOVIPV4) /*!< Time stamp snapshot for IPv4 frame */ +#define ETH_PTP_FRAME_TYPE_IPV6FRAME (ETH_PTP_TSPCTLR_TSPOVIPV6) /*!< Time stamp snapshot for IPv6 frame */ +#define ETH_PTP_FRAME_TYPE_ETHERNETFRAME (ETH_PTP_TSPCTLR_TSPOVETH) /*!< Time stamp snapshot for PTP over ethernet frame */ +#define ETH_PTP_FRAME_TYPE_ALL_RECEIVEFRAME (ETH_PTP_TSPCTLR_TSPEALL) /*!< Time stamp snapshot for all received frame */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Datagram_Version ETH PTP Datagram Version + * @{ + */ +#define ETH_PTP_DATAGRAM_VERSION_IEEE1588V1 (0UL) +#define ETH_PTP_DATAGRAM_VERSION_IEEE1588V2 (ETH_PTP_TSPCTLR_TSPVER) +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Subsecond_Scale ETH PTP Subsecond Scale + * @{ + */ +#define ETH_PTP_SUBSECOND_SCALE_HEX (0UL) /*!< The Second register increase 1 when SubSecond count to 0x7FFFFFFFH */ +#define ETH_PTP_SUBSECOND_SCALE_DEC (ETH_PTP_TSPCTLR_TSPSSR) /*!< The Second register increase 1 when SubSecond count to 0x3B9AC9FFH */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Calibration_Mode ETH PTP Calibration Mode + * @{ + */ +#define ETH_PTP_CALIBRATION_MODE_COARSE (0UL) /*!< Coarse calibration */ +#define ETH_PTP_CALIBRATION_MODE_FINE (ETH_PTP_TSPCTLR_TSPUPSEL) /*!< Fine calibration */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Time_Update_Sign ETH PTP Time Update Sign + * @{ + */ +#define ETH_PTP_TIME_UPDATE_SIGN_MINUS (0UL) /*!< Minus for update register value */ +#define ETH_PTP_TIME_UPDATE_SIGN_PLUS (ETH_PTP_TMUNSER_TSPUPNS) /*!< Plus for update register value */ +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Flag ETH PTP Flag + * @{ + */ +#define ETH_PTP_FLAG_TSERR1 (ETH_PTP_TSPSTSR_TSERR1) /*!< Target time 1 error */ +#define ETH_PTP_FLAG_TSTAR1 (ETH_PTP_TSPSTSR_TSTAR1) /*!< Target time 1 reached */ +#define ETH_PTP_FLAG_TSERR0 (ETH_PTP_TSPSTSR_TSERR0) /*!< Target time 0 error */ +#define ETH_PTP_FLAG_TSTAR0 (ETH_PTP_TSPSTSR_TSTAR0) /*!< Target time 0 reached */ +#define ETH_PTP_FLAG_TSOVF (ETH_PTP_TSPSTSR_TSOVF) /*!< System time overflow */ +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Target_Channel ETH PPS Target Channel + * @{ + */ +#define ETH_PPS_TARGET_CH0 (0x00U) +#define ETH_PPS_TARGET_CH1 (0x01U) +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Target_Time_Function ETH PPS Target Time Function + * @{ + */ +#define ETH_PPS_TARGET_TIME_FUNC_INT_EVENT (0UL) /*!< The Target register is used only for interrupt output event */ +#define ETH_PPS_TARGET_TIME_FUNC_INT_PPS_EVENT (ETH_PTP_PPSCTLR_TT0SEL_1) /*!< The Target register is used for interrupt out event and PPS single output event */ +#define ETH_PPS_TARGET_TIME_FUNC_PPS_EVENT (ETH_PTP_PPSCTLR_TT0SEL) /*!< The Target register is used for PPS single output event */ +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Output_Mode ETH PPS Output Mode + * @note PPS1(ETH_PPS_TARGET_CH1) only supports single output mode(ETH_PPS_OUTPUT_MODE_SINGLE). + * @{ + */ +#define ETH_PPS_OUTPUT_MODE_CONTINUE (0UL) /*!< Continuous output mode */ +#define ETH_PPS_OUTPUT_MODE_SINGLE (ETH_PTP_PPSCTLR_PPSOMD) /*!< Single output mode */ +/** + * @} + */ + +/** + * @defgroup ETH_PPS_Output_Frequency ETH PPS Output Frequency + * @note PPS1(ETH_PPS_TARGET_CH1) only supports generate a pulse(ETH_PPS_OUTPUT_ONE_PULSE). + * @{ + */ +#define ETH_PPS_OUTPUT_FREQ_1HZ (0UL) /*!< Ouput pulse is 1HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_2HZ (ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 2HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_4HZ (ETH_PTP_PPSCTLR_PPSFRE0_1) /*!< Ouput pulse is 4HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_8HZ (ETH_PTP_PPSCTLR_PPSFRE0_1 | ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 8HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_16HZ (ETH_PTP_PPSCTLR_PPSFRE0_2) /*!< Ouput pulse is 16HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_32HZ (ETH_PTP_PPSCTLR_PPSFRE0_2 | ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 32HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_64HZ (ETH_PTP_PPSCTLR_PPSFRE0_2 | ETH_PTP_PPSCTLR_PPSFRE0_1) /*!< Ouput pulse is 64HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_128HZ (ETH_PTP_PPSCTLR_PPSFRE0_2 | ETH_PTP_PPSCTLR_PPSFRE0_1 | ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 128HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_256HZ (ETH_PTP_PPSCTLR_PPSFRE0_3) /*!< Ouput pulse is 256HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_512HZ (ETH_PTP_PPSCTLR_PPSFRE0_3 | ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 512HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_1024HZ (ETH_PTP_PPSCTLR_PPSFRE0_3 | ETH_PTP_PPSCTLR_PPSFRE0_1) /*!< Ouput pulse is 1024HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_2048HZ (ETH_PTP_PPSCTLR_PPSFRE0_3 | ETH_PTP_PPSCTLR_PPSFRE0_1 | ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 2048HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_4096HZ (ETH_PTP_PPSCTLR_PPSFRE0_3 | ETH_PTP_PPSCTLR_PPSFRE0_2) /*!< Ouput pulse is 4096HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_8192HZ (ETH_PTP_PPSCTLR_PPSFRE0_3 | ETH_PTP_PPSCTLR_PPSFRE0_2 | ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< Ouput pulse is 8192HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_16384HZ (ETH_PTP_PPSCTLR_PPSFRE0_3 | ETH_PTP_PPSCTLR_PPSFRE0_2 | ETH_PTP_PPSCTLR_PPSFRE0_1) /*!< Ouput pulse is 16384HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_FREQ_32768HZ (ETH_PTP_PPSCTLR_PPSFRE0) /*!< Ouput pulse is 32768HZ in continuous ouput mode */ +#define ETH_PPS_OUTPUT_ONE_PULSE (ETH_PTP_PPSCTLR_PPSFRE0_0) /*!< One pulse is generated in single ouput mode */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup ETH_Global_Functions + * @{ + */ + +/** + * @brief Generate MAC pause control frame. + * @param None + * @retval None + */ +__STATIC_INLINE void ETH_MAC_GeneratePauseCtrlFrame(void) +{ + WRITE_REG32(bM4_ETH->MAC_FLOCTLR_b.FCA_BPA, Enable); +} + +/** + * @brief Get MAC flow control status. + * @param None + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +__STATIC_INLINE en_flag_status_t ETH_MAC_GetFlowCtrlStatus(void) +{ + return ((en_flag_status_t)READ_REG32(bM4_ETH->MAC_FLOCTLR_b.FCA_BPA)); +} + +/** + * @brief Resume the DMA Transmit. + * @param None + * @retval None + */ +__STATIC_INLINE void ETH_DMA_ResumeTransmit(void) +{ + WRITE_REG32(M4_ETH->DMA_TXPOLLR, 0U); +} + +/** + * @brief Resume the DMA Receive. + * @param None + * @retval None + */ +__STATIC_INLINE void ETH_DMA_ResumeReceive(void) +{ + WRITE_REG32(M4_ETH->DMA_RXPOLLR, 0U); +} + +/** + * @brief Get DMA error status. + * @param None + * @retval uint32_t The new DMA error status + * The error status may be one of the following values: + * - ETH_DMA_ERRORSTATE_RX_WRITEDATA: TxDMA generates error while reading descriptor + * - ETH_DMA_ERRORSTATE_TX_READDATA: TxDMA generates error while reading descriptor + * - ETH_DMA_ERRORSTATE_RX_WRITEDESC: TxDMA generates error while reading descriptor + * - ETH_DMA_ERRORSTATE_TX_WRITEDESC: TxDMA generates error while reading descriptor + * - ETH_DMA_ERRORSTATE_RX_READDESC: TxDMA generates error while reading descriptor + * - ETH_DMA_ERRORSTATE_TX_READDESC: TxDMA generates error while reading descriptor + */ +__STATIC_INLINE uint32_t ETH_DMA_GetErrorStatus(void) +{ + return (READ_REG32_BIT(M4_ETH->DMA_DMASTSR, ETH_DMA_DMASTSR_EBUS)); +} + +/** + * @brief Get DMA transmit status. + * @param None + * @retval uint32_t The new DMA transmit status + * The transmit status may be one of the following values: + * - ETH_DMA_TRANSMITSTATE_STOPPED: Stopped - Reset or Stop Tx Command issued + * - ETH_DMA_TRANSMITSTATE_FETCHING: Running - Fetching the Tx descriptor + * - ETH_DMA_TRANSMITSTATE_WAITING: Running - Waiting for status + * - ETH_DMA_TRANSMITSTATE_READING: Running - Reading the data from host memory + * - ETH_DMA_TRANSMITSTATE_WRITING: Running - Writing the time stamp + * - ETH_DMA_TRANSMITSTATE_SUSPENDED: Suspended - Tx Descriptor unavailable + * - ETH_DMA_TRANSMITSTATE_CLOSING: Running - Closing Rx descriptor + */ +__STATIC_INLINE uint32_t ETH_DMA_GetTransmitStatus(void) +{ + return (READ_REG32_BIT(M4_ETH->DMA_DMASTSR, ETH_DMA_DMASTSR_TSTS)); +} + +/** + * @brief Get DMA receive status. + * @param None + * @retval uint32_t The new DMA receive status + * The receive status may be one of the following values: + * - ETH_DMA_RECEIVESTATE_STOPPED: Stopped - Reset or Stop Rx Command issued + * - ETH_DMA_RECEIVESTATE_FETCHING: Running - Fetching the Rx descriptor + * - ETH_DMA_RECEIVESTATE_WAITING: Running - Waiting for packet + * - ETH_DMA_RECEIVESTATE_SUSPENDED: Suspended - Rx Descriptor unavailable + * - ETH_DMA_RECEIVESTATE_CLOSING: Running - Closing descriptor + * - ETH_DMA_RECEIVESTATE_WRITING: Running - Writing the time stamp + * - ETH_DMA_RECEIVESTATE_QUEUING: Running - Queuing the receive frame into host memory + */ +__STATIC_INLINE uint32_t ETH_DMA_GetReceiveStatus(void) +{ + return (READ_REG32_BIT(M4_ETH->DMA_DMASTSR, ETH_DMA_DMASTSR_RSTS)); +} + +/** + * @brief Get DMA Rx Overflow Missed Frame Counter value. + * @param None + * @retval uint32_t Rx Overflow Missed Frame Counter value + */ +__STATIC_INLINE uint32_t ETH_DMA_GetRxOvfMissFrameCnt(void) +{ + return ((READ_REG32_BIT(M4_ETH->DMA_RFRCNTR, ETH_DMA_RFRCNTR_OVFCNT)) >> ETH_DMA_RFRCNTR_OVFCNT_POS); +} + +/** + * @brief Get DMA Buffer Unavailable Missed Frame Counter value. + * @param None + * @retval uint32_t Buffer Unavailable Missed Frame Counter value + */ +__STATIC_INLINE uint32_t ETH_DMA_GetBufferUnavaiMissFrameCnt(void) +{ + return (READ_REG32_BIT(M4_ETH->DMA_RFRCNTR, ETH_DMA_RFRCNTR_UNACNT)); +} + +/** + * @brief Get DMA current Tx descriptor start address. + * @param None + * @retval uint32_t Transmit descriptor start address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurTxDescAddr(void) +{ + return (READ_REG32(M4_ETH->DMA_CHTXDER)); +} + +/** + * @brief Get DMA current Rx descriptor start address. + * @param None + * @retval uint32_t Receive descriptor start address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurRxDescAddr(void) +{ + return (READ_REG32(M4_ETH->DMA_CHRXDER)); +} + +/** + * @brief Get DMA current Tx buffer address. + * @param None + * @retval uint32_t Transmit buffer address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurTxBufferAddr(void) +{ + return (READ_REG32(M4_ETH->DMA_CHTXBFR)); +} + +/** + * @brief Get DMA current Rx buffer address. + * @param None + * @retval uint32_t Receive buffer address + */ +__STATIC_INLINE uint32_t ETH_DMA_GetCurRxBufferAddr(void) +{ + return (READ_REG32(M4_ETH->DMA_CHRXBFR)); +} + +/** + * @brief Get PMT wakeup frame filter register pointer index. + * @param None + * @retval uint8_t Filter register pointer index. + */ +__STATIC_INLINE uint8_t ETH_PMT_GetWakeupFramePointerIndex(void) +{ + return ((uint8_t)(READ_REG32_BIT(M4_ETH->MAC_PMTCTLR, ETH_MAC_PMTCTLR_RTWKPT) >> ETH_MAC_PMTCTLR_RTWKPT_POS)); +} + +/** + * @brief Get PTP snapshot frame type. + * @param None + * @retval uint32_t Receive frame type + */ +__STATIC_INLINE uint32_t ETH_PTP_GetSnapFrameType(void) +{ + return (READ_REG32_BIT(M4_ETH->PTP_TSPCTLR, + (ETH_PTP_TSPCTLR_TSPOVIPV4 | ETH_PTP_TSPCTLR_TSPOVIPV6 | + ETH_PTP_TSPCTLR_TSPOVETH | ETH_PTP_TSPCTLR_TSPEALL))); +} + +en_result_t ETH_DeInit(void); +en_result_t ETH_Init(stc_eth_handle_t *pstcEthHandle, stc_eth_init_t *pstcEthInit); +en_result_t ETH_CommStructInit(stc_eth_comm_init_t *pstcCommInit); +en_result_t ETH_StructInit(stc_eth_init_t *pstcEthInit); +en_result_t ETH_Start(void); +en_result_t ETH_Stop(void); + +/* PHY Functions */ +en_result_t ETH_PHY_WriteRegister(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t u16RegVal); +en_result_t ETH_PHY_ReadRegister(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t *pu16RegVal); +en_result_t ETH_PHY_LoopBackCmd(stc_eth_handle_t *pstcEthHandle, en_functional_state_t enNewSta); + +/* MAC Functions */ +void ETH_MAC_DeInit(void); +en_result_t ETH_MAC_Init(stc_eth_handle_t *pstcEthHandle, const stc_eth_mac_init_t *pstcMacInit); +en_result_t ETH_MAC_StructInit(stc_eth_mac_init_t *pstcMacInit); +void ETH_MAC_SetDuplexSpeed(uint32_t u32DuplexMode, uint32_t u32Speed); +void ETH_MAC_SetHashTable(uint32_t u32HashHigh, uint32_t u32HashLow); +void ETH_MAC_SetTxVlanTagVal(uint16_t u16TxTag); +void ETH_MAC_SetRxVlanTagVal(uint16_t u16RxTag); +void ETH_MAC_SetRxVlanHashTable(uint16_t u16HashVal); +void ETH_MAC_LoopBackCmd(en_functional_state_t enNewSta); +void ETH_MAC_GeneratePauseCtrlFrame(void); +void ETH_MAC_BackPressureCmd(en_functional_state_t enNewSta); +void ETH_MAC_TransmitCmd(en_functional_state_t enNewSta); +void ETH_MAC_ReceiveCmd(en_functional_state_t enNewSta); +void ETH_MAC_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta); +en_flag_status_t ETH_MAC_GetIntStatus(uint32_t u32Flag); +en_flag_status_t ETH_MAC_GetFlowCtrlStatus(void); + +/* MAC Address Functions */ +void ETH_MACADDR_DeInit(uint32_t u32Index); +en_result_t ETH_MACADDR_Init(uint32_t u32Index, const stc_eth_mac_addr_config_t *pstcMacAddrInit); +en_result_t ETH_MACADDR_StructInit(stc_eth_mac_addr_config_t *pstcMacAddrInit); +en_result_t ETH_MACADDR_SetAddress(uint32_t u32Index, uint8_t au8Addr[]); +en_result_t ETH_MACADDR_GetAddress(uint32_t u32Index, uint8_t au8Addr[]); +void ETH_MACADDR_SetFilterMode(uint32_t u32Index, uint32_t u32Mode); +void ETH_MACADDR_SetFilterMask(uint32_t u32Index, uint32_t u32Mask); + +/* MAC L3L4 Filter Functions */ +void ETH_MAC_L3L4FilterDeInit(void); +en_result_t ETH_MAC_L3L4FilterInit(const stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit); +en_result_t ETH_MAC_L3L4FilterStructInit(stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit); +void ETH_MAC_L3L4FilterCmd(en_functional_state_t enNewSta); +void ETH_MAC_SetPortFilterProtocol(uint32_t u32PortProtocol); +void ETH_MAC_SetDestPortFilterVal(uint16_t u16Port); +void ETH_MAC_SetSrcPortFilterVal(uint16_t u16Port); +void ETH_MAC_SetAddrFilterProtocol(uint32_t u32AddrProtocol); +void ETH_MAC_SetIpv4DestAddrFilterVal(uint32_t u32Addr); +void ETH_MAC_SetIpv4SrcAddrFilterVal(uint32_t u32Addr); +en_result_t ETH_MAC_SetIpv6AddrFilterVal(const uint32_t au32Addr[]); + +/* DMA Functions */ +void ETH_DMA_DeInit(void); +en_result_t ETH_DMA_Init(const stc_eth_dma_init_t *pstcDmaInit); +en_result_t ETH_DMA_StructInit(stc_eth_dma_init_t *pstcDmaInit); +en_result_t ETH_DMA_SoftwareReset(void); +void ETH_DMA_ResumeTransmit(void); +void ETH_DMA_ResumeReceive(void); +void ETH_DMA_SetTransPrioRatio(uint32_t u32PrioRatio); +void ETH_DMA_SetRxWatchdogCounter(uint8_t u8Value); +en_result_t ETH_DMA_FlushTransmitFIFO(void); +void ETH_DMA_TransmitCmd(en_functional_state_t enNewSta); +void ETH_DMA_ReceiveCmd(en_functional_state_t enNewSta); +void ETH_DMA_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta); +en_flag_status_t ETH_DMA_GetStatus(uint32_t u32Flag); +uint32_t ETH_DMA_GetErrorStatus(void); +uint32_t ETH_DMA_GetTransmitStatus(void); +uint32_t ETH_DMA_GetReceiveStatus(void); +en_flag_status_t ETH_DMA_GetOvfStatus(uint32_t u32Flag); +uint32_t ETH_DMA_GetRxOvfMissFrameCnt(void); +uint32_t ETH_DMA_GetBufferUnavaiMissFrameCnt(void); +uint32_t ETH_DMA_GetCurTxDescAddr(void); +uint32_t ETH_DMA_GetCurRxDescAddr(void); +uint32_t ETH_DMA_GetCurTxBufferAddr(void); +uint32_t ETH_DMA_GetCurRxBufferAddr(void); + +/* DMA descriptor Functions */ +en_result_t ETH_DMA_TxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcTxDescTab[], const uint8_t au8TxBuffer[], uint32_t u32TxBufferCnt); +en_result_t ETH_DMA_RxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcRxDescTab[], const uint8_t au8RxBuffer[], uint32_t u32RxBufferCnt); +en_result_t ETH_DMA_SetTransmitFrame(stc_eth_handle_t *pstcEthHandle, uint32_t u32FrameLength); +en_result_t ETH_DMA_GetReceiveFrame(stc_eth_handle_t *pstcEthHandle); +en_result_t ETH_DMA_GetReceiveFrame_Interrupt(stc_eth_handle_t *pstcEthHandle); +en_result_t ETH_DMA_SetTxDescOwn(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Owner); +en_result_t ETH_DMA_SetTxDescBufferSize(stc_eth_dma_desc_t *pstcTxDesc, uint8_t u8BufferNum, uint32_t u32BufferSize); +en_result_t ETH_DMA_TxDescChecksumInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32ChecksumMode); +en_result_t ETH_DMA_TxDescVlanInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32VlanMode); +en_result_t ETH_DMA_TxDescSAInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32SAMode); +en_result_t ETH_DMA_TxDescCRCCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta); +en_result_t ETH_DMA_TxDescPADCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta); +en_result_t ETH_DMA_TxDescTimestamp(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta); +en_result_t ETH_DMA_TxDescReplaceCRCCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta); +en_result_t ETH_DMA_TxDescIntCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta); +en_flag_status_t ETH_DMA_GetTxDescStatus(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Flag); +en_result_t ETH_DMA_GetTxDescCollisionCnt(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32ColliCnt); +en_result_t ETH_DMA_GetTxDescTimeStamp(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32High, uint32_t *pu32Low); +en_result_t ETH_DMA_SetRxDescOwn(stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Owner); +en_result_t ETH_DMA_RxDescIntCmd(stc_eth_dma_desc_t *pstcRxDesc, en_functional_state_t enNewSta); +en_flag_status_t ETH_DMA_GetRxDescStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag); +en_flag_status_t ETH_DMA_GetRxDescExtendStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag); +en_result_t ETH_DMA_GetRxDescPayloadType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32PayloadType); +en_result_t ETH_DMA_GetRxDescDatagramType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32DatagramType); +en_result_t ETH_DMA_GetRxDescFrameLength(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32FrameLength); +en_result_t ETH_DMA_GetRxDescBufferSize(const stc_eth_dma_desc_t *pstcRxDesc, uint8_t u8BufferNum, uint32_t *pu32BufferSize); +en_result_t ETH_DMA_GetRxDescTimeStamp(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32High, uint32_t *pu32Low); + +/* MAC PMT Functions */ +en_result_t ETH_PMT_ResetWakeupFramePointer(void); +en_result_t ETH_PMT_WriteWakeupFrameRegister(const uint32_t au32RegBuffer[]); +void ETH_PMT_ForwardWakeupFrameCmd(en_functional_state_t enNewSta); +void ETH_PMT_WakeupSourceCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewSta); +en_result_t ETH_PMT_EnterPowerDown(void); +en_flag_status_t ETH_PMT_GetStatus(uint32_t u32Flag); +uint8_t ETH_PMT_GetWakeupFramePointerIndex(void); + +/* MMC Functions */ +en_result_t ETH_MMC_DeInit(void); +en_result_t ETH_MMC_Init(const stc_eth_mmc_init_t *pstcMmcInit); +en_result_t ETH_MMC_StructInit(stc_eth_mmc_init_t *pstcMmcInit); +en_result_t ETH_MMC_CounterReset(void); +void ETH_MMC_ResetAfterReadCmd(en_functional_state_t enNewSta); +void ETH_MMC_Cmd(en_functional_state_t enNewSta); +void ETH_MMC_TxIntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta); +void ETH_MMC_RxIntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta); +en_flag_status_t ETH_MMC_GetTxStatus(uint32_t u32Flag); +en_flag_status_t ETH_MMC_GetRxStatus(uint32_t u32Flag); +uint32_t ETH_MMC_GetRegister(uint32_t u32Reg); + +/* PTP Functions */ +void ETH_PTP_DeInit(void); +en_result_t ETH_PTP_Init(const stc_eth_ptp_init_t *pstcPtpInit); +en_result_t ETH_PTP_StructInit(stc_eth_ptp_init_t *pstcPtpInit); +void ETH_PTP_SetSnapDatagramType(uint32_t u32DatagramType); +void ETH_PTP_SetSnapFrameType(uint32_t u32FrameType); +uint32_t ETH_PTP_GetSnapFrameType(void); +void ETH_PTP_SetCalibMode(uint32_t u32CalibMode); +en_result_t ETH_PTP_UpdateBasicIncValue(void); +en_result_t ETH_PTP_UpdateSystemTime(void); +en_result_t ETH_PTP_SystemTimeInit(void); +en_result_t ETH_PTP_GetSystemTime(uint32_t *pu32Sec, uint32_t *pu32SubSec); +void ETH_PTP_SetIncValue(uint32_t u32BasicVal, uint8_t u8SubSecVal); +en_result_t ETH_PTP_GetIncValue(uint32_t *pu32BasicVal, uint8_t *pu8SubSecVal); +void ETH_PTP_SetUpdateTime(uint32_t u32Sign, uint32_t u32Sec, uint32_t u32SubSec); +void ETH_PTP_Cmd(en_functional_state_t enNewSta); +void ETH_PTP_IntCmd(en_functional_state_t enNewSta); +en_flag_status_t ETH_PTP_GetStatus(uint32_t u32Flag); + +/* PTP PPS Functions */ +void ETH_PPS_DeInit(uint8_t u8Ch); +en_result_t ETH_PPS_Init(uint8_t u8Ch, const stc_eth_pps_config_t *pstcPpsInit); +en_result_t ETH_PPS_StructInit(stc_eth_pps_config_t *pstcPpsInit); +void ETH_PPS_SetTargetTime(uint8_t u8Ch, uint32_t u32Sec, uint32_t u32SubSec); +void ETH_PPS_SetTargetTimeFunc(uint8_t u8Ch, uint32_t u32Func); +void ETH_PPS_SetPps0OutputMode(uint32_t u32OutputMode); +void ETH_PPS_SetPps0OutputFreq(uint32_t u32OutputFreq); + +/** + * @} + */ + +#endif /* DDL_ETH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_ETH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_fcm.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_fcm.h new file mode 100644 index 0000000000000000000000000000000000000000..8bbd68176c2d326333b1af16dd479e4942925c70 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_fcm.h @@ -0,0 +1,307 @@ +/** + ******************************************************************************* + * @file hc32f4a0_fcm.h + * @brief This file contains all the functions prototypes of the FCM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_FCM_H__ +#define __HC32F4A0_FCM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_FCM + * @{ + */ + +#if (DDL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Types FCM Global Types + * @{ + */ +/** + * @brief FCM Init structure definition + */ +typedef struct +{ + uint16_t u16LowerLimit; /*!< FCM lower limit value*/ + + uint16_t u16UpperLimit; /*!< FCM upper limit value*/ + + uint32_t u32TarClk; /*!< FCM target clock source selection, \ + @ref FCM_Init_Config for details */ + + uint32_t u32TarClkDiv; /*!< FCM target clock source division selection,\ + @ref FCM_Init_Config for details */ + + uint32_t u32ExRefClkEn; /*!< FCM external reference clock function config, \ + @ref FCM_Init_Config for details */ + + uint32_t u32RefClkEdge; /*!< FCM reference clock trigger edge selection,\ + @ref FCM_Init_Config for details */ + + uint32_t u32DigFilter; /*!< FCM digital filter function config, \ + @ref FCM_Init_Config for details */ + + uint32_t u32RefClk; /*!< FCM reference clock source selection, \ + @ref FCM_Init_Config for details */ + + uint32_t u32RefClkDiv; /*!< FCM reference clock source division selection, \ + @ref FCM_Init_Config for details */ + + uint32_t u32RstEn; /*!< FCM abnormal reset function config, \ + @ref FCM_Init_Config for details */ + + uint32_t u32IntRstSel; /*!< FCM abnormal detecting behavior selection, \ + @ref FCM_Init_Config */ + + uint32_t u32IntType; /*!< FCM interrupt type selection, \ + @ref FCM_Init_Config for details. */ +} stc_fcm_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Macros FCM Global Macros + * @{ + */ + +/** + * @defgroup FCM_Registers_Reset_Value FCM Registers Reset Value + * @{ + */ +#define FCM_REG_RESET_VALUE (0x00000000UL) +/** + * @} + */ + +/** + * @defgroup FCM_Init_Config FCM init config + * @{ + */ + +/** + * @brief FCM target clock source selection + */ +#define FCM_TAR_CLK_XTAL (0x00UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_XTAL32 (0x01UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_HRC (0x02UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_LRC (0x03UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_SWDTLRC (0x04UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_PCLK1 (0x05UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_PLLAP (0x06UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_MRC (0x07UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_PLLHP (0x08UL << FCM_MCCR_MCKS_POS) +#define FCM_TAR_CLK_RTCLRC (0x09UL << FCM_MCCR_MCKS_POS) + +/** + * @brief FCM target clock division + */ +#define FCM_TAR_CLK_DIV1 (0x00UL) +#define FCM_TAR_CLK_DIV4 (0x01UL) +#define FCM_TAR_CLK_DIV8 (0x02UL) +#define FCM_TAR_CLK_DIV32 (0x03UL) + +/** + * @brief FCM external reference clock function config + */ +#define FCM_EX_REF_OFF (0x00UL) +#define FCM_EX_REF_ON (FCM_RCCR_EXREFE) + +/** + * @brief FCM reference clock edge config + */ +#define FCM_REF_CLK_RISING (0x00UL) +#define FCM_REF_CLK_FALLING (FCM_RCCR_EDGES_0) +#define FCM_REF_CLK_BOTH (FCM_RCCR_EDGES_1) + +/** + * @brief FCM digital filter function config + */ +#define FCM_DF_OFF (0x00UL) +#define FCM_DF_MCKS_DIV1 (FCM_RCCR_DNFS_0) +#define FCM_DF_MCKS_DIV4 (FCM_RCCR_DNFS_1) +#define FCM_DF_MCKS_DIV16 (FCM_RCCR_DNFS) + +/** + * @brief FCM reference clock source selection + */ +#define FCM_REF_CLK_EXINPUT (0x00UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL (0x10UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_XTAL32 (0x11UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_HRC (0x12UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_LRC (0x13UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_SWDTLRC (0x14UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PCLK1 (0x15UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PCLKAP (0x16UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_MRC (0x17UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_PLLHP (0x18UL << FCM_RCCR_RCKS_POS) +#define FCM_REF_CLK_RTCLRC (0x19UL << FCM_RCCR_RCKS_POS) + +/** + * @brief FCM reference clock division + */ +#define FCM_REF_CLK_DIV32 (0x00UL) +#define FCM_REF_CLK_DIV128 (0x01UL) +#define FCM_REF_CLK_DIV1024 (0x02UL) +#define FCM_REF_CLK_DIV8192 (0x03UL) + +/** + * @brief FCM abnormal reset function config + */ +#define FCM_RST_OFF (0x00UL) +#define FCM_RST_ON (FCM_RIER_ERRE) + +/** + * @brief FCM abnormal behavior selection + */ +#define FCM_ERR_INT (0x00UL) +#define FCM_ERR_RESET (FCM_RIER_ERRINTRS) + +/** + * @brief FCM counter overflow interrupt config + */ +#define FCM_OVF_INT_OFF (0x00UL) +#define FCM_OVF_INT_ON (FCM_RIER_OVFIE) + +/** + * @brief FCM measure completed interrupt config + */ +#define FCM_END_INT_OFF (0x00UL) +#define FCM_END_INT_ON (FCM_RIER_MENDIE) + +/** + * @brief FCM error interrupt config + */ +#define FCM_ERR_INT_OFF (0x00UL) +#define FCM_ERR_INT_ON (FCM_RIER_ERRIE) + +/** + * @brief FCM interrupt mask + */ +#define FCM_INT_MSK (FCM_OVF_INT_ON | FCM_END_INT_ON | FCM_ERR_INT_ON) +/** + * @} + */ + +/** + * @defgroup FCM_Flag_Sel FCM status flag selection + * @{ + */ +#define FCM_FLAG_ERR (FCM_SR_ERRF) +#define FCM_FLAG_END (FCM_SR_MENDF) +#define FCM_FLAG_OVF (FCM_SR_OVF) +#define FCM_FLAG_MSK (FCM_SR_ERRF | FCM_SR_MENDF | FCM_SR_OVF) +/** + * @} + */ + +/** + * @} + */ + + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FCM_Global_Functions + * @{ + */ +/** + * @brief Set FCM upper limit value. + * @param [in] u16Lmt + * @retval None. + */ +__STATIC_INLINE void FCM_SetUpLimit(uint16_t u16Lmt) +{ + WRITE_REG32(M4_FCM->UVR, u16Lmt); +} + +/** + * @brief Set FCM lower limit value. + * @param u16Lmt + * @retval None + */ +__STATIC_INLINE void FCM_SetLowLimit(uint16_t u16Lmt) +{ + WRITE_REG32(M4_FCM->LVR, u16Lmt); +} + +en_result_t FCM_Init(const stc_fcm_init_t *pstcFcmInit); +en_result_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit); +void FCM_DeInit(void); +uint16_t FCM_GetCounter(void); +void FCM_SetUpLimit(uint16_t u16Lmt); +void FCM_SetLowLimit(uint16_t u16Lmt); +void FCM_SetTarClk(uint32_t u32Tar, uint32_t u32Div); +void FCM_SetRefClk(uint32_t u32Ref, uint32_t u32Div); +en_flag_status_t FCM_GetStatus(uint32_t u32Flag); +void FCM_ClearStatus(uint32_t u32Flag); +void FCM_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* DDL_FCM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_FCM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_fmac.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_fmac.h new file mode 100644 index 0000000000000000000000000000000000000000..4715b5498dada617ba929e84b6853ea3b82a38b4 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_fmac.h @@ -0,0 +1,214 @@ +/** + ******************************************************************************* + * @file hc32f4a0_fmac.h + * @brief This file contains all the functions prototypes of the FMAC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_FMAC_H__ +#define __HC32F4A0_FMAC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_FMAC + * @{ + */ + +#if (DDL_FMAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup FMAC_Global_Types FMAC Global Types + * @{ + */ + +/** + * @brief FMAC configuration structure + */ +typedef struct +{ + uint32_t u32FiltStage; /*!< FMAC filter stage number config. + This parameter can be a value of @ref FMAC_Filter_stage.*/ + uint32_t u32FiltShift; /*!< FMAC filter result right shift bits. + This parameter can be a value of @ref FMAC_Filter_shift.*/ + int16_t i16FiltFactor; /*!< FMAC filter factor config. + This parameter can be set -32768~32767 */ + uint32_t u32IntCmd; /*!< Enable or disable FMAC interrupt. + This parameter can be a value of @ref FMAC_Interrupt_Definition.*/ +}stc_fmac_init_t; + +/** + * @brief FMAC result definition + */ +typedef struct +{ + uint32_t u32ResultHigh; /*!< The high value of the result. */ + uint32_t u32ResultLow; /*!< The low value of the result. */ + +} stc_fmac_result_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup FMAC_Global_Macros FMAC Global Macros + * @{ + */ + +/** + * @defgroup FMAC_ENABLE FMAC Enable or Disable + * @{ + */ +#define FMAC_FUNC_ENABLE (FMAC_ENR_FMACEN) +#define FMAC_FUNC_DISABLE (0x0UL) +/** + * @} + */ + +/** + * @defgroup FMAC_Interrupt_Definition FMAC interrupt definition + * @{ + */ +#define FMAC_INT_ENABLE (FMAC_IER_INTEN) +#define FMAC_INT_DISABLE (0x0UL) +/** + * @} + */ + +/** @defgroup FMAC_Filter_shift FMAC filter shift times + * @{ + */ +#define FMAC_FILTER_SHIFT_0BIT (0U) +#define FMAC_FILTER_SHIFT_1BIT (1U) +#define FMAC_FILTER_SHIFT_2BIT (2U) +#define FMAC_FILTER_SHIFT_3BIT (3U) +#define FMAC_FILTER_SHIFT_4BIT (4U) +#define FMAC_FILTER_SHIFT_5BIT (5U) +#define FMAC_FILTER_SHIFT_6BIT (6U) +#define FMAC_FILTER_SHIFT_7BIT (7U) +#define FMAC_FILTER_SHIFT_8BIT (8U) +#define FMAC_FILTER_SHIFT_9BIT (9U) +#define FMAC_FILTER_SHIFT_10BIT (10U) +#define FMAC_FILTER_SHIFT_11BIT (11U) +#define FMAC_FILTER_SHIFT_12BIT (12U) +#define FMAC_FILTER_SHIFT_13BIT (13U) +#define FMAC_FILTER_SHIFT_14BIT (14U) +#define FMAC_FILTER_SHIFT_15BIT (15U) +#define FMAC_FILTER_SHIFT_16BIT (16U) +#define FMAC_FILTER_SHIFT_17BIT (17U) +#define FMAC_FILTER_SHIFT_18BIT (18U) +#define FMAC_FILTER_SHIFT_19BIT (19U) +#define FMAC_FILTER_SHIFT_20BIT (20U) +#define FMAC_FILTER_SHIFT_21BIT (21U) +/** + * @} + */ + +/** @defgroup FMAC_Filter_stage FMAC filter stage number + * @{ + */ +#define FMAC_FILTER_STAGE_0 (0U) +#define FMAC_FILTER_STAGE_1 (1U) +#define FMAC_FILTER_STAGE_2 (2U) +#define FMAC_FILTER_STAGE_3 (3U) +#define FMAC_FILTER_STAGE_4 (4U) +#define FMAC_FILTER_STAGE_5 (5U) +#define FMAC_FILTER_STAGE_6 (6U) +#define FMAC_FILTER_STAGE_7 (7U) +#define FMAC_FILTER_STAGE_8 (8U) +#define FMAC_FILTER_STAGE_9 (9U) +#define FMAC_FILTER_STAGE_10 (10U) +#define FMAC_FILTER_STAGE_11 (11U) +#define FMAC_FILTER_STAGE_12 (12U) +#define FMAC_FILTER_STAGE_13 (13U) +#define FMAC_FILTER_STAGE_14 (14U) +#define FMAC_FILTER_STAGE_15 (15U) +#define FMAC_FILTER_STAGE_16 (16U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup FMAC_Global_Functions + * @{ + */ +en_result_t FMAC_StructInit(stc_fmac_init_t* pstcInitStruct); +void FMAC_DeInit(M4_FMAC_TypeDef* FMACx); +en_result_t FMAC_Init(M4_FMAC_TypeDef* FMACx, const stc_fmac_init_t *pstcFmacInit); +void FMAC_Cmd(M4_FMAC_TypeDef* FMACx, en_functional_state_t enNewState); +void FMAC_SetResultShift(M4_FMAC_TypeDef* FMACx, uint32_t u32ShiftNum); +void FMAC_SetStageFactor(M4_FMAC_TypeDef* FMACx, uint32_t u32FilterStage, int16_t i16Factor); +void FMAC_IntCmd(M4_FMAC_TypeDef* FMACx, en_functional_state_t enNewState); +void FMAC_FIRInput(M4_FMAC_TypeDef* FMACx, int16_t i16Factor); +en_flag_status_t FMAC_GetStatus(const M4_FMAC_TypeDef* FMACx); +en_result_t FMAC_GetResult(const M4_FMAC_TypeDef* FMACx, stc_fmac_result_t *stcResult); +/** + * @} + */ + +#endif /* DDL_FMAC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_FMAC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_gpio.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..b87f3a2b8f54f8a3a91d181cb8abe0f2fa37e74a --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_gpio.h @@ -0,0 +1,1408 @@ +/** + ******************************************************************************* + * @file hc32f4a0_gpio.h + * @brief This file contains all the functions prototypes of the GPIO driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-09-21 Zhangxl Typo, missing FUNC_I2C3 defintion + 2020-10-27 Zhangxl Revise debug port definition + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_GPIO_H__ +#define __HC32F4A0_GPIO_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_GPIO + * @{ + */ + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Types GPIO Global Types + * @{ + */ + +/** + * @brief GPIO Pin Set and Reset enumeration + */ +typedef enum +{ + Pin_Reset = 0U, /*!< Pin reset */ + Pin_Set = 1U /*!< Pin set */ +} en_pin_state_t; + +/** + * @brief GPIO Init structure definition + */ +typedef struct +{ + uint16_t u16PinState; /*!< Set pin state to High or Low, @ref GPIO_PinState_Sel for details */ + uint16_t u16PinDir; /*!< Pin mode setting, @ref GPIO_PinDirection_Sel for details */ + uint16_t u16PinOType; /*!< Output type setting, @ref GPIO_PinOutType_Sel for details */ + uint16_t u16PinDrv; /*!< Pin drive capacity setting, @ref GPIO_PinDrv_Sel for details */ + uint16_t u16Latch; /*!< Pin latch setting, @ref GPIO_PinLatch_Sel for details */ + uint16_t u16PullUp; /*!< Internal pull-up resistor setting, @ref GPIO_PinPU_Sel for details */ + uint16_t u16Invert; /*!< Pin input/output invert setting, @ref GPIO_PinInvert_Sel */ + uint16_t u16PinIType; /*!< Input type setting, @ref GPIO_PinInType_Sel */ + uint16_t u16ExInt; /*!< External interrupt pin setting, @ref GPIO_PinExInt_Sel for details */ + uint16_t u16PinAttr; /*!< Digital or analog attribute setting, @ref GPIO_PinMode_Sel for details */ +} stc_gpio_init_t; +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Macros GPIO Global Macros + * @{ + */ + +/** @defgroup GPIO_pins_define GPIO pin source + * @{ + */ +#define GPIO_PIN_00 (0x0001U) /*!< Pin 00 selected */ +#define GPIO_PIN_01 (0x0002U) /*!< Pin 01 selected */ +#define GPIO_PIN_02 (0x0004U) /*!< Pin 02 selected */ +#define GPIO_PIN_03 (0x0008U) /*!< Pin 03 selected */ +#define GPIO_PIN_04 (0x0010U) /*!< Pin 04 selected */ +#define GPIO_PIN_05 (0x0020U) /*!< Pin 05 selected */ +#define GPIO_PIN_06 (0x0040U) /*!< Pin 06 selected */ +#define GPIO_PIN_07 (0x0080U) /*!< Pin 07 selected */ +#define GPIO_PIN_08 (0x0100U) /*!< Pin 08 selected */ +#define GPIO_PIN_09 (0x0200U) /*!< Pin 09 selected */ +#define GPIO_PIN_10 (0x0400U) /*!< Pin 10 selected */ +#define GPIO_PIN_11 (0x0800U) /*!< Pin 11 selected */ +#define GPIO_PIN_12 (0x1000U) /*!< Pin 12 selected */ +#define GPIO_PIN_13 (0x2000U) /*!< Pin 13 selected */ +#define GPIO_PIN_14 (0x4000U) /*!< Pin 14 selected */ +#define GPIO_PIN_15 (0x8000U) /*!< Pin 15 selected */ +#define GPIO_PIN_ALL (0xFFFFU) /*!< All pins selected */ + +#define GPIO_PIN_MASK (0xFFFFU) /*!< PIN mask for assert test */ + +/** + * @} + */ + +/** @defgroup GPIO_Port_source GPIO port source + * @{ + */ +#define GPIO_PORT_A (0x00U) /*!< Port A selected */ +#define GPIO_PORT_B (0x01U) /*!< Port B selected */ +#define GPIO_PORT_C (0x02U) /*!< Port C selected */ +#define GPIO_PORT_D (0x03U) /*!< Port D selected */ +#define GPIO_PORT_E (0x04U) /*!< Port E selected */ +#define GPIO_PORT_F (0x05U) /*!< Port F selected */ +#define GPIO_PORT_G (0x06U) /*!< Port G selected */ +#define GPIO_PORT_H (0x07U) /*!< Port H selected */ +#define GPIO_PORT_I (0x08U) /*!< Port I selected */ +/** + * @} + */ + +/** @defgroup GPIO_Port_index GPIO port index + * @{ + */ +#define GPIO_PORTA_IDX (0x0001U) +#define GPIO_PORTB_IDX (0x0002U) +#define GPIO_PORTC_IDX (0x0004U) +#define GPIO_PORTD_IDX (0x0008U) +#define GPIO_PORTE_IDX (0x0010U) +#define GPIO_PORTF_IDX (0x0020U) +#define GPIO_PORTG_IDX (0x0040U) +#define GPIO_PORTH_IDX (0x0080U) +#define GPIO_PORTI_IDX (0x0100U) +#define GPIO_PORT_ALL (0x01FFU) + +#define GPIO_PORT_MASK (0x01FFU) +/** + * @} + */ + +/** + * @} + */ + +/** @defgroup GPIO_function_selection_define GPIO function selection + * @{ + */ +/** @defgroup GPIO_PinFunction0 GPIO Function 0 selection + * @{ + */ +#define GPIO_FUNC_0 (0x00U) +#define GPIO_FUNC_0_GPO (GPIO_FUNC_0) /* GPO function */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction1 GPIO Function 1 selection + * @{ + */ +#define GPIO_FUNC_1 (0x01U) +#define GPIO_FUNC_1_FCMREF (GPIO_FUNC_1) /*!< Reference clock input for FCM */ +#define GPIO_FUNC_1_CTCREF (GPIO_FUNC_1) /*!< Reference clock input for internal CTC */ +#define GPIO_FUNC_1_RTCOUT (GPIO_FUNC_1) /*!< RTC 1Hz output */ +#define GPIO_FUNC_1_VCOUT (GPIO_FUNC_1) /*!< Voltage comparator output */ +#define GPIO_FUNC_1_ADTRG (GPIO_FUNC_1) /*!< ADC external trigger */ +#define GPIO_FUNC_1_MCO (GPIO_FUNC_1) /*!< Clock output */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction2 GPIO Function 2 selection + * @{ + */ +#define GPIO_FUNC_2 (0x02U) +#define GPIO_FUNC_2_TIM41 (GPIO_FUNC_2) /*!< TMR4 unit */ +#define GPIO_FUNC_2_TIM41_PCT (GPIO_FUNC_2) /*!< TMR4 unit 1 basetimer count direction indicator */ +#define GPIO_FUNC_2_TIM41_ADSM (GPIO_FUNC_2) /*!< TMR4 unit 1 special event */ +#define GPIO_FUNC_2_TIM41_CLK (GPIO_FUNC_2) /*!< TMR4 unit 1 clock input */ +#define GPIO_FUNC_2_TIM41_OUH (GPIO_FUNC_2) /*!< TMR4 unit 1 U-phase output high */ +#define GPIO_FUNC_2_TIM41_OUL (GPIO_FUNC_2) /*!< TMR4 unit 1 U-phase output low */ +#define GPIO_FUNC_2_TIM41_OVH (GPIO_FUNC_2) /*!< TMR4 unit 1 V-phase output high */ +#define GPIO_FUNC_2_TIM41_OVL (GPIO_FUNC_2) /*!< TMR4 unit 1 V-phase output low */ +#define GPIO_FUNC_2_TIM41_OWH (GPIO_FUNC_2) /*!< TMR4 unit 1 W-phase output high */ +#define GPIO_FUNC_2_TIM41_OWL (GPIO_FUNC_2) /*!< TMR4 unit 1 W-phase output low */ + +#define GPIO_FUNC_2_TIM42 (GPIO_FUNC_2) /*!< TMR4 unit */ +#define GPIO_FUNC_2_TIM42_PCT (GPIO_FUNC_2) /*!< TMR4 unit 2 basetimer count direction indicator */ +#define GPIO_FUNC_2_TIM42_ADSM (GPIO_FUNC_2) /*!< TMR4 unit 2 special event */ +#define GPIO_FUNC_2_TIM42_CLK (GPIO_FUNC_2) /*!< TMR4 unit 2 clock input */ +#define GPIO_FUNC_2_TIM42_OUH (GPIO_FUNC_2) /*!< TMR4 unit 2 U-phase output high */ +#define GPIO_FUNC_2_TIM42_OUL (GPIO_FUNC_2) /*!< TMR4 unit 2 U-phase output low */ +#define GPIO_FUNC_2_TIM42_OVH (GPIO_FUNC_2) /*!< TMR4 unit 2 V-phase output high */ +#define GPIO_FUNC_2_TIM42_OVL (GPIO_FUNC_2) /*!< TMR4 unit 2 V-phase output low */ +#define GPIO_FUNC_2_TIM42_OWH (GPIO_FUNC_2) /*!< TMR4 unit 2 W-phase output high */ +#define GPIO_FUNC_2_TIM42_OWL (GPIO_FUNC_2) /*!< TMR4 unit 2 W-phase output low */ + +#define GPIO_FUNC_2_TIM43 (GPIO_FUNC_2) /*!< TMR4 unit */ +#define GPIO_FUNC_2_TIM43_PCT (GPIO_FUNC_2) /*!< TMR4 unit 3 basetimer count direction indicator */ +#define GPIO_FUNC_2_TIM43_ADSM (GPIO_FUNC_2) /*!< TMR4 unit 3 special event */ +#define GPIO_FUNC_2_TIM43_CLK (GPIO_FUNC_2) /*!< TMR4 unit 3 clock input */ +#define GPIO_FUNC_2_TIM43_OUH (GPIO_FUNC_2) /*!< TMR4 unit 3 U-phase output high */ +#define GPIO_FUNC_2_TIM43_OUL (GPIO_FUNC_2) /*!< TMR4 unit 3 U-phase output low */ +#define GPIO_FUNC_2_TIM43_OVH (GPIO_FUNC_2) /*!< TMR4 unit 3 V-phase output high */ +#define GPIO_FUNC_2_TIM43_OVL (GPIO_FUNC_2) /*!< TMR4 unit 3 V-phase output low */ +#define GPIO_FUNC_2_TIM43_OWH (GPIO_FUNC_2) /*!< TMR4 unit 3 W-phase output high */ +#define GPIO_FUNC_2_TIM43_OWL (GPIO_FUNC_2) /*!< TMR4 unit 3 W-phase output low */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction3 GPIO Function 3 selection + * @{ + */ +#define GPIO_FUNC_3 (0x03U) +#define GPIO_FUNC_3_TIM6_TRIG (GPIO_FUNC_3) /*!< TMR6 trigger */ +#define GPIO_FUNC_3_TIM6_TRIGA (GPIO_FUNC_3) /*!< TMR6 trigger A */ +#define GPIO_FUNC_3_TIM6_TRIGB (GPIO_FUNC_3) /*!< TMR6 trigger B */ +#define GPIO_FUNC_3_TIM6_TRIGC (GPIO_FUNC_3) /*!< TMR6 trigger C */ +#define GPIO_FUNC_3_TIM6_TRIGD (GPIO_FUNC_3) /*!< TMR6 trigger D */ + +#define GPIO_FUNC_3_TIM61 (GPIO_FUNC_3) /*!< TMR6 unit 1 */ +#define GPIO_FUNC_3_TIM61_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 1 channel A PWM output */ +#define GPIO_FUNC_3_TIM61_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 1 channel B PWM output */ + +#define GPIO_FUNC_3_TIM62 (GPIO_FUNC_3) /*!< TMR6 unit 2 */ +#define GPIO_FUNC_3_TIM62_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 2 channel A PWM output */ +#define GPIO_FUNC_3_TIM62_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 2 channel B PWM output */ + +#define GPIO_FUNC_3_TIM63 (GPIO_FUNC_3) /*!< TMR6 unit 3 */ +#define GPIO_FUNC_3_TIM63_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 3 channel A PWM output */ +#define GPIO_FUNC_3_TIM63_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 3 channel B PWM output */ + +#define GPIO_FUNC_3_TIM64 (GPIO_FUNC_3) /*!< TMR6 unit 4 */ +#define GPIO_FUNC_3_TIM64_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 4 channel A PWM output */ +#define GPIO_FUNC_3_TIM64_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 4 channel B PWM output */ + +#define GPIO_FUNC_3_TIM65 (GPIO_FUNC_3) /*!< TMR6 unit 5 */ +#define GPIO_FUNC_3_TIM65_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 5 channel A PWM output */ +#define GPIO_FUNC_3_TIM65_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 5 channel B PWM output */ + +#define GPIO_FUNC_3_TIM66 (GPIO_FUNC_3) /*!< TMR6 unit 6 */ +#define GPIO_FUNC_3_TIM66_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 6 channel A PWM output */ +#define GPIO_FUNC_3_TIM66_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 6 channel B PWM output */ + +#define GPIO_FUNC_3_TIM67 (GPIO_FUNC_3) /*!< TMR6 unit 7 */ +#define GPIO_FUNC_3_TIM67_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 7 channel A PWM output */ +#define GPIO_FUNC_3_TIM67_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 7 channel B PWM output */ + +#define GPIO_FUNC_3_TIM68 (GPIO_FUNC_3) /*!< TMR6 unit 8 */ +#define GPIO_FUNC_3_TIM68_PWMA (GPIO_FUNC_3) /*!< TMR6 unit 8 channel A PWM output */ +#define GPIO_FUNC_3_TIM68_PWMB (GPIO_FUNC_3) /*!< TMR6 unit 8 channel B PWM output */ + +/** + * @} + */ + +/** @defgroup GPIO_PinFunction4 GPIO Function 4 selection + * @{ + */ +#define GPIO_FUNC_4 (0x04U) +#define GPIO_FUNC_4_TIMA1 (GPIO_FUNC_4) /*!< TMRA unit 1 */ +#define GPIO_FUNC_4_TIMA1_TRIG (GPIO_FUNC_4) /*!< TMRA unit 1 trigger */ +#define GPIO_FUNC_4_TIMA1_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 1 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA1_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 1 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA1_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 1 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA1_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 1 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA2_PWM (GPIO_FUNC_4) /*!< TMRA unit 2 PWM */ +#define GPIO_FUNC_4_TIMA2_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 2 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA2_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 2 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA2_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 2 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA2_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 2 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA3 (GPIO_FUNC_4) /*!< TMRA unit 3 */ +#define GPIO_FUNC_4_TIMA3_TRIG (GPIO_FUNC_4) /*!< TMRA unit 3 trigger */ +#define GPIO_FUNC_4_TIMA3_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 3 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA3_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 3 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA3_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 3 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA3_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 3 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA4 (GPIO_FUNC_4) /*!< TMRA unit 4 */ +#define GPIO_FUNC_4_TIMA4_TRIG (GPIO_FUNC_4) /*!< TMRA unit 4 trigger */ +#define GPIO_FUNC_4_TIMA4_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 4 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA4_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 4 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA4_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 4 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA4_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 4 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA6 (GPIO_FUNC_4) /*!< TMRA unit 6 */ +#define GPIO_FUNC_4_TIMA6_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 6 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA6_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 6 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA6_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 6 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA6_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 6 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA7 (GPIO_FUNC_4) /*!< TMRA unit 7 */ +#define GPIO_FUNC_4_TIMA7_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 7 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA7_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 7 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA7_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 7 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA7_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 7 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA8 (GPIO_FUNC_4) /*!< TMRA unit 8 */ +#define GPIO_FUNC_4_TIMA8_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 8 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA8_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 8 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA8_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 8 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA8_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 8 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA9 (GPIO_FUNC_4) /*!< TMRA unit 9 */ +#define GPIO_FUNC_4_TIMA9_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 9 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA9_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 9 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA9_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 9 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA9_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 9 channel 4 PWM output */ + +#define GPIO_FUNC_4_TIMA10 (GPIO_FUNC_4) /*!< TMRA unit 10 */ +#define GPIO_FUNC_4_TIMA10_PWM1 (GPIO_FUNC_4) /*!< TMRA unit 10 channel 1 PWM output */ +#define GPIO_FUNC_4_TIMA10_PWM2 (GPIO_FUNC_4) /*!< TMRA unit 10 channel 2 PWM output */ +#define GPIO_FUNC_4_TIMA10_PWM3 (GPIO_FUNC_4) /*!< TMRA unit 10 channel 3 PWM output */ +#define GPIO_FUNC_4_TIMA10_PWM4 (GPIO_FUNC_4) /*!< TMRA unit 10 channel 4 PWM output */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction5 GPIO Function 5 selection + * @{ + */ +#define GPIO_FUNC_5 (0x05U) +#define GPIO_FUNC_5_TIMA2_TRIG (GPIO_FUNC_5) /*!< TMRA unit 2 trigger */ + +#define GPIO_FUNC_5_TIMA3 (GPIO_FUNC_5) /*!< TMRA unit 3 */ +#define GPIO_FUNC_5_TIMA3_TRIG (GPIO_FUNC_5) /*!< TMRA unit 3 trigger */ +#define GPIO_FUNC_5_TIMA3_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 3 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA3_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 3 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA3_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 3 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA3_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 3 channel 4 PWM output */ + +#define GPIO_FUNC_5_TIMA4 (GPIO_FUNC_5) /*!< TMRA unit 4 */ +#define GPIO_FUNC_5_TIMA4_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 4 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA4_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 4 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA4_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 4 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA4_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 4 channel 4 PWM output */ + +#define GPIO_FUNC_5_TIMA5 (GPIO_FUNC_5) /*!< TMRA unit 5 */ +#define GPIO_FUNC_5_TIMA5_TRIG (GPIO_FUNC_5) /*!< TMRA unit 5 trigger */ +#define GPIO_FUNC_5_TIMA5_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 5 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA5_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 5 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA5_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 5 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA5_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 5 channel 4 PWM output */ + +#define GPIO_FUNC_5_TIMA6 (GPIO_FUNC_5) /*!< TMRA unit 6 */ +#define GPIO_FUNC_5_TIMA6_TRIG (GPIO_FUNC_5) /*!< TMRA unit 6 trigger */ +#define GPIO_FUNC_5_TIMA6_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 6 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA6_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 6 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA6_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 6 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA6_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 6 channel 4 PWM output */ + +#define GPIO_FUNC_5_TIMA9 (GPIO_FUNC_5) /*!< TMRA unit 9 */ +#define GPIO_FUNC_5_TIMA9_TRIG (GPIO_FUNC_5) /*!< TMRA unit 9 trigger */ +#define GPIO_FUNC_5_TIMA9_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 9 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA9_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 9 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA9_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 9 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA9_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 9 channel 4 PWM output */ + +#define GPIO_FUNC_5_TIMA11_PWM (GPIO_FUNC_5) /*!< TMRA unit 11 PWM */ +#define GPIO_FUNC_5_TIMA11_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 11 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA11_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 11 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA11_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 11 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA11_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 11 channel 4 PWM output */ + +#define GPIO_FUNC_5_TIMA12_PWM (GPIO_FUNC_5) /*!< TMRA unit 12 PWM */ +#define GPIO_FUNC_5_TIMA12_PWM1 (GPIO_FUNC_5) /*!< TMRA unit 12 channel 1 PWM output */ +#define GPIO_FUNC_5_TIMA12_PWM2 (GPIO_FUNC_5) /*!< TMRA unit 12 channel 2 PWM output */ +#define GPIO_FUNC_5_TIMA12_PWM3 (GPIO_FUNC_5) /*!< TMRA unit 12 channel 3 PWM output */ +#define GPIO_FUNC_5_TIMA12_PWM4 (GPIO_FUNC_5) /*!< TMRA unit 12 channel 4 PWM output */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction6 GPIO Function 6 selection + * @{ + */ +#define GPIO_FUNC_6 (0x06U) +#define GPIO_FUNC_6_TIMA1_TRIG (GPIO_FUNC_6) /*!< TMRA unit 1 trigger */ +#define GPIO_FUNC_6_TIMA2_TRIG (GPIO_FUNC_6) /*!< TMRA unit 2 trigger */ +#define GPIO_FUNC_6_TIMA3_TRIG (GPIO_FUNC_6) /*!< TMRA unit 3 trigger */ +#define GPIO_FUNC_6_TIMA4_TRIG (GPIO_FUNC_6) /*!< TMRA unit 4 trigger */ +#define GPIO_FUNC_6_TIMA6_TRIG (GPIO_FUNC_6) /*!< TMRA unit 6 trigger */ +#define GPIO_FUNC_6_TIMA7_TRIG (GPIO_FUNC_6) /*!< TMRA unit 7 trigger */ +#define GPIO_FUNC_6_TIMA8_TRIG (GPIO_FUNC_6) /*!< TMRA unit 8 trigger */ +#define GPIO_FUNC_6_TIMA11_TRIG (GPIO_FUNC_6) /*!< TMRA unit 11 trigger */ +#define GPIO_FUNC_6_TIMA12_TRIG (GPIO_FUNC_6) /*!< TMRA unit 12 trigger */ + +#define GPIO_FUNC_6_TIMA5 (GPIO_FUNC_6) /*!< TMRA unit 5 */ +#define GPIO_FUNC_6_TIMA5_TRIG (GPIO_FUNC_6) /*!< TMRA unit 5 trigger */ +#define GPIO_FUNC_6_TIMA5_PWM1 (GPIO_FUNC_6) /*!< TMRA unit 5 channel 1 PWM output */ +#define GPIO_FUNC_6_TIMA5_PWM2 (GPIO_FUNC_6) /*!< TMRA unit 5 channel 2 PWM output */ +#define GPIO_FUNC_6_TIMA5_PWM3 (GPIO_FUNC_6) /*!< TMRA unit 5 channel 3 PWM output */ +#define GPIO_FUNC_6_TIMA5_PWM4 (GPIO_FUNC_6) /*!< TMRA unit 5 channel 4 PWM output */ + +#define GPIO_FUNC_6_TIMA9 (GPIO_FUNC_6) /*!< TMRA unit 9 */ +#define GPIO_FUNC_6_TIMA9_TRIG (GPIO_FUNC_6) /*!< TMRA unit 9 trigger */ +#define GPIO_FUNC_6_TIMA9_PWM1 (GPIO_FUNC_6) /*!< TMRA unit 9 channel 1 PWM output */ +#define GPIO_FUNC_6_TIMA9_PWM2 (GPIO_FUNC_6) /*!< TMRA unit 9 channel 2 PWM output */ +#define GPIO_FUNC_6_TIMA9_PWM3 (GPIO_FUNC_6) /*!< TMRA unit 9 channel 3 PWM output */ +#define GPIO_FUNC_6_TIMA9_PWM4 (GPIO_FUNC_6) /*!< TMRA unit 9 channel 4 PWM output */ + +#define GPIO_FUNC_6_TIMA10 (GPIO_FUNC_6) /*!< TMRA unit 10 */ +#define GPIO_FUNC_6_TIMA10_TRIG (GPIO_FUNC_6) /*!< TMRA unit 10 trigger */ +#define GPIO_FUNC_6_TIMA10_PWM1 (GPIO_FUNC_6) /*!< TMRA unit 10 channel 1 PWM output */ +#define GPIO_FUNC_6_TIMA10_PWM2 (GPIO_FUNC_6) /*!< TMRA unit 10 channel 2 PWM output */ +#define GPIO_FUNC_6_TIMA10_PWM3 (GPIO_FUNC_6) /*!< TMRA unit 10 channel 3 PWM output */ +#define GPIO_FUNC_6_TIMA10_PWM4 (GPIO_FUNC_6) /*!< TMRA unit 10 channel 4 PWM output */ + +#define GPIO_FUNC_6_TIM65_PWMA (GPIO_FUNC_6) /*!< TMR6 unit 5 channel A PWM output */ +#define GPIO_FUNC_6_TIM66_PWMA (GPIO_FUNC_6) /*!< TMR6 unit 6 channel A PWM output */ +#define GPIO_FUNC_6_TIM67_PWMA (GPIO_FUNC_6) /*!< TMR6 unit 7 channel A PWM output */ +#define GPIO_FUNC_6_TIM68_PWMA (GPIO_FUNC_6) /*!< TMR6 unit 8 channel A PWM output */ + +#define GPIO_FUNC_6_EMB_PORT (GPIO_FUNC_6) /*!< EMB port */ +#define GPIO_FUNC_6_EMB_PORT0 (GPIO_FUNC_6) /*!< EMB port 0 */ +#define GPIO_FUNC_6_EMB_PORT1 (GPIO_FUNC_6) /*!< EMB port 1 */ +#define GPIO_FUNC_6_EMB_PORT2 (GPIO_FUNC_6) /*!< EMB port 2 */ +#define GPIO_FUNC_6_EMB_PORT3 (GPIO_FUNC_6) /*!< EMB port 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction7 GPIO Function 7 selection + * @{ + */ +#define GPIO_FUNC_7 (0x07U) +#define GPIO_FUNC_7_USART1 (GPIO_FUNC_7) /*!< USART1 */ +#define GPIO_FUNC_7_USART1_CK (GPIO_FUNC_7) /*!< USART1 CK */ +#define GPIO_FUNC_7_USART1_CTS (GPIO_FUNC_7) /*!< USART1 CTS */ +#define GPIO_FUNC_7_USART1_RTS (GPIO_FUNC_7) /*!< USART1 RTS */ + +#define GPIO_FUNC_7_USART2 (GPIO_FUNC_7) /*!< USART2 */ +#define GPIO_FUNC_7_USART2_CK (GPIO_FUNC_7) /*!< USART2 CK */ +#define GPIO_FUNC_7_USART2_CTS (GPIO_FUNC_7) /*!< USART2 CTS */ +#define GPIO_FUNC_7_USART2_RTS (GPIO_FUNC_7) /*!< USART2 RTS */ + +#define GPIO_FUNC_7_USART3 (GPIO_FUNC_7) /*!< USART3 */ +#define GPIO_FUNC_7_USART3_CK (GPIO_FUNC_7) /*!< USART3 CK */ +#define GPIO_FUNC_7_USART3_CTS (GPIO_FUNC_7) /*!< USART3 CTS */ +#define GPIO_FUNC_7_USART3_RTS (GPIO_FUNC_7) /*!< USART3 RTS */ + +#define GPIO_FUNC_7_USART4 (GPIO_FUNC_7) /*!< USART4 */ +#define GPIO_FUNC_7_USART4_CK (GPIO_FUNC_7) /*!< USART4 CK */ +#define GPIO_FUNC_7_USART4_CTS (GPIO_FUNC_7) /*!< USART4 CTS */ +#define GPIO_FUNC_7_USART4_RTS (GPIO_FUNC_7) /*!< USART4 RTS */ + +#define GPIO_FUNC_7_USART5 (GPIO_FUNC_7) /*!< USART5 */ +#define GPIO_FUNC_7_USART5_CK (GPIO_FUNC_7) /*!< USART5 CK */ +#define GPIO_FUNC_7_USART5_CTS (GPIO_FUNC_7) /*!< USART5 CTS */ +#define GPIO_FUNC_7_USART5_RTS (GPIO_FUNC_7) /*!< USART5 RTS */ + +#define GPIO_FUNC_7_USART6 (GPIO_FUNC_7) /*!< USART6 */ +#define GPIO_FUNC_7_USART6_CK (GPIO_FUNC_7) /*!< USART6 CK */ +#define GPIO_FUNC_7_USART6_CTS (GPIO_FUNC_7) /*!< USART6 CTS */ +#define GPIO_FUNC_7_USART6_RTS (GPIO_FUNC_7) /*!< USART6 RTS */ + +#define GPIO_FUNC_7_USART7 (GPIO_FUNC_7) /*!< USART7 */ +#define GPIO_FUNC_7_USART7_CK (GPIO_FUNC_7) /*!< USART7 CK */ +#define GPIO_FUNC_7_USART7_CTS (GPIO_FUNC_7) /*!< USART7 CTS */ +#define GPIO_FUNC_7_USART7_RTS (GPIO_FUNC_7) /*!< USART7 RTS */ + +#define GPIO_FUNC_7_USART8 (GPIO_FUNC_7) /*!< USART8 */ +#define GPIO_FUNC_7_USART8_CK (GPIO_FUNC_7) /*!< USART8 CK */ +#define GPIO_FUNC_7_USART8_CTS (GPIO_FUNC_7) /*!< USART8 CTS */ +#define GPIO_FUNC_7_USART8_RTS (GPIO_FUNC_7) /*!< USART8 RTS */ + +#define GPIO_FUNC_7_USART9 (GPIO_FUNC_7) /*!< USART9 */ +#define GPIO_FUNC_7_USART9_CK (GPIO_FUNC_7) /*!< USART9 CK */ +#define GPIO_FUNC_7_USART9_CTS (GPIO_FUNC_7) /*!< USART9 CTS */ +#define GPIO_FUNC_7_USART9_RTS (GPIO_FUNC_7) /*!< USART9 RTS */ + +#define GPIO_FUNC_7_USART10 (GPIO_FUNC_7) /*!< USART10 */ +#define GPIO_FUNC_7_USART10_CK (GPIO_FUNC_7) /*!< USART10 CK */ +#define GPIO_FUNC_7_USART10_CTS (GPIO_FUNC_7) /*!< USART10 CTS */ +#define GPIO_FUNC_7_USART10_RTS (GPIO_FUNC_7) /*!< USART10 RTS */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction8 GPIO Function 8 selection + * @{ + */ +#define GPIO_FUNC_8 (0x08U) +#define GPIO_FUNC_8_KEYSCAN (GPIO_FUNC_8) /*!< KEYSCAN */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction9 GPIO Function 9 selection + * @{ + */ +#define GPIO_FUNC_9 (0x09U) +#define GPIO_FUNC_9_SDIO (GPIO_FUNC_9) /*!< SDIO */ +#define GPIO_FUNC_9_SDIO1 (GPIO_FUNC_9) /*!< SDIO1 */ +#define GPIO_FUNC_9_SDIO1_WP (GPIO_FUNC_9) /*!< SDIO1 WP */ +#define GPIO_FUNC_9_SDIO1_CD (GPIO_FUNC_9) /*!< SDIO1 CD */ +#define GPIO_FUNC_9_SDIO1_CMD (GPIO_FUNC_9) /*!< SDIO1 CMD */ +#define GPIO_FUNC_9_SDIO1_CK (GPIO_FUNC_9) /*!< SDIO1 CK */ +#define GPIO_FUNC_9_SDIO1_DATA (GPIO_FUNC_9) /*!< SDIO1 data bus */ + +#define GPIO_FUNC_9_SDIO2 (GPIO_FUNC_9) /*!< SDIO2 */ +#define GPIO_FUNC_9_SDIO2_WP (GPIO_FUNC_9) /*!< SDIO2 WP */ +#define GPIO_FUNC_9_SDIO2_CD (GPIO_FUNC_9) /*!< SDIO2 CD */ +#define GPIO_FUNC_9_SDIO2_CMD (GPIO_FUNC_9) /*!< SDIO2 CMD */ +#define GPIO_FUNC_9_SDIO2_CK (GPIO_FUNC_9) /*!< SDIO2 CK */ +#define GPIO_FUNC_9_SDIO2_DATA (GPIO_FUNC_9) /*!< SDIO2 data bus */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction10 GPIO Function 10 selection + * @{ + */ +#define GPIO_FUNC_10 (0x0AU) +#define GPIO_FUNC_10_USBF (GPIO_FUNC_10) /*!< USB Full-speed */ +#define GPIO_FUNC_10_USBF_DRVVBUS (GPIO_FUNC_10) /*!< USB Full-speed host VBUS ctrl */ +#define GPIO_FUNC_10_USBF_SOF (GPIO_FUNC_10) /*!< USB Full-speed SOF */ +#define GPIO_FUNC_10_USBF_VBUS (GPIO_FUNC_10) /*!< USB Full-speed slave VBUS */ +#define GPIO_FUNC_10_USBF_ID (GPIO_FUNC_10) /*!< USB Full-speed */ + +#define GPIO_FUNC_10_USBH (GPIO_FUNC_10) /*!< USB High-speed */ +#define GPIO_FUNC_10_USBH_ULPI_DIR (GPIO_FUNC_10) /*!< USB High-speed ULPI DIR */ +#define GPIO_FUNC_10_USBH_ULPI_STP (GPIO_FUNC_10) /*!< USB High-speed ULPI STP */ +#define GPIO_FUNC_10_USBH_ULPI_NXT (GPIO_FUNC_10) /*!< USB High-speed ULPI NXT */ +#define GPIO_FUNC_10_USBH_ULPI_CK (GPIO_FUNC_10) /*!< USB High-speed ULPI CK */ +#define GPIO_FUNC_10_USBH_ULPI_DRVVBUS (GPIO_FUNC_10) /*!< USB High-speed host VBUS ctrl */ +#define GPIO_FUNC_10_USBH_ULPI_DATA (GPIO_FUNC_10) /*!< USB High-speed ULPI data bus */ + +#define GPIO_FUNC_10_TIM22_PWM (GPIO_FUNC_10) /*!< TMR2 unit 2 PWM */ +#define GPIO_FUNC_10_TIM22_PWMA (GPIO_FUNC_10) /*!< TMR2 unit 2 channel A PWM */ +#define GPIO_FUNC_10_TIM22_PWMB (GPIO_FUNC_10) /*!< TMR2 unit 2 channel B PWM */ + +#define GPIO_FUNC_10_TIM24_PWM (GPIO_FUNC_10) /*!< TMR2 unit 4 PWM */ +#define GPIO_FUNC_10_TIM24_PWMA (GPIO_FUNC_10) /*!< TMR2 unit 4 channel A PWM */ +#define GPIO_FUNC_10_TIM24_PWMB (GPIO_FUNC_10) /*!< TMR2 unit 4 channel B PWM */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction11 GPIO Function 11 selection + * @{ + */ +#define GPIO_FUNC_11 (0x0BU) +#define GPIO_FUNC_11_ETH (GPIO_FUNC_11) /*!< Ethernet */ +#define GPIO_FUNC_11_ETH_TXD (GPIO_FUNC_11) /*!< ETH TXD */ +#define GPIO_FUNC_11_ETH_TXEN (GPIO_FUNC_11) /*!< ETH TX enable */ +#define GPIO_FUNC_11_ETH_TXCLK (GPIO_FUNC_11) /*!< ETH TX clock */ +#define GPIO_FUNC_11_ETH_RXD (GPIO_FUNC_11) /*!< ETH RXD */ +#define GPIO_FUNC_11_ETH_RXER (GPIO_FUNC_11) /*!< ETH RX error */ +#define GPIO_FUNC_11_ETH_RXCLK (GPIO_FUNC_11) /*!< ETH RX clock */ +#define GPIO_FUNC_11_ETH_RXDV (GPIO_FUNC_11) /*!< ETH RX data valid */ +#define GPIO_FUNC_11_ETH_SMI_MDIO (GPIO_FUNC_11) /*!< SMI data */ +#define GPIO_FUNC_11_ETH_SMI_MDC (GPIO_FUNC_11) /*!< SMI clock */ +#define GPIO_FUNC_11_ETH_CRS (GPIO_FUNC_11) /*!< ETH MII carrier sense */ +#define GPIO_FUNC_11_ETH_COL (GPIO_FUNC_11) /*!< ETH MII collisioin detected */ +#define GPIO_FUNC_11_ETH_PPS_OUT (GPIO_FUNC_11) /*!< ETH PPS out */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction12 GPIO Function 12 selection + * @{ + */ +#define GPIO_FUNC_12 (0x0CU) +#define GPIO_FUNC_12_EXMC (GPIO_FUNC_12) /*!< Ext. Bus */ +#define GPIO_FUNC_12_EXMC_CLE (GPIO_FUNC_12) /*!< Ext. Bus NAND CMD latch */ +#define GPIO_FUNC_12_EXMC_ALE (GPIO_FUNC_12) /*!< Ext. Bus NAND ADDR latch */ +#define GPIO_FUNC_12_EXMC_RB (GPIO_FUNC_12) /*!< Ext. Bus NAND busy or SRAM wait(RB0) input */ +#define GPIO_FUNC_12_EXMC_CE (GPIO_FUNC_12) /*!< Ext. Bus chip enable */ +#define GPIO_FUNC_12_EXMC_WE (GPIO_FUNC_12) /*!< Ext. Bus write enable */ +#define GPIO_FUNC_12_EXMC_OE (GPIO_FUNC_12) /*!< Ext. Bus output enable */ +#define GPIO_FUNC_12_EXMC_BAA (GPIO_FUNC_12) /*!< Ext. Bus SRAM BAA */ +#define GPIO_FUNC_12_EXMC_ADV (GPIO_FUNC_12) /*!< Ext. Bus SRAM ADDR latch */ +#define GPIO_FUNC_12_EXMC_CLK (GPIO_FUNC_12) /*!< Ext. Bus clock output */ +#define GPIO_FUNC_12_EXMC_ADDR (GPIO_FUNC_12) /*!< Ext. Bus Addr. Bus */ +#define GPIO_FUNC_12_EXMC_DATA (GPIO_FUNC_12) /*!< Ext. Bus data Bus */ + +#define GPIO_FUNC_12_USBH (GPIO_FUNC_12) /*!< USB High-speed */ +#define GPIO_FUNC_12_USBH_SOF (GPIO_FUNC_12) /*!< USB High-speed SOF */ +#define GPIO_FUNC_12_USBH_VBUS (GPIO_FUNC_12) /*!< USB High-speed slave VBUS */ +#define GPIO_FUNC_12_USBH_ID (GPIO_FUNC_12) /*!< USB High-speed ID */ + +#define GPIO_FUNC_12_I2S2_EXCK (GPIO_FUNC_12) /*!< I2S2 EXCK */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction13 GPIO Function 13 selection + * @{ + */ +#define GPIO_FUNC_13 (0x0DU) +#define GPIO_FUNC_13_DVP (GPIO_FUNC_13) /*!< DVP */ +#define GPIO_FUNC_13_DVP_DATA (GPIO_FUNC_13) /*!< DVP data bus */ +#define GPIO_FUNC_13_DVP_PIXCLK (GPIO_FUNC_13) /*!< DVP pix clock */ +#define GPIO_FUNC_13_DVP_HSYNC (GPIO_FUNC_13) /*!< DVP line sync */ +#define GPIO_FUNC_13_DVP_VSYNC (GPIO_FUNC_13) /*!< DVP frame sync */ + +#define GPIO_FUNC_13_EXMC (GPIO_FUNC_13) /*!< Ext. Bus */ +#define GPIO_FUNC_13_EXMC_A16 (GPIO_FUNC_13) /*!< Ext. Bus address 16 */ +#define GPIO_FUNC_13_EXMC_A17 (GPIO_FUNC_13) /*!< Ext. Bus address 17 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction14 GPIO Function 14 selection + * @{ + */ +#define GPIO_FUNC_14 (0x0EU) +#define GPIO_FUNC_14_EP (GPIO_FUNC_14) /*!< Event Port */ +#define GPIO_FUNC_14_EP1 (GPIO_FUNC_14) /*!< Event Port Group 1 */ +#define GPIO_FUNC_14_EP2 (GPIO_FUNC_14) /*!< Event Port Group 2 */ +#define GPIO_FUNC_14_EP3 (GPIO_FUNC_14) /*!< Event Port Group 3 */ +#define GPIO_FUNC_14_EP4 (GPIO_FUNC_14) /*!< Event Port Group 4 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction15 GPIO Function 15 selection + * @{ + */ +#define GPIO_FUNC_15 (0x0FU) +#define GPIO_FUNC_15_EVENTOUT (GPIO_FUNC_15) /*!< Event Out */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction16 GPIO Function 16 selection + * @{ + */ +#define GPIO_FUNC_16 (0x10U) +#define GPIO_FUNC_16_TIM21 (GPIO_FUNC_16) /*!< TMR2 unit 1 */ +#define GPIO_FUNC_16_TIM21_CLKA (GPIO_FUNC_16) /*!< TMR2 unit 1 channel A CLK input */ +#define GPIO_FUNC_16_TIM21_CLKB (GPIO_FUNC_16) /*!< TMR2 unit 1 channel B CLK input */ +#define GPIO_FUNC_16_TIM21_PWMA (GPIO_FUNC_16) /*!< TMR2 unit 1 channel A PWM output */ +#define GPIO_FUNC_16_TIM21_PWMB (GPIO_FUNC_16) /*!< TMR2 unit 1 channel B PWM output */ + +#define GPIO_FUNC_16_TIM22 (GPIO_FUNC_16) /*!< TMR2 unit 2 */ +#define GPIO_FUNC_16_TIM22_CLKA (GPIO_FUNC_16) /*!< TMR2 unit 2 channel A CLK input */ +#define GPIO_FUNC_16_TIM22_CLKB (GPIO_FUNC_16) /*!< TMR2 unit 2 channel B CLK input */ +#define GPIO_FUNC_16_TIM22_PWMA (GPIO_FUNC_16) /*!< TMR2 unit 2 channel A PWM output */ +#define GPIO_FUNC_16_TIM22_PWMB (GPIO_FUNC_16) /*!< TMR2 unit 2 channel B PWM output */ + +#define GPIO_FUNC_16_TIM23 (GPIO_FUNC_16) /*!< TMR2 unit 3 */ +#define GPIO_FUNC_16_TIM23_CLKA (GPIO_FUNC_16) /*!< TMR2 unit 3 channel A CLK input */ +#define GPIO_FUNC_16_TIM23_CLKB (GPIO_FUNC_16) /*!< TMR2 unit 3 channel B CLK input */ +#define GPIO_FUNC_16_TIM23_PWMA (GPIO_FUNC_16) /*!< TMR2 unit 3 channel A PWM output */ +#define GPIO_FUNC_16_TIM23_PWMB (GPIO_FUNC_16) /*!< TMR2 unit 3 channel B PWM output */ + +#define GPIO_FUNC_16_TIM24 (GPIO_FUNC_16) /*!< TMR2 unit 4 */ +#define GPIO_FUNC_16_TIM24_CLKA (GPIO_FUNC_16) /*!< TMR2 unit 4 channel A CLK input */ +#define GPIO_FUNC_16_TIM24_CLKB (GPIO_FUNC_16) /*!< TMR2 unit 4 channel B CLK input */ +#define GPIO_FUNC_16_TIM24_PWMA (GPIO_FUNC_16) /*!< TMR2 unit 4 channel A PWM output */ +#define GPIO_FUNC_16_TIM24_PWMB (GPIO_FUNC_16) /*!< TMR2 unit 4 channel B PWM output */ + +#define GPIO_FUNC_16_TIM41_CLK (GPIO_FUNC_16) /*!< TMR4 unit 1 CLK input */ + +#define GPIO_FUNC_16_TIM42_CLK (GPIO_FUNC_16) /*!< TMR4 unit 2 CLK input */ +#define GPIO_FUNC_16_TIM42_OUL (GPIO_FUNC_16) /*!< TMR4 unit 2 U-phase low output */ +#define GPIO_FUNC_16_TIM42_OVL (GPIO_FUNC_16) /*!< TMR4 unit 2 V-phase low output */ +#define GPIO_FUNC_16_TIM42_OWL (GPIO_FUNC_16) /*!< TMR4 unit 2 W-phase low output */ + +#define GPIO_FUNC_16_TIM43_ADSM (GPIO_FUNC_16) /*!< TMR4 unit 3 special event */ + +/** + * @} + */ + +/** @defgroup GPIO_PinFunction17 GPIO Function 17 selection + * @{ + */ +#define GPIO_FUNC_17 (0x11U) +#define GPIO_FUNC_17_I2S1 (GPIO_FUNC_17) /*!< I2S1 */ +#define GPIO_FUNC_17_I2S1_MCK (GPIO_FUNC_17) /*!< I2S1 MCK */ +#define GPIO_FUNC_17_I2S1_EXCK (GPIO_FUNC_17) /*!< I2S1 EXCK */ +#define GPIO_FUNC_17_I2S1_SDIN (GPIO_FUNC_17) /*!< I2S1 SDIN */ + +#define GPIO_FUNC_17_I2S2 (GPIO_FUNC_17) /*!< I2S2 */ +#define GPIO_FUNC_17_I2S2_CK (GPIO_FUNC_17) /*!< I2S2 CK */ +#define GPIO_FUNC_17_I2S2_MCK (GPIO_FUNC_17) /*!< I2S2 MCK */ +#define GPIO_FUNC_17_I2S2_EXCK (GPIO_FUNC_17) /*!< I2S2 EXCK */ +#define GPIO_FUNC_17_I2S2_SD (GPIO_FUNC_17) /*!< I2S2 SD */ +#define GPIO_FUNC_17_I2S2_SDIN (GPIO_FUNC_17) /*!< I2S2 SDIN */ + +#define GPIO_FUNC_17_I2S3 (GPIO_FUNC_17) /*!< I2S3 */ +#define GPIO_FUNC_17_I2S3_MCK (GPIO_FUNC_17) /*!< I2S3 MCK */ +#define GPIO_FUNC_17_I2S3_EXCK (GPIO_FUNC_17) /*!< I2S3 EXCK */ +#define GPIO_FUNC_17_I2S3_SDIN (GPIO_FUNC_17) /*!< I2S3 SDIN */ + +#define GPIO_FUNC_17_I2S4 (GPIO_FUNC_17) /*!< I2S4 */ +#define GPIO_FUNC_17_I2S4_MCK (GPIO_FUNC_17) /*!< I2S4 MCK */ +#define GPIO_FUNC_17_I2S4_EXCK (GPIO_FUNC_17) /*!< I2S4 EXCK */ +#define GPIO_FUNC_17_I2S4_SDIN (GPIO_FUNC_17) /*!< I2S4 SDIN */ +#define GPIO_FUNC_17_I2S4_SD (GPIO_FUNC_17) /*!< I2S4 SD */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction18 GPIO Function 18 selection + * @{ + */ +#define GPIO_FUNC_18 (0x12U) +#define GPIO_FUNC_18_SPI1 (GPIO_FUNC_18) /*!< SPI1 */ +#define GPIO_FUNC_18_SPI1_NSS1 (GPIO_FUNC_18) /*!< SPI1 NSS1 */ +#define GPIO_FUNC_18_SPI1_NSS2 (GPIO_FUNC_18) /*!< SPI1 NSS2 */ +#define GPIO_FUNC_18_SPI1_NSS3 (GPIO_FUNC_18) /*!< SPI1 NSS3 */ + +#define GPIO_FUNC_18_SPI2 (GPIO_FUNC_18) /*!< SPI2 */ +#define GPIO_FUNC_18_SPI2_NSS0 (GPIO_FUNC_18) /*!< SPI2 NSS0 */ +#define GPIO_FUNC_18_SPI2_NSS1 (GPIO_FUNC_18) /*!< SPI2 NSS1 */ +#define GPIO_FUNC_18_SPI2_NSS2 (GPIO_FUNC_18) /*!< SPI2 NSS2 */ +#define GPIO_FUNC_18_SPI2_NSS3 (GPIO_FUNC_18) /*!< SPI2 NSS3 */ + +#define GPIO_FUNC_18_SPI3 (GPIO_FUNC_18) /*!< SPI3 */ +#define GPIO_FUNC_18_SPI3_NSS1 (GPIO_FUNC_18) /*!< SPI3 NSS1 */ +#define GPIO_FUNC_18_SPI3_NSS2 (GPIO_FUNC_18) /*!< SPI3 NSS2 */ +#define GPIO_FUNC_18_SPI3_NSS3 (GPIO_FUNC_18) /*!< SPI3 NSS3 */ + +#define GPIO_FUNC_18_SPI4 (GPIO_FUNC_18) /*!< SPI4 */ +#define GPIO_FUNC_18_SPI4_NSS1 (GPIO_FUNC_18) /*!< SPI4 NSS1 */ +#define GPIO_FUNC_18_SPI4_NSS2 (GPIO_FUNC_18) /*!< SPI4 NSS2 */ +#define GPIO_FUNC_18_SPI4_NSS3 (GPIO_FUNC_18) /*!< SPI4 NSS3 */ + +#define GPIO_FUNC_18_SPI5 (GPIO_FUNC_18) /*!< SPI5 */ +#define GPIO_FUNC_18_SPI5_NSS0 (GPIO_FUNC_18) /*!< SPI5 NSS0 */ +#define GPIO_FUNC_18_SPI5_NSS1 (GPIO_FUNC_18) /*!< SPI5 NSS1 */ +#define GPIO_FUNC_18_SPI5_NSS2 (GPIO_FUNC_18) /*!< SPI5 NSS2 */ +#define GPIO_FUNC_18_SPI5_NSS3 (GPIO_FUNC_18) /*!< SPI5 NSS3 */ + +#define GPIO_FUNC_18_SPI6 (GPIO_FUNC_18) /*!< SPI6 */ +#define GPIO_FUNC_18_SPI6_NSS1 (GPIO_FUNC_18) /*!< SPI6 NSS1 */ +#define GPIO_FUNC_18_SPI6_NSS2 (GPIO_FUNC_18) /*!< SPI6 NSS2 */ +#define GPIO_FUNC_18_SPI6_NSS3 (GPIO_FUNC_18) /*!< SPI6 NSS3 */ + +#define GPIO_FUNC_18_QSPI (GPIO_FUNC_18) /*!< QSPI */ +#define GPIO_FUNC_18_QSPI_NSS (GPIO_FUNC_18) /*!< QSPI NSS */ +#define GPIO_FUNC_18_QSPI_SCK (GPIO_FUNC_18) /*!< QSPI SCK */ +#define GPIO_FUNC_18_QSPI_IO0 (GPIO_FUNC_18) /*!< QSPI IO0 */ +#define GPIO_FUNC_18_QSPI_IO1 (GPIO_FUNC_18) /*!< QSPI IO1 */ +#define GPIO_FUNC_18_QSPI_IO2 (GPIO_FUNC_18) /*!< QSPI IO2 */ +#define GPIO_FUNC_18_QSPI_IO3 (GPIO_FUNC_18) /*!< QSPI IO3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction19 GPIO Function 19 selection + * @{ + */ +#define GPIO_FUNC_19 (0x13U) +#define GPIO_FUNC_19_SPI1 (GPIO_FUNC_19) /*!< SPI1 */ +#define GPIO_FUNC_19_SPI1_NSS0 (GPIO_FUNC_19) /*!< SPI1 NSS0 */ + +#define GPIO_FUNC_19_SPI2 (GPIO_FUNC_19) /*!< SPI2 */ +#define GPIO_FUNC_19_SPI2_NSS0 (GPIO_FUNC_19) /*!< SPI2 NSS0 */ +#define GPIO_FUNC_19_SPI2_MOSI (GPIO_FUNC_19) /*!< SPI2 MOSI */ +#define GPIO_FUNC_19_SPI2_MISO (GPIO_FUNC_19) /*!< SPI2 MISO */ +#define GPIO_FUNC_19_SPI2_SCK (GPIO_FUNC_19) /*!< SPI2 SCK */ + +#define GPIO_FUNC_19_SPI3 (GPIO_FUNC_19) /*!< SPI3 */ +#define GPIO_FUNC_19_SPI3_NSS0 (GPIO_FUNC_19) /*!< SPI3 NSS0 */ +#define GPIO_FUNC_19_SPI3_MOSI (GPIO_FUNC_19) /*!< SPI3 MOSI */ +#define GPIO_FUNC_19_SPI3_MISO (GPIO_FUNC_19) /*!< SPI3 MISO */ +#define GPIO_FUNC_19_SPI3_SCK (GPIO_FUNC_19) /*!< SPI3 SCK */ + +#define GPIO_FUNC_19_SPI (GPIO_FUNC_19) /*!< SPI4 */ +#define GPIO_FUNC_19_SPI4_NSS0 (GPIO_FUNC_19) /*!< SPI4 NSS0 */ + +#define GPIO_FUNC_19_SPI5 (GPIO_FUNC_19) /*!< SPI5 */ +#define GPIO_FUNC_19_SPI5_NSS0 (GPIO_FUNC_19) /*!< SPI5 NSS0 */ +#define GPIO_FUNC_19_SPI5_MOSI (GPIO_FUNC_19) /*!< SPI5 MOSI */ +#define GPIO_FUNC_19_SPI5_MISO (GPIO_FUNC_19) /*!< SPI5 MISO */ +#define GPIO_FUNC_19_SPI5_SCK (GPIO_FUNC_19) /*!< SPI5 SCK */ + +#define GPIO_FUNC_19_SPI6 (GPIO_FUNC_19) /*!< SPI6 */ +#define GPIO_FUNC_19_SPI6_NSS0 (GPIO_FUNC_19) /*!< SPI6 NSS0 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction20 GPIO Function 20 selection + * @{ + */ +#define GPIO_FUNC_20 (0x14U) +#define GPIO_FUNC_20_USART1 (GPIO_FUNC_20) /*!< USART1 */ +#define GPIO_FUNC_20_USART1_TX (GPIO_FUNC_20) /*!< USART1 TX */ +#define GPIO_FUNC_20_USART1_RX (GPIO_FUNC_20) /*!< USART1 RX */ +#define GPIO_FUNC_20_USART1_CTS (GPIO_FUNC_20) /*!< USART1 CTS */ +#define GPIO_FUNC_20_USART1_RTS (GPIO_FUNC_20) /*!< USART1 RTS */ +#define GPIO_FUNC_20_USART1_CK (GPIO_FUNC_20) /*!< USART1 CK */ + +#define GPIO_FUNC_20_USART2 (GPIO_FUNC_20) /*!< USART2 */ +#define GPIO_FUNC_20_USART2_TX (GPIO_FUNC_20) /*!< USART2 TX */ +#define GPIO_FUNC_20_USART2_RX (GPIO_FUNC_20) /*!< USART2 RX */ +#define GPIO_FUNC_20_USART2_CTS (GPIO_FUNC_20) /*!< USART2 CTS */ +#define GPIO_FUNC_20_USART2_RTS (GPIO_FUNC_20) /*!< USART2 RTS */ +#define GPIO_FUNC_20_USART2_CK (GPIO_FUNC_20) /*!< USART2 CK */ + +#define GPIO_FUNC_20_USART4 (GPIO_FUNC_20) /*!< USART4 */ +#define GPIO_FUNC_20_USART4_TX (GPIO_FUNC_20) /*!< USART4 TX */ +#define GPIO_FUNC_20_USART4_RX (GPIO_FUNC_20) /*!< USART4 RX */ + +#define GPIO_FUNC_20_USART5 (GPIO_FUNC_20) /*!< USART5 */ +#define GPIO_FUNC_20_USART5_TX (GPIO_FUNC_20) /*!< USART5 TX */ +#define GPIO_FUNC_20_USART5_RX (GPIO_FUNC_20) /*!< USART5 RX */ + +#define GPIO_FUNC_20_USART6 (GPIO_FUNC_20) /*!< USART6 */ +#define GPIO_FUNC_20_USART6_TX (GPIO_FUNC_20) /*!< USART6 TX */ +#define GPIO_FUNC_20_USART6_RX (GPIO_FUNC_20) /*!< USART6 RX */ +#define GPIO_FUNC_20_USART6_CTS (GPIO_FUNC_20) /*!< USART6 CTS */ +#define GPIO_FUNC_20_USART6_RTS (GPIO_FUNC_20) /*!< USART6 RTS */ +#define GPIO_FUNC_20_USART6_CK (GPIO_FUNC_20) /*!< USART6 CK */ + +#define GPIO_FUNC_20_USART7 (GPIO_FUNC_20) /*!< USART7 */ +#define GPIO_FUNC_20_USART7_TX (GPIO_FUNC_20) /*!< USART7 TX */ +#define GPIO_FUNC_20_USART7_RX (GPIO_FUNC_20) /*!< USART7 RX */ + +#define GPIO_FUNC_20_USART8 (GPIO_FUNC_20) /*!< USART8 */ +#define GPIO_FUNC_20_USART8_TX (GPIO_FUNC_20) /*!< USART8 TX */ +#define GPIO_FUNC_20_USART8_RX (GPIO_FUNC_20) /*!< USART8 RX */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction32 GPIO Function 32 selection + * @{ + */ +#define GPIO_FUNC_32 (0x20U) +#define GPIO_FUNC_32_USART1_TX (GPIO_FUNC_32) /*!< USART1 TX in Function Group 1 */ +#define GPIO_FUNC_32_USART4_TX (GPIO_FUNC_32) /*!< USART4 TX in Function Group 2 */ +#define GPIO_FUNC_32_USART3_TX (GPIO_FUNC_32) /*!< USART3 TX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction33 GPIO Function 33 selection + * @{ + */ +#define GPIO_FUNC_33 (0x21U) +#define GPIO_FUNC_33_USART1_RX (GPIO_FUNC_33) /*!< USART1 RX in Function Group 1 */ +#define GPIO_FUNC_33_USART4_RX (GPIO_FUNC_33) /*!< USART4 RX in Function Group 2 */ +#define GPIO_FUNC_33_USART3_RX (GPIO_FUNC_33) /*!< USART3 RX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction34 GPIO Function 34 selection + * @{ + */ +#define GPIO_FUNC_34 (0x22U) +#define GPIO_FUNC_34_USART2_TX (GPIO_FUNC_34) /*!< USART2 TX in Function Group 1 */ +#define GPIO_FUNC_34_USART5_TX (GPIO_FUNC_34) /*!< USART5 TX in Function Group 2 */ +#define GPIO_FUNC_34_USART8_TX (GPIO_FUNC_34) /*!< USART8 TX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction35 GPIO Function 35 selection + * @{ + */ +#define GPIO_FUNC_35 (0x23U) +#define GPIO_FUNC_35_USART2_RX (GPIO_FUNC_35) /*!< USART2 RX in Function Group 1 */ +#define GPIO_FUNC_35_USART5_RX (GPIO_FUNC_35) /*!< USART5 RX in Function Group 2 */ +#define GPIO_FUNC_35_USART8_RX (GPIO_FUNC_35) /*!< USART8 RX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction36 GPIO Function 36 selection + * @{ + */ +#define GPIO_FUNC_36 (0x24U) +#define GPIO_FUNC_36_USART3_TX (GPIO_FUNC_36) /*!< USART3 TX in Function Group 1 */ +#define GPIO_FUNC_36_USART6_TX (GPIO_FUNC_36) /*!< USART6 TX in Function Group 2 */ +#define GPIO_FUNC_36_USART9_TX (GPIO_FUNC_36) /*!< USART9 TX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction37 GPIO Function 37 selection + * @{ + */ +#define GPIO_FUNC_37 (0x25U) +#define GPIO_FUNC_37_USART3_RX (GPIO_FUNC_37) /*!< USART3 RX in Function Group 1 */ +#define GPIO_FUNC_37_USART6_RX (GPIO_FUNC_37) /*!< USART6 RX in Function Group 2 */ +#define GPIO_FUNC_37_USART9_RX (GPIO_FUNC_37) /*!< USART9 RX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction38 GPIO Function 38 selection + * @{ + */ +#define GPIO_FUNC_38 (0x26U) +#define GPIO_FUNC_38_USART4_TX (GPIO_FUNC_38) /*!< USART4 TX in Function Group 1 */ +#define GPIO_FUNC_38_USART7_TX (GPIO_FUNC_38) /*!< USART7 TX in Function Group 2 */ +#define GPIO_FUNC_38_USART10_TX (GPIO_FUNC_38) /*!< USART10 TX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction39 GPIO Function 39 selection + * @{ + */ +#define GPIO_FUNC_39 (0x27U) +#define GPIO_FUNC_39_USART4_RX (GPIO_FUNC_39) /*!< USART4 RX in Function Group 1 */ +#define GPIO_FUNC_39_USART7_RX (GPIO_FUNC_39) /*!< USART7 RX in Function Group 2 */ +#define GPIO_FUNC_39_USART10_RX (GPIO_FUNC_39) /*!< USART10 RX in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction40 GPIO Function 40 selection + * @{ + */ +#define GPIO_FUNC_40 (0x28U) +#define GPIO_FUNC_40_SPI1_SCK (GPIO_FUNC_40) /*!< SPI1 SCK in Function Group 1 & 3 */ +#define GPIO_FUNC_40_SPI4_SCK (GPIO_FUNC_40) /*!< SPI4 SCK in Function Group 2 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction41 GPIO Function 41 selection + * @{ + */ +#define GPIO_FUNC_41 (0x29U) +#define GPIO_FUNC_41_SPI1_MOSI (GPIO_FUNC_41) /*!< SPI1 MOSI in Function Group 1 & 3 */ +#define GPIO_FUNC_41_SPI4_MOSI (GPIO_FUNC_41) /*!< SPI4 MOSI in Function Group 2 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction42 GPIO Function 42 selection + * @{ + */ +#define GPIO_FUNC_42 (0x2AU) +#define GPIO_FUNC_42_SPI1_MISO (GPIO_FUNC_42) /*!< SPI1 MISO in Function Group 1 & 3 */ +#define GPIO_FUNC_42_SPI4_MISO (GPIO_FUNC_42) /*!< SPI4 MISO in Function Group 2 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction43 GPIO Function 43 selection + * @{ + */ +#define GPIO_FUNC_43 (0x2BU) +#define GPIO_FUNC_43_SPI2_SCK (GPIO_FUNC_43) /*!< SPI2 SCK in Function Group 1 */ +#define GPIO_FUNC_43_SPI5_SCK (GPIO_FUNC_43) /*!< SPI5 SCK in Function Group 2 */ +#define GPIO_FUNC_43_SPI4_SCK (GPIO_FUNC_43) /*!< SPI4 SCK in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction44 GPIO Function 44 selection + * @{ + */ +#define GPIO_FUNC_44 (0x2CU) +#define GPIO_FUNC_44_SPI2_MOSI (GPIO_FUNC_44) /*!< SPI2 MOSI in Function Group 1 */ +#define GPIO_FUNC_44_SPI5_MOSI (GPIO_FUNC_44) /*!< SPI5 MOSI in Function Group 2 */ +#define GPIO_FUNC_44_SPI4_MOSI (GPIO_FUNC_44) /*!< SPI4 MOSI in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction45 GPIO Function 45 selection + * @{ + */ +#define GPIO_FUNC_45 (0x2DU) +#define GPIO_FUNC_45_SPI2_MISO (GPIO_FUNC_45) /*!< SPI2 MISO in Function Group 1 */ +#define GPIO_FUNC_45_SPI5_MISO (GPIO_FUNC_45) /*!< SPI5 MISO in Function Group 2 */ +#define GPIO_FUNC_45_SPI4_MISO (GPIO_FUNC_45) /*!< SPI4 MISO in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction46 GPIO Function 46 selection + * @{ + */ +#define GPIO_FUNC_46 (0x2EU) +#define GPIO_FUNC_46_SPI3_SCK (GPIO_FUNC_46) /*!< SPI3 SCK in Function Group 1 */ +#define GPIO_FUNC_46_SPI6_SCK (GPIO_FUNC_46) /*!< SPI6 SCK in Function Group 2 */ +#define GPIO_FUNC_46_SPI4_NSS0 (GPIO_FUNC_46) /*!< SPI4 NSS0 in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction47 GPIO Function 47 selection + * @{ + */ +#define GPIO_FUNC_47 (0x2FU) +#define GPIO_FUNC_47_SPI3_MOSI (GPIO_FUNC_47) /*!< SPI3 MOSI in Function Group 1 */ +#define GPIO_FUNC_47_SPI6_MOSI (GPIO_FUNC_47) /*!< SPI6 MOSI in Function Group 2 */ +#define GPIO_FUNC_47_SPI1_NSS0 (GPIO_FUNC_47) /*!< SPI4 NSS0 in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction48 GPIO Function 48 selection + * @{ + */ +#define GPIO_FUNC_48 (0x30U) +#define GPIO_FUNC_48_SPI3_MISO (GPIO_FUNC_48) /*!< SPI3 MISO in Function Group 1 */ +#define GPIO_FUNC_48_SPI6_MISO (GPIO_FUNC_48) /*!< SPI6 MISO in Function Group 2 */ +#define GPIO_FUNC_48_I2C1_SDA (GPIO_FUNC_48) /*!< I2C1 SDA in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction49 GPIO Function 49 selection + * @{ + */ +#define GPIO_FUNC_49 (0x31U) +#define GPIO_FUNC_49_SPI3_NSS0 (GPIO_FUNC_49) /*!< SPI3 NSS0 in Function Group 1 */ +#define GPIO_FUNC_49_SPI6_NSS0 (GPIO_FUNC_49) /*!< SPI6 NSS0 in Function Group 2 */ +#define GPIO_FUNC_49_I2C1_SCL (GPIO_FUNC_49) /*!< I2C1 SCL in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction50 GPIO Function 50 selection + * @{ + */ +#define GPIO_FUNC_50 (0x32U) +#define GPIO_FUNC_50_I2C1_SDA (GPIO_FUNC_50) /*!< I2C1 SDA in Function Group 1 */ +#define GPIO_FUNC_50_I2C2_SDA (GPIO_FUNC_50) /*!< I2C2 SDA in Function Group 2 & 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction51 GPIO Function 51 selection + * @{ + */ +#define GPIO_FUNC_51 (0x33U) +#define GPIO_FUNC_51_I2C1_SCL (GPIO_FUNC_51) /*!< I2C1 SCL in Function Group 1 */ +#define GPIO_FUNC_51_I2C2_SCL (GPIO_FUNC_51) /*!< I2C2 SCL in Function Group 2 & 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction52 GPIO Function 52 selection + * @{ + */ +#define GPIO_FUNC_52 (0x34U) +#define GPIO_FUNC_52_I2C3_SDA (GPIO_FUNC_52) /*!< I2C3 SDA in Function Group 1 */ +#define GPIO_FUNC_52_I2C4_SDA (GPIO_FUNC_52) /*!< I2C4 SDA in Function Group 2 */ +#define GPIO_FUNC_52_I2C6_SDA (GPIO_FUNC_52) /*!< I2C6 SDA in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction53 GPIO Function 53 selection + * @{ + */ +#define GPIO_FUNC_53 (0x35U) +#define GPIO_FUNC_53_I2C3_SCL (GPIO_FUNC_53) /*!< I2C3 SCL in Function Group 1 */ +#define GPIO_FUNC_53_I2C4_SCL (GPIO_FUNC_53) /*!< I2C4 SCL in Function Group 2 */ +#define GPIO_FUNC_53_I2C6_SCL (GPIO_FUNC_53) /*!< I2C6 SCL in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction54 GPIO Function 54 selection + * @{ + */ +#define GPIO_FUNC_54 (0x36U) +#define GPIO_FUNC_54_I2S1_CK (GPIO_FUNC_54) /*!< I2S1 CK in Function Group 1&3 */ +#define GPIO_FUNC_54_I2C5_SDA (GPIO_FUNC_54) /*!< I2C5 SDA in Function Group 2 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction55 GPIO Function 55 selection + * @{ + */ +#define GPIO_FUNC_55 (0x37U) +#define GPIO_FUNC_55_I2S1_WS (GPIO_FUNC_55) /*!< I2S1_WS in Function Group 1&3 */ +#define GPIO_FUNC_55_I2C5_SCL (GPIO_FUNC_55) /*!< I2C5_SCL in Function Group 2 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction56 GPIO Function 56 selection + * @{ + */ +#define GPIO_FUNC_56 (0x38U) +#define GPIO_FUNC_56_I2S1_SD (GPIO_FUNC_56) /*!< I2S1 SD in Function Group 1&3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction57 GPIO Function 57 selection + * @{ + */ +#define GPIO_FUNC_57 (0x39U) +#define GPIO_FUNC_57_I2S2_CK (GPIO_FUNC_57) /*!< I2S2 CK in Function Group 1 */ +#define GPIO_FUNC_57_I2S3_CK (GPIO_FUNC_57) /*!< I2S3 CK in Function Group 2 */ +#define GPIO_FUNC_57_I2S4_CK (GPIO_FUNC_57) /*!< I2S4 CK in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction58 GPIO Function 58 selection + * @{ + */ +#define GPIO_FUNC_58 (0x3AU) +#define GPIO_FUNC_58_I2S2_WS (GPIO_FUNC_58) /*!< I2S2 WS in Function Group 1 */ +#define GPIO_FUNC_58_I2S3_WS (GPIO_FUNC_58) /*!< I2S3 WS in Function Group 2 */ +#define GPIO_FUNC_58_I2S4_WS (GPIO_FUNC_58) /*!< I2S4 WS in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction59 GPIO Function 59 selection + * @{ + */ +#define GPIO_FUNC_59 (0x3BU) +#define GPIO_FUNC_59_I2S2_SD (GPIO_FUNC_59) /*!< I2S2 SD in Function Group 1 */ +#define GPIO_FUNC_59_I2S3_SD (GPIO_FUNC_59) /*!< I2S3 SD in Function Group 2 */ +#define GPIO_FUNC_59_I2S4_SD (GPIO_FUNC_59) /*!< I2S4 SD in Function Group 3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction60 GPIO Function 60 selection + * @{ + */ +#define GPIO_FUNC_60 (0x3CU) +#define GPIO_FUNC_60_CAN1_TX (GPIO_FUNC_60) /*!< CAN1 TX in Function Group 1~3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction61 GPIO Function 61 selection + * @{ + */ +#define GPIO_FUNC_61 (0x3DU) +#define GPIO_FUNC_61_CAN1_RX (GPIO_FUNC_61) /*!< CAN1 RX in Function Group 1~3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction62 GPIO Function 62 selection + * @{ + */ +#define GPIO_FUNC_62 (0x3EU) +#define GPIO_FUNC_62_CAN2_TX (GPIO_FUNC_62) /*!< CAN2 TX in Function Group 1~3 */ +/** + * @} + */ + +/** @defgroup GPIO_PinFunction63 GPIO Function 63 selection + * @{ + */ +#define GPIO_FUNC_63 (0x3FU) +#define GPIO_FUNC_63_CAN2_RX (GPIO_FUNC_63) /*!< CAN2 RX in Function Group 1~3 */ +/** + * @} + */ + +/** @defgroup GPIO_DebugPin_Sel GPIO Debug pin selection + * @{ + */ +#define GPIO_PIN_SWCLK (0x01U) +#define GPIO_PIN_SWDIO (0x02U) +#define GPIO_PIN_SWO (0x04U) +#define GPIO_PIN_DEBUG_SWD (0x07U) + +#define GPIO_PIN_TCK (0x01U) +#define GPIO_PIN_TMS (0x02U) +#define GPIO_PIN_TDO (0x04U) +#define GPIO_PIN_TDI (0x08U) +#define GPIO_PIN_TRST (0x10U) +#define GPIO_PIN_DEBUG_JTAG (0x1FU) +/** + * @} + */ + +/** @defgroup GPIO_ReadCycle_Sel GPIO pin read wait cycle selection + * @{ + */ +#define GPIO_READ_WAIT_0 ((uint16_t)(0x00UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_1 ((uint16_t)(0x01UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_2 ((uint16_t)(0x02UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_3 ((uint16_t)(0x03UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_4 ((uint16_t)(0x04UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_5 ((uint16_t)(0x05UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_6 ((uint16_t)(0x06UL << GPIO_PCCR_RDWT_POS)) +#define GPIO_READ_WAIT_7 ((uint16_t)(0x07UL << GPIO_PCCR_RDWT_POS)) +/** + * @} + */ + +/** + * @defgroup GPIO_PinState_Sel GPIO pin output state selection + * @{ + */ +#define PIN_STATE_RESET (0U) +#define PIN_STATE_SET (GPIO_PCR_POUT) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDirection_Sel GPIO pin input/output direction selection + * @{ + */ +#define PIN_DIR_IN (0U) +#define PIN_DIR_OUT (GPIO_PCR_POUTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinOutType_Sel GPIO pin output type selection + * @{ + */ +#define PIN_OTYPE_CMOS (0U) +#define PIN_OTYPE_NMOS (GPIO_PCR_NOD) +/** + * @} + */ + +/** + * @defgroup GPIO_PinDrv_Sel GPIO Pin drive capacity selection + * @{ + */ +#define PIN_DRV_LOW (0U) +#define PIN_DRV_MID (GPIO_PCR_DRV_0) +#define PIN_DRV_HIGH (GPIO_PCR_DRV_1) +/** + * @} + */ + +/** + * @defgroup GPIO_PinLatch_Sel GPIO Pin output latch selection + * @{ + */ +#define PIN_LATCH_OFF (0U) +#define PIN_LATCH_ON (GPIO_PCR_LTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinPU_Sel GPIO Pin internal pull-up resistor selection + * @{ + */ +#define PIN_PU_OFF (0U) +#define PIN_PU_ON (GPIO_PCR_PUU) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInvert_Sel GPIO Pin I/O invert selection + * @{ + */ +#define PIN_INVERT_OFF (0U) +#define PIN_INVERT_ON (GPIO_PCR_INVE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinInType_Sel GPIO Pin input type selection + * @{ + */ +#define PIN_ITYPE_SMT (0U) +#define PIN_ITYPE_CMOS (GPIO_PCR_CINSEL) +/** + * @} + */ + +/** + * @defgroup GPIO_PinExInt_Sel GPIO Pin external interrupt selection + * @{ + */ +#define PIN_EXINT_OFF (0U) +#define PIN_EXINT_ON (GPIO_PCR_INTE) +/** + * @} + */ + +/** + * @defgroup GPIO_PinMode_Sel GPIO Pin mode selection + * @{ + */ +#define PIN_ATTR_DIGITAL (0U) +#define PIN_ATTR_ANALOG (GPIO_PCR_DDIS) +/** + * @} + */ + +/** + * @defgroup GPIO_PinSubFuncSet_Sel GPIO Pin sub-function enable or disable + * @{ + */ +#define PIN_SUBFUNC_DISABLE (0U) +#define PIN_SUBFUNC_ENABLE (GPIO_PFSR_BFE) +/** + * @} + */ + +/** + * @defgroup GPIO_Register_Protect GPIO Registers Protect Code + * @{ + */ +#define GPIO_REG_UNPROTECT (0xA501U) +#define GPIO_REG_PROTECT (0xA500U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup GPIO_Global_Functions + * @{ + */ +/** + * @brief GPIO lock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write disable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_Lock(void) +{ + WRITE_REG16(M4_GPIO->PWPR, GPIO_REG_PROTECT); +} + +/** + * @brief GPIO unlock. PSPCR, PCCR, PINAER, PCRxy, PFSRxy write enable + * @param None + * @retval None + */ +__STATIC_INLINE void GPIO_Unlock(void) +{ + WRITE_REG16(M4_GPIO->PWPR, GPIO_REG_UNPROTECT); +} + +en_result_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit); +void GPIO_DeInit(void); +void GPIO_Unlock(void); +void GPIO_Lock(void); +en_result_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit); +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState); +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint8_t u8Func, uint16_t u16BFE); +void GPIO_SetSubFunc(uint8_t u8Func); +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait); +void GPIO_InMOSCmd(uint16_t u16PortIdx, en_functional_state_t enNewState); +void GPIO_OE(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState); +//port pin +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadInputPort(uint8_t u8Port); +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin); +uint16_t GPIO_ReadOutputPort(uint8_t u8Port); +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin); +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal); + +/** + * @} + */ + +#endif /* DDL_GPIO_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_GPIO_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_hash.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_hash.h new file mode 100644 index 0000000000000000000000000000000000000000..25ca2ee62ca34f48a732a407a329df5e71e45cac --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_hash.h @@ -0,0 +1,233 @@ +/** + ******************************************************************************* + * @file hc32f4a0_hash.h + * @brief This file contains all the functions prototypes of the HASH driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_HASH_H__ +#define __HC32F4A0_HASH_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_HASH + * @{ + */ + +#if (DDL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup HASH_Global_Macros HASH Global Macros + * @{ + */ + +#define HASH_GROUP_LEN (64U) +#define LAST_GROUP_MAX_LEN (56U) + +/** @defgroup HASH_Mode HASH Mode + * @{ + */ +#define HASH_MODE_SHA_256 (0x00000000UL) /*!< SHA_256 Operating mode */ +#define HASH_MODE_HMAC (0x00000010UL) /*!< HMAC Operating mode */ +/** + * @} + */ + +/** + * @defgroup HASH_Key_Len HASH Key Length + * @{ + */ +#define HASH_KEY_LEN_LONG (HASH_CR_LKEY) /*!< Key length > 64 Bytes */ +#define HASH_KEY_LEN_SHORT (0x0UL) /*!< Key length <= 64 Bytes */ +/** + * @} + */ + +/** + * @defgroup HASH_Interrupt_Definition HASH Interrupt Definition + * @{ + */ +#define HASH_INT_GROUP (HASH_CR_HEIE) /*!< A set of data operations complete interrupt */ +#define HASH_INT_ALL (HASH_CR_HCIE) /*!< All data operations complete interrupt */ +/** + * @} + */ + +/** + * @defgroup HASH_Msg_Group HASH Messages Group + * @{ + */ +#define HASH_MSG_GRP_FIRST (HASH_CR_FST_GRP) /*!< The first group of messages or keys */ +#define HASH_MSG_GRP_END (HASH_CR_KMSG_END) /*!< The last group of messages or keys */ +#define HASH_MSG_GRP_ONLY_ONE (HASH_CR_FST_GRP | \ + HASH_CR_KMSG_END) /*!< Only one set of message or key */ +/** + * @} + */ + +/** + * @defgroup HASH_Status HASH Status + * @{ + */ +#define HASH_FLAG_START (HASH_CR_START) /*!< Operation in progress */ +#define HASH_FLAG_BUSY (HASH_CR_BUSY) /*!< HASH in operation */ +#define HASH_FLAG_CYC_END (HASH_CR_CYC_END) /*!< key or message operation completed */ +#define HASH_FLAG_HMAC_END (HASH_CR_HMAC_END) /*!< HMAC operation completed */ +/** + * @} + */ + +/** + * @defgroup HASH_Common_Trigger_Sel HASH common trigger source select + * @{ + */ +#define HASH_COM_TRIG1 (AOS_HASH_ITRGSELA_COMTRG_EN_0) +#define HASH_COM_TRIG2 (AOS_HASH_ITRGSELA_COMTRG_EN_1) +#define HASH_COM_TRIG_MASk (AOS_HASH_ITRGSELA_COMTRG_EN) +/** + * @} + */ + +/** + * @defgroup HASH_Common_Trigger_Reg_Sel HASH common trigger cource select + * @{ + */ +#define HASH_TRIG_REG_BLKCOM (0U) /*!< DMA block transfer complete register */ +#define HASH_TRIG_REG_TRNCOM (1U) /*!< DMA transfer complete register*/ +/** + * @} + */ + +/** + * @defgroup HASH_Trigger_Source_Sel HASH Trigger Source Select + * @{ + */ +#define HASH_TRG_SRC_DMA1_BTC0 (EVT_DMA1_BTC0) /*!< Select the DMA1 ch0 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC1 (EVT_DMA1_BTC1) /*!< Select the DMA1 ch1 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC2 (EVT_DMA1_BTC2) /*!< Select the DMA1 ch2 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC3 (EVT_DMA1_BTC3) /*!< Select the DMA1 ch3 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC4 (EVT_DMA1_BTC4) /*!< Select the DMA1 ch4 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC5 (EVT_DMA1_BTC5) /*!< Select the DMA1 ch5 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC6 (EVT_DMA1_BTC6) /*!< Select the DMA1 ch6 block transfer complete */ +#define HASH_TRG_SRC_DMA1_BTC7 (EVT_DMA1_BTC7) /*!< Select the DMA1 ch7 block transfer complete */ +#define HASH_TRG_SRC_DMA1_TC0 (EVT_DMA1_TC0) /*!< Select the DMA1 ch0 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC1 (EVT_DMA1_TC1) /*!< Select the DMA1 ch1 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC2 (EVT_DMA1_TC2) /*!< Select the DMA1 ch2 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC3 (EVT_DMA1_TC3) /*!< Select the DMA1 ch3 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC4 (EVT_DMA1_TC4) /*!< Select the DMA1 ch4 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC5 (EVT_DMA1_TC5) /*!< Select the DMA1 ch5 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC6 (EVT_DMA1_TC6) /*!< Select the DMA1 ch6 transfer complete*/ +#define HASH_TRG_SRC_DMA1_TC7 (EVT_DMA1_TC7) /*!< Select the DMA1 ch7 transfer complete*/ +#define HASH_TRG_SRC_DMA2_BTC0 (EVT_DMA2_BTC0) /*!< Select the DMA2 ch0 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC1 (EVT_DMA2_BTC1) /*!< Select the DMA2 ch1 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC2 (EVT_DMA2_BTC2) /*!< Select the DMA2 ch2 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC3 (EVT_DMA2_BTC3) /*!< Select the DMA2 ch3 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC4 (EVT_DMA2_BTC4) /*!< Select the DMA2 ch4 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC5 (EVT_DMA2_BTC5) /*!< Select the DMA2 ch5 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC6 (EVT_DMA2_BTC6) /*!< Select the DMA2 ch6 block transfer complete */ +#define HASH_TRG_SRC_DMA2_BTC7 (EVT_DMA2_BTC7) /*!< Select the DMA2 ch7 block transfer complete */ +#define HASH_TRG_SRC_DMA2_TC0 (EVT_DMA2_TC0) /*!< Select the DMA2 ch0 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC1 (EVT_DMA2_TC1) /*!< Select the DMA2 ch1 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC2 (EVT_DMA2_TC2) /*!< Select the DMA2 ch2 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC3 (EVT_DMA2_TC3) /*!< Select the DMA2 ch3 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC4 (EVT_DMA2_TC4) /*!< Select the DMA2 ch4 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC5 (EVT_DMA2_TC5) /*!< Select the DMA2 ch5 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC6 (EVT_DMA2_TC6) /*!< Select the DMA2 ch6 transfer complete*/ +#define HASH_TRG_SRC_DMA2_TC7 (EVT_DMA2_TC7) /*!< Select the DMA2 ch7 transfer complete*/ +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HASH_Global_Functions + * @{ + */ +en_result_t HASH_Calculate(const void *pvSrcData, + uint32_t u32SrcDataSize, + uint8_t au8MsgDigest[]); +en_result_t HMAC_Calculate(const void *pvSrcData, + uint32_t u32SrcDataSize, + const uint8_t au8Key[], + uint32_t u32KeyLength, + uint8_t au8MsgDigest[]); +en_result_t HASH_Start(void); +en_result_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState); +en_result_t HASH_SetMode(uint32_t u32HashMode); +en_result_t HASH_SetKeyLength(uint32_t u32KeyLen); +en_result_t HASH_MsgGrpConfig(uint32_t u32MsgGroup); +en_result_t HASH_ClearStatus(uint32_t u32ClearFlag); +void HASH_SetTriggerSrc(en_event_src_t enSrc); +void HASH_ComTriggerCmd(uint8_t u8TrigReg, uint32_t u32ComTrig, \ + en_functional_state_t enNewState); +en_flag_status_t HASH_GetStatus(uint32_t u32HashFlag); +void HASH_GetResult(uint8_t au8MsgDigest[]); +/** + * @} + */ + +#endif /* DDL_HASH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_HASH_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_hrpwm.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_hrpwm.h new file mode 100644 index 0000000000000000000000000000000000000000..385de0ef1790e8d2286706bbae55c4eedb6b442c --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_hrpwm.h @@ -0,0 +1,138 @@ +/** + ******************************************************************************* + * @file hc32f4a0_hrpwm.h + * @brief Head file for HRPWM module. + * + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-09-07 Wangmin Modify channel delay configure function + parameter type. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_HRPWM_H__ +#define __HC32F4A0_HRPWM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_HRPWM + * @{ + */ + +#if (DDL_HRPWM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HRPWM_Global_Macros HRPWM Global Macros + * @{ + */ + +#define HRPWM_CH_MIN (1UL) +#define HRPWM_CH_MAX (16UL) + +#define HRPWM_CH_DELAY_NUM_MIN (1U) +#define HRPWM_CH_DELAY_NUM_MAX (256U) + +/** @defgroup HRPWM_Calibrate_Unit_Define HRPWM Calibrate unit define + * @{ + */ +#define HRPWM_CAL_UNIT0 (0x00UL) +#define HRPWM_CAL_UNIT1 (0x01UL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup HRPWM_Global_Functions + * @{ + */ +/* HRPWM Judge the condition of calibration function */ +en_functional_state_t HRPWM_ConditionConfirm(void); + +/* Process for getting HRPWM Calibrate function code */ +en_result_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t* pu8Code); + +/* HRPWM Calibrate function enable or disable for specified unit */ +void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState); +/* HRPWM Calibrate function status get for specified unit */ +en_functional_state_t HRPWM_GetCalibrateStd(uint32_t u32Unit); +/* HRPWM Calibrate code get for specified unit */ +uint8_t HRPWM_GetCalCode(uint32_t u32Unit); + +/* HRPWM function enable or disable for specified channel */ +void HRPWM_CHCmd(uint32_t u32Ch, en_functional_state_t enNewState); +/* HRPWM positive edge adjust enable or disable for specified channel */ +void HRPWM_CHPositAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState); +/* HRPWM negative edge adjust enable or disable for specified channel */ +void HRPWM_CHNegatAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState); +/* HRPWM positive edge adjust delay counts configration for specified channel */ +void HRPWM_CHPositCfg(uint32_t u32Ch, uint8_t u8DelayNum); +/* HRPWM negative edge adjust delay counts configration for specified channel */ +void HRPWM_CHNegatCfg(uint32_t u32Ch, uint8_t u8DelayNum); + +/** + * @} + */ + +#endif /* DDL_HRPWM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_HRPWM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_i2c.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..5ea767610d54167c856b93388c9fc2ec612d9d6d --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_i2c.h @@ -0,0 +1,266 @@ +/** + ******************************************************************************* + * @file hc32f4a0_i2c.h + * @brief This file contains all the functions prototypes of the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hexiao First version + 2020-07-15 Hexiao Modify I2C_SmBusCmd to I2C_SetMode + 2020-08-31 Hexiao Remove invalid clock division value + 2020-10-30 Hexiao Optimize data transfer api,etc. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_I2C_H__ +#define __HC32F4A0_I2C_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_I2C + * @{ + */ + +#if (DDL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2C_Global_Types I2C Global Types + * @{ + */ + +/** + * @brief I2c configuration structure + */ +typedef struct +{ + uint32_t u32ClkDiv; /*!< I2C clock division for pclk3*/ + uint32_t u32Baudrate; /*!< I2C baudrate config*/ + uint32_t u32SclTime; /*!< The SCL rising and falling time, count of T(pclk3)*/ +}stc_i2c_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Macros I2C Global Macros + * @{ + */ + +/** @defgroup I2C_Buadrate_Max I2C baudrate max value + * @{ + */ +#define I2C_BAUDRATE_MAX (400000UL) +/** + * @} + */ + +/** @defgroup I2C_Mode Peripheral Mode + * @{ + */ +#define I2C_MODE_I2C (0UL) +#define I2C_MODE_SMBUS (2UL) +/** + * @} + */ + +/** @defgroup I2C_Transfer_Direction I2C transfer direction + * @{ + */ +#define I2C_DIR_TX (0x0U) +#define I2C_DIR_RX (0x1U) +/** + * @} + */ + +/** @defgroup I2C_Addr_Config I2C address configuration + * @{ + */ +#define I2C_ADDR_MODE_7BIT (0x0U) +#define I2C_ADDR_MODE_10BIT (I2C_SLR0_ADDRMOD0) +/** + * @} + */ + +/** @defgroup I2C_Clock_division I2C clock division + * @{ + */ +#define I2C_CLK_DIV1 (0UL) +#define I2C_CLK_DIV2 (1UL) +#define I2C_CLK_DIV4 (2UL) +#define I2C_CLK_DIV8 (3UL) +#define I2C_CLK_DIV16 (4UL) +#define I2C_CLK_DIV32 (5UL) +#define I2C_CLK_DIV64 (6UL) +#define I2C_CLK_DIV128 (7UL) +/** + * @} + */ + +/** @defgroup I2C_Address_Num I2C address number + * @{ + */ +#define I2C_ADDR_0 (0UL) +#define I2C_ADDR_1 (1UL) +/** + * @} + */ + +/** @defgroup I2C_Ack_Type I2C ack type + * @{ + */ +#define I2C_ACK (0UL) +#define I2C_NACK (I2C_CR1_ACK) +/** + * @} + */ + +/** @defgroup I2C_Smbus_Match_Cfg I2C smbus address match configuration + * @{ + */ +#define I2C_SMBUS_MATCH_ALRT (I2C_CR1_SMBALRTEN) +#define I2C_SMBUS_MATCH_DEFAULT (I2C_CR1_SMBDEFAULTEN) +#define I2C_SMBUS_MATCH_HOST (I2C_CR1_SMBHOSTEN) +/** + * @} + */ + +/** @defgroup I2C_Smbus_clear_mask I2C smbus clear mask + * @{ + */ +#define I2C_SMBUS_CONFIG_CLEARMASK (I2C_CR1_SMBALRTEN|I2C_CR1_SMBDEFAULTEN|I2C_CR1_SMBHOSTEN) +/** + * @} + */ + +/** @defgroup I2C_Digital_Filter_mode I2C digital filter mode + * @{ + */ +#define I2C_DIG_FILTMODE_1CYCLE (0UL << I2C_FLTR_DNF_POS) +#define I2C_DIG_FILTMODE_2CYCLE (1UL << I2C_FLTR_DNF_POS) +#define I2C_DIG_FILTMODE_3CYCLE (2UL << I2C_FLTR_DNF_POS) +#define I2C_DIG_FILTMODE_4CYCLE (3UL << I2C_FLTR_DNF_POS) +/** + * @} + */ + + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2C_Global_Functions + * @{ + */ + +/* Initialization and Configuration **********************************/ +void I2C_DeInit(M4_I2C_TypeDef* I2Cx); +en_result_t I2C_StructInit(stc_i2c_init_t* pstcI2C_InitStruct); +en_result_t I2C_Init(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err); +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err); +void I2C_SlaveAddrCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState); +void I2C_SlaveAddrConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr); +void I2C_SetMode(M4_I2C_TypeDef* I2Cx, uint32_t u32Mode); +void I2C_Cmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_FastAckCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_BusWaitCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_IntCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32IntEn, en_functional_state_t enNewState); + +void I2C_ClkHighTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutH); +void I2C_ClkLowTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutL); +void I2C_ClkHighTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_ClkLowTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_ClkTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_SmbusConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState); +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32DigFilterMode); +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); +void I2C_GeneralCallCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState); + +/* Start/Restart/Stop ************************************************/ +void I2C_GenerateStart(M4_I2C_TypeDef* I2Cx); +void I2C_GenerateReStart(M4_I2C_TypeDef* I2Cx); +void I2C_GenerateStop(M4_I2C_TypeDef* I2Cx); + +/* Status management *************************************************/ +en_flag_status_t I2C_GetStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32StatusBit); +void I2C_ClearStatus(M4_I2C_TypeDef* I2Cx, uint32_t u32StatusBit); + +/* Data transfer *****************************************************/ +void I2C_WriteDataReg(M4_I2C_TypeDef* I2Cx, uint8_t u8Data); +uint8_t I2C_ReadDataReg(const M4_I2C_TypeDef *I2Cx); +void I2C_AckConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AckConfig); + +/* High level functions for reference ********************************/ +en_result_t I2C_Start(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout); +en_result_t I2C_Restart(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout); +en_result_t I2C_TransAddr(M4_I2C_TypeDef* I2Cx, uint8_t u8Addr, uint8_t u8Dir, uint32_t u32Timeout); +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout); +en_result_t I2C_TransData(M4_I2C_TypeDef* I2Cx, uint8_t const pau8TxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_Receive(M4_I2C_TypeDef* I2Cx, uint8_t pau8RxData[], uint32_t u32Size, uint32_t u32Timeout); +en_result_t I2C_Stop(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout); +en_result_t I2C_MasterReceiveAndStop(M4_I2C_TypeDef* I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout); +/** + * @} + */ + +#endif /* DDL_I2C_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_i2s.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_i2s.h new file mode 100644 index 0000000000000000000000000000000000000000..00e7990c0479894b3e2be896b1cd736470e697b6 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_i2s.h @@ -0,0 +1,331 @@ +/** + ******************************************************************************* + * @file hc32f4a0_i2s.h + * @brief This file contains all the functions prototypes of the I2S driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_I2S_H__ +#define __HC32F4A0_I2S_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_I2S + * @{ + */ + +#if (DDL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Types I2S Global Types + * @{ + */ + +/** + * @brief I2S Init structure definition + */ +typedef struct +{ + uint32_t u32ClockSrc; /*!< Specifies the clock source of I2S. + This parameter can be a value of @ref I2S_Clock_Source */ + uint32_t u32Mode; /*!< Specifies the master/slave mode of I2S. + This parameter can be a value of @ref I2S_Mode */ + uint32_t u32ComProtocol; /*!< Specifies the communication protocol of I2S. + This parameter can be a value of @ref I2S_Com_Protocol */ + uint32_t u32TransMode; /*!< Specifies the transmission mode for the I2S communication. + This parameter can be a value of @ref I2S_Trans_Mode */ + uint32_t u32AudioFreq; /*!< Specifies the frequency selected for the I2S communication. + This parameter can be a value of @ref I2S_Audio_Frequency */ + uint32_t u32ChLen; /*!< Specifies the channel length for the I2S communication. + This parameter can be a value of @ref I2S_Channel_Length */ + uint32_t u32DataLen; /*!< Specifies the data length for the I2S communication. + This parameter can be a value of @ref I2S_Data_Length */ + uint32_t u32MCKOutput; /*!< Specifies the validity of the MCK output for I2S. + This parameter can be a value of @ref I2S_MCK_Output */ + uint32_t u32TransFIFOLevel; /*!< Specifies the level of transfer FIFO. + This parameter can be a value of @ref I2S_Trans_Level */ + uint32_t u32ReceiveFIFOLevel; /*!< Specifies the level of receive FIFO. + This parameter can be a value of @ref I2S_Receive_Level */ +} stc_i2s_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Macros I2S Global Macros + * @{ + */ + +/** + * @defgroup I2S_Clock_Source I2S Clock Source + * @{ + */ +#define I2S_CLK_SRC_PLL (I2S_CTRL_I2SPLLSEL) /*!< Internal PLL Clock */ +#define I2S_CLK_SRC_EXT (I2S_CTRL_CLKSEL) /*!< External Clock */ +/** + * @} + */ + +/** + * @defgroup I2S_Mode I2S Mode + * @{ + */ +#define I2S_MD_MASTER (0UL) /*!< Master mode */ +#define I2S_MD_SLAVE (I2S_CTRL_WMS) /*!< Slave mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Com_Protocol I2S Communication Protocol + * @{ + */ +#define I2S_COM_PROTOCOL_PHILLIPS (0UL) /*!< Phillips protocol */ +#define I2S_COM_PROTOCOL_MSB (I2S_CFGR_I2SSTD_0) /*!< MSB justified protocol */ +#define I2S_COM_PROTOCOL_LSB (I2S_CFGR_I2SSTD_1) /*!< LSB justified protocol */ +#define I2S_COM_PROTOCOL_PCM_SHORT (I2S_CFGR_I2SSTD) /*!< PCM short-frame protocol */ +#define I2S_COM_PROTOCOL_PCM_LONG (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC) /*!< PCM long-frame protocol */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Mode I2S Transfer Mode + * @{ + */ +#define I2S_TRANS_MD_HALF_DUPLEX_RX (0UL) /*!< Receive only and half duplex mode */ +#define I2S_TRANS_MD_HALF_DUPLEX_TX (I2S_CTRL_SDOE) /*!< Send only and half duplex mode */ +#define I2S_TRANS_MD_FULL_DUPLEX (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE) /*!< Full duplex mode */ +/** + * @} + */ + +/** + * @defgroup I2S_Audio_Frequency I2S Audio Frequency + * @{ + */ +#define I2S_AUDIO_FREQ_192K (192000UL) /*!< FS = 192000Hz */ +#define I2S_AUDIO_FREQ_96K (96000UL) /*!< FS = 96000Hz */ +#define I2S_AUDIO_FREQ_48K (48000UL) /*!< FS = 48000Hz */ +#define I2S_AUDIO_FREQ_44K (44100UL) /*!< FS = 44100Hz */ +#define I2S_AUDIO_FREQ_32K (32000UL) /*!< FS = 32000Hz */ +#define I2S_AUDIO_FREQ_22K (22050UL) /*!< FS = 22050Hz */ +#define I2S_AUDIO_FREQ_16K (16000UL) /*!< FS = 16000Hz */ +#define I2S_AUDIO_FREQ_8K (8000UL) /*!< FS = 8000Hz */ +#define I2S_AUDIO_FREQ_DEFAULT (2UL) +/** + * @} + */ + +/** + * @defgroup I2S_Channel_Length I2S Channel Length + * @{ + */ +#define I2S_CH_LEN_16BIT (0UL) /*!< Channel length is 16bits */ +#define I2S_CH_LEN_32BIT (I2S_CFGR_CHLEN) /*!< Channel length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_Data_Length I2S Data Length + * @{ + */ +#define I2S_DATA_LEN_16BIT (0UL) /*!< Transfer data length is 16bits */ +#define I2S_DATA_LEN_24BIT (I2S_CFGR_DATLEN_0) /*!< Transfer data length is 24bits */ +#define I2S_DATA_LEN_32BIT (I2S_CFGR_DATLEN_1) /*!< Transfer data length is 32bits */ +/** + * @} + */ + +/** + * @defgroup I2S_MCK_Output I2S MCK Output + * @{ + */ +#define I2S_MCK_OUTPUT_DISABLE (0UL) /*!< Disable the drive clock(MCK) output */ +#define I2S_MCK_OUTPUT_ENABLE (I2S_CTRL_MCKOE) /*!< Enable the drive clock(MCK) output */ +/** + * @} + */ + +/** + * @defgroup I2S_Trans_Level I2S Transfer Level + * @{ + */ +#define I2S_TRANS_LVL0 (0x00UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 0 */ +#define I2S_TRANS_LVL1 (0x01UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 1 */ +#define I2S_TRANS_LVL2 (0x02UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 2 */ +#define I2S_TRANS_LVL3 (0x03UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 3 */ +#define I2S_TRANS_LVL4 (0x04UL << I2S_CTRL_TXBIRQWL_POS) /*!< Transfer FIFO level is 4 */ +/** + * @} + */ + +/** + * @defgroup I2S_Receive_Level I2S Receive Level + * @{ + */ +#define I2S_RECEIVE_LVL0 (0x00UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 0 */ +#define I2S_RECEIVE_LVL1 (0x01UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 1 */ +#define I2S_RECEIVE_LVL2 (0x02UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 2 */ +#define I2S_RECEIVE_LVL3 (0x03UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 3 */ +#define I2S_RECEIVE_LVL4 (0x04UL << I2S_CTRL_RXBIRQWL_POS) /*!< Receive FIFO level is 4 */ +/** + * @} + */ + +/** + * @defgroup I2S_Com_Func I2S Communication Function + * @{ + */ +#define I2S_FUNC_TXE (I2S_CTRL_TXE) /*!< Transfer function */ +#define I2S_FUNC_RXE (I2S_CTRL_RXE) /*!< Receive function */ +#define I2S_FUNC_ALL (I2S_FUNC_TXE | I2S_FUNC_RXE) +/** + * @} + */ + +/** + * @defgroup I2S_Reset_Type I2S Reset Type + * @{ + */ +#define I2S_RST_TYPE_SW (I2S_CTRL_SRST) /*!< I2S software reset */ +#define I2S_RST_TYPE_CODEC (I2S_CTRL_CODECRC) /*!< Reset codec of I2S */ +#define I2S_RST_TYPE_FIFO (I2S_CTRL_FIFOR) /*!< Reset FIFO of I2S */ +#define I2S_RST_TYPE_ALL (I2S_RST_TYPE_SW | I2S_RST_TYPE_CODEC | I2S_RST_TYPE_FIFO) +/** + * @} + */ + +/** + * @defgroup I2S_Interrupt I2S Interrupt + * @{ + */ +#define I2S_INT_TX (I2S_CTRL_TXIE) /*!< Transfer interrupt */ +#define I2S_INT_RX (I2S_CTRL_RXIE) /*!< Receive interrupt */ +#define I2S_INT_ERR (I2S_CTRL_EIE) /*!< Communication error interrupt */ +#define I2S_INT_ALL (I2S_INT_TX | I2S_INT_RX | I2S_INT_ERR) +/** + * @} + */ + +/** + * @defgroup I2S_Flag I2S Flag + * @{ + */ +#define I2S_FLAG_TX_ALARM (I2S_SR_TXBA) /*!< Transfer buffer alarm flag */ +#define I2S_FLAG_RX_ALARM (I2S_SR_RXBA) /*!< Receive buffer alarm flag */ +#define I2S_FLAG_TX_EMPTY (I2S_SR_TXBE) /*!< Transfer buffer empty flag */ +#define I2S_FLAG_TX_FULL (I2S_SR_TXBF) /*!< Transfer buffer full flag */ +#define I2S_FLAG_RX_EMPTY (I2S_SR_RXBE) /*!< Receive buffer empty flag */ +#define I2S_FLAG_RX_FULL (I2S_SR_RXBF) /*!< Receive buffer full flag */ +#define I2S_FLAG_TX_ERR (I2S_ER_TXERR << 16U) /*!< Transfer overflow or underflow flag */ +#define I2S_FLAG_RX_ERR (I2S_ER_RXERR << 16U) /*!< Receive overflow flag */ +#define I2S_FLAG_ALL (I2S_FLAG_TX_ALARM | I2S_FLAG_RX_ALARM | I2S_FLAG_TX_EMPTY | \ + I2S_FLAG_TX_FULL | I2S_FLAG_RX_EMPTY | I2S_FLAG_RX_FULL | \ + I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +#define I2S_CLR_FLAG_ALL (I2S_FLAG_TX_ERR | I2S_FLAG_RX_ERR) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup I2S_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +void I2S_DeInit(M4_I2S_TypeDef *I2Sx); +en_result_t I2S_Init(M4_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit); +en_result_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit); +void I2S_SetSWReset(M4_I2S_TypeDef *I2Sx, uint32_t u32ResetType); +void I2S_SetTransMode(M4_I2S_TypeDef *I2Sx, uint32_t u32Mode); +void I2S_SetTransFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetReceiveFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level); +void I2S_SetComProtocol(M4_I2S_TypeDef *I2Sx, uint32_t u32Protocol); +en_result_t I2S_SetAudioFreq(M4_I2S_TypeDef *I2Sx, uint32_t u32Freq); +void I2S_MCKOutputCmd(M4_I2S_TypeDef *I2Sx, en_functional_state_t enNewState); +void I2S_FuncCmd(M4_I2S_TypeDef* I2Sx, uint32_t u32Func, en_functional_state_t enNewState); + +/* Transfer and receive data functions */ +void I2S_WriteData(M4_I2S_TypeDef *I2Sx, uint32_t u32Data); +uint32_t I2S_ReadData(const M4_I2S_TypeDef *I2Sx); +en_result_t I2S_Trans(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout); +en_result_t I2S_Receive(const M4_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); +en_result_t I2S_TransReceive(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout); + +/* Interrupt and flag management functions */ +void I2S_IntCmd(M4_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState); +en_flag_status_t I2S_GetStatus(const M4_I2S_TypeDef *I2Sx, uint32_t u32Flag); +void I2S_ClearStatus(M4_I2S_TypeDef *I2Sx, uint32_t u32Flag); + +/** + * @} + */ + +#endif /* DDL_I2S_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_I2S_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_icg.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_icg.h new file mode 100644 index 0000000000000000000000000000000000000000..fa722a90d7f7a3e543e782d60684c4beddb180c9 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_icg.h @@ -0,0 +1,441 @@ +/** + ******************************************************************************* + * @file hc32f4a0_icg.h + * @brief This file contains all the Macro Definitions of the ICG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_ICG_H__ +#define __HC32F4A0_ICG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_ICG + * @{ + */ + +#if (DDL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ICG_Global_Macros ICG Global Macros + * @{ + */ + +/** + * @defgroup ICG_SWDT_Reset_State ICG SWDT Reset State + * @{ + */ +#define ICG_SWDT_RESET_AUTOSTART (0UL) /*!< SWDT Auto Start after reset */ +#define ICG_SWDT_RESET_STOP (ICG_ICG0_SWDTAUTS) /*!< SWDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Trigger_Type ICG SWDT Trigger Type + * @{ + */ +#define ICG_SWDT_TRIG_INT (0UL) /*!< SWDT trigger interrupt */ +#define ICG_SWDT_TRIG_RESET (ICG_ICG0_SWDTITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Counter_Cycle ICG SWDT Counter Cycle + * @{ + */ +#define ICG_SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */ +#define ICG_SWDT_COUNTER_CYCLE_4096 (ICG_ICG0_SWDTPERI_0) /*!< 4096 clock cycle */ +#define ICG_SWDT_COUNTER_CYCLE_16384 (ICG_ICG0_SWDTPERI_1) /*!< 16384 clock cycle */ +#define ICG_SWDT_COUNTER_CYCLE_65536 (ICG_ICG0_SWDTPERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Clock_Division ICG SWDT Clock Division + * @{ + */ +#define ICG_SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */ +#define ICG_SWDT_CLOCK_DIV16 (ICG_ICG0_SWDTCKS_2) /*!< SWDTCLK/16 */ +#define ICG_SWDT_CLOCK_DIV32 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/32 */ +#define ICG_SWDT_CLOCK_DIV64 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1) /*!< SWDTCLK/64 */ +#define ICG_SWDT_CLOCK_DIV128 (ICG_ICG0_SWDTCKS_2 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/128 */ +#define ICG_SWDT_CLOCK_DIV256 (ICG_ICG0_SWDTCKS_3) /*!< SWDTCLK/256 */ +#define ICG_SWDT_CLOCK_DIV2048 (ICG_ICG0_SWDTCKS_3 | ICG_ICG0_SWDTCKS_1 | ICG_ICG0_SWDTCKS_0) /*!< SWDTCLK/2048 */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_Refresh_Range ICG SWDT Refresh Range + * @{ + */ +#define ICG_SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT (ICG_ICG0_SWDTWDPT_0) /*!< 0%~25% */ +#define ICG_SWDT_RANGE_25TO50PCT (ICG_ICG0_SWDTWDPT_1) /*!< 25%~50% */ +#define ICG_SWDT_RANGE_0TO50PCT (ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% */ +#define ICG_SWDT_RANGE_50TO75PCT (ICG_ICG0_SWDTWDPT_2) /*!< 50%~75% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~75% */ +#define ICG_SWDT_RANGE_25TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~75% */ +#define ICG_SWDT_RANGE_0TO75PCT (ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~75% */ +#define ICG_SWDT_RANGE_75TO100PCT (ICG_ICG0_SWDTWDPT_3) /*!< 75%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 75%~100% */ +#define ICG_SWDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_1 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~50% & 75%~100% */ +#define ICG_SWDT_RANGE_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2)) /*!< 50%~100% */ +#define ICG_SWDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_0)) /*!< 0%~25% & 50%~100% */ +#define ICG_SWDT_RANGE_25TO100PCT (ICG_ICG0_SWDTWDPT_3 | ICG_ICG0_SWDTWDPT_2 | ICG_ICG0_SWDTWDPT_1)) /*!< 25%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_SWDT_LPM_Count ICG SWDT Low Power Mode Count + * @brief SWDT count control in the sleep/stop mode + * @{ + */ +#define ICG_SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */ +#define ICG_SWDT_LPM_COUNT_STOP (ICG_ICG0_SWDTSLPOFF) /*!< SWDT count stop in the sleep/stop mode */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Reset_State ICG WDT Reset State + * @{ + */ +#define ICG_WDT_RESET_AUTOSTART (0UL) /*!< WDT Auto Start after reset */ +#define ICG_WDT_RESET_STOP (ICG_ICG0_WDTAUTS) /*!< WDT stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Trigger_Type ICG WDT Trigger Type + * @{ + */ +#define ICG_WDT_TRIG_INT (0UL) /*!< WDT trigger interrupt */ +#define ICG_WDT_TRIG_RESET (ICG_ICG0_WDTITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Counter_Cycle ICG WDT Counter Cycle + * @{ + */ +#define ICG_WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */ +#define ICG_WDT_COUNTER_CYCLE_4096 (ICG_ICG0_WDTPERI_0) /*!< 4096 clock cycle */ +#define ICG_WDT_COUNTER_CYCLE_16384 (ICG_ICG0_WDTPERI_1) /*!< 16384 clock cycle */ +#define ICG_WDT_COUNTER_CYCLE_65536 (ICG_ICG0_WDTPERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Clock_Division ICG WDT Clock Division + * @{ + */ +#define ICG_WDT_CLOCK_DIV4 (ICG_ICG0_WDTCKS_1) /*!< PCLK3/4 */ +#define ICG_WDT_CLOCK_DIV64 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/64 */ +#define ICG_WDT_CLOCK_DIV128 (ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/128 */ +#define ICG_WDT_CLOCK_DIV256 (ICG_ICG0_WDTCKS_3) /*!< PCLK3/256 */ +#define ICG_WDT_CLOCK_DIV512 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/512 */ +#define ICG_WDT_CLOCK_DIV1024 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1) /*!< PCLK3/1024 */ +#define ICG_WDT_CLOCK_DIV2028 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_1 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/2048 */ +#define ICG_WDT_CLOCK_DIV8192 (ICG_ICG0_WDTCKS_3 | ICG_ICG0_WDTCKS_2 | ICG_ICG0_WDTCKS_0) /*!< PCLK3/8192 */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_Refresh_Range ICG WDT Refresh Range + * @{ + */ +#define ICG_WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */ +#define ICG_WDT_RANGE_0TO25PCT (ICG_ICG0_WDTWDPT_0) /*!< 0%~25% */ +#define ICG_WDT_RANGE_25TO50PCT (ICG_ICG0_WDTWDPT_1) /*!< 25%~50% */ +#define ICG_WDT_RANGE_0TO50PCT (ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% */ +#define ICG_WDT_RANGE_50TO75PCT (ICG_ICG0_WDTWDPT_2) /*!< 50%~75% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~75% */ +#define ICG_WDT_RANGE_25TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~75% */ +#define ICG_WDT_RANGE_0TO75PCT (ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~75% */ +#define ICG_WDT_RANGE_75TO100PCT (ICG_ICG0_WDTWDPT_3) /*!< 75%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 75%~100% */ +#define ICG_WDT_RANGE_25TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1) /*!< 25%~50% & 75%~100% */ +#define ICG_WDT_RANGE_0TO50PCT_75TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_1 | ICG_ICG0_WDTWDPT_0) /*!< 0%~50% & 75%~100% */ +#define ICG_WDT_RANGE_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2) /*!< 50%~100% */ +#define ICG_WDT_RANGE_0TO25PCT_50TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_0) /*!< 0%~25% & 50%~100% */ +#define ICG_WDT_RANGE_25TO100PCT (ICG_ICG0_WDTWDPT_3 | ICG_ICG0_WDTWDPT_2 | ICG_ICG0_WDTWDPT_1) /*!< 25%~100% */ +/** + * @} + */ + +/** + * @defgroup ICG_WDT_LPM_Count ICG WDT Low Power Mode Count + * @brief WDT count control in the sleep mode + * @{ + */ +#define ICG_WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */ +#define ICG_WDT_LPM_COUNT_STOP (ICG_ICG0_WDTSLPOFF) /*!< WDT count stop in the sleep mode */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Frequency_Select ICG HRC Frequency Select + * @{ + */ +#define ICG_HRC_FREQ_20MHZ (0UL) /*!< HRC frequency 20MHZ */ +#define ICG_HRC_FREQ_16MHZ (ICG_ICG1_HRCFREQSEL) /*!< HRC frequency 16MHZ */ +/** + * @} + */ + +/** + * @defgroup ICG_HRC_Reset_State ICG HRC Reset State + * @{ + */ +#define ICG_HRC_RESET_OSCILLATION (0UL) /*!< HRC Oscillation after reset */ +#define ICG_HRC_RESET_STOP (ICG_ICG1_HRCSTOP) /*!< HRC stop after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Voltage_Threshold ICG BOR Voltage Threshold + * @{ + */ +#define ICG_BOR_VOL_THRESHOLD_1P9 (0UL) /*!< BOR voltage threshold 1.9V */ +#define ICG_BOR_VOL_THRESHOLD_2P0 (ICG_ICG1_BOR_LEV_0) /*!< BOR voltage threshold 2.0V */ +#define ICG_BOR_VOL_THRESHOLD_2P1 (ICG_ICG1_BOR_LEV_1) /*!< BOR voltage threshold 2.1V */ +#define ICG_BOR_VOL_THRESHOLD_2P3 (ICG_ICG1_BOR_LEV) /*!< BOR voltage threshold 2.3V */ +/** + * @} + */ + +/** + * @defgroup ICG_BOR_Reset_State ICG BOR Reset State + * @{ + */ +#define ICG_BOR_RESET_ENABLE (0UL) /*!< Enable BOR voltage detection after reset */ +#define ICG_BOR_RESET_DISABLE (ICG_ICG1_BORDIS) /*!< Disable BOR voltage detection after reset */ +/** + * @} + */ + +/** + * @defgroup ICG_FLASH_Bank_Reset_State ICG FLASH Bank Reset State + * @{ + */ +#define ICG_FLASH_BANK_1 (0xFFFFFFFFUL) /*!< After reset, 1MBytes flash are provided by bank0 */ +#define ICG_FLASH_BANK_12 (0x004B4B4BUL) /*!< After reset, 1MBytes flash are provided by bank0 and bank1 with 512Bytes each */ +/** + * @} + */ + +/** + * @defgroup ICG_FLASH_Protect_Reset_State ICG FLASH Protect Reset State + * @brief Enable or disable D-BUS read protection for addresses 0x00000000 - 0x0001FFFF + * @{ + */ +#define ICG_FLASH_PROTECT_RESET_ENABLE (0x00004450UL) /*!< Enable D-BUS read protection after reset */ +#define ICG_FLASH_PROTECT_RESET_DISABLE (0xFFFFFFFFUL) /*!< Disable D-BUS read protection after reset */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Configuration ICG Register Configuration + * @{ + */ + +/** + ******************************************************************************* + * @defgroup ICG_SWDT_Preload_Configuration ICG SWDT Preload Configuration + * @{ + ******************************************************************************* + */ +/* SWDT register config */ +#define ICG0_RB_SWDT_AUTS (ICG_SWDT_RESET_STOP) +#define ICG0_RB_SWDT_ITS (ICG_SWDT_TRIG_INT) +#define ICG0_RB_SWDT_PERI (ICG_SWDT_COUNTER_CYCLE_65536) +#define ICG0_RB_SWDT_CKS (ICG_SWDT_CLOCK_DIV2048) +#define ICG0_RB_SWDT_WDPT (ICG_SWDT_RANGE_0TO100PCT) +#define ICG0_RB_SWDT_SLTPOFF (ICG_SWDT_LPM_COUNT_CONTINUE) + +/* SWDT register value */ +#define ICG0_RB_SWDT_CONFIG (ICG0_RB_SWDT_AUTS | ICG0_RB_SWDT_ITS | \ + ICG0_RB_SWDT_PERI | ICG0_RB_SWDT_CKS | \ + ICG0_RB_SWDT_WDPT | ICG0_RB_SWDT_SLTPOFF) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_WDT_Preload_Configuration ICG WDT Preload Configuration + * @{ + ******************************************************************************* + */ +/* WDT register config */ +#define ICG0_RB_WDT_AUTS (ICG_WDT_RESET_STOP) +#define ICG0_RB_WDT_ITS (ICG_WDT_TRIG_INT) +#define ICG0_RB_WDT_PERI (ICG_WDT_COUNTER_CYCLE_65536) +#define ICG0_RB_WDT_CKS (ICG_WDT_CLOCK_DIV8192) +#define ICG0_RB_WDT_WDPT (ICG_WDT_RANGE_0TO100PCT) +#define ICG0_RB_WDT_SLTPOFF (ICG_WDT_LPM_COUNT_CONTINUE) + +/* WDT register value */ +#define ICG0_RB_WDT_CONFIG (ICG0_RB_WDT_AUTS | ICG0_RB_WDT_ITS | \ + ICG0_RB_WDT_PERI | ICG0_RB_WDT_CKS | \ + ICG0_RB_WDT_WDPT | ICG0_RB_WDT_SLTPOFF) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_HRC_Preload_Configuration ICG HRC Preload Configuration + * @{ + ******************************************************************************* + */ +/* HRC register config */ +#define ICG1_RB_HRC_FREQSEL (ICG_HRC_FREQ_16MHZ) +#define ICG1_RB_HRC_STOP (ICG_HRC_RESET_STOP) + +/* HRC register value */ +#define ICG1_RB_HRC_CONFIG (ICG1_RB_HRC_FREQSEL | ICG1_RB_HRC_STOP) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_BOR_Preload_Configuration ICG BOR Preload Configuration + * @{ + ******************************************************************************* + */ +/* BOR register config */ +#define ICG1_RB_BOR_LEV (ICG_BOR_VOL_THRESHOLD_2P3) +#define ICG1_RB_BOR_DIS (ICG_BOR_RESET_DISABLE) + +/* BOR register value */ +#define ICG1_RB_BOR_CONFIG (ICG1_RB_BOR_LEV | ICG1_RB_BOR_DIS) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_FLASH_Bank_Preload_Configuration ICG FLASH Bank Preload Configuration + * @{ + ******************************************************************************* + */ +/* FLASH Bank register value */ +#define ICG2_RB_FLASH_BANK_CONFIG (ICG_FLASH_BANK_1) +/** + * @} + */ + +/** + ******************************************************************************* + * @defgroup ICG_FLASH_Protect_Preload_Configuration ICG FLASH Protect Preload Configuration + * @{ + ******************************************************************************* + */ +/* FLASH Read Protect register value */ +#define ICG3_RB_FLASH_PROTECT_CONFIG (ICG_FLASH_PROTECT_RESET_DISABLE) +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup ICG_Register_Value ICG Register Value + * @{ + */ +/* ICG register value */ +#define ICG_REG_CFG0_CONSTANT (ICG0_RB_WDT_CONFIG | ICG0_RB_SWDT_CONFIG | 0xE000E000UL) +#define ICG_REG_CFG1_CONSTANT (ICG1_RB_BOR_CONFIG | ICG1_RB_HRC_CONFIG | 0xFFF8FEFEUL) +#define ICG_REG_CFG2_CONSTANT (ICG2_RB_FLASH_BANK_CONFIG | 0xFF000000UL) +#define ICG_REG_CFG3_CONSTANT (ICG3_RB_FLASH_PROTECT_CONFIG | 0xFFFF0000UL) +/* ICG reserved value */ +#define ICG_RESERVED_CONSTANT (0xFFFFFFFFUL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +#endif /* DDL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_ICG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_interrupts.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_interrupts.h new file mode 100644 index 0000000000000000000000000000000000000000..c8d13a81fe4bf4dbada1b47e35aebf1c976cb1b6 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_interrupts.h @@ -0,0 +1,1033 @@ +/** + ******************************************************************************* + * @file hc32f4a0_interrupts.h + * @brief This file contains all the functions prototypes of the interrupt driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-08-25 Zhangxl Modify for MISRAC2012-8.4 + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_INTERRUPTS_H__ +#define __HC32F4A0_INTERRUPTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_INTERRUPTS + * @{ + */ + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Types INTC Global Types + * @{ + */ +/** + * @brief Interrupt registration structure definition + */ +typedef struct +{ + en_int_src_t enIntSrc; /*!< Peripheral interrupt number, can be any value @ref en_int_src_t */ + IRQn_Type enIRQn; /*!< Peripheral IRQ type, can be Int000_IRQn~Int127_IRQn @ref IRQn_Type */ + func_ptr_t pfnCallback;/*!< Callback function for corresponding peripheral IRQ */ +} stc_irq_signin_config_t; + +/** + * @brief NMI initialize configuration structure definition + */ +typedef struct +{ + uint32_t u32NmiSrc; /*!< NMI trigger source, @ref NMI_TriggerSrc_Sel for details */ + func_ptr_t pfnNmiCallback; /*!< NMI Callback function pointers */ +}stc_nmi_init_t; + +/** + * @brief EXINT initialize configuration structure definition + */ +typedef struct +{ + uint32_t u32ExIntCh; /*!< ExInt CH.0~15 @ref EXINT_Channel_Sel */ + uint32_t u32ExIntFAE; /*!< ExInt filter A function setting, @ref EXINT_FilterAClock_Sel for details */ + uint32_t u32ExIntFAClk; /*!< ExInt filter A clock division, @ref EXINT_FilterAClock_Div for details */ + uint32_t u32ExIntFBE; /*!< ExInt filter B function setting, @ref EXINT_FilterBClock_Sel for details*/ + uint32_t u32ExIntFBTime; /*!< ExInt filter B time, @ref EXINT_FilterBTim_Sel for details*/ + uint32_t u32ExIntLvl; /*!< ExInt trigger edge, @ref EXINT_Trigger_Sel for details */ +}stc_exint_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Macros INTC Global Macros + * @{ + */ +/** + * @defgroup INTC_DefaultPriority_Sel Interrupt default priority level + * Possible values are 0 (high priority) to 15 (low priority) + * @{ + */ +#define DDL_IRQ_PRIORITY_DEFAULT (15U) +/** + * @} + */ + +/** + * @defgroup INTC_Priority_Sel Interrupt priority level 00 ~ 15 + * @{ + */ +#define DDL_IRQ_PRIORITY_00 (0U) +#define DDL_IRQ_PRIORITY_01 (1U) +#define DDL_IRQ_PRIORITY_02 (2U) +#define DDL_IRQ_PRIORITY_03 (3U) +#define DDL_IRQ_PRIORITY_04 (4U) +#define DDL_IRQ_PRIORITY_05 (5U) +#define DDL_IRQ_PRIORITY_06 (6U) +#define DDL_IRQ_PRIORITY_07 (7U) +#define DDL_IRQ_PRIORITY_08 (8U) +#define DDL_IRQ_PRIORITY_09 (9U) +#define DDL_IRQ_PRIORITY_10 (10U) +#define DDL_IRQ_PRIORITY_11 (11U) +#define DDL_IRQ_PRIORITY_12 (12U) +#define DDL_IRQ_PRIORITY_13 (13U) +#define DDL_IRQ_PRIORITY_14 (14U) +#define DDL_IRQ_PRIORITY_15 (15U) +/** + * @} + */ + +/** + * @defgroup INTC_Bit_mask definition Bit Mask + * @{ + */ +#define BIT_MASK_00 (1UL << 0U) +#define BIT_MASK_01 (1UL << 1U) +#define BIT_MASK_02 (1UL << 2U) +#define BIT_MASK_03 (1UL << 3U) +#define BIT_MASK_04 (1UL << 4U) +#define BIT_MASK_05 (1UL << 5U) +#define BIT_MASK_06 (1UL << 6U) +#define BIT_MASK_07 (1UL << 7U) +#define BIT_MASK_08 (1UL << 8U) +#define BIT_MASK_09 (1UL << 9U) +#define BIT_MASK_10 (1UL << 10U) +#define BIT_MASK_11 (1UL << 11U) +#define BIT_MASK_12 (1UL << 12U) +#define BIT_MASK_13 (1UL << 13U) +#define BIT_MASK_14 (1UL << 14U) +#define BIT_MASK_15 (1UL << 15U) +#define BIT_MASK_16 (1UL << 16U) +#define BIT_MASK_17 (1UL << 17U) +#define BIT_MASK_18 (1UL << 18U) +#define BIT_MASK_19 (1UL << 19U) +#define BIT_MASK_20 (1UL << 20U) +#define BIT_MASK_21 (1UL << 21U) +#define BIT_MASK_22 (1UL << 22U) +#define BIT_MASK_23 (1UL << 23U) +#define BIT_MASK_24 (1UL << 24U) +#define BIT_MASK_25 (1UL << 25U) +#define BIT_MASK_26 (1UL << 26U) +#define BIT_MASK_27 (1UL << 27U) +#define BIT_MASK_28 (1UL << 28U) +#define BIT_MASK_29 (1UL << 29U) +#define BIT_MASK_30 (1UL << 30U) +#define BIT_MASK_31 (1UL << 31U) +/** + * @} + */ + +/** + * @defgroup NMI_TriggerSrc_Sel NMI trigger source selection + * @{ + */ +#define NMI_SRC_SWDT (1UL << INTC_NMIFR_SWDTFR_POS) +#define NMI_SRC_PVD1 (1UL << INTC_NMIFR_PVD1FR_POS) +#define NMI_SRC_PVD2 (1UL << INTC_NMIFR_PVD2FR_POS) +#define NMI_SRC_XTAL (1UL << INTC_NMIFR_XTALSTPFR_POS) +#define NMI_SRC_SRAM_PARITY (1UL << INTC_NMIFR_REPFR_POS) +#define NMI_SRC_SRAM_ECC (1UL << INTC_NMIFR_RECCFR_POS) +#define NMI_SRC_BUS_ERR (1UL << INTC_NMIFR_BUSMFR_POS) +#define NMI_SRC_WDT (1UL << INTC_NMIFR_WDTFR_POS) +#define NMI_SRC_MASK (NMI_SRC_SWDT | NMI_SRC_PVD1 | \ + NMI_SRC_PVD2 | NMI_SRC_XTAL | \ + NMI_SRC_BUS_ERR | NMI_SRC_SRAM_PARITY | \ + NMI_SRC_WDT | NMI_SRC_SRAM_ECC) +/** + * @} + */ + +/** + * @defgroup NOCCR_Register_Msk Noise cancel register mask + * @{ + */ +#define INTC_NOCCR_MASK (INTC_NOCCR_NOCSEL) + +/** + * @} + */ + + +/** + * @defgroup MNI_Register_Msk NMI register mask + * @{ + */ +#define INTC_NMIENR_MASK (INTC_NMIENR_SWDTENR | INTC_NMIENR_PVD1ENR | \ + INTC_NMIENR_PVD2ENR | INTC_NMIENR_XTALSTPENR | \ + INTC_NMIENR_REPENR | INTC_NMIENR_RECCENR | \ + INTC_NMIENR_BUSMENR | INTC_NMIENR_WDTENR) + +#define INTC_NMIFR_MASK (INTC_NMIFR_SWDTFR | INTC_NMIFR_PVD1FR | \ + INTC_NMIFR_PVD2FR | INTC_NMIFR_XTALSTPFR | \ + INTC_NMIFR_REPFR | INTC_NMIFR_RECCFR | \ + INTC_NMIFR_BUSMFR | INTC_NMIFR_WDTFR) + +#define INTC_NMICLR_MASK (INTC_NMICFR_SWDTCFR | INTC_NMICFR_PVD1CFR | \ + INTC_NMICFR_PVD2CFR | INTC_NMICFR_XTALSTPCFR | \ + INTC_NMICFR_REPCFR | INTC_NMICFR_RECCCFR | \ + INTC_NMICFR_BUSMCFR | INTC_NMICFR_WDTCFR) +/** + * @} + */ + +/** + * @defgroup EXINT_Channel_Sel External interrupt channel selection + * @{ + */ +#define EXINT_CH00 (1UL << 0U) +#define EXINT_CH01 (1UL << 1U) +#define EXINT_CH02 (1UL << 2U) +#define EXINT_CH03 (1UL << 3U) +#define EXINT_CH04 (1UL << 4U) +#define EXINT_CH05 (1UL << 5U) +#define EXINT_CH06 (1UL << 6U) +#define EXINT_CH07 (1UL << 7U) +#define EXINT_CH08 (1UL << 8U) +#define EXINT_CH09 (1UL << 9U) +#define EXINT_CH10 (1UL <<10U) +#define EXINT_CH11 (1UL <<11U) +#define EXINT_CH12 (1UL <<12U) +#define EXINT_CH13 (1UL <<13U) +#define EXINT_CH14 (1UL <<14U) +#define EXINT_CH15 (1UL <<15U) +#define EXINT_CH_MASK (EXINT_CH00 | EXINT_CH01 | EXINT_CH02 | EXINT_CH03 | \ + EXINT_CH04 | EXINT_CH05 | EXINT_CH06 | EXINT_CH07 | \ + EXINT_CH08 | EXINT_CH09 | EXINT_CH10 | EXINT_CH11 | \ + EXINT_CH12 | EXINT_CH13 | EXINT_CH14 | EXINT_CH15) +/** + * @} + */ + +/** + * @defgroup EXINT_FilterAClock_Sel External interrupt filter A function selection + * @{ + */ +#define EXINT_FILTER_A_OFF (0UL) +#define EXINT_FILTER_A_ON (INTC_EIRQCR_EFEN) +/** + * @} + */ + +/** + * @defgroup EXINT_FilterBClock_Sel External interrupt filter B function selection + * @{ + */ +#define EXINT_FILTER_B_OFF (0UL) +#define EXINT_FILTER_B_ON (INTC_EIRQCR_NOCEN) +/** + * @} + */ + +/** + * @defgroup EXINT_FilterAClock_Div External interrupt filter A sampling clock division selection + * @{ + */ +#define EXINT_FACLK_HCLK_DIV1 (0UL) +#define EXINT_FACLK_HCLK_DIV8 (INTC_EIRQCR_EISMPCLK_0) +#define EXINT_FACLK_HCLK_DIV32 (INTC_EIRQCR_EISMPCLK_1) +#define EXINT_FACLK_HCLK_DIV64 (INTC_EIRQCR_EISMPCLK) +/** + * @} + */ + +/** + * @defgroup EXINT_FilterBTim_Sel External interrupt filter B time selection + * @{ + */ +#define EXINT_FBTIM_500NS (0UL << INTC_NOCCR_NOCSEL_POS) +#define EXINT_FBTIM_1US (1UL << INTC_NOCCR_NOCSEL_POS) +#define EXINT_FBTIM_2US (2UL << INTC_NOCCR_NOCSEL_POS) +#define EXINT_FBTIM_4US (3UL << INTC_NOCCR_NOCSEL_POS) +/** + * @} + */ + +/** + * @defgroup EXINT_Trigger_Sel External interrupt trigger method selection + * @{ + */ +#define EXINT_TRIGGER_FALLING (0UL) +#define EXINT_TRIGGER_RISING (INTC_EIRQCR_EIRQTRG_0) +#define EXINT_TRIGGER_BOTH (INTC_EIRQCR_EIRQTRG_1) +#define EXINT_TRIGGER_LOW (INTC_EIRQCR_EIRQTRG) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup INTC_Global_Functions + * @{ + */ + +/** + * @brief AOS software trigger. + * @param None + * @retval None + */ +__STATIC_INLINE void AOS_SW_Trigger(void) +{ + WRITE_REG32(bM4_AOS->INT_SFTTRG_b.STRG, Set); +} + +/** + * @brief AOS common trigger source 1 config. + * @param [in] enTrig can be any value @ref en_event_src_t + * @retval None + */ +__STATIC_INLINE void AOS_COM_Trigger1(en_event_src_t enTrig) +{ + WRITE_REG32(M4_AOS->COMTRG1, enTrig); +} + +/** + * @brief AOS common trigger source 2 config. + * @param [in] enTrig can be any value @ref en_event_src_t + * @retval None + */ +__STATIC_INLINE void AOS_COM_Trigger2(en_event_src_t enTrig) +{ + WRITE_REG32(M4_AOS->COMTRG2, enTrig); +} + +en_result_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig); +en_result_t INTC_IrqSignOut(IRQn_Type enIRQn); +en_result_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState); +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState); +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState); +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState); +void INTC_SWICmd(uint32_t u32SWI, en_functional_state_t enNewState); + +en_result_t NMI_Init(const stc_nmi_init_t *pstcNmiInit); +en_result_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit); +en_flag_status_t NMI_GetNmiSrc(uint32_t u32NmiSrc); +void NMI_SetNmiSrc(uint32_t u32NmiSrc); +void NMI_ClrNmiSrc(uint32_t u32NmiSrc); + +en_result_t EXINT_Init(const stc_exint_init_t *pstcExIntInit); +en_result_t EXINT_StructInit(stc_exint_init_t *pstcExIntInit); +en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh); +void EXINT_ClrExIntSrc(uint32_t u32ExIntCh); + +void NMI_Handler(void); +void HardFault_Handler(void); +void MemManage_Handler(void); +void BusFault_Handler(void); +void UsageFault_Handler(void); +void SVC_Handler(void); +void DebugMon_Handler(void); +void PendSV_Handler(void); +void SysTick_Handler(void); +void IRQ000_Handler(void); +void IRQ001_Handler(void); +void IRQ002_Handler(void); +void IRQ003_Handler(void); +void IRQ004_Handler(void); +void IRQ005_Handler(void); +void IRQ006_Handler(void); +void IRQ007_Handler(void); +void IRQ008_Handler(void); +void IRQ009_Handler(void); +void IRQ010_Handler(void); +void IRQ011_Handler(void); +void IRQ012_Handler(void); +void IRQ013_Handler(void); +void IRQ014_Handler(void); +void IRQ015_Handler(void); +void IRQ016_Handler(void); +void IRQ017_Handler(void); +void IRQ018_Handler(void); +void IRQ019_Handler(void); +void IRQ020_Handler(void); +void IRQ021_Handler(void); +void IRQ022_Handler(void); +void IRQ023_Handler(void); +void IRQ024_Handler(void); +void IRQ025_Handler(void); +void IRQ026_Handler(void); +void IRQ027_Handler(void); +void IRQ028_Handler(void); +void IRQ029_Handler(void); +void IRQ030_Handler(void); +void IRQ031_Handler(void); +void IRQ032_Handler(void); +void IRQ033_Handler(void); +void IRQ034_Handler(void); +void IRQ035_Handler(void); +void IRQ036_Handler(void); +void IRQ037_Handler(void); +void IRQ038_Handler(void); +void IRQ039_Handler(void); +void IRQ040_Handler(void); +void IRQ041_Handler(void); +void IRQ042_Handler(void); +void IRQ043_Handler(void); +void IRQ044_Handler(void); +void IRQ045_Handler(void); +void IRQ046_Handler(void); +void IRQ047_Handler(void); +void IRQ048_Handler(void); +void IRQ049_Handler(void); +void IRQ050_Handler(void); +void IRQ051_Handler(void); +void IRQ052_Handler(void); +void IRQ053_Handler(void); +void IRQ054_Handler(void); +void IRQ055_Handler(void); +void IRQ056_Handler(void); +void IRQ057_Handler(void); +void IRQ058_Handler(void); +void IRQ059_Handler(void); +void IRQ060_Handler(void); +void IRQ061_Handler(void); +void IRQ062_Handler(void); +void IRQ063_Handler(void); +void IRQ064_Handler(void); +void IRQ065_Handler(void); +void IRQ066_Handler(void); +void IRQ067_Handler(void); +void IRQ068_Handler(void); +void IRQ069_Handler(void); +void IRQ070_Handler(void); +void IRQ071_Handler(void); +void IRQ072_Handler(void); +void IRQ073_Handler(void); +void IRQ074_Handler(void); +void IRQ075_Handler(void); +void IRQ076_Handler(void); +void IRQ077_Handler(void); +void IRQ078_Handler(void); +void IRQ079_Handler(void); +void IRQ080_Handler(void); +void IRQ081_Handler(void); +void IRQ082_Handler(void); +void IRQ083_Handler(void); +void IRQ084_Handler(void); +void IRQ085_Handler(void); +void IRQ086_Handler(void); +void IRQ087_Handler(void); +void IRQ088_Handler(void); +void IRQ089_Handler(void); +void IRQ090_Handler(void); +void IRQ091_Handler(void); +void IRQ092_Handler(void); +void IRQ093_Handler(void); +void IRQ094_Handler(void); +void IRQ095_Handler(void); +void IRQ096_Handler(void); +void IRQ097_Handler(void); +void IRQ098_Handler(void); +void IRQ099_Handler(void); +void IRQ100_Handler(void); +void IRQ101_Handler(void); +void IRQ102_Handler(void); +void IRQ103_Handler(void); +void IRQ104_Handler(void); +void IRQ105_Handler(void); +void IRQ106_Handler(void); +void IRQ107_Handler(void); +void IRQ108_Handler(void); +void IRQ109_Handler(void); +void IRQ110_Handler(void); +void IRQ111_Handler(void); +void IRQ112_Handler(void); +void IRQ113_Handler(void); +void IRQ114_Handler(void); +void IRQ115_Handler(void); +void IRQ116_Handler(void); +void IRQ117_Handler(void); +void IRQ118_Handler(void); +void IRQ119_Handler(void); +void IRQ120_Handler(void); +void IRQ121_Handler(void); +void IRQ122_Handler(void); +void IRQ123_Handler(void); +void IRQ124_Handler(void); +void IRQ125_Handler(void); +void IRQ126_Handler(void); +void IRQ127_Handler(void); +void IRQ128_Handler(void); +void IRQ129_Handler(void); +void IRQ130_Handler(void); +void IRQ131_Handler(void); +void IRQ132_Handler(void); +void IRQ133_Handler(void); +void IRQ134_Handler(void); +void IRQ135_Handler(void); +void IRQ136_Handler(void); +void IRQ137_Handler(void); +void IRQ138_Handler(void); +void IRQ139_Handler(void); +void IRQ140_Handler(void); +void IRQ141_Handler(void); +void IRQ142_Handler(void); +void IRQ143_Handler(void); + +void NMI_IrqHandler(void); +void HardFault_IrqHandler(void); +void MemManage_IrqHandler(void); +void BusFault_IrqHandler(void); +void UsageFault_IrqHandler(void); +void SVC_IrqHandler(void); +void DebugMon_IrqHandler(void); +void PendSV_IrqHandler(void); +void SysTick_IrqHandler(void); +void EXTINT_00_IrqHandler(void); +void EXTINT_01_IrqHandler(void); +void EXTINT_02_IrqHandler(void); +void EXTINT_03_IrqHandler(void); +void EXTINT_04_IrqHandler(void); +void EXTINT_05_IrqHandler(void); +void EXTINT_06_IrqHandler(void); +void EXTINT_07_IrqHandler(void); +void EXTINT_08_IrqHandler(void); +void EXTINT_09_IrqHandler(void); +void EXTINT_10_IrqHandler(void); +void EXTINT_11_IrqHandler(void); +void EXTINT_12_IrqHandler(void); +void EXTINT_13_IrqHandler(void); +void EXTINT_14_IrqHandler(void); +void EXTINT_15_IrqHandler(void); +void DMA_1_Tc0_IrqHandler(void); +void DMA_1_Tc1_IrqHandler(void); +void DMA_1_Tc2_IrqHandler(void); +void DMA_1_Tc3_IrqHandler(void); +void DMA_1_Tc4_IrqHandler(void); +void DMA_1_Tc5_IrqHandler(void); +void DMA_1_Tc6_IrqHandler(void); +void DMA_1_Tc7_IrqHandler(void); +void DMA_1_Btc0_IrqHandler(void); +void DMA_1_Btc1_IrqHandler(void); +void DMA_1_Btc2_IrqHandler(void); +void DMA_1_Btc3_IrqHandler(void); +void DMA_1_Btc4_IrqHandler(void); +void DMA_1_Btc5_IrqHandler(void); +void DMA_1_Btc6_IrqHandler(void); +void DMA_1_Btc7_IrqHandler(void); +void DMA_1_Err0_IrqHandler(void); +void DMA_1_Err1_IrqHandler(void); +void DMA_1_Err2_IrqHandler(void); +void DMA_1_Err3_IrqHandler(void); +void DMA_1_Err4_IrqHandler(void); +void DMA_1_Err5_IrqHandler(void); +void DMA_1_Err6_IrqHandler(void); +void DMA_1_Err7_IrqHandler(void); +void DMA_2_Tc0_IrqHandler(void); +void DMA_2_Tc1_IrqHandler(void); +void DMA_2_Tc2_IrqHandler(void); +void DMA_2_Tc3_IrqHandler(void); +void DMA_2_Tc4_IrqHandler(void); +void DMA_2_Tc5_IrqHandler(void); +void DMA_2_Tc6_IrqHandler(void); +void DMA_2_Tc7_IrqHandler(void); +void DMA_2_Btc0_IrqHandler(void); +void DMA_2_Btc1_IrqHandler(void); +void DMA_2_Btc2_IrqHandler(void); +void DMA_2_Btc3_IrqHandler(void); +void DMA_2_Btc4_IrqHandler(void); +void DMA_2_Btc5_IrqHandler(void); +void DMA_2_Btc6_IrqHandler(void); +void DMA_2_Btc7_IrqHandler(void); +void DMA_2_Err0_IrqHandler(void); +void DMA_2_Err1_IrqHandler(void); +void DMA_2_Err2_IrqHandler(void); +void DMA_2_Err3_IrqHandler(void); +void DMA_2_Err4_IrqHandler(void); +void DMA_2_Err5_IrqHandler(void); +void DMA_2_Err6_IrqHandler(void); +void DMA_2_Err7_IrqHandler(void); +void EFM_PgmEraseErr_IrqHandler(void); +void EFM_ColErr_IrqHandler(void); +void EFM_OpEnd_IrqHandler(void); +void QSPI_Err_IrqHandler(void); +void MAU_Sqrt_IrqHandler(void); +void DVP_FrameStart_IrqHandler(void); +void DVP_FrameEnd_IrqHandler(void); +void DVP_LineStart_IrqHandler(void); +void DVP_LineEnd_IrqHandler(void); +void DVP_SwSyncErr_IrqHandler(void); +void DVP_FifoErr_IrqHandler(void); +void FMAC_1_IrqHandler(void); +void FMAC_2_IrqHandler(void); +void FMAC_3_IrqHandler(void); +void FMAC_4_IrqHandler(void); +void DCU_1_IrqHandler(void); +void DCU_2_IrqHandler(void); +void DCU_3_IrqHandler(void); +void DCU_4_IrqHandler(void); +void DCU_5_IrqHandler(void); +void DCU_6_IrqHandler(void); +void DCU_7_IrqHandler(void); +void DCU_8_IrqHandler(void); +void TMR0_1_CmpA_IrqHandler(void); +void TMR0_1_CmpB_IrqHandler(void); +void TMR0_2_CmpA_IrqHandler(void); +void TMR0_2_CmpB_IrqHandler(void); +void TMR2_1_CmpA_IrqHandler(void); +void TMR2_1_CmpB_IrqHandler(void); +void TMR2_1_OvfA_IrqHandler(void); +void TMR2_1_OvfB_IrqHandler(void); +void TMR2_2_CmpA_IrqHandler(void); +void TMR2_2_CmpB_IrqHandler(void); +void TMR2_2_OvfA_IrqHandler(void); +void TMR2_2_OvfB_IrqHandler(void); +void TMR2_3_CmpA_IrqHandler(void); +void TMR2_3_CmpB_IrqHandler(void); +void TMR2_3_OvfA_IrqHandler(void); +void TMR2_3_OvfB_IrqHandler(void); +void TMR2_4_CmpA_IrqHandler(void); +void TMR2_4_CmpB_IrqHandler(void); +void TMR2_4_OvfA_IrqHandler(void); +void TMR2_4_OvfB_IrqHandler(void); +void RTC_TimeStamp0_IrqHandler(void); +void RTC_TimeStamp1_IrqHandler(void); +void RTC_Alarm_IrqHandler(void); +void RTC_Period_IrqHandler(void); +void CLK_XtalStop_IrqHandler(void); +void SWDT_IrqHandler(void); +void WDT_IrqHandler(void); +void PWC_WakeupTimer_IrqHandler(void); +void TMR6_1_GCmpA_IrqHandler(void); +void TMR6_1_GCmpB_IrqHandler(void); +void TMR6_1_GCmpC_IrqHandler(void); +void TMR6_1_GCmpD_IrqHandler(void); +void TMR6_1_GCmpE_IrqHandler(void); +void TMR6_1_GCmpF_IrqHandler(void); +void TMR6_1_GOvf_IrqHandler(void); +void TMR6_1_GUdf_IrqHandler(void); +void TMR6_1_Gdte_IrqHandler(void); +void TMR6_1_SCmpUpA_IrqHandler(void); +void TMR6_1_SCmpDownA_IrqHandler(void); +void TMR6_1_SCmpUpB_IrqHandler(void); +void TMR6_1_SCmpDownB_IrqHandler(void); +void TMR6_2_GCmpA_IrqHandler(void); +void TMR6_2_GCmpB_IrqHandler(void); +void TMR6_2_GCmpC_IrqHandler(void); +void TMR6_2_GCmpD_IrqHandler(void); +void TMR6_2_GCmpE_IrqHandler(void); +void TMR6_2_GCmpF_IrqHandler(void); +void TMR6_2_GOvf_IrqHandler(void); +void TMR6_2_GUdf_IrqHandler(void); +void TMR6_2_Gdte_IrqHandler(void); +void TMR6_2_SCmpUpA_IrqHandler(void); +void TMR6_2_SCmpDownA_IrqHandler(void); +void TMR6_2_SCmpUpB_IrqHandler(void); +void TMR6_2_SCmpDownB_IrqHandler(void); +void TMR6_3_GCmpA_IrqHandler(void); +void TMR6_3_GCmpB_IrqHandler(void); +void TMR6_3_GCmpC_IrqHandler(void); +void TMR6_3_GCmpD_IrqHandler(void); +void TMR6_3_GCmpE_IrqHandler(void); +void TMR6_3_GCmpF_IrqHandler(void); +void TMR6_3_GOvf_IrqHandler(void); +void TMR6_3_GUdf_IrqHandler(void); +void TMR6_3_Gdte_IrqHandler(void); +void TMR6_3_SCmpUpA_IrqHandler(void); +void TMR6_3_SCmpDownA_IrqHandler(void); +void TMR6_3_SCmpUpB_IrqHandler(void); +void TMR6_3_SCmpDownB_IrqHandler(void); +void TMR6_4_GCmpA_IrqHandler(void); +void TMR6_4_GCmpB_IrqHandler(void); +void TMR6_4_GCmpC_IrqHandler(void); +void TMR6_4_GCmpD_IrqHandler(void); +void TMR6_4_GCmpE_IrqHandler(void); +void TMR6_4_GCmpF_IrqHandler(void); +void TMR6_4_GOvf_IrqHandler(void); +void TMR6_4_GUdf_IrqHandler(void); +void TMR6_4_Gdte_IrqHandler(void); +void TMR6_4_SCmpUpA_IrqHandler(void); +void TMR6_4_SCmpDownA_IrqHandler(void); +void TMR6_4_SCmpUpB_IrqHandler(void); +void TMR6_4_SCmpDownB_IrqHandler(void); +void TMR6_5_GCmpA_IrqHandler(void); +void TMR6_5_GCmpB_IrqHandler(void); +void TMR6_5_GCmpC_IrqHandler(void); +void TMR6_5_GCmpD_IrqHandler(void); +void TMR6_5_GCmpE_IrqHandler(void); +void TMR6_5_GCmpF_IrqHandler(void); +void TMR6_5_GOvf_IrqHandler(void); +void TMR6_5_GUdf_IrqHandler(void); +void TMR6_5_Gdte_IrqHandler(void); +void TMR6_5_SCmpUpA_IrqHandler(void); +void TMR6_5_SCmpDownA_IrqHandler(void); +void TMR6_5_SCmpUpB_IrqHandler(void); +void TMR6_5_SCmpDownB_IrqHandler(void); +void TMR6_6_GCmpA_IrqHandler(void); +void TMR6_6_GCmpB_IrqHandler(void); +void TMR6_6_GCmpC_IrqHandler(void); +void TMR6_6_GCmpD_IrqHandler(void); +void TMR6_6_GCmpE_IrqHandler(void); +void TMR6_6_GCmpF_IrqHandler(void); +void TMR6_6_GOvf_IrqHandler(void); +void TMR6_6_GUdf_IrqHandler(void); +void TMR6_6_Gdte_IrqHandler(void); +void TMR6_6_SCmpUpA_IrqHandler(void); +void TMR6_6_SCmpDownA_IrqHandler(void); +void TMR6_6_SCmpUpB_IrqHandler(void); +void TMR6_6_SCmpDownB_IrqHandler(void); +void TMR6_7_GCmpA_IrqHandler(void); +void TMR6_7_GCmpB_IrqHandler(void); +void TMR6_7_GCmpC_IrqHandler(void); +void TMR6_7_GCmpD_IrqHandler(void); +void TMR6_7_GCmpE_IrqHandler(void); +void TMR6_7_GCmpF_IrqHandler(void); +void TMR6_7_GOvf_IrqHandler(void); +void TMR6_7_GUdf_IrqHandler(void); +void TMR6_7_Gdte_IrqHandler(void); +void TMR6_7_SCmpUpA_IrqHandler(void); +void TMR6_7_SCmpDownA_IrqHandler(void); +void TMR6_7_SCmpUpB_IrqHandler(void); +void TMR6_7_SCmpDownB_IrqHandler(void); +void TMR6_8_GCmpA_IrqHandler(void); +void TMR6_8_GCmpB_IrqHandler(void); +void TMR6_8_GCmpC_IrqHandler(void); +void TMR6_8_GCmpD_IrqHandler(void); +void TMR6_8_GCmpE_IrqHandler(void); +void TMR6_8_GCmpF_IrqHandler(void); +void TMR6_8_GOvf_IrqHandler(void); +void TMR6_8_GUdf_IrqHandler(void); +void TMR6_8_Gdte_IrqHandler(void); +void TMR6_8_SCmpUpA_IrqHandler(void); +void TMR6_8_SCmpDownA_IrqHandler(void); +void TMR6_8_SCmpUpB_IrqHandler(void); +void TMR6_8_SCmpDownB_IrqHandler(void); +void TMR4_1_GCmpUH_IrqHandler(void); +void TMR4_1_GCmpUL_IrqHandler(void); +void TMR4_1_GCmpVH_IrqHandler(void); +void TMR4_1_GCmpVL_IrqHandler(void); +void TMR4_1_GCmpWH_IrqHandler(void); +void TMR4_1_GCmpWL_IrqHandler(void); +void TMR4_1_Ovf_IrqHandler(void); +void TMR4_1_Udf_IrqHandler(void); +void TMR4_1_ReloadU_IrqHandler(void); +void TMR4_1_ReloadV_IrqHandler(void); +void TMR4_1_ReloadW_IrqHandler(void); +void TMR4_2_GCmpUH_IrqHandler(void); +void TMR4_2_GCmpUL_IrqHandler(void); +void TMR4_2_GCmpVH_IrqHandler(void); +void TMR4_2_GCmpVL_IrqHandler(void); +void TMR4_2_GCmpWH_IrqHandler(void); +void TMR4_2_GCmpWL_IrqHandler(void); +void TMR4_2_Ovf_IrqHandler(void); +void TMR4_2_Udf_IrqHandler(void); +void TMR4_2_ReloadU_IrqHandler(void); +void TMR4_2_ReloadV_IrqHandler(void); +void TMR4_2_ReloadW_IrqHandler(void); +void TMR4_3_GCmpUH_IrqHandler(void); +void TMR4_3_GCmpUL_IrqHandler(void); +void TMR4_3_GCmpVH_IrqHandler(void); +void TMR4_3_GCmpVL_IrqHandler(void); +void TMR4_3_GCmpWH_IrqHandler(void); +void TMR4_3_GCmpWL_IrqHandler(void); +void TMR4_3_Ovf_IrqHandler(void); +void TMR4_3_Udf_IrqHandler(void); +void TMR4_3_ReloadU_IrqHandler(void); +void TMR4_3_ReloadV_IrqHandler(void); +void TMR4_3_ReloadW_IrqHandler(void); +void TMRA_1_Ovf_IrqHandler(void); +void TMRA_1_Udf_IrqHandler(void); +void TMRA_1_Cmp1_IrqHandler(void); +void TMRA_1_Cmp2_IrqHandler(void); +void TMRA_1_Cmp3_IrqHandler(void); +void TMRA_1_Cmp4_IrqHandler(void); +void TMRA_2_Ovf_IrqHandler(void); +void TMRA_2_Udf_IrqHandler(void); +void TMRA_2_Cmp1_IrqHandler(void); +void TMRA_2_Cmp2_IrqHandler(void); +void TMRA_2_Cmp3_IrqHandler(void); +void TMRA_2_Cmp4_IrqHandler(void); +void TMRA_3_Ovf_IrqHandler(void); +void TMRA_3_Udf_IrqHandler(void); +void TMRA_3_Cmp1_IrqHandler(void); +void TMRA_3_Cmp2_IrqHandler(void); +void TMRA_3_Cmp3_IrqHandler(void); +void TMRA_3_Cmp4_IrqHandler(void); +void TMRA_4_Ovf_IrqHandler(void); +void TMRA_4_Udf_IrqHandler(void); +void TMRA_4_Cmp1_IrqHandler(void); +void TMRA_4_Cmp2_IrqHandler(void); +void TMRA_4_Cmp3_IrqHandler(void); +void TMRA_4_Cmp4_IrqHandler(void); +void TMRA_5_Ovf_IrqHandler(void); +void TMRA_5_Udf_IrqHandler(void); +void TMRA_5_Cmp1_IrqHandler(void); +void TMRA_5_Cmp2_IrqHandler(void); +void TMRA_5_Cmp3_IrqHandler(void); +void TMRA_5_Cmp4_IrqHandler(void); +void TMRA_6_Ovf_IrqHandler(void); +void TMRA_6_Udf_IrqHandler(void); +void TMRA_6_Cmp1_IrqHandler(void); +void TMRA_6_Cmp2_IrqHandler(void); +void TMRA_6_Cmp3_IrqHandler(void); +void TMRA_6_Cmp4_IrqHandler(void); +void TMRA_7_Ovf_IrqHandler(void); +void TMRA_7_Udf_IrqHandler(void); +void TMRA_7_Cmp1_IrqHandler(void); +void TMRA_7_Cmp2_IrqHandler(void); +void TMRA_7_Cmp3_IrqHandler(void); +void TMRA_7_Cmp4_IrqHandler(void); +void TMRA_8_Ovf_IrqHandler(void); +void TMRA_8_Udf_IrqHandler(void); +void TMRA_8_Cmp1_IrqHandler(void); +void TMRA_8_Cmp2_IrqHandler(void); +void TMRA_8_Cmp3_IrqHandler(void); +void TMRA_8_Cmp4_IrqHandler(void); +void TMRA_9_Ovf_IrqHandler(void); +void TMRA_9_Udf_IrqHandler(void); +void TMRA_9_Cmp1_IrqHandler(void); +void TMRA_9_Cmp2_IrqHandler(void); +void TMRA_9_Cmp3_IrqHandler(void); +void TMRA_9_Cmp4_IrqHandler(void); +void TMRA_10_Ovf_IrqHandler(void); +void TMRA_10_Udf_IrqHandler(void); +void TMRA_10_Cmp1_IrqHandler(void); +void TMRA_10_Cmp2_IrqHandler(void); +void TMRA_10_Cmp3_IrqHandler(void); +void TMRA_10_Cmp4_IrqHandler(void); +void TMRA_11_Ovf_IrqHandler(void); +void TMRA_11_Udf_IrqHandler(void); +void TMRA_11_Cmp1_IrqHandler(void); +void TMRA_11_Cmp2_IrqHandler(void); +void TMRA_11_Cmp3_IrqHandler(void); +void TMRA_11_Cmp4_IrqHandler(void); +void TMRA_12_Ovf_IrqHandler(void); +void TMRA_12_Udf_IrqHandler(void); +void TMRA_12_Cmp1_IrqHandler(void); +void TMRA_12_Cmp2_IrqHandler(void); +void TMRA_12_Cmp3_IrqHandler(void); +void TMRA_12_Cmp4_IrqHandler(void); +void EMB_GR0_IrqHandler(void); +void EMB_GR1_IrqHandler(void); +void EMB_GR2_IrqHandler(void); +void EMB_GR3_IrqHandler(void); +void EMB_GR4_IrqHandler(void); +void EMB_GR5_IrqHandler(void); +void EMB_GR6_IrqHandler(void); +void USART_1_RxErr_IrqHandler(void); +void USART_1_RxEnd_IrqHandler(void); +void USART_1_TxEmpty_IrqHandler(void); +void USART_1_TxEnd_IrqHandler(void); +void USART_1_RxTO_IrqHandler(void); +void USART_2_RxErr_IrqHandler(void); +void USART_2_RxEnd_IrqHandler(void); +void USART_2_TxEmpty_IrqHandler(void); +void USART_2_TxEnd_IrqHandler(void); +void USART_2_RxTO_IrqHandler(void); +void USART_3_RxErr_IrqHandler(void); +void USART_3_RxEnd_IrqHandler(void); +void USART_3_TxEmpty_IrqHandler(void); +void USART_3_TxEnd_IrqHandler(void); +void USART_4_RxErr_IrqHandler(void); +void USART_4_RxEnd_IrqHandler(void); +void USART_4_TxEmpty_IrqHandler(void); +void USART_4_TxEnd_IrqHandler(void); +void USART_5_LinBreakField_IrqHandler(void); +void USART_5_LinWakeup_IrqHandler(void); +void USART_5_RxErr_IrqHandler(void); +void USART_5_RxEnd_IrqHandler(void); +void USART_5_TxEmpty_IrqHandler(void); +void USART_5_TxEnd_IrqHandler(void); +void USART_6_RxErr_IrqHandler(void); +void USART_6_RxEnd_IrqHandler(void); +void USART_6_TxEmpty_IrqHandler(void); +void USART_6_TxEnd_IrqHandler(void); +void USART_6_RxTO_IrqHandler(void); +void USART_7_RxErr_IrqHandler(void); +void USART_7_RxEnd_IrqHandler(void); +void USART_7_TxEmpty_IrqHandler(void); +void USART_7_TxEnd_IrqHandler(void); +void USART_7_RxTO_IrqHandler(void); +void USART_8_RxErr_IrqHandler(void); +void USART_8_RxEnd_IrqHandler(void); +void USART_8_TxEmpty_IrqHandler(void); +void USART_8_TxEnd_IrqHandler(void); +void USART_9_RxErr_IrqHandler(void); +void USART_9_RxEnd_IrqHandler(void); +void USART_9_TxEmpty_IrqHandler(void); +void USART_9_TxEnd_IrqHandler(void); +void USART_10_LinBreakField_IrqHandler(void); +void USART_10_LinWakeup_IrqHandler(void); +void USART_10_RxErr_IrqHandler(void); +void USART_10_RxEnd_IrqHandler(void); +void USART_10_TxEmpty_IrqHandler(void); +void USART_10_TxEnd_IrqHandler(void); +void SPI_1_RxEnd_IrqHandler(void); +void SPI_1_TxEmpty_IrqHandler(void); +void SPI_1_Err_IrqHandler(void); +void SPI_1_Idle_IrqHandler(void); +void SPI_2_RxEnd_IrqHandler(void); +void SPI_2_TxEmpty_IrqHandler(void); +void SPI_2_Err_IrqHandler(void); +void SPI_2_Idle_IrqHandler(void); +void SPI_3_RxEnd_IrqHandler(void); +void SPI_3_TxEmpty_IrqHandler(void); +void SPI_3_Err_IrqHandler(void); +void SPI_3_Idle_IrqHandler(void); +void SPI_4_RxEnd_IrqHandler(void); +void SPI_4_TxEmpty_IrqHandler(void); +void SPI_4_Err_IrqHandler(void); +void SPI_4_Idle_IrqHandler(void); +void SPI_5_RxEnd_IrqHandler(void); +void SPI_5_TxEmpty_IrqHandler(void); +void SPI_5_Err_IrqHandler(void); +void SPI_5_Idle_IrqHandler(void); +void SPI_6_RxEnd_IrqHandler(void); +void SPI_6_TxEmpty_IrqHandler(void); +void SPI_6_Err_IrqHandler(void); +void SPI_6_Idle_IrqHandler(void); +void CAN_1_IrqHandler(void); +void CAN_2_IrqHandler(void); +void I2S_1_Tx_IrqHandler(void); +void I2S_1_Rx_IrqHandler(void); +void I2S_1_Err_IrqHandler(void); +void I2S_2_Tx_IrqHandler(void); +void I2S_2_Rx_IrqHandler(void); +void I2S_2_Err_IrqHandler(void); +void I2S_3_Tx_IrqHandler(void); +void I2S_3_Rx_IrqHandler(void); +void I2S_3_Err_IrqHandler(void); +void I2S_4_Tx_IrqHandler(void); +void I2S_4_Rx_IrqHandler(void); +void I2S_4_Err_IrqHandler(void); +void USBFS_Global_IrqHandler(void); +void SDIOC_1_Normal_IrqHandler(void); +void SDIOC_1_Error_IrqHandler(void); +void SDIOC_2_Normal_IrqHandler(void); +void SDIOC_2_Error_IrqHandler(void); +void ETH_Global_IrqHandler(void); +void ETH_Wakeup_IrqHandler(void); +void I2C_1_RxEnd_IrqHandler(void); +void I2C_1_TxEnd_IrqHandler(void); +void I2C_1_TxEmpty_IrqHandler(void); +void I2C_1_Err_IrqHandler(void); +void I2C_2_RxEnd_IrqHandler(void); +void I2C_2_TxEnd_IrqHandler(void); +void I2C_2_TxEmpty_IrqHandler(void); +void I2C_2_Err_IrqHandler(void); +void I2C_3_RxEnd_IrqHandler(void); +void I2C_3_TxEnd_IrqHandler(void); +void I2C_3_TxEmpty_IrqHandler(void); +void I2C_3_Err_IrqHandler(void); +void I2C_4_RxEnd_IrqHandler(void); +void I2C_4_TxEnd_IrqHandler(void); +void I2C_4_TxEmpty_IrqHandler(void); +void I2C_4_Err_IrqHandler(void); +void I2C_5_RxEnd_IrqHandler(void); +void I2C_5_TxEnd_IrqHandler(void); +void I2C_5_TxEmpty_IrqHandler(void); +void I2C_5_Err_IrqHandler(void); +void I2C_6_RxEnd_IrqHandler(void); +void I2C_6_TxEnd_IrqHandler(void); +void I2C_6_TxEmpty_IrqHandler(void); +void I2C_6_Err_IrqHandler(void); +void PWC_Pvd1_IrqHandler(void); +void PWC_Pvd2_IrqHandler(void); +void FCM_Err_IrqHandler(void); +void FCM_End_IrqHandler(void); +void FCM_Ovf_IrqHandler(void); +void CTC_Udf_IrqHandler(void); +void CTC_Ovf_IrqHandler(void); +void ADC_1_SeqA_IrqHandler(void); +void ADC_1_SeqB_IrqHandler(void); +void ADC_1_Cmp0_IrqHandler(void); +void ADC_1_Cmp1Ind_IrqHandler(void); +void ADC_1_Cmp1Comb_IrqHandler(void); +void ADC_2_SeqA_IrqHandler(void); +void ADC_2_SeqB_IrqHandler(void); +void ADC_2_Cmp0_IrqHandler(void); +void ADC_2_Cmp1Ind_IrqHandler(void); +void ADC_2_Cmp1Comb_IrqHandler(void); +void ADC_3_SeqA_IrqHandler(void); +void ADC_3_SeqB_IrqHandler(void); +void ADC_3_Cmp0_IrqHandler(void); +void ADC_3_Cmp1Ind_IrqHandler(void); +void ADC_3_Cmp1Comb_IrqHandler(void); +void NFC_IrqHandler(void); + +/** + * @} + */ + +#endif /* DDL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_INTERRUPTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_keyscan.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_keyscan.h new file mode 100644 index 0000000000000000000000000000000000000000..b545ff2f0dde2052b192dd48363f551107ed326c --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_keyscan.h @@ -0,0 +1,239 @@ +/** + ******************************************************************************* + * @file hc32f4a0_keyscan.h + * @brief This file contains all the functions prototypes of the KEYSCAN driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_KEYSCAN_H__ +#define __HC32F4A0_KEYSCAN_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_KEYSCAN + * @{ + */ + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Types KEYSCAN Global Types + * @{ + */ + +/** + * @brief KEYSCAN configuration + */ +typedef struct +{ + uint32_t u32HizCycle; /*!< Specifies the KEYSCAN Hiz cycles. + This parameter can be a value of @ref KEYSCAN_Hiz_Cycle_Sel */ + + uint32_t u32LowCycle; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Low_Cycle_Sel */ + + uint32_t u32KeyClk; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Clock_Sel */ + + uint32_t u32KeyOut; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyout_Sel */ + + uint32_t u32KeyIn; /*!< Specifies the KEYSCAN low cycles. + This parameter can be a value of @ref KEYSCAN_Keyin_Sel */ +} stc_keyscan_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Macros KEYSCAN Global Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Hiz_Cycle_Sel KEYSCAN Hiz cycles during low ouput selection + * @{ + */ +#define KEYSCAN_HIZ_CLC_4 (0x00UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 4 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_8 (0x01UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 8 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_16 (0x02UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 16 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_32 (0x03UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 32 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_64 (0x04UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 64 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_256 (0x05UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 256 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_512 (0x06UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 512 cycles during low ouput */ +#define KEYSCAN_HIZ_CLC_1024 (0x07UL << KEYSCAN_SCR_T_HIZ_POS) /*!< KEYSCAN HiZ keep 1024 cycles during low ouput */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Low_Cycle_Sel KEYSCAN low level output cycles selection + * @{ + */ +#define KEYSCAN_LOW_CLC_4 (0x02UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^2=4 cycles */ +#define KEYSCAN_LOW_CLC_8 (0x03UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^3=8 cycles */ +#define KEYSCAN_LOW_CLC_16 (0x04UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^4=16 cycles */ +#define KEYSCAN_LOW_CLC_32 (0x05UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^5=32 cycles */ +#define KEYSCAN_LOW_CLC_64 (0x06UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^6=64 cycles */ +#define KEYSCAN_LOW_CLC_128 (0x07UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^7=128 cycles */ +#define KEYSCAN_LOW_CLC_256 (0x08UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^8=256 cycles */ +#define KEYSCAN_LOW_CLC_512 (0x09UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^9=512 cycles */ +#define KEYSCAN_LOW_CLC_1K (0x0AUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^10=1K cycles */ +#define KEYSCAN_LOW_CLC_2K (0x0BUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^11=2K cycles */ +#define KEYSCAN_LOW_CLC_4K (0x0CUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^12=4K cycles */ +#define KEYSCAN_LOW_CLC_8K (0x0DUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^13=8K cycles */ +#define KEYSCAN_LOW_CLC_16K (0x0EUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^14=16K cycles */ +#define KEYSCAN_LOW_CLC_32K (0x0FUL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^15=32K cycles */ +#define KEYSCAN_LOW_CLC_64K (0x10UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^16=64K cycles */ +#define KEYSCAN_LOW_CLC_128K (0x11UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^17=128K cycles */ +#define KEYSCAN_LOW_CLC_256K (0x12UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^18=256K cycles */ +#define KEYSCAN_LOW_CLC_512K (0x13UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^19=512K cycles */ +#define KEYSCAN_LOW_CLC_1M (0x14UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^20=1M cycles */ +#define KEYSCAN_LOW_CLC_2M (0x15UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^21=2M cycles */ +#define KEYSCAN_LOW_CLC_4M (0x16UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^22=4M cycles */ +#define KEYSCAN_LOW_CLC_8M (0x17UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^23=8M cycles */ +#define KEYSCAN_LOW_CLC_16M (0x18UL << KEYSCAN_SCR_T_LLEVEL_POS) /*!< KEYSCAN low level output is 2^24=16M cycles */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Clock_Sel KEYSCAN scan clock selection + * @{ + */ +#define KEYSCAN_CLK_HCLK (0x00UL) /*!< Use as HCLK KEYSCAN clock */ +#define KEYSCAN_CLK_LRC (KEYSCAN_SCR_CKSEL_0) /*!< Use as LRC KEYSCAN clock */ +#define KEYSCAN_CLK_XTAL32 (KEYSCAN_SCR_CKSEL_1) /*!< Use as XTAL32 KEYSCAN clock */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyout_Sel KEYSCAN keyout pins selection + * @{ + */ +#define KEYSCAN_OUT_0T1 (0x01UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 1 are selected */ +#define KEYSCAN_OUT_0T2 (0x02UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 2 are selected */ +#define KEYSCAN_OUT_0T3 (0x03UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 3 are selected */ +#define KEYSCAN_OUT_0T4 (0x04UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 4 are selected */ +#define KEYSCAN_OUT_0T5 (0x05UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 5 are selected */ +#define KEYSCAN_OUT_0T6 (0x06UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 6 are selected */ +#define KEYSCAN_OUT_0T7 (0x07UL << KEYSCAN_SCR_KEYOUTSEL_POS) /*!< KEYOUT 0 ~ 7 are selected */ +/** + * @} + */ + +/** + * @defgroup KEYSCAN_Keyin_Sel KEYSCAN keyin pins selection + * @{ + */ +#define KEYSCAN_IN_0 (KEYSCAN_SCR_KEYINSEL_0) /*!< KEYIN(EIRQ) 0 is selected */ +#define KEYSCAN_IN_1 (KEYSCAN_SCR_KEYINSEL_1) /*!< KEYIN(EIRQ) 1 is selected */ +#define KEYSCAN_IN_2 (KEYSCAN_SCR_KEYINSEL_2) /*!< KEYIN(EIRQ) 2 is selected */ +#define KEYSCAN_IN_3 (KEYSCAN_SCR_KEYINSEL_3) /*!< KEYIN(EIRQ) 3 is selected */ +#define KEYSCAN_IN_4 (KEYSCAN_SCR_KEYINSEL_4) /*!< KEYIN(EIRQ) 4 is selected */ +#define KEYSCAN_IN_5 (KEYSCAN_SCR_KEYINSEL_5) /*!< KEYIN(EIRQ) 5 is selected */ +#define KEYSCAN_IN_6 (KEYSCAN_SCR_KEYINSEL_6) /*!< KEYIN(EIRQ) 6 is selected */ +#define KEYSCAN_IN_7 (KEYSCAN_SCR_KEYINSEL_7) /*!< KEYIN(EIRQ) 7 is selected */ +#define KEYSCAN_IN_8 (KEYSCAN_SCR_KEYINSEL_8) /*!< KEYIN(EIRQ) 8 is selected */ +#define KEYSCAN_IN_9 (KEYSCAN_SCR_KEYINSEL_9) /*!< KEYIN(EIRQ) 9 is selected */ +#define KEYSCAN_IN_10 (KEYSCAN_SCR_KEYINSEL_10) /*!< KEYIN(EIRQ) 10 is selected */ +#define KEYSCAN_IN_11 (KEYSCAN_SCR_KEYINSEL_11) /*!< KEYIN(EIRQ) 11 is selected */ +#define KEYSCAN_IN_12 (KEYSCAN_SCR_KEYINSEL_12) /*!< KEYIN(EIRQ) 12 is selected */ +#define KEYSCAN_IN_13 (KEYSCAN_SCR_KEYINSEL_13) /*!< KEYIN(EIRQ) 13 is selected */ +#define KEYSCAN_IN_14 (KEYSCAN_SCR_KEYINSEL_14) /*!< KEYIN(EIRQ) 14 is selected */ +#define KEYSCAN_IN_15 (KEYSCAN_SCR_KEYINSEL_15) /*!< KEYIN(EIRQ) 15 is selected */ +#define KEYSCAN_IN_MASK (KEYSCAN_SCR_KEYINSEL) /*!< KEYIN(EIRQ) mask */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup KEYSCAN_Global_Functions + * @{ + */ +/** + * @brief Get KEYOUT index. + * @param None. + * @retval uint32_t: KEYOUT index 0~7. + */ +__STATIC_INLINE uint32_t KEYSCAN_GetKeyoutIdx(void) +{ + return READ_REG32_BIT(M4_KEYSCAN->SSR, KEYSCAN_SSR_INDEX); +} + +en_result_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit); +en_result_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit); +void KEYSCAN_Cmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* DDL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_KEYSCAN_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_mau.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_mau.h new file mode 100644 index 0000000000000000000000000000000000000000..d2e5652f28afd1a1068fd23ade2d5b18a96f0266 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_mau.h @@ -0,0 +1,122 @@ +/** + ******************************************************************************* + * @file hc32f4a0_mau.h + * @brief This file contains all the functions prototypes of the MAU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hexiao First version + 2020-07-15 Hexiao Modify MAU_SqrtStartCmd to MAU_SqrtStart + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_MAU_H__ +#define __HC32F4A0_MAU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_MAU + * @{ + */ + +#if (DDL_MAU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup MAU_Global_Macros MAU Global Macros + * @{ + */ + +#define MAU_SQRT_TIMEOUT (HCLK_VALUE / 10000UL)/* About 1mS timeout */ +#define MAU_SQRT_OUTPUT_LSHIFT_MAX (16U) +#define MAU_SIN_Q15_SCALAR (0x8000UL) +#define MAU_SIN_ANGIDX_TOTAL (0x1000UL) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ + +/** + * @addtogroup MAU_Global_Functions + * @{ + */ + +void MAU_SqrtInit(M4_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber, en_functional_state_t enIntNewState); +void MAU_SqrtDeInit(M4_MAU_TypeDef *MAUx); + +void MAU_SqrtResultLShiftCfg(M4_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber); +void MAU_SqrtIntCmd(M4_MAU_TypeDef *MAUx, en_functional_state_t enNewState); +void MAU_SqrtWriteDataReg(M4_MAU_TypeDef *MAUx, uint32_t u32Radicand); +en_flag_status_t MAU_SqrtGetStatus(const M4_MAU_TypeDef *MAUx); +uint32_t MAU_SqrtReadDataReg(const M4_MAU_TypeDef *MAUx); +void MAU_SqrtStart(M4_MAU_TypeDef* MAUx); + +en_result_t MAU_Sqrt(M4_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result); + +int16_t MAU_Sin(M4_MAU_TypeDef *MAUx, uint16_t u16AngleIdx); + +/** + * @} + */ + +#endif /* DDL_MAU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_MAU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_mpu.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_mpu.h new file mode 100644 index 0000000000000000000000000000000000000000..89be765842d0611dfb0a2816157312c4704e5e90 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_mpu.h @@ -0,0 +1,380 @@ +/** + ******************************************************************************* + * @file hc32f4a0_mpu.h + * @brief This file contains all the functions prototypes of the MPU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_MPU_H__ +#define __HC32F4A0_MPU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_MPU + * @{ + */ + +#if (DDL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Types MPU Global Types + * @{ + */ + +/** + * @brief MPU Unit configure structure definition + */ +typedef struct +{ + uint32_t u32ExceptionType; /*!< Specifies the type of exception that occurs when the unit accesses a protected region. + This parameter can be a value of @ref MPU_Exception_Type */ + uint32_t u32BackgroundWriteProtect; /*!< Specifies the unit's write protection for the background space. + This parameter can be a value of @ref MPU_Background_Write_Protect */ + uint32_t u32BackgroundReadProtect; /*!< Specifies the unit's read protection for the background space + This parameter can be a value of @ref MPU_Background_Read_Protect */ +} stc_mpu_unit_config_t; + +/** + * @brief MPU Init structure definition + */ +typedef struct +{ + stc_mpu_unit_config_t stcDma1; /*!< Configure storage protection unit of DMA1 */ + stc_mpu_unit_config_t stcDma2; /*!< Configure storage protection unit of DMA2 */ + stc_mpu_unit_config_t stcUsbFSDma; /*!< Configure storage protection unit of USBFS_DMA */ + stc_mpu_unit_config_t stcUsbHSDma; /*!< Configure storage protection unit of USBHS_DMA */ + stc_mpu_unit_config_t stcEthDma; /*!< Configure storage protection unit of ETH_DMA */ +} stc_mpu_init_t; + +/** + * @brief MPU Region Permission structure definition + */ +typedef struct +{ + uint32_t u32WriteProtect; /*!< Specifies the unit's write protection for the region. + This parameter can be a value of @ref MPU_Region_Write_Protect */ + uint32_t u32ReadProtect; /*!< Specifies the unit's read protection for the region. + This parameter can be a value of @ref MPU_Region_Read_Protect */ +} stc_mpu_region_permission_t; + +/** + * @brief MPU region initialization structure definition + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + */ +typedef struct +{ + uint32_t u32BaseAddr; /*!< Specifies the base address of the region. + This parameter can be a number between 0UL and 0xFFFFFFE0UL */ + uint32_t u32Size; /*!< Specifies the size of the region. + This parameter can be a value of @ref MPU_Region_Size */ + stc_mpu_region_permission_t stcDma1; /*!< Specifies the DMA1 access permission for the region */ + stc_mpu_region_permission_t stcDma2; /*!< Specifies the DMA2 access permission for the region */ + stc_mpu_region_permission_t stcUsbFSDma; /*!< Specifies the USBFS_DMA access permission for the region */ + stc_mpu_region_permission_t stcUsbHSDma; /*!< Specifies the USBHS_DMA access permission for the region */ + stc_mpu_region_permission_t stcEthDma; /*!< Specifies the ETH_DMA access permission for the region */ +} stc_mpu_region_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Macros MPU Global Macros + * @{ + */ + +/** + * @defgroup MPU_Unit_Type MPU Unit Type + * @{ + */ +#define MPU_UNIT_DMA1 (0x01UL) /*!< System DMA_1 MPU */ +#define MPU_UNIT_DMA2 (0x02UL) /*!< System DMA_2 MPU */ +#define MPU_UNIT_USBFS_DMA (0x04UL) /*!< USBFS_DMA MPU */ +#define MPU_UNIT_USBHS_DMA (0x08UL) /*!< USBHS_DMA MPU */ +#define MPU_UNIT_ETH_DMA (0x10UL) /*!< ETH_DMA MPU */ +#define MPU_UNIT_ALL (0x1FUL) +/** + * @} + */ + +/** + * @defgroup MPU_Region_Number MPU Region Number + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @{ + */ +#define MPU_REGION_NUM0 (0x00UL) /*!< MPU region number 0 */ +#define MPU_REGION_NUM1 (0x01UL) /*!< MPU region number 1 */ +#define MPU_REGION_NUM2 (0x02UL) /*!< MPU region number 2 */ +#define MPU_REGION_NUM3 (0x03UL) /*!< MPU region number 3 */ +#define MPU_REGION_NUM4 (0x04UL) /*!< MPU region number 4 */ +#define MPU_REGION_NUM5 (0x05UL) /*!< MPU region number 5 */ +#define MPU_REGION_NUM6 (0x06UL) /*!< MPU region number 6 */ +#define MPU_REGION_NUM7 (0x07UL) /*!< MPU region number 7 */ +#define MPU_REGION_NUM8 (0x08UL) /*!< MPU region number 8 */ +#define MPU_REGION_NUM9 (0x09UL) /*!< MPU region number 9 */ +#define MPU_REGION_NUM10 (0x0AUL) /*!< MPU region number 10 */ +#define MPU_REGION_NUM11 (0x0BUL) /*!< MPU region number 11 */ +#define MPU_REGION_NUM12 (0x0CUL) /*!< MPU region number 12 */ +#define MPU_REGION_NUM13 (0x0DUL) /*!< MPU region number 13 */ +#define MPU_REGION_NUM14 (0x0EUL) /*!< MPU region number 14 */ +#define MPU_REGION_NUM15 (0x0FUL) /*!< MPU region number 15 */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Write_Protect MPU Background Write Protect + * @{ + */ +#define MPU_BKGRD_WR_PROTECT_DISABLE (0UL) /*!< Disable write protection of background space */ +#define MPU_BKGRD_WR_PROTECT_ENABLE (MPU_S1CR_SMPU1BWP) /*!< Enable write protection of background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Background_Read_Protect MPU Background Read Protect + * @{ + */ +#define MPU_BKGRD_RD_PROTECT_DISABLE (0UL) /*!< Disable read protection of background space */ +#define MPU_BKGRD_RD_PROTECT_ENABLE (MPU_S1CR_SMPU1BRP) /*!< Enable read protection of background space */ +/** + * @} + */ + +/** + * @defgroup MPU_Exception_Type MPU Exception Type + * @{ + */ +#define MPU_EXP_TYPE_NONE (0UL) /*!< The host unit access protection regions will be ignored */ +#define MPU_EXP_TYPE_BUS_ERR (MPU_S1CR_SMPU1ACT_0) /*!< The host unit access protection regions will be ignored and a bus error will be triggered */ +#define MPU_EXP_TYPE_NMI (MPU_S1CR_SMPU1ACT_1) /*!< The host unit access protection regions will be ignored and a NMI interrupt will be triggered */ +#define MPU_EXP_TYPE_RST (MPU_S1CR_SMPU1ACT) /*!< The host unit access protection regions will trigger the reset */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Write_Protect MPU Region Write Protect + * @{ + */ +#define MPU_REGION_WR_PROTECT_DISABLE (0UL) /*!< Disable write protection of the region */ +#define MPU_REGION_WR_PROTECT_ENABLE (MPU_S1RGWP_S1RG0WP) /*!< Enable write protection of the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Read_Protect MPU Region Read Protect + * @{ + */ +#define MPU_REGION_RD_PROTECT_DISABLE (0UL) /*!< Disable read protection of the region */ +#define MPU_REGION_RD_PROTECT_ENABLE (MPU_S1RGRP_S1RG0RP) /*!< Enable read protection of the region */ +/** + * @} + */ + +/** + * @defgroup MPU_Region_Size MPU Region Size + * @{ + */ +#define MPU_REGION_SIZE_32BYTE (0x04UL) /*!< 32 Byte */ +#define MPU_REGION_SIZE_64BYTE (0x05UL) /*!< 64 Byte */ +#define MPU_REGION_SIZE_128BYTE (0x06UL) /*!< 126 Byte */ +#define MPU_REGION_SIZE_256BYTE (0x07UL) /*!< 256 Byte */ +#define MPU_REGION_SIZE_512BYTE (0x08UL) /*!< 512 Byte */ +#define MPU_REGION_SIZE_1KBYTE (0x09UL) /*!< 1K Byte */ +#define MPU_REGION_SIZE_2KBYTE (0x0AUL) /*!< 2K Byte */ +#define MPU_REGION_SIZE_4KBYTE (0x0BUL) /*!< 4K Byte */ +#define MPU_REGION_SIZE_8KBYTE (0x0CUL) /*!< 8K Byte */ +#define MPU_REGION_SIZE_16KBYTE (0x0DUL) /*!< 16K Byte */ +#define MPU_REGION_SIZE_32KBYTE (0x0EUL) /*!< 32K Byte */ +#define MPU_REGION_SIZE_64KBYTE (0x0FUL) /*!< 64K Byte */ +#define MPU_REGION_SIZE_128KBYTE (0x10UL) /*!< 128K Byte */ +#define MPU_REGION_SIZE_256KBYTE (0x11UL) /*!< 256K Byte */ +#define MPU_REGION_SIZE_512KBYTE (0x12UL) /*!< 512K Byte */ +#define MPU_REGION_SIZE_1MBYTE (0x13UL) /*!< 1M Byte */ +#define MPU_REGION_SIZE_2MBYTE (0x14UL) /*!< 2M Byte */ +#define MPU_REGION_SIZE_4MBYTE (0x15UL) /*!< 4M Byte */ +#define MPU_REGION_SIZE_8MBYTE (0x16UL) /*!< 8M Byte */ +#define MPU_REGION_SIZE_16MBYTE (0x17UL) /*!< 16M Byte */ +#define MPU_REGION_SIZE_32MBYTE (0x18UL) /*!< 32M Byte */ +#define MPU_REGION_SIZE_64MBYTE (0x19UL) /*!< 64M Byte */ +#define MPU_REGION_SIZE_128MBYTE (0x1AUL) /*!< 128M Byte */ +#define MPU_REGION_SIZE_256MBYTE (0x1BUL) /*!< 256M Byte */ +#define MPU_REGION_SIZE_512MBYTE (0x1CUL) /*!< 512M Byte */ +#define MPU_REGION_SIZE_1GBYTE (0x1DUL) /*!< 1G Byte */ +#define MPU_REGION_SIZE_2GBYTE (0x1EUL) /*!< 2G Byte */ +#define MPU_REGION_SIZE_4GBYTE (0x1FUL) /*!< 4G Byte */ +/** + * @} + */ + +/** + * @defgroup MPU_Flag MPU Flag + * @{ + */ +#define MPU_FLAG_SMPU1EAF (MPU_SR_SMPU1EAF) /*!< System DMA_1 error flag */ +#define MPU_FLAG_SMPU2EAF (MPU_SR_SMPU2EAF) /*!< System DMA_2 error flag */ +#define MPU_FLAG_FMPUEAF (MPU_SR_FMPUEAF) /*!< USBFS_DMA error flag */ +#define MPU_FLAG_HMPUEAF (MPU_SR_HMPUEAF) /*!< USBHS_DMA error flag */ +#define MPU_FLAG_EMPUEAF (MPU_SR_EMPUEAF) /*!< ETH_DMA error flag */ +#define MPU_FLAG_ALL (0x0000001FUL) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Type MPU IP Type + * @note IP access protection is not available in privileged mode. + * @{ + */ +#define MPU_IP_AES (MPU_IPPR_AESRDP) /*!< AES module */ +#define MPU_IP_HASH (MPU_IPPR_HASHRDP) /*!< HASH module */ +#define MPU_IP_TRNG (MPU_IPPR_TRNGRDP) /*!< TRNG module */ +#define MPU_IP_CRC (MPU_IPPR_CRCRDP) /*!< CRC module */ +#define MPU_IP_FMC (MPU_IPPR_FMCRDP) /*!< FMC module */ +#define MPU_IP_WDT (MPU_IPPR_WDTRDP) /*!< WDT module */ +#define MPU_IP_SWDT (MPU_IPPR_SWDTRDP) /*!< SWDT module */ +#define MPU_IP_BKSRAM (MPU_IPPR_BKSRAMRDP) /*!< BKSRAM module */ +#define MPU_IP_RTC (MPU_IPPR_RTCRDP) /*!< RTC module */ +#define MPU_IP_DMPU (MPU_IPPR_DMPURDP) /*!< DMPU module */ +#define MPU_IP_SRAMC (MPU_IPPR_SRAMCRDP) /*!< SRAMC module */ +#define MPU_IP_INTC (MPU_IPPR_INTCRDP) /*!< INTC module */ +#define MPU_IP_SYSC (MPU_IPPR_SYSCRDP) /*!< SYSC module */ +#define MPU_IP_MSTP (MPU_IPPR_MSTPRDP) /*!< MSTP module */ +#define MPU_IP_ALL (0x15555155UL) +/** + * @} + */ + +/** + * @defgroup MPU_IP_Exception_Type MPU IP Exception Type + * @{ + */ +#define MPU_IP_EXP_TYPE_NONE (0UL) /*!< Access to the protected IP will be ignored */ +#define MPU_IP_EXP_TYPE_BUS_ERR (MPU_IPPR_BUSERRE) /*!< Access to the protected IP will trigger a bus error */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup MPU_Global_Functions + * @{ + */ + +/** + * @brief MPU write protect unlock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_Unlock(void) +{ + WRITE_REG32(M4_MPU->WP, 0x96A5UL); +} + +/** + * @brief MPU write protect lock. + * @param None + * @retval None + */ +__STATIC_INLINE void MPU_Lock(void) +{ + WRITE_REG32(M4_MPU->WP, 0x96A4UL); +} + +void MPU_Unlock(void); +void MPU_Lock(void); + +void MPU_DeInit(void); +en_result_t MPU_Init(const stc_mpu_init_t *pstcMpuInit); +en_result_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit); +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32ExceptionType); +void MPU_BackgroundWriteProtectCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_BackgroundReadProtectCmd(uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState); +en_flag_status_t MPU_GetStatus(uint32_t u32Flag); +void MPU_ClearStatus(uint32_t u32Flag); + +en_result_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit); +en_result_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit); +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr); +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size); +void MPU_RegionWriteProtectCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionReadProtectCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState); + +void MPU_IP_SetExceptionType(uint32_t u32ExceptionType); +void MPU_IP_WriteProtectCmd(uint32_t u32Peripheral, en_functional_state_t enNewState); +void MPU_IP_ReadProtectCmd(uint32_t u32Peripheral, en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* DDL_MPU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_MPU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_nfc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_nfc.h new file mode 100644 index 0000000000000000000000000000000000000000..6fbd2cd37525b716f05623bff4704e56bdf60228 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_nfc.h @@ -0,0 +1,635 @@ +/** + ******************************************************************************* + * @file hc32f4a0_nfc.h + * @brief This file contains all the functions prototypes of the EXMC NFC + * (External Memory Controller: NAND Flash Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-14 Hongjh 1. Merge API from EXMC_NFC_Enable/Disable to EXMC_NFC_Cmd + 2. Merge API from EXMC_NFC_Enable/DisableEcc + to EXMC_NFC_EccCmd + 3. Merge API from EXMC_NFC_Enable/DisableWriteProtect + to EXMC_NFC_WriteProtectCmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_NFC_H__ +#define __HC32F4A0_NFC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_EXMC_NFC + * @{ + */ + +#if (DDL_NFC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Global_Types NAND Flash Controller Global Types + * @{ + */ + +/** + * @brief EXMC SMC Chip Configuration Structure definition + */ +typedef struct +{ + uint32_t u32CapacitySize; /*!< Defines the capacity size. + This parameter can be a value of @ref EXMC_NFC_BANK_Memory_Capacity. */ + + uint32_t u32MemWidth; /*!< Defines the memory width. + This parameter can be a value of @ref EXMC_NFC_Memory_Width. */ + + uint32_t u32BankNum; /*!< Defines the bank number. + This parameter can be a value of @ref EXMC_NFC_Bank_Number */ + + uint32_t u32PageSize; /*!< Defines the page size. + This parameter can be a value of @ref EXMC_NFC_Page_Size. */ + + uint32_t u32WrProtect; /*!< Defines the write protect. + This parameter can be a value of @ref EXMC_NFC_Write_Protect. */ + + uint32_t u32EccMode; /*!< Defines the ECC mode. + This parameter can be a value of @ref EXMC_NFC_ECC_Mode. */ + + uint32_t u32RowAddrCycle; /*!< Defines the row address cycle. + This parameter can be a value of @ref EXMC_NFC_Row_Address_Cycle. */ + + uint8_t u8SpareSizeForUserData; /*!< Defines the spare column size for user data. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +}stc_exmc_nfc_base_cfg_t; + +/** + * @brief EXMC NFC Timing Register 0 Configuration Structure definition + */ +typedef struct +{ + uint32_t u32TS; /*!< Defines the CLE/ALE/CE setup time in memory clock cycles(tALS/tCS/tCLS). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TWP; /*!< Defines the WE# pulse width time in memory clock cycles(tWP). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TRP; /*!< Defines the RE# pulse width time in memory clock cycles(tRP). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TH; /*!< Defines the CLE/ALE/CE hold time in memory clock cycles(tALH/tCH/tCLH). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_cfg_timing_reg0_t; + +/** + * @brief EXMC NFC Timing Register 1 Configuration Structure definition + */ +typedef struct +{ + uint32_t u32TWH; /*!< Defines the WE# pulse width HIGH time in memory clock cycles(tWH). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TRH; /*!< Defines the RE# HIGH hold time in memory clock cycles(tREH). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TRR; /*!< Defines the Ready to RE# LOW time in memory clock cycles(tRR). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TWB; /*!< Defines the WE# HIGH to busy time in memory clock cycles(tWB). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_cfg_timing_reg1_t; + +/** + * @brief EXMC NFC Timing Register 2 Configuration Structure definition + */ +typedef struct +{ + uint32_t u32TCCS; /*!< Defines the command(change read/write column) delay time in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TWTR; /*!< Defines the WE# HIGH to RE# LOW time in memory clock cycles(tWHR). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TRTW; /*!< Defines the RE# HIGH to WE# LOW time in memory clock cycles(tRHW). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32TADL; /*!< Defines the Address to Data Loading time in memory clock cycles(tADL). + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ +} stc_exmc_nfc_cfg_timing_reg2_t; + +/** + * @brief EXMC NFC Initialization Structure definition + */ +typedef struct +{ + uint32_t u32OpenPage; /*!< NFC memory open-page selection. + This structure details refer @ref EXMC_NFC_Open_Page. */ + + stc_exmc_nfc_base_cfg_t stcBaseCfg; /*!< NFC memory base configure. + This structure details refer @ref stc_exmc_nfc_base_cfg_t. */ + + stc_exmc_nfc_cfg_timing_reg0_t stcTimingReg0; /*!< NFC memory timing configure 0. + This structure details refer @ref stc_exmc_nfc_cfg_timing_reg0_t. */ + + stc_exmc_nfc_cfg_timing_reg1_t stcTimingReg1; /*!< NFC memory timing configure 1. + This structure details refer @ref stc_exmc_nfc_cfg_timing_reg1_t. */ + + stc_exmc_nfc_cfg_timing_reg2_t stcTimingReg2; /*!< NFC memory timing configure 2. + This structure details refer @ref stc_exmc_nfc_cfg_timing_reg2_t. */ +} stc_exmc_nfc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Global_Macros NAND Flash Controller Global Macros + * @{ + */ + +/** + * @defgroup EXMC_NFC_Bank EXMC NFC Bank + * @{ + */ +#define EXMC_NFC_BANK_0 (0UL) /*!< Bank 0 */ +#define EXMC_NFC_BANK_1 (1UL) /*!< Bank 1 */ +#define EXMC_NFC_BANK_2 (2UL) /*!< Bank 2 */ +#define EXMC_NFC_BANK_3 (3UL) /*!< Bank 3 */ +#define EXMC_NFC_BANK_4 (4UL) /*!< Bank 4 */ +#define EXMC_NFC_BANK_5 (5UL) /*!< Bank 5 */ +#define EXMC_NFC_BANK_6 (6UL) /*!< Bank 6 */ +#define EXMC_NFC_BANK_7 (7UL) /*!< Bank 7 */ +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Memory_Command EXMC NFC Memory Command + * @{ + */ +#define EXMC_NFC_CMD_READ_1ST (0x00UL) +#define EXMC_NFC_CMD_READ_2ND (0xE0UL) + +#define EXMC_NFC_CMD_COPYBACK_READ_1ST (0x00UL) +#define EXMC_NFC_CMD_COPYBACK_READ_2ND (0x35UL) + +#define EXMC_NFC_CMD_CHANGE_RD_COL_1ST (0x05UL) +#define EXMC_NFC_CMD_CHANGE_RD_COL_2ND (0xE0UL) + +#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_1ST (0x06UL) +#define EXMC_NFC_CMD_CHANGE_RD_COL_ENHANCED_2ND (0xE0UL) + +#define EXMC_NFC_CMD_READ_CACHE_RANDOM_1ST (0x00UL) +#define EXMC_NFC_CMD_READ_CACHE_RANDOM_2ND (0x31UL) + +#define EXMC_NFC_CMD_CALCULATE_ECC (0x23UL) + +#define EXMC_NFC_CMD_READ_CACHE_SEQ (0x31UL) + +#define EXMC_NFC_CMD_READ_CACHE_END (0x3FUL) + +#define EXMC_NFC_CMD_BLK_ERASE_1ST (0x60UL) +#define EXMC_NFC_CMD_BLK_ERASE_2ND (0xD0UL) + +#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_1ST (0x60UL) +#define EXMC_NFC_CMD_BLK_ERASE_INTERLEAVED_2ND (0xD1UL) + +#define EXMC_NFC_CMD_READ_STATUS (0x70UL) + +#define EXMC_NFC_CMD_READ_STATUS_ENHANCED (0x78UL) + +#define EXMC_NFC_CMD_PAGE_PROGRAM_1ST (0x80UL) +#define EXMC_NFC_CMD_PAGE_PROGRAM_2ND (0x10UL) + +#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_1ST (0x80UL) +#define EXMC_NFC_CMD_PAGE_PROGRAM_INTERLEAVED_2ND (0x11UL) + +#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_1ST (0x80UL) +#define EXMC_NFC_CMD_PAGE_CACHE_PROGRAM_2ND (0x15UL) + +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_1ST (0x85UL) +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_2ND (0x10UL) + +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_1ST (0x85UL) +#define EXMC_NFC_CMD_COPYBACK_PROGRAM_INTERLEAVED_2ND (0x11UL) + +#define EXMC_NFC_CMD_CHANGE_WR_COL (0x85UL) + +#define EXMC_NFC_CMD_CHANGE_ROW_ADDRESS (0x85UL) + +#define EXMC_NFC_CMD_READ_ID (0x90UL) + +#define EXMC_NFC_CMD_READ_PARAMETER_PAGE (0xECUL) + +#define EXMC_NFC_CMD_READ_UNIQUE_ID (0xEDUL) + +#define EXMC_NFC_CMD_GET_FEATURES (0xEEUL) + +#define EXMC_NFC_CMD_SET_FEATURES (0xEFUL) + +#define EXMC_NFC_CMD_RESET_LUN (0xFAUL) + +#define EXMC_NFC_CMD_ASYNCHRONOUS_RESSET (0xFCUL) + +#define EXMC_NFC_CMD_DESELECT_CHIP (0xFEUL) + +#define EXMC_NFC_CMD_RESET (0xFFUL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Page_Size EXMC NFC Page Size + * @{ + */ +#define EXMC_NFC_PAGE_SIZE_2KBYTES (NFC_BACR_PAGE_0) +#define EXMC_NFC_PAGE_SIZE_4KBYTES (NFC_BACR_PAGE_1) +#define EXMC_NFC_PAGE_SIZE_8KBYTES (NFC_BACR_PAGE) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_BANK_Memory_Capacity EXMC NFC BANK Memory Capacity + * @{ + */ +#define EXMC_NFC_BANK_CAPACITY_512MBIT (NFC_BACR_SIZE_1 | NFC_BACR_SIZE_0) +#define EXMC_NFC_BANK_CAPACITY_1GBIT (NFC_BACR_SIZE_2) +#define EXMC_NFC_BANK_CAPACITY_2GBIT (NFC_BACR_SIZE_2 | NFC_BACR_SIZE_0) +#define EXMC_NFC_BANK_CAPACITY_4GBIT (NFC_BACR_SIZE_2 | NFC_BACR_SIZE_1) +#define EXMC_NFC_BANK_CAPACITY_8GBIT (NFC_BACR_SIZE) +#define EXMC_NFC_BANK_CAPACITY_16GBIT (0UL) +#define EXMC_NFC_BANK_CAPACITY_32GBIT (NFC_BACR_SIZE_0) +#define EXMC_NFC_BANK_CAPACITY_64GBIT (NFC_BACR_SIZE_1) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Memory_Width EXMC NFC Memory Width + * @{ + */ +#define EXMC_NFC_MEMORY_WIDTH_8BIT (0UL) +#define EXMC_NFC_MEMORY_WIDTH_16BIT (NFC_BACR_B16BIT) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Bank_Number EXMC NFC Bank Number + * @{ + */ +#define EXMC_NFC_1_BANK (0UL) +#define EXMC_NFC_2_BANKS (NFC_BACR_BANK_0) +#define EXMC_NFC_4_BANKS (NFC_BACR_BANK_1) +#define EXMC_NFC_8_BANKS (NFC_BACR_BANK) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Open_Page EXMC NFC Open Page + * @{ + */ +#define EXMC_NFC_OPEN_PAGE_DISABLE (0UL) +#define EXMC_NFC_OPEN_PAGE_ENABLE (PERIC_NFC_SYCTLREG_OPO) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Write_Protect EXMC NFC Write Protect + * @{ + */ +#define EXMC_NFC_WR_PROTECT_ENABLE (0UL) +#define EXMC_NFC_WR_PROTECT_DISABLE (NFC_BACR_WP) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Mode EXMC NFC ECC Mode + * @{ + */ +#define EXMC_NFC_ECC_1BIT (0UL) +#define EXMC_NFC_ECC_4BITS (NFC_BACR_ECCM_0) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Row_Address_Cycle EXMC NFC Row Address Cycle + * @{ + */ +#define EXMC_NFC_2_ROW_ADDRESS_CYCLES (0UL) +#define EXMC_NFC_3_ROW_ADDRESS_CYCLES (NFC_BACR_RAC) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Interrupt EXMC NFC Interrupt + * @{ + */ +#define EXMC_NFC_INT_ECC_UNCORRECTABLE_ERROR (NFC_IENR_ECCEUEN) +#define EXMC_NFC_INT_ECC_CORRECTABLE_ERROR (NFC_IENR_ECCECEN) +#define EXMC_NFC_INT_ECC_CALC_COMPLETION (NFC_IENR_ECCCEN) +#define EXMC_NFC_INT_ECC_ERROR (NFC_IENR_ECCEEN) +#define EXMC_NFC_INT_RB_BANK0 (NFC_IENR_RBEN_0) +#define EXMC_NFC_INT_RB_BANK1 (NFC_IENR_RBEN_1) +#define EXMC_NFC_INT_RB_BANK2 (NFC_IENR_RBEN_2) +#define EXMC_NFC_INT_RB_BANK3 (NFC_IENR_RBEN_3) +#define EXMC_NFC_INT_RB_BANK4 (NFC_IENR_RBEN_4) +#define EXMC_NFC_INT_RB_BANK5 (NFC_IENR_RBEN_5) +#define EXMC_NFC_INT_RB_BANK6 (NFC_IENR_RBEN_6) +#define EXMC_NFC_INT_RB_BANK7 (NFC_IENR_RBEN_7) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Flag EXMC NFC Flag + * @{ + */ +#define EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR (NFC_ISTR_ECCEUST) +#define EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR (NFC_ISTR_ECCECST) +#define EXMC_NFC_FLAG_ECC_CALC_COMPLETION (NFC_ISTR_ECCCST) +#define EXMC_NFC_FLAG_ECC_ERROR (NFC_ISTR_ECCEST) +#define EXMC_NFC_FLAG_RB_BANK0 (NFC_ISTR_RBST_0) +#define EXMC_NFC_FLAG_RB_BANK1 (NFC_ISTR_RBST_1) +#define EXMC_NFC_FLAG_RB_BANK2 (NFC_ISTR_RBST_2) +#define EXMC_NFC_FLAG_RB_BANK3 (NFC_ISTR_RBST_3) +#define EXMC_NFC_FLAG_RB_BANK4 (NFC_ISTR_RBST_4) +#define EXMC_NFC_FLAG_RB_BANK5 (NFC_ISTR_RBST_5) +#define EXMC_NFC_FLAG_RB_BANK6 (NFC_ISTR_RBST_6) +#define EXMC_NFC_FLAG_RB_BANK7 (NFC_ISTR_RBST_7) +#define EXMC_NFC_FLAG_ECC_CALCULATING (NFC_ISTR_RESV) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Calculate_Bytes EXMC NFC ECC Calculate Bytes + * @{ + */ +#define EXMC_NFC_ECC_CALCULATE_BLOCK_BYTES (512UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Value_Bytes EXMC NFC ECC Value Bytes + * @{ + */ +#define EXMC_NFC_1BIT_ECC_VALUE_BYTES (0x03UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_1Bit_ECC_Result EXMC NFC 1Bit ECC Result + * @{ + */ +#define EXMC_NFC_1BIT_ECC_SINGLE_BIT_ERR (NFC_ECCR_SE) +#define EXMC_NFC_1BIT_ECC_MULTIPLE_BITS_ERR (NFC_ECCR_ME) +#define EXMC_NFC_1BIT_ECC_ERR_LOCATION (NFC_ECCR_ERRLOC) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_1Bit_ECC_Error_Location_Position EXMC NFC 1Bit ECC Error Location Position + * @{ + */ +#define EXMC_NFC_1BIT_ECC_ERR_BIT_POS (NFC_ECCR_ERRLOC_POS) +#define EXMC_NFC_1BIT_ECC_ERR_BYTE_POS (NFC_ECCR_ERRLOC_POS + 3UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_ECC_Section EXMC NFC ECC Section + * @{ + */ +#define EXMC_NFC_ECC_SECTION0 (0UL) +#define EXMC_NFC_ECC_SECTION1 (1UL) +#define EXMC_NFC_ECC_SECTION2 (2UL) +#define EXMC_NFC_ECC_SECTION3 (3UL) +#define EXMC_NFC_ECC_SECTION4 (4UL) +#define EXMC_NFC_ECC_SECTION5 (5UL) +#define EXMC_NFC_ECC_SECTION6 (6UL) +#define EXMC_NFC_ECC_SECTION7 (7UL) +#define EXMC_NFC_ECC_SECTION8 (8UL) +#define EXMC_NFC_ECC_SECTION9 (9UL) +#define EXMC_NFC_ECC_SECTION10 (10UL) +#define EXMC_NFC_ECC_SECTION11 (11UL) +#define EXMC_NFC_ECC_SECTION12 (12UL) +#define EXMC_NFC_ECC_SECTION13 (13UL) +#define EXMC_NFC_ECC_SECTION14 (14UL) +#define EXMC_NFC_ECC_SECTION15 (15UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Operation_Timeout EXMC NFC Operation Timeout + * @{ + */ +#define EXMC_NFC_MAX_TIMEOUT (0xFFFFFFFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_NFC_Global_Functions + * @{ + */ + +/** + * @brief Set EXMC NFC command register value. + * @param [in] u32Val The combination value of command and arguments. + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_WriteCmdReg(uint32_t u32Val) +{ + WRITE_REG32(M4_NFC->CMDR, u32Val); +} + +/** + * @brief Set EXMC NFC Index register value. + * @param [in] u32Val The value of NFC_IDXR0. + * This parameter can be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_WriteIDXR0(uint32_t u32Val) +{ + WRITE_REG32(M4_NFC->IDXR0, u32Val); +} + +/** + * @brief Set EXMC NFC Index register value. + * @param [in] u32Val The value of NFC_IDXR1. + * This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_WriteIDXR1(uint32_t u32Val) +{ + WRITE_REG32(M4_NFC->IDXR1, u32Val); +} + +/** + * @brief De-select NFC bank. + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_NFC_DeselectChip(void) +{ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_DESELECT_CHIP); +} + +/** + * @brief Get the 4BIT ECC error section. + * @param None + * @retval The register value + */ +__STATIC_INLINE uint32_t EXMC_NFC_GetEcc4BitsErrSection(void) +{ + return READ_REG32(M4_NFC->ECC_STAT); +} + +/* Initialization and configuration EXMC NFC functions */ +en_result_t EXMC_NFC_Init(const stc_exmc_nfc_init_t *pstcInit); +void EXMC_NFC_DeInit(void); +en_result_t EXMC_NFC_StructInit(stc_exmc_nfc_init_t *pstcInit); +void EXMC_NFC_Cmd(en_functional_state_t enNewState); +void EXMC_NFC_EccCmd(en_functional_state_t enNewState); +void EXMC_NFC_WriteProtectCmd(en_functional_state_t enNewState); +void EXMC_NFC_IntCmd(uint16_t u16IntSource, en_functional_state_t enNewState); +en_flag_status_t EXMC_NFC_GetStatus(uint32_t u32Flag); +void EXMC_NFC_ClearStatus(uint32_t u32Flag); +en_flag_status_t EXMC_NFC_GetIntResultStatus(uint32_t u32Flag); +uint32_t EXMC_NFC_GetEcc1BitResult(uint32_t u32Section); +en_result_t EXMC_NFC_GetSyndrome(uint32_t u32Section, + uint16_t au16Synd[], + uint8_t u8Length); +void EXMC_NFC_SetSpareAreaSize(uint8_t u8SpareSizeForUserData); +void EXMC_NFC_SetEccMode(uint32_t u32EccMode); + +/* EXMC NFC command functions */ +uint32_t EXMC_NFC_ReadStatus(uint32_t u32Bank); +uint32_t EXMC_NFC_ReadStatusEnhanced(uint32_t u32Bank, + uint32_t u32RowAddress); +en_result_t EXMC_NFC_Reset(uint32_t u32Bank, uint32_t u32Timeout); +en_result_t EXMC_NFC_AsyncReset(uint32_t u32Bank, uint32_t u32Timeout); +en_result_t EXMC_NFC_ResetLun(uint32_t u32Bank, + uint32_t u32RowAddress, + uint32_t u32Timeout); +en_result_t EXMC_NFC_ReadId(uint32_t u32Bank, + uint32_t u32IdAddr, + uint8_t au8DevId[], + uint32_t u32NumBytes, + uint32_t u32Timeout); +en_result_t EXMC_NFC_ReadUniqueId(uint32_t u32Bank, + uint32_t u32IdAddr, + uint32_t au32UniqueId[], + uint8_t u8NumWords, + uint32_t u32Timeout); +en_result_t EXMC_NFC_ReadParameterPage(uint32_t u32Bank, + uint32_t au32Data[], + uint16_t u16NumWords, + uint32_t u32Timeout); +en_result_t EXMC_NFC_SetFeature(uint32_t u32Bank, + uint8_t u8FeatrueAddr, + const uint32_t au32Data[], + uint8_t u8NumWords, + uint32_t u32Timeout); +en_result_t EXMC_NFC_GetFeature(uint32_t u32Bank, + uint8_t u8FeatrueAddr, + uint32_t au32Data[], + uint8_t u8NumWords, + uint32_t u32Timeout); +en_result_t EXMC_NFC_EraseBlock(uint32_t u32Bank, + uint32_t u32RowAddress, + uint32_t u32Timeout); +en_result_t EXMC_NFC_ReadPageMeta(uint32_t u32Bank, + uint32_t u32Page, + uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout); +en_result_t EXMC_NFC_WritePageMeta(uint32_t u32Bank, + uint32_t u32Page, + const uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout); +en_result_t EXMC_NFC_ReadPageHwEcc(uint32_t u32Bank, + uint32_t u32Page, + uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout); +en_result_t EXMC_NFC_WritePageHwEcc(uint32_t u32Bank, + uint32_t u32Page, + const uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout); +/** + * @} + */ + +#endif /* DDL_NFC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_NFC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_ots.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_ots.h new file mode 100644 index 0000000000000000000000000000000000000000..dcc05dfceecd18d13af7bc66ed1c144638af0db9 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_ots.h @@ -0,0 +1,212 @@ +/** + ******************************************************************************* + * @file hc32f4a0_ots.h + * @brief This file contains all the functions prototypes of the OTS driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_OTS_H__ +#define __HC32F4A0_OTS_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_OTS + * @{ + */ + +#if (DDL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Types OTS Global Types + * @{ + */ + +/** + * @brief Conditions for default parameters(slope K and offset M). + * @note 'u8T1' CANNOT equal 'u8T2'. + */ +typedef struct +{ + uint16_t u16ClkFreq; /*!< Frequency(MHz) of clock sources that OTS is going to use. */ + uint8_t u8T1; /*!< Temperature value T1 for the default parameter. + This parameter can be a value of @ref OTS_Temp_Condition */ + uint8_t u8T2; /*!< Temperature value T2 for the default parameter. + This parameter can be a value of @ref OTS_Temp_Condition */ +} stc_para_cond_t; + +/** + * @brief OTS initialization structure. + */ +typedef struct +{ + uint16_t u16ClkSrc; /*!< Specifies clock source for OTS. + This parameter can be a value of @ref OTS_Clock_Source */ + float32_t f32SlopeK; /*!< K: Temperature slope (calculated by calibration experiment). \ + When you want to use the default parameters(slope K and offset M), specify it as ZERO. */ + float32_t f32OffsetM; /*!< M: Temperature offset (calculated by calibration experiment). \ + When you want to use the default parameters(slope K and offset M), specify it as ZERO. */ + uint16_t u16AutoOffEn; /*!< OTS automatic-off function control. + This parameter can be a value of @ref OTS_Automatic_Off_Ctrl */ + stc_para_cond_t stcParaCond; /*!< Specify the conditions when you want to use the default parameters(slope K and offset M). */ +} stc_ots_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Macros OTS Global Macros + * @{ + */ + +/** + * @defgroup OTS_Clock_Source OTS Clock Source + * @{ + */ +#define OTS_CLK_XTAL (0x0U) /*!< Select XTAL as OTS clock. */ +#define OTS_CLK_HRC (OTS_CTL_OTSCK) /*!< Select HRC as OTS clock */ +/** + * @} + */ + +/** + * @defgroup OTS_Automatic_Off_Ctrl OTS Automatic Off Control + * @{ + */ +#define OTS_AUTO_OFF_DISABLE (0x0U) +#define OTS_AUTO_OFF_ENABLE (OTS_CTL_TSSTP) +/** + * @} + */ + +/** + * @defgroup OTS_Temp_Condition OTS Temperature Condition For Default Parameters(slope K and offset M) + * @{ + */ +#define OTS_COND_TN40 (0U) /*!< -40 degrees Celsius. */ +#define OTS_COND_T25 (1U) /*!< 25 degrees Celsius. */ +#define OTS_COND_T125 (2U) /*!< 125 degrees Celsius. */ +/** + * @} + */ + +/** + * @defgroup OTS_Common_Trigger_Sel OTS Common Trigger Source Select + * @{ + */ +#define OTS_COM_TRIG1 (AOS_OTS_TRG_COMTRG_EN_0) +#define OTS_COM_TRIG2 (AOS_OTS_TRG_COMTRG_EN_1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup OTS_Global_Functions + * @{ + */ + +/** + * @brief Start OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Start(void) +{ + bM4_OTS->CTL_b.OTSST = (uint32_t)1U; +} + +/** + * @brief Stop OTS. + * @param None + * @retval None + */ +__STATIC_INLINE void OTS_Stop(void) +{ + bM4_OTS->CTL_b.OTSST = (uint32_t)0U; +} + +en_result_t OTS_Init(const stc_ots_init_t *pstcInit); +en_result_t OTS_StructInit(stc_ots_init_t *pstcInit); +void OTS_DeInit(void); + +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout); + +void OTS_IntCmd(en_functional_state_t enNewState); +void OTS_SetTriggerSrc(en_event_src_t enEvent); +void OTS_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState); + +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout); + +float OTS_CalculateTemp(void); + +/** + * @} + */ + +#endif /* DDL_OTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_OTS_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_pwc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_pwc.h new file mode 100644 index 0000000000000000000000000000000000000000..4d40971440473e12bb069dda6292f5d61e7d22c2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_pwc.h @@ -0,0 +1,630 @@ +/** + ******************************************************************************* + * @file hc32f4a0_pwc.h + * @brief This file contains all the functions prototypes of the PWC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_PWC_H__ +#define __HC32F4A0_PWC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_PWC + * @{ + */ + +#if (DDL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Types PWC Global Types + * @{ + */ +typedef struct +{ + uint32_t u32RamCtrl; /*!< Internal RAM power setting. */ + uint32_t u32PRamCtrl; /*!< Peripheral RAM power setting. */ + uint16_t u16RamMode; /*!< RAM setting for Operating mode, @ref PWC_RAM_Config for details */ +} stc_pwc_ram_config_t; + +typedef struct +{ + uint8_t u8PvdEn; /*!< PVD function setting, @ref PWC_PVD_Config for details */ + uint8_t u8Pvd2ExtInEn; /*!< PVD2 ext. pin input function setting, @ref PWC_PVD2_ExtIn_Config */ + uint8_t u8PvdCmpOutEn; /*!< PVD compare output function setting, @ref PWC_PVD_CMP_Config for details */ + uint8_t u8PvdIntRstSel; /*!< PVD interrupt or reset selection, @ref PWC_PVD_IntRst_Sel for details */ + uint8_t u8PvdIntRstEn; /*!< PVD interrupt or reset function setting, @ref PWC_PVD_IR_Config for details */ + uint8_t u8FilterEn; /*!< PVD digital filter function setting, @ref PWC_PVD_DF_Config for details */ + uint8_t u8FilterClk; /*!< PVD digital filter clock setting, @ref PWC_PVD_DFS_Clk_Sel for details */ + uint8_t u8PvdVoltage; /*!< PVD detect voltage setting, @ref PWC_PVD_detection_Vol for details */ + uint8_t u8PvdNmiEn; /*!< PVD NMI function setting, @ref PWC_PVD_Int_Mode_Config for details */ + uint8_t u8PvdTrigger; /*!< PVD trigger setting, @ref PWC_PVD_Trigger_Sel for details */ +} stc_pwc_pvd_config_t; + +typedef struct +{ + uint8_t u8PDMode; /*!< Power down mode, @ref PWC_PDMode_Sel for details. */ + uint8_t u8IOState; /*!< IO state in power down mode, @ref PWC_PDMode_IO_Sel for details. */ + uint8_t u8WkUpSpeed; /*!< Wakeup speed selection, @ref PWC_PDMode_WKUP_TIME_Sel for details. */ +}stc_pwc_pd_mode_config_t; + +typedef struct +{ + uint8_t u8StopDrv; /*!< Stop mode drive capacity, @ref PWC_STOP_DRV_Sel for details. */ + uint16_t u16ExBusHold; /*!< Exbus status in stop mode, @ref PWC_STOP_EXBUS_Sel for details. */ + uint16_t u16ClkKeep; /*!< System clock setting after wake-up from stop mode, + @ref PWC_STOP_CLK_Sel for details. */ + uint16_t u16FlashWait; /*!< Waiting flash stable after wake-up from stop mode, + @ref STOP_FLASH_WAIT_Sel for details. */ +} stc_pwc_stop_mode_config; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Macros PWC Global Macros + * @{ + */ + +/** + * @defgroup PWC_PDMode_Sel Power down mode selection + * @{ + */ +#define PWC_PD_MODE1 (0x00U) /*!< Power down mode 0 */ +#define PWC_PD_MODE2 (0x01U) /*!< Power down mode 1 */ +#define PWC_PD_MODE3 (0x02U) /*!< Power down mode 2 */ +#define PWC_PD_MODE4 (0x03U) /*!< Power down mode 3 */ +/** + * @} + */ + +/** + * @defgroup PWC_PDMode_IO_Sel IO state config in Power down mode + * @{ + */ +#define PWC_PD_IO_STATE1 (0x00U) /*!< IO state retain in PD mode and configurable after wakeup */ +#define PWC_PD_IO_STATE2 (PWC_PWRC0_IORTN_0) /*!< IO state retain in PD mode and configurable after wakeup & set IORTN[1:0]=00b */ +#define PWC_PD_IO_STATE3 (PWC_PWRC0_IORTN_1) /*!< IO state switch to HiZ */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_DRV_Sel Drive capacity while enter stop mode + * @{ + */ +#define PWC_STOP_DRV_HIGH (0x00U) /*!< Enter stop mode from high speed mode */ +#define PWC_STOP_DRV_LOW (PWC_PWRC1_STPDAS) /*!< Enter stop mode from ultra low speed mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_EXBUS_Sel ExBus status while enter stop mode + * @{ + */ +#define PWC_STOP_EXBUS_HIZ (0x00U) /*!< Ex-Bus Hiz in stop mode */ +#define PWC_STOP_EXBUS_HOLD (PWC_STPMCR_EXBUSOE) /*!< Ex-Bus keep in stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_STOP_CLK_Sel System clock setting after wake-up from stop mode + * @{ + */ +#define PWC_STOP_CLK_KEEP (0x00U) /*!< Keep System clock setting after wake-up from stop mode */ +#define PWC_STOP_CLK_MRC (PWC_STPMCR_CKSMRC) /*!< System clock switch to MRC after wake-up from stop mode */ +/** + * @} + */ + +/** + * @defgroup STOP_FLASH_WAIT_Sel Whether wait flash stable or not after wake-up from stop mode + * @{ + */ +#define PWC_STOP_FLASH_WAIT (0x00U) /*!< Wait flash stable after wake-up from stop mode */ +#define PWC_STOP_FLASH_NOWAIT (PWC_STPMCR_FLNWT) /*!< Don't wait flash stable after wake-up from stop mode */ +/** + * @} + */ + +/** + * @defgroup PWC_PWR_DRV_Sel Drive capacity selection + * @{ + */ +#define PWC_NOR_DRV_HIGH (PWC_PWRC2_DVS) /*!< Drive capacity in high speed operation */ +#define PWC_NOR_DRV_LOW (PWC_PWRC2_DVS_1) /*!< Drive capacity in ultra low speed operation */ +/** + * @} + */ + +/** + * @defgroup PWC_PDMode_WKUP_TIME_Sel Wakeup speed config in Power down mode + * @{ + */ +#define PWC_PD_WKUP_SLOW (0x00U) /*!< VCAP1/VCAP2 = 0.1uF x2 or 0.22uF x1 */ +#define PWC_PD_WKUP_FAST (0x01U) /*!< VCAP1/VCAP2 = 0.047uF x2 or 0.1uF x1 */ +/** + * @} + */ + +/** + * @defgroup PWC_RAM_Config Operating mode for RAM Config + * @{ + */ +#define PWC_RAM_HIGH (0x8043U) /*!< MCU operating under high frequency (lower than 240MHz) */ +#define PWC_RAM_LOW (0x9062U) /*!< MCU operating under ultra low frequency (lower than 8MHz) */ +/** + * @} + */ + +/** + * @defgroup PWC_PWMON_Config PWC Power Monitor Config + * @{ + */ +#define PWC_PWRMON_ON (PWC_PWRC_PWMONE) +#define PWC_PWRMON_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_PWMON_Sel PWC Power Monitor Selection + * @{ + */ +#define PWC_PWRMON_VINREF (0x00U) /*!< Internal reference voltage */ +#define PWC_PWRMON_VOTS (PWC_PWRC_PWMONSEL) /*!< temperature sensor voltage */ +/** + * @} + */ + +/** + * @defgroup PWC_DRV_Sel PWC Driver ability selection + * @{ + */ +#define PWC_DRV_LOW (0x00U) /*!< system clock = 32kHz */ +#define PWC_DRV_HIGH (0x07U) /*!< system clock < 48Mhz */ +/** + * @} + */ + +/** + * @defgroup PWC_PVD_Channel PWC PVD channel + * @{ + */ +#define PWC_PVD_CH1 (0x00U) +#define PWC_PVD_CH2 (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_Config PWC PVD Config + * @{ + */ +#define PWC_PVD_ON (0x01U) +#define PWC_PVD_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_PVD2_ExtIn_Config PWC PVD2 external input Config + * @{ + */ +#define PWC_PVD2_EXINP_ON (PWC_PVDCR0_EXVCCINEN) +#define PWC_PVD2_EXINP_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_IR_Config PWC PVD Interrupt/Reset Config + * @{ + */ +#define PWC_PVD_IR_ON (PWC_PVDCR1_PVD1IRE) +#define PWC_PVD_IR_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_IntRst_Sel set PVD to interrupt or reset + * @{ + */ +#define PWC_PVD_INT (0x00U) +#define PWC_PVD_RST (PWC_PVDCR1_PVD1IRS) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_CMP_Config PWC PVD Compare Config + * @{ + */ +#define PWC_PVD_CMP_ON (PWC_PVDCR1_PVD1CMPOE) +#define PWC_PVD_CMP_OFF (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_DF_Config PVD digital filter ON or OFF + * @{ + */ +#define PWC_PVD_DF_ON (0x00U) +#define PWC_PVD_DF_OFF (PWC_PVDFCR_PVD1NFDIS) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_DFS_Clk_Sel PVD digital filter sample ability + * @note modified this value must when PWC_PVD_DF_OFF + * @{ + */ +#define PWC_PVD_DFS_DIV4 (0x00U) /*!< 0.25 LRC cycle */ +#define PWC_PVD_DFS_DIV2 (PWC_PVDFCR_PVD1NFCKS_0) /*!< 0.5 LRC cycle */ +#define PWC_PVD_DFS_DIV1 (PWC_PVDFCR_PVD1NFCKS_1) /*!< 1 LRC cycle */ +#define PWC_PVD_DFS_MUL2 (PWC_PVDFCR_PVD1NFCKS) /*!< 2 LRC cycles */ +/** + * @} + */ + +/** + * @defgroup PWC_PVD_detection_Vol PWC PVD Detection voltage + * @{ + */ +#define PWC_PVD1_2V0_PVD2_2V1 (0x00U) /*!< Specifies the voltage of PVD1 is 2.0V or PVD2 is 2.0V. */ +#define PWC_PVD1_2V1_PVD2_2V3 (0x01U) /*!< Specifies the voltage of PVD1 is 2.1V or PVD2 is 2.1V. */ +#define PWC_PVD1_2V3_PVD2_2V5 (0x02U) /*!< Specifies the voltage of PVD1 is 2.3V or PVD2 is 2.3V. */ +#define PWC_PVD1_2V5_PVD2_2V6 (0x03U) /*!< Specifies the voltage of PVD1 is 2.5V or PVD2 is 2.5V. */ +#define PWC_PVD1_2V6_PVD2_2V7 (0x04U) /*!< Specifies the voltage of PVD1 is 2.6V or PVD2 is 2.6V. */ +#define PWC_PVD1_2V7_PVD2_2V8 (0x05U) /*!< Specifies the voltage of PVD1 is 2.7V or PVD2 is 2.7V. */ +#define PWC_PVD1_2V8_PVD2_2V9 (0x06U) /*!< Specifies the voltage of PVD1 is 2.8V or PVD2 is 2.8V. */ +#define PWC_PVD1_2V9_PVD2_1V1 (0x07U) /*!< Specifies the voltage of PVD1 is 2.9V or PVD2 is 1.1V (only ext. input). */ +/** + * @} + */ + +/** + * @defgroup PWC_PVD_Int_Mode_Config PVD interrupt set to maskable or non_maskable + * @{ + */ +#define PWC_PVD_INT_MASK (PWC_PVDICR_PVD1NMIS) +#define PWC_PVD_INT_NONMASK (0x00U) +/** + * @} + */ + +/** + * @defgroup PWC_PVD_Trigger_Sel PVD trigger setting + * @{ + */ +#define PWC_PVD_TRIGGER_FALLING (0x00U) +#define PWC_PVD_TRIGGER_RISING (PWC_PVDICR_PVD1EDGS_0) +#define PWC_PVD_TRIGGER_BOTH (PWC_PVDICR_PVD1EDGS_1) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Event_Sel Power down mode wakeup event selection + * @{ + */ +#define PWC_PD_WKUP_TRIG_PVD1 (PWC_PDWKES_VD1EGS) +#define PWC_PD_WKUP_TRIG_PVD2 (PWC_PDWKES_VD2EGS) +#define PWC_PD_WKUP_TRIG_WKP0 (PWC_PDWKES_WK0EGS) +#define PWC_PD_WKUP_TRIG_WKP1 (PWC_PDWKES_WK1EGS) +#define PWC_PD_WKUP_TRIG_WKP2 (PWC_PDWKES_WK2EGS) +#define PWC_PD_WKUP_TRIG_WKP3 (PWC_PDWKES_WK3EGS) +#define PWC_PD_WKUP_TRIG_MASK (PWC_PDWKES_VD1EGS | PWC_PDWKES_VD2EGS | \ + PWC_PDWKES_WK0EGS | PWC_PDWKES_WK1EGS | \ + PWC_PDWKES_WK2EGS | PWC_PDWKES_WK3EGS) +/** + * @} + */ + +/** + * @defgroup PWC_WKUP_Trigger_Edge_Sel Power down mode wakeup trigger edge selection + * @{ + */ +#define PWC_PD_WKUP_FALLING (0x00U) +#define PWC_PD_WKUP_RISING (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_DBGC_config PWC Debug Config + * @{ + */ +#define PWC_AD_INTERN_REF (0x00U) +#define PWC_AD_VBAT_DIV2 (0x01U) +/** + * @} + */ + +/** + * @defgroup PWC_VBAT_Voltage_Status PWC VBAT Voltage Status + * @{ + */ +#define PWC_VOL_VBAT_MORE_THAN_VBATREF (0x00U) /*!< Vbat > VbatREF */ +#define PWC_VOL_VBAT_LESS_THAN_VBATREF (0x01U) /*!< Vbat < VbatREF */ +/** + * @} + */ + +/** + * @defgroup PWC_VBAT_Reference_Voltage PWC VBAT Reference Voltage + * @{ + */ +#define PWC_VBAT_REF_VOL_1P8V (0x00U) /*!< Vbat reference voltage is 1.8V */ +#define PWC_VBAT_REF_VOL_2P0V (0x01U) /*!< Vbat reference voltage is 2.0V */ +/** + * @} + */ + +/** + * @defgroup PWC_BACKUP_RAM_Flag PWC Backup RAM Flag + * @{ + */ +#define PWC_BACKUP_RAM_FLAG_RAMPDF (PWC_VBATCR_RAMPDF) /*!< Backup RAM power down flag */ +#define PWC_BACKUP_RAM_FLAG_RAMVALID (PWC_VBATCR_RAMVALID) /*!< Backup RAM read/write flag */ +/** + * @} + */ + +/** + * @defgroup PWC_WKT_Clock_Source PWC WKT Clock Source + * @{ + */ +#define PWC_WKT_CLK_SRC_64HZ (0U) /*!< 64Hz Clock */ +#define PWC_WKT_CLK_SRC_XTAL32 (PWC_WKTC2_WKCKS_0) /*!< XTAL32 Clock */ +#define PWC_WKT_CLK_SRC_RTCLRC (PWC_WKTC2_WKCKS_1) /*!< RTCLRC Clock */ +/** + * @} + */ + +/** + * @defgroup PWC_REG_Write_Unlock_Code PWC register unlock code. + * @brief Lock/unlock Code for each module + * PWC_UNLOCK_CODE_0: + * Below registers are locked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * PWC_UNLOCK_CODE_1: + * Below registers are locked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are locked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is locked in RMU module. + * RSTF0 + * PWC_UNLOCK_CODE_2: + * Below registers are locked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @{ + */ +#define PWC_UNLOCK_CODE_0 (0xA501U) +#define PWC_UNLOCK_CODE_1 (0xA502U) +#define PWC_UNLOCK_CODE_2 (0xA508U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup PWC_Global_Functions + * @{ + */ +/** + * @brief Lock PWC, CLK, RMU register. + * @param [in] u16Module Lock code for each module. + * @arg PWC_UNLOCK_CODE_0: + * Below registers are locked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * @arg PWC_UNLOCK_CODE_1: + * Below registers are locked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are locked in VBAT module. + * RSTR, BATCR0, VBTBKR0~VBTBK127. + * Below registers are locked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is locked in RMU module. + * RSTF0 + * @arg PWC_UNLOCK_CODE_2: + * Below registers are locked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @retval None + */ +__STATIC_INLINE void PWC_Lock(uint16_t u16Module) +{ + M4_PWC->FPRC = (0xA500U | (uint16_t)((uint16_t)(~u16Module) & (M4_PWC->FPRC))); +} + +/** + * @brief Unlock PWC, CLK, RMU register. + * @param [in] u16Module Unlock code for each module. + * @arg PWC_UNLOCK_CODE_0: + * Below registers are unlocked in CLK module. + * XTALCFGR, XTALSTBCR, XTALCR, XTALSTDCR, XTALSTDSR, HRCTRM, HRCCR, + * MRCTRM, MRCCR, PLLCFGR, PLLCR, UPLLCFGR, UPLLCR, OSCSTBSR, CKSWR, + * SCFGR, UFSCKCFGR, TPIUCKCFGR, MCO1CFGR, MCO2CFGR, XTAL32CR, + * XTALC32CFGR, XTAL32NFR, LRCCR, LRCTRM. + * @arg PWC_UNLOCK_CODE_1: + * Below registers are unlocked in PWC module. + * PWRC0, PWRC1, PWRC2, PWRC3, PDWKE0, PDWKE1, PDWKE2, PDWKES, PDWKF0, + * PDWKF1, PWCMR, PWR_STPMCR, RAMPC0, RAMOPM. + * Below registers are unlocked in VBAT module. + * RSTR, BATCR0, VBTBKR0~VBTBK127. + * Below registers are unlocked in CLK module. + * PERICKSEL, I2SCKSEL, + * Below register is unlocked in RMU module. + * RSTF0 + * @arg PWC_UNLOCK_CODE_2: + * Below registers are unlocked in PWC module. + * PVDCR0, PVDCR1, PVDFCR, PVDLCR, PVDICR, PVDDSR + * @retval None + */ +__STATIC_INLINE void PWC_Unlock(uint16_t u16Module) +{ + SET_REG16_BIT(M4_PWC->FPRC, u16Module); +} + +/** + * @brief Lock PWC_FCG0 register . + * @param None + * @retval None + */ +__STATIC_INLINE void PWC_FCG0_Lock(void) +{ + WRITE_REG32(M4_PWC->FCG0PC, 0xA5A50000UL); +} + +/** + * @brief Unlock PWR_FCG0 register. + * @param None + * @retval None + * @note Call this function before PWC_Fcg0PeriphClockCmd() + */ +__STATIC_INLINE void PWC_FCG0_Unlock(void) +{ + WRITE_REG32(M4_PWC->FCG0PC, 0xA5A50001UL); +} + +en_result_t PWC_PowerDownStructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig); +en_result_t PWC_PowerDownConfig(const stc_pwc_pd_mode_config_t *pstcPDModeConfig); +void PWC_EnterPowerDownMode(void); +void PWC_EnterStopMode(void); +void PWC_EnterSleepMode(void); + +en_result_t PWC_StopStructInit(stc_pwc_stop_mode_config *pstcStopConfig); +en_result_t PWC_StopConfig(const stc_pwc_stop_mode_config *pstcStopConfig); +void PWC_StopDrvConfig(uint8_t u8StopDrv); +void PWC_StopClockKeepConfig(uint16_t u16ClkKeep); +void PWC_StopFlashWaitConfig(uint16_t u16FlashWait); +void PWC_StopExBusHoldConfig(uint16_t u16ExBusHold); + +en_result_t PWC_HighSpeedToLowSpeed(void); +en_result_t PWC_LowSpeedToHighSpeed(void); + +void PWC_HrcPwrCmd(en_functional_state_t enNewState); +void PWC_PllPwrCmd(en_functional_state_t enNewState); + +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState); +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState); +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState); +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState); + +en_result_t PWC_RamConfig(const stc_pwc_ram_config_t *pstcRamConfig); +en_result_t PWC_PVD_Init(uint8_t u8Ch, const stc_pwc_pvd_config_t *pstcPvdConfig); +en_result_t PWC_PVD_StructInit(stc_pwc_pvd_config_t *pstcPvdConfig); +en_flag_status_t PWC_PVD_GetStatus(uint8_t u8Flag); +void PWC_PVD_ClearStatus(void); + +void PWC_PdWakeup0Cmd(uint8_t u8Wkup0Evt, en_functional_state_t enNewState); +void PWC_PdWakeup1Cmd(uint8_t u8Wkup1Evt, en_functional_state_t enNewState); +void PWC_PdWakeup2Cmd(uint8_t u8Wkup2Evt, en_functional_state_t enNewState); +void PWC_PdWakeupTrigConfig(uint8_t u8WkupEvt, uint8_t u8TrigEdge); +en_flag_status_t PWC_GetWakeup0Status(uint8_t u8Flag); +en_flag_status_t PWC_GetWakeup1Status(uint8_t u8Flag); + +void PWC_AdcBufCmd(en_functional_state_t enNewState); +void PWC_AdcInternVolSel(uint8_t u8AdcInternVol); + +void PWC_VBAT_MonitorVolSel(uint8_t u8RefVol); +void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState); +uint8_t PWC_VBAT_GetVolStatus(void); +void PWC_VBAT_MeasureVolCmd(en_functional_state_t enNewState); +void PWC_VBAT_Reset(void); +void PWC_VBAT_PwrCmd(en_functional_state_t enNewState); + +void PWC_BkRamPwrCmd(en_functional_state_t enNewState); +en_flag_status_t PWC_GetBkRamStatus(uint8_t u8Flag); +void PWC_WriteBackupReg(uint8_t u8RegNum, uint8_t u8RegVal); +uint8_t PWC_ReadBackupReg(uint8_t u8RegNum); + +void PWC_WKT_Init(uint8_t u8ClkSrc, uint16_t u16CmpVal); +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal); +uint16_t PWC_WKT_GetCompareValue(void); +void PWC_WKT_Cmd(en_functional_state_t enNewState); +en_flag_status_t PWC_WKT_GetStatus(void); +void PWC_WKT_ClearStatus(void); + +/** + * @} + */ + +#endif /* DDL_PWC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_PWC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_qspi.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_qspi.h new file mode 100644 index 0000000000000000000000000000000000000000..d1c435fd99c0f6bf6a15c256f25e9f29c87010a4 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_qspi.h @@ -0,0 +1,430 @@ +/** + ******************************************************************************* + * @file hc32f4a0_qspi.h + * @brief This file contains all the functions prototypes of the QSPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-07-15 Wuze Corrected the definition of 'QSPI_4BIC_ENABLE'. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_QSPI_H__ +#define __HC32F4A0_QSPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_QSPI + * @{ + */ + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Types QSPI Global Types + * @{ + */ + +/** + * @brief QSPI initialization structure. + */ +typedef struct +{ + uint32_t u32ClkDiv; /*!< Specifies the clock divider for QSCK. QSCK = HCLK / u32ClkDiv. + This parameter can be a value between 2U and 64U, inclusive. */ + uint32_t u32CSSetupTiming; /*!< Specifies the setup timing of CS. + This parameter can be a value of @ref QSPI_CS_Setup_Timing */ + uint32_t u32CSReleaseTiming; /*!< Specifies the hold timing of CS. + This parameter can be a value of @ref QSPI_CS_Release_Timing */ + uint32_t u32CSIdleTime; /*!< Specifies the minimum idle time for CS. CS needs idle(stay high) for several cycles between commands. + This parameter can be a value of between 1U and 16U, inclusive. */ + uint32_t u32CSExtendTime; /*!< Extend the time of chip-select signal after SPI bus access. + This parameter can be a value of @ref QSPI_CS_Extend_Time */ + uint32_t u32SPIMode; /*!< Specifies the SPI mode. The difference between SPI modes 0 and 3 is the standby level of the QSCK signal. + The standby level of the QSCK signal in SPI mode 0 is low, and high in SPI mode 3. + This parameter can be a value of @ref QSPI_SPI_Mode */ + uint32_t u32PrefetchCmd; /*!< Enable or disable prefeth function. + This parameter can be a value of @ref QSPI_Prefetch_Cmd */ + uint32_t u32PrefetchStopPos; /*!< Specifies the position of prefetch stop. + This parameter can be a value of @ref QSPI_Prefetch_Stop_Position */ + uint32_t u32WPLevel; /*!< Specifies the level of pin WP(IO2). + This parameter can be a value of @ref QSPI_WP_Level */ + uint32_t u32CommMode; /*!< Specifies the communication mode. + This parameter can be a value of @ref QSPI_Communication_Mode */ + uint32_t u32AddrWidth; /*!< Specifies the address width. + This parameter can be a value of @ref QSPI_Addr_Width */ + uint32_t u32InstrMode; /*!< Specifies the instruction mode. + This parameter can be a value of @ref QSPI_Instruction_Mode */ + uint32_t u32AddrMode; /*!< Specifies the address mode. + This parameter can be a value of @ref QSPI_Addr_Mode */ + uint32_t u32DataMode; /*!< Specifies the data mode (used for dummy cycles and data phases) + This parameter can be a value of @ref QSPI_Data_Mode */ + uint32_t u32ReadMode; /*!< Specifies the read mode. + This parameter can be a value of @ref QSPI_Read_Mode */ + uint8_t u8RomAccessInstr; /*!< Rom access instruction. This parameter only supports read instruction of QSPI flash now. + Tis instruction must correspond to the read mode that specified by parameter 'u32ReadMode'. */ + uint32_t u32DummyCycles; /*!< Specifies the number of dummy cycles for fast read. + This parameter can be a value between 3U and 18U. */ +} stc_qspi_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Macros QSPI Global Macros + * @{ + */ + +/** + * @defgroup QSPI_Read_Mode QSPI Read Mode + * @{ + */ +#define QSPI_READ_STANDARD_READ (0x0U) /*!< Standard read mode (no dummy cycles). */ +#define QSPI_READ_FAST_READ (QSPI_CR_MDSEL_0) /*!< Fast read mode (dummy cycles between address and data). */ +#define QSPI_READ_FAST_READ_DUAL_OUTPUT (QSPI_CR_MDSEL_1) /*!< Fast read dual output mode (data on 2 lines). */ +#define QSPI_READ_FAST_READ_DUAL_IO (QSPI_CR_MDSEL_1 | \ + QSPI_CR_MDSEL_0) /*!< Fast read dual I/O mode (address and data on 2 lines). */ +#define QSPI_READ_FAST_READ_QUAD_OUTPUT (QSPI_CR_MDSEL_2) /*!< Fast read quad output mode (data on 4 lines). */ +#define QSPI_READ_FAST_READ_QUAD_IO (QSPI_CR_MDSEL_2 | \ + QSPI_CR_MDSEL_0) /*!< Fast read quad I/O mode (address and data on 4 lines). */ +#define QSPI_READ_CUSTOM_STANDARD_READ (QSPI_CR_MDSEL_2 | \ + QSPI_CR_MDSEL_1) /*!< Custom standard read mode. */ +#define QSPI_READ_CUSTOM_FAST_READ (QSPI_CR_MDSEL_2 | \ + QSPI_CR_MDSEL_1 | \ + QSPI_CR_MDSEL_0) /*!< Custom fast read mode. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Prefetch_Cmd QSPI Prefetch Cmd + * @{ + */ +#define QSPI_PREFETCH_DISABLE (0x0U) /*!< Disable prefetch. */ +#define QSPI_PREFETCH_ENABLE (QSPI_CR_PFE) /*!< Enable prefetch. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Prefetch_Stop_Position QSPI Prefetch Stop Position + * @{ + */ +#define QSPI_PREFETCH_STOP_BYTE_EDGE (0x0U) /*!< Stop prefetch at the edge of byte. */ +#define QSPI_PREFETCH_STOP_IMMED (QSPI_CR_PFSAE) /*!< Stop prefetch at current position immediately. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Communication_Mode QSPI Communication Mode + * @{ + */ +#define QSPI_COMM_ROM_ACCESS (0x0U) /*!< ROM access mode. */ +#define QSPI_COMM_DIRECT_COMM (QSPI_CR_DCOME) /*!< Direct communication mode. */ +/** + * @} + */ + +/** + * @defgroup QSPI_XIP_Mode_Command QSPI XIP Mode Command + * @{ + */ +#define QSPI_XIP_DISABLE (0x0U) /*!< XIP mode disable. */ +#define QSPI_XIP_ENABLE (QSPI_CR_XIPE) /*!< XIP mode enable. */ +/** + * @} + */ + +/** + * @defgroup QSPI_SPI_Mode QSPI SPI Mode + * @{ + */ +#define QSPI_SPI_MODE_0 (0x0U) /*!< Selects SPI mode 0. */ +#define QSPI_SPI_MODE_3 (QSPI_CR_SPIMD3) /*!< Selects SPI mode 3. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Instruction_Mode QSPI Instruction Mode + * @{ + */ +#define QSPI_INSTR_1LINE (0x0U) /*!< Instruction on a single line. */ +#define QSPI_INSTR_2LINE (QSPI_CR_IPRSL_0) /*!< Instruction on 2 lines. */ +#define QSPI_INSTR_4LINE (QSPI_CR_IPRSL_1) /*!< Instruction on 4 lines. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Mode QSPI Address Mode + * @{ + */ +#define QSPI_ADDR_1LINE (0x0U) /*!< Address on a single line. */ +#define QSPI_ADDR_2LINE (QSPI_CR_APRSL_0) /*!< Address on 2 lines. */ +#define QSPI_ADDR_4LINE (QSPI_CR_APRSL_1) /*!< Address on 4 lines. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Data_Mode QSPI Data Mode + * @{ + */ +#define QSPI_DATA_1LINE (0x0U) /*!< Data on a single line. */ +#define QSPI_DATA_2LINE (QSPI_CR_DPRSL_0) /*!< Data on 2 lines. */ +#define QSPI_DATA_4LINE (QSPI_CR_DPRSL_1) /*!< Data on 4 lines. */ +/** + * @} + */ + +/** + * @defgroup QSPI_CS_Extend_Time QSPI Chip-select Extend Time + * @{ + */ +#define QSPI_CS_EXTEND_0CYCLE (0x0U) /*!< Do not extend chip-select signal time. */ +#define QSPI_CS_EXTEND_32CYCLE (QSPI_CSCR_SSNW_0) /*!< Extend chip-select time by 32 QSCK cycles. */ +#define QSPI_CS_EXTEND_128CYCLE (QSPI_CSCR_SSNW_1) /*!< Extend chip-select time by 128 QSCK cycles. */ +#define QSPI_CS_EXTEND_INFINITE (QSPI_CSCR_SSNW_1 | \ + QSPI_CSCR_SSNW_0) /*!< Extend chip-select time infinitely. */ +/** + * @} + */ + +/** + * @defgroup QSPI_Addr_Width QSPI Address Width + * @{ + */ +#define QSPI_ADDR_WIDTH_1BYTE (0x0U) /*!< QSPI address width is 1 byte. */ +#define QSPI_ADDR_WIDTH_2BYTE (QSPI_FCR_AWSL_0) /*!< QSPI address width is 2 bytes. */ +#define QSPI_ADDR_WIDTH_3BYTE (QSPI_FCR_AWSL_1) /*!< QSPI address width is 3 bytes. */ +#define QSPI_ADDR_WIDTH_4BYTE (QSPI_FCR_AWSL_1 | \ + QSPI_FCR_AWSL_0) /*!< QSPI address width is 4 bytes. */ +/** + * @} + */ + +/** + * @defgroup QSPI_4BIC_Command QSPI 4-Byte Address Instruction Read Code Command + * @note Valid when the serial interface address width is 4 bytes. + * @{ + */ +#define QSPI_4BIC_DISABLE (0x0U) /*!< Do not use 4-byte address read instruction code. */ +#define QSPI_4BIC_ENABLE (QSPI_FCR_FOUR_BIC) /*!< Use 4-byte address read instruction code. */ +/** + * @} + */ + +/** + * @defgroup QSPI_CS_Release_Timing QSPI Chip-select Hold Timing + * @{ + */ +#define QSPI_CS_RELEASE_AFTER_0P5_CYCLE (0x0U) /*!< Release chip-select signal 0.5 QSCK cycles after the last rising edge of QSCK. */ +#define QSPI_CS_RELEASE_AFTER_1P5_CYCLE (QSPI_FCR_SSNHD) /*!< Release chip-select signal 1.5 QSCK cycles after the last rising edge of QSCK. */ +/** + * @} + */ + +/** + * @defgroup QSPI_CS_Setup_Timing QSPI Chip-select Setup Timing + * @{ + */ +#define QSPI_CS_SETUP_BEFORE_0P5_CYCLE (0x0U) /*!< Output chip-select signal 0.5 QSCK cycles before the first rising edge of QSCK. */ +#define QSPI_CS_SETUP_BEFORE_1P5_CYCLE (QSPI_FCR_SSNLD) /*!< Output chip-select signal 1.5 QSCK cycles before the first rising edge of QSCK. */ +/** + * @} + */ + +/** + * @defgroup QSPI_WP_Level QSPI Write Protect Pin Level + * @{ + */ +#define QSPI_WP_LOW (0x0U) /*!< WP(QIO2) output low. */ +#define QSPI_WP_HIGH (QSPI_FCR_WPOL) /*!< WP(QIO2) output high. */ +/** + * @} + */ + +/** + * @defgroup QSPI_QSCK_Duty_Correction_Command QSPI QSCK Duty Correction Command + * @{ + */ +#define QSPI_DUTY_CORRECTION_DISABLE (0x0U) /*!< Make no duty ratio correction on QSCK. */ +#define QSPI_DUTY_CORRECTION_ENABLE (QSPI_FCR_DUTY) /*!< Delay the rising of the QSCK signal by 0.5 HCLK cycles. \ + (Valid when HCLK is multiplied by an odd number.) */ +/** + * @} + */ + +/** + * @defgroup QSPI_Status_Flag QSPI Status Flag + * @{ + */ +#define QSPI_FLAG_DIRECT_COMM_BUSY (QSPI_SR_BUSY) /*!< Serial transfer being processed. */ +#define QSPI_FLAG_XIP_MODE (QSPI_SR_XIPF) /*!< XIP mode. */ +#define QSPI_FLAG_ROM_ACCESS_ERR (QSPI_SR_RAER) /*!< ROM access detection status in direct communication mode. */ +#define QSPI_FLAG_PREFETCH_BUF_FULL (QSPI_SR_PFFUL) /*!< Prefetch buffer is full. */ +#define QSPI_FLAG_PREFETCH_ACTIVE (QSPI_SR_PFAN) /*!< Prefetch function operating. */ + +#define QSPI_FLAG_ALL (QSPI_FLAG_DIRECT_COMM_BUSY | \ + QSPI_FLAG_XIP_MODE | \ + QSPI_FLAG_ROM_ACCESS_ERR | \ + QSPI_FLAG_PREFETCH_BUF_FULL | \ + QSPI_FLAG_PREFETCH_ACTIVE) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup QSPI_Global_Functions + * @{ + */ + +/** + * @brief Enter direct communication mode. + * @param None + * @retval None + */ +__STATIC_INLINE void QSPI_EnterDirectCommMode(void) +{ + /* Set standard read mode. */ + CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_MDSEL); + /* Enter direct communication mode. */ + SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Exit direct communication mode. + * @param None + * @retval None + */ +__STATIC_INLINE void QSPI_ExitDirectCommMode(void) +{ + CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_DCOME); +} + +/** + * @brief Write data in direct communication mode. + * @param [in] u8Val Byte data. + * @retval None + */ +__STATIC_INLINE void QSPI_WriteDirectCommValue(uint8_t u8Val) +{ + WRITE_REG32(M4_QSPI->DCOM, u8Val); +} + +/** + * @brief Read data in communication mode. + * @param None + * @retval Byte data. + */ +__STATIC_INLINE uint8_t QSPI_ReadDirectCommValue(void) +{ + return (uint8_t)M4_QSPI->DCOM; +} + +/** + * @brief Set ROM access instruction. + * @param [in] u8Instr ROM access instruction. + * @retval None + */ +__STATIC_INLINE void QSPI_SetRomAccressInstr(uint8_t u8Instr) +{ + WRITE_REG32(M4_QSPI->CCMD, u8Instr); +} + + +en_result_t QSPI_Init(const stc_qspi_init_t *pstcInit); +void QSPI_DeInit(void); +en_result_t QSPI_StructInit(stc_qspi_init_t *pstcInit); + +en_result_t QSPI_WriteData(uint32_t u32Instr, uint32_t u32Address, \ + const uint8_t pu8Src[], uint32_t u32SrcSize); +en_result_t QSPI_ReadData(uint32_t u32Address, uint8_t pu8Dest[], uint32_t u32DestSize); + +void QSPI_SetReadMode(uint32_t u32ReadMode, uint8_t u8ReadInstr, uint32_t u32DummyCycles); +void QSPI_DutyCorrectCmd(en_functional_state_t enNewState); +void QSPI_PrefetchCmd(en_functional_state_t enNewState); +void QSPI_XIPModeCmd(en_functional_state_t enNewState); +void QSPI_SetWPPinLevel(uint32_t u32Level); +void QSPI_4ByteAddrModeCmd(en_functional_state_t enNewState); +void QSPI_SelectBlock(uint32_t u32Block); + +uint32_t QSPI_GetPrefetchedSize(void); +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag); +void QSPI_ClrStatus(uint32_t u32Flag); + +void QSPI_EnterDirectCommMode(void); +void QSPI_ExitDirectCommMode(void); +void QSPI_WriteDirectCommValue(uint8_t u8Val); +uint8_t QSPI_ReadDirectCommValue(void); +void QSPI_SetRomAccressInstr(uint8_t u8Instr); + +/** + * @} + */ + +#endif /* DDL_QSPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_QSPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_rmu.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_rmu.h new file mode 100644 index 0000000000000000000000000000000000000000..0c6d45f1f67e62404be1007145c28f013ff0366e --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_rmu.h @@ -0,0 +1,124 @@ +/** + ******************************************************************************* + * @file hc32f4a0_rmu.h + * @brief This file contains all the functions prototypes of the RMU driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_RMU_H__ +#define __HC32F4A0_RMU_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_RMU + * @{ + */ +#if (DDL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Macros RMU Global Macros + * @{ + */ + +/** + * @defgroup RMU_ResetCause Rmu reset cause + * @{ + */ +#define RMU_RST_POWER_ON (RMU_RSTF0_PORF) /*!< Power on reset */ +#define RMU_RST_RESET_PIN (RMU_RSTF0_PINRF) /*!< Reset pin reset */ +#define RMU_RST_BROWN_OUT (RMU_RSTF0_BORF) /*!< Brown-out reset */ +#define RMU_RST_PVD1 (RMU_RSTF0_PVD1RF) /*!< Program voltage Detection 1 reset */ +#define RMU_RST_PVD2 (RMU_RSTF0_PVD2RF) /*!< Program voltage Detection 2 reset */ +#define RMU_RST_WDT (RMU_RSTF0_WDRF) /*!< Watchdog timer reset */ +#define RMU_RST_SWDT (RMU_RSTF0_SWDRF) /*!< Special watchdog timer reset */ +#define RMU_RST_POWER_DOWN (RMU_RSTF0_PDRF) /*!< Power down reset */ +#define RMU_RST_SOFTWARE (RMU_RSTF0_SWRF) /*!< Software reset */ +#define RMU_RST_MPU_ERR (RMU_RSTF0_MPUERF) /*!< Mpu error reset */ +#define RMU_RST_RAM_PARITY_ERR (RMU_RSTF0_RAPERF) /*!< Ram parity error reset */ +#define RMU_RST_RAM_ECC (RMU_RSTF0_RAECRF) /*!< Ram ECC reset */ +#define RMU_RST_CLK_ERR (RMU_RSTF0_CKFERF) /*!< Clk frequence error reset */ +#define RMU_RST_XTAL_ERR (RMU_RSTF0_XTALERF) /*!< Xtal error reset */ +#define RMU_RST_LOCKUP (RMU_RSTF0_LKUPRF) /*!< M4 Lockup reset */ +#define RMU_RST_MULTI (RMU_RSTF0_MULTIRF) /*!< Multiply reset cause */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RMU_Global_Functions + * @{ + */ + +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause); +void RMU_ClrStatus(void); +void RMU_CPULockUpCmd(en_functional_state_t enNewState); + +/** + * @} + */ + +#endif /* DDL_RMU_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_RMU_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_rtc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_rtc.h new file mode 100644 index 0000000000000000000000000000000000000000..fc4850935be543a4875c79b8c751b88a63e8edb4 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_rtc.h @@ -0,0 +1,458 @@ +/** + ******************************************************************************* + * @file hc32f4a0_rtc.h + * @brief This file contains all the functions prototypes of the RTC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_RTC_H__ +#define __HC32F4A0_RTC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_RTC + * @{ + */ + +#if (DDL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Types RTC Global Types + * @{ + */ + +/** + * @brief RTC Init structure definition + */ +typedef struct +{ + uint8_t u8ClockSource; /*!< Specifies the RTC clock source. + This parameter can be a value of @ref RTC_Clock_Source */ + + uint8_t u8HourFormat; /*!< Specifies the RTC hour format. + This parameter can be a value of @ref RTC_Hour_Format */ + + uint8_t u8PeriodInterrupt; /*!< Specifies the RTC period interrupt. + This parameter can be a value of @ref RTC_Period_Interrupt */ + + uint8_t u8ClkCompenEn; /*!< Specifies the validity of RTC clock compensation. + This parameter can be a value of @ref RTC_Clock_Compensation */ + + uint16_t u16ClkCompenValue; /*!< Specifies the value of RTC clock compensation. + This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF */ + + uint8_t u8CompenMode; /*!< Specifies the compensation mode of one Hz output. + This parameter can be a value of @ref RTC_Output_Compen_Mode */ +} stc_rtc_init_t; + +/** + * @brief RTC Date structure definition + */ +typedef struct +{ + uint8_t u8Year; /*!< Specifies the RTC Year. + This parameter can be a number between Min_Data = 0 and Max_Data = 99 */ + + uint8_t u8Month; /*!< Specifies the RTC Month (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + + uint8_t u8Day; /*!< Specifies the RTC Day. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ + + uint8_t u8Weekday; /*!< Specifies the RTC Weekday. + This parameter can be a value of @ref RTC_Weekday */ +} stc_rtc_date_t; + +/** + * @brief RTC Time structure definition + */ +typedef struct +{ + uint8_t u8Hour; /*!< Specifies the RTC Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FORMAT_12 is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FORMAT_24 is selected */ + + uint8_t u8Minute; /*!< Specifies the RTC Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t u8Second; /*!< Specifies the RTC Second. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t u8AmPm; /*!< Specifies the RTC Am/Pm Time (in RTC_HOUR_FORMAT_12 mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_time_t; + +/** + * @brief RTC Alarm structure definition + */ +typedef struct +{ + uint8_t u8AlarmHour; /*!< Specifies the RTC Alarm Hour. + This parameter can be a number between Min_Data = 1 and Max_Data = 12 if the RTC_HOUR_FORMAT_12 is selected. + This parameter can be a number between Min_Data = 0 and Max_Data = 23 if the RTC_HOUR_FORMAT_24 is selected */ + + uint8_t u8AlarmMinute; /*!< Specifies the RTC Alarm Minute. + This parameter can be a number between Min_Data = 0 and Max_Data = 59 */ + + uint8_t u8AlarmWeekday; /*!< Specifies the RTC Alarm Weekday. + This parameter can be a value of @ref RTC_Alarm_Weekday */ + + uint8_t u8AlarmAmPm; /*!< Specifies the RTC Alarm Am/Pm Time (in RTC_HOUR_FORMAT_12 mode). + This parameter can be a value of @ref RTC_Hour12_AM_PM */ +} stc_rtc_alarm_t; + +/** + * @brief RTC Intrusion structure definition + */ +typedef struct +{ + uint8_t u8TimeStampEn; /*!< Specifies the validity of RTC intrusion timestemp. + This parameter can be a value of @ref RTC_Intrusion_Timestamp */ + + uint8_t u8ResetBackupRegEn; /*!< Specifies the validity of RTC intrusion event that trigger backup registers reset. + This parameter can be a value of @ref RTC_Reset_Backup_Register */ + + uint8_t u8Filter; /*!< Specifies the RTC intrusion pin filter. + This parameter can be a value of @ref RTC_Intrusion_Filter */ + + uint8_t u8TrigEdge; /*!< Specifies the RTC intrusion detect edge. + This parameter can be a value of @ref RTC_Intrusion_Detect_Edge */ +} stc_rtc_intrusion_t; + +/** + * @brief RTC Timestamp structure definition + */ +typedef struct +{ + stc_rtc_time_t stcTSTime; /*!< Specifies the RTC Intrusion Timestamp Time members */ + + uint8_t u8TSMonth; /*!< Specifies the Month of RTC timestamp (in Decimal format). + This parameter can be a value of @ref RTC_Month */ + + uint8_t u8TSDay; /*!< Specifies the Day of RTC timestamp. + This parameter can be a number between Min_Data = 1 and Max_Data = 31 */ +} stc_rtc_timestamp_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Macros RTC Global Macros + * @{ + */ + +/** + * @defgroup RTC_Data_Format RTC Data Format + * @{ + */ +#define RTC_DATA_FORMAT_DEC (0x00U) /*!< Decimal data format */ +#define RTC_DATA_FORMAT_BCD (0x01U) /*!< BCD data format */ +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Source RTC Clock Source + * @{ + */ +#define RTC_CLOCK_SOURCE_XTAL32 (0U) /*!< XTAL32 Clock */ +#define RTC_CLOCK_SOURCE_RTCLRC (RTC_CR3_RCKSEL | RTC_CR3_LRCEN) /*!< RTC LRC Clock */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour_Format RTC Hour Format + * @{ + */ +#define RTC_HOUR_FORMAT_12 (0U) /*!< 12 hour time system */ +#define RTC_HOUR_FORMAT_24 (RTC_CR1_AMPM) /*!< 24 hour time system */ +/** + * @} + */ + +/** + * @defgroup RTC_Period_Interrupt RTC Period Interrupt + * @{ + */ +#define RTC_PERIOD_INT_INVALID (0U) /*!< Periodic interrupt invalid */ +#define RTC_PERIOD_INT_HALF_SECOND (RTC_CR1_PRDS_0) /*!< Periodic interrupt per half second */ +#define RTC_PERIOD_INT_ONE_SECOND (RTC_CR1_PRDS_1) /*!< Periodic interrupt per second */ +#define RTC_PERIOD_INT_ONE_MINUTE (RTC_CR1_PRDS_0 | RTC_CR1_PRDS_1) /*!< Periodic interrupt per minute */ +#define RTC_PERIOD_INT_ONE_HOUR (RTC_CR1_PRDS_2) /*!< Periodic interrupt per hour */ +#define RTC_PERIOD_INT_ONE_DAY (RTC_CR1_PRDS_0 | RTC_CR1_PRDS_2) /*!< Periodic interrupt per day */ +#define RTC_PERIOD_INT_ONE_MONTH (RTC_CR1_PRDS_1 | RTC_CR1_PRDS_2) /*!< Periodic interrupt per month */ +/** + * @} + */ + +/** + * @defgroup RTC_Clock_Compensation RTC Clock Compensation + * @{ + */ +#define RTC_CLOCK_COMPEN_DISABLE (0U) +#define RTC_CLOCK_COMPEN_ENABLE (RTC_ERRCRH_COMPEN) +/** + * @} + */ + +/** + * @defgroup RTC_Output_Compen_Mode RTC Output Compensation Mode + * @{ + */ +#define RTC_OUTPUT_COMPEN_MODE_DISTRIBUTED (0U) /*!< Distributed compensation 1Hz output */ +#define RTC_OUTPUT_COMPEN_MODE_UNIFORM (RTC_CR1_ONEHZSEL) /*!< Uniform compensation 1Hz output */ +/** + * @} + */ + +/** + * @defgroup RTC_Hour12_AM_PM RTC Hour12 AM/PM + * @{ + */ +#define RTC_HOUR12_AM_HOUR24 (0U) /*!< AM or 24-hour format */ +#define RTC_HOUR12_PM (RTC_HOUR_HOURD_1) /*!< PM */ +/** + * @} + */ + +/** + * @defgroup RTC_Month RTC Month + * @{ + */ +#define RTC_MONTH_JANUARY (0x01U) +#define RTC_MONTH_FEBRUARY (0x02U) +#define RTC_MONTH_MARCH (0x03U) +#define RTC_MONTH_APRIL (0x04U) +#define RTC_MONTH_MAY (0x05U) +#define RTC_MONTH_JUNE (0x06U) +#define RTC_MONTH_JULY (0x07U) +#define RTC_MONTH_AUGUST (0x08U) +#define RTC_MONTH_SEPTEMBER (0x09U) +#define RTC_MONTH_OCTOBER (0x0AU) +#define RTC_MONTH_NOVEMBER (0x0BU) +#define RTC_MONTH_DECEMBER (0x0CU) +/** + * @} + */ + +/** + * @defgroup RTC_Weekday RTC Weekday + * @{ + */ +#define RTC_WEEKDAY_SUNDAY (0x00U) +#define RTC_WEEKDAY_MONDAY (0x01U) +#define RTC_WEEKDAY_TUESDAY (0x02U) +#define RTC_WEEKDAY_WEDNESDAY (0x03U) +#define RTC_WEEKDAY_THURSDAY (0x04U) +#define RTC_WEEKDAY_FRIDAY (0x05U) +#define RTC_WEEKDAY_SATURDAY (0x06U) +/** + * @} + */ + +/** + * @defgroup RTC_Alarm_Weekday RTC Alarm Weekday + * @{ + */ +#define RTC_ALARM_WEEKDAY_SUNDAY (0x01U) +#define RTC_ALARM_WEEKDAY_MONDAY (0x02U) +#define RTC_ALARM_WEEKDAY_TUESDAY (0x04U) +#define RTC_ALARM_WEEKDAY_WEDNESDAY (0x08U) +#define RTC_ALARM_WEEKDAY_THURSDAY (0x10U) +#define RTC_ALARM_WEEKDAY_FRIDAY (0x20U) +#define RTC_ALARM_WEEKDAY_SATURDAY (0x40U) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Channel RTC Intrustion Channel + * @{ + */ +#define RTC_INTRU_CH0 (0x00U) +#define RTC_INTRU_CH1 (0x04U) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Timestamp RTC Intrustion Timestamp + * @{ + */ +#define RTC_INTRU_TIMESTAMP_DISABLE (0U) +#define RTC_INTRU_TIMESTAMP_ENABLE (RTC_TPCR0_TSTPE0) +/** + * @} + */ + +/** + * @defgroup RTC_Reset_Backup_Register RTC Reset Backup Register + * @{ + */ +#define RTC_RESET_BACKUP_REG_DISABLE (0U) +#define RTC_RESET_BACKUP_REG_ENABLE (RTC_TPCR0_TPRSTE0) +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Filter RTC Intrusion Filter + * @{ + */ +#define RTC_INTRU_FILTER_INVALID (0U) /*!< Invalid filter function */ +#define RTC_INTRU_FILTER_THREE_TIME (RTC_TPCR0_TPNF0_1) /*!< The filter detection is consistent with the timing clock for 3 times */ +#define RTC_INTRU_FILTER_THREE_TIME_CLK_DIV32 (RTC_TPCR0_TPNF0) /*!< The filter detection is consistent with the 32 frequency division of the timing clock for 3 times */ +/** + * @} + */ + +/** + * @defgroup RTC_Intrusion_Detect_Edge RTC Intrusion Detect Edge + * @{ + */ +#define RTC_DETECT_EDGE_NONE (0U) /*!< No detect */ +#define RTC_DETECT_EDGE_RISING (RTC_TPCR0_TPCT0_0) /*!< Detect rising edge */ +#define RTC_DETECT_EDGE_FALLING (RTC_TPCR0_TPCT0_1) /*!< Detect falling edge */ +#define RTC_DETECT_EDGE_RISING_FALLING (RTC_TPCR0_TPCT0) /*!< Detect rising and falling edge */ +/** + * @} + */ + +/** + * @defgroup RTC_Flag RTC Flag + * @{ + */ +#define RTC_FLAG_PRDF (RTC_CR2_PRDF) /*!< Period flag */ +#define RTC_FLAG_ALMF (RTC_CR2_ALMF) /*!< Alarm flag */ +#define RTC_FLAG_RWEN (RTC_CR2_RWEN) /*!< Read and write permission flag */ +#define RTC_FLAG_TPOVF ((uint32_t)RTC_TPSR_TPOVF << 16U) /*!< Intrusion overflow flag */ +#define RTC_FLAG_TPF0 ((uint32_t)RTC_TPSR_TPF0 << 16U) /*!< RTCIC0 intrusion flag */ +#define RTC_FLAG_TPF1 ((uint32_t)RTC_TPSR_TPF1 << 16U) /*!< RTCIC1 intrusion flag */ +/** + * @} + */ + +/** + * @defgroup RTC_Interrupt RTC Interrupt + * @{ + */ +#define RTC_INT_PRDIE (RTC_CR2_PRDIE) /*!< Period interrupt */ +#define RTC_INT_ALMIE (RTC_CR2_ALMIE) /*!< Alarm interrupt */ +#define RTC_INT_TPIE0 ((uint32_t)RTC_TPCR0_TPIE0 << 8U) /*!< RTCIC0 intrusion interrupt */ +#define RTC_INT_TPIE1 ((uint32_t)RTC_TPCR1_TPIE1 << 16U) /*!< RTCIC1 intrusion interrupt */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup RTC_Global_Functions + * @{ + */ + +/* Initialization and configuration functions */ +en_result_t RTC_DeInit(void); +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit); +en_result_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit); +en_result_t RTC_EnterRwMode(void); +en_result_t RTC_ExitRwMode(void); +void RTC_PeriodIntConfig(uint8_t u8IntCond); +en_result_t RTC_LowPowerCheck(void); +void RTC_SetClkCompenValue(uint16_t u16CompenVal); +void RTC_Cmd(en_functional_state_t enNewSta); +void RTC_LrcCmd(en_functional_state_t enNewSta); +en_functional_state_t RTC_GetCounterState(void); +void RTC_OneHzOutputCmd(en_functional_state_t enNewSta); +void RTC_ClkCompenCmd(en_functional_state_t enNewSta); + +/* Date and time functions */ +en_result_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +en_result_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate); +en_result_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); +en_result_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime); + +/* Alarm configuration functions */ +en_result_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +en_result_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm); +void RTC_AlarmCmd(en_functional_state_t enNewSta); + +/* Intrusion timestamp functions */ +en_result_t RTC_IntrusionConfig(uint8_t u8Ch, const stc_rtc_intrusion_t *pstcIntru); +en_result_t RTC_GetIntrusionTimestamp(uint8_t u8Format, stc_rtc_timestamp_t *pstcTimestamp); +void RTC_IntrusionCmd(uint8_t u8Ch, en_functional_state_t enNewSta); + +/* Interrupt and flag management functions */ +void RTC_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta); +en_flag_status_t RTC_GetStatus(uint32_t u32Flag); +void RTC_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* DDL_RTC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_RTC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_sdioc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_sdioc.h new file mode 100644 index 0000000000000000000000000000000000000000..eeb92d52a8a5a0518af3652cf21a922a6a1c386d --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_sdioc.h @@ -0,0 +1,753 @@ +/** + ******************************************************************************* + * @file hc32f4a0_sdioc.h + * @brief This file contains all the functions prototypes of the SDIOC driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_SDIOC_H__ +#define __HC32F4A0_SDIOC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_SDIOC + * @{ + */ + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Types SDIOC Global Types + * @{ + */ + +/** + * @brief SDIOC Init structure definition + */ +typedef struct +{ + uint32_t u32Mode; /*!< Specifies the SDIOC work mode. + This parameter can be a value of @ref SDIOC_Mode */ + + uint8_t u8CardDetectSelect; /*!< Specifies the SDIOC card detect source select. + This parameter can be a value of @ref SDIOC_Card_Detect_Select */ + + uint8_t u8SpeedMode; /*!< Specifies the SDIOC speed mode. + This parameter can be a value of @ref SDIOC_Speed_Mode */ + + uint8_t u8BusWidth; /*!< Specifies the SDIOC bus width. + This parameter can be a value of @ref SDIOC_Bus_Width */ + + uint16_t u16ClockDiv; /*!< Specifies the SDIOC clock division. + This parameter can be a value of @ref SDIOC_Clock_Division */ +} stc_sdioc_init_t; + +/** + * @brief SDIOC Command Init structure definition + */ +typedef struct +{ + uint32_t u32Argument; /*!< Specifies the SDIOC command argument. */ + + uint16_t u16CmdIndex; /*!< Specifies the SDIOC command index. + This parameter must be a number between Min_Data = 0 and Max_Data = 63 */ + + uint16_t u16CmdType; /*!< Specifies the SDIOC command type. + This parameter can be a value of @ref SDIOC_Command_Type */ + + uint16_t u16DataLineEn; /*!< Specifies whether SDIOC uses data lines in current command. + This parameter can be a value of @ref SDIOC_Data_Line_Valid */ + + uint16_t u16RespType; /*!< Specifies the SDIOC response type. + This parameter can be a value of @ref SDIOC_Response_Type */ +} stc_sdioc_cmd_init_t; + +/** + * @brief SDIOC Data Init structure definition + */ +typedef struct +{ + uint16_t u16BlockSize; /*!< Specifies the SDIOC data block size. + This parameter must be a number between Min_Data = 1 and Max_Data = 512 */ + + uint16_t u16BlockCount; /*!< Specifies the SDIOC data block count. + This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF */ + + uint16_t u16TransferDir; /*!< Specifies the SDIOC data transfer direction. + This parameter can be a value of @ref SDIOC_Transfer_Direction */ + + uint16_t u16AutoCMD12En; /*!< Specifies the validity of the SDIOC Auto Send CMD12. + This parameter can be a value of @ref SDIOC_Auto_Send_CMD12 */ + + uint16_t u16TransferMode; /*!< Specifies the SDIOC data transfer mode. + This parameter can be a value of @ref SDIOC_Transfer_Mode */ + + uint8_t u16DataTimeout; /*!< Specifies the SDIOC data timeout time. + This parameter can be a value of @ref SDIOC_Data_Timeout_Time */ +} stc_sdioc_data_init_t; + + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Macros SDIOC Global Macros + * @{ + */ + +/** + * @defgroup SDIOC_Mode SDIOC Mode + * @{ + */ +#define SDIOC_MODE_SD (0x00UL) /*!< SDIOCx selects SD mode */ +#define SDIOC_MODE_MMC (0x01UL) /*!< SDIOCx selects MMC mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Select SDIOC Card Detect Select + * @{ + */ +#define SDIOC_CARD_DETECT_CD_PIN_LEVEL (0x00U) /*!< SDIOCx_CD(x=1~2) line is selected (for normal use) */ +#define SDIOC_CARD_DETECT_TEST_SIGNAL (SDIOC_HOSTCON_CDSS) /*!< The Card Detect Test Level is selected(for test purpose) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Card_Detect_Test_Level SDIOC Card Detect Test Level + * @{ + */ +#define SDIOC_CARD_DETECT_TEST_LEVEL_LOW (0x00U) /*!< Card identification test signal is low level (with device insertion) */ +#define SDIOC_CARD_DETECT_TEST_LEVEL_HIGH (SDIOC_HOSTCON_CDTL) /*!< Card identification test signal is high level (no device insertion) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Speed_Mode SDIOC Speed Mode + * @{ + */ +#define SDIOC_SPEED_MODE_NORMAL (0x00U) /*!< Normal speed mode */ +#define SDIOC_SPEED_MODE_HIGH (SDIOC_HOSTCON_HSEN) /*!< High speed mode */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Bus_Width SDIOC Bus Width + * @{ + */ +#define SDIOC_BUS_WIDTH_1BIT (0x00U) /*!< The Bus width is 1 bit */ +#define SDIOC_BUS_WIDTH_4BIT (SDIOC_HOSTCON_DW) /*!< The Bus width is 4 bit */ +#define SDIOC_BUS_WIDTH_8BIT (SDIOC_HOSTCON_EXDW) /*!< The Bus width is 8 bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Clock_Division SDIOC Clock Division + * @{ + */ +#define SDIOC_CLOCK_DIV_1 (0x00U) /*!< PCLK1/1 */ +#define SDIOC_CLOCK_DIV_2 (SDIOC_CLKCON_FS_0) /*!< PCLK1/2 */ +#define SDIOC_CLOCK_DIV_4 (SDIOC_CLKCON_FS_1) /*!< PCLK1/4 */ +#define SDIOC_CLOCK_DIV_8 (SDIOC_CLKCON_FS_2) /*!< PCLK1/8 */ +#define SDIOC_CLOCK_DIV_16 (SDIOC_CLKCON_FS_3) /*!< PCLK1/16 */ +#define SDIOC_CLOCK_DIV_32 (SDIOC_CLKCON_FS_4) /*!< PCLK1/32 */ +#define SDIOC_CLOCK_DIV_64 (SDIOC_CLKCON_FS_5) /*!< PCLK1/64 */ +#define SDIOC_CLOCK_DIV_128 (SDIOC_CLKCON_FS_6) /*!< PCLK1/128 */ +#define SDIOC_CLOCK_DIV_256 (SDIOC_CLKCON_FS_7) /*!< PCLK1/256 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Command_Type SDIOC Command Type + * @{ + */ +#define SDIOC_CMD_TYPE_NORMAL (0x00U) /*!< Other commands */ +#define SDIOC_CMD_TYPE_SUSPEND (SDIOC_CMD_TYP_0) /*!< CMD52 for writing "Bus Suspend" in CCCR */ +#define SDIOC_CMD_TYPE_RESUME (SDIOC_CMD_TYP_1) /*!< CMD52 for writing "Function Select" in CCCR */ +#define SDIOC_CMD_TYPE_ABORT (SDIOC_CMD_TYP) /*!< CMD12, CMD52 for writing "I/O Abort" in CCCR */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Line_Valid SDIOC Data Line Valid + * @{ + */ +#define SDIOC_DATA_LINE_DISABLE (0x00U) /*!< The current command uses only SDIOCx_CMD(x=1~2) command line */ +#define SDIOC_DATA_LINE_ENABLE (SDIOC_CMD_DAT) /*!< The current command requires the use of SDIOCx_Dy(x=1~2) data line */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Direction SDIOC Transfer Direction + * @{ + */ +#define SDIOC_TRANSFER_DIR_TO_CARD (0x00U) /*!< Write (Host to Card) */ +#define SDIOC_TRANSFER_DIR_TO_HOST (SDIOC_TRANSMODE_DDIR) /*!< Read (Card to Host) */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_Send_CMD12 SDIOC Auto Send CMD12 + * @{ + */ +#define SDIOC_AUTO_SEND_CMD12_DISABLE (0x00U) /*!< Do not send autocommands */ +#define SDIOC_AUTO_SEND_CMD12_ENABLE (SDIOC_TRANSMODE_ATCEN_0) /*!< CMD12 is automatically sent after multiple block transfers */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Transfer_Mode SDIOC Transfer Mode + * @{ + */ +#define SDIOC_TRANSFER_MODE_SINGLE (0x00U) /*!< Single Block transfer */ +#define SDIOC_TRANSFER_MODE_INFINITE (SDIOC_TRANSMODE_MULB) /*!< Infinite Block transfer */ +#define SDIOC_TRANSFER_MODE_MULTIPLE (SDIOC_TRANSMODE_MULB | SDIOC_TRANSMODE_BCE) /*!< Multiple Block transfer */ +#define SDIOC_TRANSFER_MODE_STOP_MULTIPLE (0x8000U | SDIOC_TRANSFER_MODE_MULTIPLE) /*!< Stop Multiple Block transfer */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Data_Timeout_Time SDIOC Data Timeout Time + * @{ + */ +#define SDIOC_DATA_TIMEOUT_CLK_2_13 (0x00U) /*!< Timeout time: PCLK1*2^13 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_14 (0x01U) /*!< Timeout time: PCLK1*2^14 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_15 (0x02U) /*!< Timeout time: PCLK1*2^15 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_16 (0x03U) /*!< Timeout time: PCLK1*2^16 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_17 (0x04U) /*!< Timeout time: PCLK1*2^17 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_18 (0x05U) /*!< Timeout time: PCLK1*2^18 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_19 (0x06U) /*!< Timeout time: PCLK1*2^19 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_20 (0x07U) /*!< Timeout time: PCLK1*2^20 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_21 (0x08U) /*!< Timeout time: PCLK1*2^21 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_22 (0x09U) /*!< Timeout time: PCLK1*2^22 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_23 (0x0AU) /*!< Timeout time: PCLK1*2^23 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_24 (0x0BU) /*!< Timeout time: PCLK1*2^24 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_25 (0x0CU) /*!< Timeout time: PCLK1*2^25 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_26 (0x0DU) /*!< Timeout time: PCLK1*2^26 */ +#define SDIOC_DATA_TIMEOUT_CLK_2_27 (0x0EU) /*!< Timeout time: PCLK1*2^27 */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Register SDIOC Response Register + * @{ + */ +#define SDIOC_RESPONSE_REG_BIT0_31 (0x00U) /*!< Command Response Register 0-31bit */ +#define SDIOC_RESPONSE_REG_BIT32_63 (0x04U) /*!< Command Response Register 32-63bit */ +#define SDIOC_RESPONSE_REG_BIT64_95 (0x08U) /*!< Command Response Register 64-95bit */ +#define SDIOC_RESPONSE_REG_BIT96_127 (0x0CU) /*!< Command Response Register 96-127bit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Software_Reset_Type SDIOC_Software_Reset_Type + * @{ + */ +#define SDIOC_SW_RESET_DATA_LINE (SDIOC_SFTRST_RSTD) /*!< Only part of data circuit is reset */ +#define SDIOC_SW_RESET_CMD_LINE (SDIOC_SFTRST_RSTC) /*!< Only part of command circuit is reset */ +#define SDIOC_SW_RESET_ALL (SDIOC_SFTRST_RSTA) /*!< Reset the entire Host Controller except for the card detection circuit */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Output_Clock_Frequency SDIOC Output Clock Frequency + * @{ + */ +#define SDIOC_OUTPUT_CLK_FREQ_400K (400000UL) /*!< SDIOC clock: 400KHz */ +#define SDIOC_OUTPUT_CLK_FREQ_25M (25000000UL) /*!< SDIOC clock: 25MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_26M (26000000UL) /*!< SDIOC clock: 26MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_50M (50000000UL) /*!< SDIOC clock: 50MHz */ +#define SDIOC_OUTPUT_CLK_FREQ_52M (52000000UL) /*!< SDIOC clock: 52MHz */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Host_Status SDIOC Host Status + * @{ + */ +#define SDIOC_HOST_FLAG_CMDL (SDIOC_PSTAT_CMDL) /*!< CMD Line Level status */ +#define SDIOC_HOST_FLAG_DATL (SDIOC_PSTAT_DATL) /*!< DAT[3:0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D0 (SDIOC_PSTAT_DATL_0) /*!< DAT[0] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D1 (SDIOC_PSTAT_DATL_1) /*!< DAT[1] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D2 (SDIOC_PSTAT_DATL_2) /*!< DAT[2] Line Level status */ +#define SDIOC_HOST_FLAG_DATL_D3 (SDIOC_PSTAT_DATL_3) /*!< DAT[3] Line Level status */ +#define SDIOC_HOST_FLAG_WPL (SDIOC_PSTAT_WPL) /*!< Write Protect Line Level status */ +#define SDIOC_HOST_FLAG_CDL (SDIOC_PSTAT_CDL) /*!< Card Detect Line Level status */ +#define SDIOC_HOST_FLAG_CSS (SDIOC_PSTAT_CSS) /*!< Device Stable Status */ +#define SDIOC_HOST_FLAG_CIN (SDIOC_PSTAT_CIN) /*!< Device Inserted status */ +#define SDIOC_HOST_FLAG_BRE (SDIOC_PSTAT_BRE) /*!< Data buffer full status */ +#define SDIOC_HOST_FLAG_BWE (SDIOC_PSTAT_BWE) /*!< Data buffer empty status */ +#define SDIOC_HOST_FLAG_RTA (SDIOC_PSTAT_RTA) /*!< Read operation status */ +#define SDIOC_HOST_FLAG_WTA (SDIOC_PSTAT_WTA) /*!< Write operation status */ +#define SDIOC_HOST_FLAG_DA (SDIOC_PSTAT_DA) /*!< DAT Line transfer status */ +#define SDIOC_HOST_FLAG_CID (SDIOC_PSTAT_CID) /*!< Command Inhibit with data status */ +#define SDIOC_HOST_FLAG_CIC (SDIOC_PSTAT_CIC) /*!< Command Inhibit status */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Normal_Error_Interrupt_Status SDIOC Normal Error Interrupt Status + * @{ + */ +#define SDIOC_NORMAL_INT_FLAG_EI (SDIOC_NORINTST_EI) /*!< Error Interrupt Status */ +#define SDIOC_NORMAL_INT_FLAG_CINT (SDIOC_NORINTST_CINT) /*!< Card Interrupt status */ +#define SDIOC_NORMAL_INT_FLAG_CRM (SDIOC_NORINTST_CRM) /*!< Card Removal status */ +#define SDIOC_NORMAL_INT_FLAG_CIST (SDIOC_NORINTST_CIST) /*!< Card Insertion status */ +#define SDIOC_NORMAL_INT_FLAG_BRR (SDIOC_NORINTST_BRR) /*!< Buffer Read Ready status */ +#define SDIOC_NORMAL_INT_FLAG_BWR (SDIOC_NORINTST_BWR) /*!< Buffer Write Ready status */ +#define SDIOC_NORMAL_INT_FLAG_BGE (SDIOC_NORINTST_BGE) /*!< Block Gap Event status */ +#define SDIOC_NORMAL_INT_FLAG_TC (SDIOC_NORINTST_TC) /*!< Transfer Complete status */ +#define SDIOC_NORMAL_INT_FLAG_CC (SDIOC_NORINTST_CC) /*!< Command Complete status */ +#define SDIOC_ERROR_INT_FLAG_ACE ((uint32_t)SDIOC_ERRINTST_ACE << 16U) /*!< Auto CMD12 Error Status */ +#define SDIOC_ERROR_INT_FLAG_DEBE ((uint32_t)SDIOC_ERRINTST_DEBE << 16U) /*!< Data End Bit Error status */ +#define SDIOC_ERROR_INT_FLAG_DCE ((uint32_t)SDIOC_ERRINTST_DCE << 16U) /*!< Data CRC Error status */ +#define SDIOC_ERROR_INT_FLAG_DTOE ((uint32_t)SDIOC_ERRINTST_DTOE << 16U) /*!< Data Timeout Error status */ +#define SDIOC_ERROR_INT_FLAG_CIE ((uint32_t)SDIOC_ERRINTST_CIE << 16U) /*!< Command Index Error status */ +#define SDIOC_ERROR_INT_FLAG_CEBE ((uint32_t)SDIOC_ERRINTST_CEBE << 16U) /*!< Command End Bit Error status */ +#define SDIOC_ERROR_INT_FLAG_CCE ((uint32_t)SDIOC_ERRINTST_CCE << 16U) /*!< Command CRC Error status */ +#define SDIOC_ERROR_INT_FLAG_CTOE ((uint32_t)SDIOC_ERRINTST_CTOE << 16U) /*!< Command Timeout Error status */ +#define SDIOC_ERROR_INT_STATIC_FLAGS ((uint32_t)SDIOC_ERROR_INT_FLAG_ACE | SDIOC_ERROR_INT_FLAG_DEBE | \ + SDIOC_ERROR_INT_FLAG_DCE | SDIOC_ERROR_INT_FLAG_DTOE | \ + SDIOC_ERROR_INT_FLAG_CIE | SDIOC_ERROR_INT_FLAG_CEBE | \ + SDIOC_ERROR_INT_FLAG_CCE | SDIOC_ERROR_INT_FLAG_CTOE | \ + SDIOC_NORMAL_INT_FLAG_TC | SDIOC_NORMAL_INT_FLAG_CC) +/** + * @} + */ + +/** + * @defgroup SDIOC_Normal_Error_Interrupt SDIOC Normal Error Interrupt + * @{ + */ +#define SDIOC_NORMAL_INT_CINTSEN (SDIOC_NORINTSGEN_CINTSEN) /*!< Card Interrupt */ +#define SDIOC_NORMAL_INT_CRMSEN (SDIOC_NORINTSGEN_CRMSEN) /*!< Card Removal Interrupt */ +#define SDIOC_NORMAL_INT_CISTSEN (SDIOC_NORINTSGEN_CISTSEN) /*!< Card Insertion Interrupt */ +#define SDIOC_NORMAL_INT_BRRSEN (SDIOC_NORINTSGEN_BRRSEN) /*!< Buffer Read Ready Interrupt */ +#define SDIOC_NORMAL_INT_BWRSEN (SDIOC_NORINTSGEN_BWRSEN) /*!< Buffer Write Ready Interrupt */ +#define SDIOC_NORMAL_INT_BGESEN (SDIOC_NORINTSGEN_BGESEN) /*!< Block Gap Event Interrupt */ +#define SDIOC_NORMAL_INT_TCSEN (SDIOC_NORINTSGEN_TCSEN) /*!< Transfer Complete Interrupt */ +#define SDIOC_NORMAL_INT_CCSEN (SDIOC_NORINTSGEN_CCSEN) /*!< Command Complete Interrupt */ +#define SDIOC_ERROR_INT_ACESEN ((uint32_t)SDIOC_ERRINTSGEN_ACESEN << 16U) /*!< Auto CMD12 Error Interrupt */ +#define SDIOC_ERROR_INT_DEBESEN ((uint32_t)SDIOC_ERRINTSGEN_DEBESEN << 16U) /*!< Data End Bit Error Interrupt */ +#define SDIOC_ERROR_INT_DCESEN ((uint32_t)SDIOC_ERRINTSGEN_DCESEN << 16U) /*!< Data CRC Error Interrupt */ +#define SDIOC_ERROR_INT_DTOESEN ((uint32_t)SDIOC_ERRINTSGEN_DTOESEN << 16U) /*!< Data Timeout Error Interrupt */ +#define SDIOC_ERROR_INT_CIESEN ((uint32_t)SDIOC_ERRINTSGEN_CIESEN << 16U) /*!< Command Index Error Interrupt */ +#define SDIOC_ERROR_INT_CEBESEN ((uint32_t)SDIOC_ERRINTSGEN_CEBESEN << 16U) /*!< Command End Bit Error Interrupt */ +#define SDIOC_ERROR_INT_CCESEN ((uint32_t)SDIOC_ERRINTSGEN_CCESEN << 16U) /*!< Command CRC Error Interrupt */ +#define SDIOC_ERROR_INT_CTOESEN ((uint32_t)SDIOC_ERRINTSGEN_CTOESEN << 16U) /*!< Command Timeout Error Interrupt */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Auto_CMD_Error_Status SDIOC Auto CMD Error Status + * @{ + */ +#define SDIOC_AUTO_CMD_ERROR_FLAG_CMDE (SDIOC_ATCERRST_CMDE) /*!< Command Not Issued By Auto CMD12 Error Status */ +#define SDIOC_AUTO_CMD_ERROR_FLAG_IE (SDIOC_ATCERRST_IE) /*!< Auto CMD12 Index Error status */ +#define SDIOC_AUTO_CMD_ERROR_FLAG_EBE (SDIOC_ATCERRST_EBE) /*!< Auto CMD12 End Bit Error status */ +#define SDIOC_AUTO_CMD_ERROR_FLAG_CE (SDIOC_ATCERRST_CE) /*!< Auto CMD12 CRC Error status */ +#define SDIOC_AUTO_CMD_ERROR_FLAG_TOE (SDIOC_ATCERRST_TOE) /*!< Auto CMD12 Timeout Error status */ +#define SDIOC_AUTO_CMD_ERROR_FLAG_NE (SDIOC_ATCERRST_NE) /*!< Auto CMD12 Not Executed status */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Auto_CMD_Error SDIOC Force Auto CMD Error + * @{ + */ +#define SDIOC_FORCE_AUTO_CMD_ERROR_FCMDE (SDIOC_FEA_FCMDE) /*!< Force Event for Command Not Issued By Auto CMD12 Error */ +#define SDIOC_FORCE_AUTO_CMD_ERROR_FIE (SDIOC_FEA_FIE) /*!< Force Event for Auto CMD12 Index Error */ +#define SDIOC_FORCE_AUTO_CMD_ERROR_FEBE (SDIOC_FEA_FEBE) /*!< Force Event for Auto CMD12 End Bit Error */ +#define SDIOC_FORCE_AUTO_CMD_ERROR_FCE (SDIOC_FEA_FCE) /*!< Force Event for Auto CMD12 CRC Error */ +#define SDIOC_FORCE_AUTO_CMD_ERROR_FTOE (SDIOC_FEA_FTOE) /*!< Force Event for Auto CMD12 Timeout Error */ +#define SDIOC_FORCE_AUTO_CMD_ERROR_FNE (SDIOC_FEA_FNE) /*!< Force Event for Auto CMD12 Not Executed */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Force_Error_Interrupt SDIOC Force Error Interrupt + * @{ + */ +#define SDIOC_FORCE_ERROR_INT_FACE (SDIOC_FEE_FACE) /*!< Force Event for Auto CMD12 Error */ +#define SDIOC_FORCE_ERROR_INT_FDEBE (SDIOC_FEE_FDEBE) /*!< Force Event for Data End Bit Error */ +#define SDIOC_FORCE_ERROR_INT_FDCE (SDIOC_FEE_FDCE) /*!< Force Event for Data CRC Error */ +#define SDIOC_FORCE_ERROR_INT_FDTOE (SDIOC_FEE_FDTOE) /*!< Force Event for Data Timeout Error */ +#define SDIOC_FORCE_ERROR_INT_FCIE (SDIOC_FEE_FCIE) /*!< Force Event for Command Index Error */ +#define SDIOC_FORCE_ERROR_INT_FCEBE (SDIOC_FEE_FCEBE) /*!< Force Event for Command End Bit Error */ +#define SDIOC_FORCE_ERROR_INT_FCCE (SDIOC_FEE_FCCE) /*!< Force Event for Command CRC Error */ +#define SDIOC_FORCE_ERROR_INT_FCTOE (SDIOC_FEE_FCTOE) /*!< Force Event for Command Timeout Error */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Response_Type SDIOC Response Type + * @{ + */ +#define SDIOC_RESOPNE_TYPE_NO (0x00U) /*!< No Response */ +#define SDIOC_RESOPNE_TYPE_R2 (SDIOC_CMD_RESTYP_0 | SDIOC_CMD_CCE) /*!< Command Response 2 */ +#define SDIOC_RESOPNE_TYPE_R3_R4 (SDIOC_CMD_RESTYP_1) /*!< Command Response 3, 4 */ +#define SDIOC_RESOPNE_TYPE_R1_R5_R6_R7 (SDIOC_CMD_RESTYP_1 | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1, 5, 6, 7 */ +#define SDIOC_RESOPNE_TYPE_R1B_R5B (SDIOC_CMD_RESTYP | SDIOC_CMD_ICE | SDIOC_CMD_CCE) /*!< Command Response 1 and 5 with busy */ +/** + * @} + */ + +/** + * @defgroup SDIOC_Commands_Index SDIOC Commands Index + * @{ + */ +#define SDIOC_CMD0_GO_IDLE_STATE (0U) /*!< Resets the SD memory card. */ +#define SDIOC_CMD1_SEND_OP_COND (1U) /*!< Sends host capacity support information and activates the card's initialization process. */ +#define SDIOC_CMD2_ALL_SEND_CID (2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */ +#define SDIOC_CMD3_SEND_RELATIVE_ADDR (3U) /*!< Asks the card to publish a new relative address (RCA). */ +#define SDIOC_CMD4_SET_DSR (4U) /*!< Programs the DSR of all cards. */ +#define SDIOC_CMD5_IO_SEND_OP_COND (5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its \ + operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_CMD6_SWITCH_FUNC (6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */ +#define SDIOC_CMD7_SELECT_DESELECT_CARD (7U) /*!< Selects the card by its own relative address and gets deselected by any other address */ +#define SDIOC_CMD8_SEND_IF_COND (8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information \ + and asks the card whether card supports voltage. */ +#define SDIOC_CMD9_SEND_CSD (9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */ +#define SDIOC_CMD10_SEND_CID (10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */ +#define SDIOC_CMD11_READ_DAT_UNTIL_STOP (11U) /*!< SD card doesn't support it. */ +#define SDIOC_CMD12_STOP_TRANSMISSION (12U) /*!< Forces the card to stop transmission. */ +#define SDIOC_CMD13_SEND_STATUS (13U) /*!< Addressed card sends its status register. */ +#define SDIOC_CMD14_HS_BUSTEST_READ (14U) /*!< Reserved */ +#define SDIOC_CMD15_GO_INACTIVE_STATE (15U) /*!< Sends an addressed card into the inactive state. */ +#define SDIOC_CMD16_SET_BLOCKLEN (16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands(read, write). \ + Default block length is fixed to 512 Bytes. Not effective for SDHS and SDXC. */ +#define SDIOC_CMD17_READ_SINGLE_BLOCK (17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed \ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD18_READ_MULTIPLE_BLOCK (18U) /*!< Continuously transfers data blocks from card to host until interrupted by \ + STOP_TRANSMISSION command. */ +#define SDIOC_CMD19_HS_BUSTEST_WRITE (19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */ +#define SDIOC_CMD20_WRITE_DAT_UNTIL_STOP (20U) /*!< Speed class control command. */ +#define SDIOC_CMD23_SET_BLOCK_COUNT (23U) /*!< Specify block count for CMD18 and CMD25. */ +#define SDIOC_CMD24_WRITE_SINGLE_BLOCK (24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of fixed\ + 512 bytes in case of SDHC and SDXC. */ +#define SDIOC_CMD25_WRITE_MULTIPLE_BLOCK (25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */ +#define SDIOC_CMD26_PROGRAM_CID (26U) /*!< Reserved for manufacturers. */ +#define SDIOC_CMD27_PROGRAM_CSD (27U) /*!< Programming of the programmable bits of the CSD. */ +#define SDIOC_CMD28_SET_WRITE_PROT (28U) /*!< Sets the write protection bit of the addressed group. */ +#define SDIOC_CMD29_CLR_WRITE_PROT (29U) /*!< Clears the write protection bit of the addressed group. */ +#define SDIOC_CMD30_SEND_WRITE_PROT (30U) /*!< Asks the card to send the status of the write protection bits. */ +#define SDIOC_CMD32_ERASE_WR_BLK_START (32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */ +#define SDIOC_CMD33_ERASE_WR_BLK_END (33U) /*!< Sets the address of the last write block of the continuous range to be erased. */ +#define SDIOC_CMD35_ERASE_GRP_START (35U) /*!< Sets the address of the first write block to be erased. Reserved for each command system \ + set by switch function command (CMD6). */ +#define SDIOC_CMD36_ERASE_GRP_END (36U) /*!< Sets the address of the last write block of the continuous range to be erased. \ + Reserved for each command system set by switch function command (CMD6). */ +#define SDIOC_CMD38_ERASE (38U) /*!< Reserved for SD security applications. */ +#define SDIOC_CMD39_FAST_IO (39U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD40_GO_IRQ_STATE (40U) /*!< SD card doesn't support it (Reserved). */ +#define SDIOC_CMD42_LOCK_UNLOCK (42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by \ + the SET_BLOCK_LEN command. */ +#define SDIOC_CMD55_APP_CMD (55U) /*!< Indicates to the card that the next command is an application specific command rather \ + than a standard command. */ +#define SDIOC_CMD56_GEN_CMD (56U) /*!< Used either to transfer a data block to the card or to get a data block from the card \ + for general purpose/application specific commands. */ +#define SDIOC_CMD64_NO_CMD (64U) /*!< No command */ + +/** + * @brief Following commands are SD Card Specific commands. + * CMD55_APP_CMD should be sent before sending these commands. + */ +#define SDIOC_ACMD6_SET_BUS_WIDTH (6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus \ + widths are given in SCR register. */ +#define SDIOC_ACMD13_SD_STATUS (13U) /*!< (ACMD13) Sends the SD status. */ +#define SDIOC_ACMD22_SEND_NUM_WR_BLOCKS (22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with \ + 32bit+CRC data block. */ +#define SDIOC_ACMD41_SD_APP_OP_COND (41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to \ + send its operating condition register (OCR) content in the response on the CMD line. */ +#define SDIOC_ACMD42_SET_CLR_CARD_DETECT (42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */ +#define SDIOC_ACMD51_SEND_SCR (51U) /*!< Reads the SD Configuration Register (SCR). */ +#define SDIOC_ACMD52_RW_DIRECT (52U) /*!< For SD I/O card only, reserved for security specification. */ +#define SDIOC_ACMD53_RW_EXTENDED (53U) /*!< For SD I/O card only, reserved for security specification. */ + +/** + * @brief Following commands are SD Card Specific security commands. + * CMD55_APP_CMD should be sent before sending these commands. + */ +#define SDIOC_ACMD43_GET_MKB (43U) +#define SDIOC_ACMD44_GET_MID (44U) +#define SDIOC_ACMD45_SET_CER_RN1 (45U) +#define SDIOC_ACMD46_GET_CER_RN2 (46U) +#define SDIOC_ACMD47_SET_CER_RES2 (47U) +#define SDIOC_ACMD48_GET_CER_RES1 (48U) +#define SDIOC_ACMD18_SECURE_READ_MULTIPLE_BLOCK (18U) +#define SDIOC_ACMD25_SECURE_WRITE_MULTIPLE_BLOCK (25U) +#define SDIOC_ACMD38_SECURE_ERASE (38U) +#define SDIOC_ACMD49_CHANGE_SECURE_AREA (49U) +#define SDIOC_ACMD48_SECURE_WRITE_MKB (48U) +/** + * @} + */ + +/** + * @defgroup SDMMC_Error_Code SDMMC Error Code + * @{ + */ +#define SDMMC_ERROR_NONE (0x00000000UL) /*!< No error */ +#define SDMMC_ERROR_ADDR_OUT_OF_RANGE (0x80000000UL) /*!< Error when addressed block is out of range */ +#define SDMMC_ERROR_ADDR_MISALIGNED (0x40000000UL) /*!< Misaligned address */ +#define SDMMC_ERROR_BLOCK_LEN_ERR (0x20000000UL) /*!< Transferred block length is not allowed for the card or the \ + number of transferred bytes does not match the block length */ +#define SDMMC_ERROR_ERASE_SEQ_ERR (0x10000000UL) /*!< An error in the sequence of erase command occurs */ +#define SDMMC_ERROR_BAD_ERASE_PARAM (0x08000000UL) /*!< An invalid selection for erase groups */ +#define SDMMC_ERROR_WRITE_PROT_VIOLATION (0x04000000UL) /*!< Attempt to program a write protect block */ +#define SDMMC_ERROR_LOCK_UNLOCK_FAILED (0x01000000UL) /*!< Sequence or password error has been detected in unlock command \ + or if there was an attempt to access a locked card */ +#define SDMMC_ERROR_COM_CRC_FAILED (0x00800000UL) /*!< CRC check of the previous command failed */ +#define SDMMC_ERROR_ILLEGAL_CMD (0x00400000UL) /*!< Command is not legal for the card state */ +#define SDMMC_ERROR_CARD_ECC_FAILED (0x00200000UL) /*!< Card internal ECC was applied but failed to correct the data */ +#define SDMMC_ERROR_CC_ERR (0x00100000UL) /*!< Internal card controller error */ +#define SDMMC_ERROR_GENERAL_UNKNOWN_ERR (0x00080000UL) /*!< General or unknown error */ +#define SDMMC_ERROR_STREAM_READ_UNDERRUN (0x00040000UL) /*!< The card could not sustain data reading in stream rmode */ +#define SDMMC_ERROR_STREAM_WRITE_OVERRUN (0x00020000UL) /*!< The card could not sustain data programming in stream mode */ +#define SDMMC_ERROR_CID_CSD_OVERWRITE (0x00010000UL) /*!< CID/CSD overwrite error */ +#define SDMMC_ERROR_WP_ERASE_SKIP (0x00008000UL) /*!< Only partial address space was erased */ +#define SDMMC_ERROR_CARD_ECC_DISABLED (0x00004000UL) /*!< Command has been executed without using internal ECC */ +#define SDMMC_ERROR_ERASE_RESET (0x00002000UL) /*!< Erase sequence was cleared before executing because an out of \ + erase sequence command was received */ +#define SDMMC_ERROR_CMD_AUTO_SEND (0x00001000UL) /*!< An error occurred in sending the command automatically */ +#define SDMMC_ERROR_CMD_INDEX (0x00000800UL) /*!< The received response contains a command number error */ +#define SDMMC_ERROR_CMD_STOP_BIT (0x00000400UL) /*!< Command line detects low level at stop bit */ +#define SDMMC_ERROR_CMD_CRC_FAIL (0x00000200UL) /*!< Command response received (but CRC check failed) */ +#define SDMMC_ERROR_CMD_TIMEOUT (0x00000100UL) /*!< Command response timeout */ +#define SDMMC_ERROR_SWITCH_ERROR (0x00000080UL) /*!< The card did not switch to the expected mode as requested by \ + the SWITCH command */ +#define SDMMC_ERROR_DATA_STOP_BIT (0x00000040UL) /*!< Data line detects low level at stop bit */ +#define SDMMC_ERROR_DATA_CRC_FAIL (0x00000020UL) /*!< Data block sent/received (CRC check failed) */ +#define SDMMC_ERROR_DATA_TIMEOUT (0x00000010UL) /*!< Data timeout */ +#define SDMMC_ERROR_AKE_SEQ_ERR (0x00000008UL) /*!< Error in sequence of authentication */ +#define SDMMC_ERROR_INVALID_VOLTRANGE (0x00000004UL) /*!< Error in case of invalid voltage range */ +#define SDMMC_ERROR_REQUEST_NOT_APPLICABLE (0x00000002UL) /*!< Error when command request is not applicable */ +#define SDMMC_ERROR_UNSUPPORTED_FEATURE (0x00000001UL) /*!< Error when feature is not insupported */ + +#define SDMMC_CARD_ERROR_BITS_MASK (0xFDFFE048UL) /*!< SD/MMC Error status bits mask */ +/** + * @} + */ + +/** + * @defgroup SDMMC_Card_Status_Bit SDMMC Card Status Bit + * @{ + */ +#define SDMMC_STATUS_CARD_IS_LOCKED_POS (24U) +#define SDMMC_STATUS_CARD_IS_LOCKED (0x02000000UL) /*!< When set, signals that the card is locked by the host */ +#define SDMMC_STATUS_CURRENT_STATE_POS (9U) +#define SDMMC_STATUS_CURRENT_STATE (0x00001E00UL) /*!< The state of the card when receiving the command */ +#define SDMMC_STATUS_READY_FOR_DATA_POS (8U) +#define SDMMC_STATUS_READY_FOR_DATA (0x00000100UL) /*!< Corresponds to buffer empty signaling on the bus */ +#define SDMMC_STATUS_APP_CMD_POS (5U) +#define SDMMC_STATUS_APP_CMD (0x00000020UL) /*!< The card will expect ACMD, or an indication that the command has been interpreted as ACMD */ +/** + * @} + */ + +/** + * @defgroup SDMMC_SCR_Register SDMMC SCR Register + * @{ + */ +#define SDMMC_SCR_PHY_SPEC_VER_1P0 (0x00000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_1P1 (0x01000000UL) +#define SDMMC_SCR_PHY_SPEC_VER_2P0 (0x02000000UL) +#define SDMMC_SCR_BUS_WIDTH_4BIT (0x00040000UL) +#define SDMMC_SCR_BUS_WIDTH_1BIT (0x00010000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_OCR_Register SDMMC OCR Register + * @{ + */ +#define SDMMC_OCR_HIGH_CAPACITY (0x40000000UL) +#define SDMMC_OCR_STD_CAPACITY (0x00000000UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_CSD_Register SDMMC CSD Register + * @{ + */ +/* Command Class supported */ +#define SDMMC_CSD_SUPPORT_CLASS5_ERASE (0x00000020UL) +/** + * @} + */ + +/** + * @defgroup SDMMC_Common_Parameter SDMMC Common Parameter + * @{ + */ +#define SDMMC_DATA_TIMEOUT (0x0000FFFFUL) +#define SDMMC_MAX_VOLTAGE_TRIAL (0x0000FFFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SDIOC_Global_Functions + * @{ + */ +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx); +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit); +en_result_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit); +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8ResetType); +void SDIOC_PowerCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta); +en_functional_state_t SDIOC_GetPowerState(const M4_SDIOC_TypeDef *SDIOCx); +uint32_t SDIOC_GetMode(const M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_ClockCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta); +void SDIOC_SetClockDiv(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16ClkDiv); +en_result_t SDIOC_GetOptimumClockDiv(uint32_t u32ClkFreq, uint16_t *pu16ClkDiv); +en_result_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClkDiv); +en_functional_state_t SDIOC_GetDeviceInsertState(const M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode); +void SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth); +void SDIOC_SetCardDetectSource(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8Src); +void SDIOC_SetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8Level); + +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_init_t *pstcCmd); +en_result_t SDIOC_CmdStructInit(stc_sdioc_cmd_init_t *pstcCmd); +en_result_t SDIOC_GetResponse(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8RespReg, uint32_t *pu32RespVal); +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_init_t *pstcData); +en_result_t SDIOC_DataStructInit(stc_sdioc_data_init_t *pstcData); +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len); +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len); + +void SDIOC_BlockGapStopCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta); +void SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx); +void SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta); +void SDIOC_BlockGapInterruptCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta); + +void SDIOC_IntCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc, en_functional_state_t enNewSta); +en_functional_state_t SDIOC_GetIntEnableState(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc); +en_flag_status_t SDIOC_GetIntStatus(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +void SDIOC_ClearIntStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +void SDIOC_IntStatusCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc, en_functional_state_t enNewSta); +en_flag_status_t SDIOC_GetHostStatus(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag); +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const M4_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag); +void SDIOC_ForceAutoCmdErrorEvent(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16CmdFlag); +void SDIOC_ForceErrorInterruptEvent(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16IntFlag); + +/* SDMMC Commands management functions */ +en_result_t SDMMC_CMD0_GoIdleState(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD2_AllSendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD3_SendRelativeAddr(M4_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD6_SwitchFunc(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD7_SelectDeselectCard(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD8_SendInterfaceCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD9_SendCSD(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD12_StopTransmission(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD16_SetBlockLength(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD17_ReadSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD18_ReadMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD24_WriteSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD25_WriteMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD32_EraseBlockStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD33_EraseBlockEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD38_Erase(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD55_AppCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta); + +en_result_t SDMMC_ACMD6_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrSta); +en_result_t SDMMC_ACMD13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +en_result_t SDMMC_ACMD41_SendOperatCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta); +en_result_t SDMMC_ACMD51_SendSCR(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); + +en_result_t SDMMC_CMD1_SendOperatCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD35_EraseGroupStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrSta); +en_result_t SDMMC_CMD36_EraseGroupEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrSta); + +/** + * @} + */ + +#endif /* DDL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_SDIOC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_smc.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_smc.h new file mode 100644 index 0000000000000000000000000000000000000000..d6f4013aee5fecc84dfb825fcf19e7d23122d843 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_smc.h @@ -0,0 +1,379 @@ +/** + ******************************************************************************* + * @file hc32f4a0_smc.h + * @brief This file contains all the functions prototypes of the EXMC SMC + * (External Memory Controller: Static Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-14 Hongjh Merge API from EXMC_SMC_Enable/Disable to EXMC_SMC_Cmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_SMC_H__ +#define __HC32F4A0_SMC_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_EXMC_SMC + * @{ + */ + +#if (DDL_SMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Types Static Memory Controller Global Types + * @{ + */ + +/** + * @brief EXMC SMC Chip Configuration Structure definition + */ +typedef struct +{ + uint32_t u32ReadMode; /*!< Defines the read sync enable. + This parameter can be a value of @ref EXMC_SMC_Memory_Read_Mode */ + + uint32_t u32WriteMode; /*!< Defines the write sync enable. + This parameter can be a value of @ref EXMC_SMC_Memory_Write_Mode */ + + uint32_t u32ReadBurstLen; /*!< Defines the number of read data access. + This parameter can be a value of @ref EXMC_SMC_Memory_Read_Burst_Length. */ + + uint32_t u32WriteBurstLen; /*!< Defines the number of write data access. + This parameter can be a value of @ref EXMC_SMC_Memory_Write_Burst_Length. */ + + uint32_t u32SmcMemWidth; /*!< Defines the SMC memory width. + This parameter can be a value of @ref EXMC_SMC_Memory_Width. */ + + uint32_t u32BAA; /*!< Defines the SMC BAA signal enable. + This parameter can be a value of @ref EXMC_SMC_BAA_Port_Selection. */ + + uint32_t u32ADV; /*!< Defines the SMC ADVS signal enable. + This parameter can be a value of @ref EXMC_SMC_ADV_Port_Selection. */ + + uint32_t u32BLS; /*!< Defines the SMC BLS signal selection. + This parameter can be a value of @ref EXMC_SMC_BLS_Synchronization_Selection. */ + + uint32_t u32AddressMask; /*!< Defines the address mask. + This parameter can be a value between Min_Data = 0 and Max_Data = 0xFF */ + + uint32_t u32AddressMatch; /*!< Defines the address match. + This parameter can be a value between Min_Data = 0x60 and Max_Data = 0x7F */ +}stc_exmc_smc_chip_cfg_t; + +/** + * @brief EXMC SMC Timing Configuration Structure definition + */ +typedef struct +{ + uint32_t u32RC; /*!< Defines the RC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + + uint32_t u32WC; /*!< Defines the WC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 0x0F */ + + uint32_t u32CEOE; /*!< Defines the CEOE in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t u32WP; /*!< Defines the WP in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t u32PC; /*!< Defines the PC in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ + + uint32_t u32TR; /*!< Defines the TR in memory clock cycles. + This parameter can be a value between Min_Data = 0 and Max_Data = 7 */ +} stc_exmc_smc_timing_cfg_t; + +/** + * @brief EXMC SMC Initialization Structure definition + */ +typedef struct +{ + stc_exmc_smc_chip_cfg_t stcChipCfg; /*!< SMC memory chip configure. + This structure details refer @ref stc_exmc_smc_chip_cfg_t. */ + + stc_exmc_smc_timing_cfg_t stcTimingCfg; /*!< SMC memory timing configure. + This structure details refer @ref stc_exmc_smc_timing_cfg_t. */ +} stc_exmc_smc_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Macros Static Memory Controller Global Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Chip EXMC SMC Chip + * @{ + */ +#define EXMC_SMC_CHIP_0 (0UL) /*!< Chip 0 */ +#define EXMC_SMC_CHIP_1 (1UL) /*!< Chip 1 */ +#define EXMC_SMC_CHIP_2 (2UL) /*!< Chip 2 */ +#define EXMC_SMC_CHIP_3 (3UL) /*!< Chip 3 */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Read_Mode EXMC SMC Memory Read Mode + * @{ + */ +#define EXMC_SMC_MEM_READ_ASYNC (0UL) +#define EXMC_SMC_MEM_READ_SYNC (SMC_CPCR_RSYN) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Write_Mode EXMC SMC Memory Write Mode + * @{ + */ +#define EXMC_SMC_MEM_WRITE_ASYNC (0UL) +#define EXMC_SMC_MEM_WRITE_SYNC (SMC_CPCR_WSYN) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Read_Burst_Length EXMC SMC Memory Read Burst Length + * @{ + */ +#define EXMC_SMC_MEM_READ_BURST_1 (0UL) /*!< 1 beat */ +#define EXMC_SMC_MEM_READ_BURST_4 (SMC_CPCR_RBL_0) /*!< 4 beats */ +#define EXMC_SMC_MEM_READ_BURST_8 (SMC_CPCR_RBL_1) /*!< 8 beats */ +#define EXMC_SMC_MEM_READ_BURST_16 (SMC_CPCR_RBL_1 | \ + SMC_CPCR_RBL_0) /*!< 16 beats */ +#define EXMC_SMC_MEM_READ_BURST_32 (SMC_CPCR_RBL_2) /*!< 32 beats */ +#define EXMC_SMC_MEM_READ_BURST_CONTINUOUS (SMC_CPCR_RBL_2 | \ + SMC_CPCR_RBL_0) /*!< continuous */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Write_Burst_Length EXMC SMC Memory Write Burst Length + * @{ + */ +#define EXMC_SMC_MEM_WRITE_BURST_1 (0UL) /*!< 1 beat */ +#define EXMC_SMC_MEM_WRITE_BURST_4 (SMC_CPCR_WBL_0) /*!< 4 beats */ +#define EXMC_SMC_MEM_WRITE_BURST_8 (SMC_CPCR_WBL_1) /*!< 8 beats */ +#define EXMC_SMC_MEM_WRITE_BURST_16 (SMC_CPCR_WBL_1 | \ + SMC_CPCR_WBL_0) /*!< 16 beats */ +#define EXMC_SMC_MEM_WRITE_BURST_32 (SMC_CPCR_WBL_2) /*!< 32 beats */ +#define EXMC_SMC_MEM_WRITE_BURST_CONTINUOUS (SMC_CPCR_WBL_2 | \ + SMC_CPCR_WBL_0) /*!< continuous */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Memory_Width EXMC SMC Memory Width + * @{ + */ +#define EXMC_SMC_MEMORY_WIDTH_16BIT (SMC_CPCR_MW_0) +#define EXMC_SMC_MEMORY_WIDTH_32BIT (SMC_CPCR_MW_1) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_BAA_Port_Selection EXMC SMC BAA Port Selection + * @{ + */ +#define EXMC_SMC_BAA_PORT_DISABLE (0UL) +#define EXMC_SMC_BAA_PORT_ENABLE (SMC_CPCR_BAAS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_ADV_Port_Selection EXMC SMC ADV Port Selection + * @{ + */ +#define EXMC_SMC_ADV_PORT_DISABLE (0UL) +#define EXMC_SMC_ADV_PORT_ENABLE (SMC_CPCR_ADVS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_BLS_Synchronization_Selection EXMC SMC BLS Synchronization Selection + * @{ + */ +#define EXMC_SMC_BLS_SYNC_CS (0UL) +#define EXMC_SMC_BLS_SYNC_WE (SMC_CPCR_BLSS) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Command EXMC SMC Command + * @{ + */ +#define EXMC_SMC_CMD_MDREGCONFIG (SMC_CMDR_CMD_0) /*!< Command: MdRetConfig */ +#define EXMC_SMC_CMD_UPDATEREGS (SMC_CMDR_CMD_1) /*!< Command: UpdateRegs */ +#define EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS (SMC_CMDR_CMD) /*!< Command: MdRetConfig & UpdateRegs */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_CRE_Polarity EXMC SMC CRE Polarity + * @{ + */ +#define EXMC_SMC_CRE_POLARITY_LOW (0UL) /*!< CRE is LOW */ +#define EXMC_SMC_CRE_POLARITY_HIGH (SMC_CMDR_CRES) /*!< CRE is HIGH when ModeReg write occurs */ +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Status EXMC SMC Status + * @{ + */ +#define EXMC_SMC_READY (0UL) /*!< SMC is ready */ +#define EXMC_SMC_LOWPOWER (SMC_STSR_STATUS) /*!< SMC is low power */ +/** + * @} + */ + +/** + * @brief SMC device memory address shifting. + * @param [in] mem_base_address SMC base address + * @param [in] mem_width SMC memory width + * @param [in] address SMC device memory address + * @retval SMC device shifted address value + */ +#define SMC_ADDR_SHIFT(mem_base_address, mem_width, address) \ +( ((EXMC_SMC_MEMORY_WIDTH_16BIT == (mem_width))? (((mem_base_address) + ((address) << 1UL))):\ + (((mem_base_address) + ((address) << 2UL))))) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup EXMC_SMC_Global_Functions + * @{ + */ + +/** + * @brief SMC entry low power state + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_SMC_EntryLowPower(void) +{ + WRITE_REG32(M4_SMC->STCR0, SMC_STCR0_LPWIR); +} + +/** + * @brief SMC exit low power state + * @param None + * @retval None + */ +__STATIC_INLINE void EXMC_SMC_ExitLowPower(void) +{ + WRITE_REG32(M4_SMC->STCR1, SMC_STCR1_LPWOR); +} + +/** + * @brief Get SMC status + * @param None + * @retval Returned value can be one of the following values: + * @arg EXMC_SMC_READY: SMC is ready + * @arg EXMC_SMC_LOWPOWER: SMC is low power + */ +__STATIC_INLINE uint32_t EXMC_SMC_GetStatus(void) +{ + return READ_REG32_BIT(M4_SMC->STSR, SMC_STSR_STATUS); +} + +/* Initialization and configuration EXMC SMC functions */ +en_result_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcInit); +void EXMC_SMC_DeInit(void); +en_result_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcInit); + +void EXMC_SMC_Cmd(en_functional_state_t enNewState); +void EXMC_SMC_SetCommand(uint32_t u32Chip, + uint32_t u32Cmd, + uint32_t u32CrePolarity, + uint32_t u32Address); + +uint32_t EXMC_SMC_ChipStartAddress(uint32_t u32Chip); +uint32_t EXMC_SMC_ChipEndAddress(uint32_t u32Chip); + +en_result_t EXMC_SMC_CheckChipStatus(uint32_t u32Chip, + const stc_exmc_smc_chip_cfg_t *pstcChipCfg); +en_result_t EXMC_SMC_CheckTimingStatus(uint32_t u32Chip, + const stc_exmc_smc_timing_cfg_t *pstcTimingCfg); + +void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState); +void EXMC_SMC_SetRefreshPeriod(uint32_t u32PeriodVal); + +/** + * @} + */ + +#endif /* DDL_SMC_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_SMC_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_spi.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..2e372bb3ec510b812ce3090d41bc71fb894809cf --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_spi.h @@ -0,0 +1,446 @@ +/** + ******************************************************************************* + * @file hc32f4a0_spi.h + * @brief This file contains all the functions prototypes of the SPI driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_SPI_H__ +#define __HC32F4A0_SPI_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_SPI + * @{ + */ + +#if (DDL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Types SPI Global Types + * @{ + */ + +/** + * @brief Structure definition of SPI initialization. + */ +typedef struct +{ + uint32_t u32WireMode; /*!< SPI wire mode, 3 wire mode or 4 wire mode. + This parameter can be a value of @ref SPI_Wire_Mode_Define */ + uint32_t u32TransMode; /*!< SPI transfer mode, send only or full duplex. + This parameter can be a value of @ref SPI_Transfer_Mode_Define */ + uint32_t u32MasterSlave; /*!< SPI master/slave mode. + This parameter can be a value of @ref SPI_Master_Slave_Mode_Define */ + uint32_t u32SuspMode; /*!< SPI communication suspend function. + This parameter can be a value of @ref SPI_Communication_Suspend_Function_Define */ + uint32_t u32Modfe; /*!< SPI mode fault detect command. + This parameter can be a value of @ref SPI_Mode_Fault_Dectet_Command_Define */ + uint32_t u32Parity; /*!< SPI parity check selection. + This parameter can be a value of @ref SPI_Parity_Check_Define */ + uint32_t u32SpiMode; /*!< SPI mode. + This parameter can be a value of @ref SPI_Mode_Define */ + uint32_t u32BaudRatePrescaler; /*!< SPI baud rate prescaler. + This parameter can be a value of @ref SPI_Baud_Rate_Prescaler_Define */ + uint32_t u32DataBits; /*!< SPI data bits, 4 bits ~ 32 bits. + This parameter can be a value of @ref SPI_Data_Size_Define */ + uint32_t u32FirstBit; /*!< MSB first or LSB first. + This parameter can be a value of @ref SPI_First_Bit_Define */ + uint32_t u32FrameLevel; /*!< SPI frame level, SPI_FRAME_1 ~ SPI_FRAME_4. + This parameter can be a value of @ref SPI_Frame_Level_Define */ +} stc_spi_init_t; + +/** + * @brief Structure definition of SPI delay time configuration. + */ +typedef struct +{ + uint32_t u32IntervalDelay; /*!< SPI interval time delay (Next access delay time) + This parameter can be a value of @ref SPI_Interval_Delay_Time_define */ + uint32_t u32ReleaseDelay; /*!< SPI release time delay (SCK invalid delay time) + This parameter can be a value of @ref SPI_Release_Delay_Time_define */ + uint32_t u32SetupDelay; /*!< SPI Setup time delay (SCK valid delay time) define + This parameter can be a value of @ref SPI_Setup_Delay_Time_define */ +} stc_spi_delay_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Macros SPI Global Macros + * @{ + */ + +/** + * @defgroup SPI_Wire_Mode_Define SPI wire mode define + * @{ + */ +#define SPI_WIRE_4 (0UL) +#define SPI_WIRE_3 (SPI_CR1_SPIMDS) +/** + * @} + */ + +/** + * @defgroup SPI_Transfer_Mode_Define SPI transfer mode define + * @{ + */ +#define SPI_FULL_DUPLEX (0UL) /*!< Full duplex. */ +#define SPI_SEND_ONLY (SPI_CR1_TXMDS) /*!< Send only. */ +/** + * @} + */ + +/** + * @defgroup SPI_Master_Slave_Mode_Define SPI master slave mode define + * @{ + */ +#define SPI_SLAVE (0UL) +#define SPI_MASTER (SPI_CR1_MSTR) +/** + * @} + */ + +/** + * @defgroup SPI_Loopback_Selection_Define SPI loopback selection define + * @note Loopback mode is mainly used for parity self-diagnosis in 4-wire full-duplex mode. + * @{ + */ +#define SPI_SPLPBK_INVALID (0UL) +#define SPI_SPLPBK_MOSI_INVERT (SPI_CR1_SPLPBK) /*!< MISO data is the inverse of the data output by MOSI. */ +#define SPI_SPLPBK_MOSI (SPI_CR1_SPLPBK2) /*!< MISO data is the data output by MOSI. */ +/** + * @} + */ + +/** + * @defgroup SPI_Communication_Suspend_Function_Define SPI communication suspend function define + * @{ + */ +#define SPI_COM_SUSP_FUNC_OFF (0UL) +#define SPI_COM_SUSP_FUNC_ON (SPI_CR1_CSUSPE) +/** + * @} + */ + +/** + * @defgroup SPI_Interrupt_Type_Define SPI interrupt type define + * @{ + */ +#define SPI_INT_ERROR (SPI_CR1_EIE) /*!< Including overload, underload and parity error. */ +#define SPI_INT_TX_BUFFER_EMPTY (SPI_CR1_TXIE) +#define SPI_INT_RX_BUFFER_FULL (SPI_CR1_RXIE) +#define SPI_INT_IDLE (SPI_CR1_IDIE) +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Fault_Dectet_Command_Define SPI mode fault dectect command define + * @{ + */ +#define SPI_MODFE_DISABLE (0UL) /*!< Disable mode fault detection. */ +#define SPI_MODFE_ENABLE (SPI_CR1_MODFE) /*!< Enable mode fault detection. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Error_Self_Diagnosis_Define SPI parity check error self diagnosis define + * @{ + */ +#define SPI_PATE_DISABLE (0UL) /*!< Disable self diagnosis of parity check. */ +#define SPI_PATE_ENABLE (SPI_CR1_PATE) /*!< Enable self diagnosis of parity check. */ +/** + * @} + */ + +/** + * @defgroup SPI_Parity_Check_Define SPI parity check mode define + * @{ + */ +#define SPI_PARITY_INVALID (0UL) /*!< Parity check invalid. */ +#define SPI_PARITY_EVEN (SPI_CR1_PAE) /*!< Parity check selection even parity. */ +#define SPI_PARITY_ODD (SPI_CR1_PAE | SPI_CR1_PAOE) /*!< Parity check selection odd parity. */ +/** + * @} + */ + +/** + * @defgroup SPI_Interval_Delay_Time_define SPI interval time delay (Next access delay time) define + * @{ + */ +#define SPI_INTERVAL_TIME_1SCK_2PCLK1 (0UL) +#define SPI_INTERVAL_TIME_2SCK_2PCLK1 (SPI_CFG1_MIDI_0) +#define SPI_INTERVAL_TIME_3SCK_2PCLK1 (SPI_CFG1_MIDI_1) +#define SPI_INTERVAL_TIME_4SCK_2PCLK1 (SPI_CFG1_MIDI_1 | SPI_CFG1_MIDI_0) +#define SPI_INTERVAL_TIME_5SCK_2PCLK1 (SPI_CFG1_MIDI_2) +#define SPI_INTERVAL_TIME_6SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_0) +#define SPI_INTERVAL_TIME_7SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_1) +#define SPI_INTERVAL_TIME_8SCK_2PCLK1 (SPI_CFG1_MIDI_2 | SPI_CFG1_MIDI_1 | SPI_CFG1_MIDI_0) +/** + * @} + */ + +/** + * @defgroup SPI_Release_Delay_Time_define SPI release time delay (SCK invalid delay time) define + * @{ + */ +#define SPI_RELEASE_TIME_1SCK (0UL) +#define SPI_RELEASE_TIME_2SCK (SPI_CFG1_MSSDL_0) +#define SPI_RELEASE_TIME_3SCK (SPI_CFG1_MSSDL_1) +#define SPI_RELEASE_TIME_4SCK (SPI_CFG1_MSSDL_1 | SPI_CFG1_MSSDL_0) +#define SPI_RELEASE_TIME_5SCK (SPI_CFG1_MSSDL_2) +#define SPI_RELEASE_TIME_6SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_0) +#define SPI_RELEASE_TIME_7SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_1) +#define SPI_RELEASE_TIME_8SCK (SPI_CFG1_MSSDL_2 | SPI_CFG1_MSSDL_1 | SPI_CFG1_MSSDL_0) +/** + * @} + */ + +/** + * @defgroup SPI_Setup_Delay_Time_define SPI Setup time delay (SCK valid delay time) define + * @{ + */ +#define SPI_SETUP_TIME_1SCK (0UL) +#define SPI_SETUP_TIME_2SCK (SPI_CFG1_MSSI_0) +#define SPI_SETUP_TIME_3SCK (SPI_CFG1_MSSI_1) +#define SPI_SETUP_TIME_4SCK (SPI_CFG1_MSSI_1 | SPI_CFG1_MSSI_0) +#define SPI_SETUP_TIME_5SCK (SPI_CFG1_MSSI_2) +#define SPI_SETUP_TIME_6SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_0) +#define SPI_SETUP_TIME_7SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_1) +#define SPI_SETUP_TIME_8SCK (SPI_CFG1_MSSI_2 | SPI_CFG1_MSSI_1 | SPI_CFG1_MSSI_0) +/** + * @} + */ + +/** + * @defgroup SPI_SS_Pin_Define SPI SSx define + * @{ + */ +#define SPI_PIN_SS0 (SPI_CFG1_SS0PV) +#define SPI_PIN_SS1 (SPI_CFG1_SS1PV) +#define SPI_PIN_SS2 (SPI_CFG1_SS2PV) +#define SPI_PIN_SS3 (SPI_CFG1_SS3PV) +/** + * @} + */ + +/** + * @defgroup SPI_SS_Active_Level_Define SPI SSx Active Level define + * @{ + */ +#define SPI_SS_ACTIVE_LOW (0UL) /*!< SS pin active low. */ +#define SPI_SS_ACTIVE_HIGH (1UL) /*!< SS pin active high. */ +/** + * @} + */ + +/** + * @defgroup SPI_Read_Target_Buffer_Define SPI read data register target buffer define + * @{ + */ +#define SPI_RD_TARGET_RD_BUF (0UL) /*!< Read RX buffer. */ +#define SPI_RD_TARGET_WR_BUF (SPI_CFG1_SPRDTD) /*!< Read TX buffer. */ +/** + * @} + */ + +/** + * @defgroup SPI_Frame_Level_Define SPI data frame level define, The Data in the + * SPI_DR register will be send to TX_BUFF after + * enough data frame write to the SPI_DR + * @{ + */ +#define SPI_FRAME_1 (0UL) /*!< Data 1 frame */ +#define SPI_FRAME_2 (SPI_CFG1_FTHLV_0) /*!< Data 2 frame.*/ +#define SPI_FRAME_3 (SPI_CFG1_FTHLV_1) /*!< Data 3 frame.*/ +#define SPI_FRAME_4 (SPI_CFG1_FTHLV_0 | SPI_CFG1_FTHLV_1) /*!< Data 4 frame.*/ +/** + * @} + */ + +/** + * @defgroup SPI_Mode_Define SPI Mode define + * @{ + */ +/* SCK pin output low in idle state; MOSI/MISO pin data valid in odd edge , MOSI/MISO pin data change in even edge */ +#define SPI_MODE_0 (0UL) +/* SCK pin output low in idle state; MOSI/MISO pin data valid in even edge , MOSI/MISO pin data change in odd edge */ +#define SPI_MODE_1 (SPI_CFG2_CPHA) +/* SCK pin output high in idle state; MOSI/MISO pin data valid in odd edge , MOSI/MISO pin data change in even edge */ +#define SPI_MODE_2 (SPI_CFG2_CPOL) +/* SCK pin output high in idle state; MOSI/MISO pin data valid in even edge , MOSI/MISO pin data change in odd edge */ +#define SPI_MODE_3 (SPI_CFG2_CPOL | SPI_CFG2_CPHA) +/** + * @} + */ + +/** + * @defgroup SPI_Baud_Rate_Prescaler_Define SPI baudrate prescaler define + * @{ + */ +#define SPI_BR_PCLK1_DIV2 (0UL) /*!< SPI baud rate is the pclk1 divided by 2. */ +#define SPI_BR_PCLK1_DIV4 (SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 4. */ +#define SPI_BR_PCLK1_DIV8 (SPI_CFG2_MBR_1) /*!< SPI baud rate is the pclk1 clock divided by 8. */ +#define SPI_BR_PCLK1_DIV16 (SPI_CFG2_MBR_1 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 16. */ +#define SPI_BR_PCLK1_DIV32 (SPI_CFG2_MBR_2) /*!< SPI baud rate is the pclk1 clock divided by 32. */ +#define SPI_BR_PCLK1_DIV64 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 clock divided by 64. */ +#define SPI_BR_PCLK1_DIV128 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_1) /*!< SPI baud rate is the pclk1 clock divided by 128. */ +#define SPI_BR_PCLK1_DIV256 (SPI_CFG2_MBR_2 | SPI_CFG2_MBR_1 | SPI_CFG2_MBR_0) /*!< SPI baud rate is the pclk1 divided by 256. */ +/** + * @} + */ + +/** + * @defgroup SPI_Data_Size_Define SPI data size define + * @{ + */ +#define SPI_DATA_SIZE_4BIT (0UL) +#define SPI_DATA_SIZE_5BIT (SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_6BIT (SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_7BIT (SPI_CFG2_DSIZE_0 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_8BIT (SPI_CFG2_DSIZE_2) +#define SPI_DATA_SIZE_9BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_10BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_11BIT (SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_12BIT (SPI_CFG2_DSIZE_3) +#define SPI_DATA_SIZE_13BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_14BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_15BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_16BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2) +#define SPI_DATA_SIZE_20BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_0) +#define SPI_DATA_SIZE_24BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1) +#define SPI_DATA_SIZE_32BIT (SPI_CFG2_DSIZE_3 | SPI_CFG2_DSIZE_2 | SPI_CFG2_DSIZE_1 | SPI_CFG2_DSIZE_0) +/** + * @} + */ + +/** + * @defgroup SPI_First_Bit_Define SPI first bit define + * @{ + */ +#define SPI_FIRST_MSB (0UL) +#define SPI_FIRST_LSB (SPI_CFG2_LSBF) +/** + * @} + */ + +/** + * @defgroup SPI_State_Flag_Define SPI state flag define + * @{ + */ +#define SPI_FLAG_OVERLOAD (SPI_SR_OVRERF) +#define SPI_FLAG_IDLE (SPI_SR_IDLNF) +#define SPI_FLAG_MODE_FAULT (SPI_SR_MODFERF) +#define SPI_FLAG_PARITY_ERROR (SPI_SR_PERF) +#define SPI_FLAG_UNDERLOAD (SPI_SR_UDRERF) +#define SPI_FLAG_TX_BUFFER_EMPTY (SPI_SR_TDEF) /*!< This flag is set when the data in the data register \ + is copied into the shift register, but the transmission \ + of the data bit may not have been completed. */ +#define SPI_FLAG_RX_BUFFER_FULL (SPI_SR_RDFF) /*!< When this flag is set, it indicates that a data was received. */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SPI_Global_Functions + * @{ + */ +en_result_t SPI_StructInit(stc_spi_init_t *pstcInit); +en_result_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayCfg); + +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcInit); +void SPI_DeInit(M4_SPI_TypeDef *SPIx); + +void SPI_IntCmd(M4_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState); +void SPI_FunctionCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState); + +void SPI_WriteDataReg(M4_SPI_TypeDef *SPIx, uint32_t u32Data); +uint32_t SPI_ReadDataReg(const M4_SPI_TypeDef *SPIx); + +en_flag_status_t SPI_GetStatus(const M4_SPI_TypeDef *SPIx, uint32_t u32Flag); +void SPI_ClearFlag(M4_SPI_TypeDef *SPIx, uint32_t u32Flag); + +void SPI_LoopbackModeCfg(M4_SPI_TypeDef *SPIx, uint32_t u32Mode); +void SPI_PateCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState); +en_result_t SPI_DelayTimeCfg(M4_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayCfg); +void SPI_SSValidLevelCfg(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState); +void SPI_SSPinSel(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin); +void SPI_ReadBufCfg(M4_SPI_TypeDef *SPIx, uint32_t u32ReadBuf); + +en_result_t SPI_Transmit(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLength); +en_result_t SPI_Receive(M4_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLength); +en_result_t SPI_TransmitReceive(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length); + +/** + * @} + */ + +#endif /* DDL_SPI_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_SPI_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_sram.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_sram.h new file mode 100644 index 0000000000000000000000000000000000000000..87d223ceb741a7fc64231a2e37364ee7097bba89 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_sram.h @@ -0,0 +1,252 @@ +/** + ******************************************************************************* + * @file hc32f4a0_sram.h + * @brief This file contains all the functions prototypes of the SRAM driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_SRAM_H__ +#define __HC32F4A0_SRAM_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_SRAM + * @{ + */ + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Macros SRAM Global Macros + * @{ + */ + +/** + * @defgroup SRAM_Index_Bit_Mask SRAM Index Bit Mask + * @{ + */ +#define SRAM_SRAMH (1UL << 2U) /*!< 0x1FFE0000~0x1FFFFFFF, 128KB */ +#define SRAM_SRAM123 (1UL << 0U) /*!< SRAM1: 0x20000000~0x2001FFFF, 128KB \ + SRAM2: 0x20020000~0x2003FFFF, 128KB \ + SRAM3: 0x20040000~0x20057FFF, 96KB */ +#define SRAM_SRAM4 (1UL << 1U) /*!< 0x20058000~0x2005FFFF, 32KB */ +#define SRAM_SRAMB (1UL << 3U) /*!< 0x200F0000~0x200F0FFF, 4KB */ +#define SRAM_SRAM_ALL (SRAM_SRAMH | SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB) +/** + * @} + */ + +/** + * @defgroup SRAM_Access_Wait_Cycle SRAM Access Wait Cycle + * @{ + */ +#define SRAM_WAIT_CYCLE_0 (0U) /*!< Wait 0 CPU cycle. */ +#define SRAM_WAIT_CYCLE_1 (1U) /*!< Wait 1 CPU cycle. */ +#define SRAM_WAIT_CYCLE_2 (2U) /*!< Wait 2 CPU cycles. */ +#define SRAM_WAIT_CYCLE_3 (3U) /*!< Wait 3 CPU cycles. */ +#define SRAM_WAIT_CYCLE_4 (4U) /*!< Wait 4 CPU cycles. */ +#define SRAM_WAIT_CYCLE_5 (5U) /*!< Wait 5 CPU cycles. */ +#define SRAM_WAIT_CYCLE_6 (6U) /*!< Wait 6 CPU cycles. */ +#define SRAM_WAIT_CYCLE_7 (7U) /*!< Wait 7 CPU cycles. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Operation_After_Check_Error SRAM Operation After Check Error + * @note For: Even-parity check error of SRAM1, SRAM2, SRAM3 and SRAMH. ECC check error of SRAM4 and SRAMB. + * @{ + */ +#define SRAM_ERR_OP_NMI (0U) /*!< Non-maskable interrupt occurres while check error occurres. */ +#define SRAM_ERR_OP_RESET (SRAMC_CKCR_PYOAD) /*!< System reset occurres while check error occurres. */ +/** + * @} + */ + +/** + * @defgroup SRAM_ECC_Mode SRAM ECC Mode + * @note For: SRAM4 and SRAMB. + * @{ + */ +#define SRAM_ECC_MODE_INVALID (0U) /*!< The ECC mode is invalid. */ +#define SRAM_ECC_MODE_1 (SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \ + ECC error corrects. \ + No 1-bit-error status flag setting, no interrupt or reset. \ + When 2-bit error occurres: \ + ECC error detects. \ + 2-bit-error status flag sets and interrupt or reset occurres. */ +#define SRAM_ECC_MODE_2 (SRAMC_CKCR_ECCMOD_1) /*!< When 1-bit error occurres: \ + ECC error corrects. \ + 1-bit-error status flag sets, no interrupt or reset. \ + When 2-bit error occurres: \ + ECC error detects. \ + 2-bit-error status flag sets and interrupt or reset occurres. */ +#define SRAM_ECC_MODE_3 (SRAMC_CKCR_ECCMOD_1 | \ + SRAMC_CKCR_ECCMOD_0) /*!< When 1-bit error occurres: \ + ECC error corrects. \ + 1-bit-error status flag sets and interrupt or reset occurres. \ + When 2-bit error occurres: \ + ECC error detects. \ + 2-bit-error status flag sets and interrupt or reset occurres. */ +/** + * @} + */ + +/** + * @defgroup SRAM_Check_Status_Flag SRAM Check Status Flag + * @{ + */ +#define SRAM_FLAG_SRAM1_PYERR (SRAMC_CKSR_SRAM1_PYERR) /*!< SRAM1 parity error. */ +#define SRAM_FLAG_SRAM2_PYERR (SRAMC_CKSR_SRAM2_PYERR) /*!< SRAM2 parity error. */ +#define SRAM_FLAG_SRAM3_PYERR (SRAMC_CKSR_SRAM3_PYERR) /*!< SRAM3 parity error. */ +#define SRAM_FLAG_SRAMH_PYERR (SRAMC_CKSR_SRAMH_PYERR) /*!< SRAMH parity error. */ +#define SRAM_FLAG_SRAM4_1ERR (SRAMC_CKSR_SRAM4_1ERR) /*!< SRAM4 ECC 1-bit error. */ +#define SRAM_FLAG_SRAM4_2ERR (SRAMC_CKSR_SRAM4_2ERR) /*!< SRAM4 ECC 2-bit error. */ +#define SRAM_FLAG_SRAMB_1ERR (SRAMC_CKSR_SRAMB_1ERR) /*!< SRAMB ECC 1-bit error. */ +#define SRAM_FLAG_SRAMB_2ERR (SRAMC_CKSR_SRAMB_2ERR) /*!< SRAMB ECC 2-bit error. */ +#define SRAM_FLAG_CACHE_PYERR (SRAMC_CKSR_CACHE_PYERR) /*!< Cache RAM parity error. */ +#define SRAM_FLAG_ALL (0x1FFUL) +/** + * @} + */ + +/** + * @defgroup SRAM_Register_Protect_Command SRAM Register Protect Command + * @{ + */ +#define SRAM_LOCK_CMD (0x76U) +#define SRAM_UNLOCK_CMD (0x77U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SRAM_Global_Functions + * @{ + */ + +/** + * @brief Lock access wait cycle control register. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_WTCR_Lock(void) +{ + WRITE_REG32(M4_SRAMC->WTPR, SRAM_LOCK_CMD); +} + +/** + * @brief Unlock access wait cycle control register. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_WTCR_Unlock(void) +{ + WRITE_REG32(M4_SRAMC->WTPR, SRAM_UNLOCK_CMD); +} + +/** + * @brief Lock check control register. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_CKCR_Lock(void) +{ + WRITE_REG32(M4_SRAMC->CKPR, SRAM_LOCK_CMD); +} + +/** + * @brief Unlock check control register. + * @param None + * @retval None + */ +__STATIC_INLINE void SRAM_CKCR_Unlock(void) +{ + WRITE_REG32(M4_SRAMC->CKPR, SRAM_UNLOCK_CMD); +} + +void SRAM_Init(void); +void SRAM_DeInit(void); + +void SRAM_WTCR_Lock(void); +void SRAM_WTCR_Unlock(void); +void SRAM_CKCR_Lock(void); +void SRAM_CKCR_Unlock(void); + +void SRAM_SetWaitCycle(uint32_t u32SramIndex, uint32_t u32WriteCycle, uint32_t u32ReadCycle); +void SRAM_SetEccMode(uint32_t u32SramIndex, uint32_t u32EccMode); +void SRAM_SetErrOperation(uint32_t u32SramIndex, uint32_t u32OpAfterError); + +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag); +void SRAM_ClrStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* DDL_SRAM_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_SRAM_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_swdt.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_swdt.h new file mode 100644 index 0000000000000000000000000000000000000000..f6d4b4f0ddeaa6e7dc6da58aac3a541c2e14ddc7 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_swdt.h @@ -0,0 +1,227 @@ +/** + ******************************************************************************* + * @file hc32f4a0_swdt.h + * @brief This file contains all the functions prototypes of the SWDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_SWDT_H__ +#define __HC32F4A0_SWDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_SWDT + * @{ + */ + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Types SWDT Global Types + * @{ + */ + +/** + * @brief SWDT Init structure definition + */ +typedef struct +{ + uint32_t u32CountCycle; /*!< Specifies the SWDT Count Cycle. + This parameter can be a value of @ref SWDT_Counter_Cycle */ + + uint32_t u32ClockDivision; /*!< Specifies the SWDT Clock Division. + This parameter can be a value of @ref SWDT_Clock_Division */ + + uint32_t u32RefreshRange; /*!< Specifies the SWDT Allow Refresh Range. + This parameter can be a value of @ref SWDT_Refresh_Percent_Range */ + + uint32_t u32LPModeCountEn; /*!< Specifies the SWDT Count Enable/Disable In Low Power Mode(Sleep/Stop Mode). + This parameter can be a value of @ref SWDT_LPW_Mode_Count */ + + uint32_t u32TrigType; /*!< Specifies the SWDT Refresh Error or Count Underflow trigger event Type. + This parameter can be a value of @ref SWDT_Trigger_Event_Type */ +} stc_swdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Macros SWDT Global Macros + * @{ + */ + +/** + * @defgroup SWDT_Counter_Cycle SWDT Counter Cycle + * @{ + */ +#define SWDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */ +#define SWDT_COUNTER_CYCLE_4096 (SWDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define SWDT_COUNTER_CYCLE_16384 (SWDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define SWDT_COUNTER_CYCLE_65536 (SWDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup SWDT_Clock_Division SWDT Clock Division + * @{ + */ +#define SWDT_CLOCK_DIV1 (0UL) /*!< SWDTCLK */ +#define SWDT_CLOCK_DIV16 (SWDT_CR_CKS_2) /*!< SWDTCLK/16 */ +#define SWDT_CLOCK_DIV32 (SWDT_CR_CKS_2 | SWDT_CR_CKS_0) /*!< SWDTCLK/32 */ +#define SWDT_CLOCK_DIV64 (SWDT_CR_CKS_2 | SWDT_CR_CKS_1) /*!< SWDTCLK/64 */ +#define SWDT_CLOCK_DIV128 (SWDT_CR_CKS_2 | SWDT_CR_CKS_1 | SWDT_CR_CKS_0) /*!< SWDTCLK/128 */ +#define SWDT_CLOCK_DIV256 (SWDT_CR_CKS_3) /*!< SWDTCLK/256 */ +#define SWDT_CLOCK_DIV2048 (SWDT_CR_CKS_3 | SWDT_CR_CKS_1 | SWDT_CR_CKS_0) /*!< SWDTCLK/2048 */ +/** + * @} + */ + +/** + * @defgroup SWDT_Refresh_Percent_Range SWDT Refresh Percent Range + * @{ + */ +#define SWDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */ +#define SWDT_RANGE_0TO25PCT (SWDT_CR_WDPT_0) /*!< 0%~25% */ +#define SWDT_RANGE_25TO50PCT (SWDT_CR_WDPT_1) /*!< 25%~50% */ +#define SWDT_RANGE_0TO50PCT (SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~50% */ +#define SWDT_RANGE_50TO75PCT (SWDT_CR_WDPT_2) /*!< 50%~75% */ +#define SWDT_RANGE_0TO25PCT_50TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_0) /*!< 0%~25% & 50%~75% */ +#define SWDT_RANGE_25TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1) /*!< 25%~75% */ +#define SWDT_RANGE_0TO75PCT (SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~75% */ +#define SWDT_RANGE_75TO100PCT (SWDT_CR_WDPT_3) /*!< 75%~100% */ +#define SWDT_RANGE_0TO25PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_0) /*!< 0%~25% & 75%~100% */ +#define SWDT_RANGE_25TO50PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_1) /*!< 25%~50% & 75%~100% */ +#define SWDT_RANGE_0TO50PCT_75TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_1 | SWDT_CR_WDPT_0) /*!< 0%~50% & 75%~100% */ +#define SWDT_RANGE_50TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2) /*!< 50%~100% */ +#define SWDT_RANGE_0TO25PCT_50TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2 | SWDT_CR_WDPT_0) /*!< 0%~25% & 50%~100% */ +#define SWDT_RANGE_25TO100PCT (SWDT_CR_WDPT_3 | SWDT_CR_WDPT_2 | SWDT_CR_WDPT_1) /*!< 25%~100% */ +/** + * @} + */ + +/** + * @defgroup SWDT_LPW_Mode_Count SWDT Low Power Mode Count + * @brief SWDT count control in the sleep/stop mode + * @{ + */ +#define SWDT_LPM_COUNT_CONTINUE (0UL) /*!< SWDT count continue in the sleep/stop mode */ +#define SWDT_LPM_COUNT_STOP (SWDT_CR_SLPOFF) /*!< SWDT count stop in the sleep/stop mode */ +/** + * @} + */ + +/** +* @defgroup SWDT_Trigger_Event_Type SWDT Trigger Event Type +* @{ +*/ +#define SWDT_TRIG_EVENT_INT (0UL) /*!< SWDT trigger interrupt */ +#define SWDT_TRIG_EVENT_RESET (SWDT_CR_ITS) /*!< SWDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup SWDT_Flag SWDT Flag + * @{ + */ +#define SWDT_FLAG_UDF (SWDT_SR_UDF) /*!< Count underflow flag */ +#define SWDT_FLAG_REF (SWDT_SR_REF) /*!< Refresh error flag */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup SWDT_Global_Functions + * @{ + */ + +/** + * @brief Get SWDT count value. + * @param None + * @retval Count value + */ +__STATIC_INLINE uint16_t SWDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(M4_SWDT->SR) & SWDT_SR_CNT); +} + +/* Initialization and configuration functions */ +en_result_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit); +void SWDT_Feed(void); +uint16_t SWDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag); +en_result_t SWDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* DDL_SWDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_SWDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmr0.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmr0.h new file mode 100644 index 0000000000000000000000000000000000000000..46c94ee1692e13124ddc3deffb9e723ca9f82b91 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmr0.h @@ -0,0 +1,243 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmr0.h + * @brief This file contains all the functions prototypes of the TMR0 driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_TMR0_H__ +#define __HC32F4A0_TMR0_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_TMR0 + * @{ + */ + +#if (DDL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Types TMR0 Global Types + * @{ + */ + +/** + * @brief Tmr0 base counter function init structrue definition + */ +typedef struct +{ + uint32_t u32ClockDivision; /*!< Specifies the TMR0 clock division, + and this parameter can be a value of + @ref TMR0_Clock_Division_define */ + + uint32_t u32ClockSource; /*!< Specifies the TMR0 clock source, + and this parameter can be a value of + @ref TMR0_Clock_Source_define*/ + + uint32_t u32Tmr0Func; /*!< Specifies the TMR0 function, + compare output or capture input + @ref TMR0_Function_define */ + + uint32_t u32HwTrigFunc; /*!< Specifies the TMR0 compare + function hardware trigger function, and + this parameter can be a value of @ref + TMR0_HardwareTrigger_Func_define */ + + uint16_t u16CmpValue; /*!< Specifies the TMR0 compare value + This value can be set 0-0xFFFF */ + + uint16_t u16CntValue; /*!< Specifies the TMR0 count value + This value can be set 0-0xFFFF */ +}stc_tmr0_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Global_Macros TMR0 Global Macros + * @{ + */ + +/** @defgroup TMR0_Clock_Division_define TMR0 clock division define + * @{ + */ +#define TMR0_CLK_DIV1 (0UL<_OxH port output mode + This parameter can be a value of @ref TMR4_PWM_Port_Output_Mode */ + + uint32_t u32EmbOxHPortState; /*!< TIM4__OxH port state + This parameter can be a value of @ref TMR4_PWM_EMB_Port_State */ + + uint32_t u32OxLPortOutMode; /*!< TIM4__OxL port output mode + This parameter can be a value of @ref TMR4_PWM_Port_Output_Mode */ + + uint32_t u32EmbOxLPortState; /*!< TIM4__OxL port state + This parameter can be a value of @ref TMR4_PWM_EMB_Port_State */ +} stc_tmr4_pwm_init_t; + +/** + * @brief TMR4 Special-EVT initialization configuration + */ +typedef struct +{ + uint16_t u16CompareVal; /*!< TMR4 Special-EVT compare match value. + This parameter can be a value of half-word */ + + uint16_t u16Mode; /*!< Configure TMR4 Special-EVT Running mode + This parameter can be a value of @ref TMR4_SEVT_Mode */ + + uint16_t u16OutpuEvent; /*!< TMR4 Special-EVT output event + This parameter can be a value of @ref TMR4_SEVT_Output_Event */ + + uint16_t u16BufMode; /*!< Buffer mode + This parameter can be a value of @ref TMR4_SEVT_Buffer_Mode */ + + uint16_t u16LinkTransfer; /*!< Enable or disable the buffer linked transfer with the CNT interrupt mask counter + This parameter can be a value of @ref TMR4_SEVT_Link_Transfer */ + + uint16_t u16UpMatchCmd; /*!< Enable or disable trigger signal when match with SCCR&SCMR and TMR4 CNT count up + This parameter can be a value of @ref TMR4_SEVT_Up_Selection */ + + uint16_t u16DownMatchCmd; /*!< Enable or disable trigger signal when match with SCCR&SCMR and TMR4 CNT count down + This parameter can be a value of @ref TMR4_SEVT_Down_Selection */ + + uint16_t u16PeakMatchCmd; /*!< Enable or disable trigger signal when match with SCCR&SCMR and TMR4 CNT count peak + This parameter can be a value of @ref TMR4_SEVT_Peak_Selection */ + + uint16_t u16ZeroMatchCmd; /*!< Enable or disable trigger signal when match with SCCR&SCMR and TMR4 CNT count zero + This parameter can be a value of @ref TMR4_SEVT_Zero_Selection */ + + uint16_t u16ZeroMatchMaskCmd; /*!< Enable or disable perform to compare with the CNT zero interrupt mask counter + This parameter can be a value of @ref TMR4_SEVT_Zero_Match_Mask_Selection */ + + uint16_t u16PeakMatchMaskCmd; /*!< Enable or disable perform to compare with the CNT peak interrupt mask counter + This parameter can be a value of @ref TMR4_SEVT_Peak_Match_Mask_Selection */ + + uint16_t u16MaskTimes; /*!< Specifies start time by the value to be compared with the CNT interrupt mask counter */ +} stc_tmr4_sevt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Global_Macros TMR4 Global Macros + * @{ + */ + +/** + * @defgroup TMR4_CNT_Macros TMR4 Counter Macros + * @{ + */ + +/** @defgroup TMR4_CNT_PCLK_Division TMR4 Counter PCLK Clock Division + * @{ + */ +#define TMR4_CNT_PCLK_DIV1 (0U) /*!< PCLK */ +#define TMR4_CNT_PCLK_DIV2 (TMR4_CCSR_CKDIV_0) /*!< PCLK/2 */ +#define TMR4_CNT_PCLK_DIV4 (TMR4_CCSR_CKDIV_1) /*!< PCLK/4 */ +#define TMR4_CNT_PCLK_DIV8 (TMR4_CCSR_CKDIV_1 | \ + TMR4_CCSR_CKDIV_0) /*!< PCLK/8 */ +#define TMR4_CNT_PCLK_DIV16 (TMR4_CCSR_CKDIV_2) /*!< PCLK/16 */ +#define TMR4_CNT_PCLK_DIV32 (TMR4_CCSR_CKDIV_2 | \ + TMR4_CCSR_CKDIV_0) /*!< PCLK/32 */ +#define TMR4_CNT_PCLK_DIV64 (TMR4_CCSR_CKDIV_2 | \ + TMR4_CCSR_CKDIV_1) /*!< PCLK/64 */ +#define TMR4_CNT_PCLK_DIV128 (TMR4_CCSR_CKDIV_2 | \ + TMR4_CCSR_CKDIV_1 | \ + TMR4_CCSR_CKDIV_0) /*!< PCLK/128 */ +#define TMR4_CNT_PCLK_DIV256 (TMR4_CCSR_CKDIV_3) /*!< PCLK/256 */ +#define TMR4_CNT_PCLK_DIV512 (TMR4_CCSR_CKDIV_3 | \ + TMR4_CCSR_CKDIV_0) /*!< PCLK/512 */ +#define TMR4_CNT_PCLK_DIV1024 (TMR4_CCSR_CKDIV_3 | \ + TMR4_CCSR_CKDIV_1) /*!< PCLK/1024 */ +/** + * @} + */ + +/** + * @defgroup TMR4_CNT_Mode TMR4 Counter Mode + * @{ + */ +#define TMR4_CNT_MODE_SAWTOOTH_WAVE (0U) +#define TMR4_CNT_MODE_TRIANGLE_WAVE (TMR4_CCSR_MODE) +/** + * @} + */ + +/** + * @defgroup TMR4_CNT_Flag TMR4 Counter Flag + * @{ + */ +#define TMR4_CNT_FLAG_PEAK (TMR4_CCSR_IRQPF) +#define TMR4_CNT_FLAG_ZERO (TMR4_CCSR_IRQZF) +#define TMR4_CNT_FLAG_MASK (TMR4_CCSR_IRQPF | TMR4_CCSR_IRQZF) +/** + * @} + */ + +/** + * @defgroup TMR4_CNT_Interrupt TMR4 Counter Interrupt + * @{ + */ +#define TMR4_CNT_INT_PEAK (TMR4_CCSR_IRQPEN) +#define TMR4_CNT_INT_ZERO (TMR4_CCSR_IRQZEN) +#define TMR4_CNT_INT_MASK (TMR4_CCSR_IRQPEN | TMR4_CCSR_IRQZEN) +/** + * @} + */ + +/** + * @defgroup TMR4_CNT_Buffer_State TMR4 CNT Buffer State + * @{ + */ +#define TMR4_CNT_BUFFER_DISABLE (0U) /*!< Disable TMR4 counter buffer function */ +#define TMR4_CNT_BUFFER_ENABLE (TMR4_CCSR_BUFEN) /*!< Enable TMR4 counter buffer function */ +/** + * @} + */ + +/** + * @defgroup TMR4_CNT_Clock_Source TMR4 Count Clock Source + * @{ + */ +#define TMR4_CNT_PCLK (0U) +#define TMR4_CNT_EXTCLK (TMR4_CCSR_ECKEN) +/** + * @} + */ + +/** @defgroup TMR4_CNT_Interrupt_Mask_Times TMR4 Counter Interrupt Mask Times + * @{ + */ +#define TMR4_CNT_INT_MASK_0 (0U) /*!< Counter interrupt flag is always set(not masked) for every counter count at "0x0000" */ +#define TMR4_CNT_INT_MASK_1 (1U) /*!< Counter interrupt flag is set once for 2 for every counter counts at "0x0000" (skiping 1 count) */ +#define TMR4_CNT_INT_MASK_2 (2U) /*!< Counter interrupt flag is set once for 3 for every counter counts at "0x0000" (skiping 2 count) */ +#define TMR4_CNT_INT_MASK_3 (3U) /*!< Counter interrupt flag is set once for 4 for every counter counts at "0x0000" (skiping 3 count) */ +#define TMR4_CNT_INT_MASK_4 (4U) /*!< Counter interrupt flag is set once for 5 for every counter counts at "0x0000" (skiping 4 count) */ +#define TMR4_CNT_INT_MASK_5 (5U) /*!< Counter interrupt flag is set once for 6 for every counter counts at "0x0000" (skiping 5 count) */ +#define TMR4_CNT_INT_MASK_6 (6U) /*!< Counter interrupt flag is set once for 7 for every counter counts at "0x0000" (skiping 6 count) */ +#define TMR4_CNT_INT_MASK_7 (7U) /*!< Counter interrupt flag is set once for 8 for every counter counts at "0x0000" (skiping 7 count) */ +#define TMR4_CNT_INT_MASK_8 (8U) /*!< Counter interrupt flag is set once for 9 for every counter counts at "0x0000" (skiping 8 count) */ +#define TMR4_CNT_INT_MASK_9 (9U) /*!< Counter interrupt flag is set once for 10 for every counter counts at "0x0000" (skiping 9 count) */ +#define TMR4_CNT_INT_MASK_10 (10U) /*!< Counter interrupt flag is set once for 11 for every counter counts at "0x0000" (skiping 10 count) */ +#define TMR4_CNT_INT_MASK_11 (11U) /*!< Counter interrupt flag is set once for 12 for every counter counts at "0x0000" (skiping 11 count) */ +#define TMR4_CNT_INT_MASK_12 (12U) /*!< Counter interrupt flag is set once for 13 for every counter counts at "0x0000" (skiping 12 count) */ +#define TMR4_CNT_INT_MASK_13 (13U) /*!< Counter interrupt flag is set once for 14 for every counter counts at "0x0000" (skiping 13 count) */ +#define TMR4_CNT_INT_MASK_14 (14U) /*!< Counter interrupt flag is set once for 15 for every counter counts at "0x0000" (skiping 14 count) */ +#define TMR4_CNT_INT_MASK_15 (15U) /*!< Counter interrupt flag is set once for 16 for every counter counts at "0x0000" (skiping 15 count) */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_OCO_Macros TMR4 Output Compare Macros + * @{ + */ + +/** @defgroup TMR4_OCO_Channel TMR4 OCO Channel + * @{ + */ +#define TMR4_OCO_UH (0UL) /*!< TMR4 OCO channel:UH */ +#define TMR4_OCO_UL (1UL) /*!< TMR4 OCO channel:UL */ +#define TMR4_OCO_VH (2UL) /*!< TMR4 OCO channel:VH */ +#define TMR4_OCO_VL (3UL) /*!< TMR4 OCO channel:VL */ +#define TMR4_OCO_WH (4UL) /*!< TMR4 OCO channel:WH */ +#define TMR4_OCO_WL (5UL) /*!< TMR4 OCO channel:WL */ +/** + * @} + */ + +/** + * @defgroup TMR4_OCO_State TMR4 OCO State + * @{ + */ +#define TMR4_OCO_DISABLE (0U) /*!< Disable TMR4 OCO output */ +#define TMR4_OCO_ENABLE (TMR4_OCSR_OCEH) /*!< Enable TMR4 OCO output */ +/** + * @} + */ + +/** + * @defgroup TMR4_OCO_Invalid_Output_Polarity TMR4 OCO Invalid Output Polarity + * @{ + */ +#define TMR4_OCO_INVAILD_OP_LOW (0U) /*!< TMR4 OCO Output low level when OCO is invalid */ +#define TMR4_OCO_INVAILD_OP_HIGH (TMR4_OCSR_OCPH) /*!< TMR4 OCO Output high level when OCO is invalid */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_Extend_Match_Condtion TMR4 OCO Extend Match Condtion + * @{ + */ +#define TMR4_OCO_EXTEND_MATCH_DISABLE (0U) /*!< Disable TMR4 OCO extend match function */ +#define TMR4_OCO_EXTEND_MATCH_ENABLE (TMR4_OCER_MCECH) /*!< Enable TMR4 OCO extend match function */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_OCCR_Link_Transfer TMR4 OCO OCCR Link Transfer + * @{ + */ +#define TMR4_OCO_OCCR_LINK_TRANSFER_DISABLE (0U) /*!< Disable the register OCCR buffer link transfer function */ +#define TMR4_OCO_OCCR_LINK_TRANSFER_ENABLE (TMR4_OCER_LMCH) /*!< Register OCCR buffer transfer when the value is both 0 and CPSR and ZIC/PIC is 0 */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_OCCR_Buffer_Mode TMR4 OCO OCCR Buffer Mode + * @{ + */ +#define TMR4_OCO_OCCR_BUF_DISABLE (0U) /*!< Disable the register OCCR buffer function */ +#define TMR4_OCO_OCCR_BUF_CNT_ZERO (TMR4_OCER_CHBUFEN_0) /*!< Register OCCR buffer transfer when counter value is 0x0000 */ +#define TMR4_OCO_OCCR_BUF_CNT_PEAK (TMR4_OCER_CHBUFEN_1) /*!< Register OCCR buffer transfer when counter value is CPSR */ +#define TMR4_OCO_OCCR_BUF_CNT_ZERO_OR_PEAK (TMR4_OCER_CHBUFEN) /*!< Register OCCR buffer transfer when the value is both 0 and CPSR */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_OCMR_Link_Transfer TMR4 OCO OCMR Link Transfer + * @{ + */ +#define TMR4_OCO_OCMR_LINK_TRANSFER_DISABLE (0x0000U) /*!< Disable the register OCMR buffer link transfer function */ +#define TMR4_OCO_OCMR_LINK_TRANSFER_ENABLE (TMR4_OCER_LMMH) /*!< Register OCMR buffer transfer when the value is both 0 and CPSR and ZIC/PIC is 0 */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_OCMR_Buffer_Mode TMR4 OCO OCMR Buffer Mode + * @{ + */ +#define TMR4_OCO_OCMR_BUF_DISABLE (0U) /*!< Disable the register OCCR buffer function */ +#define TMR4_OCO_OCMR_BUF_CNT_ZERO (TMR4_OCER_MHBUFEN_0) /*!< Register OCMR buffer transfer when counter value is 0x0000 */ +#define TMR4_OCO_OCMR_BUF_CNT_PEAK (TMR4_OCER_MHBUFEN_1) /*!< Register OCMR buffer transfer when counter value is CPSR */ +#define TMR4_OCO_OCMR_BUF_CNT_ZERO_OR_PEAK (TMR4_OCER_MHBUFEN) /*!< Register OCMR buffer transfer when the value is both 0 and CPSR */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_Cnt_Match_OCF_State TMR4 OCO Cnt Match OCF State + * @{ + */ +#define TMR4_OCO_OCF_HOLD (0U) /*!< Hold OCF */ +#define TMR4_OCO_OCF_SET (TMR4_OCMRH_OCFDCH) /*!< Set OCF */ +/** + * @} + */ + +/** @defgroup TMR4_OCO_Cnt_Match_Output_Polarity TMR4 OCO Cnt Match Output Polarity + * @{ + */ +#define TMR4_OCO_OP_HOLD (0U) /*!< Hold output when the TMR4 OCO count match */ +#define TMR4_OCO_OP_HIGH (1U) /*!< Output high when the TMR4 OCO count match */ +#define TMR4_OCO_OP_LOW (2U) /*!< Output low when the TMR4 OCO count match */ +#define TMR4_OCO_OP_INVERT (3U) /*!< Invert output when the TMR4 OCO count match */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Macros TMR4 PWM Macros + * @{ + */ + +/** @defgroup TMR4_PWM_Channel TMR4 PWM Channel + * @{ + */ +#define TMR4_PWM_U (0UL) /*!< TMR4 PWM couple channel: U */ +#define TMR4_PWM_V (1UL) /*!< TMR4 PWM couple channel: V */ +#define TMR4_PWM_W (2UL) /*!< TMR4 PWM couple channel: W */ +/** + * @} + */ + +/** @defgroup TMR4_PWM_Port TMR4 PWM Port + * @{ + */ +#define TMR4_PWM_PORT_OUH (0UL) /*!< TMR4 PWM port: TIM4__OUH */ +#define TMR4_PWM_PORT_OUL (1UL) /*!< TMR4 PWM port: TIM4__OUL */ +#define TMR4_PWM_PORT_OVH (2UL) /*!< TMR4 PWM port: TIM4__OVH */ +#define TMR4_PWM_PORT_OVL (3UL) /*!< TMR4 PWM port: TIM4__OVL */ +#define TMR4_PWM_PORT_OWH (4UL) /*!< TMR4 PWM port: TIM4__OWH */ +#define TMR4_PWM_PORT_OWL (5UL) /*!< TMR4 PWM port: TIM4__OWL */ +/** + * @} + */ + +/** @defgroup TMR4_PWM_PCLK_Division TMR4 PWM PCLK Clock Division + * @{ + */ +#define TMR4_PWM_PCLK_DIV1 (0U) /*!< PCLK */ +#define TMR4_PWM_PCLK_DIV2 (TMR4_POCR_DIVCK_0) /*!< PCLK/2 */ +#define TMR4_PWM_PCLK_DIV4 (TMR4_POCR_DIVCK_1) /*!< PCLK/4 */ +#define TMR4_PWM_PCLK_DIV8 (TMR4_POCR_DIVCK_1 | \ + TMR4_POCR_DIVCK_0) /*!< PCLK/8 */ +#define TMR4_PWM_PCLK_DIV16 (TMR4_POCR_DIVCK_2) /*!< PCLK/16 */ +#define TMR4_PWM_PCLK_DIV32 (TMR4_POCR_DIVCK_2 | \ + TMR4_POCR_DIVCK_0) /*!< PCLK/32 */ +#define TMR4_PWM_PCLK_DIV64 (TMR4_POCR_DIVCK_2 | \ + TMR4_POCR_DIVCK_1) /*!< PCLK/64 */ +#define TMR4_PWM_PCLK_DIV128 (TMR4_POCR_DIVCK_2 | \ + TMR4_POCR_DIVCK_1 | \ + TMR4_POCR_DIVCK_0) /*!< PCLK/128 */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Mode TMR4 PWM Mode + * @{ + */ +#define TMR4_PWM_THROUGH_MODE (0U) /*!< Through mode */ +#define TMR4_PWM_DEAD_TIMER_MODE (TMR4_POCR_PWMMD_0) /*!< Dead timer mode */ +#define TMR4_PWM_DEAD_TIMER_FILTER_MODE (TMR4_POCR_PWMMD_1) /*!< Dead timer filter mode */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Transform_OCO_Polarity TMR4 PWM Transform OCO Polarity + * @{ + */ +#define TMR4_PWM_OP_OXH_HOLD_OXL_HOLD (0U) /*!< Output PWML and PWMH signals without changing the level */ +#define TMR4_PWM_OP_OXH_INVERT_OXL_INVERT (TMR4_POCR_LVLS_0) /*!< Output both PWML and PWMH signals reversed */ +#define TMR4_PWM_OP_OXH_INVERT_OXL_HOLD (TMR4_POCR_LVLS_1) /*!< Output the PWMH signal reversed, outputs the PWML signal without changing the level. */ +#define TMR4_PWM_OP_OXH_HOLD_OXL_INVERT (TMR4_POCR_LVLS) /*!< Output the PWMH signal without changing the level, Outputs the PWML signal reversed. */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Port_Output_Mode TMR4 PWM Port Mode + * @{ + */ +#define TMR4_PWM_PORT_OUTPUT_OSxy (0UL) /*!< TIM4__Oxy output polarity by specified OSxy */ +#define TMR4_PWM_PORT_OUTPUT_NORMAL (TMR4_PSCR_OEUH) /*!< TIM4__Oxy output normal PWM */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_EMB_Port_State TMR4 PWM EMB Port State + * @{ + */ +#define TMR4_PWM_EMB_PORT_OUTPUT_NORMAL (0UL) /*!< TIM4__Oxy output normal */ +#define TMR4_PWM_EMB_PORT_OUTPUT_HIZ (TMR4_PSCR_OSUH_0) /*!< TIM4__Oxy output Hi-z */ +#define TMR4_PWM_EMB_PORT_OUTPUT_LOW (TMR4_PSCR_OSUH_1) /*!< TIM4__Oxy output low level */ +#define TMR4_PWM_EMB_PORT_OUTPUT_HIGH (TMR4_PSCR_OSUH) /*!< TIM4__Oxy output high level */ +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Port_Enable_Bit_Effective_Time TMR4 PWM Port Enable Bit Effective Time + * @{ + */ +#define TMR4_PWM_PORT_ENBIT_EFFECT_IMMEDIATE (0UL) /*!< TMR4 PWM Port Enable Bit Effective Time: immediate */ +#define TMR4_PWM_PORT_ENBIT_EFFECT_CNTUVF (TMR4_PSCR_ODT_1) /*!< TMR4 PWM Port Enable Bit Effective Time: TMR4 counter underflow */ +#define TMR4_PWM_PORT_ENBIT_EFFECT_CNTOVF (TMR4_PSCR_ODT) /*!< TMR4 PWM Port Enable Bit Effective Time: TMR4 counter overflow */ + /** + * @} + */ + +/** + * @} + */ + +/** + * @defgroup TMR4_SEVT_Macros TMR4 Special Event Macros + * @{ + */ + +/** @defgroup TMR4_SEVT_Channel TMR4 SEVT Channel + * @{ + */ +#define TMR4_SEVT_UH (0UL) /*!< TMR4 SEVT channel:UH */ +#define TMR4_SEVT_UL (1UL) /*!< TMR4 SEVT channel:UL */ +#define TMR4_SEVT_VH (2UL) /*!< TMR4 SEVT channel:VH */ +#define TMR4_SEVT_VL (3UL) /*!< TMR4 SEVT channel:VL */ +#define TMR4_SEVT_WH (4UL) /*!< TMR4 SEVT channel:WH */ +#define TMR4_SEVT_WL (5UL) /*!< TMR4 SEVT channel:WL */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Link_Transfer TMR4 SEVT Link Transfer + * @{ + */ +#define TMR4_SEVT_LINK_TRANSFER_DISABLE (0U) /*!< Disable the SEVT Link Transfer function */ +#define TMR4_SEVT_LINK_TRANSFER_ENABLE (TMR4_SCSR_LMC) /*!< Enable the SEVT Link Transfer function */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Down_Selection TMR4 SEVT Down Selection + * @{ + */ +#define TMR4_SEVT_DOWN_DISABLE (0U) /*!< Disable trigger signal when match with SCCR&SCMR and TMR4 CNT count zero */ +#define TMR4_SEVT_DOWN_ENABLE (TMR4_SCSR_DEN) /*!< Enable trigger signal when match with SCCR&SCMR and TMR4 CNT count down */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Up_Selection TMR4 SEVT Up Selection + * @{ + */ +#define TMR4_SEVT_UP_DISABLE (0U) /*!< Disable trigger signal when match with SCCR&SCMR and TMR4 CNT count up */ +#define TMR4_SEVT_UP_ENABLE (TMR4_SCSR_UEN) /*!< Enable trigger signal when match with SCCR&SCMR and TMR4 CNT count up */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Peak_Selection TMR4 SEVT Peak Selection + * @{ + */ +#define TMR4_SEVT_PEAK_DISABLE (0U) /*!< Disable trigger signal when match with SCCR&SCMR and TMR4 CNT count peak */ +#define TMR4_SEVT_PEAK_ENABLE (TMR4_SCSR_PEN) /*!< Enable trigger signal when match with SCCR&SCMR and TMR4 CNT count peak */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Zero_Selection TMR4 SEVT Zero Selection + * @{ + */ +#define TMR4_SEVT_ZERO_DISABLE (0U) /*!< Disable trigger signal when match with SCCR&SCMR and TMR4 CNT count zero */ +#define TMR4_SEVT_ZERO_ENABLE (TMR4_SCSR_ZEN) /*!< Enable trigger signal when match with SCCR&SCMR and TMR4 CNT count zero */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Zero_Match_Mask_Selection TMR4 SEVT Zero Match Mask Selection + * @{ + */ +#define TMR4_SEVT_ZERO_MATCH_MASK_DISABLE (0U) /*!< Disable perform to compare with the CNT zero interrupt mask counter */ +#define TMR4_SEVT_ZERO_MATCH_MASK_ENABLE (TMR4_SCMR_MZCE) /*!< Enable perform to compare with the CNT zero interrupt mask counter */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Peak_Match_Mask_Selection TMR4 SEVT Peak Match Mask Selection + * @{ + */ +#define TMR4_SEVT_PEAK_MATCH_MASK_DISABLE (0U) /*!< Disable perform to compare with the CNT peak interrupt mask counter */ +#define TMR4_SEVT_PEAK_MATCH_MASK_ENABLE (TMR4_SCMR_MPCE) /*!< Enable perform to compare with the CNT peak interrupt mask counter */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Buffer_Mode TMR4 SEVT Buffer Mode + * @{ + */ +#define TMR4_SEVT_BUF_DISABLE (0U) /*!< Disable the register SCCR&SCMR buffer function */ +#define TMR4_SEVT_BUF_CNT_ZERO (TMR4_SCSR_BUFEN_0) /*!< Register SCCR&SCMR buffer transfer when counter value is 0x0000 */ +#define TMR4_SEVT_BUF_CNT_PEAK (TMR4_SCSR_BUFEN_1) /*!< Register SCCR&SCMR buffer transfer when counter value is CPSR */ +#define TMR4_SEVT_BUF_CNT_ZERO_OR_PEAK (TMR4_SCSR_BUFEN) /*!< Register SCCR&SCMR buffer transfer when the value is both 0 and CPSR */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Output_Event TMR4 SEVT Output Event + * @{ + */ +#define TMR4_SEVT_OUTPUT_EVENT0 (0U) /*!< TMR4 SEVT output special event 0 */ +#define TMR4_SEVT_OUTPUT_EVENT1 (TMR4_SCSR_EVTOS_0) /*!< TMR4 SEVT output special event 1 */ +#define TMR4_SEVT_OUTPUT_EVENT2 (TMR4_SCSR_EVTOS_1) /*!< TMR4 SEVT output special event 2 */ +#define TMR4_SEVT_OUTPUT_EVENT3 (TMR4_SCSR_EVTOS_1 | \ + TMR4_SCSR_EVTOS_0) /*!< TMR4 SEVT output special event 3 */ +#define TMR4_SEVT_OUTPUT_EVENT4 (TMR4_SCSR_EVTOS_2) /*!< TMR4 SEVT output special event 4 */ +#define TMR4_SEVT_OUTPUT_EVENT5 (TMR4_SCSR_EVTOS_2 | \ + TMR4_SCSR_EVTOS_0) /*!< TMR4 SEVT output special event 5 */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Mode TMR4 SEVT Mode + * @{ + */ +#define TMR4_SEVT_MODE_COMPARE_TRIGGER (0U) +#define TMR4_SEVT_MODE_DELAY_TRIGGER (TMR4_SCSR_EVTMS) +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Delay_Object TMR4 SEVT Delay Object + * @{ + */ +#define TMR4_SEVT_DELAY_OCCRXH (0U) /*!< TMR4 SEVT delay object: OCCRxh */ +#define TMR4_SEVT_DELAY_OCCRXL (TMR4_SCSR_EVTDS) /*!< TMR4 SEVT delay object: OCCRxl */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Mask_Times TMR4 SEVT Mask Times + * @{ + */ +#define TMR4_SEVT_MASK_0 (0U) /*!< Mask 0 time */ +#define TMR4_SEVT_MASK_1 (1U) /*!< Mask 1 times */ +#define TMR4_SEVT_MASK_2 (2U) /*!< Mask 2 times */ +#define TMR4_SEVT_MASK_3 (3U) /*!< Mask 3 times */ +#define TMR4_SEVT_MASK_4 (4U) /*!< Mask 4 times */ +#define TMR4_SEVT_MASK_5 (5U) /*!< Mask 5 times */ +#define TMR4_SEVT_MASK_6 (6U) /*!< Mask 6 times */ +#define TMR4_SEVT_MASK_7 (7U) /*!< Mask 7 times */ +#define TMR4_SEVT_MASK_8 (8U) /*!< Mask 8 times */ +#define TMR4_SEVT_MASK_9 (9U) /*!< Mask 9 times */ +#define TMR4_SEVT_MASK_10 (10U) /*!< Mask 10 times */ +#define TMR4_SEVT_MASK_11 (11U) /*!< Mask 11 times */ +#define TMR4_SEVT_MASK_12 (12U) /*!< Mask 12 times */ +#define TMR4_SEVT_MASK_13 (13U) /*!< Mask 13 times */ +#define TMR4_SEVT_MASK_14 (14U) /*!< Mask 14 times */ +#define TMR4_SEVT_MASK_15 (15U) /*!< Mask 15 times */ +/** + * @} + */ + +/** @defgroup TMR4_SEVT_Port_Output_Event_Signal TMR4 SEVT Port Output Event Signal + * @{ + */ +#define TMR4_SEVT_PORT_OUTPUT_NONE (0U) /*!< Disable output event signal of TMR4 Special-EVT */ +#define TMR4_SEVT_PORT_OUTPUT_EVENT0_SIGNAL (TMR4_SCER_EVTRS_0 ) /*!< Output the specified event 0 signal of TMR4 Special-EVT */ +#define TMR4_SEVT_PORT_OUTPUT_EVENT1_SIGNAL (TMR4_SCER_EVTRS_1) /*!< Output the specified event 1 signal of TMR4 Special-EVT */ +#define TMR4_SEVT_PORT_OUTPUT_EVENT2_SIGNAL (TMR4_SCER_EVTRS_1 | \ + TMR4_SCER_EVTRS_0) /*!< Output the specified event 2 signal of TMR4 Special-EVT */ +#define TMR4_SEVT_PORT_OUTPUT_EVENT3_SIGNAL (TMR4_SCER_EVTRS_2) /*!< Output the specified event 3 signal of TMR4 Special-EVT */ +#define TMR4_SEVT_PORT_OUTPUT_EVENT4_SIGNAL (TMR4_SCER_EVTRS_2 | \ + TMR4_SCER_EVTRS_0) /*!< Output the specified event 4 signal of TMR4 Special-EVT */ +#define TMR4_SEVT_PORT_OUTPUT_EVENT5_SIGNAL (TMR4_SCER_EVTRS_2 | \ + TMR4_SCER_EVTRS_1) /*!< Output the specified event 5 signal of TMR4 Special-EVT */ +/** + * @} + */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR4_Global_Functions + * @{ + */ + +/** + * @addtogroup TMR4_CNT_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 counter functions */ +en_result_t TMR4_CNT_Init(M4_TMR4_TypeDef *TMR4x, + const stc_tmr4_cnt_init_t *pstcInit); +en_result_t TMR4_CNT_StructInit(stc_tmr4_cnt_init_t *pstcInit); +void TMR4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x, uint16_t u16ClkSrc); +uint16_t TMR4_CNT_GetClock(const M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_SetPclkDiv(M4_TMR4_TypeDef *TMR4x, uint16_t u16Div); +uint16_t TMR4_CNT_GetPclkDiv(const M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x, uint16_t u16Mode); +uint16_t TMR4_CNT_GetMode(const M4_TMR4_TypeDef *TMR4x); +en_flag_status_t TMR4_CNT_GetStatus(const M4_TMR4_TypeDef *TMR4x, uint16_t u16Flag); +void TMR4_CNT_ClearStatus(M4_TMR4_TypeDef *TMR4x, uint16_t u16Flag); +void TMR4_CNT_IntCmd(M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + en_functional_state_t enNewState); +void TMR4_CNT_Start(M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_Stop(M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16CycleVal); +uint16_t TMR4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x); +void TMR4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16CountVal); +uint16_t TMR4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x); +en_result_t TMR4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + uint16_t u16MaskTimes); +en_result_t TMR4_CNT_GetIntMaskTimes(const M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + uint16_t *pu16MaskTimes); +en_result_t TMR4_CNT_GetIntMaskCurrentTimes(const M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + uint16_t *pu16MaskTimes); +void TMR4_CNT_PortOutputDirSigCmd(M4_TMR4_TypeDef *TMR4x, + en_functional_state_t enNewState); +/** + * @} + */ + +/** + * @addtogroup TMR4_OCO_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 OCO functions */ +en_result_t TMR4_OCO_Init(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_tmr4_oco_init_t *pstcInit); +en_result_t TMR4_OCO_StructInit(stc_tmr4_oco_init_t *pstcInit); +void TMR4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OccrBufMode); +uint16_t TMR4_OCO_GetOccrBufMode(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_OCO_SetOccrLinkTransfer(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16TransferState); +void TMR4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OcmrBufMode); +uint16_t TMR4_OCO_GetOcmrBufMode(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_OCO_SetOcmrLinkTransfer(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16TransferState); +void TMR4_OCO_SetExtMatchCond(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16ExtMatch); +en_result_t TMR4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_oco_high_ch_compare_mode_t *pstcMode); +en_result_t TMR4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_oco_low_ch_compare_mode_t *pstcMode); +void TMR4_OCO_SetOutputCompare(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OcoCmd); +void TMR4_OCO_IntCmd(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + en_functional_state_t enNewState); +en_flag_status_t TMR4_OCO_GetStatus(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_OCO_ClearStatus(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_OCO_SetOcoInvalidOp(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OutputPolarity); +uint16_t TMR4_OCO_GetOutputPolarity(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_OCO_SetCompareVal(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16CompareVal); +uint16_t TMR4_OCO_GetCompareVal(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +/** + * @} + */ + +/** + * @addtogroup TMR4_PWM_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 PWM functions */ +en_result_t TMR4_PWM_Init(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_tmr4_pwm_init_t *pstcInit); +en_result_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcInit); +void TMR4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetPclkDiv(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16Div); +uint16_t TMR4_PWM_GetPclkDiv(const M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_SetOcoPolarityTransform(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OcoPolTransform); +uint16_t TMR4_PWM_GetOcoPolarityTransform(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_PWM_StartReloadTimer(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_StopReloadTimer(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_PWM_IntCmd(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + en_functional_state_t enNewState); +en_flag_status_t TMR4_PWM_GetStatus(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_PWM_ClearStatus(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_PWM_SetDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16PDAR, + uint16_t u16PDBR); +void TMR4_PWM_GetDeadRegionValue(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t *pu16PDAR, + uint16_t *pu16PDBR); +void TMR4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16Count); +void TMR4_PWM_AutoOutputCmd(M4_TMR4_TypeDef *TMR4x, + en_functional_state_t enNewState); +void TMR4_PWM_MasterOutputCmd(M4_TMR4_TypeDef *TMR4x, + en_functional_state_t enNewState); +void TMR4_PWM_PortOutputMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32PwmPort, + uint32_t u32Mode); +void TMR4_PWM_SetPortEnBitEffectTime(M4_TMR4_TypeDef *TMR4x, + uint32_t u32EffectTime); +uint32_t TMR4_PWM_GetPortEnBitEffectTime(const M4_TMR4_TypeDef *TMR4x); +void TMR4_PWM_EmbPwmPortOutputState(M4_TMR4_TypeDef *TMR4x, + uint32_t u32PwmPort, + uint32_t u32State); +/** + * @} + */ + +/** + * @addtogroup TMR4_SEVT_Global_Functions + * @{ + */ + +/* Initialization and configuration TMR4 SEVT functions */ +en_result_t TMR4_SEVT_Init(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_tmr4_sevt_init_t *pstcInit); +en_result_t TMR4_SEVT_StructInit(stc_tmr4_sevt_init_t *pstcInit); +void TMR4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_SEVT_SetOutpuEvent(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16Event); +uint16_t TMR4_SEVT_GetOutpuEvent(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch); +void TMR4_SEVT_SetDelayObject(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16DelayObject); +uint16_t TMR4_SEVT_GetDelayObject(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_SEVT_SetCompareVal(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16CompareVal); +uint16_t TMR4_SEVT_GetCompareVal(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16MaskTimes); +uint16_t TMR4_SEVT_GetMaskTimes(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch); +void TMR4_SEVT_SetPortOutputEventSig(M4_TMR4_TypeDef *TMR4x, + uint16_t u16EvtSignal); +uint16_t TMR4_SEVT_GetPortOutputEventSig(const M4_TMR4_TypeDef *TMR4x); +/** + * @} + */ + +/** + * @} + */ + +#endif /* DDL_TMR4_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_TMR4_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmr6.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmr6.h new file mode 100644 index 0000000000000000000000000000000000000000..4606c5af685e88d703afd3673ae3ac952d8c52c3 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmr6.h @@ -0,0 +1,895 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmr6.h + * @brief Head file for TMR6 module. + * + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-07-15 Wangmin Refine macro define + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_TMR6_H__ +#define __HC32F4A0_TMR6_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_TMR6 + * @{ + */ + +#if (DDL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Types TMR6 Global Types + * @{ + */ + +/** + * @brief Timer6 base counter function structure definition + */ +typedef struct +{ + uint32_t u32CntMode; /*!< Count mode, @ref TMR6_Count_Mode_define */ + uint32_t u32CntDir; /*!< Count direction, @ref TMR6_Count_Direction_define */ + uint32_t u32CntClkDiv; /*!< Count clock division select, @ref TMR6_Count_Clock_define */ + uint32_t u32CntStpAftOvf; /*!< Count stop after overflow @ref TMR6_Count_Stop_After_Overflow_define*/ +}stc_tmr6_basecnt_cfg_t; + +/** + * @brief Timer6 buffer function configuration structure definition + */ +typedef struct +{ + uint32_t u32BufFunCmd; /*!< specifies the buffer function status, + and this parameter can be a value of + @ref TMR6_Buffer_Function_sta_Define */ + uint32_t u32BufNum; /*!< specifies the buffer number, + and this parameter can be a value of + @ref TMR6_Buffer_Number_Chose_Define */ + uint32_t u32BufTransTim; /*!< specifies the buffer send time, + and this parameter can be a value of + @ref TMR6_Buffer_Transfer_Time_Cfg_Define */ +}stc_tmr6_buf_func_cfg_t; + +/** + * @brief Timer6 Valid period function configuration structure definition + */ +typedef struct +{ + uint32_t u32StatChA; /*!< specifies the valid period function status for channel A, + and this parameter can be a value of + @ref TMR6_Valid_Period_CHA_STAT_Define */ + uint32_t u32StatChB; /*!< specifies the valid period function status for channel B, + and this parameter can be a value of + @ref TMR6_Valid_Period_CHB_STAT_Define */ + uint32_t u32CntCond; /*!< specifies the count condition, + and this parameter can be a value of + @ref TMR6_Valid_Period_Count_Condition_Define */ + uint32_t u32PeriodInterval; /*!< specifies the interval of the valid period, + @ref TMR6_Valid_Period_Count_Define */ +}stc_tmr6_valid_period_func_cfg_t; + +/** + * @brief Timer6 port input configuration structure definition + */ +typedef struct +{ + uint32_t u32PortMode; /*!< Port function mode @ref TMR6_Port_Mode_Func */ + uint32_t u32FilterSta; /*!< trig source capture input filter status + @ref TMR6_Port_Input_Filter_Sta*/ + uint32_t u32FltClk; /*!< Filter clock @ref TMR6_Input_Port_Filter_Clk*/ +}stc_tmr6_port_input_cfg_t; + +/** + * @brief Timer6 port output configuration structure definition + */ +typedef struct +{ + uint32_t u32PortMode; /*!< Port function mode @ref TMR6_Port_Mode_Func */ + uint32_t u32NextPeriodForceSta; /*!< Port State Next period @ref TMR6_Force_Port_Output_Sta */ + uint32_t u32DownCntMatchAnotherCmpRegSta; /*!< Port state when counter match another compare register + (CHA matched GCMBR, CHB matched GCMAR) in count-down mode + @ref TMR6_Port_Output_Sta */ + uint32_t u32UpCntMatchAnotherCmpRegSta; /*!< Port state when counter match another compare register + (CHA matched GCMBR, CHB matched GCMAR) in count-up mode + @ref TMR6_Port_Output_Sta*/ + uint32_t u32DownCntMatchCmpRegSta; /*!< Port state when counter match compare register + (CHA matched GCMAR, CHB matched GCMBR) in count-down mode + @ref TMR6_Port_Output_Sta */ + uint32_t u32UpCntMatchCmpRegSta; /*!< Port state when counter match compare register + (CHA matched GCMAR, CHB matched GCMBR) in count-up mode + @ref TMR6_Port_Output_Sta */ + uint32_t u32UnderflowSta; /*!< Port State when counter underflow @ref TMR6_Port_Output_Sta */ + uint32_t u32OverflowSta; /*!< Port State when counter overflow @ref TMR6_Port_Output_Sta */ + uint32_t u32StopSta; /*!< Port State when count stop @ref TMR6_Port_Output_Sta */ + uint32_t u32StartSta; /*!< Port State when count start @ref TMR6_Port_Output_Sta */ +}stc_tmr6_port_output_cfg_t; + +/** + * @brief Timer6 EMB configuration structure definition + */ +typedef struct +{ + uint32_t u32ValidCh; /*!< Valid EMB event channel @ref TMR6_Emb_channel */ + uint32_t u32ReleaseMode; /*!< Port release mode when EMB event invalid @ref TMR6_Emb_Release_Mode */ + uint32_t u32PortSta; /*!< Port Output status when EMB event valid @ref TMR6_Emb_Port_Sta */ +}stc_tmr6_emb_cfg_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct +{ + uint32_t u32DtEqualUpDwn; /*!< Enable down count dead time register equal to up count DT register + @ref TMR6_Deadtime_Reg_Equal_Func_define */ + uint32_t u32EnDtBufUp; /*!< Enable buffer transfer for up count dead time register + (DTUBR-->DTUAR) @ref TMR6_Deadtime_CountUp_Buf_Func_define*/ + uint32_t u32EnDtBufDwn; /*!< Enable buffer transfer for down count dead time register + (DTDBR-->DTDAR) @ref TMR6_Deadtime_CountDown_Buf_Func_define*/ + uint32_t u32DtUpdCond; /*!< Buffer transfer condition for triangular wave mode + @ref TMR6_Deadtime_Buf_Transfer_Condition_define */ +}stc_tmr6_deadtime_cfg_t; + +/** + * @brief Timer6 Dead time function configuration structure definition + */ +typedef struct +{ + uint32_t u32ZMaskCycle; /*!< Z phase input mask periods selection @ref TMR6_Zmask_Cycle_define*/ + uint32_t u32PosCntMaskEn; /*!< As position count timer, clear function enable(TRUE) or disable(FALSE) + during the time of Z phase input mask @ref TMR6_Zmask_Position_Unit_Clear_Func_define*/ + uint32_t u32RevCntMaskEn; /*!< As revolution count timer, the counter function enable(TRUE) or + disable(FALSE) during the time of Z phase input mask @ref TMR6_Zmask_Revolution_Unit_Count_Func_define*/ +}stc_tmr6_zmask_cfg_t; + + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Global_Macros TMR6 Global Macros + * @{ + */ + + +/** @defgroup TMR6_Sta_Bit_Get_Define TMR6 status bit define + * @{ + */ +/* Status bit indicate that GCMAR register matched with counter register */ +#define TMR6_STAT_CNT_MATCH_A (TMR6_STFLR_CMAF) +/* Status bit indicate that GCMBR register matched with counter register */ +#define TMR6_STAT_CNT_MATCH_B (TMR6_STFLR_CMBF) +/* Status bit indicate that GCMCR register matched with counter register */ +#define TMR6_STAT_CNT_MATCH_C (TMR6_STFLR_CMCF) +/* Status bit indicate that GCMDR register matched with counter register */ +#define TMR6_STAT_CNT_MATCH_D (TMR6_STFLR_CMDF) +/* Status bit indicate that GCMER register matched with counter register */ +#define TMR6_STAT_CNT_MATCH_E (TMR6_STFLR_CMEF) +/* Status bit indicate that GCMFR register matched with counter register */ +#define TMR6_STAT_CNT_MATCH_F (TMR6_STFLR_CMFF) +/* Status bit indicate that counter register overflow */ +#define TMR6_STAT_OVERFLOW (TMR6_STFLR_OVFF) +/* Status bit indicate that counter register underflow */ +#define TMR6_STAT_UNDERFLOW (TMR6_STFLR_UDFF) +/* Status bit indicate that dead time error */ +#define TMR6_STAT_DEAD_TIME_ERR (TMR6_STFLR_DTEF) +/* Status bit indicate that SCMAR register matched with counter register during count-up */ +#define TMR6_STAT_UPCNT_SP_MATCH_A (TMR6_STFLR_CMSAUF) +/* Status bit indicate that SCMAR register matched with counter register during count-down */ +#define TMR6_STAT_DOWNCNT_SP_MATCH_A (TMR6_STFLR_CMSADF) +/* Status bit indicate that SCMBR register matched with counter register during count-up */ +#define TMR6_STAT_UPCNT_SP_MATCH_B (TMR6_STFLR_CMSBUF) +/* Status bit indicate that SCMBR register matched with counter register during count-down */ +#define TMR6_STAT_DOWNCNT_SP_MATCH_B (TMR6_STFLR_CMSBDF) +/* Counter direction flag */ +#define TMR6_STAT_CNT_DIR (TMR6_STFLR_DIRF) +/** + * @} + */ + +/** @defgroup TMR6_Interrupt_Enable_Bit_Define TMR6 interrupt configuration bit define + * @{ + */ +/* Interrupt enable bit for GCMAR register matched */ +#define TMR6_IRQ_EN_CNT_MATCH_A (TMR6_ICONR_INTENA) +/* Interrupt enable bit for GCMBR register matched */ +#define TMR6_IRQ_EN_CNT_MATCH_B (TMR6_ICONR_INTENB) +/* Interrupt enable bit for GCMCR register matched */ +#define TMR6_IRQ_EN_CNT_MATCH_C (TMR6_ICONR_INTENC) +/* Interrupt enable bit for GCMDR register matched */ +#define TMR6_IRQ_EN_CNT_MATCH_D (TMR6_ICONR_INTEND) +/* Interrupt enable bit for GCMER register matched */ +#define TMR6_IRQ_EN_CNT_MATCH_E (TMR6_ICONR_INTENE) +/* Interrupt enable bit for GCMFR register matched */ +#define TMR6_IRQ_EN_CNT_MATCH_F (TMR6_ICONR_INTENF) +/* Interrupt enable bit for counter register overflow */ +#define TMR6_IRQ_EN_OVERFLOW (TMR6_ICONR_INTENOVF) +/* Interrupt enable bit for counter register underflow */ +#define TMR6_IRQ_EN_UNDERFLOW (TMR6_ICONR_INTENUDF) +/* Interrupt enable bit for dead time */ +#define TMR6_IRQ_EN_DEAD_TIME_ERR (TMR6_ICONR_INTENDTE) +/* Interrupt enable bit for SCMAR register matched during count-up*/ +#define TMR6_IRQ_EN_UPCNT_SP_MATCH_A (TMR6_ICONR_INTENSAU) +/* Interrupt enable bit for SCMAR register matched during count-down*/ +#define TMR6_IRQ_EN_DOWNCNT_SP_MATCH_A (TMR6_ICONR_INTENSAD) +/* Interrupt enable bit for SCMBR register matched during count-up*/ +#define TMR6_IRQ_EN_UPCNT_SP_MATCH_B (TMR6_ICONR_INTENSBU) +/* Interrupt enable bit for SCMBR register matched during count-down*/ +#define TMR6_IRQ_EN_DOWNCNT_SP_MATCH_B (TMR6_ICONR_INTENSBD) +/** + * @} + */ + +/** @defgroup TMR6_Period_Register_Index_Define TMR6 period register Index define + * @{ + */ +#define TMR6_PERIOD_REG_A (0x00UL) +#define TMR6_PERIOD_REG_B (0x01UL) +#define TMR6_PERIOD_REG_C (0x02UL) +/** + * @} + */ + +/** @defgroup TMR6_Compare_Register_Index_Define TMR6 compare register Index define + * @{ + */ +#define TMR6_CMP_REG_A (0x00UL) +#define TMR6_CMP_REG_B (0x01UL) +#define TMR6_CMP_REG_C (0x02UL) +#define TMR6_CMP_REG_D (0x03UL) +#define TMR6_CMP_REG_E (0x04UL) +#define TMR6_CMP_REG_F (0x05UL) +/** + * @} + */ + +/** @defgroup TMR6_Compare_channel_Define TMR6 general/special compare channel index define + * @{ + */ +#define TMR6_CH_A (0x00UL) +#define TMR6_CH_B (0x01UL) +/** + * @} + */ + +/** @defgroup TMR6_Buffer_Function_sta_Define TMR6 buffer function status define + * @{ + */ +#define TMR6_BUF_FUNC_OFF (0x00000000UL) +#define TMR6_BUF_FUNC_ON (TMR6_BCONR_BENA) +/** + * @} + */ + +/** @defgroup TMR6_Buffer_Number_Chose_Define TMR6 buffer number configuration define + * @{ + */ +#define TMR6_BUF_FUNC_SINGLE (0x00000000UL) +#define TMR6_BUF_FUNC_DOUBLE (TMR6_BCONR_BSEA) +/** + * @} + */ + +/** @defgroup TMR6_Buffer_Transfer_Time_Cfg_Define TMR6 buffer transfer time configuration define + * @{ + */ +#define TMR6_BUF_TRANS_TIM_NONE (0x00000000UL) +#define TMR6_BUF_TRANS_TIM_OVERFLOW (TMR6_BCONR_BTRUA) +#define TMR6_BUF_TRANS_TIM_UNDERFLOW (TMR6_BCONR_BTRDA) +#define TMR6_BUF_TRANS_TIM_BOTH (TMR6_BCONR_BTRUA | TMR6_BCONR_BTRDA) +/** + * @} + */ + +/** @defgroup TMR6_Valid_Period_Count_Condition_Define TMR6 valid period function count condition define + * @{ + */ +/* Valid period function off */ +#define TMR6_VALID_PERIOD_FUNC_OFF (0x00000000UL) +/* Counted when Sawtooth waveform overflow and underflow, triangular wave underflow */ +#define TMR6_VALID_PERIOD_CNT_COND_UNDERFLOW (TMR6_VPERR_PCNTE_0) +/* Counted when Sawtooth waveform overflow and underflow, triangular wave overflow */ +#define TMR6_VALID_PERIOD_CNT_COND_OVERFLOW (TMR6_VPERR_PCNTE_1) +/* Counted when Sawtooth waveform overflow and underflow, triangular wave overflow and underflow */ +#define TMR6_VALID_PERIOD_CNT_COND_BOTH (TMR6_VPERR_PCNTE_0 | TMR6_VPERR_PCNTE_1) +/** + * @} + */ + +/** @defgroup TMR6_Valid_Period_Count_Define TMR6 valid period function count define + * @{ + */ +/* Valid period count function invalid */ +#define TMR6_VALID_PERIOD_CNT_INVALID (0x00000000UL) +/* Interrupt and event valid every other 1 period */ +#define TMR6_VALID_PERIOD_CNT_1 (TMR6_VPERR_PCNTS_0) +/* Interrupt and event valid every other 2 period */ +#define TMR6_VALID_PERIOD_CNT_2 (TMR6_VPERR_PCNTS_1) +/* Interrupt and event valid every other 3 period */ +#define TMR6_VALID_PERIOD_CNT_3 (TMR6_VPERR_PCNTS_0 | TMR6_VPERR_PCNTS_1) +/* Interrupt and event valid every other 4 period */ +#define TMR6_VALID_PERIOD_CNT_4 (TMR6_VPERR_PCNTS_2) +/* Interrupt and event valid every other 5 period */ +#define TMR6_VALID_PERIOD_CNT_5 (TMR6_VPERR_PCNTS_2 | TMR6_VPERR_PCNTS_0) +/* Interrupt and event valid every other 6 period */ +#define TMR6_VALID_PERIOD_CNT_6 (TMR6_VPERR_PCNTS_2 | TMR6_VPERR_PCNTS_1) +/* Interrupt and event valid every other 7 period */ +#define TMR6_VALID_PERIOD_CNT_7 (TMR6_VPERR_PCNTS_2 | TMR6_VPERR_PCNTS_1 | TMR6_VPERR_PCNTS_0) +/** + * @} + */ + +/** @defgroup TMR6_Valid_Period_CHA_STAT_Define TMR6 valid period function channel A status define + * @{ + */ +#define TMR6_VALID_PERIOD_FUNC_CHA_OFF (0x00000000UL) +#define TMR6_VALID_PERIOD_FUNC_CHA_ON (TMR6_VPERR_SPPERIA) +/** + * @} + */ + +/** @defgroup TMR6_Valid_Period_CHB_STAT_Define TMR6 valid period function channel B status define + * @{ + */ +#define TMR6_VALID_PERIOD_FUNC_CHB_OFF (0x00000000UL) +#define TMR6_VALID_PERIOD_FUNC_CHB_ON (TMR6_VPERR_SPPERIB) +/** + * @} + */ + +/** @defgroup TMR6_DeadTime_Reg_Define TMR6 dead time register define + * @{ + */ +/* Register DTUAR */ +#define TMR6_DEADTIME_REG_UP_A (0x00U) +/* Register DTDAR */ +#define TMR6_DEADTIME_REG_DOWN_A (0x01U) +/* Register DTUBR */ +#define TMR6_DEADTIME_REG_UP_B (0x02U) +/* Register DTDBR */ +#define TMR6_DEADTIME_REG_DOWN_B (0x03U) +/** + * @} + */ + +/** @defgroup TMR6_Port_Define TMR6 input and output port define + * @{ + */ +/* port TIM6__PWMA */ +#define TMR6_IO_PWMA (0x00U) +/* port TIM6__PWMB */ +#define TMR6_IO_PWMB (0x01U) +/* Input port TIM6_TRIGA */ +#define TMR6_INPUT_TRIGA (0x02U) +/* Input port TIM6_TRIGB */ +#define TMR6_INPUT_TRIGB (0x03U) +/* Input port TIM6_TRIGC */ +#define TMR6_INPUT_TRIGC (0x04U) +/* Input port TIM6_TRIGD */ +#define TMR6_INPUT_TRIGD (0x05U) +/** + * @} + */ + +/** @defgroup TMR6_Input_Port_Filter_Clk TMR6 input port define + * @{ + */ +#define TMR6_INPUT_FILTER_PCLK0_DIV1 (0x00U) +#define TMR6_INPUT_FILTER_PCLK0_DIV4 (0x01U) +#define TMR6_INPUT_FILTER_PCLK0_DIV16 (0x02U) +#define TMR6_INPUT_FILTER_PCLK0_DIV64 (0x03U) +/** + * @} + */ + +/** @defgroup TMR6_Port_Mode_Func TMR6 port function mode selection + * @{ + */ +#define TMR6_PORT_COMPARE_OUTPUT (0x00U) +#define TMR6_PORT_CAPTURE_INPUT (TMR6_PCNAR_CAPMDA) +/** + * @} + */ + +/** @defgroup TMR6_Port_Input_Filter_Sta TMR6 port input filter function status + * @{ + */ +#define TMR6_PORT_INPUT_FILTER_OFF (0x00U) +#define TMR6_PORT_INPUT_FILTER_ON (0x01U) +/** + * @} + */ + +/** @defgroup TMR6_Port_Output_Sta TMR6 port output status + * @{ + */ +#define TMR6_PORT_OUTPUT_STA_LOW (0x00U) +#define TMR6_PORT_OUTPUT_STA_HIGH (0x01U) +#define TMR6_PORT_OUTPUT_STA_HOLD (0x02U) +#define TMR6_PORT_OUTPUT_STA_REVERSE (0x03U) +/** + * @} + */ + +/** @defgroup TMR6_Force_Port_Output_Sta TMR6 force port output status next period + * @{ + */ +#define TMR6_FORCE_PORT_OUTPUT_INVALID (0x00U) +#define TMR6_FORCE_PORT_OUTPUT_STA_LOW (0x02U) +#define TMR6_FORCE_PORT_OUTPUT_STA_HIGH (0x03U) +/** + * @} + */ + +/** @defgroup TMR6_Emb_channel TMR6 EMB event valid channel + * @{ + */ +#define TMR6_EMB_EVENT_VALID_CH0 (0x00U) +#define TMR6_EMB_EVENT_VALID_CH1 (TMR6_PCNAR_EMBSA_0) +#define TMR6_EMB_EVENT_VALID_CH2 (TMR6_PCNAR_EMBSA_1) +#define TMR6_EMB_EVENT_VALID_CH3 (TMR6_PCNAR_EMBSA_0 | TMR6_PCNAR_EMBSA_1) +/** + * @} + */ + +/** @defgroup TMR6_Emb_Release_Mode TMR6 EMB function release mode when EMB event invalid + * @{ + */ +#define TMR6_EMB_RELEASE_IMMEDIATE (0x00U) +#define TMR6_EMB_RELEASE_OVERFLOW (TMR6_PCNAR_EMBRA_0) +#define TMR6_EMB_RELEASE_UNDERFLOW (TMR6_PCNAR_EMBRA_1) +#define TMR6_EMB_RELEASE_OVERFLOW_UNDERFLOW (TMR6_PCNAR_EMBRA_0 | TMR6_PCNAR_EMBRA_1) +/** + * @} + */ + +/** @defgroup TMR6_Emb_Port_Sta TMR6 EMB port output status when EMB event valid + * @{ + */ +#define TMR6_EMB_PORTSTA_NORMAL (0x00U) +#define TMR6_EMB_PORTSTA_HIZ (TMR6_PCNAR_EMBCA_0) +#define TMR6_EMB_PORTSTA_LOW (TMR6_PCNAR_EMBCA_1) +#define TMR6_EMB_PORTSTA_HIGH (TMR6_PCNAR_EMBCA_0 | TMR6_PCNAR_EMBCA_1) +/** + * @} + */ + +/** @defgroup TMR6_Deadtime_CountUp_Buf_Func_define TMR6 Dead time buffer function for count up stage + * @{ + */ +#define TMR6_DEADTIME_CNT_UP_BUF_OFF (0x00U) +#define TMR6_DEADTIME_CNT_UP_BUF_ON (TMR6_DCONR_DTBENU) +/** + * @} + */ + +/** @defgroup TMR6_Deadtime_CountDown_Buf_Func_define TMR6 Dead time buffer function for count down stage + * @{ + */ +#define TMR6_DEADTIME_CNT_DOWN_BUF_OFF (0x00U) +#define TMR6_DEADTIME_CNT_DOWN_BUF_ON (TMR6_DCONR_DTBEND) +/** + * @} + */ + +/** @defgroup TMR6_Deadtime_Buf_Transfer_Condition_define TMR6 Dead time buffer transfer condition define for triangular count mode + * @{ + */ +#define TMR6_DEADTIME_TRANS_COND_NONE (0x00U) +#define TMR6_DEADTIME_TRANS_COND_OVERFLOW (TMR6_DCONR_DTBTRU) +#define TMR6_DEADTIME_TRANS_COND_UNDERFLOW (TMR6_DCONR_DTBTRD) +#define TMR6_DEADTIME_TRANS_COND_BOTH (TMR6_DCONR_DTBTRU | TMR6_DCONR_DTBTRD) +/** + * @} + */ + +/** @defgroup TMR6_Deadtime_Reg_Equal_Func_define TMR6 Dead time function DTDAR equal DTUAR + * @{ + */ +#define TMR6_DEADTIME_EQUAL_OFF (0x00U) +#define TMR6_DEADTIME_EQUAL_ON (TMR6_DCONR_SEPA) +/** + * @} + */ + +/** @defgroup TMR6_Soft_Sync_Ctrl_Unit_Number_define TMR6 Software synchronization start/stop/clear/update unit number define + * @{ + */ +#define TMR6_SOFT_SYNC_CTRL_U1 (TMR6_SSTAR_SSTA1) +#define TMR6_SOFT_SYNC_CTRL_U2 (TMR6_SSTAR_SSTA2) +#define TMR6_SOFT_SYNC_CTRL_U3 (TMR6_SSTAR_SSTA3) +#define TMR6_SOFT_SYNC_CTRL_U4 (TMR6_SSTAR_SSTA4) +#define TMR6_SOFT_SYNC_CTRL_U5 (TMR6_SSTAR_SSTA5) +#define TMR6_SOFT_SYNC_CTRL_U6 (TMR6_SSTAR_SSTA6) +#define TMR6_SOFT_SYNC_CTRL_U7 (TMR6_SSTAR_SSTA7) +#define TMR6_SOFT_SYNC_CTRL_U8 (TMR6_SSTAR_SSTA8) +/** + * @} + */ + +/** @defgroup TMR6_hardware_control_event_define TMR6 hardware start/stop/clear/update/capture events define + * @{ + */ +#define TMR6_HW_CTRL_PWMA_RISING (TMR6_HSTAR_HSTA0) +#define TMR6_HW_CTRL_PWMA_FAILLING (TMR6_HSTAR_HSTA1) +#define TMR6_HW_CTRL_PWMB_RISING (TMR6_HSTAR_HSTA2) +#define TMR6_HW_CTRL_PWMB_FAILLING (TMR6_HSTAR_HSTA3) +#define TMR6_HW_CTRL_INTER_EVENT0 (TMR6_HSTAR_HSTA8) +#define TMR6_HW_CTRL_INTER_EVENT1 (TMR6_HSTAR_HSTA9) +#define TMR6_HW_CTRL_INTER_EVENT2 (TMR6_HSTAR_HSTA10) +#define TMR6_HW_CTRL_INTER_EVENT3 (TMR6_HSTAR_HSTA11) +#define TMR6_HW_CTRL_TRIGEA_RISING (TMR6_HSTAR_HSTA16) +#define TMR6_HW_CTRL_TRIGEA_FAILLING (TMR6_HSTAR_HSTA17) +#define TMR6_HW_CTRL_TRIGEB_RISING (TMR6_HSTAR_HSTA18) +#define TMR6_HW_CTRL_TRIGEB_FAILLING (TMR6_HSTAR_HSTA19) +#define TMR6_HW_CTRL_TRIGEC_RISING (TMR6_HSTAR_HSTA20) +#define TMR6_HW_CTRL_TRIGEC_FAILLING (TMR6_HSTAR_HSTA21) +#define TMR6_HW_CTRL_TRIGED_RISING (TMR6_HSTAR_HSTA22) +#define TMR6_HW_CTRL_TRIGED_FAILLING (TMR6_HSTAR_HSTA23) +/** + * @} + */ + +/** @defgroup TMR6_hardware_count_event_define TMR6 hardware increase/decrease events define + * @{ + */ +#define TMR6_HW_CNT_PWMAL_PWMBRISING (TMR6_HCUPR_HCUP0) +#define TMR6_HW_CNT_PWMAL_PWMBFAILLING (TMR6_HCUPR_HCUP1) +#define TMR6_HW_CNT_PWMAH_PWMBRISING (TMR6_HCUPR_HCUP2) +#define TMR6_HW_CNT_PWMAH_PWMBFAILLING (TMR6_HCUPR_HCUP3) +#define TMR6_HW_CNT_PWMBL_PWMARISING (TMR6_HCUPR_HCUP4) +#define TMR6_HW_CNT_PWMBL_PWMAFAILLING (TMR6_HCUPR_HCUP5) +#define TMR6_HW_CNT_PWMBH_PWMARISING (TMR6_HCUPR_HCUP6) +#define TMR6_HW_CNT_PWMBH_PWMAFAILLING (TMR6_HCUPR_HCUP7) +#define TMR6_HW_CNT_INTER_EVENT0 (TMR6_HCUPR_HCUP8) +#define TMR6_HW_CNT_INTER_EVENT1 (TMR6_HCUPR_HCUP9) +#define TMR6_HW_CNT_INTER_EVENT2 (TMR6_HCUPR_HCUP10) +#define TMR6_HW_CNT_INTER_EVENT3 (TMR6_HCUPR_HCUP11) +#define TMR6_HW_CNT_TRIGEA_RISING (TMR6_HCUPR_HCUP16) +#define TMR6_HW_CNT_TRIGEA_FAILLING (TMR6_HCUPR_HCUP17) +#define TMR6_HW_CNT_TRIGEB_RISING (TMR6_HCUPR_HCUP18) +#define TMR6_HW_CNT_TRIGEB_FAILLING (TMR6_HCUPR_HCUP19) +#define TMR6_HW_CNT_TRIGEC_RISING (TMR6_HCUPR_HCUP20) +#define TMR6_HW_CNT_TRIGEC_FAILLING (TMR6_HCUPR_HCUP21) +#define TMR6_HW_CNT_TRIGED_RISING (TMR6_HCUPR_HCUP22) +#define TMR6_HW_CNT_TRIGED_FAILLING (TMR6_HCUPR_HCUP23) +/** + * @} + */ + +/** @defgroup TMR6_Count_Direction_define TMR6 base counter function direction define + * @{ + */ +#define TMR6_CNT_INCREASE (TMR6_GCONR_DIR) +#define TMR6_CNT_DECREASE (0x00U) +/** + * @} + */ + +/** @defgroup TMR6_Count_Mode_define TMR6 base counter function mode define + * @{ + */ +#define TMR6_MODE_SAWTOOTH (0x00U) +#define TMR6_MODE_TRIANGLE (TMR6_GCONR_MODE) +/** + * @} + */ + +/** @defgroup TMR6_Count_Clock_define TMR6 base counter clock source define + * @{ + */ +#define TMR6_CLK_PCLK0_DIV1 (0x00UL) +#define TMR6_CLK_PCLK0_DIV2 (0x01UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV4 (0x02UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV8 (0x03UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV16 (0x04UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV32 (0x05UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV64 (0x06UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV128 (0x07UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV256 (0x08UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV512 (0x09UL << TMR6_GCONR_CKDIV_POS) +#define TMR6_CLK_PCLK0_DIV1024 (0x0AUL << TMR6_GCONR_CKDIV_POS) +/** + * @} + */ + +/** @defgroup TMR6_Count_Stop_After_Overflow_define TMR6 count stop after overflow function define + * @{ + */ +#define TMR6_CNT_CONTINUOUS (0x00U) +#define TMR6_STOP_AFTER_OVF (TMR6_GCONR_OVSTP) +/** + * @} + */ + +/** @defgroup TMR6_Zmask_Cycle_define TMR6 Z Mask input function mask cycles number define + * @{ + */ +#define TMR6_ZMASK_CYCLE_FUNC_INVALID (0x00U) +#define TMR6_ZMASK_CYCLE_4 (TMR6_GCONR_ZMSKVAL_0) +#define TMR6_ZMASK_CYCLE_8 (TMR6_GCONR_ZMSKVAL_1) +#define TMR6_ZMASK_CYCLE_16 (TMR6_GCONR_ZMSKVAL_0 | TMR6_GCONR_ZMSKVAL_1) +/** + * @} + */ + +/** @defgroup TMR6_Zmask_Position_Unit_Clear_Func_define TMR6 unit as position timer, z phase input mask function define for clear action + * @{ + */ +#define TMR6_POS_CLR_ZMASK_FUNC_INVALID (0x00U) +#define TMR6_POS_CLR_ZMASK_FUNC_VALID (TMR6_GCONR_ZMSKPOS) +/** + * @} + */ + +/** @defgroup TMR6_Zmask_Revolution_Unit_Count_Func_define TMR6 unit as revolution timer, z phase input mask function define for count action + * @{ + */ +#define TMR6_REVO_CNT_ZMASK_FUNC_INVALID (0x00U) +#define TMR6_REVO_CNT_ZMASK_FUNC_VALID (TMR6_GCONR_ZMSKREV) +/** + * @} + */ + +/** @defgroup TMR6_Hardware_Trigger_Index_define TMR6 hardware trigger index define + * @{ + */ +#define TMR6_HW_TRIG_0 (0x00U) +#define TMR6_HW_TRIG_1 (0x01U) +#define TMR6_HW_TRIG_2 (0x02U) +#define TMR6_HW_TRIG_3 (0x03U) +/** + * @} + */ + +/** @defgroup TMR6_Common_Trigger_Source_Cfg_define TMR6 common Trigger Source Config + * @{ + */ +#define TMR6_COM_TRIG1 (AOS_TMR6_HTSSR_COMTRG_EN_0) +#define TMR6_COM_TRIG2 (AOS_TMR6_HTSSR_COMTRG_EN_1) +#define TMR6_COM_TRIG_MASK (AOS_TMR6_HTSSR_COMTRG_EN) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMR6_Global_Functions + * @{ + */ +/** + * @brief Get Software Sync start status + * @param None + * @retval An uint32_t data indicate the read status. + */ +__STATIC_INLINE uint32_t TMR6_GetSwSyncStaState(void) +{ + return READ_REG32(M4_TMR6_1->SSTAR); +} + +/* TMR6 interrupt request enable or disable */ +void TMR6_IntCmd(M4_TMR6_TypeDef *TMR6x, uint32_t u32Tmr6Irq, en_functional_state_t enNewState); +/* Get Timer6 status flag */ +en_flag_status_t TMR6_GetSta(const M4_TMR6_TypeDef *TMR6x, uint32_t u32StaBit); +/* Get Timer6 period number when valid period function enable */ +uint32_t TMR6_GetPeriodNum(const M4_TMR6_TypeDef *TMR6x); +/* De-initialize the timer6 unit */ +void TMR6_DeInit(M4_TMR6_TypeDef *TMR6x); +/* Initialize the timer6 unit */ +en_result_t TMR6_Init(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_basecnt_cfg_t* pstcTmr6BaseCntCfg); +/* Timer6 counter function command */ +void TMR6_CountCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Timer6 counter register set */ +void TMR6_SetCntReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32Value); +/* Timer6 update register set */ +void TMR6_SetUpdateReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32Value); +/* Timer6 set period register(A~C) */ +void TMR6_SetPeriodReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32PeriodReg, uint32_t u32PeriodVal); +/* Timer6 set general compare register(A~F) */ +void TMR6_SetGenCmpReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32GenCmpReg, uint32_t u32CmpVal); +/* Timer6 set special compare register(A~F) */ +void TMR6_SetSpecialCmpReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32SpecialCmpReg, uint32_t u32CmpVal); +/* Timer6 set dead time registerr */ +void TMR6_SetDeadTimeReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32DeadTimeReg, uint32_t u32CmpVal); + +/* Timer6 get counter register value */ +uint32_t TMR6_GetCntReg(const M4_TMR6_TypeDef *TMR6x); +/* Timer6 get update register value */ +uint32_t TMR6_GetUpdateReg(const M4_TMR6_TypeDef *TMR6x); +/* Timer6 Get period register(A~C) */ +uint32_t TMR6_GetPeriodReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32PeriodReg); +/* Timer6 get general compare registers value(A~F) */ +uint32_t TMR6_GetGenCmpReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32GenCmpReg); +/* Timer6 get special compare registers value(A~F) */ +uint32_t TMR6_GetSpecialCmpReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32SpecialCmpReg); +/* Timer6 get dead time register */ +uint32_t TMR6_GetDeadTimeReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32DeadTimeReg); + +/* Timer6 general compare buffer function configuration */ +en_result_t TMR6_GenCmpBufCfg(M4_TMR6_TypeDef *TMR6x, uint32_t u32CmpChIdx, const stc_tmr6_buf_func_cfg_t* pstcGenBufCfg); +/* Timer6 special compare buffer function configuration */ +en_result_t TMR6_SpecialCmpBufCfg(M4_TMR6_TypeDef *TMR6x, uint32_t u32CmpChIdx, const stc_tmr6_buf_func_cfg_t* pstcSpecialBufCfg); +/* Timer6 period buffer function configuration */ +en_result_t TMR6_PeriodBufCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_buf_func_cfg_t* pstcPeriodBufCfg); + +/* Timer6 valid period function configuration for special compare function */ +en_result_t TMR6_ValidPeriodCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_valid_period_func_cfg_t* pstcValidPeriodCfg); +/* Port input configuration(Trig) */ +en_result_t TMR6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, + uint32_t u32PortSel, + const stc_tmr6_port_input_cfg_t* pstcTmr6PortInputCfg); +/* Port output configuration(Trig) */ +en_result_t TMR6_PortOutputConfig(M4_TMR6_TypeDef *TMR6x, + uint32_t u32PortSel, + const stc_tmr6_port_output_cfg_t* pstcTmr6PortOutputCfg); +/* EMB function configuration */ +en_result_t TMR6_EMBConfig(M4_TMR6_TypeDef *TMR6x, + uint32_t u32PortSel, + const stc_tmr6_emb_cfg_t* pstcTmr6EmbCfg); + +/* Timer6 dead time function command */ +void TMR6_DeadTimeFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/* DeadTime function configuration */ +en_result_t TMR6_DeadTimeCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_cfg_t* pstcTmr6DTCfg); + +/* Timer6 unit Z phase input mask config */ +en_result_t TMR6_ZMaskCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_cfg_t* pstcTmr6ZMaskCfg); + +/* Software Sync Start */ +void TMR6_SwSyncStart(uint32_t u32UnitCombine); +/* Software Sync Stop */ +void TMR6_SwSyncStop(uint32_t u32UnitCombine); +/* Software Sync clear */ +void TMR6_SwSyncClr(uint32_t u32UnitCombine); +/* Software Sync update */ +void TMR6_SwSyncUpdate(uint32_t u32UnitCombine); + +/* Hardware start function command */ +void TMR6_HwStartFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/* Hardware stop function command */ +void TMR6_HwStopFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/* Hardware clear function command */ +void TMR6_HwClrFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); +/* Hardware update function command */ +void TMR6_HwUpdateFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState); + +/* Hardware start condtion command */ +void TMR6_HwStartCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware stop condtion command */ +void TMR6_HwStopCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware clear condtion command */ +void TMR6_HwClrCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware update condtion command */ +void TMR6_HwUpdCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware capture condtion command for channel A */ +void TMR6_HwCaptureChACondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware capture condtion command for channel B */ +void TMR6_HwCaptureChBCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware increase conditon command */ +void TMR6_HwIncreaseCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); +/* Hardware decrease conditon command */ +void TMR6_HwDecreaseCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState); + +/* Hardware start function condition clear */ +void TMR6_HwStartCondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware stop function condition clear */ +void TMR6_HwStopCondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware clear function condition clear */ +void TMR6_HwClrCondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware update function condition clear */ +void TMR6_HwUpdCondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware capture condition clear for channel A */ +void TMR6_HwCaptureChACondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware capture condition clear for channel B */ +void TMR6_HwCaptureChBCondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware increase condition clear */ +void TMR6_HwIncreaseCondClr(M4_TMR6_TypeDef *TMR6x); +/* Hardware decrease condition clear */ +void TMR6_HwDecreaseCondClr(M4_TMR6_TypeDef *TMR6x); + +/* Timer6 Hardware trigger event configuration for(trigger0~trigger3) */ +void TMR6_SetTriggerSrc(uint32_t u32TrigIndex, en_event_src_t enEvent); +/* Timer6 Hardware trigger common event function command for(trigger0~trigger3) */ +void TMR6_ComTriggerCmd(uint32_t u32TrigIndex, uint32_t u32ComTrig, en_functional_state_t enNewState); + +/* Set the fields of structure stc_timer4_pwm_init_t to default values */ +en_result_t TMR6_BaseCntStructInit(stc_tmr6_basecnt_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_buf_func_cfg_t to default values */ +en_result_t TMR6_BufFuncStructInit(stc_tmr6_buf_func_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_valid_period_func_cfg_t to default values */ +en_result_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_func_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_port_input_cfg_t to default values */ +en_result_t TMR6_PortInputStructInit(stc_tmr6_port_input_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_port_output_cfg_t to default values */ +en_result_t TMR6_PortOutputStructInit(stc_tmr6_port_output_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_emb_cfg_t to default values */ +en_result_t TMR6_EMBCfgStructInit(stc_tmr6_emb_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_deadtime_cfg_t to default values */ +en_result_t TMR6_DeadTimeCfgStructInit(stc_tmr6_deadtime_cfg_t *pstcInit); +/* Set the fields of structure stc_tmr6_zmask_cfg_t to default values */ +en_result_t TMR6_ZMaskCfgStructInit(stc_tmr6_zmask_cfg_t *pstcInit); + +/** + * @} + */ + +#endif /* DDL_TMR6_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_TMR6_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmra.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmra.h new file mode 100644 index 0000000000000000000000000000000000000000..37809887f5964eba91fa456097e0176c3dc6c721 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_tmra.h @@ -0,0 +1,616 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmra.h + * @brief This file contains all the functions prototypes of the TMRA(TimerA) + * driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_TMRA_H__ +#define __HC32F4A0_TMRA_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_TMRA + * @{ + */ + +#if (DDL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Types TMRA Global Types + * @{ + */ +/** + * @brief TMRA initialization structure. + * @note 'u32PCLKDiv', 'u32CntDir' and 'u32CntMode' are valid only when the clock source is PCLK(PCLK0 for unit1 ~ uint4. PCLK1 for unit5 ~ uint12). + */ +typedef struct +{ + uint32_t u32ClkSrc; /*!< Specify the counting clock source of TMRA. + This parameter can be a value of @ref TMRA_Clock_Source */ + uint32_t u32PCLKDiv; /*!< Specify the divider of clock source while the clock source is PCLK. + This parameter can be a value of @ref TMRA_PCLK_Divider */ + uint32_t u32CntDir; /*!< Specify the direction of counting. + This parameter can be a value of @ref TMRA_Count_Direction */ + uint32_t u32CntMode; /*!< Specify the mode of counting. + This parameter can be a value of @ref TMRA_Count_Mode */ + uint32_t u32CntOvfOp; /*!< Specify the operation when counting overflow/underflow. + This parameter can be a value of @ref TMRA_Count_Overflow_Operation */ + uint32_t u32PeriodVal; /*!< Specify the period reference value. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ + uint32_t u32CntVal; /*!< Specify the initial value of count register. + This parameter can be a number between 0U and 0xFFFFU, inclusive. */ +} stc_tmra_init_t; + +/** + * @brief TMRA PWM configuration structure. + */ +typedef struct +{ + uint32_t u32StartPolarity; /*!< Specify the polarity when the specified TMRA channel start counting. + This parameter can be a value of @ref TMRA_PWM_Start_Polarity */ + uint32_t u32StopPolarity; /*!< Specify the polarity when the specified TMRA channel stop counting. + This parameter can be a value of @ref TMRA_PWM_Stop_Polarity */ + uint32_t u32CmpPolarity; /*!< Specify the polarity when the specified TMRA channel counting matches the compare register. + This parameter can be a value of @ref TMRA_PWM_Match_Cmp_Polarity */ + uint32_t u32PeriodPolarity; /*!< Specify the polarity when the specified TMRA channel counting matches the period register. + This parameter can be a value of @ref TMRA_PWM_Match_Period_Polarity */ + uint32_t u32ForcePolarity; /*!< Specify the polarity when the specified TMRA channel at the beginning of the next cycle. + This parameter can be a value of @ref TMRA_PWM_Force_Polarity */ +} stc_tmra_pwm_cfg_t; + +/** + * @brief TMRA hardware trigger condition configuration structure. + */ +typedef struct +{ + uint32_t u32StartCond; /*!< Specify the condition to start the specified TMRA unit. + This parameter can be a value of @ref TMRA_Hardware_Start_Condition */ + uint32_t u32StopCond; /*!< Specify the condition to stop the specified TMRA unit. + This parameter can be a value of @ref TMRA_Hardware_Stop_Condition */ + uint32_t u32ClrCond; /*!< Specify the condition to clear the specified TMRA unit's count register. + This parameter can be a value of @ref TMRA_Hardware_Clear_Condition */ +} stc_tmra_trig_cond_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Macros TMRA Global Macros + * @{ + */ + +/** + * @defgroup TMRA_Channel TMRA Channel + * @{ + */ +#define TMRA_CH_1 (0U) /*!< Channel 1 of TMRA. */ +#define TMRA_CH_2 (1U) /*!< Channel 2 of TMRA. */ +#define TMRA_CH_3 (2U) /*!< Channel 3 of TMRA. */ +#define TMRA_CH_4 (3U) /*!< Channel 4 of TMRA. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Input_Pin TMRA Input Pin + * @{ + */ +#define TMRA_PIN_TRIG (1UL << 0U) /*!< Pin TIMA__TRIG. */ +#define TMRA_PIN_CLKA (1UL << 1U) /*!< Pin TIMA__CLKA. */ +#define TMRA_PIN_CLKB (1UL << 2U) /*!< Pin TIMA__CLKB. */ +#define TMRA_PIN_PWM1 (1UL << 3U) /*!< Pin TIMA__PWM1. */ +#define TMRA_PIN_PWM2 (1UL << 4U) /*!< Pin TIMA__PWM2. */ +#define TMRA_PIN_PWM3 (1UL << 5U) /*!< Pin TIMA__PWM3. */ +#define TMRA_PIN_PWM4 (1UL << 6U) /*!< Pin TIMA__PWM4. */ +#define TMRA_PIN_ALL (TMRA_PIN_TRIG | \ + TMRA_PIN_CLKA | \ + TMRA_PIN_CLKB | \ + TMRA_PIN_PWM1 | \ + TMRA_PIN_PWM2 | \ + TMRA_PIN_PWM3 | \ + TMRA_PIN_PWM4) +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Direction TMRA Counting Direction + * @{ + */ +#define TMRA_DIR_DOWN (0x0U) /*!< TMRA count down. */ +#define TMRA_DIR_UP (TMRA_BCSTR_DIR) /*!< TMRA count up. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Mode TMRA Counting Mode + * @{ + */ +#define TMRA_MODE_SAWTOOTH (0x0U) /*!< Count mode is sawtooth wave. */ +#define TMRA_MODE_TRIANGLE (TMRA_BCSTR_MODE) /*!< Count mode is triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Clock_Source TMRA Counting Clock Source + * @note PCLK is automatically disabled when other clock is selected. + * @note Symmetric units: uint 1 and 2; uint 3 and 4; ...; uint 11 and 12. + * @{ + */ +#define TMRA_CLK_PCLK (0x0U) /*!< PCLK. PCLK0 for unit1 ~ uint4. PCLK1 for unit5 ~ uint12. */ + +#define TMRA_CLK_HW_UP_CLKAL_CLKBR (1UL << 0U) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKAL_CLKBF (1UL << 1U) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKAH_CLKBR (1UL << 2U) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKAH_CLKBF (1UL << 3U) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKBL_CLKAR (1UL << 4U) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKBL_CLKAF (1UL << 5U) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKBH_CLKAR (1UL << 6U) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CLK_HW_UP_CLKBH_CLKAF (1UL << 7U) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts up. */ +#define TMRA_CLK_HW_UP_TRIGR (1UL << 8U) /*!< When a rising edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CLK_HW_UP_TRIGF (1UL << 9U) /*!< When a falling edge occurred on TRIG, the counter register counts up. */ +#define TMRA_CLK_HW_UP_EVENT (1UL << 10U) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts up. */ +#define TMRA_CLK_HW_UP_SYM_OVF (1UL << 11U) /*!< When the symmetric unit overflow, the counter register counts up. */ +#define TMRA_CLK_HW_UP_SYM_UNF (1UL << 12U) /*!< When the symmetric unit underflow, the counter register counts up. */ +#define TMRA_CLK_HW_UP_ALL (0x1FFFUL) + +#define TMRA_CLK_HW_DOWN_CLKAL_CLKBR (1UL << 16U) /*!< When CLKA is low, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKAL_CLKBF (1UL << 17U) /*!< When CLKA is low, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKAH_CLKBR (1UL << 18U) /*!< When CLKA is high, a rising edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKAH_CLKBF (1UL << 19U) /*!< When CLKA is high, a falling edge is sampled on CLKB, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKBL_CLKAR (1UL << 20U) /*!< When CLKB is low, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKBL_CLKAF (1UL << 21U) /*!< When CLKB is low, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKBH_CLKAR (1UL << 22U) /*!< When CLKB is high, a rising edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_CLKBH_CLKAF (1UL << 23U) /*!< When CLKB is high, a falling edge is sampled on CLKA, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_TRIGR (1UL << 24U) /*!< When a rising edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_TRIGF (1UL << 25U) /*!< When a falling edge occurred on TRIG, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_EVENT (1UL << 26U) /*!< When the event specified by TMRA_HTSSR occurred, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_SYM_OVF (1UL << 27U) /*!< When the symmetric unit overflow, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_SYM_UNF (1UL << 28U) /*!< When the symmetric unit underflow, the counter register counts down. */ +#define TMRA_CLK_HW_DOWN_ALL (0x1FFF0000UL) +/** + * @} + */ + +/** + * @defgroup TMRA_PCLK_Divider TMRA PCLK Divider + * @note Clock divider is only valid for PCLK(PCLK0 for unit1 ~ uint4. PCLK1 for unit5 ~ uint12). + * @{ + */ +#define TMRA_PCLK_DIV1 (0x0U) /*!< The clock source of TMRA is PCLK. */ +#define TMRA_PCLK_DIV2 (TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 2. */ +#define TMRA_PCLK_DIV4 (TMRA_BCSTR_CKDIV_1) /*!< The clock source of TMRA is PCLK / 4. */ +#define TMRA_PCLK_DIV8 (TMRA_BCSTR_CKDIV_1 | \ + TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 8. */ +#define TMRA_PCLK_DIV16 (TMRA_BCSTR_CKDIV_2) /*!< The clock source of TMRA is PCLK / 16. */ +#define TMRA_PCLK_DIV32 (TMRA_BCSTR_CKDIV_2 | \ + TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 32. */ +#define TMRA_PCLK_DIV64 (TMRA_BCSTR_CKDIV_2 | \ + TMRA_BCSTR_CKDIV_1) /*!< The clock source of TMRA is PCLK / 64. */ +#define TMRA_PCLK_DIV128 (TMRA_BCSTR_CKDIV_2 | \ + TMRA_BCSTR_CKDIV_1 | \ + TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 128. */ +#define TMRA_PCLK_DIV256 (TMRA_BCSTR_CKDIV_3) /*!< The clock source of TMRA is PCLK / 256. */ +#define TMRA_PCLK_DIV512 (TMRA_BCSTR_CKDIV_3 | \ + TMRA_BCSTR_CKDIV_0) /*!< The clock source of TMRA is PCLK / 512. */ +#define TMRA_PCLK_DIV1024 (TMRA_BCSTR_CKDIV_3 | \ + TMRA_BCSTR_CKDIV_1) /*!< The clock source of TMRA is PCLK / 1024. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Count_Overflow_Operation TMRA Count Overflow Operation + * @note Count up corresponds to overflow, counter zeroing when counting value overflow period value. + * @note Count down corresponds to underflow, counter reload period value when counting value underflow 0. + * @{ + */ +#define TMRA_OVF_CNT_CONTINUE (0x0U) /*!< When counting overflow(or underflow), counting continue. */ +#define TMRA_OVF_CNT_STOP (TMRA_BCSTR_OVSTP) /*!< When counting overflow(or underflow), counting stop. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Interrupt_Type TMRA Interrupt Type + * @{ + */ +#define TMRA_INT_OVF (1UL << 12U) /*!< The interrupt of counting overflow. */ +#define TMRA_INT_UNF (1UL << 13U) /*!< The interrupt of counting underflow. */ +#define TMRA_INT_CMP_CH1 (1UL << 16U) /*!< The interrupt of compare-match of channel 1. */ +#define TMRA_INT_CMP_CH2 (1UL << 17U) /*!< The interrupt of compare-match of channel 2. */ +#define TMRA_INT_CMP_CH3 (1UL << 18U) /*!< The interrupt of compare-match of channel 3. */ +#define TMRA_INT_CMP_CH4 (1UL << 19U) /*!< The interrupt of compare-match of channel 4. */ +#define TMRA_INT_ALL (TMRA_INT_OVF | \ + TMRA_INT_UNF | \ + TMRA_INT_CMP_CH1 | \ + TMRA_INT_CMP_CH2 | \ + TMRA_INT_CMP_CH3 | \ + TMRA_INT_CMP_CH4) +/** + * @} + */ + +/** + * @defgroup TMRA_Event_Type TMRA Event Type + * @{ + */ +#define TMRA_EVENT_CMP_CH1 (TMRA_ECONR_ETEN1) /*!< The event of compare-match of channel 1. */ +#define TMRA_EVENT_CMP_CH2 (TMRA_ECONR_ETEN2) /*!< The event of compare-match of channel 2. */ +#define TMRA_EVENT_CMP_CH3 (TMRA_ECONR_ETEN3) /*!< The event of compare-match of channel 3. */ +#define TMRA_EVENT_CMP_CH4 (TMRA_ECONR_ETEN4) /*!< The event of compare-match of channel 4. */ +#define TMRA_EVENT_ALL (TMRA_EVENT_CMP_CH1 | \ + TMRA_EVENT_CMP_CH2 | \ + TMRA_EVENT_CMP_CH3 | \ + TMRA_EVENT_CMP_CH4) +/** + * @} + */ + +/** + * @defgroup TMRA_Status_Flag TMRA Status Flag + * @{ + */ +#define TMRA_FLAG_OVF (1UL << 14U) /*!< The flag of counting overflow. */ +#define TMRA_FLAG_UNF (1UL << 15U) /*!< The flag of counting underflow. */ +#define TMRA_FLAG_CMP_CH1 (1UL << 16U) /*!< The flag of compare-match of channel 1. */ +#define TMRA_FLAG_CMP_CH2 (1UL << 17U) /*!< The flag of compare-match of channel 2. */ +#define TMRA_FLAG_CMP_CH3 (1UL << 18U) /*!< The flag of compare-match of channel 3. */ +#define TMRA_FLAG_CMP_CH4 (1UL << 19U) /*!< The flag of compare-match of channel 4. */ +#define TMRA_FLAG_ALL (TMRA_FLAG_OVF | \ + TMRA_FLAG_UNF | \ + TMRA_FLAG_CMP_CH1 | \ + TMRA_FLAG_CMP_CH2 | \ + TMRA_FLAG_CMP_CH3 | \ + TMRA_FLAG_CMP_CH4) +/** + * @} + */ + +/** + * @defgroup TMRA_Cmp_Value_Cache_Condition TMRA Compare Value Cache Condition + * @{ + */ +#define TMRA_CACHE_COND_OVF_CLR (0x0U) /*!< This configuration value applies to non-triangular wave counting mode. \ + When counting overflow or underflow or counting register was cleared, \ + transfer CMPARm(m=2, 4) to CMPARn(n=1, 3). */ +#define TMRA_CACHE_COND_TW_PEAK (TMRA_BCONR_BSE0) /*!< In triangle wave count mode, when count reached peak, \ + transfer CMPARm(m=2, 4) to CMPARn(n=1, 3). */ +#define TMRA_CACHE_COND_TW_VALLEY (TMRA_BCONR_BSE1) /*!< In triangle wave count mode, when count reached valley, \ + transfer CMPARm(m=2, 4) to CMPARn(n=1, 3). */ +/** + * @} + */ + +/** + * @defgroup TMRA_Function_Mode TMRA Function Mode + * @{ + */ +#define TMRA_FUNC_COMPARE (0x0U) /*!< The function mode of TMRA is comparison ouput. */ +#define TMRA_FUNC_CAPTURE (TMRA_CCONR_CAPMD) /*!< The function mode of TMRA is capture the input. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Channel_Capture_Condition TMRA Capturing Condition Of Channel + * @note 'TMRA_CAPT_COND_TRIGR' and 'TMRA_CAPT_COND_TRIGF' are only valid for channel 4. + * @{ + */ +#define TMRA_CAPT_COND_INVALID (0x0U) /*!< The condition of capture is INVALID. */ +#define TMRA_CAPT_COND_PWMR (TMRA_CCONR_HICP0) /*!< The condition of capture is a rising edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_PWMF (TMRA_CCONR_HICP1) /*!< The condition of capture is a falling edge is sampled on pin TIMA__PWMn. */ +#define TMRA_CAPT_COND_EVENT (TMRA_CCONR_HICP2) /*!< The condition of capture is the specified event occurred. */ +#define TMRA_CAPT_COND_TRIGR (TMRA_CCONR_HICP3) /*!< The condition of capture is a rising edge is sampled on pin TIMA__TRIG. \ + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_TRIGF (TMRA_CCONR_HICP4) /*!< The condition of capture is a falling edge is sampled on pin TIMA__TRIG. \ + This condition is only valid for channel 4. */ +#define TMRA_CAPT_COND_ALL (TMRA_CAPT_COND_PWMR | \ + TMRA_CAPT_COND_PWMF | \ + TMRA_CAPT_COND_EVENT | \ + TMRA_CAPT_COND_TRIGR | \ + TMRA_CAPT_COND_TRIGF) +/** + * @} + */ + +/** + * @defgroup TMRA_Filter_Clock_Divider TMRA Filter Clock Divider + * @{ + */ +#define TMRA_FILTER_CLK_DIV1 (0x0U) /*!< The filter clock is PCLK / 1. */ +#define TMRA_FILTER_CLK_DIV4 (0x1U) /*!< The filter clock is PCLK / 4. */ +#define TMRA_FILTER_CLK_DIV16 (0x2U) /*!< The filter clock is PCLK / 16. */ +#define TMRA_FILTER_CLK_DIV64 (0x3U) /*!< The filter clock is PCLK / 64. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Out_Command TMRA PWM Out Command + * @{ + */ +#define TMRA_PWM_DISABLE (0x0U) /*!< Disable PWM output. */ +#define TMRA_PWM_ENABLE (TMRA_PCONR_OUTEN) /*!< Enable PWM output. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Start_Polarity TMRA PWM Start Polarity + * @note The 'START' in the following macros is the state 'counting start'. + * @{ + */ +#define TMRA_PWM_START_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_START_HIGH (TMRA_PCONR_STAC_0) /*!< PWM output high. */ +#define TMRA_PWM_START_KEEP (TMRA_PCONR_STAC_1) /*!< PWM output keeps the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Stop_Polarity TMRA PWM Stop Polarity + * @note The 'STOP' in the following macros is the state 'counting stop'. + * @{ + */ +#define TMRA_PWM_STOP_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_STOP_HIGH (TMRA_PCONR_STPC_0) /*!< PWM output high. */ +#define TMRA_PWM_STOP_KEEP (TMRA_PCONR_STPC_1) /*!< PWM output keeps the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Match_Cmp_Polarity TMRA PWM Polarity When Counting Matchs Compare Reference Value + * @{ + */ +#define TMRA_PWM_CMP_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_CMP_HIGH (TMRA_PCONR_CMPC_0) /*!< PWM output high. */ +#define TMRA_PWM_CMP_KEEP (TMRA_PCONR_CMPC_1) /*!< PWM output keeps the current polarity. */ +#define TMRA_PWM_CMP_REVERSE (TMRA_PCONR_CMPC_1 | \ + TMRA_PCONR_CMPC_0) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Match_Period_Polarity TMRA PWM Polarity When Counting Matchs Period Reference Value + * @{ + */ +#define TMRA_PWM_PERIOD_LOW (0x0U) /*!< PWM output low. */ +#define TMRA_PWM_PERIOD_HIGH (TMRA_PCONR_PERC_0) /*!< PWM output high. */ +#define TMRA_PWM_PERIOD_KEEP (TMRA_PCONR_PERC_1) /*!< PWM output keeps the current polarity. */ +#define TMRA_PWM_PERIOD_REVERSE (TMRA_PCONR_PERC_1 | \ + TMRA_PCONR_PERC_0) /*!< PWM output reverses the current polarity. */ +/** + * @} + */ + +/** + * @defgroup TMRA_PWM_Force_Polarity TMRA PWM Force Polarity + * @{ + */ +#define TMRA_PWM_FORCE_INVALID (0x0U) /*!< Force polarity is invalid. */ +#define TMRA_PWM_FORCE_LOW (TMRA_PCONR_FORC_1) /*!< Force the PWM output low at the beginning of the next cycle. \ + The beginning of the next cycle: overflow position or underflow position \ + of sawtooth wave; valley position of triangle wave. */ +#define TMRA_PWM_FORCE_HIGH (TMRA_PCONR_FORC_1 | \ + TMRA_PCONR_FORC_0) /*!< Force the PWM output high at the beginning of the next cycle. \ + The beginning of the next cycle: overflow position or underflow position \ + of sawtooth wave; valley position of triangle wave. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Start_Condition TMRA Hardware Start Condition + * @{ + */ +#define TMRA_START_COND_INVALID (0x0U) /*!< The condition of start is INVALID. */ +#define TMRA_START_COND_TRIGR (TMRA_HCONR_HSTA0) /*!< 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. \ + 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_TRIGF (TMRA_HCONR_HSTA1) /*!< 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. \ + 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. */ +#define TMRA_START_COND_EVENT (TMRA_HCONR_HSTA2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_START_COND_ALL (TMRA_START_COND_TRIGR | \ + TMRA_START_COND_TRIGF | \ + TMRA_START_COND_EVENT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Stop_Condition TMRA Hardware Stop Condition + * @{ + */ +#define TMRA_STOP_COND_INVALID (0x0U) /*!< The condition of stop is INVALID. */ +#define TMRA_STOP_COND_TRIGR (TMRA_HCONR_HSTP0) /*!< The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_TRIGF (TMRA_HCONR_HSTP1) /*!< The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. */ +#define TMRA_STOP_COND_EVENT (TMRA_HCONR_HSTP2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_STOP_COND_ALL (TMRA_STOP_COND_TRIGR | \ + TMRA_STOP_COND_TRIGF | \ + TMRA_STOP_COND_EVENT) +/** + * @} + */ + +/** + * @defgroup TMRA_Hardware_Clear_Condition TMRA Hardware Clear Condition + * @note Symmetric units: uint 1 and 2; uint 3 and 4; ... ; uint 11 and 12. + * @{ + */ +#define TMRA_CLR_COND_INVALID (0x0U) /*!< The condition of clear is INVALID. */ +#define TMRA_CLR_COND_TRIGR (TMRA_HCONR_HCLE0) /*!< The condition is that a rising edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_TRIGF (TMRA_HCONR_HCLE1) /*!< The condition is that a falling edge is sampled on TRIG of the current TMRA unit. */ +#define TMRA_CLR_COND_EVENT (TMRA_HCONR_HCLE2) /*!< The condition is that the event which is set in register TMRA_HTSSR0 has occurred. */ +#define TMRA_CLR_COND_SYM_TRIGR (TMRA_HCONR_HCLE3) /*!< The condition is that a rising edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_SYM_TRIGF (TMRA_HCONR_HCLE4) /*!< The condition is that a falling edge is sampled on TRIG of the symmetric unit. */ +#define TMRA_CLR_COND_PWM3R (TMRA_HCONR_HCLE5) /*!< The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_PWM3F (TMRA_HCONR_HCLE6) /*!< The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. */ +#define TMRA_CLR_COND_ALL (TMRA_CLR_COND_TRIGR | \ + TMRA_CLR_COND_TRIGF | \ + TMRA_CLR_COND_EVENT | \ + TMRA_CLR_COND_SYM_TRIGR | \ + TMRA_CLR_COND_SYM_TRIGF | \ + TMRA_CLR_COND_PWM3R | \ + TMRA_CLR_COND_PWM3F) +/** + * @} + */ + +/** + * @defgroup TMRA_Event_Usage TMRA Event Usage + * @{ + */ +#define TMRA_EVENT_USAGE_CNT (0U) /*!< The specified event is used for counting. */ +#define TMRA_EVENT_USAGE_CAPT (1U) /*!< The specified event is used for capturing. */ +/** + * @} + */ + +/** + * @defgroup TMRA_Common_Trigger_Sel TMRA Common Trigger Source Select + * @{ + */ +#define TMRA_COM_TRIG1 (AOS_TMRA_HTSSR_COMTRG_EN_0) +#define TMRA_COM_TRIG2 (AOS_TMRA_HTSSR_COMTRG_EN_1) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TMRA_Global_Functions + * @{ + */ + en_result_t TMRA_Init(M4_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcInit); + en_result_t TMRA_StructInit(stc_tmra_init_t *pstcInit); + void TMRA_DeInit(M4_TMRA_TypeDef *TMRAx); + + void TMRA_SetCntVal(M4_TMRA_TypeDef *TMRAx, uint32_t u32Val); + uint32_t TMRA_GetCntVal(const M4_TMRA_TypeDef *TMRAx); + void TMRA_SetPeriodVal(M4_TMRA_TypeDef *TMRAx, uint32_t u32Val); + uint32_t TMRA_GetPeriodVal(const M4_TMRA_TypeDef *TMRAx); + + void TMRA_SetFuncMode(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32FuncMode); + + void TMRA_SetCmpVal(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Val); + uint32_t TMRA_GetCmpVal(const M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh); + + en_result_t TMRA_PWM_Config(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, const stc_tmra_pwm_cfg_t *pstcCfg); + en_result_t TMRA_PWM_StructInit(stc_tmra_pwm_cfg_t *pstcCfg); + void TMRA_PWM_Cmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, en_functional_state_t enNewState); + + void TMRA_FilterConfig(M4_TMRA_TypeDef *TMRAx, uint8_t u8InputPin, uint32_t u32ClkDiv); + void TMRA_FilterCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8InputPin, en_functional_state_t enNewState); + + void TMRA_SetCaptCond(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Cond); + en_result_t TMRA_SetTrigCond(M4_TMRA_TypeDef *TMRAx, const stc_tmra_trig_cond_t *pstcCond); + en_result_t TMRA_TrigCondStructInit(stc_tmra_trig_cond_t *pstcCond); + void TMRA_SetTriggerSrc(M4_TMRA_TypeDef *TMRAx, uint8_t u8EvtUsage, en_event_src_t enEvent); + void TMRA_ComTriggerCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8EvtUsage, \ + uint32_t u32ComTrig, en_functional_state_t enNewState); + + void TMRA_CmpValCacheConfig(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32CacheCond); + void TMRA_CmpValCacheCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, en_functional_state_t enNewState); + + void TMRA_SetOvfOperation(M4_TMRA_TypeDef *TMRAx, uint32_t u32OvfOp); + void TMRA_SyncStartCmd(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState); + + void TMRA_IntCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState); + void TMRA_EventCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32EvtType, en_functional_state_t enNewState); + +en_flag_status_t TMRA_GetStatus(const M4_TMRA_TypeDef *TMRAx, uint32_t u32Flag); + void TMRA_ClrStatus(M4_TMRA_TypeDef *TMRAx, uint32_t u32Flag); + + void TMRA_Start(M4_TMRA_TypeDef *TMRAx); + void TMRA_Stop(M4_TMRA_TypeDef *TMRAx); + + void TMRA_SetCntDir(M4_TMRA_TypeDef *TMRAx, uint32_t u32CntDir); + void TMRA_SetCntMode(M4_TMRA_TypeDef *TMRAx, uint32_t u32CntMode); + void TMRA_SetPCLKDiv(M4_TMRA_TypeDef *TMRAx, uint32_t u32ClkDiv); + uint32_t TMRA_GetCntDir(const M4_TMRA_TypeDef *TMRAx); + + void TMRA_SetClkSrc(M4_TMRA_TypeDef *TMRAx, uint32_t u32ClkSrc); + void TMRA_HwClkSrcCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32HwClkSrc, en_functional_state_t enNewState); + + void TMRA_PWM_SetStartPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity); + void TMRA_PWM_SetStopPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity); + void TMRA_PWM_SetMatchCmpPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity); + void TMRA_PWM_SetMatchPeriodPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity); + void TMRA_PWM_SetForcePolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity); + + void TMRA_CaptCondCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32CaptCond, en_functional_state_t enNewState); + void TMRA_TrigCondCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32TrigCond, en_functional_state_t enNewState); +/** + * @} + */ + +#endif /* DDL_TMRA_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_TMRA_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_trng.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_trng.h new file mode 100644 index 0000000000000000000000000000000000000000..c4e6e44408069799dbb29cb44f274adc6b3019f2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_trng.h @@ -0,0 +1,124 @@ +/** + ******************************************************************************* + * @file hc32f4a0_trng.h + * @brief This file contains all the functions prototypes of the TRNG driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_TRNG_H__ +#define __HC32F4A0_TRNG_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_TRNG + * @{ + */ + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/** + * @defgroup TRNG_Global_Macros TRNG Global Macros + * @{ + */ + +/** + * @defgroup TRNG_Load_New_Value TRNG load new value + * @{ + */ +#define TRNG_RELOAD_ENABLE (TRNG_MR_LOAD) /* Enable load new initial values. */ +#define TRNG_RELOAD_DISABLE (0x00000000UL) /* Disable load new initial values. */ +/** + * @} + */ + +/** + * @defgroup TRNG_Shift_Control TRNG Shift Control + * @{ + */ +#define TRNG_SHIFT_COUNT_32 (0x0000000CUL) /* Shift 32 times when capturing random noise. */ +#define TRNG_SHIFT_COUNT_64 (0x00000010UL) /* Shift 64 times when capturing random noise. */ +#define TRNG_SHIFT_COUNT_128 (0x00000014UL) /* Shift 128 times when capturing random noise. */ +#define TRNG_SHIFT_COUNT_256 (0x00000018UL) /* Shift 256 times when capturing random noise. */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup TRNG_Global_Functions + * @{ + */ +void TRNG_SetShiftCnt(uint32_t u32ShiftCount); +void TRNG_ReloadCmd(uint32_t u32ReloadCmd); + +en_result_t TRNG_Generate(uint32_t au32Random[]); +/** + * @} + */ + +#endif /* DDL_TRNG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_TRNG_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_usart.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..66987adf8ada94daf52b136808da4a6394487f8a --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_usart.h @@ -0,0 +1,611 @@ +/** + ******************************************************************************* + * @file hc32f4a0_usart.h + * @brief This file contains all the functions prototypes of the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_USART_H__ +#define __HC32F4A0_USART_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_USART + * @{ + */ + +#if (DDL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup USART_Global_Types USART Global Types + * @{ + */ + +/** + * @brief UART mode initialization structure definition + */ +typedef struct +{ + uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */ + + uint32_t u32ClkMode; /*!< Clock mode. + This parameter can be a value of @ref USART_Clock_Mode */ + + uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK. + This parameter can be a value of @ref USART_PCLK_Division */ + + uint32_t u32Parity; /*!< Parity format. + This parameter can be a value of @ref USART_Parity_Control */ + + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Length_Bits */ + + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t u32OversamplingBits; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Oversampling_Bits */ + + uint32_t u32BitDirection; /*!< Significant bit. + This parameter can be a value of @ref USART_Significant_Bit */ + + uint32_t u32NoiseFilterState; /*!< RX pin noise filter state. + This parameter can be a value of @ref USART_Noise_Filter_State */ + + uint32_t u32SbDetectPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Detect_Polarity */ + + uint32_t u32HwFlowCtrl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_uart_init_t; + +/** + * @brief UART multiple-processor initialization structure definition + */ +typedef struct +{ + uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */ + + uint32_t u32ClkMode; /*!< Clock mode. + This parameter can be a value of @ref USART_Clock_Mode */ + + uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK. + This parameter can be a value of @ref USART_PCLK_Division */ + + uint32_t u32DataWidth; /*!< Data width. + This parameter can be a value of @ref USART_Data_Length_Bits */ + + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t u32OversamplingBits; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Oversampling_Bits */ + + uint32_t u32BitDirection; /*!< Significant bit. + This parameter can be a value of @ref USART_Significant_Bit */ + + uint32_t u32NoiseFilterState; /*!< RX pin noise filter state. + This parameter can be a value of @ref USART_Noise_Filter_State */ + + uint32_t u32SbDetectPolarity; /*!< Start Bit Detect Polarity. + This parameter can be a value of @ref USART_Start_Bit_Detect_Polarity */ + + uint32_t u32HwFlowCtrl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_multiprocessor_init_t; + +/** + * @brief LIN mode initialization structure definition + */ +typedef struct +{ + uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */ + + uint32_t u32ClkMode; /*!< Clock mode. + This parameter can be a value of @ref USART_Clock_Mode */ + + uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK. + This parameter can be a value of @ref USART_PCLK_Division */ + + uint32_t u32BmcPclkDiv; /*!< BMC PCLK division. The PCLK division function is valid when clock source is PCLK. + This parameter can be a value of @ref USART_LIN_BMC_PCLK_Division */ + + uint32_t u32OversamplingBits; /*!< Oversampling Bits. + This parameter can be a value of @ref USART_Oversampling_Bits */ + + uint32_t u32DetectBreakLen; /*!< Detect break length. + This parameter can be a value of @ref USART_LIN_Detect_Break_Length */ + + uint32_t u32SendBreakLen; /*!< Send break length. + This parameter can be a value of @ref USART_LIN_Send_Break_Length */ + + uint32_t u32SendBreakMode; /*!< Send break mode. + This parameter can be a value of @ref USART_LIN_Send_Break_Mode */ +} stc_usart_lin_init_t; + +/** + * @brief Smart card mode initialization structure definition + */ +typedef struct +{ + uint32_t u32Baudrate; /*!< UART baudrate */ + + uint32_t u32ClkMode; /*!< Clock mode. + This parameter can be a value of @ref USART_Clock_Mode */ + + uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK. + This parameter can be a value of @ref USART_PCLK_Division */ + + uint32_t u32StopBit; /*!< Stop Bits. + This parameter can be a value of @ref USART_Stop_Bits */ + + uint32_t u32BitDirection; /*!< Significant bit. + This parameter can be a value of @ref USART_Significant_Bit */ +} stc_usart_smartcard_init_t; + +/** + * @brief clock synchronization mode initialization structure definition + */ +typedef struct +{ + uint32_t u32Baudrate; /*!< UART baudrate. The baudrate is valid when clock source is PCLK. */ + + uint32_t u32ClkMode; /*!< Clock mode. + This parameter can be a value of @ref USART_Clock_Mode */ + + uint32_t u32PclkDiv; /*!< PCLK division. The PCLK division function is valid when clock source is PCLK. + This parameter can be a value of @ref USART_PCLK_Division */ + + uint32_t u32BitDirection; /*!< Significant bit. + This parameter can be a value of @ref USART_Significant_Bit */ + + uint32_t u32HwFlowCtrl; /*!< Hardware flow control. + This parameter can be a value of @ref USART_Hardware_Flow_Control */ +} stc_usart_clksync_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Global_Macros USART Global Macros + * @{ + */ + +/** + * @defgroup USART_Flag USART Flag + * @{ + */ +#define USART_FLAG_PE (USART_SR_PE) /*!< Parity error flag */ +#define USART_FLAG_FE (USART_SR_FE) /*!< Framing error flag */ +#define USART_FLAG_ORE (USART_SR_ORE) /*!< Overrun error flag */ +#define USART_FLAG_BE (USART_SR_BE) /*!< LIN bus error flag */ +#define USART_FLAG_RXNE (USART_SR_RXNE) /*!< Receive data register not empty flag */ +#define USART_FLAG_TC (USART_SR_TC) /*!< Transmission complete flag */ +#define USART_FLAG_TXE (USART_SR_TXE) /*!< Transmit data register empty flag */ +#define USART_FLAG_RTOF (USART_SR_RTOF) /*!< Receive timeout flag */ +#define USART_FLAG_LBD (USART_SR_LBD) /*!< LIN break signal detection flag */ +#define USART_FLAG_WKUP (USART_SR_WKUP) /*!< LIN wakeup signal detection flag */ +#define USART_FLAG_MPB (USART_SR_MPB) /*!< Receive processor ID flag */ +/** + * @} + */ + +/** + * @defgroup USART_Transmission_Type USART Transmission Type + * @{ + */ +#define USART_TRANSMISSION_ID (USART_DR_MPID) +#define USART_TRANSMISSION_DATA (0UL) +/** + * @} + */ + +/** + * @defgroup USART_Clear_Flag USART Clear Flag + * @{ + */ +#define USART_CLEAR_FLAG_PE (USART_CR1_CPE) /*!< Clear Parity error flag */ +#define USART_CLEAR_FLAG_FE (USART_CR1_CFE) /*!< Clear Framing error flag */ +#define USART_CLEAR_FLAG_ORE (USART_CR1_CORE) /*!< Clear Overrun error flag */ +#define USART_CLEAR_FLAG_RTOF (USART_CR1_CRTOF) /*!< Clear RX timeout flag */ +#define USART_CLEAR_FLAG_BE (USART_CR1_CBE) /*!< Clear LIN bus error flag */ +#define USART_CLEAR_FLAG_WKUP (USART_CR1_CWKUP) /*!< Clear LIN wakeup signal flag */ +#define USART_CLEAR_FLAG_LBD (USART_CR1_CLBD) /*!< Clear LIN break detection flag */ +/** + * @} + */ + +/** + * @defgroup USART_Transmit_Receive_Function USART Transmit/Receive Function + * @{ + */ +#define USART_RX (USART_CR1_RE) /*!< USART RX function */ +#define USART_TX (USART_CR1_TE) /*!< USART TX function */ +#define USART_RTO (USART_CR1_RTOE) /*!< USART RX timerout function */ +#define USART_INT_RX (USART_CR1_RIE) /*!< USART receive data register not empty && receive error interrupt */ +#define USART_INT_TXE (USART_CR1_TXEIE) /*!< USART transmit data register empty interrupt */ +#define USART_INT_TC (USART_CR1_TCIE) /*!< USART transmission complete interrupt */ +#define USART_INT_RTO (USART_CR1_RTOIE) /*!< USART RX timerout interrupt */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Function USART LIN Function + * @{ + */ +#define USART_LIN (USART_CR2_LINEN) /*!< USART LIN function */ +#define USART_LIN_WKUP (USART_CR2_WKUPE) /*!< USART LIN wakeup signal detect function */ +#define USART_LIN_INT_WKUP (USART_CR2_WKUPIE) /*!< USART LIN wakeup signal detect interrupt function */ +#define USART_LIN_BUSERR (USART_CR2_BEE) /*!< USART LIN bus error detect function */ +#define USART_LIN_INT_BUSERR (USART_CR2_BEIE) /*!< USART LIN bus error detect interrupt function */ +#define USART_LIN_INT_BREAK (USART_CR2_LBDIE) /*!< USART LIN break field detect interrupt function */ +/** + * @} + */ + +/** + * @defgroup USART_Parity_Control USART Parity Control + * @{ + */ +#define USART_PARITY_NONE (0UL) /*!< Parity control disabled */ +#define USART_PARITY_EVEN (USART_CR1_PCE) /*!< Parity control enabled and Even Parity is selected */ +#define USART_PARITY_ODD (USART_CR1_PCE | \ + USART_CR1_PS) /*!< Parity control enabled and Odd Parity is selected */ +/** + * @} + */ + +/** + * @defgroup USART_Data_Length_Bits Data Length Bits + * @{ + */ +#define USART_DATA_LENGTH_8BIT (0UL) /*!< 8 bits */ +#define USART_DATA_LENGTH_9BIT (USART_CR1_M) /*!< 9 bits */ +/** + * @} + */ + +/** + * @defgroup USART_Oversampling_Bits USART Oversampling Bits + * @{ + */ +#define USART_OVERSAMPLING_16BIT (0UL) /*!< Oversampling by 16 bits */ +#define USART_OVERSAMPLING_8BIT (USART_CR1_OVER8) /*!< Oversampling by 8 bits */ +/** + * @} + */ + +/** + * @defgroup USART_Significant_Bit USART Significant Bit + * @{ + */ +#define USART_LSB (0UL) /*!< LSB(Least Significant Bit) */ +#define USART_MSB (USART_CR1_ML) /*!< MSB(Most Significant Bit) */ +/** + * @} + */ + +/** + * @defgroup USART_Noise_Filter_State USART Noise Filter State + * @{ + */ +#define USART_NOISE_FILTER_DISABLE (0UL) /*!< Disable noise filter */ +#define USART_NOISE_FILTER_ENABLE (USART_CR1_NFE) /*!< Enable noise filter */ +/** + * @} + */ + +/** + * @defgroup USART_Start_Bit_Detect_Polarity USART Start Bit Detect Polarity + * @{ + */ +#define USART_SB_DETECT_LOW (0UL) /*!< Detect RX pin low level */ +#define USART_SB_DETECT_FALLING (USART_CR1_SBS) /*!< Detect RX pin falling edge */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Send_Break_Mode USART LIN Send Break Mode + * @{ + */ +#define USART_LIN_SEND_BREAK_MODE_SBK (0UL) /*!< Start send break after USART_CR2 SBK bit set 1 value */ +#define USART_LIN_SEND_BREAK_MODE_TDR (USART_CR2_SBKM) /*!< Start send break after USART_DR TDR write 0x00 value */ +/** + * @} + */ + +/** + * @defgroup USART_Multiple_Processor_State USART Multiple Processor State + * @{ + */ +#define USART_MULTIPLE_PROCESSOR_DISABLE (0UL) /*!< Disable multiple processor function */ +#define USART_MULTIPLE_PROCESSOR_ENABLE (USART_CR2_MPE) /*!< Enable multiple processor function */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Detect_Break_Length USART LIN Detect Break Length + * @{ + */ +#define USART_LIN_DETECT_BREAK_10BIT (0UL) /*!< Detect break 10-bit */ +#define USART_LIN_DETECT_BREAK_11BIT (USART_CR2_LBDL) /*!< Detect break 11-bit */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_Send_Break_Length USART LIN Send Break Length + * @{ + */ +#define USART_LIN_SEND_BREAK_10BIT (0UL) /*!< Send break 10-bit */ +#define USART_LIN_SEND_BREAK_11BIT (USART_CR2_SBKL_0) /*!< Send break 11-bit */ +#define USART_LIN_SEND_BREAK_13BIT (USART_CR2_SBKL_1) /*!< Send break 13-bit */ +#define USART_LIN_SEND_BREAK_14BIT (USART_CR2_SBKL) /*!< Send break 14-bit */ +/** + * @} + */ + +/** + * @defgroup USART_Clock_Mode USART Clock Mode Selection + * @{ + */ +#define USART_EXTCLK (USART_CR2_CLKC_1) /*!< Select external clock source. */ +#define USART_INTERNCLK_OUTPUT (USART_CR2_CLKC_0) /*!< Select internal clock source and output clock. */ +#define USART_INTERNCLK_NONE_OUTPUT (0UL) /*!< Select internal clock source and don't output clock */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Bits USART Stop Bits + * @{ + */ +#define USART_STOPBIT_1BIT (0UL) /*!< 1 stop bit */ +#define USART_STOPBIT_2BIT (USART_CR2_STOP) /*!< 2 stop bit */ +/** + * @} + */ + +/** + * @defgroup USART_DUPLEX_SEL USART Half-duplex/Full-duplex Selection + * @{ + */ +#define USART_FULLDUPLEX_MODE (0UL) /*!< USART full-duplex mode */ +#define USART_HALFDUPLEX_MODE (USART_CR3_HDSEL) /*!< USART half-duplex mode */ +/** + * @} + */ + +/** + * @defgroup USART_Hardware_Flow_Control USART Hardware Flow Control RTS/CTS + * @{ + */ +#define USART_HWFLOWCTRL_NONE (0UL) /*!< Disable USART hardware flow controle */ +#define USART_HWFLOWCTRL_RTS (USART_CR3_RTSE) /*!< USART hardware flow control RTS mode */ +#define USART_HWFLOWCTRL_CTS (USART_CR3_CTSE) /*!< USART hardware flow control CTS mode */ +#define USART_HWFLOWCTRL_RTS_CTS (USART_CR3_RTSE | \ + USART_CR3_CTSE) /*!< USART hardware flow control RTS and CTS mode */ +/** + * @} + */ + +/** + * @defgroup USART_Smartcard_ETU_Clock USART Smartcard ETU Clock + * @{ + */ +#define USART_SC_ETU_CLK_32 (0UL) /*!< 1 etu = 32/f */ +#define USART_SC_ETU_CLK_64 (USART_CR3_BCN_0) /*!< 1 etu = 64/f */ +#define USART_SC_ETU_CLK_128 (USART_CR3_BCN_1 | \ + USART_CR3_BCN_0) /*!< 1 etu = 128/f */ +#define USART_SC_ETU_CLK_256 (USART_CR3_BCN_2 | \ + USART_CR3_BCN_0) /*!< 1 etu = 256/f */ +#define USART_SC_ETU_CLK_372 (USART_CR3_BCN_2 | \ + USART_CR3_BCN_1) /*!< 1 etu = 372/f */ +/** + * @} + */ + +/** + * @defgroup USART_PCLK_Division USART PCLK Clock Prescaler Division + * @{ + */ +#define USART_PCLK_DIV1 (0UL) /*!< PCLK */ +#define USART_PCLK_DIV4 (USART_PR_PSC_0) /*!< PCLK/4 */ +#define USART_PCLK_DIV16 (USART_PR_PSC_1) /*!< PCLK/16 */ +#define USART_PCLK_DIV64 (USART_PR_PSC) /*!< PCLK/64 */ +/** + * @} + */ + +/** + * @defgroup USART_LIN_BMC_PCLK_Division USART LIN Baudrate Measure Counter PCLK Division + * @{ + */ +#define USART_LIN_BMC_PCLK_DIV1 (0UL) /*!< PCLK */ +#define USART_LIN_BMC_PCLK_DIV2 (USART_PR_LBMPSC_0) /*!< PCLK/2 */ +#define USART_LIN_BMC_PCLK_DIV4 (USART_PR_LBMPSC_1) /*!< PCLK/4 */ +#define USART_LIN_BMC_PCLK_DIV8 (USART_PR_LBMPSC) /*!< PCLK/8 */ +/** + * @} + */ + +/** + * @defgroup USART_Stop_Mode_Noise_Filter USART Stop Mode Noise_Filter + * @{ + */ +#define USART_STOP_MODE_FILTER_NONE (0UL) /*!< Disable noise filter */ +#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_1 (PERIC_USART1_NFC_NFE) /*!< Filter width level 1 */ +#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_2 (PERIC_USART1_NFC_NFE | \ + PERIC_USART1_NFC_NFS_0) /*!< Filter width level 2 */ +#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_3 (PERIC_USART1_NFC_NFE | \ + PERIC_USART1_NFC_NFS_1) /*!< Filter width level 3 */ +#define USART_STOP_MODE_FILTER_WIDTH_LEVEL_4 (PERIC_USART1_NFC_NFE | \ + PERIC_USART1_NFC_NFS) /*!< Filter width level 4 */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup USART_Global_Functions + * @{ + */ +en_result_t USART_UartInit(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInit); +en_result_t USART_HalfduplexInit(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInit); +en_result_t USART_UartStructInit(stc_usart_uart_init_t *pstcInit); +en_result_t USART_MultiProcessorInit(M4_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcInit); +en_result_t USART_MultiProcessorStructInit(stc_usart_multiprocessor_init_t *pstcInit); +en_result_t USART_LinInit(M4_USART_TypeDef *USARTx, + const stc_usart_lin_init_t *pstcInit); +en_result_t USART_LinStructInit(stc_usart_lin_init_t *pstcInit); +en_result_t USART_SmartcardInit(M4_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcInit); +en_result_t USART_SmartcardStructInit(stc_usart_smartcard_init_t *pstcInit); +en_result_t USART_ClkSyncInit(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInit); +en_result_t USART_ClkSyncStructInit(stc_usart_clksync_init_t *pstcInit); +void USART_DeInit(M4_USART_TypeDef *USARTx); +void USART_FuncCmd(M4_USART_TypeDef *USARTx, + uint32_t u32Func, + en_functional_state_t enNewState); +en_functional_state_t USART_GetFuncState(const M4_USART_TypeDef *USARTx, + uint32_t u32Func); +en_flag_status_t USART_GetStatus(const M4_USART_TypeDef *USARTx, + uint32_t u32Flag); +void USART_ClearStatus(M4_USART_TypeDef *USARTx, uint32_t u32Flag); +void USART_SetTransmissionType(M4_USART_TypeDef *USARTx, uint32_t u32Type); +uint32_t USART_GetTransmissionType(const M4_USART_TypeDef *USARTx); +void USART_SetParity(M4_USART_TypeDef *USARTx, uint32_t u32Parity); +uint32_t USART_GetParity(const M4_USART_TypeDef *USARTx); +void USART_SetDataWidth(M4_USART_TypeDef *USARTx, uint32_t u32DataWidth); +uint32_t USART_GetDataWidth(const M4_USART_TypeDef *USARTx); +void USART_SetOversmaplingBits(M4_USART_TypeDef *USARTx, + uint32_t u32OversamplingBits); +uint32_t USART_GetOversmaplingBits(const M4_USART_TypeDef *USARTx); +void USART_SetBitDirection(M4_USART_TypeDef *USARTx, uint32_t u32BitDir); +uint32_t USART_GetBitDirection(const M4_USART_TypeDef *USARTx); +void USART_SetSbDetectPolarity(M4_USART_TypeDef *USARTx, + uint32_t u32Polarity); +uint32_t USART_GetSbDetectPolarity(const M4_USART_TypeDef *USARTx); +void USART_SetClockMode(M4_USART_TypeDef *USARTx, uint32_t u32ClkMode); +uint32_t USART_GetClockMode(const M4_USART_TypeDef *USARTx); +void USART_SetStopBits(M4_USART_TypeDef *USARTx, uint32_t u32StopBits); +uint32_t USART_GetStopBits(const M4_USART_TypeDef *USARTx); +uint16_t USART_RecData(const M4_USART_TypeDef *USARTx); +void USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data); +void USART_SendId(M4_USART_TypeDef *USARTx, uint16_t u16ID); +void USART_SilenceCmd(M4_USART_TypeDef *USARTx, + en_functional_state_t enNewState); +void USART_LinLoopCmd(M4_USART_TypeDef *USARTx, + en_functional_state_t enNewState); +void USART_LinRequestBreakSending(M4_USART_TypeDef *USARTx); +en_flag_status_t USART_GetLinRequestBreakStatus(const M4_USART_TypeDef *USARTx); +void USART_SetLinBreakMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode); +uint32_t USART_GetLinBreakMode(const M4_USART_TypeDef *USARTx); +void USART_SetDuplexMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode); +uint32_t USART_GetDuplexMode(const M4_USART_TypeDef *USARTx); +void USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, uint32_t u32HwFlowCtrl); +uint32_t USART_GetHwFlowCtrl(const M4_USART_TypeDef *USARTx); +void USART_SetSmartcardEtuClk(M4_USART_TypeDef *USARTx, + uint32_t u32EtuClk); +uint32_t USART_GetSmartcardEtuClk(const M4_USART_TypeDef *USARTx); +void USART_SetPclkDiv(M4_USART_TypeDef *USARTx, + uint32_t u32PclkDiv); +uint32_t USART_GetPclkDiv(const M4_USART_TypeDef *USARTx); +void USART_SetLinBmcPclkDiv(M4_USART_TypeDef *USARTx, + uint32_t u32PclkDiv); +uint32_t USART_GetLinBmcPclkDiv(const M4_USART_TypeDef *USARTx); +void USART_SetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx, + uint32_t u32Filter); +uint32_t USART_GetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx); +void USART_LinFuncCmd(M4_USART_TypeDef *USARTx, + uint32_t u32Func, + en_functional_state_t enNewState); +en_functional_state_t USART_GetLinFuncState(const M4_USART_TypeDef *USARTx, + uint32_t u32Func); +uint32_t USART_GetLinMeasureCnt(const M4_USART_TypeDef *USARTx); +uint32_t USART_GetLinMeasureBaudrate(const M4_USART_TypeDef *USARTx); +void USART_SetLinDetectBreakLen(M4_USART_TypeDef *USARTx, + uint32_t u32Len); +uint32_t USART_GetLinDetectBreakLen(const M4_USART_TypeDef *USARTx); +void USART_SetLinSendBreakLen(M4_USART_TypeDef *USARTx, uint32_t u32Len); +uint32_t USART_GetLinSendBreakLen(const M4_USART_TypeDef *USARTx); +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate, + float32_t *pf32Err); + +/** + * @} + */ + +#endif /* DDL_USART_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_utility.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_utility.h new file mode 100644 index 0000000000000000000000000000000000000000..5fe838fef0c065ba8f94d476223d6cd39a61a071 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_utility.h @@ -0,0 +1,120 @@ +/** + ******************************************************************************* + * @file hc32f4a0_utility.h + * @brief This file contains all the functions prototypes of the DDL utility. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_UTILITY_H__ +#define __HC32F4A0_UTILITY_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_UTILITY + * @{ + */ + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup UTILITY_Global_Functions + * @{ + */ + +/* Imprecise delay */ +void DDL_DelayMS(uint32_t u32Cnt); +void DDL_DelayUS(uint32_t u32Cnt); + +/* Systick functions */ +en_result_t SysTick_Init(uint32_t u32Freq); +void SysTick_Delay(uint32_t u32Delay); +void SysTick_IncTick(void); +uint32_t SysTick_GetTick(void); +void SysTick_Suspend(void); +void SysTick_Resume(void); + +/* You can add your own assert functions by implement the function DDL_AssertHandler + definition follow the function DDL_AssertHandler declaration */ +#ifdef __DEBUG + #define DDL_ASSERT(x) \ + do{ \ + ((x) ? (void)0 : DDL_AssertHandler(__FILE__, __LINE__)); \ + }while(0) + /* Exported function */ + void DDL_AssertHandler(const char *file, int line); +#else + #define DDL_ASSERT(x) ((void)0U) +#endif /* __DEBUG */ + +#if (DDL_PRINT_ENABLE == DDL_ON) +#include + +en_result_t DDL_PrintfInit(void); +#endif + +/** + * @} + */ + +#endif /* DDL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_UTILITY_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_wdt.h b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_wdt.h new file mode 100644 index 0000000000000000000000000000000000000000..a4cfc10f29a12efa6ba9afab1d97e4c7367b7a98 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/inc/hc32f4a0_wdt.h @@ -0,0 +1,228 @@ +/** + ******************************************************************************* + * @file hc32f4a0_wdt.h + * @brief This file contains all the functions prototypes of the WDT driver + * library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ +#ifndef __HC32F4A0_WDT_H__ +#define __HC32F4A0_WDT_H__ + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_common.h" +#include "ddl_config.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @addtogroup DDL_WDT + * @{ + */ + +#if (DDL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Types WDT Global Types + * @{ + */ + +/** + * @brief WDT Init structure definition + */ +typedef struct +{ + uint32_t u32CountCycle; /*!< Specifies the WDT Count Cycle. + This parameter can be a value of @ref WDT_Counter_Cycle */ + + uint32_t u32ClockDivision; /*!< Specifies the WDT Clock Division. + This parameter can be a value of @ref WDT_Clock_Division */ + + uint32_t u32RefreshRange; /*!< Specifies the WDT Allow Refresh Range. + This parameter can be a value of @ref WDT_Refresh_Percent_Range */ + + uint32_t u32LPModeCountEn; /*!< Specifies the WDT Count Enable/Disable In Low Power Mode(Sleep Mode). + This parameter can be a value of @ref WDT_LPW_Mode_Count */ + + uint32_t u32TrigType; /*!< Specifies the WDT Refresh Error or Count Underflow trigger event Type. + This parameter can be a value of @ref WDT_Trigger_Event_Type */ +} stc_wdt_init_t; + +/** + * @} + */ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Macros WDT Global Macros + * @{ + */ + +/** + * @defgroup WDT_Counter_Cycle WDT Counter Cycle + * @{ + */ +#define WDT_COUNTER_CYCLE_256 (0UL) /*!< 256 clock cycle */ +#define WDT_COUNTER_CYCLE_4096 (WDT_CR_PERI_0) /*!< 4096 clock cycle */ +#define WDT_COUNTER_CYCLE_16384 (WDT_CR_PERI_1) /*!< 16384 clock cycle */ +#define WDT_COUNTER_CYCLE_65536 (WDT_CR_PERI) /*!< 65536 clock cycle */ +/** + * @} + */ + +/** + * @defgroup WDT_Clock_Division WDT Clock Division + * @{ + */ +#define WDT_CLOCK_DIV4 (WDT_CR_CKS_1) /*!< PLCK3/4 */ +#define WDT_CLOCK_DIV64 (WDT_CR_CKS_2 | WDT_CR_CKS_1) /*!< PLCK3/64 */ +#define WDT_CLOCK_DIV128 (WDT_CR_CKS_2 | WDT_CR_CKS_1 | WDT_CR_CKS_0) /*!< PLCK3/128 */ +#define WDT_CLOCK_DIV256 (WDT_CR_CKS_3) /*!< PLCK3/256 */ +#define WDT_CLOCK_DIV512 (WDT_CR_CKS_3 | WDT_CR_CKS_0) /*!< PLCK3/512 */ +#define WDT_CLOCK_DIV1024 (WDT_CR_CKS_3 | WDT_CR_CKS_1) /*!< PLCK3/1024 */ +#define WDT_CLOCK_DIV2048 (WDT_CR_CKS_3 | WDT_CR_CKS_1 | WDT_CR_CKS_0) /*!< PLCK3/2048 */ +#define WDT_CLOCK_DIV8192 (WDT_CR_CKS_3 | WDT_CR_CKS_2 | WDT_CR_CKS_0) /*!< PLCK3/8192 */ +/** + * @} + */ + +/** + * @defgroup WDT_Refresh_Percent_Range WDT Refresh Percent Range + * @{ + */ +#define WDT_RANGE_0TO100PCT (0UL) /*!< 0%~100% */ +#define WDT_RANGE_0TO25PCT (WDT_CR_WDPT_0) /*!< 0%~25% */ +#define WDT_RANGE_25TO50PCT (WDT_CR_WDPT_1) /*!< 25%~50% */ +#define WDT_RANGE_0TO50PCT (WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~50% */ +#define WDT_RANGE_50TO75PCT (WDT_CR_WDPT_2) /*!< 50%~75% */ +#define WDT_RANGE_0TO25PCT_50TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_0) /*!< 0%~25% & 50%~75% */ +#define WDT_RANGE_25TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_1) /*!< 25%~75% */ +#define WDT_RANGE_0TO75PCT (WDT_CR_WDPT_2 | WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~75% */ +#define WDT_RANGE_75TO100PCT (WDT_CR_WDPT_3) /*!< 75%~100% */ +#define WDT_RANGE_0TO25PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_0) /*!< 0%~25% & 75%~100% */ +#define WDT_RANGE_25TO50PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_1) /*!< 25%~50% & 75%~100% */ +#define WDT_RANGE_0TO50PCT_75TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_1 | WDT_CR_WDPT_0) /*!< 0%~50% & 75%~100% */ +#define WDT_RANGE_50TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2) /*!< 50%~100% */ +#define WDT_RANGE_0TO25PCT_50TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2 | WDT_CR_WDPT_0) /*!< 0%~25% & 50%~100% */ +#define WDT_RANGE_25TO100PCT (WDT_CR_WDPT_3 | WDT_CR_WDPT_2 | WDT_CR_WDPT_1) /*!< 25%~100% */ +/** + * @} + */ + +/** + * @defgroup WDT_LPW_Mode_Count WDT Low Power Mode Count + * @brief WDT count control in the sleep mode + * @{ + */ +#define WDT_LPM_COUNT_CONTINUE (0UL) /*!< WDT count continue in the sleep mode */ +#define WDT_LPM_COUNT_STOP (WDT_CR_SLPOFF) /*!< WDT count stop in the sleep mode */ +/** + * @} + */ + +/** +* @defgroup WDT_Trigger_Event_Type WDT Trigger Event Type +* @{ +*/ +#define WDT_TRIG_EVENT_INT (0UL) /*!< WDT trigger interrupt */ +#define WDT_TRIG_EVENT_RESET (WDT_CR_ITS) /*!< WDT trigger reset */ +/** + * @} + */ + +/** + * @defgroup WDT_Flag WDT Flag + * @{ + */ +#define WDT_FLAG_UDF (WDT_SR_UDF) /*!< Count underflow flag */ +#define WDT_FLAG_REF (WDT_SR_REF) /*!< Refresh error flag */ +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + Global function prototypes (definition in C source) + ******************************************************************************/ +/** + * @addtogroup WDT_Global_Functions + * @{ + */ + +/** + * @brief Get WDT count value. + * @param None + * @retval Count value + */ +__STATIC_INLINE uint16_t WDT_GetCountValue(void) +{ + return (uint16_t)(READ_REG32(M4_WDT->SR) & WDT_SR_CNT); +} + +/* Initialization and configuration functions */ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit); +void WDT_Feed(void); +uint16_t WDT_GetCountValue(void); + +/* Flags management functions */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag); +en_result_t WDT_ClearStatus(uint32_t u32Flag); + +/** + * @} + */ + +#endif /* DDL_WDT_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +#ifdef __cplusplus +} +#endif + +#endif /* __HC32F4A0_WDT_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_adc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_adc.c new file mode 100644 index 0000000000000000000000000000000000000000..07b74cb870bc4f7f7fb746eabaa2abc2685c77c7 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_adc.c @@ -0,0 +1,1588 @@ +/** + ******************************************************************************* + * @file hc32f4a0_adc.c + * @brief This file provides firmware functions to manage the Analog-to-Digital + * Converter(ADC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-07-02 Wuze 1. API ADC_SH_ChannelCmd() refine. + 2. Some other optimizations. + 2020-08-10 Wuze ADC_SeqClrStatus(): ADC_SEQ_FLAG_NESTED can be cleared. + 2020-12-15 Wuze ADC_ComTriggerCmd() refine. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_adc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_ADC ADC + * @brief Analog-to-Digital Converter Driver Library + * @{ + */ + +#if (DDL_ADC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ADC_Local_Macros ADC Local Macros + * @{ + */ + +/** + * @defgroup ADC_Unit_Base_Address ADC Unit Base Address + * @{ + */ +#define ADC1_BASE (0x40040000UL) +#define ADC2_BASE (0x40040400UL) +#define ADC3_BASE (0x40040800UL) +/** + * @} + */ + +/** + * @defgroup ADC_Configuration_Bit_Mask ADC Configuration Bit Mask + * @{ + */ +#define ADC_TRIG_SRC_MSK (ADC_TRGSR_TRGSELA) +#define ADC_AWD_COMB_MODE_MSK (ADC_AWDCR_AWDCM) +#define ADC_PGA_CMD_MSK (ADC_PGACR1_PGACTL) +#define ADC_PGA_GAIN_MSK (ADC_PGACR1_PGAGAIN) +#define ADC_SYNC_CFG_MSK (ADC_SYNCCR_SYNCMD | ADC_SYNCCR_SYNCDLY) +#define ADC_CH_MAP_PIN_MSK (ADC_CHMUXR0_CH00MUX) +#define ADC_SH_CFG_MSK (ADC_SHCR_SHSST) +#define ADC_SH_CH_MSK (ADC_SHCR_SHSEL) +#define ADC_COM_TRIG_MSK (ADC_COM_TRIG1 | ADC_COM_TRIG2) +#define ADC_TRIG_EVENT_MSK (AOS_ADC_1_ITRGSELR_TRGSEL) +/** + * @} + */ + +/** + * @defgroup ADC_PGA_Command ADC PGA Command + * @{ + */ +#define ADC_PGA_DISABLE (0x0U) +#define ADC_PGA_ENABLE (0xEU) +/** + * @} + */ + +/** + * @defgroup ADC_Unit_Number ADC Unit Number + * @{ + */ +#define __ADC_BASE (ADC1_BASE) +#define __ADC_UNIT_SIZE (0x400UL) +#define ADC_IDX(__ADCx__) ((uint8_t)(((uint32_t)&(__ADCx__)->STR - __ADC_BASE) / __ADC_UNIT_SIZE)) +/** + * @} + */ + +/** + * @defgroup ADC_Register_Bit_Band ADC Register Bit Band + * @{ + */ +#define __BIT_BAND_BASE (0x42000000UL) +#define __PERIP_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIP_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __BIT_BAND_BASE) +#define BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup ADC_Sequence_Configuration_Bit_Field_Offset ADC Sequence Configuration Bit Field Offset + * @{ + */ +#define ADC_OFS_TRGSR(__seq__) ((uint32_t)(__seq__) * ADC_TRGSR_TRGSELB_POS) +#define ADC_OFS_AWDCR(__num__) ((uint32_t)(__num__) * ADC_AWDCR_AWD1EN) +/** + * @} + */ + +/** + * @defgroup ADC_Register_Configuration_Value ADC Register Configuration Value + * @{ + */ +#define ADC_TRGSR_VAL(__seq__, __val__) ((uint32_t)(__val__) << ADC_OFS_TRGSR(__seq__)) +#define ADC_AWDCR_VAL(__num__, __val__) ((uint32_t)(__val__) << ADC_OFS_AWDCR(__num__)) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_DR ADC AWD DR + * @{ + */ +#define ADC_AWDx_DR(__base__, __awdNum__) (*(__IO uint32_t *)((uint32_t)(__base__) + ((uint32_t)(__awdNum__) << 3U))) +/** + * @} + */ + +/** + * @defgroup ADC_AWD_CHSR ADC AWD CHSR + * @{ + */ +#define ADC_AWDx_CHSR(__base__, __awdNum__) (*(__IO uint32_t *)((uint32_t)(__base__) + ((uint32_t)(__awdNum__) << 3U))) +/** + * @} + */ + +/** + * @defgroup ADC_Check_Parameters_Validity ADC check parameters validity + * @{ + */ +#define IS_ADC_UNIT(x) \ +( ((x) == M4_ADC1) || \ + ((x) == M4_ADC2) || \ + ((x) == M4_ADC3)) + +#define IS_ADC_SEQ(x) \ +( ((x) == ADC_SEQ_A) || \ + ((x) == ADC_SEQ_B)) + +#define IS_ADC_SCAN_MODE(x) \ +( ((x) == ADC_MODE_SA_SSHOT) || \ + ((x) == ADC_MODE_SA_CONT) || \ + ((x) == ADC_MODE_SA_SB_SSHOT) || \ + ((x) == ADC_MODE_SA_CONT_SB_SSHOT)) + +#define IS_ADC_RESOLUTION(x) \ +( ((x) == ADC_RESOLUTION_8BIT) || \ + ((x) == ADC_RESOLUTION_10BIT) || \ + ((x) == ADC_RESOLUTION_12BIT)) + +#define IS_ADC_TRIG_SRC(x) \ +( ((x) == ADC_TRIG_SRC_ADTRG) || \ + ((x) == ADC_TRIG_SRC_EVENT0) || \ + ((x) == ADC_TRIG_SRC_EVENT1) || \ + ((x) == ADC_TRIG_SRC_EVENT0_EVENT1)) + +#define IS_ADC_AUTO_CLEAR_CMD(x) \ +( ((x) == ADC_AUTO_CLR_DISABLE) || \ + ((x) == ADC_AUTO_CLR_ENABLE)) + +#define IS_ADC_DATA_ALIGN(x) \ +( ((x) == ADC_DATA_ALIGN_RIGHT) || \ + ((x) == ADC_DATA_ALIGN_LEFT)) + +#define IS_ADC_SA_RESUME_POS(x) \ +( ((x) == ADC_SA_RESUME_POS_INT_CH) || \ + ((x) == ADC_SA_RESUME_POS_FIRST_CH)) + +#define IS_ADC_SAMPLE_TIME(x) \ +( ((x) >= 5U)) + +#define IS_ADC_AVG_CNT(x) \ +( ((x) == ADC_AVG_CNT_2) || \ + ((x) == ADC_AVG_CNT_4) || \ + ((x) == ADC_AVG_CNT_8) || \ + ((x) == ADC_AVG_CNT_16) || \ + ((x) == ADC_AVG_CNT_32) || \ + ((x) == ADC_AVG_CNT_64) || \ + ((x) == ADC_AVG_CNT_128) || \ + ((x) == ADC_AVG_CNT_256)) + +#define IS_ADC_EXCH_SRC(x) \ +( ((x) == ADC_EXCH_SRC_ADC_PIN) || \ + ((x) == ADC_EXCH_SRC_INTERNAL)) + +#define IS_AWD_UNIT(x) \ +( ((x) == ADC_AWD_0) || \ + ((x) == ADC_AWD_1)) + +#define IS_AWD_CH_NUM(x) \ +( ((x) <= ADC_CH_NUM_15)) + +#define IS_AWD_CMP_MODE(x) \ +( ((x) == ADC_AWD_CMP_OUT_RANGE) || \ + ((x) == ADC_AWD_CMP_IN_RANGE)) + +#define IS_AWD_COMB_MODE(x) \ +( ((x) == ADC_AWD_COMB_OR) || \ + ((x) == ADC_AWD_COMB_AND) || \ + ((x) == ADC_AWD_COMB_XOR)) + +#define IS_PGA_UNIT(x) \ +( ((x) <= ADC_PGA_4)) + +#define IS_PGA_GAIN(x) \ +( ((x) <= ADC_PGA_GAIN_32)) + +#define IS_PGA_VSS(x) \ +( ((x) == ADC_PGA_VSS_PGAVSS) || \ + ((x) == ADC_PGA_VSS_AVSS)) + +#define IS_ADC_SYNC_MODE(x) \ +( ((x) == ADC_SYNC_SSHOT_SEQUENTIAL) || \ + ((x) == ADC_SYNC_SSHOT_SIMULTANEOUS) || \ + ((x) == ADC_SYNC_CONT_SEQUENTIAL) || \ + ((x) == ADC_SYNC_CONT_SIMULTANEOUS)) + +#define IS_ADC_SYNC_UNIT(x) \ +( ((x) == ADC_SYNC_ADC1_ADC2) || \ + ((x) == ADC_SYNC_ADC1_ADC2_ADC3)) + +#define IS_ADC_SYNC_TRIG_DLY(x) \ +( ((x) != 0U)) + +#define IS_ADC_REMAP_PIN_NUM(x) \ +( ((x) <= ADC12_IN15)) + +#define IS_ADC1_DR_LENGTH(x) \ +( ((x) >= ADC1_CH_COUNT)) + +#define IS_ADC2_DR_LENGTH(x) \ +( ((x) >= ADC2_CH_COUNT)) + +#define IS_ADC3_DR_LENGTH(x) \ +( ((x) >= ADC3_CH_COUNT)) + +#define IS_ADC_1_BIT_MSK(x) \ +( ((x) != 0U) && \ + (((x) & ((x) - 1U)) == 0U)) + +#define IS_ADC_BIT_MSK(x, msk) \ +( ((x) != 0U) && \ + (((x) | (msk)) == (msk))) + +/** + * @} + */ + +/** + * @defgroup ADC_Miscellaneous_Macros ADC Miscellaneous Macros + * @{ + */ +#define ADC_UNIT_COUNT (3U) +#define ADC_IND_SPL_TIME_COUNT (16U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ADC_Global_Functions ADC Global Functions + * @{ + */ + +/** + * @brief Initializes the specified ADC peripheral according to the specified parameters + * in the structure stc_adc_init_t. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] pstcInit Pointer to a stc_adc_init_t structure value that + * contains the configuration information for the ADC. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t ADC_Init(M4_ADC_TypeDef *ADCx, const stc_adc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SCAN_MODE(pstcInit->u16ScanMode)); + DDL_ASSERT(IS_ADC_RESOLUTION(pstcInit->u16Resolution)); + DDL_ASSERT(IS_ADC_AUTO_CLEAR_CMD(pstcInit->u16AutoClrCmd)); + DDL_ASSERT(IS_ADC_DATA_ALIGN(pstcInit->u16DataAlign)); + DDL_ASSERT(IS_ADC_SA_RESUME_POS(pstcInit->u16SAResumePos)); + + /* Configures scan convert mode, resolution, data automatically clear command + and data alignment. */ + WRITE_REG16(ADCx->CR0, \ + (pstcInit->u16ScanMode | \ + pstcInit->u16Resolution | \ + pstcInit->u16AutoClrCmd | \ + pstcInit->u16DataAlign)); + + /* Configures the channel sequence A restart from. */ + WRITE_REG16(ADCx->CR1, pstcInit->u16SAResumePos); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initializes the ADC peripheral. Reset the registers of the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @retval None + */ +void ADC_DeInit(M4_ADC_TypeDef *ADCx) +{ + uint8_t i; + uint32_t u32SSTRAddr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + /* Stop the ADC. */ + WRITE_REG8(ADCx->STR, 0U); + + /* Set the registers to reset value. */ + WRITE_REG16(ADCx->CR0, 0x0U); + WRITE_REG16(ADCx->CR1, 0x0U); + WRITE_REG16(ADCx->TRGSR, 0x0U); + + WRITE_REG32(ADCx->CHSELRA, 0x0U); + WRITE_REG32(ADCx->CHSELRB, 0x0U); + WRITE_REG32(ADCx->AVCHSELR, 0x0U); + WRITE_REG8(ADCx->EXCHSELR, 0x0U); + + WRITE_REG16(ADCx->CHMUXR0, 0x3210U); + WRITE_REG16(ADCx->CHMUXR1, 0x7654U); + WRITE_REG16(ADCx->CHMUXR2, 0xBA98U); + WRITE_REG16(ADCx->CHMUXR3, 0xFEDCU); + + WRITE_REG8(ADCx->ICR, 0x03U); + WRITE_REG8(ADCx->ISCLRR, 0x13U); + + WRITE_REG16(ADCx->AWDCR, 0x0U); + WRITE_REG8(ADCx->AWDSCLRR, 0x13U); + + WRITE_REG16(ADCx->AWD0DR0, 0x0U); + WRITE_REG16(ADCx->AWD0DR1, 0xFFFFU); + WRITE_REG16(ADCx->AWD1DR0, 0x0U); + WRITE_REG16(ADCx->AWD1DR1, 0xFFFFU); + + WRITE_REG8(ADCx->AWD0CHSR, 0x0U); + WRITE_REG8(ADCx->AWD1CHSR, 0x0U); + + u32SSTRAddr = (uint32_t)&ADCx->SSTR0; + for (i=0U; iSYNCCR, 0x0C00U); + WRITE_REG16(ADCx->SHCR, 0x18U); + WRITE_REG8(ADCx->PGACR1, 0x0U); + WRITE_REG8(ADCx->PGACR2, 0x0U); + WRITE_REG8(ADCx->PGACR3, 0x0U); + WRITE_REG8(ADCx->PGAVSSENR, 0x0U); + } + else if (ADCx == M4_ADC2) + { + WRITE_REG8(ADCx->PGACR1, 0x0U); + WRITE_REG8(ADCx->PGAVSSENR, 0x0U); + } + else if (ADCx == M4_ADC3) + { + WRITE_REG8(ADCx->SSTRL, 0x0BU); + } + else + { + /* rsvd */ + } +} + +/** + * @brief Set a default value for the ADC initialization structure. + * @param [in] pstcInit Pointer to a stc_adc_init_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t ADC_StructInit(stc_adc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + pstcInit->u16ScanMode = ADC_MODE_SA_SSHOT; + pstcInit->u16Resolution = ADC_RESOLUTION_12BIT; + pstcInit->u16AutoClrCmd = ADC_AUTO_CLR_DISABLE; + pstcInit->u16DataAlign = ADC_DATA_ALIGN_RIGHT; + pstcInit->u16SAResumePos = ADC_SA_RESUME_POS_INT_CH; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set scan convert mode for the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u16Mode ADC san convert mode. + * This parameter can be a value of @ref ADC_Scan_Convert_Mode. + * @arg ADC_MODE_SA_SSHOT: Sequence A single shot. + * @arg ADC_MODE_SA_CONT: Sequence A continuous. + * @arg ADC_MODE_SA_SB_SSHOT: Sequence A and B both single shot. + * @arg ADC_MODE_SA_CONT_SB_SSHOT: Sequence A continuous and sequence B single shot. + * @retval None + */ +void ADC_SetScanMode(M4_ADC_TypeDef *ADCx, uint16_t u16Mode) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SCAN_MODE(u16Mode)); + MODIFY_REG16(ADCx->CR0, ADC_CR0_MS, u16Mode); +} + +/** + * @brief Enable or disable the specified sequence's channels. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Seq The sequence that it's specified channels will be enabled or disabled. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] u32AdcCh The ADC channels. + * This parameter can be values of @ref ADC_Channel + * @arg ADC_CH0 ~ ADC_CH15: For M4_ADC1 and M4_ADC2. + * @arg ADC_CH0 ~ ADC_CH19: For M4_ADC3. + * @param [in] pu8SplTime: Pointer to an uint8_t type array which contains sampling time of the specified channels. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the specified sequence's specified channels. + * @arg Disable: Disable the specified sequence's specified channels. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pu8SplTime == NULL. + * @note Sequence A and Sequence B CAN NOT include the same channel! + * @note ADC_CH16 ~ ADC_CH19 of ADC3 share the same sampling time. + */ +en_result_t ADC_ChannelCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, \ + uint32_t u32AdcCh, const uint8_t pu8SplTime[], \ + en_functional_state_t enNewState) +{ + uint8_t i = 0U; + uint8_t j = 0U; + uint32_t u32CHSELAddr; + uint32_t u32SSTRAddr; + uint32_t au32ChMsk[] = {ADC1_CH_ALL, ADC2_CH_ALL, ADC3_CH_ALL}; + en_result_t enRet = ErrorInvalidParameter; + + if (pu8SplTime != NULL) + { + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CHSELAddr = (uint32_t)&ADCx->CHSELRA + ((uint32_t)u8Seq * 4U); + u32SSTRAddr = (uint32_t)&ADCx->SSTR0; + u32AdcCh &= au32ChMsk[ADC_IDX(ADCx)]; + + if (enNewState == Enable) + { + RW_MEM32(u32CHSELAddr) |= u32AdcCh; + + while (u32AdcCh != 0U) + { + if ((u32AdcCh & 0x1UL) != 0U) + { + DDL_ASSERT(IS_ADC_SAMPLE_TIME(pu8SplTime[j])); + RW_MEM8(u32SSTRAddr+i) = pu8SplTime[j]; + if (i < ADC_IND_SPL_TIME_COUNT) + { + j++; + } + } + u32AdcCh >>= 1U; + if (i < ADC_IND_SPL_TIME_COUNT) + { + i++; + } + } + } + else + { + RW_MEM32(u32CHSELAddr) &= (uint32_t)(~u32AdcCh); + } + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set average count for the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u16AvgCnt The average count to be set for the specified ADC unit. + * This parameter can be a value of @ref ADC_Average_Count + * @arg ADC_AVG_CNT_2 + * @arg ADC_AVG_CNT_4 + * @arg ADC_AVG_CNT_8 + * @arg ADC_AVG_CNT_16 + * @arg ADC_AVG_CNT_32 + * @arg ADC_AVG_CNT_64 + * @arg ADC_AVG_CNT_128 + * @arg ADC_AVG_CNT_256 + * @retval None + */ +void ADC_AvgChannelConfig(M4_ADC_TypeDef *ADCx, uint16_t u16AvgCnt) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_AVG_CNT(u16AvgCnt)); + MODIFY_REG16(ADCx->CR0, ADC_CR0_AVCNT, u16AvgCnt); +} + +/** + * @brief Enable or disable the specified ADC unit's average channels. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u32AdcCh The ADC channels. + * This parameter can be values of @ref ADC_Channel + * @arg ADC_CH0 ~ ADC_CH15: For M4_ADC1 and M4_ADC2. + * @arg ADC_CH0 ~ ADC_CH19: For M4_ADC3. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the specified ADC unit's average channels. + * @arg Disable: Disable the specified ADC unit's average channels. + * @retval None + */ +void ADC_AvgChannelCmd(M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh, en_functional_state_t enNewState) +{ + uint32_t u32SACh; + uint32_t u32SBCh; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32SACh = ADCx->CHSELRA; + u32SBCh = ADCx->CHSELRB; + u32AdcCh &= (u32SACh | u32SBCh); + if (enNewState == Enable) + { + SET_REG32_BIT(ADCx->AVCHSELR, u32AdcCh); + } + else + { + CLEAR_REG32_BIT(ADCx->AVCHSELR, u32AdcCh); + } +} + +/** + * @brief Set analog input source for the specified ADC unit's extend channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8ExChSrc The analog input source for the extend channel. + * This parameter can be a value of @ref ADC_Extend_Channel_Source + * @arg ADC_EXCH_SRC_ADC_PIN: The analog input source of extend channel is ADC analog input pin, + * ADC12_IN15 of ADC1/ADC2 and ADC3_IN15 of ADC3. + * @arg ADC_EXCH_SRC_INTERNAL: The analog input source of extend channels is internal reference voltage or + * the partial voltage of VBAT. + * @retval None + */ +void ADC_SetExChannelSrc(M4_ADC_TypeDef *ADCx, uint8_t u8ExChSrc) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_EXCH_SRC(u8ExChSrc)); + WRITE_REG8(ADCx->EXCHSELR, u8ExChSrc); +} + +/** + * @brief Set a default value for the trigger source configuration structure. + * @param [in] pstcCfg Pointer to a stc_adc_trig_cfg_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t ADC_TrigSrcStructInit(stc_adc_trig_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + pstcCfg->u16TrigSrc = ADC_TRIG_SRC_ADTRG; + pstcCfg->enEvent0 = EVT_MAX; + pstcCfg->enEvent1 = EVT_MAX; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Configures the trigger source for the specified sequence of the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] pstcCfg Pointer to a stc_adc_trig_cfg_t structure that contains + * the configuration information of the trigger source. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + * @note ADC must be stopped while calling this function. + * @note The trigger source CANNOT be an event that generated by the sequence itself. + */ +en_result_t ADC_TrigSrcConfig(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, const stc_adc_trig_cfg_t *pstcCfg) +{ + uint32_t u32AdcIdx; + uint32_t u32ITRGSELRAddr; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_ADC_TRIG_SRC(pstcCfg->u16TrigSrc)); + + u32AdcIdx = ADC_IDX(ADCx); + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC_1_ITRGSELR0 + u32AdcIdx * 8U; + if ((pstcCfg->u16TrigSrc & ADC_TRIG_SRC_EVENT0) != 0U) + { + MODIFY_REG32(RW_MEM32(u32ITRGSELRAddr), ADC_TRIG_EVENT_MSK, pstcCfg->enEvent0); + } + + if ((pstcCfg->u16TrigSrc & ADC_TRIG_SRC_EVENT1) != 0U) + { + u32ITRGSELRAddr += 4U; + MODIFY_REG32(RW_MEM32(u32ITRGSELRAddr), ADC_TRIG_EVENT_MSK, pstcCfg->enEvent1); + } + + MODIFY_REG16(ADCx->TRGSR, \ + ADC_TRGSR_VAL(u8Seq, ADC_TRIG_SRC_MSK), \ + ADC_TRGSR_VAL(u8Seq, pstcCfg->u16TrigSrc)); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable the trigger source of the specified sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable the trigger source of the specified sequence. + * @arg Disable: Disable the trigger source of the specified sequence. + * @retval None + * @note ADC must be stopped while calling this function. + */ +void ADC_TrigSrcCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + uint8_t au8CmdPos[] = {ADC_TRGSR_TRGENA_POS, ADC_TRGSR_TRGENB_POS}; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->TRGSR; + BIT_BAND(u32Addr, au8CmdPos[u8Seq]) = (uint32_t)enNewState; +} + +/** + * @brief Enable or disable common trigger event to start ADC. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u16TrigSrc ADC trigger source type. + * This parameter can be a value of @ref ADC_Trigger_Source_Type except ADC_TRIG_SRC_ADTRG. + * @arg ADC_TRIG_SRC_EVENT0: The trigger source is a internal event from other peripheral. \ + * Only one event can be configured to trigger ADC. + * @arg ADC_TRIG_SRC_EVENT1: The trigger source is a internal event from other peripheral. \ + * Only one event can be configured to trigger ADC. + * @arg ADC_TRIG_SRC_EVENT0_EVENT1: The trigger source are two internal events from other peripheral(s). \ + * Two events can be configured to trigger ADC and one of which can trigger the ADC. + * @param [in] u32ComTrig Common trigger event enable bit mask. + * This parameter can be a value of @ref ADC_Common_Trigger_Sel + * @arg ADC_COM_TRIG1: Common trigger 1. + * @arg ADC_COM_TRIG2: Common trigger 2. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified common trigger. + * @arg Disable: Disable the specified common trigger. + * @retval None + */ +void ADC_ComTriggerCmd(M4_ADC_TypeDef *ADCx, uint16_t u16TrigSrc, \ + uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + uint32_t u32AdcIdx; + uint32_t u32ITRGSELRAddr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_BIT_MSK(u32ComTrig, ADC_COM_TRIG_MSK)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32AdcIdx = ADC_IDX(ADCx); + u32ITRGSELRAddr = (uint32_t)&M4_AOS->ADC_1_ITRGSELR0 + u32AdcIdx * 8U; + + if ((u16TrigSrc & ADC_TRIG_SRC_EVENT0) != 0U) + { + if (enNewState == Enable) + { + SET_REG32_BIT(RW_MEM32(u32ITRGSELRAddr), u32ComTrig); + } + else + { + CLEAR_REG32_BIT(RW_MEM32(u32ITRGSELRAddr), u32ComTrig); + } + } + + if ((u16TrigSrc & ADC_TRIG_SRC_EVENT1) != 0U) + { + u32ITRGSELRAddr += 4UL; + if (enNewState == Enable) + { + SET_REG32_BIT(RW_MEM32(u32ITRGSELRAddr), u32ComTrig); + } + else + { + CLEAR_REG32_BIT(RW_MEM32(u32ITRGSELRAddr), u32ComTrig); + } + } +} + +/** + * @brief Enable or disable the interrupt of the specified ADC unit's specified sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Seq The sequence to be configured. + * This parameter can be a value of @ref ADC_Sequence + * @arg ADC_SEQ_A: Sequence A. + * @arg ADC_SEQ_B: Sequence B. + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable the interrupt of the specified sequence. + * @arg Disable: Disable the interrupt of the specified sequence. + * @retval None + */ +void ADC_SeqIntCmd(M4_ADC_TypeDef *ADCx, uint8_t u8Seq, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_SEQ(u8Seq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&ADCx->ICR; + BIT_BAND(u32Addr, u8Seq) = (uint32_t)enNewState; +} + +/** + * @brief Get the status flag of the specified ADC unit's specified sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Flag Status flag type. + * This parameter can be valueS of @ref ADC_Sequence_Status_Flag + * @arg ADC_SEQ_FLAG_EOCA: Status flag of the end of conversion of sequence A. + * @arg ADC_SEQ_FLAG_EOCB: Status flag of the end of conversion of sequence B. + * @arg ADC_SEQ_FLAG_NESTED: Status flag of sequence A was interrupted by sequence B. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified flags is set. + * @arg Reset: The specified flags are not set. + */ +en_flag_status_t ADC_SeqGetStatus(const M4_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + en_flag_status_t enRet = Reset; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (READ_REG8_BIT(ADCx->ISR, (u8Flag & (uint8_t)ADC_SEQ_FLAG_ALL)) != 0U) + { + enRet = Set; + } + + return enRet; +} + +/** + * @brief Clear the status flag of the specified ADC unit's specified sequence. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Flag Status flag type. + * This parameter can be values of @ref ADC_Sequence_Status_Flag + * @arg ADC_SEQ_FLAG_EOCA: Status flag of the end of conversion of sequence A. + * @arg ADC_SEQ_FLAG_EOCB: Status flag of the end of conversion of sequence B. + * @arg ADC_SEQ_FLAG_NESTED: Status flag of sequence A was interrupted by sequence B. + * @retval None + */ +void ADC_SeqClrStatus(M4_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + SET_REG8_BIT(ADCx->ISCLRR, (u8Flag & (uint8_t)ADC_SEQ_FLAG_ALL)); +} + +/** + * @brief Configures analog watchdog(AWD). + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8AWDx AWD unit that is going to be configured. + * This parameter can be a value of @ref ADC_AWD_Unit + * @arg ADC_AWD_0: AWD unit 0 of the specified ADC. + * @arg ADC_AWD_1: AWD unit 1 of the specified ADC. + * @param [in] pstcCfg Pointer to a stc_adc_awd_cfg_t structure value that + * contains the configuration information for the AWD. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t ADC_AWD_Config(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, const stc_adc_awd_cfg_t *pstcCfg) +{ + uint32_t u32AwdCr; + uint32_t u32AwdDr0; + uint32_t u32AwdDr1; + uint32_t u32AwdChsr; + uint32_t u32Pos; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_AWD_UNIT(u8AWDx)); + DDL_ASSERT(IS_AWD_CH_NUM(pstcCfg->u8ChNum)); + DDL_ASSERT(IS_AWD_CMP_MODE(pstcCfg->u16CmpMode)); + + u32Pos = ((uint32_t)u8AWDx << 2U) + ADC_AWDCR_AWD0MD_POS; + u32AwdCr = (uint32_t)&ADCx->AWDCR; + u32AwdDr0 = (uint32_t)&ADCx->AWD0DR0; + u32AwdDr1 = (uint32_t)&ADCx->AWD0DR1; + u32AwdChsr = (uint32_t)&ADCx->AWD0CHSR; + + BIT_BAND(u32AwdCr, u32Pos) = (uint32_t)pstcCfg->u16CmpMode; + ADC_AWDx_DR(u32AwdDr0, u8AWDx) = pstcCfg->u16LowerLimit; + ADC_AWDx_DR(u32AwdDr1, u8AWDx) = pstcCfg->u16UpperLimit; + ADC_AWDx_CHSR(u32AwdChsr, u8AWDx) = pstcCfg->u8ChNum; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable combination mode of analog watchdog(AWD). + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u16CombMode Combination mode of analog watchdog. + * This parameter can be a value of @ref ADC_AWD_Combination_Mode + * @arg ADC_AWD_COMB_OR: The status of AWD0 is set or the status of AWD1 is set, the status of combination mode is set. + * @arg ADC_AWD_COMB_AND: The status of AWD0 is set and the status of AWD1 is set, the status of combination mode is set. + * @arg ADC_AWD_COMB_XOR: Only one of the status of AWD0 and AWD1 is set, the status of combination mode is set. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the combination mode of specified ADC unit's AWD. + * @arg Disable: Disable the combination mode of specified ADC unit's AWD. + * @retval None + */ +void ADC_AWD_CombModeCmd(M4_ADC_TypeDef *ADCx, uint16_t u16CombMode, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_AWD_COMB_MODE(u16CombMode)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CLEAR_REG16_BIT(ADCx->AWDCR, ADC_AWD_COMB_MODE_MSK); + if (enNewState == Enable) + { + SET_REG16_BIT(ADCx->AWDCR, u16CombMode); + } +} + +/** + * @brief Enable or disable the specified analog watchdog(AWD). + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8AWDx AWD unit that is going to be enabled or disabled. + * This parameter can be a value of @ref ADC_AWD_Unit + * @arg ADC_AWD_0: AWD unit 0 of the specified ADC. + * @arg ADC_AWD_1: AWD unit 1 of the specified ADC. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the specified AWD. + * @arg Disable: Disable the specified AWD. + * @retval None + */ +void ADC_AWD_Cmd(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + uint32_t u32Pos; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_AWD_UNIT(u8AWDx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Pos = ((uint32_t)u8AWDx << 2U) + ADC_AWDCR_AWD0EN_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + BIT_BAND(u32Addr, u32Pos) = (uint32_t)enNewState; +} + +/** + * @brief Enable or disable the specified analog watchdog's interrupt. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8AWDx AWD unit. + * This parameter can be a value of @ref ADC_AWD_Unit + * @arg ADC_AWD_0: AWD unit 0 of the specified ADC. + * @arg ADC_AWD_1: AWD unit 1 of the specified ADC. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the specified AWD's interrupt. + * @arg Disable: Disable the specified AWD's interrupt. + * @retval None + */ +void ADC_AWD_IntCmd(M4_ADC_TypeDef *ADCx, uint8_t u8AWDx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + uint32_t u32Pos; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_AWD_UNIT(u8AWDx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Pos = ((uint32_t)u8AWDx << 2U) + ADC_AWDCR_AWD0IEN_POS; + u32Addr = (uint32_t)&ADCx->AWDCR; + BIT_BAND(u32Addr, u32Pos) = (uint32_t)enNewState; +} + +/** + * @brief Get the analog watchdog's flag status of the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Flag AWD status flag type. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @arg ADC_AWD_FLAG_AWD0: Flag of AWD0. + * @arg ADC_AWD_FLAG_AWD1: Flag of AWD1. + * @arg ADC_AWD_FLAG_COMB: Flag of combination mode. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified flags is set. + * @arg Reset: The specified flags are not set. + */ +en_flag_status_t ADC_AWD_GetStatus(const M4_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + en_flag_status_t enRet = Reset; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + if (READ_REG8_BIT(ADCx->AWDSR, (u8Flag & (uint8_t)ADC_AWD_FLAG_ALL)) != 0U) + { + enRet = Set; + } + + return enRet; +} + +/** + * @brief Clear the analog watchdog's flag status of the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8Flag AWD status flag type. + * This parameter can be values of @ref ADC_AWD_Status_Flag + * @arg ADC_AWD_FLAG_AWD0: Flag of AWD0. + * @arg ADC_AWD_FLAG_AWD1: Flag of AWD1. + * @arg ADC_AWD_FLAG_COMB: Flag of combination mode. + * @retval None + */ +void ADC_AWD_ClrStatus(M4_ADC_TypeDef *ADCx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + u8Flag &= (uint8_t)ADC_AWD_FLAG_ALL; + SET_REG8_BIT(ADCx->AWDSCLRR, u8Flag); +} + +/** + * @brief Configures the specified programmable gain amplifier(PGA). + * @param [in] u8PGAx The PGA unit that is going to be configured. + * This parameter can be a value of @ref ADC_PGA_Unit + * @arg ADC_PGA_1: PGA1, belongs to ADC1. Input pin is ADC123_IN0. + * @arg ADC_PGA_2: PGA2, belongs to ADC1. Input pin is ADC123_IN1. + * @arg ADC_PGA_3: PGA3, belongs to ADC1. Input pin is ADC123_IN2. + * @arg ADC_PGA_4: PGA4, belongs to ADC2. Input pin is ADC12_IN7. + * @param [in] u8GainFactor Gain factor for the specified PGA. + * This parameter can be a value of @ref ADC_PGA_Gain_Factor + * @arg ADC_PGA_GAIN_2: PGA gain factor is 2. + * @arg ADC_PGA_GAIN_2P133: PGA gain factor is 2.133. + * @arg ADC_PGA_GAIN_2P286: PGA gain factor is 2.286. + * @arg ADC_PGA_GAIN_2P667: PGA gain factor is 2.667. + * @arg ADC_PGA_GAIN_2P909: PGA gain factor is 2.909. + * @arg ADC_PGA_GAIN_3P2: PGA gain factor is 3.2. + * @arg ADC_PGA_GAIN_3P556: PGA gain factor is 2.556. + * @arg ADC_PGA_GAIN_4: PGA gain factor is 4. + * @arg ADC_PGA_GAIN_4P571: PGA gain factor is 4.571. + * @arg ADC_PGA_GAIN_5P333: PGA gain factor is 5.333. + * @arg ADC_PGA_GAIN_6P4: PGA gain factor is 6.4. + * @arg ADC_PGA_GAIN_8: PGA gain factor is 8. + * @arg ADC_PGA_GAIN_10P667: PGA gain factor is 10.667. + * @arg ADC_PGA_GAIN_16: PGA gain factor is 16. + * @arg ADC_PGA_GAIN_32: PGA gain factor is 32. + * @param [in] u8PgaVss VSS for the specified PGA. + * This parameter can be a value of @ref ADC_PGA_VSS + * @arg ADC_PGA_VSS_PGAVSS: Use pin PGA123_VSS as the reference GND of PGA1, PGA2 and PGA3. + * @arg ADC_PGA_VSS_AVSS: Use AVSS as the reference GND of PGA1, PGA2 and PGA3. + * @retval None + */ +void ADC_PGA_Config(uint8_t u8PGAx, uint8_t u8GainFactor, uint8_t u8PgaVss) +{ + uint32_t u32Addr; + uint32_t u32PGACRAddr; + M4_ADC_TypeDef *ADCx; + uint32_t au32AdcBase[] = {ADC1_BASE, ADC1_BASE, ADC1_BASE, ADC2_BASE}; + + DDL_ASSERT(IS_PGA_GAIN(u8GainFactor)); + DDL_ASSERT(IS_PGA_VSS(u8PgaVss)); + DDL_ASSERT(IS_PGA_UNIT(u8PGAx)); + + ADCx = (M4_ADC_TypeDef *)au32AdcBase[u8PGAx]; + u8PGAx %= 3U; + u32PGACRAddr = (uint32_t)&ADCx->PGACR1 + u8PGAx; + MODIFY_REG8(RW_MEM8(u32PGACRAddr), ADC_PGA_GAIN_MSK, u8GainFactor); + u32Addr = (uint32_t)&ADCx->PGAVSSENR; + BIT_BAND(u32Addr, u8PGAx) = (uint32_t)u8PgaVss; +} + +/** + * @brief Enable the specified programmable gain amplifier(PGA). + * @param [in] u8PGAx The PGA unit which is going to be enabled or disabled. + * This parameter can be a value of @ref ADC_PGA_Unit + * @arg ADC_PGA_1: PGA1, belongs to ADC1. Input pin is ADC123_IN0. + * @arg ADC_PGA_2: PGA2, belongs to ADC1. Input pin is ADC123_IN1. + * @arg ADC_PGA_3: PGA3, belongs to ADC1. Input pin is ADC123_IN2. + * @arg ADC_PGA_4: PGA4, belongs to ADC2. Input pin is ADC12_IN7. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the specified PGA. + * @arg Disable: Disable the specified PGA. + * @retval None + */ +void ADC_PGA_Cmd(uint8_t u8PGAx, en_functional_state_t enNewState) +{ + uint32_t u32PGACRAddr; + M4_ADC_TypeDef *ADCx; + uint32_t au32AdcBase[] = {ADC1_BASE, ADC1_BASE, ADC1_BASE, ADC2_BASE}; + uint8_t au8Cmd[] = {ADC_PGA_DISABLE, ADC_PGA_ENABLE}; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PGA_UNIT(u8PGAx)); + + ADCx = (M4_ADC_TypeDef *)au32AdcBase[u8PGAx]; + u8PGAx %= 3U; + u32PGACRAddr = (uint32_t)&ADCx->PGACR1 + u8PGAx; + MODIFY_REG8(RW_MEM8(u32PGACRAddr), ADC_PGA_CMD_MSK, au8Cmd[(uint8_t)enNewState]); +} + +/** + * @brief Configures synchronous mode. + * @param [in] u16SyncUnit Specify the ADC units which work synchronously. + * This parameter can be a value of @ref ADC_Synchronous_Unit + * @arg ADC_SYNC_ADC1_ADC2: ADC1 and ADC2 work synchronously. + * @arg ADC_SYNC_ADC1_ADC2_ADC3: ADC1, ADC2 and ADC3 work synchronously. + * @param [in] u16SyncMode Synchronous mode. + * This parameter can be a value of @ref ADC_Synchronous_Mode + * @arg ADC_SYNC_SSHOT_SEQUENTIAL: Single shot trigger, sequentially trigger. \ + * When the trigger condition occurs, ADC1 starts before ADC2, \ + * and ADC1 and ADC2 only perform one sample conversion. + * @arg ADC_SYNC_SSHOT_SIMULTANEOUS: Single shot trigger, simultaneously trigger. \ + * When the trigger condition occurs, ADC1 and ADC2 start at the same time, \ + * and ADC1 and ADC2 only perform one sample conversion. + * @arg ADC_SYNC_CONT_SEQUENTIAL: Continuously trigger, sequentially trigger. \ + * When the trigger condition occurs, ADC1 starts before ADC2, \ + * and ADC1 and ADC2 will continue to sample conversion until stopped by software. + * @arg ADC_SYNC_CONT_SIMULTANEOUS: Continuously trigger, simultaneously trigger. \ + * When the trigger condition occurs, ADC1 and ADC2 start at the same time, \ + * and ADC1 and ADC2 will continue to sample conversion until stopped by software. + * @param [in] u8TrigDelay Trigger delay time(PCLK2 cycle), range is [1, 255]. + * @retval None + */ +void ADC_SYNC_Config(uint16_t u16SyncUnit, uint16_t u16SyncMode, uint8_t u8TrigDelay) +{ + DDL_ASSERT(IS_ADC_SYNC_UNIT(u16SyncUnit)); + DDL_ASSERT(IS_ADC_SYNC_MODE(u16SyncMode)); + DDL_ASSERT(IS_ADC_SYNC_TRIG_DLY(u8TrigDelay)); + + u16SyncMode |= ((uint16_t)((uint32_t)u8TrigDelay << ADC_SYNCCR_SYNCDLY_POS)) | u16SyncUnit; + MODIFY_REG16(M4_ADC1->SYNCCR, ADC_SYNC_CFG_MSK, u16SyncMode); +} + +/** + * @brief Enable or disable synchronous mode. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable synchronous mode. + * @arg Disable: Disable synchronous mode. + * @retval None + */ +void ADC_SYNC_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bM4_ADC1->SYNCCR_b.SYNCEN, enNewState); +} + +/** + * @brief Configures sample-hold. Specifies the sample time of sample-hold. + * @param [in] u8SplTime Sample time(ADCLK cycles) for sample-hold. \ + * It should be more than 0.4 microseconds. + * @retval None + */ +void ADC_SH_Config(uint8_t u8SplTime) +{ + MODIFY_REG16(M4_ADC1->SHCR, ADC_SH_CFG_MSK, u8SplTime); +} + +/** + * @brief Enable or disable sample-hold channels. + * @param [in] u32AdcCh ADC channels. + * This parameter be values of the following that from @ref ADC_Channel + * @arg ADC_CH0: Channel 0 of ADC1. + * @arg ADC_CH1: Channel 1 of ADC1. + * @arg ADC_CH2: Channel 2 of ADC1. + * @param [in] enNewState: An en_functional_state_t value. + * @arg Enable: Enable the specified sample-hold channels. + * @arg Disable: Disable the specified sample-hold channels. + * @retval None + */ +void ADC_SH_ChannelCmd(uint32_t u32AdcCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_ADC_BIT_MSK(u32AdcCh, ADC_CH0|ADC_CH1|ADC_CH2)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32AdcCh <<= ADC_SHCR_SHSEL_POS; + if (enNewState == Enable) + { + SET_REG16_BIT(M4_ADC1->SHCR, u32AdcCh); + } + else + { + CLEAR_REG16_BIT(M4_ADC1->SHCR, u32AdcCh); + } +} + +/** + * @brief Remap the correspondence between ADC channels and analog input pins. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u32AdcCh This parameter be values of the following that from @ref ADC_Channel + * @arg ADC_CH0 ~ ADC_CH15 For all of ADC units. + * @param [in] u8AdcPinNum This parameter be a value of @ref ADC_Pin_Number + * @arg ADC123_xxx: Pin number belongs to all of ADC units. + * @arg ADC12_xxx: Pin number belongs to ADC1 and ADC2. + * @arg ADC3_xxx: Pin number belongs to ADC3. + * @note The pin number is from 0 to 15 can be remaped. + * @retval None + */ +void ADC_ChannelRemap(M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh, uint8_t u8AdcPinNum) +{ + uint8_t u8FieldOfs; + uint32_t u32RegIdx; + uint32_t u32CHMUXRAddr; + uint32_t u32ChNum = 0U; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_REMAP_PIN_NUM(u8AdcPinNum)); + DDL_ASSERT(IS_ADC_BIT_MSK(u32AdcCh, ADC_CH_REMAP_ALL)); + + u32CHMUXRAddr = (uint32_t)&ADCx->CHMUXR0; + while (u32AdcCh != 0U) + { + if ((u32AdcCh & 0x1UL) != 0U) + { + u32RegIdx = u32ChNum / 4U; + u8FieldOfs = (uint8_t)((u32ChNum % 4U) << 2U); + MODIFY_REG16(RW_MEM16(u32CHMUXRAddr + u32RegIdx * 2U), \ + ((uint32_t)ADC_CH_MAP_PIN_MSK << u8FieldOfs), \ + ((uint32_t)u8AdcPinNum << u8FieldOfs)); + } + + u32AdcCh >>= 1U; + u32ChNum++; + } +} + +/** + * @brief Get the number of the analog input pin corresponding to the specified ADC unit's channel. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u32AdcCh ADC channel. + * This parameter can be one of the following values of @ref ADC_Channel + * @arg ADC_CH0 ~ ADC_CH15 + * @retval An uint8_t type value of ADC pin number that corresponding to the specified channel number. + * This parameter can be one of the following values of @ref ADC_Pin_Number + * @arg ADC123_xxx: Pin number belongs to all of ADC units. + * @arg ADC12_xxx: Pin number belongs to ADC1 and ADC2. + * @arg ADC3_xxx: Pin number belongs to ADC3. + */ +uint8_t ADC_GetChannelPinNum(const M4_ADC_TypeDef *ADCx, uint32_t u32AdcCh) +{ + uint32_t u32RegIdx; + uint32_t u32CHMUXRAddr; + uint32_t u32ChNum = 0U; + uint8_t u8RetPinNum; + uint8_t u8FieldOfs; + + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + DDL_ASSERT(IS_ADC_BIT_MSK(u32AdcCh, ADC_CH_REMAP_ALL)); + DDL_ASSERT(IS_ADC_1_BIT_MSK(u32AdcCh)); + + while ((u32AdcCh & (1UL << u32ChNum)) == 0U) + { + u32ChNum++; + } + + u32RegIdx = u32ChNum / 4U; + u8FieldOfs = (uint8_t)((u32ChNum % 4U) << 2U); + u32CHMUXRAddr = (uint32_t)&ADCx->CHMUXR0 + (u32RegIdx * 2U); + u8RetPinNum = (uint8_t)((RW_MEM16(u32CHMUXRAddr) >> u8FieldOfs) & 0xFU); + + return u8RetPinNum; +} + +/** + * @brief Basic usage of ADC sampling. Get the ADC values of the pins + * corresponding to the channels enabled in sequence A. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [out] pu16AdcVal Pointer to an uint16_t type memory which the ADC values to be stored. + * The location of the value store depends on the parameter u8Length. + * u8Length >= ADCx_CH_COUNT, all of the ADC data registers will be read: + * pu16AdcVal[0] = value of Channel 0, + * pu16AdcVal[1] = value of Channel 1, + * pu16AdcVal[2] = value of Channel 2, + * ... + * u8Length < ADCx_CH_COUNT(ADC1_CH_COUNT or ADC2_CH_COUNT), + * only the value of the enabled channels will be read: + * pu16AdcVal[0] = value of the 1st enabled channel, + * pu16AdcVal[1] = value of the 2nd enabled channel, + * pu16AdcVal[2] = value of the 3rd enabled channel, + * @param [in] u8Length The length of the ADC value to be got. + * @param [in] u32Timeout Timeout value(millisecond). + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: -pu16AdcVal == NULL. + * -u8Length == 0. + * -u32Timeout == 0. + * -The base address of 'pu16AdcVal' is not 2-byte aligned. + */ +en_result_t ADC_PollingSA(M4_ADC_TypeDef *ADCx, uint16_t pu16AdcVal[], uint8_t u8Length, uint32_t u32Timeout) +{ + uint32_t u32Ch; + uint32_t u32TimeCnt; + uint8_t au8DrLen[ADC_UNIT_COUNT] = {ADC1_CH_COUNT, ADC2_CH_COUNT, ADC3_CH_COUNT}; + en_result_t enRet = ErrorInvalidParameter; + + if ((pu16AdcVal != NULL) && \ + (u8Length != 0U) && (u32Timeout != 0U) && \ + IS_ADDRESS_ALIGN_HALFWORD(&pu16AdcVal[0U])) + { + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + u32TimeCnt = u32Timeout * (HCLK_VALUE / 10U / 1000U); + enRet = ErrorTimeout; + /* Start ADC.*/ + WRITE_REG8(ADCx->STR, ADC_STR_STRT); + while (u32TimeCnt-- != 0U) + { + if (READ_REG8_BIT(ADCx->ISR, ADC_SEQ_FLAG_EOCA) != 0U) + { + if (u8Length < au8DrLen[ADC_IDX(ADCx)]) + { + u32Ch = ADCx->CHSELRA; + (void)ADC_GetChannelData(ADCx, u32Ch, pu16AdcVal, u8Length); + } + else + { + (void)ADC_GetAllData(ADCx, pu16AdcVal, u8Length); + } + /* Clear EOC flag. */ + SET_REG8_BIT(ADCx->ISCLRR, ADC_ISCLRR_CLREOCAF); + enRet = Ok; + break; + } + } + if (enRet != Ok) + { + /* Stop ADC if timeout. */ + WRITE_REG8(ADCx->STR, 0U); + } + } + + return enRet; +} + +/** + * @brief Start the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @retval None + */ +void ADC_Start(M4_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, ADC_STR_STRT); +} + +/** + * @brief Stop the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @retval None + */ +void ADC_Stop(M4_ADC_TypeDef *ADCx) +{ + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + WRITE_REG8(ADCx->STR, 0U); +} + +/** + * @brief Get all of the channels' value of the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [out] pu16AdcVal Pointer to an uint16_t type memory which the ADC values to be stored. + * pu16AdcVal[0] = value of Channel 0, + * pu16AdcVal[1] = value of Channel 1, + * pu16AdcVal[2] = value of Channel 2, + * @param [in] u8Length The length of the ADC value to be got. + * It CAN NOT be less than the number of channels of the ADC unit. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: -pu16AdcVal == NULL. + * -The base address of 'pu16AdcVal' is not 2-byte aligned. + */ +en_result_t ADC_GetAllData(const M4_ADC_TypeDef *ADCx, uint16_t pu16AdcVal[], uint8_t u8Length) +{ + uint8_t u8AdcIdx; + uint32_t i; + uint32_t u32DRAddr; + uint8_t au8DrLen[ADC_UNIT_COUNT] = {ADC1_CH_COUNT, ADC2_CH_COUNT, ADC3_CH_COUNT}; + en_result_t enRet = ErrorInvalidParameter; + + if ((pu16AdcVal != NULL) && IS_ADDRESS_ALIGN_HALFWORD(&pu16AdcVal[0U])) + { + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + u8AdcIdx = ADC_IDX(ADCx); + DDL_ASSERT(u8Length >= au8DrLen[u8AdcIdx]); + + if (u8Length > au8DrLen[u8AdcIdx]) + { + u8Length = au8DrLen[u8AdcIdx]; + } + u32DRAddr = (uint32_t)&ADCx->DR0; + for (i=0U; iDR0; + while ((u32TargetCh != 0U) && (u8Length != 0U)) + { + if ((u32TargetCh & 0x1UL) != 0U) + { + pu16AdcVal[j++] = RW_MEM16(u32DRAddr + i * 2U); + u8Length--; + } + u32TargetCh >>= 1U; + i++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Get a specified channel's value of the specified ADC unit. + * @param [in] ADCx Pointer to ADC instance register base. + * This parameter can be a value of the following: + * @arg M4_ADC1: ADC unit 1 instance register base. + * @arg M4_ADC2: ADC unit 2 instance register base. + * @arg M4_ADC3: ADC unit 3 instance register base. + * @param [in] u8ChNum The index number of ADC channel. + * The following parameters that from @ref ADC_Channel_Number can be used: + * @arg ADC_CH_NUM_0 ~ ADC_CH_NUM_15: For ADC1 and ADC2. + * @arg ADC_CH_NUM_0 ~ ADC_CH_NUM_19: For ADC3. + * @retval An uint16_t type value between 0 ~ 4095. + */ +uint16_t ADC_GetValue(const M4_ADC_TypeDef *ADCx, uint8_t u8ChNum) +{ + uint32_t u32DRAddr; +#ifdef __DEBUG + uint8_t au8DrLen[ADC_UNIT_COUNT] = {ADC1_CH_COUNT, ADC2_CH_COUNT, ADC3_CH_COUNT}; + DDL_ASSERT(u8ChNum < au8DrLen[ADC_IDX(ADCx)]); +#endif + DDL_ASSERT(IS_ADC_UNIT(ADCx)); + + u32DRAddr = (uint32_t)&ADCx->DR0 + ((uint32_t)u8ChNum * 2U); + return RW_MEM16(u32DRAddr); +} + +/** + * @} + */ + +#endif /* DDL_ADC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_aes.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_aes.c new file mode 100644 index 0000000000000000000000000000000000000000..7f9c0efc3a819916f5a18db8c4d98aad732495e0 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_aes.c @@ -0,0 +1,376 @@ +/** + ******************************************************************************* + * @file hc32f4a0_aes.c + * @brief This file provides firmware functions to manage the Advanced Encryption + * Standard(AES). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_aes.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_AES AES + * @brief AES Driver Library + * @{ + */ + +#if (DDL_AES_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup AES_Local_Macros AES Local Macros + * @{ + */ +/* Delay count for timeout */ +#define AES_TIMEOUT (30000UL) + +/** + * @defgroup AES_KEY_LENGTH AES key length in bytes + * @{ + */ +#define AES_KEY_LEN_128BIT (16U) +#define AES_KEY_LEN_192BIT (24U) +#define AES_KEY_LEN_256BIT (32U) +/** + * @} + */ + +/** + * @defgroup AES_Check_Parameters_Validity AES Check Parameters Validity + * @{ + */ +#define IS_AES_KEYLENGTH(x) \ +( ((x) == AES_KEY_LEN_128BIT) || \ + ((x) == AES_KEY_LEN_192BIT) || \ + ((x) == AES_KEY_LEN_256BIT)) +/** + * @} + */ +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void AES_WriteData(const uint8_t *pu8Srcdata); +static void AES_ReadData(const uint8_t *pu8Result); +static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeyLength); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup AES_Global_Functions AES Global Functions + * @{ + */ + +/** + * @brief AES encryption. + * @param [in] au8Plaintext Buffer of the plaintext(the source data which will be encrypted). + * @param [in] u32PlaintextSize Length of plaintext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeyLength Buffer of the key in bytes. + * @param [out] au8Ciphertext Buffer of the ciphertext. + * @retval An en_result_t enumeration value: + * Ok: Encryption successfully. + * ErrorInvalidParameter: Invalid parameter + * ErrorTimeout: Encryption error timeout + */ +en_result_t AES_Encrypt(uint8_t au8Plaintext[], + uint32_t u32PlaintextSize, + const uint8_t *pu8Key, + uint8_t u8KeyLength, + uint8_t au8Ciphertext[]) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TimeCount = 0UL; + uint32_t u32Index = 0UL; + uint8_t au8FillBuffer[16U] = {0U}; + if((au8Plaintext != NULL) && (u32PlaintextSize != 0UL) \ + && (pu8Key != NULL) && (u8KeyLength != 0U) \ + && (au8Ciphertext != NULL)) + { + DDL_ASSERT(IS_AES_KEYLENGTH(u8KeyLength)); + enRet = Ok; + while(u32PlaintextSize > 0UL) + { + /* Wait for AES to stop */ + while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1U) + { + if(u32TimeCount++ >= AES_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + if (u32PlaintextSize >= AES_BLOCK_LEN) + { + AES_WriteData(&au8Plaintext[u32Index]); + } + else + { + (void)memcpy(au8FillBuffer, &au8Plaintext[u32Index], u32PlaintextSize); + AES_WriteData(&au8FillBuffer[0U]); + } + AES_WriteKey(pu8Key, u8KeyLength); + switch (u8KeyLength) + { + case AES_KEY_LEN_128BIT: + MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_128BIT); + break; + + case AES_KEY_LEN_192BIT: + MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_192BIT); + break; + + case AES_KEY_LEN_256BIT: + MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_256BIT); + break; + + default: + break; + } + /* Set AES encrypt. */ + CLEAR_REG32_BIT(M4_AES->CR, AES_CR_MODE); + /* Start AES calculating. */ + SET_REG32_BIT(M4_AES->CR, AES_CR_START); + /* Wait for AES to stop */ + u32TimeCount = 0UL; + while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1U) + { + if(u32TimeCount++ > AES_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + AES_ReadData(&au8Ciphertext[u32Index]); + if (u32PlaintextSize < AES_BLOCK_LEN) + { + u32PlaintextSize = 0UL; + } + else + { + u32PlaintextSize -= AES_BLOCK_LEN; + } + u32Index += AES_BLOCK_LEN; + } + } + } + } + return enRet; +} + +/** + * @brief AES decryption. + * @param [in] au8Ciphertext Buffer of the Ciphertext(the source data which will be decrypted). + * @param [in] u32CiphertextSize Length of ciphertext in bytes. + * @param [in] pu8Key Pointer to the AES key. + * @param [in] u8KeyLength Length of key in bytes. + * @param [out] au8Plaintext Buffer of the plaintext. + * @retval An en_result_t enumeration value: + * Ok: Decryption successfully. + * ErrorInvalidParameter: Invalid parameter + * ErrorTimeout: Decryption error timeout + */ +en_result_t AES_Decrypt(uint8_t au8Ciphertext[], + uint32_t u32CiphertextSize, + const uint8_t *pu8Key, + uint8_t u8KeyLength, + uint8_t au8Plaintext[]) +{ + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + uint32_t u32Index = 0UL; + if((au8Plaintext != NULL) && (u32CiphertextSize != 0UL) \ + && (pu8Key != NULL) && (u8KeyLength != 0U) \ + && (au8Ciphertext != NULL)) + { + DDL_ASSERT(IS_AES_KEYLENGTH(u8KeyLength)); + enRet = Ok; + while(u32CiphertextSize > 0UL) + { + /* Wait for AES to stop */ + while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1U) + { + if(u32TimeCount++ > AES_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + AES_WriteData(&au8Ciphertext[u32Index]); + AES_WriteKey(pu8Key, u8KeyLength); + switch (u8KeyLength) + { + case AES_KEY_LEN_128BIT: + MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_128BIT); + break; + + case AES_KEY_LEN_192BIT: + MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_192BIT); + break; + + case AES_KEY_LEN_256BIT: + MODIFY_REG32(M4_AES->CR, AES_CR_KEYSIZE, AES_KEY_SIZE_256BIT); + break; + + default: + break; + } + /* Set AES decrypt. */ + SET_REG32_BIT(M4_AES->CR, AES_CR_MODE); + /* Start AES calculating. */ + SET_REG32_BIT(M4_AES->CR, AES_CR_START); + /* Wait for AES to stop */ + u32TimeCount = 0UL; + while(READ_REG32_BIT(M4_AES->CR, AES_CR_START) == 1UL) + { + if(u32TimeCount++ >= AES_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + AES_ReadData(&au8Plaintext[u32Index]); + u32CiphertextSize -= AES_BLOCK_LEN; + u32Index += AES_BLOCK_LEN; + } + } + } + } + return enRet; +} + +/** + * @brief Write the input buffer in data register. + * @param [in] pu8Srcdata Point to the source data buffer. + * @retval None + */ +static void AES_WriteData(const uint8_t *pu8Srcdata) +{ + uint8_t i; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + uint32_t u32SrcAddr = (uint32_t)pu8Srcdata; + + for(i = 0U; i < 4U; i++) + { + RW_MEM32(u32DrAddr) = RW_MEM32(u32SrcAddr); + u32SrcAddr += 4UL; + u32DrAddr += 4UL; + } +} + +/** + * @brief Read the from data register. + * @param [out] pu8Result Point to the result buffer. + * @retval None + */ +static void AES_ReadData(const uint8_t *pu8Result) +{ + uint8_t i; + uint32_t u32DrAddr = (uint32_t)&(M4_AES->DR0); + uint32_t u32ResultAddr = (uint32_t)pu8Result; + for(i = 0U; i < 4U; i++) + { + RW_MEM32(u32ResultAddr) = RW_MEM32(u32DrAddr); + u32DrAddr += 4U; + u32ResultAddr += 4UL; + } +} + +/** + * @brief Write the input buffer in key register. + * @param [in] pu8Key Pointer to the kry buffer. + * @param [in] u8KeyLength Length of key in bytes. + * @retval None + */ +static void AES_WriteKey(const uint8_t *pu8Key, uint8_t u8KeyLength) +{ + uint8_t i; + uint8_t Length = 0U; + uint32_t u32KeyAddr = (uint32_t)&(M4_AES->KR0); + uint32_t u32DataAddr = (uint32_t)pu8Key; + switch (u8KeyLength) + { + case AES_KEY_LEN_128BIT: + Length = 4U; + break; + case AES_KEY_LEN_192BIT: + Length = 6U; + break; + case AES_KEY_LEN_256BIT: + Length = 8U; + break; + default: + break; + } + for(i = 0U; i < Length; i++) + { + RW_MEM32(u32KeyAddr) = RW_MEM32(u32DataAddr); + u32DataAddr += 4UL; + u32KeyAddr += 4UL; + } +} +/** + * @} + */ + +#endif /* DDL_AES_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_can.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_can.c new file mode 100644 index 0000000000000000000000000000000000000000..d8160d9f4e468d91e4d859dcef242306499e2c54 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_can.c @@ -0,0 +1,2107 @@ +/** + ******************************************************************************* + * @file hc32f4a0_can.c + * @brief This file provides firmware functions to manage the CAN. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-08-10 Wuze Refined CAN_GetStatusVal() + 2020-12-14 Wuze 1. Fixed a bug of CAN_TTC_TransData(); Refined CAN_SBTConfig() + 2. Modified comment of structure stc_can_bt_cfg_t + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_can.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_CAN CAN + * @brief CAN Driver Library + * @{ + */ + +#if (DDL_CAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CAN_Local_Macros CAN Local Macros + * @{ + */ + +/** + * @defgroup CAN_Configuration_Bit_Mask CAN Configuration Bit Mask + * @{ + */ +#define CAN_LB_MODE_MSK (CAN_CFG_STAT_LBMI | CAN_CFG_STAT_LBME) +#define CAN_TRANS_MODE_MSK (CAN_CFG_STAT_TPSS | CAN_CFG_STAT_TSSS) +#define CAN_TTC_FLAG_CLR_MSK (CAN_TTC_FLAG_TTI | CAN_TTC_FLAG_WTI) +/** + * @} + */ + +/** + * @defgroup CAN_Register_Bit_Band CAN Register Bit Band + * @{ + */ +#define __BIT_BAND_BASE (0x42000000UL) +#define __PERIP_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIP_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __BIT_BAND_BASE) +#define BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup CAN_Check_Parameters_Validity CAN check parameters validity + * @{ + */ +#define IS_CAN_UNIT(x) \ +( ((x) == M4_CAN1) || \ + ((x) == M4_CAN2)) + +#define IS_CAN_SBT_SEG1(x) \ +( ((x) >= 2U) && \ + ((x) <= 65U)) + +#define IS_CAN_SBT_SEG2(x) \ +( ((x) >= 1U) && \ + ((x) <= 8U)) + +#define IS_CAN_FD_SBT_SEG2(x) \ +( ((x) >= 1U) && \ + ((x) <= 32U)) + +#define IS_CAN_SBT_SJW(x) \ +( ((x) >= 1U) && \ + ((x) <= 16U)) + +#define IS_CAN_SBT_PRESC(x) \ +( ((x) >= 1U) && \ + ((x) <= 256U)) + +#define IS_CAN_FBT_SEG1(x) \ +( ((x) >= 2U) && \ + ((x) <= 17U)) + +#define IS_CAN_FBT_SEG2(x) \ +( ((x) >= 1U) && \ + ((x) <= 8U)) + +#define IS_CAN_FBT_SJW(x) \ +( ((x) >= 1U) && \ + ((x) <= 8U)) + +#define IS_CAN_FBT_PRESC(x) \ +( ((x) >= 1U) && \ + ((x) <= 256U)) + +#define IS_CAN_SBT_PRIO_MODE(x) \ +( ((x) == CAN_STB_PRIO_FIFO) || \ + ((x) == CAN_STB_PRIO_ID)) + +#define IS_CAN_IDE(x) \ +( ((x) == 0U) || \ + ((x) == 1U)) + +#define IS_CAN_SELF_ACK_CMD(x) \ +( ((x) == CAN_SELF_ACK_DISABLE) || \ + ((x) == CAN_SELF_ACK_ENABLE)) + +#define IS_CAN_TB_TYPE(x) \ +( ((x) == CAN_BUF_PTB) || \ + ((x) == CAN_BUF_STB)) + +#define IS_CAN_STB_TX_CTRL(x) \ +( ((x) == CAN_STB_TRANS_ALL) || \ + ((x) == CAN_STB_TRANS_ONE)) + +#define IS_CAN_WORK_MODE(x) \ +( ((x) <= CAN_MODE_ELB_SILENT)) + +#define IS_CAN_TRANS_MODE(x) \ +( ((x) == CAN_TRANS_PTB_STB_AUTO_RETX) || \ + ((x) == CAN_TRANS_PTB_SSHOT) || \ + ((x) == CAN_TRANS_STB_SSHOT) || \ + ((x) == CAN_TRANS_PTB_STB_SSHOT)) + +#define IS_CAN_RB_STORE_SEL(x) \ +( ((x) == CAN_RB_STORE_CORRECT_DATA) || \ + ((x) == CAN_RB_STORE_ALL_DATA)) + +#define IS_CAN_RB_OVF_OP(x) \ +( ((x) == CAN_RB_OVF_SAVE_NEW) || \ + ((x) == CAN_RB_OVF_DISCARD_NEW)) + +#define IS_CAN_RBS_FULL_WARN_LIMIT(x) \ +( ((x) >= CAN_RBS_WARN_LIMIT_MIN) && \ + ((x) <= CAN_RBS_WARN_LIMIT_MAX)) + +#define IS_CAN_ERR_WARN_LIMIT(x) \ +( ((x) < 16U)) + +#define IS_CAN_AF_MSK_TYPE(x) \ +( ((x) == CAN_AF_MSK_STD_EXT) || \ + ((x) == CAN_AF_MSK_STD) || \ + ((x) == CAN_AF_MSK_EXT)) + +#define IS_CAN_1_BIT_MSK(x) \ +( ((x) != 0U) && \ + (((x) & ((x) - 1U)) == 0U)) + +#define IS_CAN_BIT_MSK(x, msk) \ +( ((x) != 0U) && \ + (((x) | (msk)) == (msk))) + +#define IS_CAN_FD_MODE(x) \ +( ((x) == CAN_FD_MODE_BOSCH) || \ + ((x) == CAN_FD_MODE_ISO_11898)) + +#define IS_CAN_FD_SSP(x) \ +( ((x) < 128U)) + +#define IS_CAN_TDC_CMD(x) \ +( ((x) == CAN_FD_TDC_DISABLE) || \ + ((x) == CAN_FD_TDC_ENABLE)) + +#define IS_CAN_TTC_TB_MODE(x) \ +( ((x) == CAN_TTC_TB_MODE_NORMAL) || \ + ((x) == CAN_TTC_TB_MODE_PTR)) + +#define IS_CAN_TTC_TBS(x) \ +( ((x) <= CAN_TTC_TBS_STB3)) + +#define IS_CAN_TTC_TRIG_TYPE(x) \ +( ((x) == CAN_TTC_TRIG_IMMED_TRIG) || \ + ((x) == CAN_TTC_TRIG_TIME_TRIG) || \ + ((x) == CAN_TTC_TRIG_SSHOT_TRANS_TRIG) || \ + ((x) == CAN_TTC_TRIG_TRANS_START_TRIG) || \ + ((x) == CAN_TTC_TRIG_TRANS_STOP_TRIG)) + +#define IS_CAN_TTC_NTU_PRESC(x) \ +( ((x) == CAN_TTC_NTU_PRESC_1) || \ + ((x) == CAN_TTC_NTU_PRESC_2) || \ + ((x) == CAN_TTC_NTU_PRESC_4) || \ + ((x) == CAN_TTC_NTU_PRESC_8)) + +#define IS_CAN_TTC_TX_EN_WINDOW(x) \ +( (x) <= 16U) + +/** + * @} + */ + +/** + * @defgroup CAN_Miscellaneous_Macros CAN Miscellaneous Macros + * @{ + */ +#define CAN_RBS_CNT (8U) /*!< Each CAN unit has 8 receive buffer slots. */ +#define CAN_RBS_WARN_LIMIT_MIN (1U) +#define CAN_RBS_WARN_LIMIT_MAX (CAN_RBS_CNT) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CAN_Global_Functions CAN Global Functions + * @{ + */ + +/** + * @brief Initializes the specified CAN peripheral according to the specified parameters + * in the stc_can_init_t type structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] pstcInit Pointer to a stc_can_init_t structure value that + * contains the configuration information for the CAN. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL + */ +en_result_t CAN_Init(M4_CAN_TypeDef *CANx, const stc_can_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { +#ifdef __DEBUG + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInit->enCANFDCmd)); + if (pstcInit->enCANFDCmd == Disable) + { + DDL_ASSERT(IS_CAN_SBT_SEG2(pstcInit->stcSBT.u32SEG2)); + } + else + { + DDL_ASSERT(IS_CAN_FD_SBT_SEG2(pstcInit->stcSBT.u32SEG2)); + } +#endif + /* Software reset. */ + CAN_SWReset(CANx); + /* Defines slow bit time. */ + (void)CAN_SBTConfig(CANx, &pstcInit->stcSBT); + /* Specifies STB priority mode. */ + CAN_SetSTBPrioMode(CANx, pstcInit->u8STBPrioMode); + /* Configures acceptance filters. */ + (void)CAN_AFConfig(CANx, pstcInit->u16AFSel, pstcInit->pstcAFCfg); + /* Configures CAN-FD if enabled. */ + CAN_FD_Cmd(CANx, Disable); + if (pstcInit->enCANFDCmd == Enable) + { + (void)CAN_FD_Config(CANx, &pstcInit->stcFDCfg); + CAN_FD_Cmd(CANx, Enable); + } + + /* CAN bus enters normal communication mode. */ + CAN_EnterNormalComm(CANx); + /* Specifies work mode. */ + CAN_SetWorkMode(CANx, pstcInit->u8WorkMode); + /* Specifies transmission mode. */ + CAN_SetTransMode(CANx, pstcInit->u8TransMode); + + CAN_SetRBStoreSel(CANx, pstcInit->u8RBStoreSel); + CAN_SetRBSWarnLimit(CANx, pstcInit->u8RBSWarnLimit); + CAN_SetErrWarnLimit(CANx, pstcInit->u8ErrWarnLimit); + /* Specifies the operation when receiving buffer overflow. */ + CAN_SetRBOvfOp(CANx, pstcInit->u8RBOvfOp); + /* Enable acceptance filters that configured before. */ + SET_REG16_BIT(CANx->ACFEN, pstcInit->u16AFSel); + + /* Enable or disable self-ACK. */ + DDL_ASSERT(IS_CAN_SELF_ACK_CMD(pstcInit->u8SelfACKCmd)); + MODIFY_REG8(CANx->RCTRL, CAN_RCTRL_SACK, pstcInit->u8SelfACKCmd); + + /* Clear all status flags. */ + CAN_ClrStatus(CANx, CAN_FLAG_ALL); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for CAN initialization structure. \ + * Slow bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 4. \ + * Bit rate 500Kbps, 1 bit time is 20TQs, sample point is 80%. + * CAN-FD bit time configuration: + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. \ + * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, \ + * secondary sample point is 80%. + * @param [in] pstcInit Pointer to a stc_can_init_t structure value that + * contains the configuration information for the CAN unit. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t CAN_StructInit(stc_can_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + pstcInit->u8WorkMode = CAN_MODE_NORMAL; + pstcInit->u8TransMode = CAN_TRANS_PTB_STB_AUTO_RETX; + pstcInit->u8STBPrioMode = CAN_STB_PRIO_FIFO; + pstcInit->u8RBSWarnLimit = 6U; + pstcInit->u8ErrWarnLimit = 7U; + pstcInit->u16AFSel = CAN_AF1; + pstcInit->u8RBStoreSel = CAN_RB_STORE_CORRECT_DATA; + pstcInit->u8RBOvfOp = CAN_RB_OVF_DISCARD_NEW; + pstcInit->u8SelfACKCmd = CAN_SELF_ACK_DISABLE; + pstcInit->pstcAFCfg = NULL; + /* + * Synchronization Segment(SS): Fixed as 1TQ + * Propagation Time Segment(PTS) and Phase Buffer Segment 1(PBS1): 15TQs + * Phase Buffer Segment 2(PBS2): 4TQs + * + * Field 'S_SEG_1' in register CAN_SBT contains SS, PTS and PBS1. + * Field 'S_SEG_2' in register CAN_SBT only contains PBS2. + * Sample point = (SS + PTS + PBS1) / (SS + PTS + PBS1 + PBS2) + * = (1 + 15) / (1 + 15 + 4) + * = 80%. + */ + pstcInit->stcSBT.u32SEG1 = 1U + 15U; + pstcInit->stcSBT.u32SEG2 = 4U; + pstcInit->stcSBT.u32SJW = 2U; + pstcInit->stcSBT.u32Prescaler = 4U; + + /* + * Set enCANFDCmd as Enable if CAN-FD is needed. + * + * u8TDCCmd: Enalbe(CAN_FD_TDC_ENABLE) or disable(CAN_FD_TDC_DISABLE) transmitter delay compensation. + * u8TDCSSP: The position(TQs) of secondary sample point. + * + * Primary sample point: u32SEG1 / (u32SEG1 + u32SEG2) = 80% + * Secondary sample point: u8TDCSSP / (u32SEG1 + u32SEG2) = 80% + */ + pstcInit->enCANFDCmd = Disable; + (void)CAN_FD_StructInit(&pstcInit->stcFDCfg); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initializes the CAN peripheral. Reset the registers of the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval None + */ +void CAN_DeInit(M4_CAN_TypeDef *CANx) +{ + uint8_t i; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + CLEAR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + for (i=0U; i<2U; i++) + { + WRITE_REG8(CANx->CFG_STAT, 0x80U); + WRITE_REG8(CANx->TCMD, 0x00U); + WRITE_REG8(CANx->TCTRL, 0x90U); + WRITE_REG8(CANx->RCTRL, 0x10U); + WRITE_REG8(CANx->RTIE, 0xFEU); + WRITE_REG8(CANx->RTIF, 0xFFU); + WRITE_REG8(CANx->ERRINT, 0xD5U); + WRITE_REG8(CANx->LIMIT, 0x1BU); + WRITE_REG32(CANx->SBT, 0x01020203U); + WRITE_REG32(CANx->FBT, 0x01020203U); + WRITE_REG8(CANx->EALCAP, 0x00U); + WRITE_REG8(CANx->TDC, 0x00U); + WRITE_REG8(CANx->RECNT, 0x00U); + WRITE_REG8(CANx->TECNT, 0x00U); + WRITE_REG8(CANx->ACFCTRL, 0x00U); + WRITE_REG8(CANx->ACFEN, 0x01U); + WRITE_REG8(CANx->TBSLOT, 0x00U); + WRITE_REG8(CANx->TTCFG, 0xD8U); + WRITE_REG16(CANx->TRG_CFG, 0x00U); + WRITE_REG16(CANx->TT_TRIG, 0x00U); + WRITE_REG16(CANx->TT_WTRIG, 0x00U); + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); + } +} + +/** + * @brief Software reset the specified CAN unit. \ + Software reset is a partial reset and CANNOT reset all registers. \ + Some registers need software reset before written. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval None + */ +void CAN_SWReset(M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); +} + +/** + * @brief Set the CAN node to enter the normal communication mode. + * When this state is set, it takes 11 CAN bit time for this node to participate in communication. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval None + */ +void CAN_EnterNormalComm(M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + CLEAR_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_RESET); +} + +/** + * @brief Specifies work mode for the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8WorkMode Work mode of CAN. + * This parameter can be a value of @ref CAN_Work_Mode + * @arg CAN_MODE_NORMAL: Normal work mode. + * @arg CAN_MODE_SILENT: Silent work mode. Prohibit data transmission. + * @arg CAN_MODE_ILB: Internal loopback mode, just for self-test while developing. + * @arg CAN_MODE_ELB: External loopback mode, just for self-test while developing. + * @arg CAN_MODE_ELB_SILENT: External loppback silent mode, just for self-test while developing. \ + * It is forbidden to respond to received frames and error frames, but data can be transmitted. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_SetWorkMode(M4_CAN_TypeDef *CANx, uint8_t u8WorkMode) +{ + uint8_t u8CFGSTAT = 0U; + uint8_t u8TCMD = 0U; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_WORK_MODE(u8WorkMode)); + + switch (u8WorkMode) + { + case CAN_MODE_SILENT: + u8TCMD = CAN_TCMD_LOM; + break; + case CAN_MODE_ILB: + u8CFGSTAT = CAN_CFG_STAT_LBMI; + break; + case CAN_MODE_ELB: + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_MODE_ELB_SILENT: + u8TCMD = CAN_TCMD_LOM; + u8CFGSTAT = CAN_CFG_STAT_LBME; + break; + case CAN_MODE_NORMAL: + default: + break; + } + + MODIFY_REG8(CANx->CFG_STAT, CAN_LB_MODE_MSK, u8CFGSTAT); + MODIFY_REG8(CANx->TCMD, CAN_TCMD_LOM, u8TCMD); +} + +/** + * @brief Specifies transmission mode for the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8TransMode PTB/STB transmission mode. + * This parameter can be a value of @ref CAN_Trans_Mode + * @arg CAN_TRANS_PTB_STB_AUTO_RETX: Both PTB and STB automatically retransmit. + * @arg CAN_TRANS_PTB_SSHOT: PTB single shot transmit. + * @arg CAN_TRANS_STB_SSHOT: STB single shot transmit. + * @arg CAN_TRANS_PTB_STB_SSHOT: STB and PTB both single shot transmit. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_SetTransMode(M4_CAN_TypeDef *CANx, uint8_t u8TransMode) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TRANS_MODE(u8TransMode)); + MODIFY_REG8(CANx->CFG_STAT, CAN_TRANS_MODE_MSK, u8TransMode); +} + +/** + * @brief Specifies STB transmission priority mode for the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8STBPrioMode STB transmission priority mode. + * This parameter can be a value of @ref CAN_STB_Priority_Mode + * @arg CAN_STB_PRIO_FIFO: Data first in first be transmitted. + * @arg CAN_STB_PRIO_ID : Data with smallest ID first be transmitted. + * @retval None + * @note Whatever the priority mode of STB is, PTB always has the highest priority. + */ +void CAN_SetSTBPrioMode(M4_CAN_TypeDef *CANx, uint8_t u8STBPrioMode) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_SBT_PRIO_MODE(u8STBPrioMode)); + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TSMODE, u8STBPrioMode); +} + +/** + * @brief Specifies the receive buffer store selection for specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8RBStoreSel Receive buffer store selection. + * This parameter can be a value of @ref CAN_RB_Store_Selection + * @arg CAN_RB_STORE_CORRECT_DATA: Receive buffer stores correct data frames only. + * @arg CAN_RB_STORE_ALL_DATA: Receive buffer stores all data frames, includes error data. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_SetRBStoreSel(M4_CAN_TypeDef *CANx, uint8_t u8RBStoreSel) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_RB_STORE_SEL(u8RBStoreSel)); + MODIFY_REG8(CANx->RCTRL, CAN_RCTRL_RBALL, u8RBStoreSel); +} + +/** + * @brief Specifies the operation when receiving buffer overflow. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8RBOvfOperation Operation when receive buffer overflow. + * This parameter can be a value of @ref CAN_RB_Overflow_Operation + * @arg CAN_RB_OVF_SAVE_NEW: Saves the newly received data and the first received data will be overwritten. + * @arg CAN_RB_OVF_DISCARD_NEW: Discard the newly received data. + * @retval None + */ +void CAN_SetRBOvfOp(M4_CAN_TypeDef *CANx, uint8_t u8RBOvfOperation) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_RB_OVF_OP(u8RBOvfOperation)); + MODIFY_REG8(CANx->RCTRL, CAN_RCTRL_ROM, u8RBOvfOperation); +} + +/** + * @brief Enable or disable the specified interrupts of the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u32IntType Interrupt type of CAN. Set this parameter to 0xFFFFFFFF to select all the interrupts of CAN. + * This parameter can be values of @ref CAN_Interrupt_Type + * @arg CAN_INT_ERR_INT: Register bit RTIE.EIE. Error interrupt. + * @arg CAN_INT_STB_TRANS_OK: Register bit RTIE.TSIE. Secondary transmit buffer was transmitted successfully. + * @arg CAN_INT_PTB_TRANS_OK: Register bit RTIE.TPIE. Primary transmit buffer was transmitted successfully. + * @arg CAN_INT_RB_ALMOST_FULL: Register bit RTIE.RAFIE. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_INT_RB_FIFO_FULL: Register bit RTIE.RFIE. The FIFO of receive buffer is full. + * @arg CAN_INT_RX_OVERRUN: Register bit RTIE.ROIE. Receive buffers are full and there is a further message to be stored. + * @arg CAN_INT_RX: Register bit RTIE.RIE. Received a valid data frame or remote frame. + * @arg CAN_INT_BUS_ERR: Register bit ERRINT.BEIE. Arbitration lost caused bus error + * @arg CAN_INT_ARB_LOST: Register bit ERRINT.ALIE. Arbitration lost. + * @arg CAN_INT_ERR_PASSIVE: Register bit ERRINT.EPIE. A change from error-passive to error-active or error-active to error-passive has occurred. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified interrupts. + * @arg Disable: Disable the specified interrupts. + * @retval None + */ +void CAN_IntCmd(M4_CAN_TypeDef *CANx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint8_t u8RTIE; + uint8_t u8ERRINT; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32IntType &= CAN_INT_ALL; + u8RTIE = (uint8_t)u32IntType; + u8ERRINT = (uint8_t)(u32IntType >> 8U); + + if (enNewState == Enable) + { + SET_REG8_BIT(CANx->RTIE, u8RTIE); + SET_REG8_BIT(CANx->ERRINT, u8ERRINT); + } + else + { + CLEAR_REG8_BIT(CANx->RTIE, u8RTIE); + CLEAR_REG8_BIT(CANx->ERRINT, u8ERRINT); + } +} + +/** + * @brief Configures slow bit timing(SBT). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] pstcCfg Pointer to a stc_can_bt_cfg_t structure value that + * contains the configuration information for SBT. + * @arg u32SEG1: TQs of segment 1. Contains synchronization segment, \ + * propagation time segment and phase buffer segment 1. + * @arg u32SEG2: TQs of segment 2. Phase buffer segment 2. + * @arg u32SJW: TQs of synchronization jump width. + * @arg u32Prescaler: Range [1, 256]. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + * @note 1. Restrictions: u32SEG1 >= u32SEG2 + 1, u32SEG2 >= u32SJW. + * @note 2. TQ = u32Prescaler / CANClock. + * @note 3. Slow bit time = (u32SEG1 + u32SEG2) * TQ. + * @note 4. Call this function when CFG_STAT.RESET is 1. + */ +en_result_t CAN_SBTConfig(M4_CAN_TypeDef *CANx, const stc_can_bt_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; +#ifdef __DEBUG + uint32_t u32Addr; + uint32_t u32BitPos = 0U; +#endif + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_SBT_SEG1(pstcCfg->u32SEG1)); + DDL_ASSERT(IS_CAN_SBT_SJW(pstcCfg->u32SJW)); + DDL_ASSERT(IS_CAN_SBT_PRESC(pstcCfg->u32Prescaler)); +#ifdef __DEBUG + if (CANx == M4_CAN2) + { + u32BitPos = 1U; + } + /* If CAN-FD enabled. */ + u32Addr = (uint32_t)&M4_PERIC->CAN_SYCTLREG; + if (BIT_BAND(u32Addr, u32BitPos) == (uint32_t)Disable) + { + DDL_ASSERT(IS_CAN_SBT_SEG2(pstcCfg->u32SEG2)); + } + else + { + DDL_ASSERT(IS_CAN_FD_SBT_SEG2(pstcCfg->u32SEG2)); + } +#endif + WRITE_REG32(CANx->SBT, ((pstcCfg->u32SEG1 - 2U) | \ + ((pstcCfg->u32SEG2 - 1U) << CAN_SBT_S_SEG_2_POS) | \ + ((pstcCfg->u32SJW - 1U) << CAN_SBT_S_SJW_POS) | \ + ((pstcCfg->u32Prescaler - 1U) << CAN_SBT_S_PRESC_POS))); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Get arbitration lost position of a frame. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval A uint8_t type value of arbitration lost position. + */ +uint8_t CAN_GetArbLostPos(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_ALC)); +} + +/** + * @brief Get error type. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t value of error type. It's can be a value of @ref CAN_Error_Type + * @arg CAN_ERR_NO: No error. + * @arg CAN_ERR_BIT: Error is bit error. + * @arg CAN_ERR_FORM: Error is form error. + * @arg CAN_ERR_STUFF: Error is stuff error. + * @arg CAN_ERR_ACK: Error is ACK error. + * @arg CAN_ERR_CRC: Error is CRC error. + * @arg CAN_ERR_OTHER: Error is other error. + */ +uint8_t CAN_GetErrType(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->EALCAP, CAN_EALCAP_KOER)); +} + +/** + * @brief Set receive buffer slots full warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8RBSWarnLimit: Receive buffer slots full warning limit. Rang is [1, 8]. + * Each CAN unit has 8 receive buffer slots. When the number of received frames \ + * reaches the value specified by parameter 'u8RBSWarnLimit', register bit RTIF.RAFIF is set and \ + * the interrupt occurred if it was enabled. + * @retval None + */ +void CAN_SetRBSWarnLimit(M4_CAN_TypeDef *CANx, uint8_t u8RBSWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_RBS_FULL_WARN_LIMIT(u8RBSWarnLimit)); + + u8RBSWarnLimit <<= CAN_LIMIT_AFWL_POS; + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_AFWL, u8RBSWarnLimit); +} + +/** + * @brief Set error warning limit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8ErrWarnLimit Programmable error warning limit. Range is [0, 15]. + * Error warning limit = (u8ErrWarnLimit + 1) * 8. + * @retval None + */ +void CAN_SetErrWarnLimit(M4_CAN_TypeDef *CANx, uint8_t u8ErrWarnLimit) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_ERR_WARN_LIMIT(u8ErrWarnLimit)); + MODIFY_REG8(CANx->LIMIT, CAN_LIMIT_EWL, u8ErrWarnLimit); +} + +/** + * @brief Get receive error count(REC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value of REC. + */ +uint8_t CAN_GetREC(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (CANx->RECNT); +} + +/** + * @brief Get transmission error count(TEC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value of TEC. + */ +uint8_t CAN_GetTEC(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (CANx->TECNT); +} + +/** + * @brief Clear receive error count(REC) and transmission error count(TEC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval None + * @note Set CFG_STAT.BUSOFF to 1 to clear REC and TEC. ONLY for TEST mode! + */ +void CAN_ClrErrCount(M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + SET_REG8_BIT(CANx->CFG_STAT, CAN_CFG_STAT_BUSOFF); +} + +/** + * @brief Configures acceptance filter. Set ID and ID mask for the specified acceptance filters. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u16AFSel Acceptance filter enable bit. + * This parameter can be values of @ref CAN_AF + * @arg CAN_AF1 ~ CAN_AF16 + * @param [in] pstcAFCfg Points to a stc_can_af_cfg_t structure type array which contains ID and ID mask + * values for the acceptance filters specified by parameter u16AFSel. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: -u16AFSel == 0U. + * -pstcAFCfg == NULL. + * @note Call this function when CFG_STAT.RESET is 1. + */ +en_result_t CAN_AFConfig(M4_CAN_TypeDef *CANx, uint16_t u16AFSel, const stc_can_af_cfg_t pstcAFCfg[]) +{ + uint8_t u8AFAddr = 0U; + uint8_t i = 0U; + en_result_t enRet = ErrorInvalidParameter; + + if ((u16AFSel != 0U) && (pstcAFCfg != NULL)) + { + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + while (u16AFSel != 0U) + { + if ((u16AFSel & (uint16_t)0x1U) != 0U) + { + DDL_ASSERT(IS_CAN_AF_MSK_TYPE(pstcAFCfg[i].u32MskType)); + + WRITE_REG8(CANx->ACFCTRL, u8AFAddr); + WRITE_REG32(CANx->ACF, pstcAFCfg[i].u32ID); + SET_REG8_BIT(CANx->ACFCTRL, CAN_ACFCTRL_SELMASK); + WRITE_REG32(CANx->ACF, pstcAFCfg[i].u32IDMsk | pstcAFCfg[i].u32MskType); + i++; + } + + u16AFSel >>= 1U; + u8AFAddr++; + } + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable acceptance filter. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u16AFSel Acceptance filter enable bit. + * This parameter can be values of @ref CAN_AF + * @arg CAN_AF1 ~ CAN_AF16 + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the acceptance filters that specified by parameter u16AFSel. + * @arg Disable: Disable the acceptance filters that specified by parameter u16AFSel. + * @retval None + */ +void CAN_AFCmd(M4_CAN_TypeDef *CANx, uint16_t u16AFSel, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == Enable) + { + SET_REG16_BIT(CANx->ACFEN, u16AFSel); + } + else + { + CLEAR_REG16_BIT(CANx->ACFEN, u16AFSel); + } +} + +/** + * @brief Get the transmit buffer which is being transmitted. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value of transmit buffer type. It can be a value of @ref CAN_Transmit_Buffer_Type + * @arg CAN_BUF_PTB: The transmit buffer which is being transmitted is PTB. + * @arg CAN_BUF_STB: The transmit buffer which is being transmitted is STB. + * @arg 0xFFU: No transmit buffer is being transmitted. + */ +uint8_t CAN_GetTBType(const M4_CAN_TypeDef *CANx) +{ + uint8_t u8Tmp; + uint8_t u8Ret; + + u8Tmp = CANx->TCMD; + if ((u8Tmp & CAN_TCMD_TPE) != 0U) + { + u8Ret = CAN_BUF_PTB; + } + else if ((u8Tmp & (CAN_TCMD_TSALL | CAN_TCMD_TSONE)) != 0U) + { + u8Ret = CAN_BUF_STB; + } + else + { + u8Ret = 0xFFU; + } + + return u8Ret; +} + +/** + * @brief Abort the transmission of the specified transmit buffer that ready but not started. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8TBType The transmit buffer to be aborted. + * This parameter can be a value of @ref CAN_Transmit_Buffer_Type + * @arg CAN_BUF_PTB: Abort PTB transmission that ready but not started. + * @arg CAN_BUF_STB: Abort STB transmission that ready but not started. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_AbortTrans(M4_CAN_TypeDef *CANx, uint8_t u8TBType) +{ + uint8_t au8Abort[] = {CAN_TCMD_TPA, CAN_TCMD_TSA}; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TB_TYPE(u8TBType)); + SET_REG8_BIT(CANx->TCMD, au8Abort[u8TBType]); +} + +/** + * @brief Get the common flag's status. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u32Flag Status flag. + * This parameter can be a value of @ref CAN_Common_Status_Flag + * @arg CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * @arg CAN_FLAG_BUS_TX: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * @arg CAN_FLAG_BUS_RX: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * @arg CAN_FLAG_RB_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TB_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: \ + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. \ + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * @arg CAN_FLAG_TRANS_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the \ + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than \ + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TRANS_OK: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TRANS_OK: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RB_ALMOST_FULL: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RB_FIFO_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX_OK: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. Arbitration lost caused bus error. + * @arg CAN_FLAG_ARB_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_REACH_WARN_LIMIT: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified status flags is set. + * @arg Reset: None of the specified status flags is set. + */ +en_flag_status_t CAN_GetStatus(const M4_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8CFGSTAT; + uint8_t u8RCTRL; + uint8_t u8RTIE; + uint8_t u8RTIF; + uint8_t u8ERRINT; + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32Flag &= CAN_FLAG_ALL; + + u8CFGSTAT = (uint8_t)(u32Flag); + u8RCTRL = (uint8_t)(u32Flag & CAN_FLAG_RB_OVF); + u8RTIE = (uint8_t)(u32Flag >> 8U); + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + u8CFGSTAT = READ_REG8_BIT(CANx->CFG_STAT, u8CFGSTAT); + u8RCTRL = READ_REG8_BIT(CANx->RCTRL, u8RCTRL); + u8RTIE = READ_REG8_BIT(CANx->RTIE, u8RTIE); + u8RTIF = READ_REG8_BIT(CANx->RTIF, u8RTIF); + u8ERRINT = READ_REG8_BIT(CANx->ERRINT, u8ERRINT); + + if ((u8CFGSTAT != 0U) || (u8RCTRL != 0U) || \ + (u8RTIE != 0U) || (u8RTIF != 0U) || (u8ERRINT != 0U)) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief Clear the common flag's status. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u32Flag Status flag. Set this parameter to 0xFFFFFFFF to select all sataus flags of CAN. + * This parameter can be a value of @ref CAN_Common_Status_Flag + * @arg CAN_FLAG_RB_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TRANS_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter \ + * and the set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than \ + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TRANS_OK: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TRANS_OK: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RB_ALMOST_FULL: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RB_FIFO_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX_OK: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. Arbitration lost caused bus error. + * @arg CAN_FLAG_ARB_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_REACH_WARN_LIMIT: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + * @retval None + */ +void CAN_ClrStatus(M4_CAN_TypeDef *CANx, uint32_t u32Flag) +{ + uint8_t u8RTIF; + uint8_t u8ERRINT; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32Flag &= CAN_FLAG_CLR_MSK; + u8RTIF = (uint8_t)(u32Flag >> 16U); + u8ERRINT = (uint8_t)(u32Flag >> 24U); + + if ((u32Flag & CAN_FLAG_RB_OVF) != 0U) + { + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + } + SET_REG8_BIT(CANx->RTIF, u8RTIF); + SET_REG8_BIT(CANx->ERRINT, u8ERRINT); +} + +/** + * @brief Get the value of status. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint32_t type value that includes the flowing status flags. + * @arg CAN_FLAG_BUS_OFF: Register bit CFG_STAT.BUSOFF. CAN bus off. + * @arg CAN_FLAG_BUS_TX: Register bit CFG_STAT.TACTIVE. CAN bus is transmitting. + * @arg CAN_FLAG_BUS_RX: Register bit CFG_STAT.RACTIVE. CAN bus is receiving. + * @arg CAN_FLAG_RB_OVF: Register bit RCTRL.ROV. Receive buffer is full and there is a further bit to be stored. At least one data is lost. + * @arg CAN_FLAG_TB_FULL: Register bit RTIE.TSFF. Transmit buffers are all full: \ + * TTCFG.TTEN == 0 or TCTRL.TTTEM == 0: ALL STB slots are filled. \ + * TTCFG.TTEN == 1 and TCTRL.TTTEM == 1: Transmit buffer that pointed by TBSLOT.TBPTR is filled. + * @arg CAN_FLAG_TRANS_ABORTED: Register bit RTIF.AIF. Transmit messages requested via TCMD.TPA and TCMD.TSA were successfully canceled. + * @arg CAN_FLAG_ERR_INT: Register bit RTIF.EIF. The CFG_STAT.BUSOFF bit changes, or the relative relationship between the value of the error counter and the \ + * set value of the ERROR warning limit changes. For example, the value of the error counter changes from less than \ + * the set value to greater than the set value, or from greater than the set value to less than the set value. + * @arg CAN_FLAG_STB_TRANS_OK: Register bit RTIF.TSIF. STB was transmitted successfully. + * @arg CAN_FLAG_PTB_TRANS_OK: Register bit RTIF.TPIF. PTB was transmitted successfully. + * @arg CAN_FLAG_RB_ALMOST_FULL: Register bit RTIF.RAFIF. The number of filled RB slot is greater than or equal to the LIMIT.AFWL setting value. + * @arg CAN_FLAG_RB_FIFO_FULL: Register bit RTIF.RFIF. The FIFO of receive buffer is full. + * @arg CAN_FLAG_RX_OVERRUN: Register bit RTIF.ROIF. Receive buffers are all full and there is a further message to be stored. + * @arg CAN_FLAG_RX_OK: Register bit RTIF.RIF. Received a valid data frame or remote frame. + * @arg CAN_FLAG_BUS_ERR: Register bit ERRINT.BEIF. Arbitration lost caused bus error. + * @arg CAN_FLAG_ARB_LOST: Register bit ERRINT.ALIF. Arbitration lost. + * @arg CAN_FLAG_ERR_PASSIVE: Register bit ERRINT.EPIF. A change from error-passive to error-active or error-active to error-passive has occurred. + * @arg CAN_FLAG_ERR_PASSIVE_NODE: Register bit ERRINT.EPASS. The node is an error-passive node. + * @arg CAN_FLAG_REACH_WARN_LIMIT: Register bit ERRINT.EWARN. REC or TEC is greater than or equal to the LIMIT.EWL setting value. + */ +uint32_t CAN_GetStatusVal(const M4_CAN_TypeDef *CANx) +{ + uint32_t u32RCTRL; + uint32_t u32RTIE; + uint32_t u32RTIF; + uint32_t u32ERRINT; + uint32_t u32RetVal; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32RetVal = CANx->CFG_STAT; + u32RCTRL = CANx->RCTRL; + u32RCTRL &= CAN_FLAG_RB_OVF; + u32RTIE = CANx->RTIE; + u32RTIF = CANx->RTIF; + u32ERRINT = CANx->ERRINT; + + u32RetVal |= (u32RCTRL | (u32RTIE << 8U) | (u32RTIF << 16U) | (u32ERRINT << 24U)); + u32RetVal &= CAN_FLAG_ALL; + + return u32RetVal; +} + +/** + * @brief Get status(full or empty) of transmit buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value of status of transmit buffer. It's can be a value of @ref CAN_TB_Status + * @arg CAN_TB_STAT_EMPTY: TTCAN is disabled(TTEN == 0): STB is empty. + * TTCAN is disabled(TTEN == 1) and transmit buffer is specified by TBPTR and TTPTR(TTTBM == 1): + * PTB and STB are both empty. + * @arg CAN_TB_STAT_LESS_HALF: TTEN == 0: STB is not less than half full; + * TTEN == 1 && TTTBM == 1: PTB and STB are neither empty. + * @arg CAN_TB_STAT_MORE_HALF: TTEN == 0: STB is more than half full; + * TTEN == 1 && TTTBM == 1: reserved value. + * @arg CAN_TB_STAT_FULL TTEN == 0: STB is full; + * TTEN == 1 && TTTBM == 1: PTB and STB are both full. + */ +uint8_t CAN_GetTBFullStatus(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSSTAT)); +} + +/** + * @brief Get status(full or empty) of receive buffer. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value of status of receive buffer. It's can be a value of @ref CAN_RB_Status + * @arg CAN_RB_STAT_EMPTY: Receive buffer(RB) is empty. + * @arg CAN_RB_STAT_LESS_WARN_LIMIT: RB is not empty, but is less than almost full warning limit. + * @arg CAN_RB_STAT_MORE_WARN_LIMIT: RB is not full, but is more than or equal to almost full warning limit. + * @arg CAN_RB_STAT_FULL: RB is full. + */ +uint8_t CAN_GetRBFullStatus(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG8_BIT(CANx->TCTRL, CAN_RCTRL_RSTAT)); +} + +/** + * @brief Configures the specified CAN FD according to the specified parameters + * in the stc_can_fd_cfg_t type structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] pstcCfg Pointer to a stc_can_fd_cfg_t structure value that + * contains the configuration information for the CAN FD. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + * @note Call this function when CFG_STAT.RESET is 1. + */ +en_result_t CAN_FD_Config(M4_CAN_TypeDef *CANx, const stc_can_fd_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_FD_MODE(pstcCfg->u8CANFDMode)); + DDL_ASSERT(IS_CAN_TDC_CMD(pstcCfg->u8TDCCmd)); + DDL_ASSERT(IS_CAN_FD_SSP(pstcCfg->u8TDCSSP)); + + DDL_ASSERT(IS_CAN_FBT_SEG1(pstcCfg->stcFBT.u32SEG1)); + DDL_ASSERT(IS_CAN_FBT_SEG2(pstcCfg->stcFBT.u32SEG2)); + DDL_ASSERT(IS_CAN_FBT_SJW(pstcCfg->stcFBT.u32SJW)); + DDL_ASSERT(IS_CAN_FBT_PRESC(pstcCfg->stcFBT.u32Prescaler)); + + /* Specifies CAN FD ISO mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_FD_ISO, pstcCfg->u8CANFDMode); + + /* + * Configures fast bit time. + * Restrictions: u32SEG1 >= u32SEG2 + 1, u32SEG2 >= u32SJW. + * TQ = u32Prescaler / CANClock. + * Fast bit time = (u32SEG1 + u32SEG2) * TQ. + */ + WRITE_REG32(CANx->FBT, ((pstcCfg->stcFBT.u32SEG1 - 2U) | \ + ((pstcCfg->stcFBT.u32SEG2 - 1U) << CAN_FBT_F_SEG_2_POS) | \ + ((pstcCfg->stcFBT.u32SJW - 1U) << CAN_FBT_F_SJW_POS) | \ + ((pstcCfg->stcFBT.u32Prescaler - 1U) << CAN_FBT_F_PRESC_POS))); + + /* Specifies the secondary sample point. Number of TQ. */ + MODIFY_REG8(CANx->TDC, CAN_TDC_SSPOFF, pstcCfg->u8TDCSSP); + + /* Enable or disable TDC. */ + MODIFY_REG8(CANx->TDC, CAN_TDC_TDCEN, pstcCfg->u8TDCCmd); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for the CAN FD configuration structure. + * Based on 40MHz CAN clock, TQ clock is CAN clock divided by 1. \ + * Bit rate 2Mbps, 1 bit time is 20TQs, primary sample point is 80%, \ + * secondary sample point is 80%. + * @param [in] pstcCfg Pointer to a stc_can_fd_cfg_t structure value that + * contains the configuration information for the CAN FD. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t CAN_FD_StructInit(stc_can_fd_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + /* + * u8TDCCmd: Enalbe(CAN_FD_TDC_ENABLE) or disable(CAN_FD_TDC_DISABLE) transmitter delay compensation. + * u8TDCSSP: The position(TQs) of secondary sample point. + * + * Primary sample point: u32SEG1 / (u32SEG1 + u32SEG2) = 80% + * Secondary sample point: u8TDCSSP / (u32SEG1 + u32SEG2) = 80% + * + * u32SEG1: TQs of segment 1. Contains synchronization segment, \ + * propagation time segment and phase buffer segment 1. + * u32SEG2: TQs of segment 2. Phase buffer segment 2. + * u32SJW: TQs of synchronization jump width. + * u32Prescaler: Range [1, 256]. + */ + pstcCfg->u8CANFDMode = CAN_FD_MODE_BOSCH; + pstcCfg->u8TDCCmd = CAN_FD_TDC_ENABLE; + pstcCfg->u8TDCSSP = 16U; + pstcCfg->stcFBT.u32SEG1 = 1U + 15U; + pstcCfg->stcFBT.u32SEG2 = 4U; + pstcCfg->stcFBT.u32SJW = 4U; + pstcCfg->stcFBT.u32Prescaler = 1U; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable CAN FD. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable CAN FD. + * @arg Disable: Disable CAN FD. + * @retval None + */ +void CAN_FD_Cmd(const M4_CAN_TypeDef *CANx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + uint32_t u32BitPos = 0U; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (CANx == M4_CAN2) + { + u32BitPos = 1U; + } + u32Addr = (uint32_t)&M4_PERIC->CAN_SYCTLREG; + BIT_BAND(u32Addr, u32BitPos) = (uint32_t)enNewState; +} + +/** + * @brief Set a default value for the CAN TTC(time-triggered communication) configuration structure. + * @param [in] pstcCfg Pointer to a stc_can_ttc_cfg_t structure value that + * contains the configuration information for the CAN TTC. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t CAN_TTC_StructInit(stc_can_ttc_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + pstcCfg->u8TransBufMode = CAN_TTC_TB_MODE_PTR; + pstcCfg->u8NTUPrescaler = CAN_TTC_NTU_PRESC_1; + pstcCfg->u32RefMsgIDE = 0U; + pstcCfg->u32RefMsgID = 0x0U; + pstcCfg->u16TrigType = CAN_TTC_TRIG_SSHOT_TRANS_TRIG; + pstcCfg->u16TxEnWindow = 16U; + pstcCfg->u16TxTrigTime = 0xFFFFU; + pstcCfg->u16WatchTrigTime = 0xFFFFU; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Configures the specified CAN TTC(time-triggered communication) according to the specified parameters + * in the stc_can_ttc_cfg_t type structure. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] pstcCfg Pointer to a stc_can_ttc_cfg_t structure value that + * contains the configuration information for the CAN TTC. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t CAN_TTC_Config(M4_CAN_TypeDef *CANx, const stc_can_ttc_cfg_t *pstcCfg) +{ + uint32_t u32RefMsgID; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TTC_TB_MODE(pstcCfg->u8TransBufMode)); + DDL_ASSERT(IS_CAN_TTC_NTU_PRESC(pstcCfg->u8NTUPrescaler)); + DDL_ASSERT(IS_CAN_IDE(pstcCfg->u32RefMsgIDE)); + DDL_ASSERT(IS_CAN_TTC_TRIG_TYPE(pstcCfg->u16TrigType)); + DDL_ASSERT(IS_CAN_TTC_TX_EN_WINDOW(pstcCfg->u16TxEnWindow)); + + u32RefMsgID = pstcCfg->u32RefMsgID & ((uint32_t)(~CAN_REF_MSG_REF_IDE)); + + /* Specifies transmission buffer mode. */ + MODIFY_REG8(CANx->TCTRL, CAN_TCTRL_TTTBM, pstcCfg->u8TransBufMode); + /* Specifies Tx_Enable window and trigger type. */ + WRITE_REG16(CANx->TRG_CFG, ((((uint32_t)pstcCfg->u16TxEnWindow-1U) << CAN_TRG_CFG_TEW_POS) | pstcCfg->u16TrigType)); + /* Specifies ID of reference message and its extension bit. */ + WRITE_REG32(CANx->REF_MSG, (((pstcCfg->u32RefMsgIDE << CAN_REF_MSG_REF_IDE_POS) | u32RefMsgID))); + /* Specifies transmission trigger time. */ + WRITE_REG16(CANx->TT_TRIG, pstcCfg->u16TxTrigTime); + /* Specifies watch trigger time. */ + WRITE_REG16(CANx->TT_WTRIG, pstcCfg->u16WatchTrigTime); + /* Specifies NTU prescaler. */ + WRITE_REG8(CANx->TTCFG, pstcCfg->u8NTUPrescaler); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable time-triggered communication(TTC) of the specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable TTC. + * @arg Disable: Disable TTC. + * @retval None + * @note Call this function when CFG_STAT.RESET is 0. + */ +void CAN_TTC_Cmd(M4_CAN_TypeDef *CANx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + u32Addr = (uint32_t)&CANx->TTCFG; + BIT_BAND(u32Addr, CAN_TTCFG_TTEN_POS) = (uint32_t)enNewState; +} + +/** + * @brief Specifies transmission buffer slot(TBS) which is going to be filled. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8SlotPtr Transmit-trigger transmit buffer slot. + * This parameter can be a value of @ref CAN_TTC_TBS_Pointer + * @arg CAN_TTC_TBS_PTB: TBS pointer points to PTB. + * @arg CAN_TTC_TBS_STB1: TBS pointer points to STB slot 1. + * @arg CAN_TTC_TBS_STB2: TBS pointer points to STB slot 2. + * @arg CAN_TTC_TBS_STB3: TBS pointer points to STB slot 3. + * @retval None + */ +void CAN_TTC_SetTBSToBeFilled(M4_CAN_TypeDef *CANx, uint8_t u8SlotPtr) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TTC_TBS(u8SlotPtr)); + MODIFY_REG8(CANx->TBSLOT, CAN_TBSLOT_TBPTR, u8SlotPtr); +} + +/** + * @brief Marks the transmission buffer slot(TBS) as filled. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval None + */ +void CAN_TTC_SetTBSFilled(M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + SET_REG8_BIT(CANx->TBSLOT, CAN_TBSLOT_TBF); +} + +/** + * @brief Specifies time-triggered communication(TTC) timer prescaler. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8NTUPrescaler Time-triggered communication timer prescaler. + * This parameter can be a value of @ref CAN_TTC_NTU_Prescaler + * @arg CAN_TTC_NTU_PRESC_1: NTU is SBT bit time * 1. + * @arg CAN_TTC_NTU_PRESC_2: NTU is SBT bit time * 2. + * @arg CAN_TTC_NTU_PRESC_4: NTU is SBT bit time * 4. + * @arg CAN_TTC_NTU_PRESC_8: NTU is SBT bit time * 8. + * @retval None + */ +void CAN_TTC_SetNTUPrescaler(M4_CAN_TypeDef *CANx, uint8_t u8NTUPrescaler) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TTC_NTU_PRESC(u8NTUPrescaler)); + MODIFY_REG8(CANx->TTCFG, CAN_TTCFG_T_PRESC, u8NTUPrescaler); +} + +/** + * @brief Enable or disable the specified interrupts of time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8IntType Interrupt type of TTC. + * This parameter can be values of @ref CAN_TTC_Interrupt_Type + * @arg CAN_TTC_INT_TTI: Time trigger interrupt. + * @arg CAN_TTC_INT_WTI: Watch trigger interrupt. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified interrupts. + * @arg Disable: Disable the specified interrupts. + * @retval None + */ +void CAN_TTC_IntCmd(M4_CAN_TypeDef *CANx, uint8_t u8IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8IntType &= CAN_TTC_INT_ALL; + if (enNewState == Enable) + { + SET_REG8_BIT(CANx->TTCFG, u8IntType); + } + else + { + CLEAR_REG8_BIT(CANx->TTCFG, u8IntType); + } +} + +/** + * @brief Get flag status of time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8Flag Status flag of TTC. + * This parameter can be values of @ref CAN_TTC_Status_Flag + * @arg CAN_TTC_FLAG_TTI: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_TEI: Trigger error interrupt flag. + * @arg CAN_TTC_FLAG_WTI: Watch trigger interrupt flag. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified flags is set. + * @arg Reset: None of the specified flags is reset. + */ +en_flag_status_t CAN_TTC_GetStatus(const M4_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + if (READ_REG8_BIT(CANx->TTCFG, (u8Flag & (uint8_t)CAN_TTC_FLAG_ALL)) != 0U) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief Clear flag status of time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8Flag Status flag of TTC. + * This parameter can be a value of @ref CAN_TTC_Status_Flag except CAN_TTC_FLAG_TEI. + * @arg CAN_TTC_FLAG_TTI: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_WTI: Watch trigger interrupt flag. + * @retval None + */ +void CAN_TTC_ClrStatus(M4_CAN_TypeDef *CANx, uint8_t u8Flag) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + SET_REG8_BIT(CANx->TTCFG, (u8Flag & CAN_TTC_FLAG_CLR_MSK)); +} + +/** + * @brief Get the value of status of TTC. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value that includes the flowing status flags. + * @arg CAN_TTC_FLAG_TTI: Time trigger interrupt flag. + * @arg CAN_TTC_FLAG_TEI: Trigger error interrupt flag. + * @arg CAN_TTC_FLAG_WTI: Watch trigger interrupt flag. + */ +uint8_t CAN_TTC_GetStatusVal(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return READ_REG8_BIT(CANx->TTCFG, CAN_TTC_FLAG_ALL); +} + +/** + * @brief Specifies reference message ID and IDE for time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u32ID Reference message ID. + * @retval None + */ +void CAN_TTC_SetRefMsgID(M4_CAN_TypeDef *CANx, uint32_t u32ID) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + u32ID &= (uint32_t)(~CAN_REF_MSG_REF_IDE); + MODIFY_REG32(CANx->REF_MSG, CAN_REF_MSG_REF_ID, u32ID); +} + +/** + * @brief Specifiy IDE of TTC(time-triggered communication) reference message. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u32IDE IDE bit. + * @arg 0: Standard ID. + * @arg 1: Extended ID. + * @retval None + */ +void CAN_TTC_SetRefMsgIDE(M4_CAN_TypeDef *CANx, uint32_t u32IDE) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_IDE(u32IDE)); + u32Addr = (uint32_t)&CANx->REF_MSG; + BIT_BAND(u32Addr, CAN_REF_MSG_REF_IDE_POS) = u32IDE; +} + +/** + * @brief Get reference message ID of time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint32_t value of reference message ID. + */ +uint32_t CAN_TTC_GetRefMsgID(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (READ_REG32_BIT(CANx->REF_MSG, CAN_REF_MSG_REF_ID)); +} + +/** + * @brief Get reference message ID extension bit of time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint32_t value of reference message IDE. + * @arg 0: Standard ID. + * @arg 1: Extended ID. + */ +uint32_t CAN_TTC_GetRefMsgIDE(const M4_CAN_TypeDef *CANx) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_CAN_UNIT(CANx)); + u32Addr = (uint32_t)&CANx->REF_MSG; + return BIT_BAND(u32Addr, CAN_REF_MSG_REF_IDE_POS); +} + +/** + * @brief Specifies transmit-trigger transmit buffer slot(TBS) for time-triggered communication(TTC) of specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u8TBSlotPtr Transmit-trigger transmit buffer slot. + * This parameter can be a value of @ref CAN_TTC_TBS_Pointer + * @arg CAN_TTC_TBS_PTB: TBS pointer points to PTB. + * @arg CAN_TTC_TBS_STB_S1: TBS pointer points to STB slot 1. + * @arg CAN_TTC_TBS_STB_S2: TBS pointer points to STB slot 2. + * @arg CAN_TTC_TBS_STB_S3: TBS pointer points to STB slot 3. + * @retval None + */ +void CAN_TTC_SetTxTrigTBS(M4_CAN_TypeDef *CANx, uint8_t u8TBSlotPtr) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TTC_TBS(u8TBSlotPtr)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR, u8TBSlotPtr); +} + +/** + * @brief Get transmit-trigger transmit buffer slot(TBS) of specified CAN unit's time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint8_t type value of transmit buffer slot pointer. It is can be a value of @ref CAN_TTC_TBS_Pointer + * @arg CAN_TTC_TBS_PTB: TBS pointer points to PTB. + * @arg CAN_TTC_TBS_STB1: TBS pointer points to STB slot 1. + * @arg CAN_TTC_TBS_STB2: TBS pointer points to STB slot 2. + * @arg CAN_TTC_TBS_STB3: TBS pointer points to STB slot 3. + */ +uint8_t CAN_TTC_GetTxTrigTBS(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (uint8_t)(READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR)); +} + +/** + * @brief Specifies trigger type for time-triggered communication(TTC) of specified CAN unit. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u16TrigType Time-triggered communication trigger type. + * This parameter can be a value of @ref CAN_TTC_Trigger_Type + * @arg CAN_TTC_TRIG_IMMED_TRIG: Immediate trigger for immediate transmission. + * @arg CAN_TTC_TRIG_TIME_TRIG: Time trigger for receive triggers. + * @arg CAN_TTC_TRIG_SSHOT_TRANS_TRIG: Single shot transmit trigger for exclusive time windows. + * @arg CAN_TTC_TRIG_TRANS_START_TRIG: Transmit start trigger for merged arbitrating time windows. + * @arg CAN_TTC_TRIG_TRANS_STOP_TRIG: Transmit stop trigger for merged arbitrating time windows. + * @retval None + */ +void CAN_TTC_SetTrigType(M4_CAN_TypeDef *CANx, uint16_t u16TrigType) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TTC_TRIG_TYPE(u16TrigType)); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE, u16TrigType); +} + +/** + * @brief Get trigger type of specified CAN unit's time-triggered communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint16_t type value of TTC trigger type. + * @arg CAN_TTC_TRIG_IMMED_TRIG: Immediate trigger for immediate transmission. + * @arg CAN_TTC_TRIG_TIME_TRIG: Time trigger for receive triggers. + * @arg CAN_TTC_TRIG_SSHOT_TRANS_TRIG: Single shot transmit trigger for exclusive time windows. + * @arg CAN_TTC_TRIG_TRANS_START_TRIG: Transmit start trigger for merged arbitrating time windows. + * @arg CAN_TTC_TRIG_TRANS_STOP_TRIG: Transmit stop trigger for merged arbitrating time windows. + */ +uint16_t CAN_TTC_GetTrigType(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return READ_REG16_BIT(CANx->TRG_CFG, CAN_TRG_CFG_TTYPE); +} + +/** + * @brief Specifies transmission enable window for single shot transmit trigger. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u16TxEnableWindow Number of NTU. Time period within which the transmission of a message may be started. + * @retval None + */ +void CAN_TTC_SetTxEnableWindow(M4_CAN_TypeDef *CANx, uint16_t u16TxEnableWindow) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TTC_TX_EN_WINDOW(u16TxEnableWindow)); + u16TxEnableWindow -= 1U; + u16TxEnableWindow = (uint16_t)((uint32_t)u16TxEnableWindow << CAN_TRG_CFG_TEW_POS); + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TEW, u16TxEnableWindow); +} + +/** + * @brief Get transmit enable window of single shot transmit trigger. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint16_t type value of Tx_Enable window. + */ +uint16_t CAN_TTC_GetTxEnableWindow(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return ((CANx->TRG_CFG >> CAN_TRG_CFG_TEW_POS) + 1U); +} + +/** + * @brief Set transmission trigger time for timer-trigger communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u16TxTrigTime Transmission trigger time. Number of NTU. + * @retval None + */ +void CAN_TTC_SetTxTrigTime(M4_CAN_TypeDef *CANx, uint16_t u16TxTrigTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_TRIG, u16TxTrigTime); +} + +/** + * @brief Get watch trigger time of timer-trigger communication(TTC). + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint16_t type value of cycle time. + */ +uint16_t CAN_TTC_GetTxTrigTime(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (CANx->TT_TRIG); +} + +/** + * @brief Set cycle time for timer-trigger communication(TTC) watch-trigger. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] u16WatchTrigTime Watch trigger time. Number of NTU. + * @retval None + */ +void CAN_TTC_SetWatchTrigTime(M4_CAN_TypeDef *CANx, uint16_t u16WatchTrigTime) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + WRITE_REG16(CANx->TT_WTRIG, u16WatchTrigTime); +} + +/** + * @brief Get cycle time of timer-trigger communication(TTC) watch-trigger. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @retval An uint16_t type value of cycle time. + */ +uint16_t CAN_TTC_GetWatchTrigTime(const M4_CAN_TypeDef *CANx) +{ + DDL_ASSERT(IS_CAN_UNIT(CANx)); + return (CANx->TT_WTRIG); +} + +/** + * @brief CAN bus transmits data. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] pstcTx Points to a stc_can_tx_t structure type data which stores the frames to be transmitted. + * @param [in] u8TxBufType CAN transmit buffer type. + * This parameter can be a value of @ref CAN_Transmit_Buffer_Type + * @arg CAN_BUF_PTB: Primary transmit buffer. + * @arg CAN_BUF_STB: Secondary transmit buffer. + * @param [in] u8STBTxCtrl STB transmission control. If transmit via PTB, set u8STBTxCtrl to 0. + * This parameter can be a value of @ref CAN_STB_Trans_Control + * @arg CAN_STB_TRANS_ALL: Transmit all of STB slots. + * @arg CAN_STB_TRANS_ONE: Transmit one STB slot. + * @param [in] u32Timeout Timeout value. Set it as zero for transmit in interrupt-mode. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcTx == NULL. + * @arg ErrorBufferFull: The target transmit buffer is full. + * @arg ErrorOperationInProgress: The target transmit buffer is being transmitted. + * @arg ErrorAddressAlignment: Data address is not 4-byte aligned. + * @arg ErrorTimeout: Transmit timeout. + * @arg Error: CAN bus transmission error. + */ +en_result_t CAN_TransData(M4_CAN_TypeDef *CANx, const stc_can_tx_t *pstcTx, + uint8_t u8TxBufType, uint8_t u8STBTxCtrl, uint32_t u32Timeout) +{ + uint32_t i; + uint8_t u8DataSize; + uint8_t u8WordLen; + uint32_t u32Addr; + uint32_t u32TimeCnt; + uint32_t u32SrcDataAddr; + uint32_t u32TBAddr; + uint8_t au8TxEn[2U][2U] = {{CAN_TCMD_TPE, CAN_TCMD_TPE}, \ + {CAN_TCMD_TSALL, CAN_TCMD_TSONE}}; + uint8_t au8Check[2U] = {CAN_RTIF_TPIF, CAN_RTIF_TSIF}; + uint8_t au8DLC2Size[2U][16U] = + { + {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8U, 8U, 8U, 8U, 8U, 8U, 8U}, + {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U}, + }; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcTx != NULL) + { + DDL_ASSERT(IS_CAN_UNIT(CANx)); + DDL_ASSERT(IS_CAN_TB_TYPE(u8TxBufType)); + DDL_ASSERT(IS_CAN_STB_TX_CTRL(u8STBTxCtrl)); + + u32SrcDataAddr = (uint32_t)pstcTx->pu8Data; + + if ((READ_REG8_BIT(CANx->TCTRL, CAN_TB_STAT_FULL) == CAN_TB_STAT_FULL) && \ + (u8TxBufType == CAN_BUF_STB)) + { + /* All STBs are full. */ + enRet = ErrorBufferFull; + } + else if ((READ_REG8_BIT(CANx->TCMD, CAN_TCMD_TPE) != 0U) && \ + (u8TxBufType == CAN_BUF_PTB)) + { + /* PTB is being transmitted. */ + enRet = ErrorOperationInProgress; + } + else if ((u32SrcDataAddr & 0x03UL) != 0U) + { + enRet = ErrorAddressAlignment; + } + else + { + u8DataSize = au8DLC2Size[pstcTx->FDF][pstcTx->DLC]; + u8WordLen = u8DataSize / 4U; + if ((u8DataSize % 4U) != 0U) + { + u8WordLen += 1U; + } + + /* Specifies the transmit buffer, PTB or STB. */ + u32Addr = (uint32_t)&CANx->TCMD; + BIT_BAND(u32Addr, CAN_TCMD_TBSEL_POS) = (uint32_t)u8TxBufType; + + u32TBAddr = (uint32_t)&CANx->TBUF; + RW_MEM32(u32TBAddr) = pstcTx->u32ID; + RW_MEM32(u32TBAddr + 4U) = pstcTx->u32Ctrl; + + i = 0U; + u32TBAddr += 8U; + while (i < u8WordLen) + { + RW_MEM32(u32TBAddr + i * 4U) = *(uint32_t *)u32SrcDataAddr; + u32SrcDataAddr += 4U; + i++; + } + + if (u8TxBufType == CAN_BUF_STB) + { + /* After writes the data in transmit buffer(TB), sets the TSNEXT bit to indicate that the current \ + STB slot has been filled, so that the hardware will point TB to the next STB slot. */ + SET_REG8_BIT(CANx->TCTRL, CAN_TCTRL_TSNEXT); + } + + /* Enable transmission. */ + SET_REG8_BIT(CANx->TCMD, au8TxEn[u8TxBufType][u8STBTxCtrl]); + + if (u32Timeout == 0U) + { + enRet = Ok; + } + else + { + /* Check transmission. */ + u32TimeCnt = u32Timeout * (HCLK_VALUE / 10U / 1000U); + enRet = ErrorTimeout; + while (u32TimeCnt-- != 0U) + { + if ((CAN_GetStatusVal(CANx) & CAN_FLAG_TX_ERR_MSK) != 0U) + { + enRet = Error; + } + else if (READ_REG8_BIT(CANx->RTIF, au8Check[u8TxBufType]) != 0U) + { + /* Clear the transmit-OK status flag. */ + CANx->RTIF |= au8Check[u8TxBufType]; + enRet = Ok; + } + else + { + /* rsvd */ + } + if (enRet != ErrorTimeout) + { + break; + } + } + } + } + } + + return enRet; +} + +/** + * @brief TTCAN transmits data. For single shot transmit trigger. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [in] pstcTx Points to a stc_can_tx_t structure type data which stores the frames to be transmitted. + * @param [in] u8TBSlot Transmit buffer pointer. + * This parameter can be a value of @ref CAN_TTC_TBS_Pointer + * @arg CAN_TTC_TBS_PTB: Point to PTB. + * @arg CAN_TTC_TBS_STB1: Point to STB slot 1. + * @arg CAN_TTC_TBS_STB2: Point to STB slot 2. + * @arg CAN_TTC_TBS_STB3: Point to STB slot 3. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcTx == NULL. + * @arg ErrorBufferFull: The target transmit buffer is full. + * @arg ErrorAddressAlignment: Data address is not 4-byte aligned. + */ +en_result_t CAN_TTC_TransData(M4_CAN_TypeDef *CANx, const stc_can_tx_t *pstcTx, uint8_t u8TBSlot) +{ + uint32_t i; + uint8_t u8Tmp; + uint8_t u8DataSize; + uint8_t u8WordLen; + uint32_t u32SrcDataAddr; + uint32_t u32TBAddr; + uint8_t au8DLC2Size[2U][16U] = + { + {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8U, 8U, 8U, 8U, 8U, 8U, 8U}, + {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U}, + }; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcTx != NULL) + { + DDL_ASSERT(IS_CAN_UNIT(CANx)); + + u32SrcDataAddr = (uint32_t)pstcTx->pu8Data; + u8Tmp = CANx->TBSLOT; + WRITE_REG8(CANx->TBSLOT, u8TBSlot); + if (READ_REG8_BIT(CANx->TCTRL, CAN_TB_STAT_FULL) == CAN_TB_STAT_FULL) + { + enRet = ErrorBufferFull; + } + else if (READ_REG8_BIT(CANx->RTIE, CAN_RTIE_TSFF) != 0U) + { + WRITE_REG8(CANx->TBSLOT, CAN_TBSLOT_TBF|u8Tmp); + WRITE_REG16(CANx->TT_TRIG, CANx->TT_TRIG); + enRet = ErrorBufferFull; + } + else if ((u32SrcDataAddr & 0x03UL) != 0U) + { + enRet = ErrorAddressAlignment; + } + else + { + u8DataSize = au8DLC2Size[pstcTx->FDF][pstcTx->DLC]; + u8WordLen = u8DataSize / 4U; + if ((u8DataSize % 4U) != 0U) + { + u8WordLen += 1U; + } + + u32TBAddr = (uint32_t)&CANx->TBUF; + MODIFY_REG16(CANx->TRG_CFG, CAN_TRG_CFG_TTPTR, u8TBSlot); + + RW_MEM32(u32TBAddr) = pstcTx->u32ID; + RW_MEM32(u32TBAddr + 4U) = pstcTx->u32Ctrl; + + i = 0U; + u32TBAddr += 8U; + while (i < u8WordLen) + { + RW_MEM32(u32TBAddr + i * 4U) = *(uint32_t *)u32SrcDataAddr; + u32SrcDataAddr += 4U; + i++; + } + /* Set buffer as filled. */ + SET_REG8_BIT(CANx->TBSLOT, CAN_TBSLOT_TBF); + + /* Write MSB of TT_TRIG to transmit. */ + WRITE_REG16(CANx->TT_TRIG, CANx->TT_TRIG); + + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief CAN bus receives data. + * @param [in] CANx Pointer to CAN instance register base. + * This parameter can be a value of the following: + * @arg M4_CAN1: CAN unit 1 instance register base. + * @arg M4_CAN2: CAN unit 2 instance register base. + * @param [out] pstcRx Points to a stc_can_rx_t structure type array which is used to \ + * store the received frames. + * @param [out] pu8RxFrameCnt Address to store the number of frames received. + * If you do not need it, set it as NULL.\ + * @param [in] u8RxFrameBufLength The length of the buffer which is used to store the received frames. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: -pstcRx == NULL. + * -u8RxFrameBufLength == 0U. + */ +en_result_t CAN_ReceiveData(M4_CAN_TypeDef *CANx, stc_can_rx_t pstcRx[], uint8_t *pu8RxFrameCnt, uint8_t u8RxFrameBufLength) +{ + uint32_t i; + uint8_t u8DataSize; + uint8_t u8WordLen; + uint8_t u8RxFrameCnt = 0U; + uint32_t u32DestDataAddr; + uint32_t u32RBAddr; + en_result_t enRet; + uint8_t au8DLC2Size[2U][16U] = + { + {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 8U, 8U, 8U, 8U, 8U, 8U, 8U}, + {0U, 1U, 2U, 3U, 4U, 5U, 6U, 7U, 8U, 12U, 16U, 20U, 24U, 32U, 48U, 64U}, + }; + + if ((pstcRx == NULL) || (u8RxFrameBufLength == 0U)) + { + enRet = ErrorInvalidParameter; + } + else + { + enRet = Ok; + while (READ_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RSTAT) != CAN_RB_STAT_EMPTY) + { + u32RBAddr = (uint32_t)&CANx->RBUF; + pstcRx[u8RxFrameCnt].u32ID = RW_MEM32(u32RBAddr); + pstcRx[u8RxFrameCnt].u32Ctrl = RW_MEM32(u32RBAddr + 4U); + + u8DataSize = au8DLC2Size[pstcRx[u8RxFrameCnt].FDF][pstcRx[u8RxFrameCnt].DLC]; + u8WordLen = u8DataSize / 4U; + if ((u8DataSize % 4U) != 0U) + { + u8WordLen += 1U; + } + + u32DestDataAddr = (uint32_t)pstcRx[u8RxFrameCnt].pu8Data; + if (!IS_ADDRESS_ALIGN_WORD(u32DestDataAddr)) + { + enRet = ErrorAddressAlignment; + break; + } + i = 0U; + u32RBAddr += 8U; + while (i < u8WordLen) + { + *(uint32_t *)u32DestDataAddr = RW_MEM32(u32RBAddr + i * 4U); + u32DestDataAddr += 4U; + i++; + } + + /* Set RB to point to the next RB slot. */ + SET_REG8_BIT(CANx->RCTRL, CAN_RCTRL_RREL); + u8RxFrameCnt++; + if (u8RxFrameCnt >= u8RxFrameBufLength) + { + break; + } + } + + if (pu8RxFrameCnt != NULL) + { + *pu8RxFrameCnt = u8RxFrameCnt; + } + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_CAN_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_clk.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_clk.c new file mode 100644 index 0000000000000000000000000000000000000000..79efb51eb983a92d29dc94f1f989ebb80414d680 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_clk.c @@ -0,0 +1,1990 @@ +/** + ******************************************************************************* + * @file hc32f4a0_clk.c + * @brief This file provides firmware functions to manage the Clock(CLK). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-07-03 Zhangxl 1. Tpyo + 2. API CLK_SetSysClkSrc() refine + 2020-08-19 Zhangxl 1. Modify formula of PLL clock get API + 2. Zero structure for CLK_PLLxStrucInit() + 2020-08-25 Zhangxl Modify for MISRAC2012-10.1, 10.3 + 2020-10-13 Chengy Add VBAT init at head of CLK_Xtal32Init() + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_clk.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_CLK CLK + * @brief Clock Driver Library + * @{ + */ + +#if (DDL_CLK_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CLK_Local_Macros CLK Local Macros + * @brief Be able to modify TIMEOUT according to board condition. + * @{ + */ +#define CLK_XTAL_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_XTAL32_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_HRC_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_MRC_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_LRC_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_PLLH_TIMEOUT ((uint32_t)0x1000UL) +#define CLK_PLLA_TIMEOUT ((uint32_t)0x1000UL) + +/** + * @defgroup CLK_Check_Parameters_Validity CLK Check Parameters Validity + * @{ + */ + +/* Check CLK register lock status. */ +#define IS_CLK_UNLOCKED() ((M4_PWC->FPRC & PWC_FPRC_FPRCB0) == PWC_FPRC_FPRCB0) + +/* Check CLK register lock status. */ +#define IS_CLK_SEL_UNLOCKED() ((M4_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/*! Parameter valid check for XTAL state */ +#define IS_CLK_XTAL_STATE(sta) \ +( ((sta) == CLK_XTAL_OFF) || \ + ((sta) == CLK_XTAL_ON)) + +/*! Parameter valid check for XTAL mode */ +#define IS_CLK_XTAL_MODE(MODE) \ +( ((MODE) == CLK_XTALMODE_OSC) || \ + ((MODE) == CLK_XTALMODE_EXCLK)) + +/*! Parameter valid check for XTAL driver ability mode */ +#define IS_CLK_XTALDRV_MODE(drv) \ +( ((drv) == CLK_XTALDRV_HIGH) || \ + ((drv) == CLK_XTALDRV_MID) || \ + ((drv) == CLK_XTALDRV_LOW) || \ + ((drv) == CLK_XTALDRV_ULOW)) + +/*! Parameter valid check for XTAL stable time selection */ +#define IS_CLK_XTALSTB_SEL(stb) \ +( ((stb) == CLK_XTALSTB_133US) || \ + ((stb) == CLK_XTALSTB_255US) || \ + ((stb) == CLK_XTALSTB_499US) || \ + ((stb) == CLK_XTALSTB_988US) || \ + ((stb) == CLK_XTALSTB_2MS) || \ + ((stb) == CLK_XTALSTB_4MS) || \ + ((stb) == CLK_XTALSTB_8MS) || \ + ((stb) == CLK_XTALSTB_16MS) || \ + ((stb) == CLK_XTALSTB_31MS)) + +/*! Parameter valid check for XTALSTD state */ +#define IS_CLK_XTALSTD_STATE(sta) \ +( ((sta) == CLK_XTALSTD_OFF) || \ + ((sta) == CLK_XTALSTD_ON)) + +/*! Parameter valid check for XTALSTD mode */ +#define IS_CLK_XTALSTD_MODE(mode) \ +( ((mode) == CLK_XTALSTD_MODE_RST) || \ + ((mode) == CLK_XTALSTD_MODE_INT)) + +/*! Parameter valid check for XTALSTD interrupt state */ +#define IS_CLK_XTALSTD_INT_STATE(sta) \ +( ((sta) == CLK_XTALSTD_INT_OFF) || \ + ((sta) == CLK_XTALSTD_INT_ON)) + +/*! Parameter valid check for XTALSTD reset state */ +#define IS_CLK_XTALSTD_RST_STATE(sta) \ +( ((sta) == CLK_XTALSTD_RST_OFF) || \ + ((sta) == CLK_XTALSTD_RST_ON)) + +/*! Parameter valid check for PLLA state */ +#define IS_CLK_PLLA_STATE(sta) \ +( ((sta) == CLK_PLLA_OFF) || \ + ((sta) == CLK_PLLA_ON)) + +/*! Parameter valid check for PLLH state */ +#define IS_CLK_PLLH_STATE(sta) \ +( ((sta) == CLK_PLLH_OFF) || \ + ((sta) == CLK_PLLH_ON)) + +/*! Parameter valid check for XTAL32 state */ +#define IS_CLK_XTAL32_STATE(sta) \ +( ((sta) == CLK_XTAL32_OFF) || \ + ((sta) == CLK_XTAL32_ON)) + +/*! Parameter valid check for XTAL32 driver ability mode */ +#define IS_CLK_XTAL32DRV_MODE(mode) \ +( ((mode) == CLK_XTAL32DRV_MID) || \ + ((mode) == CLK_XTAL32DRV_HIGH)) + +/*! Parameter valid check for XTAL32 filtering selection */ +#define IS_CLK_XTAL32_FILT_SEL(sel) \ +( ((sel) == CLK_XTAL32NF_FULL) || \ + ((sel) == CLK_XTAL32NF_PART) || \ + ((sel) == CLK_XTAL32NF_NONE)) + +/*! Parameter valid check for system clock source */ +#define IS_CLK_SYSCLK_SRC(src) \ +( ((src) == CLK_SYSCLKSOURCE_HRC) || \ + ((src) == CLK_SYSCLKSOURCE_MRC) || \ + ((src) == CLK_SYSCLKSOURCE_LRC) || \ + ((src) == CLK_SYSCLKSOURCE_XTAL) || \ + ((src) == CLK_SYSCLKSOURCE_XTAL32) || \ + ((src) == CLK_SYSCLKSOURCE_PLLH)) + +/*! Parameter validity check for PLL input source */ +#define IS_CLK_PLL_SRC(src) \ +( ((src) == CLK_PLLSRC_XTAL) || \ + ((src) == CLK_PLLSRC_HRC)) + +/*! Parameter validity check for PLLH frequency range */ +#define IS_CLK_PLLH_FREQ(freq) \ +( (CLK_PLLH_FREQ_MIN <= (freq)) && \ + (CLK_PLLH_FREQ_MAX >= (freq))) + +/*! Parameter validity check for PLLH M divide */ +#define IS_CLK_PLLHM_DIV(m) \ +( (CLK_PLLHM_DIV_MIN <= (m)) && \ + (CLK_PLLHM_DIV_MAX >= (m))) + +/*! Parameter validity check for PLLH N multi- */ +#define IS_CLK_PLLHN_MULTI(n) \ +( (CLK_PLLHN_MULTI_MIN <= (n)) && \ + (CLK_PLLHN_MULTI_MAX >= (n))) + +/*! Parameter validity check for PLLH R divide */ +#define IS_CLK_PLLHR_DIV(r) \ +( (CLK_PLLHR_DIV_MIN <= (r)) && \ + (CLK_PLLHR_DIV_MAX >= (r))) + +/*! Parameter validity check for PLLH Q divede */ +#define IS_CLK_PLLHQ_DIV(q) \ +( (CLK_PLLHQ_DIV_MIN <= (q)) && \ + (CLK_PLLHQ_DIV_MAX >= (q))) + +/*! Parameter validity check for PLLH P divide */ +#define IS_CLK_PLLHP_DIV(p) \ +( (CLK_PLLHP_DIV_MIN <= (p)) && \ + (CLK_PLLHP_DIV_MAX >= (p))) + +/*! Parameter validity check for PLLH_input freq./PLLM(vco_in) */ +#define IS_CLK_PLLH_VCO_IN(vco_in) \ +( (CLK_PLLH_VCO_IN_MIN <= (vco_in)) && \ + (CLK_PLLH_VCO_IN_MAX >= (vco_in))) + +/*! Parameter validity check for PLLH vco_in*PLLN(vco_out) */ +#define IS_CLK_PLLH_VCO_OUT(vco_out) \ +( (CLK_PLLH_VCO_OUT_MIN <= (vco_out)) && \ + (CLK_PLLH_VCO_OUT_MAX >= (vco_out))) + +/*! Parameter validity check for PLLA frequency range */ +#define IS_CLK_PLLA_FREQ(freq) \ +( (CLK_PLLA_FREQ_MIN <= (freq)) && \ + (CLK_PLLA_FREQ_MAX >= (freq))) + +/*! Parameter validity check for PLLA M divide */ +#define IS_CLK_PLLAM_DIV(m) \ +( (CLK_PLLAM_DIV_MIN <= (m)) && \ + (CLK_PLLAM_DIV_MAX >= (m))) + +/*! Parameter validity check for PLLA N multi- */ +#define IS_CLK_PLLAN_MULTI(n) \ +( (CLK_PLLAN_MULTI_MIN <= (n)) && \ + (CLK_PLLAN_MULTI_MAX >= (n))) + +/*! Parameter validity check for PLLA R divide */ +#define IS_CLK_PLLAR_DIV(r) \ +( (CLK_PLLAR_DIV_MIN <= (r)) && \ + (CLK_PLLAR_DIV_MAX >= (r))) + +/*! Parameter validity check for PLLA Q divede */ +#define IS_CLK_PLLAQ_DIV(q) \ +( (CLK_PLLAQ_DIV_MIN <= (q)) && \ + (CLK_PLLAQ_DIV_MAX >= (q))) + +/*! Parameter validity check for PLLA P divide */ +#define IS_CLK_PLLAP_DIV(p) \ +( (CLK_PLLAP_DIV_MIN <= (p)) && \ + (CLK_PLLAP_DIV_MAX >= (p))) + +/*! Parameter validity check for PLLA_input freq./PLLM(vco_in) */ +#define IS_CLK_PLLA_VCO_IN(vco_in) \ +( (CLK_PLLA_VCO_IN_MIN <= (vco_in)) && \ + (CLK_PLLA_VCO_IN_MAX >= (vco_in))) + +/*! Parameter validity check for PLLA vco_in*PLLN(vco_out) */ +#define IS_CLK_PLLA_VCO_OUT(vco_out) \ +( (CLK_PLLA_VCO_OUT_MIN <= (vco_out)) && \ + (CLK_PLLA_VCO_OUT_MAX >= (vco_out))) + +/*! Parameter valid check for CLK stable flag. */ +#define IS_CLK_STB_FLAG(flag) \ +( ((flag) != 0x00U) && \ + (((flag) | CLK_STB_FLAG_MASK) == CLK_STB_FLAG_MASK)) + +/*! Parameter valid check for clock category */ +#define IS_CLK_CATE(cate) (((cate) & CLK_CATE_ALL) != (uint8_t)(0x00U)) + +/*! Parameter valid check for HCLK divider */ +#define IS_CLK_HCLK_DIV(div) \ +( ((div) == CLK_HCLK_DIV1) || \ + ((div) == CLK_HCLK_DIV2) || \ + ((div) == CLK_HCLK_DIV4) || \ + ((div) == CLK_HCLK_DIV8) || \ + ((div) == CLK_HCLK_DIV16) || \ + ((div) == CLK_HCLK_DIV32) || \ + ((div) == CLK_HCLK_DIV64)) + +/*! Parameter valid check for EXCLK divider */ +#define IS_CLK_EXCLK_DIV(div) \ +( ((div) == CLK_EXCLK_DIV1) || \ + ((div) == CLK_EXCLK_DIV2) || \ + ((div) == CLK_EXCLK_DIV4) || \ + ((div) == CLK_EXCLK_DIV8) || \ + ((div) == CLK_EXCLK_DIV16) || \ + ((div) == CLK_EXCLK_DIV32) || \ + ((div) == CLK_EXCLK_DIV64)) + +/*! Parameter valid check for PCLK0 divider */ +#define IS_CLK_PCLK0_DIV(div) \ +( ((div) == CLK_PCLK0_DIV1) || \ + ((div) == CLK_PCLK0_DIV2) || \ + ((div) == CLK_PCLK0_DIV4) || \ + ((div) == CLK_PCLK0_DIV8) || \ + ((div) == CLK_PCLK0_DIV16) || \ + ((div) == CLK_PCLK0_DIV32) || \ + ((div) == CLK_PCLK0_DIV64)) + +/*! Parameter valid check for PCLK1 divider */ +#define IS_CLK_PCLK1_DIV(div) \ +( ((div) == CLK_PCLK1_DIV1) || \ + ((div) == CLK_PCLK1_DIV2) || \ + ((div) == CLK_PCLK1_DIV4) || \ + ((div) == CLK_PCLK1_DIV8) || \ + ((div) == CLK_PCLK1_DIV16) || \ + ((div) == CLK_PCLK1_DIV32) || \ + ((div) == CLK_PCLK1_DIV64)) + +/*! Parameter valid check for PCLK2 divider */ +#define IS_CLK_PCLK2_DIV(div) \ +( ((div) == CLK_PCLK2_DIV1) || \ + ((div) == CLK_PCLK2_DIV2) || \ + ((div) == CLK_PCLK2_DIV4) || \ + ((div) == CLK_PCLK2_DIV8) || \ + ((div) == CLK_PCLK2_DIV16) || \ + ((div) == CLK_PCLK2_DIV32) || \ + ((div) == CLK_PCLK2_DIV64)) + +/*! Parameter valid check for PCLK3 divider */ +#define IS_CLK_PCLK3_DIV(div) \ +( ((div) == CLK_PCLK3_DIV1) || \ + ((div) == CLK_PCLK3_DIV2) || \ + ((div) == CLK_PCLK3_DIV4) || \ + ((div) == CLK_PCLK3_DIV8) || \ + ((div) == CLK_PCLK3_DIV16) || \ + ((div) == CLK_PCLK3_DIV32) || \ + ((div) == CLK_PCLK3_DIV64)) + +/*! Parameter valid check for PCLK4 divider */ +#define IS_CLK_PCLK4_DIV(div) \ +( ((div) == CLK_PCLK4_DIV1) || \ + ((div) == CLK_PCLK4_DIV2) || \ + ((div) == CLK_PCLK4_DIV4) || \ + ((div) == CLK_PCLK4_DIV8) || \ + ((div) == CLK_PCLK4_DIV16) || \ + ((div) == CLK_PCLK4_DIV32) || \ + ((div) == CLK_PCLK4_DIV64)) + +/*! Parameter valid check for USB clock source */ +#define IS_CLK_USB_CLK(src) \ +( ((src) == CLK_USB_CLK_MCLK_DIV2) || \ + ((src) == CLK_USB_CLK_MCLK_DIV3) || \ + ((src) == CLK_USB_CLK_MCLK_DIV4) || \ + ((src) == CLK_USB_CLK_MCLK_DIV5) || \ + ((src) == CLK_USB_CLK_MCLK_DIV6) || \ + ((src) == CLK_USB_CLK_MCLK_DIV7) || \ + ((src) == CLK_USB_CLK_MCLK_DIV8) || \ + ((src) == CLK_USB_CLK_PLLHQ) || \ + ((src) == CLK_USB_CLK_PLLHR) || \ + ((src) == CLK_USB_CLK_PLLAP) || \ + ((src) == CLK_USB_CLK_PLLAQ) || \ + ((src) == CLK_USB_CLK_PLLAR)) + +/*! Parameter valid check for CAN clock source */ +#define IS_CLK_CAN_CLK(src) \ +( ((src) == CLK_CAN1_CLK_MCLK_DIV2) || \ + ((src) == CLK_CAN1_CLK_MCLK_DIV3) || \ + ((src) == CLK_CAN1_CLK_MCLK_DIV4) || \ + ((src) == CLK_CAN1_CLK_MCLK_DIV5) || \ + ((src) == CLK_CAN1_CLK_MCLK_DIV6) || \ + ((src) == CLK_CAN1_CLK_MCLK_DIV7) || \ + ((src) == CLK_CAN1_CLK_MCLK_DIV8) || \ + ((src) == CLK_CAN1_CLK_PLLHQ) || \ + ((src) == CLK_CAN1_CLK_PLLHR) || \ + ((src) == CLK_CAN1_CLK_PLLAP) || \ + ((src) == CLK_CAN1_CLK_PLLAQ) || \ + ((src) == CLK_CAN1_CLK_PLLAR) || \ + ((src) == CLK_CAN1_CLK_XTAL) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV2) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV3) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV4) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV5) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV6) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV7) || \ + ((src) == CLK_CAN2_CLK_MCLK_DIV8) || \ + ((src) == CLK_CAN2_CLK_PLLHQ) || \ + ((src) == CLK_CAN2_CLK_PLLHR) || \ + ((src) == CLK_CAN2_CLK_PLLAP) || \ + ((src) == CLK_CAN2_CLK_PLLAQ) || \ + ((src) == CLK_CAN2_CLK_PLLAR) || \ + ((src) == CLK_CAN2_CLK_XTAL)) + +/*! Parameter valid check for CAN channel for clock source config */ +#define IS_CLK_CAN_CH(ch) (((ch) & CLK_CAN_CH_ALL) != (uint8_t)(0x00U)) + +/*! Parameter valid check for I2S clock source */ +#define IS_CLK_I2S_CLK(src) \ +( ((src) == CLK_I2S1_CLK_PCLK) || \ + ((src) == CLK_I2S1_CLK_PLLHQ) || \ + ((src) == CLK_I2S1_CLK_PLLHR) || \ + ((src) == CLK_I2S1_CLK_PLLAP) || \ + ((src) == CLK_I2S1_CLK_PLLAQ) || \ + ((src) == CLK_I2S1_CLK_PLLAR) || \ + ((src) == CLK_I2S2_CLK_PCLK) || \ + ((src) == CLK_I2S2_CLK_PLLHQ) || \ + ((src) == CLK_I2S2_CLK_PLLHR) || \ + ((src) == CLK_I2S2_CLK_PLLAP) || \ + ((src) == CLK_I2S2_CLK_PLLAQ) || \ + ((src) == CLK_I2S2_CLK_PLLAR) || \ + ((src) == CLK_I2S3_CLK_PCLK) || \ + ((src) == CLK_I2S3_CLK_PLLHQ) || \ + ((src) == CLK_I2S3_CLK_PLLHR) || \ + ((src) == CLK_I2S3_CLK_PLLAP) || \ + ((src) == CLK_I2S3_CLK_PLLAQ) || \ + ((src) == CLK_I2S3_CLK_PLLAR) || \ + ((src) == CLK_I2S4_CLK_PCLK) || \ + ((src) == CLK_I2S4_CLK_PLLHQ) || \ + ((src) == CLK_I2S4_CLK_PLLHR) || \ + ((src) == CLK_I2S4_CLK_PLLAP) || \ + ((src) == CLK_I2S4_CLK_PLLAQ) || \ + ((src) == CLK_I2S4_CLK_PLLAR)) + +/*! Parameter valid check for I2S channel for clock source config */ +#define IS_CLK_I2S_CH(ch) (((ch) & CLK_I2S_CH_ALL) != (uint8_t)(0x00U)) + +/*! Parameter valid check for PCLK2/PCLK4 source */ +#define IS_CLK_PERI_CLK(src) \ +( ((src) == CLK_PERI_CLK_PCLK) || \ + ((src) == CLK_PERI_CLK_PLLHQ) || \ + ((src) == CLK_PERI_CLK_PLLHR) || \ + ((src) == CLK_PERI_CLK_PLLAP) || \ + ((src) == CLK_PERI_CLK_PLLAQ) || \ + ((src) == CLK_PERI_CLK_PLLAR)) + +/*! Parameter valid check for TPIU clock divider */ +#define IS_CLK_TPIU_CLK_DIV(div) \ +( ((div) == CLK_TPIU_CLK_DIV1) || \ + ((div) == CLK_TPIU_CLK_DIV2) || \ + ((div) == CLK_TPIU_CLK_DIV4)) + +/*! Parameter valid check for CLK MCO clock source. */ +#define IS_CLK_MCOSOURCE(src) \ +( ((src) == CLK_MCOSOURCCE_HRC) || \ + ((src) == CLK_MCOSOURCCE_MRC) || \ + ((src) == CLK_MCOSOURCCE_LRC) || \ + ((src) == CLK_MCOSOURCCE_XTAL) || \ + ((src) == CLK_MCOSOURCCE_XTAL32) || \ + ((src) == CLK_MCOSOURCCE_PLLHP) || \ + ((src) == CLK_MCOSOURCCE_PLLHQ) || \ + ((src) == CLK_MCOSOURCCE_PLLAP) || \ + ((src) == CLK_MCOSOURCCE_PLLAQ) || \ + ((src) == CLK_MCOSOURCCE_PLLAR) || \ + ((src) == CLK_MCOSOURCCE_SYSCLK)) + +/*! Parameter valid check for CLK MCO clock divider. */ +#define IS_CLK_MCODIV(div) \ +( ((div) == CLK_MCO_DIV1) || \ + ((div) == CLK_MCO_DIV2) || \ + ((div) == CLK_MCO_DIV4) || \ + ((div) == CLK_MCO_DIV8) || \ + ((div) == CLK_MCO_DIV16) || \ + ((div) == CLK_MCO_DIV32) || \ + ((div) == CLK_MCO_DIV64) || \ + ((div) == CLK_MCO_DIV128)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CLK_Global_Functions CLK Global Functions + * @{ + */ +/** + * @brief Set PLLH/A source clock. + * @param [in] u32PllSrc PLLH/A source clock. + * @arg CLK_PLLSRC_XTAL + * @arg CLK_PLLSRC_HRC + * @retval None + */ +void CLK_SetPLLSrc(uint32_t u32PllSrc) +{ + DDL_ASSERT(IS_CLK_PLL_SRC(u32PllSrc)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG32(bM4_CMU->PLLHCFGR_b.PLLSRC, u32PllSrc); +} + +/** + * @brief Init PLLA initial structure with default value. + * @param [in] pstcPLLAInit specifies the Parameter of PLLA. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: NULL pointer + */ +en_result_t CLK_PLLAStrucInit(stc_clk_plla_init_t* pstcPLLAInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLAInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcPLLAInit->PLLCFGR = 0UL; + pstcPLLAInit->u8PLLState = CLK_PLLA_OFF; + pstcPLLAInit->PLLCFGR_f.PLLP = CLK_PLLAP_DFT; + pstcPLLAInit->PLLCFGR_f.PLLQ = CLK_PLLAQ_DFT; + pstcPLLAInit->PLLCFGR_f.PLLR = CLK_PLLAR_DFT; + pstcPLLAInit->PLLCFGR_f.PLLN = CLK_PLLAN_DFT; + pstcPLLAInit->PLLCFGR_f.PLLM = CLK_PLLAM_DFT; + } + return enRet; +} + +/** + * @brief PLLA Initialize. + * @param [in] pstcPLLAInit specifies the structure of PLLA initial config. + * @arg u8PLLState : The new state of the PLLA. + * @arg PLLCFGR : PLLA config. + * @retval en_result_t + * OK, PLLA initial successfully + * ErrorTimeout, PLLA initial timeout + * ErrorInvalidParameter, NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 1 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 240 ~ 480MHz. + * The PLLA frequency (VCOOUT/PLLAP_Q_R) is between 15 ~ 240MHz. + */ +en_result_t CLK_PLLAInit(const stc_clk_plla_init_t *pstcPLLAInit) +{ + en_result_t enRet; + +#ifdef __DEBUG + uint32_t vcoIn; + uint32_t vcoOut; +#endif + + if (NULL == pstcPLLAInit) + { + enRet = ErrorInvalidParameter; + } + else + { +#ifdef __DEBUG + DDL_ASSERT(IS_CLK_PLLAM_DIV(pstcPLLAInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLAN_MULTI(pstcPLLAInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLAR_DIV(pstcPLLAInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLLAQ_DIV(pstcPLLAInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLAP_DIV(pstcPLLAInit->PLLCFGR_f.PLLP + 1UL)); + + vcoIn = ((CLK_PLLSRC_XTAL == bM4_CMU->PLLHCFGR_b.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLAInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLAInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLLA_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLLA_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLLA_FREQ(vcoOut/(pstcPLLAInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLLA_FREQ(vcoOut/(pstcPLLAInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLLA_FREQ(vcoOut/(pstcPLLAInit->PLLCFGR_f.PLLP + 1UL))); +#endif + DDL_ASSERT(IS_CLK_PLLA_STATE(pstcPLLAInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG32(M4_CMU->PLLACFGR, pstcPLLAInit->PLLCFGR); + + if (CLK_PLLA_ON == pstcPLLAInit->u8PLLState) + { + enRet = CLK_PLLACmd(Enable); + } + else + { + enRet = CLK_PLLACmd(Disable); + } + } + return enRet; +} + +/** + * @brief Init PLLH initial structure with default value. + * @param [in] pstcPLLHInit specifies the Parameter of PLLH. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: NULL pointer + */ +en_result_t CLK_PLLHStrucInit(stc_clk_pllh_init_t* pstcPLLHInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcPLLHInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcPLLHInit->PLLCFGR = 0UL; + pstcPLLHInit->u8PLLState = CLK_PLLH_OFF; + pstcPLLHInit->PLLCFGR_f.PLLP = CLK_PLLHP_DFT; + pstcPLLHInit->PLLCFGR_f.PLLQ = CLK_PLLHQ_DFT; + pstcPLLHInit->PLLCFGR_f.PLLR = CLK_PLLHR_DFT; + pstcPLLHInit->PLLCFGR_f.PLLN = CLK_PLLHN_DFT; + pstcPLLHInit->PLLCFGR_f.PLLM = CLK_PLLHM_DFT; + pstcPLLHInit->PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL; + } + return enRet; +} + +/** + * @brief PLLH initialize. + * @param [in] pstcPLLHInit specifies the structure of PLLH initial config. + * @arg u8PLLState : The new state of the PLLH. + * @arg PLLCFGR : PLLH config. + * @retval en_result_t + * OK, PLLH initial successfully + * ErrorTimeout, PLLH initial timeout + * ErrorNotReady, PLLH is the source clock, CANNOT stop it. + * ErrorInvalidParameter, NULL pointer + * @note The pll_input/PLLM (VCOIN) must between 8 ~ 24MHz. + * The VCOIN*PLLN (VCOOUT) is between 600 ~ 1200MHz. + * The PLLH frequency (VCOOUT/PLLHP_Q_R) is between 40 ~ 240MHz. + */ +en_result_t CLK_PLLHInit(const stc_clk_pllh_init_t *pstcPLLHInit) +{ + en_result_t enRet; + +#ifdef __DEBUG + uint32_t vcoIn; + uint32_t vcoOut; +#endif + + if (NULL == pstcPLLHInit) + { + enRet = ErrorInvalidParameter; + } + else + { +#ifdef __DEBUG + DDL_ASSERT(IS_CLK_PLLHM_DIV(pstcPLLHInit->PLLCFGR_f.PLLM + 1UL)); + DDL_ASSERT(IS_CLK_PLLHN_MULTI(pstcPLLHInit->PLLCFGR_f.PLLN + 1UL)); + DDL_ASSERT(IS_CLK_PLLHR_DIV(pstcPLLHInit->PLLCFGR_f.PLLR + 1UL)); + DDL_ASSERT(IS_CLK_PLLHQ_DIV(pstcPLLHInit->PLLCFGR_f.PLLQ + 1UL)); + DDL_ASSERT(IS_CLK_PLLHP_DIV(pstcPLLHInit->PLLCFGR_f.PLLP + 1UL)); + DDL_ASSERT(IS_CLK_PLL_SRC(pstcPLLHInit->PLLCFGR_f.PLLSRC)); + + vcoIn = ((CLK_PLLSRC_XTAL == pstcPLLHInit->PLLCFGR_f.PLLSRC ? + XTAL_VALUE : HRC_VALUE) / (pstcPLLHInit->PLLCFGR_f.PLLM + 1UL)); + vcoOut = vcoIn * (pstcPLLHInit->PLLCFGR_f.PLLN + 1UL); + + DDL_ASSERT(IS_CLK_PLLH_VCO_IN(vcoIn)); + DDL_ASSERT(IS_CLK_PLLH_VCO_OUT(vcoOut)); + DDL_ASSERT(IS_CLK_PLLH_FREQ(vcoOut/(pstcPLLHInit->PLLCFGR_f.PLLR + 1UL))); + DDL_ASSERT(IS_CLK_PLLH_FREQ(vcoOut/(pstcPLLHInit->PLLCFGR_f.PLLQ + 1UL))); + DDL_ASSERT(IS_CLK_PLLH_FREQ(vcoOut/(pstcPLLHInit->PLLCFGR_f.PLLP + 1UL))); +#endif + DDL_ASSERT(IS_CLK_PLLH_STATE(pstcPLLHInit->u8PLLState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* set PLL source in advance */ + WRITE_REG32(bM4_CMU->PLLHCFGR_b.PLLSRC, pstcPLLHInit->PLLCFGR_f.PLLSRC); + WRITE_REG32(M4_CMU->PLLHCFGR, pstcPLLHInit->PLLCFGR); + + if (CLK_PLLH_ON == pstcPLLHInit->u8PLLState) + { + enRet = CLK_PLLHCmd(Enable); + } + else + { + enRet = CLK_PLLHCmd(Disable); + } + } + + return enRet; +} + +/** + * @brief Init Xtal initial structure with default value. + * @param [in] pstcXtalInit specifies the Parameter of XTAL. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: NULL pointer + */ +en_result_t CLK_XtalStrucInit(stc_clk_xtal_init_t* pstcXtalInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcXtalInit->u8XtalState = CLK_XTAL_OFF; + pstcXtalInit->u8XtalMode = CLK_XTALMODE_OSC; + pstcXtalInit->u8XtalDrv = CLK_XTALDRV_HIGH; + pstcXtalInit->u8XtalStb = CLK_XTALSTB_2MS; + } + + return enRet; +} + +/** + * @brief XTAL initialize. + * @param [in] pstcXtalInit specifies the XTAL initial config. + * @arg u8XtalState : The new state of the XTAL. + * @arg u8XtalDrv : The XTAL drive ability. + * @arg u8XtalMode : The XTAL mode selection osc or exclk. + * @arg u8XtalStb : The XTAL stable time selection. + * @retval en_result_t + * OK, XTAL intial successfully. + * ErrorTimeout, XTAL operate timeout. + * ErrorNotReady, XTAL is the system clock, CANNOT stop it. + * ErrorInvalidParameter, NULL pointer. + * @note DO NOT STOP XTAL while using it as system clock. + */ +en_result_t CLK_XtalInit(const stc_clk_xtal_init_t *pstcXtalInit) +{ + en_result_t enRet; + + if (NULL == pstcXtalInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_CLK_XTAL_STATE(pstcXtalInit->u8XtalState)); + DDL_ASSERT(IS_CLK_XTALDRV_MODE(pstcXtalInit->u8XtalDrv)); + DDL_ASSERT(IS_CLK_XTAL_MODE(pstcXtalInit->u8XtalMode)); + DDL_ASSERT(IS_CLK_XTALSTB_SEL(pstcXtalInit->u8XtalStb)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(M4_CMU->XTALSTBCR, pstcXtalInit->u8XtalStb); + WRITE_REG8(M4_CMU->XTALCFGR, (0x80U | pstcXtalInit->u8XtalDrv | pstcXtalInit->u8XtalMode)); + + if (CLK_XTAL_ON == pstcXtalInit->u8XtalState) + { + enRet = CLK_XtalCmd(Enable); + } + else + { + enRet = CLK_XtalCmd(Disable); + } + } + + return enRet; +} + +/** + * @brief Init Xtal32 initial structure with default value. + * @param [in] pstcXtal32Init specifies the Parameter of XTAL32. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: NULL pointer + */ +en_result_t CLK_Xtal32StrucInit(stc_clk_xtal32_init_t* pstcXtal32Init) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcXtal32Init) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcXtal32Init->u8Xtal32State = CLK_XTAL32_OFF; + pstcXtal32Init->u8Xtal32Drv = CLK_XTAL32DRV_MID; + pstcXtal32Init->u8Xtal32NF = CLK_XTAL32NF_FULL; + } + + return enRet; +} + +/** + * @brief XTAL32 initialize. + * @param [in] pstcXtal32Init specifies the XTAL32 initial config. + * @arg u8Xtal32State : The new state of the XTAL32. + * @arg u8Xtal32Drv : The XTAL32 drive capacity. + * @arg u8Xtal32NF : The XTAL32 nosie filter on or off. + * @retval en_result_t + * OK, XTAL32 intial successfully. + * ErrorNotReady, XTAL32 is the system clock, CANNOT stop it. + * ErrorInvalidParameter, NULL pointer. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +en_result_t CLK_Xtal32Init(const stc_clk_xtal32_init_t *pstcXtal32Init) +{ + en_result_t enRet; + + if (NULL == pstcXtal32Init) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Parameters check */ + DDL_ASSERT(IS_CLK_XTAL32DRV_MODE(pstcXtal32Init->u8Xtal32Drv)); + DDL_ASSERT(IS_CLK_XTAL32_FILT_SEL(pstcXtal32Init->u8Xtal32NF)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + DDL_ASSERT(IS_CLK_SEL_UNLOCKED()); + + WRITE_REG8(M4_PWC->VBATRSTR, 0xA5U); + WRITE_REG8(M4_CMU->XTAL32CFGR, pstcXtal32Init->u8Xtal32Drv); + WRITE_REG8(M4_CMU->XTAL32NFR, pstcXtal32Init->u8Xtal32NF); + + if (CLK_XTAL32_ON == pstcXtal32Init->u8Xtal32State) + { + enRet = CLK_Xtal32Cmd(Enable); + } + else + { + enRet = CLK_Xtal32Cmd(Disable); + } + } + + return enRet; +} + +/** + * @brief XTAL function enable/disbale. + * @param [in] enNewState specifies the new state of XTAL. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, XTAL operate successfully + * ErrorNotReady, XTAL is the system clock or as the PLL source clock, + * CANNOT stop it. + * ErrorTimeout, XTAL operate timeout. + * @note DO NOT STOP XTAL while using it as system clock or as the PLL source clock. + */ +en_result_t CLK_XtalCmd(en_functional_state_t enNewState) +{ + + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + if (CLK_SYSCLKSOURCE_XTAL == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + enRet = ErrorNotReady; + } + /* XTAL as PLL clock source and PLL is working */ + else if (0UL == bM4_CMU->PLLHCFGR_b.PLLSRC) + { + if (0UL == bM4_CMU->PLLHCR_b.PLLHOFF) + { + enRet = ErrorNotReady; + } + else + { + WRITE_REG32(bM4_CMU->XTALCR_b.XTALSTP, CLK_XTAL_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->XTALCR_b.XTALSTP, CLK_XTAL_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->XTALCR_b.XTALSTP, CLK_XTAL_ON); + + enRet = ErrorTimeout; + while (timeout <= CLK_XTAL_TIMEOUT) + { + if (Set == CLK_GetStableStatus(CMU_OSCSTBSR_XTALSTBF)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + return enRet; +} + +/** + * @brief XTAL32 function enable/disbale. + * @param [in] enNewState specifies the new state of XTAL32. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, XTAL32 operate successfully + * ErrorNotReady, XTAL32 is the system clock, CANNOT stop it. + * @note DO NOT STOP XTAL32 while using it as system clock. + */ +en_result_t CLK_Xtal32Cmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + if (CLK_SYSCLKSOURCE_XTAL32 == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + enRet = ErrorNotReady; + } + else + { + WRITE_REG32(bM4_CMU->XTAL32CR_b.XTAL32STP, CLK_XTAL32_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->XTAL32CR_b.XTAL32STP, CLK_XTAL32_ON); + + while (timeout <= CLK_XTAL32_TIMEOUT) + { + timeout++; + } + } + + return enRet; +} + +/** + * @brief HRC function enable/disbale. + * @param [in] enNewState specifies the new state of HRC. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, HRC operate successfully + * ErrorNotReady, HRC is the system clock or as the PLL source clock, + * CANNOT stop it. + * ErrorTimeout, HRC operate timeout + * @note DO NOT STOP HRC while using it as system clock or as the PLL source clock. + */ +en_result_t CLK_HrcCmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + if (CLK_SYSCLKSOURCE_HRC == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + enRet = ErrorNotReady; + } + /* HRC as PLL clock source and PLL is working */ + else if (1UL == bM4_CMU->PLLHCFGR_b.PLLSRC) + { + if (0UL == bM4_CMU->PLLHCR_b.PLLHOFF) + { + enRet = ErrorNotReady; + } + else + { + WRITE_REG32(bM4_CMU->HRCCR_b.HRCSTP, CLK_HRC_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->HRCCR_b.HRCSTP, CLK_HRC_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->HRCCR_b.HRCSTP, CLK_HRC_ON); + + enRet = ErrorTimeout; + while (timeout <= CLK_HRC_TIMEOUT) + { + if (Set == CLK_GetStableStatus(CMU_OSCSTBSR_HRCSTBF)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + return enRet; +} + +/** + * @brief MRC function enable/disbale. + * @param [in] enNewState specifies the new state of MRC. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, MRC operate successfully + * ErrorNotReady, MRC is the system clock, CANNOT stop it. + * @note DO NOT STOP MRC while using it as system clock. + */ +en_result_t CLK_MrcCmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + if (CLK_SYSCLKSOURCE_MRC == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + enRet = ErrorNotReady; + } + else + { + WRITE_REG32(bM4_CMU->MRCCR_b.MRCSTP, CLK_MRC_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->MRCCR_b.MRCSTP, CLK_MRC_ON); + + while (timeout <= CLK_MRC_TIMEOUT) + { + timeout++; + } + } + + return enRet; +} + +/** + * @brief LRC function enable/disbale. + * @param [in] enNewState specifies the new state of LRC. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, LRC operate successfully + * ErrorNotReady, LRC is the system clock, CANNOT stop it. + * @note DO NOT STOP LRC while using it as system clock. + */ +en_result_t CLK_LrcCmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + if (CLK_SYSCLKSOURCE_LRC == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + enRet = ErrorNotReady; + } + else + { + WRITE_REG32(bM4_CMU->LRCCR_b.LRCSTP, CLK_LRC_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->LRCCR_b.LRCSTP, CLK_LRC_ON); + + while (timeout <= CLK_LRC_TIMEOUT) + { + timeout++; + } + } + + return enRet; +} + +/** + * @brief PLLA function enable/disbale. + * @param [in] enNewState specifies the new state of PLLA. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, PLLA operate successfully + * ErrorTimeout, PLLA operate timeout + * @note + */ +en_result_t CLK_PLLACmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + WRITE_REG32(bM4_CMU->PLLACR_b.PLLAOFF, CLK_PLLA_OFF); + } + else + { + WRITE_REG32(bM4_CMU->PLLACR_b.PLLAOFF, CLK_PLLA_ON); + + enRet = ErrorTimeout; + while (timeout <= CLK_PLLA_TIMEOUT) + { + if (Set == CLK_GetStableStatus(CMU_OSCSTBSR_PLLASTBF)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + return enRet; +} + +/** + * @brief PLLH function enable/disbale. + * @param [in] enNewState specifies the new state of PLLH. + * @arg Enable + * @arg Disable + * @retval en_result_t + * OK, PLLH operate successfully + * ErrorNotReady, PLLH is the system clock, CANNOT stop it. + * ErrorTimeout, PLLH operate timeout + * @note DO NOT STOP PLLH while using it as system clock. + */ +en_result_t CLK_PLLHCmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + __IO uint32_t timeout = 0UL; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (Disable == enNewState) + { + if (CLK_SYSCLKSOURCE_PLLH == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + enRet = ErrorNotReady; + } + else + { + WRITE_REG32(bM4_CMU->PLLHCR_b.PLLHOFF, CLK_PLLH_OFF); + } + } + else + { + WRITE_REG32(bM4_CMU->PLLHCR_b.PLLHOFF, CLK_PLLH_ON); + + enRet = ErrorTimeout; + while (timeout <= CLK_PLLH_TIMEOUT) + { + if (Set == CLK_GetStableStatus(CMU_OSCSTBSR_PLLHSTBF)) + { + enRet = Ok; + break; + } + timeout++; + } + } + + return enRet; +} + +/** + * @brief Init XtalStd initial structure with default value. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t CLK_XtalStdStrucInit(stc_clk_xtalstd_init_t* pstcXtalStdInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcXtalStdInit->u8XtalStdState = CLK_XTALSTD_OFF; + pstcXtalStdInit->u8XtalStdMode = CLK_XTALSTD_MODE_INT; + pstcXtalStdInit->u8XtalStdInt = CLK_XTALSTD_RST_OFF; + pstcXtalStdInit->u8XtalStdRst = CLK_XTALSTD_INT_OFF; + } + + return enRet; +} + +/** + * @brief Initialise the XTAL status detection. + * @param [in] pstcXtalStdInit specifies the Parameter of XTALSTD. + * @arg u8XtalStdState: The new state of the XTALSTD. + * @arg u8XtalStdMode: The XTAL status detection occur interrupt or reset. + * @arg u8XtalStdInt: The XTAL status detection interrupt on or off. + * @arg u8XtalStdRst: The XTAL status detection reset on or off. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t CLK_XtalStdInit(const stc_clk_xtalstd_init_t* pstcXtalStdInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcXtalStdInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_STATE(pstcXtalStdInit->u8XtalStdState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if(CLK_XTALSTD_OFF == pstcXtalStdInit->u8XtalStdState) + { + /* Disbale XTAL status detection */ + WRITE_REG32(bM4_CMU->XTALSTDCR_b.XTALSTDE, (uint32_t)CLK_XTALSTD_OFF); + } + else + { + /* Parameter valid check */ + DDL_ASSERT(IS_CLK_XTALSTD_MODE(pstcXtalStdInit->u8XtalStdMode)); + DDL_ASSERT(IS_CLK_XTALSTD_INT_STATE(pstcXtalStdInit->u8XtalStdInt)); + DDL_ASSERT(IS_CLK_XTALSTD_RST_STATE(pstcXtalStdInit->u8XtalStdRst)); + + /* Configure and enable XTALSTD */ + WRITE_REG8(M4_CMU->XTALSTDCR, (pstcXtalStdInit->u8XtalStdState | \ + pstcXtalStdInit->u8XtalStdMode | \ + pstcXtalStdInit->u8XtalStdInt | \ + pstcXtalStdInit->u8XtalStdRst)); + } + } + + return enRet; +} + +/** + * @brief Clear the XTAL error flag. + * @param None + * @retval None + * @note The system clock should not be XTAL before call this function. + */ +void CLK_ClearXtalStdStatus(void) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if(1UL == READ_REG32(bM4_CMU->XTALSTDSR_b.XTALSTDF)) + { + /* Clear the XTAL STD flag */ + WRITE_REG32(bM4_CMU->XTALSTDSR_b.XTALSTDF, 0UL); + } +} + +/** + * @brief Get the XTAL error flag. + * @param None + * @retval en_flag_status_t + */ +en_flag_status_t CLK_GetXtalStdStatus(void) +{ + return ((0UL != READ_REG32(bM4_CMU->XTALSTDSR_b.XTALSTDF)) ? Set : Reset); +} + +/** + * @brief Set HRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for HRC. + * @retval None + */ +void CLK_HrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(M4_CMU->HRCTRM, i8TrimVal); +} + +/** + * @brief Set MRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for MRC. + * @retval None + */ +void CLK_MrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(M4_CMU->MRCTRM, i8TrimVal); +} + +/** + * @brief Set LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for LRC. + * @retval None + */ +void CLK_LrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(M4_CMU->LRCTRM, i8TrimVal); +} + +/** + * @brief Set RTC LRC trimming value. + * @param [in] i8TrimVal specifies the trimming value for RTC LRC. + * @retval None + */ +void CLK_RtcLrcTrim(int8_t i8TrimVal) +{ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(M4_CMU->RTCLRCTRM, i8TrimVal); +} + +/** + * @brief PLL/XTAL/HRC stable flag read. + * @param [in] u8StableFlag specifies the stable flag to be read. + * @arg CLK_STB_FLAG_HRCSTB + * @arg CLK_STB_FLAG_XTALSTB + * @arg CLK_STB_FLAG_PLLASTB + * @arg CLK_STB_FLAG_PLLHSTB + * @retval en_flag_status_t + */ +en_flag_status_t CLK_GetStableStatus(uint8_t u8StableFlag) +{ + DDL_ASSERT(IS_CLK_STB_FLAG(u8StableFlag)); + + return ((READ_REG8_BIT(M4_CMU->OSCSTBSR, u8StableFlag))? Set : Reset); +} + +/** + * @brief Set the system clock source. + * @param [in] u8Src specifies the source of system clock. + * This parameter can be one of the following values: + * @arg CLK_SYSCLKSOURCE_HRC : select HRC as system clock source + * @arg CLK_SYSCLKSOURCE_MRC : select MHRC as system clock source + * @arg CLK_SYSCLKSOURCE_LRC : select LRC as system clock source + * @arg CLK_SYSCLKSOURCE_XTAL : select XTAL as system clock source + * @arg CLK_SYSCLKSOURCE_XTAL32 : select XTAL32 as system clock source + * @arg CLK_SYSCLKSOURCE_PLLH : select PLLH as system clock source + * @retval None + */ +void CLK_SetSysClkSrc(uint8_t u8Src) +{ + __IO uint32_t timeout = 0UL; + /* backup FCGx setting */ + __IO uint32_t fcg0 = M4_PWC->FCG0; + __IO uint32_t fcg1 = M4_PWC->FCG1; + __IO uint32_t fcg2 = M4_PWC->FCG2; + __IO uint32_t fcg3 = M4_PWC->FCG3; + uint8_t u8TmpFlag = 0U; + + DDL_ASSERT(IS_CLK_SYSCLK_SRC(u8Src)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLKSOURCE_PLLH == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW) || \ + (CLK_SYSCLKSOURCE_PLLH == u8Src)) + { + u8TmpFlag = 1U; + /* FCG0 protect judgment */ + DDL_ASSERT((M4_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + /* Close FCGx. */ + M4_PWC->FCG0 = CLK_FCG0_DEFAULT; + M4_PWC->FCG1 = CLK_FCG1_DEFAULT; + M4_PWC->FCG2 = CLK_FCG2_DEFAULT; + M4_PWC->FCG3 = CLK_FCG3_DEFAULT; + + /* Wait stable after close FCGx. */ + do + { + timeout++; + } while(timeout < CLK_SYSCLK_SW_STABLE); + } + + /* Set system clock source */ + WRITE_REG8(M4_CMU->CKSWR, u8Src); + + if (1U == u8TmpFlag) + { + M4_PWC->FCG0 = fcg0; + M4_PWC->FCG1 = fcg1; + M4_PWC->FCG2 = fcg2; + M4_PWC->FCG3 = fcg3; + /* Wait stable after open fcg. */ + timeout = 0UL; + do + { + timeout++; + } while(timeout < CLK_SYSCLK_SW_STABLE); + } + + /* Update system clock */ + SystemCoreClockUpdate(); +} + +/** + * @brief Get bus clock frequency. + * @param [out] pstcClkFreq specifies the pointer to get bus frequency. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: NULL pointer + */ +en_result_t CLK_GetClockFreq(stc_clk_freq_t *pstcClkFreq) +{ + en_result_t enRet = Ok; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + + if (NULL == pstcClkFreq) + { + enRet = ErrorInvalidParameter; + } + else + { + switch (READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + case CLK_SYSCLKSOURCE_HRC: + /* HRC is used to system clock */ + pstcClkFreq->sysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLKSOURCE_MRC: + /* MRC is used to system clock */ + pstcClkFreq->sysclkFreq = MRC_VALUE; + break; + case CLK_SYSCLKSOURCE_LRC: + /* LRC is used to system clock */ + pstcClkFreq->sysclkFreq = LRC_VALUE; + break; + case CLK_SYSCLKSOURCE_XTAL: + /* XTAL is used to system clock */ + pstcClkFreq->sysclkFreq = XTAL_VALUE; + break; + case CLK_SYSCLKSOURCE_XTAL32: + /* XTAL32 is used to system clock */ + pstcClkFreq->sysclkFreq = HRC_VALUE; + break; + case CLK_SYSCLKSOURCE_PLLH: + /* PLLHP is used as system clock. */ + pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL); + plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL); + pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL); + + /* fpll = ((pllin / pllm) * plln) / pllp */ + if (CLK_PLLSRC_XTAL == READ_REG32_BIT(M4_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC)) + { + pstcClkFreq->sysclkFreq = ((XTAL_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL); + } + else + { + pstcClkFreq->sysclkFreq = ((HRC_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL); + } + break; + default: + break; + } + + /* Get hclk. */ + pstcClkFreq->hclkFreq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_HCLKS) >> CMU_SCFGR_HCLKS_POS); + + /* Get exck. */ + pstcClkFreq->exckFreq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_EXCKS) >> CMU_SCFGR_EXCKS_POS); + + /* Get pclk0. */ + pstcClkFreq->pclk0Freq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + + /* Get pclk1. */ + pstcClkFreq->pclk1Freq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS); + + /* Get pclk2. */ + pstcClkFreq->pclk2Freq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK2S) >> CMU_SCFGR_PCLK2S_POS); + + /* Get pclk3. */ + pstcClkFreq->pclk3Freq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS); + + /* Get pclk4. */ + pstcClkFreq->pclk4Freq = pstcClkFreq->sysclkFreq >> \ + (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK4S) >> CMU_SCFGR_PCLK4S_POS); + } + return enRet; +} + +/** + * @brief Get PLLH/PLLA P/Q/R clock frequency. + * @param [out] pstcPllClkFreq specifies the pointer to get PLLH/PLLA frequency. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: NULL pointer + */ +en_result_t CLK_GetPllClockFreq(stc_pll_clk_freq_t *pstcPllClkFreq) +{ + en_result_t enRet = Ok; + uint32_t pllhn; + uint32_t pllhm; + uint32_t pllhp; + uint32_t pllhq; + uint32_t pllhr; + uint32_t pllan; + uint32_t pllam; + uint32_t pllap; + uint32_t pllaq; + uint32_t pllar; + uint32_t pllin; + + if (NULL == pstcPllClkFreq) + { + enRet = ErrorInvalidParameter; + } + else + { + pllhp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL); + pllhq = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHQ_POS) & 0x0FUL); + pllhr = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHR_POS) & 0x0FUL); + pllhn = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL); + pllhm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL); + + pllap = (uint32_t)((M4_CMU->PLLACFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL); + pllaq = (uint32_t)((M4_CMU->PLLACFGR >> CMU_PLLHCFGR_PLLHQ_POS) & 0x0FUL); + pllar = (uint32_t)((M4_CMU->PLLACFGR >> CMU_PLLHCFGR_PLLHR_POS) & 0x0FUL); + pllan = (uint32_t)((M4_CMU->PLLACFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0x1FFUL); + pllam = (uint32_t)((M4_CMU->PLLACFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x1FUL); + + /* PLLHP is used as system clock. */ + if (CLK_PLLSRC_XTAL == READ_REG32_BIT(M4_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC)) + { + pllin = XTAL_VALUE; + } + else + { + pllin = HRC_VALUE; + } + pstcPllClkFreq->pllhvcin = (pllin/(pllhm + 1UL)); + pstcPllClkFreq->pllhvco = ((pllin/(pllhm + 1UL))*(pllhn + 1UL)); + pstcPllClkFreq->pllhp = ((pllin/(pllhm + 1UL))*(pllhn + 1UL))/(pllhp + 1UL); + pstcPllClkFreq->pllhq = ((pllin/(pllhm + 1UL))*(pllhn + 1UL))/(pllhq + 1UL); + pstcPllClkFreq->pllhr = ((pllin/(pllhm + 1UL))*(pllhn + 1UL))/(pllhr + 1UL); + + pstcPllClkFreq->pllavcin = (pllin/(pllam + 1UL)); + pstcPllClkFreq->pllavco = ((pllin/(pllam + 1UL))*(pllan + 1UL)); + pstcPllClkFreq->pllap = ((pllin/(pllam + 1UL))*(pllan + 1UL))/(pllap + 1UL); + pstcPllClkFreq->pllaq = ((pllin/(pllam + 1UL))*(pllan + 1UL))/(pllaq + 1UL); + pstcPllClkFreq->pllar = ((pllin/(pllam + 1UL))*(pllan + 1UL))/(pllar + 1UL); + } + return enRet; +} + +/** + * @brief HCLK/PCLK divide setting. + * @param [in] u8ClkCate specifies the clock to be divided. + * @arg CLK_CATE_PCLK0: Select PCLK0 to be divided + * @arg CLK_CATE_PCLK1: Select PCLK1 to be divided + * @arg CLK_CATE_PCLK2: Select PCLK2 to be divided + * @arg CLK_CATE_PCLK3: Select PCLK3 to be divided + * @arg CLK_CATE_PCLK4: Select PCLK4 to be divided + * @arg CLK_CATE_EXCLK: Select EXCLK to be divided + * @arg CLK_CATE_HCLK : Select HCLK to be divided + * @arg CLK_CATE_ALL : Select all to be divided + * @param [in] u32Div specifies the clock divide factor. + * @arg CLK_HCLK_DIV1 : HCLK no divide + * @arg CLK_HCLK_DIV2 : HCLK divided by 2 + * @arg CLK_HCLK_DIV4 : HCLK divided by 4 + * @arg CLK_HCLK_DIV8 : HCLK divided by 8 + * @arg CLK_HCLK_DIV16: HCLK divided by 16 + * @arg CLK_HCLK_DIV32: HCLK divided by 32 + * @arg CLK_HCLK_DIV64: HCLK divided by 64 + * @arg CLK_EXCLK_DIV1 : EXCLK no divide + * @arg CLK_EXCLK_DIV2 : EXCLK divided by 2 + * @arg CLK_EXCLK_DIV4 : EXCLK divided by 4 + * @arg CLK_EXCLK_DIV8 : EXCLK divided by 8 + * @arg CLK_EXCLK_DIV16: EXCLK divided by 16 + * @arg CLK_EXCLK_DIV32: EXCLK divided by 32 + * @arg CLK_EXCLK_DIV64: EXCLK divided by 64 + * @arg CLK_PCLKx_DIV1 : PCLKx no divide + * @arg CLK_PCLKx_DIV2 : PCLKx divided by 2 + * @arg CLK_PCLKx_DIV4 : PCLKx divided by 4 + * @arg CLK_PCLKx_DIV8 : PCLKx divided by 8 + * @arg CLK_PCLKx_DIV16: PCLKx divided by 16 + * @arg CLK_PCLKx_DIV32: PCLKx divided by 32 + * @arg CLK_PCLKx_DIV64: PCLKx divided by 64 + * @retval None + * @note 'x' is 0~4 in CLK_PCLKx_DIVy + */ +void CLK_ClkDiv(uint8_t u8ClkCate, uint32_t u32Div) +{ + __IO uint32_t timeout = 0UL; + /* backup FCGx setting */ + __IO uint32_t fcg0 = M4_PWC->FCG0; + __IO uint32_t fcg1 = M4_PWC->FCG1; + __IO uint32_t fcg2 = M4_PWC->FCG2; + __IO uint32_t fcg3 = M4_PWC->FCG3; + uint8_t u8TmpFlag = 0U; + + DDL_ASSERT(IS_CLK_HCLK_DIV(u32Div & CMU_SCFGR_HCLKS)); + DDL_ASSERT(IS_CLK_EXCLK_DIV(u32Div & CMU_SCFGR_EXCKS)); + DDL_ASSERT(IS_CLK_PCLK0_DIV(u32Div & CMU_SCFGR_PCLK0S)); + DDL_ASSERT(IS_CLK_PCLK1_DIV(u32Div & CMU_SCFGR_PCLK1S)); + DDL_ASSERT(IS_CLK_PCLK2_DIV(u32Div & CMU_SCFGR_PCLK2S)); + DDL_ASSERT(IS_CLK_PCLK3_DIV(u32Div & CMU_SCFGR_PCLK3S)); + DDL_ASSERT(IS_CLK_PCLK4_DIV(u32Div & CMU_SCFGR_PCLK4S)); + DDL_ASSERT(IS_CLK_CATE(u8ClkCate)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Only current system clock source or target system clock source is PLLH + need to close fcg0~fcg3 and open fcg0~fcg3 during switch system clock source. + We need to backup fcg0~fcg3 before close them. */ + if (CLK_SYSCLKSOURCE_PLLH == READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + DDL_ASSERT((M4_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0); + + u8TmpFlag = 1U; + + /* Close FCGx. */ + M4_PWC->FCG0 = CLK_FCG0_DEFAULT; + M4_PWC->FCG1 = CLK_FCG1_DEFAULT; + M4_PWC->FCG2 = CLK_FCG2_DEFAULT; + M4_PWC->FCG3 = CLK_FCG3_DEFAULT; + + /* Wait stable after close FCGx. */ + do + { + timeout++; + } while(timeout < CLK_SYSCLK_SW_STABLE); + } + + /* PCLK0 div */ + if (0U != (CLK_CATE_PCLK0 & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_PCLK0S, u32Div); + } + /* PCLK1 div */ + if (0U != (CLK_CATE_PCLK1 & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S, u32Div); + } + /* PCLK2 div */ + if (0U != (CLK_CATE_PCLK2 & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_PCLK2S, u32Div); + } + /* PCLK3 div */ + if (0U != (CLK_CATE_PCLK3 & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_PCLK3S, u32Div); + } + /* PCLK4 div */ + if (0U != (CLK_CATE_PCLK4 & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_PCLK4S, u32Div); + } + /* Ext. bus clock div */ + if (0U != (CLK_CATE_EXCLK & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_EXCKS, u32Div); + } + /* HCLK div */ + if (0U != (CLK_CATE_HCLK & u8ClkCate)) + { + MODIFY_REG32(M4_CMU->SCFGR, CMU_SCFGR_HCLKS, u32Div); + } + if (1U == u8TmpFlag) + { + M4_PWC->FCG0 = fcg0; + M4_PWC->FCG1 = fcg1; + M4_PWC->FCG2 = fcg2; + M4_PWC->FCG3 = fcg3; + + /* Wait stable after open fcg. */ + timeout = 0UL; + do + { + timeout++; + } while(timeout < CLK_SYSCLK_SW_STABLE); + } +} + +/** + * @brief USB clock source config. + * @param [in] u8UsbClk specifies the USB clock source. + * @arg CLK_USB_CLK_MCLK_DIV2: Select PCLK1 divide by 2 as USB clock + * @arg CLK_USB_CLK_MCLK_DIV3: Select PCLK1 divide by 3 as USB clock + * @arg CLK_USB_CLK_MCLK_DIV4: Select PCLK1 divide by 4 as USB clock + * @arg CLK_USB_CLK_MCLK_DIV5: Select PCLK1 divide by 5 as USB clock + * @arg CLK_USB_CLK_MCLK_DIV6: Select PCLK1 divide by 6 as USB clock + * @arg CLK_USB_CLK_MCLK_DIV7: Select PCLK1 divide by 7 as USB clock + * @arg CLK_USB_CLK_MCLK_DIV8: Select PCLK1 divide by 8 as USB clock + * @arg CLK_USB_CLK_PLLHQ: Select PLLHQ as USB clock + * @arg CLK_USB_CLK_PLLHR: Select PLLHR as USB clock + * @arg CLK_USB_CLK_PLLAP: Select PLLAP as USB clock + * @arg CLK_USB_CLK_PLLAQ: Select PLLAQ as USB clock + * @arg CLK_USB_CLK_PLLAR: Select PLLAR as USB clock + * @retval None + */ +void CLK_USB_ClkConfig(uint8_t u8UsbClk) +{ + DDL_ASSERT(IS_CLK_USB_CLK(u8UsbClk)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG8(M4_CMU->USBCKCFGR, u8UsbClk); +} + +/** + * @brief CAN clock source config. + * @param [in] u8CanCh specifies the CAN channel for clock source. + * @arg CLK_CAN_CH1: CAN Channel 1 + * @arg CLK_CAN_CH2: CAN Channel 2 + * @param [in] u8CanClk specifies the CAN clock source. + * @arg CLK_CAN1_CLK_MCLK_DIV2: Select system clock divide by 2 as CAN clock + * @arg CLK_CAN1_CLK_MCLK_DIV3: Select system clock divide by 3 as CAN clock + * @arg CLK_CAN1_CLK_MCLK_DIV4: Select system clock divide by 4 as CAN clock + * @arg CLK_CAN1_CLK_MCLK_DIV5: Select system clock divide by 5 as CAN clock + * @arg CLK_CAN1_CLK_MCLK_DIV6: Select system clock divide by 6 as CAN clock + * @arg CLK_CAN1_CLK_MCLK_DIV7: Select system clock divide by 7 as CAN clock + * @arg CLK_CAN1_CLK_MCLK_DIV8: Select system clock divide by 8 as CAN clock + * @arg CLK_CAN1_CLK_PLLHQ: Select PLLHQ as CAN clock + * @arg CLK_CAN1_CLK_PLLHR: Select PLLHR as CAN clock + * @arg CLK_CAN1_CLK_PLLAP: Select PLLAP as CAN clock + * @arg CLK_CAN1_CLK_PLLAQ: Select PLLAQ as CAN clock + * @arg CLK_CAN1_CLK_PLLAR: Select PLLAR as CAN clock + * @arg CLK_CAN_CLK_XTAL: Select PLLAR as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV2: Select system clock divide by 2 as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV3: Select system clock divide by 3 as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV4: Select system clock divide by 4 as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV5: Select system clock divide by 5 as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV6: Select system clock divide by 6 as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV7: Select system clock divide by 7 as CAN clock + * @arg CLK_CAN2_CLK_MCLK_DIV8: Select system clock divide by 8 as CAN clock + * @arg CLK_CAN2_CLK_PLLHQ: Select PLLHQ as CAN clock + * @arg CLK_CAN2_CLK_PLLHR: Select PLLHR as CAN clock + * @arg CLK_CAN2_CLK_PLLAP: Select PLLAP as CAN clock + * @arg CLK_CAN2_CLK_PLLAQ: Select PLLAQ as CAN clock + * @arg CLK_CAN2_CLK_PLLAR: Select PLLAR as CAN clock + * @arg CLK_CAN2_CLK_XTAL: Select PLLAR as CAN clock + * @retval None + */ +void CLK_CAN_ClkConfig(uint8_t u8CanCh, uint8_t u8CanClk) +{ + DDL_ASSERT(IS_CLK_CAN_CH(u8CanCh)); + DDL_ASSERT(IS_CLK_CAN_CLK(u8CanClk)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + if (0U != (CLK_CAN_CH1 & u8CanCh)) + { + MODIFY_REG8(M4_CMU->CANCKCFGR, CMU_CANCKCFGR_CAN1CKS, u8CanClk); + } + if (0U != (CLK_CAN_CH2 & u8CanCh)) + { + MODIFY_REG8(M4_CMU->CANCKCFGR, CMU_CANCKCFGR_CAN2CKS, u8CanClk); + } +} + +/** + * @brief I2S clock source config. + * @param [in] u8I2sCh specifies the I2S channel for clock source. + * @arg CLK_I2S_CH1: I2S Channel 1 + * @arg CLK_I2S_CH2: I2S Channel 2 + * @arg CLK_I2S_CH3: I2S Channel 3 + * @arg CLK_I2S_CH4: I2S Channel 4 + * @param [in] u16I2sClk specifies the I2S clock source. + * @arg CLK_I2S1_CLK_PCLK: Select PCLK3 as I2S clock + * @arg CLK_I2S1_CLK_PLLHQ: Select PLLHQ as I2S clock + * @arg CLK_I2S1_CLK_PLLHR: Select PLLHR as I2S clock + * @arg CLK_I2S1_CLK_PLLAP: Select PLLAP as I2S clock + * @arg CLK_I2S1_CLK_PLLAQ: Select PLLAQ as I2S clock + * @arg CLK_I2S1_CLK_PLLAR: Select PLLAR as I2S clock + * @arg CLK_I2S2_CLK_PCLK: Select PCLK3 as I2S clock + * @arg CLK_I2S2_CLK_PLLHQ: Select PLLHQ as I2S clock + * @arg CLK_I2S2_CLK_PLLHR: Select PLLHR as I2S clock + * @arg CLK_I2S2_CLK_PLLAP: Select PLLAP as I2S clock + * @arg CLK_I2S2_CLK_PLLAQ: Select PLLAQ as I2S clock + * @arg CLK_I2S2_CLK_PLLAR: Select PLLAR as I2S clock + * @arg CLK_I2S3_CLK_PCLK: Select PCLK3 as I2S clock + * @arg CLK_I2S3_CLK_PLLHQ: Select PLLHQ as I2S clock + * @arg CLK_I2S3_CLK_PLLHR: Select PLLHR as I2S clock + * @arg CLK_I2S3_CLK_PLLAP: Select PLLAP as I2S clock + * @arg CLK_I2S3_CLK_PLLAQ: Select PLLAQ as I2S clock + * @arg CLK_I2S3_CLK_PLLAR: Select PLLAR as I2S clock + * @arg CLK_I2S4_CLK_PCLK: Select PCLK3 as I2S clock + * @arg CLK_I2S4_CLK_PLLHQ: Select PLLHQ as I2S clock + * @arg CLK_I2S4_CLK_PLLHR: Select PLLHR as I2S clock + * @arg CLK_I2S4_CLK_PLLAP: Select PLLAP as I2S clock + * @arg CLK_I2S4_CLK_PLLAQ: Select PLLAQ as I2S clock + * @arg CLK_I2S4_CLK_PLLAR: Select PLLAR as I2S clock + * @retval None + */ +void CLK_I2S_ClkConfig(uint8_t u8I2sCh, uint16_t u16I2sClk) +{ + DDL_ASSERT(IS_CLK_I2S_CH(u8I2sCh)); + DDL_ASSERT(IS_CLK_I2S_CLK(u16I2sClk)); + DDL_ASSERT(IS_CLK_SEL_UNLOCKED()); + + if (0U != (CLK_I2S_CH1 & u8I2sCh)) + { + MODIFY_REG16(M4_CMU->I2SCKSEL, CMU_I2SCKSEL_I2S1CKSEL, u16I2sClk); + } + if (0U != (CLK_I2S_CH2 & u8I2sCh)) + { + MODIFY_REG16(M4_CMU->I2SCKSEL, CMU_I2SCKSEL_I2S2CKSEL, u16I2sClk); + } + if (0U != (CLK_I2S_CH3 & u8I2sCh)) + { + MODIFY_REG16(M4_CMU->I2SCKSEL, CMU_I2SCKSEL_I2S3CKSEL, u16I2sClk); + } + if (0U != (CLK_I2S_CH4 & u8I2sCh)) + { + MODIFY_REG16(M4_CMU->I2SCKSEL, CMU_I2SCKSEL_I2S4CKSEL, u16I2sClk); + } +} + +/** + * @brief ADC/DAC/TRNG clock source config. + * @param [in] u16Periclk specifies the ADC/DAC/TRNG clock source. + * @arg CLK_PERI_CLK_PCLK: Select default setting for PCLK2/PCLK4 clock + * @arg CLK_PERI_CLK_PLLHQ: Select PLLHQ as PCLK2/PCLK4 clock + * @arg CLK_PERI_CLK_PLLHR: Select PLLHR as PCLK2/PCLK4 clock + * @arg CLK_PERI_CLK_PLLAP: Select PLLAP as PCLK2/PCLK4 clock + * @arg CLK_PERI_CLK_PLLAQ: Select PLLAQ as PCLK2/PCLK4 clock + * @arg CLK_PERI_CLK_PLLAR: Select PLLAR as PCLK2/PCLK4 clock + * @retval None + * @note PCLK2 is used for ADC clock, PCLK4 is used for DAC/TRANG clock + */ +void CLK_PERI_ClkConfig(uint16_t u16Periclk) +{ + DDL_ASSERT(IS_CLK_PERI_CLK(u16Periclk)); + DDL_ASSERT(IS_CLK_SEL_UNLOCKED()); + + WRITE_REG16(M4_CMU->PERICKSEL, u16Periclk); +} + +/** + * @brief Enable or disable the TPIU clock. + * @param [in] enNewState specifies the new state of the TPIU clock. + * @arg Enable: Enable clock output. + * @arg Disable: Disable clock output. + * @retval None + */ +void CLK_TpiuClkCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + WRITE_REG32(bM4_CMU->TPIUCKCFGR_b.TPIUCKOE, enNewState); +} + +/** + * @brief TPIU clock divider config. + * @param [in] u8TpiuDiv specifies the TPIU clock divide factor. + * @arg CLK_TPIU_CLK_DIV1: TPIU clock no divide + * @arg CLK_TPIU_CLK_DIV2: TPIU clock divide by 2 + * @arg CLK_TPIU_CLK_DIV4: TPIU clock divide by 4 + * @retval None + */ +void CLK_TpiuClkConfig(uint8_t u8TpiuDiv) +{ + DDL_ASSERT(IS_CLK_TPIU_CLK_DIV(u8TpiuDiv)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + MODIFY_REG8(M4_CMU->TPIUCKCFGR, CMU_TPIUCKCFGR_TPIUCKS, u8TpiuDiv); +} + +/** + * @brief Selects the clock source to output on MCO1 pin. + * @param [in] CLK_MCOSource specifies the clock source to output. + * @arg CLK_MCOSOURCCE_HRC HRC clock selected as MCOx source + * @arg CLK_MCOSOURCCE_MRC MRC clock selected as MCOx source + * @arg CLK_MCOSOURCCE_LRC LRC clock selected as MCOx source + * @arg CLK_MCOSOURCCE_XTAL XTAL clock selected as MCOx source + * @arg CLK_MCOSOURCCE_XTAL32 XTAL32 clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLHP PLLHP clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLAP PLLAP clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLHQ PLLHQ clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLAQ PLLAQ clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLAR PLLAR clock selected as MCOx source + * @arg CLK_MCOSOURCCE_SYSCLK System clock selected as MCOx source + * @param [in] CLK_MCODiv specifies the MCOx prescaler. + * @arg CLK_MCO_DIV1: no division applied to MCOx clock + * @arg CLK_MCO_DIV2: division by 2 applied to MCOx clock + * @arg CLK_MCO_DIV4: division by 4 applied to MCOx clock + * @arg CLK_MCO_DIV8: division by 8 applied to MCOx clock + * @arg CLK_MCO_DIV16: division by 16 applied to MCOx clock + * @arg CLK_MCO_DIV32: division by 32 applied to MCOx clock + * @arg CLK_MCO_DIV64: division by 64 applied to MCOx clock + * @arg CLK_MCO_DIV128: division by 128 applied to MCOx clock + * @retval None + * @note MCO pin should be configured in alternate function 1 mode. + */ +void CLK_MCO1Config(uint8_t CLK_MCOSource, uint8_t CLK_MCODiv) +{ + /* Check the parameters. */ + DDL_ASSERT(IS_CLK_MCOSOURCE(CLK_MCOSource)); + DDL_ASSERT(IS_CLK_MCODIV(CLK_MCODiv)); + + /* Enable register write. */ + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Config the MCO1 */ + MODIFY_REG8(M4_CMU->MCO1CFGR, (CMU_MCO1CFGR_MCO1SEL | CMU_MCO1CFGR_MCO1DIV), (CLK_MCODiv | CLK_MCOSource)); +} + +/** + * @brief Enable or disable the MCO1 output. + * @param [in] enNewState specifies the new state of the clock output. + * @arg Enable: Enable clock output. + * @arg Disable: Disable clock output. + * @retval None + */ +void CLK_MCO1Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Enable or disable clock output. */ + WRITE_REG32(bM4_CMU->MCO1CFGR_b.MCO1EN, enNewState); +} + +/** + * @brief Selects the clock source to output on MCO2 pin. + * @param [in] CLK_MCOSource specifies the clock source to output. + * @arg CLK_MCOSOURCCE_HRC HRC clock selected as MCOx source + * @arg CLK_MCOSOURCCE_MRC MRC clock selected as MCOx source + * @arg CLK_MCOSOURCCE_LRC LRC clock selected as MCOx source + * @arg CLK_MCOSOURCCE_XTAL XTAL clock selected as MCOx source + * @arg CLK_MCOSOURCCE_XTAL32 XTAL32 clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLHP PLLHP clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLAP PLLAP clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLHQ PLLHQ clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLAQ PLLAQ clock selected as MCOx source + * @arg CLK_MCOSOURCCE_PLLAR PLLAR clock selected as MCOx source + * @arg CLK_MCOSOURCCE_SYSCLK System clock selected as MCOx source + * @param [in] CLK_MCODiv specifies the MCOx prescaler. + * @arg CLK_MCO_DIV1: no division applied to MCOx clock + * @arg CLK_MCO_DIV2: division by 2 applied to MCOx clock + * @arg CLK_MCO_DIV4: division by 4 applied to MCOx clock + * @arg CLK_MCO_DIV8: division by 8 applied to MCOx clock + * @arg CLK_MCO_DIV16: division by 16 applied to MCOx clock + * @arg CLK_MCO_DIV32: division by 32 applied to MCOx clock + * @arg CLK_MCO_DIV64: division by 64 applied to MCOx clock + * @arg CLK_MCO_DIV128: division by 128 applied to MCOx clock + * @retval None + * @note MCO2 pin should be configured in alternate function 1 mode. + */ +void CLK_MCO2Config(uint8_t CLK_MCOSource, uint8_t CLK_MCODiv) +{ + /* Check the parameters. */ + DDL_ASSERT(IS_CLK_MCOSOURCE(CLK_MCOSource)); + DDL_ASSERT(IS_CLK_MCODIV(CLK_MCODiv)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Config the MCO */ + MODIFY_REG8(M4_CMU->MCO2CFGR, (CMU_MCO2CFGR_MCO2SEL | CMU_MCO2CFGR_MCO2DIV), (CLK_MCODiv | CLK_MCOSource)); +} + +/** + * @brief Enable or disable the MCO2 output. + * @param [in] enNewState specifies the new state of the clock output. + * @arg Enable: Enable clock output. + * @arg Disable: Disable clock output. + * @retval None + */ +void CLK_MCO2Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_CLK_UNLOCKED()); + + /* Enable or disable clock output. */ + WRITE_REG32(bM4_CMU->MCO2CFGR_b.MCO2EN, enNewState); +} + +/** + * @} + */ + +#endif /* DDL_CLK_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_cmp.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_cmp.c new file mode 100644 index 0000000000000000000000000000000000000000..4d94b67e45f95ca54d3a1408d11059b0d48c7914 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_cmp.c @@ -0,0 +1,782 @@ +/** + ******************************************************************************* + * @file hc32f4a0_cmp.c + * @brief This file provides firmware functions to manage the Comparator(CMP). + * + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + 2020-08-31 Heqb Replace CMP_Delay300ns() with the function DDL_DelayUS() + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_cmp.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_CMP CMP + * @brief CMP Driver Library + * @{ + */ + +#if (DDL_CMP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CMP_Local_Macros CMP Local Macros + * @{ + */ + +/** + * @defgroup CMP_Check_Parameters_Validity CMP Check Parameters Validity + * @{ + */ + +#define IS_CMP_INSTANCE(x) \ +( ((x) == M4_CMP1) || \ + ((x) == M4_CMP2) || \ + ((x) == M4_CMP3) || \ + ((x) == M4_CMP4)) + +#define IS_CMP_MODE(x) \ +( ((x) == CMP_MODE_NORMAL) || \ + ((x) == CMP_MODE_WINDOW)) + +#define IS_CMP_CVSL_CH(x) \ +( ((x) == CMP_CVSL_NONE) || \ + ((x) == CMP_CVSL_INP1) || \ + ((x) == CMP_CVSL_INP2) || \ + ((x) == CMP_CVSL_INP3) || \ + ((x) == CMP_CVSL_INP4)) + +#define IS_CMP1_CVSL_SOURCE(x) \ +( ((x) == CMP1_INP3_NONE) || \ + ((x) == CMP1_INP3_CMP1_INP3) || \ + ((x) == CMP1_INP3_CMP2_INP3) || \ + ((x) == CMP1_INP2_NONE) || \ + ((x) == CMP1_INP2_PGA1) || \ + ((x) == CMP1_INP2_PGA2) || \ + ((x) == CMP1_INP2_CMP1_INP2)) + +#define IS_CMP3_CVSL_SOURCE(x) \ +( ((x) == CMP3_INP3_NONE) || \ + ((x) == CMP3_INP3_CMP3_INP3) || \ + ((x) == CMP3_INP3_CMP4_INP3) || \ + ((x) == CMP3_INP2_NONE) || \ + ((x) == CMP3_INP2_PGA3) || \ + ((x) == CMP3_INP2_PGA4) || \ + ((x) == CMP3_INP2_CMP3_INP2)) + +#define IS_CMP_RVSL(x) \ +( ((x) == CMP_RVSL_NONE) || \ + ((x) == CMP_RVSL_INM1) || \ + ((x) == CMP_RVSL_INM2) || \ + ((x) == CMP_RVSL_INM3) || \ + ((x) == CMP_RVSL_INM4)) + +#define IS_CMP_OUT_POLARITY(x) \ +( ((x) == CMP_OUT_REVERSE_OFF) || \ + ((x) == CMP_OUT_REVERSE_ON)) + +#define IS_CMP_OUT_DETECT_EDGE(x) \ +( ((x) == CMP_DETECT_EDGS_NONE) || \ + ((x) == CMP_DETECT_EDGS_RISING) || \ + ((x) == CMP_DETECT_EDGS_FALLING) || \ + ((x) == CMP_DETECT_EDGS_BOTH)) + +#define IS_CMP_OUT_FILTER(x) \ +( ((x) == CMP_OUT_FILTER_NONE) || \ + ((x) == CMP_OUT_FILTER_PCLK3) || \ + ((x) == CMP_OUT_FILTER_PCLK3_DIV8) || \ + ((x) == CMP_OUT_FILTER_PCLK3_DIV32)) + +#define IS_CMP_TIMWIN_FUNC(x) \ +( ((x) == CMP_TIMERWIN_OFF) || \ + ((x) == CMP_TIMERWIN_ON)) + +#define IS_CMP_TIMWIN_INVALIDLEVEL(x) \ +( ((x) == CMP_TIMERWIN_INVALID_LEVEL_LOW) || \ + ((x) == CMP_TIMERWIN_INVALID_LEVEL_HIGH)) + +#define IS_CMP_TIMWIN_OUT_LEVEL(x) \ +( ((x) == CMP_TIMERWIN_OUT_LEVEL_LOW) || \ + ((x) == CMP_TIMERWIN_OUT_LEVEL_HIGH)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup CMP_Global_Functions CMP Global Functions + * @{ + */ + +/** + * @brief Initialize structure stc_cmp_init_t variable with default value. + * @param [in] pstcCMP_InitStruct Pointer to a stc_cmp_init_t structure variable which will be initialized. + * @arg See the struct @ref stc_cmp_init_t. + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + */ +en_result_t CMP_StructInit(stc_cmp_init_t *pstcCMP_InitStruct) +{ + en_result_t enRet = ErrorInvalidParameter; + if (pstcCMP_InitStruct != NULL) + { + pstcCMP_InitStruct->u8CmpCh = CMP_CVSL_NONE; + pstcCMP_InitStruct->u8RefVol = CMP_RVSL_NONE; + pstcCMP_InitStruct->u8OutDetectEdges = CMP_DETECT_EDGS_NONE; + pstcCMP_InitStruct->u8OutFilter = CMP_OUT_FILTER_NONE; + pstcCMP_InitStruct->u8OutPolarity = CMP_OUT_REVERSE_OFF; + enRet = Ok; + } + return enRet; +} + +/** + * @brief De-initialize CMP unit + * @param [in] CMPx Pointer to CMP instance register base,This + * parameter can be one of the following values: + * @arg M0P_CMP1: CMP unit 1 instance register base + * @arg M0P_CMP2: CMP unit 2 instance register base + * @arg M0P_CMP3: CMP unit 3 instance register base + * @arg M0P_CMP4: CMP unit 4 instance register base + * @retval None + */ +void CMP_DeInit(M4_CMP_TypeDef *CMPx) +{ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + CLEAR_REG8(CMPx->MDR); + CLEAR_REG8(CMPx->FIR); + CLEAR_REG8(CMPx->OCR); + CLEAR_REG8(CMPx->PMSR); + CLEAR_REG16(CMPx->VISR); + CLEAR_REG16(CMPx->TWSR); + CLEAR_REG16(CMPx->TWPR); +} + +/** + * @brief CMP normal mode initialize + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] pstcCmpInit CMP function base parameter structure + * @arg See the structure definition for @ref stc_cmp_init_t + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + */ +en_result_t CMP_NormalModeInit(M4_CMP_TypeDef *CMPx, + const stc_cmp_init_t *pstcCmpInit) +{ + en_result_t enRet = ErrorInvalidParameter; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcCmpInit) + { + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_CVSL_CH(pstcCmpInit->u8CmpCh)); + DDL_ASSERT(IS_CMP_RVSL(pstcCmpInit->u8RefVol)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u8OutDetectEdges)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u8OutFilter)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u8OutPolarity)); + + /* Stop CMP compare */ + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Set compare voltage */ + WRITE_REG8(CMPx->PMSR, pstcCmpInit->u8CmpCh); + if((M4_CMP1 == CMPx) && ((pstcCmpInit->u8CmpCh == CMP_CVSL_INP2) || + (pstcCmpInit->u8CmpCh == CMP_CVSL_INP3))) + { + DDL_ASSERT(IS_CMP1_CVSL_SOURCE(pstcCmpInit->u16CmpVol)); + WRITE_REG8(CMPx->VISR, pstcCmpInit->u16CmpVol); + } + if((M4_CMP3 == CMPx) && ((pstcCmpInit->u8CmpCh == CMP_CVSL_INP2) || + (pstcCmpInit->u8CmpCh == CMP_CVSL_INP3))) + { + DDL_ASSERT(IS_CMP3_CVSL_SOURCE(pstcCmpInit->u16CmpVol)); + WRITE_REG8(CMPx->VISR, pstcCmpInit->u16CmpVol); + } + /* Set reference voltage */ + MODIFY_REG8(CMPx->PMSR, CMP_PMSR_RVSL, pstcCmpInit->u8RefVol); + /* Delay 1us*/ + DDL_DelayUS(1U); + /* Start CMP compare */ + SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + DDL_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(CMPx->FIR, (pstcCmpInit->u8OutFilter | pstcCmpInit->u8OutDetectEdges)); + WRITE_REG8(CMPx->OCR, pstcCmpInit->u8OutPolarity); + enRet = Ok; + } + return enRet; +} + +/** + * @brief CMP window mode initialize + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: Select CMP1 and CMP2 for window comparison + * @arg M4_CMP2: Select CMP1 and CMP2 for window comparison + * @arg M4_CMP3: Select CMP3 and CMP4 for window comparison + * @arg M4_CMP4: Select CMP3 and CMP4 for window comparison + * @param [in] pstcCmpInit Configuration structure for window mode initialize + * @arg See the structure definition for @ref stc_cmp_init_t + * @param [in] pstcCmpWinRef Configuration structure for window mode reference voltage + * @arg See the structure definition for @ref stc_cmp_win_ref_t + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + */ +en_result_t CMP_WindowModeInit(const M4_CMP_TypeDef *CMPx, + const stc_cmp_init_t *pstcCmpInit, + const stc_cmp_win_ref_t *pstcCmpWinRef) +{ + en_result_t enRet = ErrorInvalidParameter; + /* Check configuration structure */ + if (NULL != pstcCmpInit) + { + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_CVSL_CH(pstcCmpWinRef->u8CmpCh1)); + DDL_ASSERT(IS_CMP_CVSL_CH(pstcCmpWinRef->u8CmpCh2)); + DDL_ASSERT(IS_CMP_RVSL(pstcCmpWinRef->u8WinVolLow)); + DDL_ASSERT(IS_CMP_RVSL(pstcCmpWinRef->u8WinVolHigh)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(pstcCmpInit->u8OutDetectEdges)); + DDL_ASSERT(IS_CMP_OUT_FILTER(pstcCmpInit->u8OutFilter)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(pstcCmpInit->u8OutPolarity)); + if((CMPx == M4_CMP1) || (CMPx == M4_CMP2)) + { + /* Stop CMP1 CMP2 compare */ + CLEAR_REG8_BIT(M4_CMP1->MDR, CMP_MDR_CENB); + CLEAR_REG8_BIT(M4_CMP2->MDR, CMP_MDR_CENB); + /* Set compare voltage */ + WRITE_REG8(M4_CMP1->PMSR, pstcCmpWinRef->u8CmpCh1); + WRITE_REG8(M4_CMP1->VISR, pstcCmpWinRef->u16CmpVol); + WRITE_REG8(M4_CMP2->PMSR, pstcCmpWinRef->u8CmpCh2); + /* Set reference Voltage */ + MODIFY_REG8(M4_CMP1->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolLow); + MODIFY_REG8(M4_CMP2->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolHigh); + /* Select window compare mode */ + SET_REG8_BIT(M4_CMP2->MDR, CMP_MDR_CWDE); + /* Start CMP compare function */ + SET_REG8_BIT(M4_CMP1->MDR, CMP_MDR_CENB); + SET_REG8_BIT(M4_CMP2->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + DDL_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(M4_CMP2->FIR, pstcCmpInit->u8OutFilter | pstcCmpInit->u8OutDetectEdges); + WRITE_REG8(M4_CMP2->OCR, pstcCmpInit->u8OutPolarity); + } + else + { + /* Stop CMP3 CMP4 compare */ + CLEAR_REG8_BIT(M4_CMP3->MDR, CMP_MDR_CENB); + CLEAR_REG8_BIT(M4_CMP4->MDR, CMP_MDR_CENB); + /* Set compare voltage */ + WRITE_REG8(M4_CMP3->PMSR, pstcCmpWinRef->u8CmpCh1); + WRITE_REG8(M4_CMP3->VISR, pstcCmpWinRef->u16CmpVol); + WRITE_REG8(M4_CMP4->PMSR, pstcCmpWinRef->u8CmpCh2); + /* Set reference Voltage */ + MODIFY_REG8(M4_CMP3->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolLow); + MODIFY_REG8(M4_CMP4->PMSR, CMP_PMSR_RVSL, pstcCmpWinRef->u8WinVolHigh); + /* Select window compare mode */ + SET_REG8_BIT(M4_CMP4->MDR, CMP_MDR_CWDE); + /* Start CMP compare function */ + SET_REG8_BIT(M4_CMP3->MDR, CMP_MDR_CENB); + SET_REG8_BIT(M4_CMP4->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + DDL_DelayUS(1U); + /* Set output filter and output detect edge and output polarity */ + WRITE_REG8(M4_CMP4->FIR, pstcCmpInit->u8OutFilter | pstcCmpInit->u8OutDetectEdges); + WRITE_REG8(M4_CMP4->OCR, pstcCmpInit->u8OutPolarity); + } + enRet = Ok; + } + return enRet; +} + +/** + * @brief Voltage compare function command + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] enNewStatus The function new status. + * This parameter can be: Enable or Disable. + * @retval None + */ +void CMP_FuncCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus) +{ + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus)); + + if(Enable == enNewStatus) + { + SET_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Delay 1us*/ + DDL_DelayUS(1U); + } + else + { + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + } +} + +/** + * @brief Voltage compare interrupt function command + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] enNewStatus The function new status. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void CMP_IntCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus)); + if(Enable == enNewStatus) + { + SET_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN); + } + else + { + CLEAR_REG8_BIT(CMPx->FIR, CMP_FIR_CIEN); + } +} + +/** + * @brief Voltage compare output command + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] enNewStatus The function new status. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void CMP_OutputCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus)); + if(Enable == enNewStatus) + { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_COEN); + } + else + { + CLEAR_REG8_BIT(CMPx->OCR, CMP_OCR_COEN); + } +} + +/** + * @brief Voltage compare output port VCOUT function command + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] enNewStatus The function new status. + * This parameter can be: Enable or Disable. + * @retval None + */ +void CMP_VCOUTCmd(M4_CMP_TypeDef *CMPx, en_functional_state_t enNewStatus) +{ + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus)); + if(Enable == enNewStatus) + { + SET_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE); + } + else + { + CLEAR_REG8_BIT(CMPx->OCR, CMP_OCR_CPOE); + } +} + +/** + * @brief Voltage compare result flag read + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @retval In normal mode: + * Reset: compare voltage < reference voltage + * Set: compare voltage > reference voltage + * In Window mode: + * Reset: compare voltage < reference low voltage or + * compare voltage > reference high voltage + * Set: reference low voltage < compare voltage < reference high voltage + */ +en_flag_status_t CMP_GetResult(const M4_CMP_TypeDef *CMPx) +{ + en_flag_status_t enRet; + /* Check CMPx instance */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + enRet = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CMON) ? Set : Reset; + return enRet; +} + +/** + * @brief Voltage compare timer window function configuration + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] pstcCMP_TimerWinStruct Configuration structure for Timer window mode. + * @retval Ok: Successfully + * ErrorInvalidParameter: Parameter error + */ +en_result_t CMP_TimerWindowConfig(M4_CMP_TypeDef *CMPx, + const stc_cmp_timerwindow_t *pstcCMP_TimerWinStruct) +{ + en_result_t enRet = ErrorInvalidParameter; + /* Check CMPx instance and configuration structure*/ + if (NULL != pstcCMP_TimerWinStruct) + { + enRet = Ok; + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_TIMWIN_INVALIDLEVEL(pstcCMP_TimerWinStruct->u8TWInvalidLevel)); + DDL_ASSERT(IS_CMP_TIMWIN_OUT_LEVEL(pstcCMP_TimerWinStruct->u8TWOutLevel)); + /* Select timer window mode */ + SET_REG8_BIT(CMPx->OCR, CMP_OCR_TWOE); + /* Select output level when timer window invalid */ + MODIFY_REG8(CMPx->OCR, CMP_OCR_TWOL, pstcCMP_TimerWinStruct->u8TWInvalidLevel); + /* Select Timer window source */ + WRITE_REG16(CMPx->TWSR, pstcCMP_TimerWinStruct->u16TWSelect); + /* Select timer window mode output level */ + if(CMP_TIMERWIN_OUT_LEVEL_HIGH == pstcCMP_TimerWinStruct->u8TWOutLevel) + { + SET_REG16_BIT(CMPx->TWPR, pstcCMP_TimerWinStruct->u16TWSelect); + } + else + { + CLEAR_REG16_BIT(CMPx->TWPR, pstcCMP_TimerWinStruct->u16TWSelect); + } + } + return enRet; +} + +/** + * @brief Set output detect edge + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] u8CmpEdges CMP output detect edge selection. + * This parameter can be one of the following values: + * @arg CMP_DETECT_EDGS_NONE: Do not detect edge + * @arg CMP_DETECT_EDGS_RISING: Detect rising edge + * @arg CMP_DETECT_EDGS_FALLING: Detect falling edge + * @arg CMP_DETECT_EDGS_BOTH: Detect rising and falling edges + * @retval None + */ +void CMP_SetOutDetectEdges(M4_CMP_TypeDef *CMPx, uint8_t u8CmpEdges) +{ + uint8_t u8temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_OUT_DETECT_EDGE(u8CmpEdges)); + /* Read CMP status */ + u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* CMP output detect edge selection */ + MODIFY_REG8(CMPx->FIR, CMP_FIR_EDGS, u8CmpEdges); + if(u8temp != 0U) + { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp); + /* Delay 1us */ + DDL_DelayUS(1U); + } +} + +/** + * @brief Set output filter + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] u8CmpFilter CMP output filter selection. + * This parameter can be one of the following values: + * @arg CMP_OUT_FILTER_NONE: Don't filter + * @arg CMP_OUT_FILTER_PCLK3: Use PCLK3 + * @arg CMP_OUT_FILTER_PCLK3_DIV8: Use PCLK3 / 8 + * @arg CMP_OUT_FILTER_PCLK3_DIV32: Use PCLK3 / 32 + * @retval None + */ +void CMP_SetOutputFilter(M4_CMP_TypeDef *CMPx, uint8_t u8CmpFilter) +{ + uint8_t u8temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_OUT_FILTER(u8CmpFilter)); + /* Read CMP status */ + u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* CMP output filter selection */ + MODIFY_REG8(CMPx->FIR, CMP_FIR_FCKS, u8CmpFilter); + if(u8temp != 0U) + { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp); + /* Delay 1us */ + DDL_DelayUS(1U); + } +} + +/** + * @brief Set output polarity + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] u8CmpPolarity CMP output polarity selection. + * This parameter can be one of the following values: + * @arg CMP_OUT_REVERSE_OFF: CMP output don't reverse + * @arg CMP_OUT_REVERSE_ON: CMP output level reverse + * @retval None + */ +void CMP_SetOutputPolarity(M4_CMP_TypeDef *CMPx, uint8_t u8CmpPolarity) +{ + uint8_t u8temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_OUT_POLARITY(u8CmpPolarity)); + /* Read CMP status */ + u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* CMP output polarity selection */ + MODIFY_REG8(CMPx->OCR, CMP_OCR_COPS, u8CmpPolarity); + if(u8temp != 0U) + { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp); + /* Delay 1us */ + DDL_DelayUS(1U); + } +} + +/** + * @brief Set compare voltage + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] u8CmpCh Select the compare voltage. + * This parameter can be one of the following values: + * @arg CMP_CVSL_NONE: Don't input compare voltage + * @arg CMP_CVSL_INP1: Select INP1 as compare voltage + * @arg CMP_CVSL_INP2: Select INP2 as compare voltage + * @arg CMP_CVSL_INP3: Select INP3 as compare voltage + * @arg CMP_CVSL_INP4: Select INP4 as compare voltage + * @param [in] u8CmpVol Select the compare voltage source (Config the parameter when use CMP1 or CMP3) + * This parameter can be one of the following values: + * When use CMP1: + * @arg CMP1_INP3_NONE: Don't input voltage to CMP1 INP3 + * @arg CMP1_INP3_CMP1_INP3: Select CMP1_INP3 as CMP1 INP3 input + * @arg CMP1_INP3_CMP2_INP3: Select CMP2_INP3 as CMP1 INP3 input + * @arg CMP1_INP2_NONE: Don't input voltage to CMP1 INP2 + * @arg CMP1_INP2_PGA1: Select PGA1 as CMP1 INP2 input + * @arg CMP1_INP2_PGA2: Select PGA2 as CMP1 INP2 input + * @arg CMP1_INP2_CMP1_INP2: Select CMP1_INP2 as CMP1 INP2 input + * When use CMP3: + * @arg CMP3_INP3_NONE: Don't input voltage to CMP3 INP3 + * @arg CMP3_INP3_CMP3_INP3: Select CMP3_INP3 as CMP3 INP3 input + * @arg CMP3_INP3_CMP4_INP3: Select CMP4_INP3 as CMP3 INP3 input + * @arg CMP3_INP2_NONE: Don't input voltage to CMP3 INP2 + * @arg CMP3_INP2_PGA3: Select PGA3 as CMP3 INP2 input + * @arg CMP3_INP2_PGA4: Select PGA4 as CMP3 INP2 input + * @arg CMP3_INP2_CMP3_INP2: Select CMP3_INP2 as CMp3 INP2 input + * @retval None + * @note When use INP1 or INP4, please set u8CmpVol to 0 + */ +void CMP_SetCompareVol(M4_CMP_TypeDef *CMPx, uint8_t u8CmpCh, uint8_t u8CmpVol) +{ + uint8_t u8temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_CVSL_CH(u8CmpCh)); + /* Read CMP status */ + u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Set compare voltage */ + MODIFY_REG8(CMPx->PMSR, CMP_PMSR_CVSL, u8CmpCh); + if((M4_CMP1 == CMPx) && ((u8CmpCh == CMP_CVSL_INP2) || (u8CmpCh == CMP_CVSL_INP3))) + { + DDL_ASSERT(IS_CMP1_CVSL_SOURCE(u8CmpVol)); + WRITE_REG8(CMPx->VISR, u8CmpVol); + } + if((M4_CMP3 == CMPx) && ((u8CmpCh == CMP_CVSL_INP2) || (u8CmpCh == CMP_CVSL_INP3))) + { + DDL_ASSERT(IS_CMP3_CVSL_SOURCE(u8CmpVol)); + WRITE_REG8(CMPx->VISR, u8CmpVol); + } + if(u8temp != 0U) + { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp); + /* Delay 1us */ + DDL_DelayUS(1U); + } +} + +/** + * @brief Set reference voltage + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] u8RefVol Select the reference voltage. + * This parameter can be one of the following values: + * @arg CMP_RVSL_NONE: Don't input reference voltage + * @arg CMP_RVSL_INM1: Select INM1 as reference voltage + * @arg CMP_RVSL_INM2: Select INM2 as reference voltage + * @arg CMP_RVSL_INM3: Select INM3 as reference voltage + * @arg CMP_RVSL_INM4: Select INM4 as reference voltage + * @retval None + */ +void CMP_SetRefVol(M4_CMP_TypeDef *CMPx, uint8_t u8RefVol) +{ + uint8_t u8temp; + /* Check parameters */ + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + DDL_ASSERT(IS_CMP_RVSL(u8RefVol)); + /* Read CMP status */ + u8temp = READ_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Stop CMP function */ + CLEAR_REG8_BIT(CMPx->MDR, CMP_MDR_CENB); + /* Set reference voltage */ + MODIFY_REG8(CMPx->PMSR, CMP_PMSR_RVSL, u8RefVol); + if(u8temp != 0U) + { + /* Recover CMP status */ + MODIFY_REG8(CMPx->MDR, CMP_MDR_CENB, u8temp); + /* Delay 1us */ + DDL_DelayUS(1U); + } +} + +/** + * @brief Ste CMP Timer window signal. + * @param [in] CMPx Pointer to CMP instance register base + * This parameter can be one of the following values: + * @arg M4_CMP1: CMP unit 1 instance register base + * @arg M4_CMP2: CMP unit 2 instance register base + * @arg M4_CMP3: CMP unit 3 instance register base + * @arg M4_CMP4: CMP unit 4 instance register base + * @param [in] u16TWSignal Selection timer window signal + * This parameter can be value of @ref CMP_TimerWin_Select + * @param [in] enNewStatus The function new status. + * This parameter can be: Enable or Disable. + * @retval None + */ +void CMP_SetTimerWinSignal(M4_CMP_TypeDef *CMPx, \ + uint16_t u16TWSignal, en_functional_state_t enNewStatus) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewStatus)); + DDL_ASSERT(IS_CMP_INSTANCE(CMPx)); + if (enNewStatus == Enable) + { + MODIFY_REG16(CMPx->TWSR, u16TWSignal, u16TWSignal); + } + else + { + CLEAR_REG16_BIT(CMPx->TWSR, u16TWSignal); + } +} + +/** + * @} + */ + +#endif /* DDL_CMP_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_crc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_crc.c new file mode 100644 index 0000000000000000000000000000000000000000..38939a6bb599d745baf78fcdcbbc00b43fb46e58 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_crc.c @@ -0,0 +1,317 @@ +/** + ******************************************************************************* + * @file hc32f4a0_crc.c + * @brief This file provides firmware functions to manage the Cyclic Redundancy + * Check(CRC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + 2020-07-21 Heqb Fixed a bug for CRC_Check function + 2020-08-11 Heqb Modify macro definition name IS_CRC_PROCOTOL + to IS_CRC_PROTOCOL + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_crc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_CRC CRC + * @brief Cyclic Redundancy Check Driver Library + * @{ + */ + +#if (DDL_CRC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Macros CRC Local Macros + * @{ + */ + +/** + * @defgroup CRC_Check_Parameters_Validity CRC check parameters validity + * @{ + */ +#define IS_CRC_PROTOCOL(x) \ +( ((x) == CRC_CRC16) || \ + ((x) == CRC_CRC32)) + +#define IS_CRC_BIT_WIDTH(x) \ +( ((x) == CRC_BW_8) || \ + ((x) == CRC_BW_16) || \ + ((x) == CRC_BW_32)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup CRC_Local_Functions CRC Local Functions + * @{ + */ +static void CRC_8BitWrite(const uint8_t au8Data[], uint32_t u32Length); +static void CRC_16BitWrite(const uint16_t au16Data[], uint32_t u32Length); +static void CRC_32BitWrite(const uint32_t au32Data[], uint32_t u32Length); +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CRC_Global_Functions CRC Global Functions + * @{ + */ + +/** + * @brief CRC16 calculation. + * @param [in] u32CrcProtocol CRC protocol control bit. + * This parameter can be a value of @ref CRC_Protocol_Control_Bit + * @param [in] pvData Pointer to the buffer containing the data to be computed. + * @param [in] u32InitVal Initialize the CRC calculation. + * @param [in] u32Length The length(countted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @param [in] u8BitWidth Bit width of the data. + * @arg CRC_BW_8: 8 Bit. + * @arg CRC_BW_16: 16 Bit. + * @arg CRC_BW_32: 32 Bit. + * @retval CRC checksum. + */ +uint32_t CRC_Calculate(uint32_t u32CrcProtocol, + const void *pvData, + uint32_t u32InitVal, + uint32_t u32Length, + uint8_t u8BitWidth) +{ + uint32_t u32CheckSum = 0UL; + + if ((pvData != NULL) && (u32Length != 0U)) + { + DDL_ASSERT(IS_CRC_PROTOCOL(u32CrcProtocol)); + DDL_ASSERT(IS_CRC_BIT_WIDTH(u8BitWidth)); + /* Set operation mode (CRC16 or CRC32) */ + WRITE_REG32(M4_CRC->CR, u32CrcProtocol); + /* Set initial value */ + if (u32CrcProtocol == CRC_CRC32) + { + WRITE_REG32(M4_CRC->RESLT, u32InitVal); + } + else + { + WRITE_REG16(M4_CRC->RESLT, u32InitVal); + } + /* Write data */ + if (u8BitWidth == CRC_BW_8) + { + CRC_8BitWrite(pvData, u32Length); + } + else if (u8BitWidth == CRC_BW_16) + { + CRC_16BitWrite(pvData, u32Length); + } + else + { + CRC_32BitWrite(pvData, u32Length); + } + /* Get checksum */ + if (u32CrcProtocol == CRC_CRC32) + { + u32CheckSum = READ_REG32(M4_CRC->RESLT); + } + else + { + u32CheckSum = READ_REG16(M4_CRC->RESLT); + } + } + return u32CheckSum; +} + +/** + * @brief CRC check. + * @param [in] u32CrcProtocol CRC protocol control bit. + * This parameter can be a value of @ref CRC_Protocol_Control_Bit + * @param [in] u32CheckSum The checksum of the data pointed by pointer pvData. + * @param [in] pvData Pointer to the buffer containing the data to be checked. + * @param [in] u32InitVal Initialize the CRC calculation. + * @param [in] u32Length The length(countted in bytes or half word or word, depending on + * the bit width) of the data to be computed. + * @param [in] u8BitWidth Bit width of the data. + * @arg CRC_BW_8: 8 Bit. + * @arg CRC_BW_16: 16 Bit. + * @arg CRC_BW_32: 32 Bit. + * @retval A en_flag_status_t value. + * @arg Set: CRC checks successfully. + * @arg Reset: CRC checks unsuccessfully. + */ +en_flag_status_t CRC_Check(uint32_t u32CrcProtocol, + uint32_t u32CheckSum, + const void *pvData, + uint32_t u32InitVal, + uint32_t u32Length, + uint8_t u8BitWidth) +{ + en_flag_status_t enFlag = Reset; + uint32_t u32DataAddr = (uint32_t)&M4_CRC->DAT0; + DDL_ASSERT(IS_CRC_PROTOCOL(u32CrcProtocol)); + DDL_ASSERT(IS_CRC_BIT_WIDTH(u8BitWidth)); + if ((pvData != NULL) && (u32Length != 0UL)) + { + /* Set operation mode (CRC16 or CRC32) */ + WRITE_REG32(M4_CRC->CR, u32CrcProtocol); + /* Set initial value */ + if (u32CrcProtocol == CRC_CRC32) + { + WRITE_REG32(M4_CRC->RESLT, u32InitVal); + } + else + { + WRITE_REG16(M4_CRC->RESLT, u32InitVal); + } + /* Write data */ + if (u8BitWidth == CRC_BW_8) + { + CRC_8BitWrite(pvData, u32Length); + } + else if (u8BitWidth == CRC_BW_16) + { + CRC_16BitWrite(pvData, u32Length); + } + else + { + CRC_32BitWrite(pvData, u32Length); + } + /* Write checksum */ + if (u32CrcProtocol == CRC_CRC32) + { + RW_MEM32(u32DataAddr) = u32CheckSum; + } + else + { + + RW_MEM16(u32DataAddr) = (uint16_t)u32CheckSum; + } + /* Get flag */ + if (READ_REG32_BIT(M4_CRC->CR, CRC_CR_FLAG) != 0UL) + { + enFlag = Set; + } + } + return enFlag; +} + +/** + * @} + */ + +/** + * @addtogroup CRC_Local_Functions CRC Local Functions + * @{ + */ + +/** + * @brief Write CRC data register in bytes. + * @param [in] au8Data The buffer for writing. + * @param [in] u32Length The length of data the in bytes. + * @retval None + */ +static void CRC_8BitWrite(const uint8_t au8Data[], uint32_t u32Length) +{ + uint32_t i; + const uint32_t u32DataAddr = (uint32_t)(&M4_CRC->DAT0); + for (i = 0UL; i < u32Length; i++) + { + RW_MEM8(u32DataAddr) = au8Data[i]; + + } +} + +/** + * @brief Write CRC data register in half words. + * @param [in] au16Data The buffer for writing. + * @param [in] u32Length The length of the data in half words. + * @retval None + */ +static void CRC_16BitWrite(const uint16_t au16Data[], uint32_t u32Length) +{ + uint32_t i; + const uint32_t u32DataAddr = (uint32_t)(&M4_CRC->DAT0); + for (i = 0UL; i < u32Length; i++) + { + RW_MEM16(u32DataAddr) = au16Data[i]; + } +} + +/** + * @brief Write CRC data register in words. + * @param [in] au32Data The buffer for writing. + * @param [in] u32Length The length of the data in words. + * @retval None + */ +static void CRC_32BitWrite(const uint32_t au32Data[], uint32_t u32Length) +{ + uint32_t i; + const uint32_t u32DataAddr = (uint32_t)(&M4_CRC->DAT0); + for (i = 0UL; i < u32Length; i++) + { + RW_MEM32(u32DataAddr) = au32Data[i]; + } +} + +/** + * @} + */ + +#endif /* DDL_CRC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_ctc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_ctc.c new file mode 100644 index 0000000000000000000000000000000000000000..ff6fe6e001f60efe4eee71976798f1f694d43298 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_ctc.c @@ -0,0 +1,399 @@ +/** + ******************************************************************************* + * @file hc32f4a0_ctc.c + * @brief This file provides firmware functions to manage the Clock Trimming + * Controller(CTC). + @verbatim + Change Logs: + Date Author Notes + 2020-09-01 Hongjh First version + 2020-10-30 Hongjh Modify for refining CTC initialization structure + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_ctc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_CTC CTC + * @brief CTC Driver Library + * @{ + */ + +#if (DDL_CTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup CTC_Local_Macros CTC Local Macros + * @{ + */ + +/** + * @defgroup CTC_Check_Parameters_Validity CTC Check Parameters Validity + * @{ + */ + +#define IS_CTC_REF_CLK_SRC(x) \ +( ((x) == CTC_REF_CLK_XTAL) || \ + ((x) == CTC_REF_CLK_XTAL32) || \ + ((x) == CTC_REF_CLK_CTCREF)) + +#define IS_CTC_REF_CLK_DIV(x) \ +( ((x) == CTC_REF_CLK_DIV8) || \ + ((x) == CTC_REF_CLK_DIV32) || \ + ((x) == CTC_REF_CLK_DIV128) || \ + ((x) == CTC_REF_CLK_DIV256) || \ + ((x) == CTC_REF_CLK_DIV512) || \ + ((x) == CTC_REF_CLK_DIV1024) || \ + ((x) == CTC_REF_CLK_DIV2048) || \ + ((x) == CTC_REF_CLK_DIV4096)) + +#define IS_CTC_OFFSET_VALUE(x) ((x) <= 0xFFUL) + +#define IS_CTC_RELOAD_VALUE(x) ((x) <= 0xFFFFUL) + +#define IS_CTC_TRIM_VALUE(x) ((x) <= 0x3FUL) + +#define IS_CTC_TOLERANCE_DEVIATION(x) (((x) >= 0.0F) && \ + ((x) <= CTC_TOLERANCE_DEVIATION_MAX)) + +#define IS_CTC_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | CTC_FLAG_ALL) == CTC_FLAG_ALL)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup CTC_Global_Functions CTC Global Functions + * @{ + */ + +/** + * @brief Initialize CTC function. + * @param [in] pstcCtcInit Pointer to a @ref stc_ctc_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorNotReady: CTC state is busy + * - ErrorInvalidParameter: If one of following cases matches: + * - pstcCtcInit is NULL + * - Reference frequency is out of range + * - Calculate reload & offset value out of range + */ +en_result_t CTC_Init(const stc_ctc_init_t *pstcCtcInit) +{ + float f32OffsetValue; + uint32_t u32RegValue; + uint32_t u32ReloadValue; + uint32_t u32OffsetValue; + uint32_t u32RefClockDiv; + uint32_t u32Multiplier; + uint64_t u64InterClock; + uint32_t u32HrcFreq = HRC_VALUE; + en_result_t enRet = ErrorNotReady; + + /* Check CTC status */ + if (CTC_FLAG_BUSY != (READ_REG32_BIT(M4_CTC->STR, CTC_FLAG_BUSY))) + { + if ((NULL == pstcCtcInit) || (0UL == pstcCtcInit->u32RefClockFreq)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_CTC_REF_CLK_SRC(pstcCtcInit->u32RefClockSrc)); + DDL_ASSERT(IS_CTC_REF_CLK_DIV(pstcCtcInit->u32RefClockDiv)); + DDL_ASSERT(IS_CTC_TRIM_VALUE(pstcCtcInit->u32TrimValue)); + DDL_ASSERT(IS_CTC_TOLERANCE_DEVIATION(pstcCtcInit->f32ToleranceDeviation)); + + if (pstcCtcInit->u32RefClockDiv < CTC_REF_CLK_DIV128) + { + u32RefClockDiv = (8UL << (2UL * pstcCtcInit->u32RefClockDiv)); + } + else + { + u32RefClockDiv = (32UL << pstcCtcInit->u32RefClockDiv); + } + u64InterClock = ((uint64_t)u32HrcFreq) * ((uint64_t)(u32RefClockDiv)); + u32Multiplier = (uint32_t)(u64InterClock / pstcCtcInit->u32RefClockFreq); + + /* Calculate offset value formula: OFSVAL = (Fhrc / (Fref * Fref_divsion)) * TA */ + f32OffsetValue = ((float)u32Multiplier) * (pstcCtcInit->f32ToleranceDeviation); + u32OffsetValue = (uint32_t)(f32OffsetValue); + + /* Calculate reload value formula: RLDVAL = (Fhrc / (Fref * Fref_divsion)) + OFSVAL */ + u32ReloadValue = u32Multiplier + u32OffsetValue; + + if ((IS_CTC_OFFSET_VALUE(u32OffsetValue)) && (IS_CTC_RELOAD_VALUE(u32ReloadValue))) + { + /* Set CR1 */ + u32RegValue = (pstcCtcInit->u32RefClockDiv | \ + pstcCtcInit->u32RefClockSrc | \ + (pstcCtcInit->u32TrimValue << CTC_CR1_TRMVAL_POS)); + WRITE_REG32(M4_CTC->CR1, u32RegValue); + + /* Set CR2 */ + u32RegValue = ((u32ReloadValue << CTC_CR2_RLDVAL_POS) | u32OffsetValue); + WRITE_REG32(M4_CTC->CR2, u32RegValue); + enRet = Ok; + } + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_uart_init_t to default values. + * @param [out] pstcCtcInit Pointer to a @ref stc_ctc_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: pstcCtcInit is NULL + */ +en_result_t CTC_StructInit(stc_ctc_init_t *pstcCtcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if (NULL != pstcCtcInit) + { + pstcCtcInit->u32RefClockFreq = 0UL; + pstcCtcInit->u32RefClockSrc = CTC_REF_CLK_CTCREF; + pstcCtcInit->u32RefClockDiv = CTC_REF_CLK_DIV8; + pstcCtcInit->f32ToleranceDeviation = 0.0F; + pstcCtcInit->u32TrimValue = 0UL; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize CTC function. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: De-Initialize success + * - ErrorNotReady: CTC state is busy + */ +en_result_t CTC_DeInit(void) +{ + en_result_t enRet = ErrorNotReady; + + /* Check CTC status */ + if (CTC_FLAG_BUSY != (READ_REG32_BIT(M4_CTC->STR, CTC_FLAG_BUSY))) + { + /* Configures the registers to reset value. */ + WRITE_REG32(M4_CTC->CR1, 0UL); + WRITE_REG32(M4_CTC->CR2, 0UL); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set CTC reference clock division. + * @param [in] u32Div CTC reference clock prescaler + * This parameter can be one of the following values: + * @arg CTC_REF_CLK_DIV8: REFCLK/8 + * @arg CTC_REF_CLK_DIV32: REFCLK/32 + * @arg CTC_REF_CLK_DIV128: REFCLK/128 + * @arg CTC_REF_CLK_DIV256: REFCLK/256 + * @arg CTC_REF_CLK_DIV512: REFCLK/512 + * @arg CTC_REF_CLK_DIV1024: REFCLK/1024 + * @arg CTC_REF_CLK_DIV2048: REFCLK/2048 + * @arg CTC_REF_CLK_DIV4096: REFCLK/4096 + * @retval None + */ +void CTC_SetRefClockDiv(uint32_t u32Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_CTC_REF_CLK_DIV(u32Div)); + + MODIFY_REG32(M4_CTC->CR1, CTC_CR1_REFPSC, u32Div); +} + +/** + * @brief Set CTC reference clock source. + * @param [in] u32ClockSrc CTC reference clock source + * This parameter can be one of the following values: + * @arg CTC_REF_CLK_CTCREF: Clock source CTCREF + * @arg CTC_REF_CLK_XTAL: Clock source XTAL + * @retval None + */ +void CTC_SetRefClockSrc(uint32_t u32ClockSrc) +{ + /* Check parameters */ + DDL_ASSERT(IS_CTC_REF_CLK_SRC(u32ClockSrc)); + + MODIFY_REG32(M4_CTC->CR1, CTC_CR1_REFCKS, u32ClockSrc); +} + +/** + * @brief Enable or disable CTC error interrupt function. + * @param [in] enNewState The function new state. + * This parameter can be one of the following values: + * @arg Enable: Enable CTC error interrupt function. + * @arg Disable: Disable CTC error interrupt function. + * @retval None + */ +void CTC_IntCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_CTC->CR1_b.ERRIE, enNewState); +} + +/** + * @brief Get CTC flag. + * @param [in] u32Flag CTC flag + * This parameter can be any composed value of the following values:: + * @arg CTC_FLAG_TRIM_OK: Trimming OK flag + * @arg CTC_FLAG_TRIM_OVF: Trimming overflow flag + * @arg CTC_FLAG_TRIM_UDF: Trimming underflow flag + * @arg CTC_FLAG_BUSY: CTC busy flag + * @retval Returned value can be one of the following values: + * - Set: Any bit of the composed flag is set. + * - Reset: All bit of the composed flag is reset. + */ +en_flag_status_t CTC_GetStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_CTC_FLAG(u32Flag)); + + return ((0UL == READ_REG32_BIT(M4_CTC->STR, u32Flag)) ? Reset : Set); +} + +/** + * @brief Set CTC trimming value. + * @param [in] u32TrimValue CTC trimming value + * This parameter can be min=0 && max=0x3F + * @retval None + */ +void CTC_SetTrimValue(uint32_t u32TrimValue) +{ + /* Check parameters */ + DDL_ASSERT(IS_CTC_TRIM_VALUE(u32TrimValue)); + + MODIFY_REG32(M4_CTC->CR1, CTC_CR1_TRMVAL, (u32TrimValue << CTC_CR1_TRMVAL_POS)); +} + +/** + * @brief Get CTC trimming value. + * @param None + * @retval CTC trimming value(between Min_Data=0 and Max_Data=0x3F) + */ +uint32_t CTC_GetTrimValue(void) +{ + return (READ_REG32_BIT(M4_CTC->CR1, CTC_CR1_TRMVAL) >> CTC_CR1_TRMVAL_POS); +} + +/** + * @brief Set CTC reload value. + * @param [in] u32ReloadValue CTC reload value + * This parameter can be between Min_Data=0 and Max_Data=0xFFFF + * @retval None + */ +void CTC_SetReloadValue(uint32_t u32ReloadValue) +{ + /* Check parameters */ + DDL_ASSERT(IS_CTC_RELOAD_VALUE(u32ReloadValue)); + + MODIFY_REG32(M4_CTC->CR2, CTC_CR2_RLDVAL, (u32ReloadValue << CTC_CR2_RLDVAL_POS)); +} + +/** + * @brief Get CTC reload value. + * @param None + * @retval CTC reload value (between Min_Data=0 and Max_Data=0xFFFF) + */ +uint16_t CTC_GetReloadValue(void) +{ + return (uint16_t)(READ_REG32_BIT(M4_CTC->CR2, CTC_CR2_RLDVAL) >> CTC_CR2_RLDVAL_POS); +} + +/** + * @brief Set CTC offset value. + * @param [in] u32OffsetValue CTC offset value + * This parameter can be between Min_Data=0 and Max_Data=0xFF + * @retval None + */ +void CTC_SetOffsetValue(uint32_t u32OffsetValue) +{ + /* Check parameters */ + DDL_ASSERT(IS_CTC_OFFSET_VALUE(u32OffsetValue)); + + MODIFY_REG32(M4_CTC->CR2, CTC_CR2_OFSVAL, (u32OffsetValue << CTC_CR2_OFSVAL_POS)); +} + +/** + * @brief Get CTC offset value. + * @param None + * @retval CTC offset value (between Min_Data=0 and Max_Data=0xFF) + */ +uint32_t CTC_GetOffsetValue(void) +{ + return (READ_REG32_BIT(M4_CTC->CR2, CTC_CR2_OFSVAL) >> CTC_CR2_OFSVAL_POS); +} + +/** + * @} + */ + +#endif /* DDL_CTC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dac.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dac.c new file mode 100644 index 0000000000000000000000000000000000000000..138a429b84ce03d3721e6e8066fcc3c484d5f2ad --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dac.c @@ -0,0 +1,636 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dac.c + * @brief This file provides firmware functions to manage the Digital-to-Analog + * Converter(DAC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hexiao First version + 2020-07-15 Hexiao 1. Modify DAC_ChannelCmd to DAC_Start and DAC_Stop + 2. Modify DAC_DualChannelCmd to DAC_DualChannelStart + and DAC_DualChannelStop + 2020-08-31 Hexiao Refine DAC_AMPCmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_dac.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_DAC DAC + * @brief DAC Driver Library + * @{ + */ + +#if (DDL_DAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DAC_Local_Macros DAC Local Macros + * @{ + */ +#define DAC_ADP_SELECT_ALL (DAC_DAADPCR_ADPSL1 | DAC_DAADPCR_ADPSL2 | DAC_DAADPCR_ADPSL3) + +/** + * @defgroup DAC_Check_Parameters_Validity DAC Check Parameters Validity + * @{ + */ + +#define IS_VALID_UNIT(x) \ +( ((x) == M4_DAC1) || \ + ((x) == M4_DAC2)) + +#define IS_VALID_CH(x) \ +( ((x) == DAC_CH_1) || \ + ((x) == DAC_CH_2)) + +#define IS_VALID_DATA_ALIGN(x) \ +( ((x) == DAC_DATA_ALIGN_L) || \ + ((x) == DAC_DATA_ALIGN_R)) + +#define IS_VALID_DATA_SRC(x) \ +( ((x) == DAC_DATA_SRC_DATAREG) || \ + ((x) == DAC_DATA_SRC_DCU)) + +#define IS_VALID_ADCPRIO_CONFIG(x) \ +( (0U != (x)) && \ + (DAC_ADP_SELECT_ALL == ((x) | DAC_ADP_SELECT_ALL))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup DAC_Global_Functions DAC Global Functions + * @{ + */ + +/** + * @brief Set DAC data source for specified channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Ch Specify the DAC channel @ref DAC_CH. + * This parameter can be one of the following values: + * @arg DAC_CH_1 + * @arg DAC_CH_2 + * @param [in] u16Src Specify the data source. + * This parameter can be a value of @ref DAC_DATA_SRC + * - DAC_DATA_SRC_DATAREG: convert source is from data register + * - DAC_DATA_SRC_DCU: convert source is from DCU + * @retval None + */ +void DAC_SetDataSource(M4_DAC_TypeDef *DACx, uint16_t u16Ch, uint16_t u16Src) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_VALID_DATA_SRC(u16Src)); + + SET_REG16_BIT(DACx->DACR, u16Src << (DAC_DACR_EXTDSL1_POS + u16Ch)); +} + +/** + * @brief DAC data register's data alignment pattern configuration + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Align Specify the data alignment. + * This parameter can be a value of @ref DAC_DATAREG_ALIGN_PATTERN + * - DAC_DATA_ALIGN_L: left alignment + * - DAC_DATA_ALIGN_R: right alignment + * @retval None + */ +void DAC_DataRegAlignConfig(M4_DAC_TypeDef *DACx, uint16_t u16Align) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_DATA_ALIGN(u16Align)); + + SET_REG16_BIT(DACx->DACR, u16Align); +} + +/** + * @brief DAC output function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be one of the following values: + * @arg DAC_CH_1 + * @arg DAC_CH_2 + * @param [in] enNewState New state of the DAC output function, + * @ref en_functional_state_t + * @retval None + */ +void DAC_OutputCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + const uint16_t u16Cmd = (uint16_t)1U << (DAC_DAOCR_DAODIS1_POS + u16Ch); + + if(Enable == enNewState) + { + CLEAR_REG16_BIT(DACx->DAOCR, u16Cmd); + } + else + { + SET_REG16_BIT(DACx->DAOCR, u16Cmd); + } +} + +/** + * @brief DAC AMP function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be one of the following values: + * @arg DAC_CH_1 + * @arg DAC_CH_2 + * @param [in] enNewState New state of the AMP function, + * @ref en_functional_state_t + * @retval An en_result_t enumeration value: + * - Ok: No errors occurred + * - ErrorInvalidMode: cannot enable AMP when data source is from DCU + */ +en_result_t DAC_AMPCmd(M4_DAC_TypeDef *DACx, uint16_t u16Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + en_result_t ret = Ok; + uint16_t u16Cmd = (uint16_t)1U << (DAC_DACR_EXTDSL1_POS + u16Ch); + + if((0U != (READ_REG16_BIT(DACx->DACR, u16Cmd))) && (Enable == enNewState)) + { + ret = ErrorInvalidMode; + } + else + { + u16Cmd = (uint16_t)1U << (DAC_DACR_DAAMP1_POS + u16Ch); + + if(Enable == enNewState) + { + SET_REG16_BIT(DACx->DACR, u16Cmd); + } + else + { + CLEAR_REG16_BIT(DACx->DACR, u16Cmd); + } + } + + return ret; +} + +/** + * @brief DAC ADC priority function command + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] enNewState New state of the ADC priority function, + * @ref en_functional_state_t + * @retval None + * @note please make sure ADC is in stoped status before calling DAC_ADCPrioCmd + */ +void DAC_ADCPrioCmd(M4_DAC_TypeDef *DACx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN); + } + else + { + CLEAR_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN); + } +} + +/** + * @brief Enable or Disable the ADP priority for the selected ADCx + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16ADCxPrio ADCx priority to be enabled or disabled. + * This parameter can be one or any combination of the following values: + * @arg DAC_ADP_SELECT_ADC1 + * @arg DAC_ADP_SELECT_ADC2 + * @arg DAC_ADP_SELECT_ADC3 + * @param [in] enNewState New state of ADCx priority + * @ref en_functional_state_t + * @retval None + * @note please make sure ADC is in stoped status before calling DAC_ADCPrioConfig + */ +void DAC_ADCPrioConfig(M4_DAC_TypeDef *DACx, uint16_t u16ADCxPrio, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_ADCPRIO_CONFIG(u16ADCxPrio)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG16_BIT(DACx->DAADPCR, u16ADCxPrio); + } + else + { + CLEAR_REG16_BIT(DACx->DAADPCR, u16ADCxPrio); + } +} + +/** + * @brief Start the specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be one of the following values: + * @arg DAC_CH_1 + * @arg DAC_CH_2 + * @retval An en_result_t enumeration value: + * - Ok: No errors occurred + * - ErrorInvalidMode: cannot start single channel when \n + * this channel have already been started by \n + * @ref DAC_DualChannelStart + */ +en_result_t DAC_Start(M4_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if((DACx->DACR & DAC_DACR_DAE) != 0U) + { + enRet = ErrorInvalidMode; + } + else + { + const uint16_t u16Cmd = (uint16_t)1U << (DAC_DACR_DA1E_POS + u16Ch); + SET_REG16_BIT(DACx->DACR, u16Cmd); + } + + return enRet; +} + +/** + * @brief Stop the specified DAC channel + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Ch Specify DAC channel @ref DAC_CH. + * This parameter can be one of the following values: + * @arg DAC_CH_1 + * @arg DAC_CH_2 + * @retval An en_result_t enumeration value: + * - Ok: No errors occurred + * - ErrorInvalidMode: cannot stop single channel when \n + * this channel is started by \n + * @ref DAC_DualChannelStart + */ +en_result_t DAC_Stop(M4_DAC_TypeDef *DACx, uint16_t u16Ch) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + if((DACx->DACR & DAC_DACR_DAE) != 0U) + { + enRet = ErrorInvalidMode; + } + else + { + const uint16_t u16Cmd = (uint16_t)1U << (DAC_DACR_DA1E_POS + u16Ch); + CLEAR_REG16_BIT(DACx->DACR, u16Cmd); + } + + return enRet; +} + +/** + * @brief Start DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @retval None + */ +void DAC_DualChannelStart(M4_DAC_TypeDef *DACx) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + SET_REG16_BIT(DACx->DACR, DAC_DACR_DAE); +} + +/** + * @brief Stop DAC channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @retval None + */ +void DAC_DualChannelStop(M4_DAC_TypeDef *DACx) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + CLEAR_REG16_BIT(DACx->DACR, DAC_DACR_DAE); +} + +/** + * @brief Set the specified data holding register value for DAC channel 1 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] data Data to be loaded into data holding register of channel 1 + * @retval None + */ +void DAC_SetChannel1Data(M4_DAC_TypeDef *DACx, uint16_t data) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if(READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_L) + { + DDL_ASSERT(0U == (data & 0xFU)); + } + else + { + DDL_ASSERT(0U == (data & 0xF000U)); + } + + WRITE_REG16(DACx->DADR1,data); +} + +/** + * @brief Set the specified data holding register value for DAC channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] data Data to be loaded into data holding register of channel 2 + * @retval None + */ +void DAC_SetChannel2Data(M4_DAC_TypeDef *DACx, uint16_t data) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if(READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_L) + { + DDL_ASSERT(0U == (data & 0xFU)); + } + else + { + DDL_ASSERT(0U == (data & 0xF000U)); + } + + WRITE_REG16(DACx->DADR2,data); +} + +/** + * @brief Set the specified data holding register value for channel 1 and channel 2 + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param data2: Data to be loaded into data holding register of channel 2 + * @param data1: Data to be loaded into data holding register of channel 1 + * @retval None + */ +void DAC_SetDualChannelData(M4_DAC_TypeDef *DACx, uint16_t data2, uint16_t data1) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if(READ_REG16_BIT(DACx->DACR, DAC_DACR_DPSEL) == DAC_DATA_ALIGN_L) + { + DDL_ASSERT(0U == (data1 & 0xFU)); + DDL_ASSERT(0U == (data2 & 0xFU)); + } + else + { + DDL_ASSERT(0U == (data1 & 0xF000U)); + DDL_ASSERT(0U == (data2 & 0xF000U)); + } + + WRITE_REG16(DACx->DADR1,data1); + WRITE_REG16(DACx->DADR2,data2); +} + +/** + * @brief Get convert status of channel 1 in ADC priority mode + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @retval An en_dac_conv_sate_t enumeration value: + * - ErrorInvalidMode: Could not get convert status when adc priority is not enabled + * - Ok: Data convert completed + * - OperationInProgress: Data convert is ongoing + */ +en_result_t DAC_GetChannel1ConvState(const M4_DAC_TypeDef *DACx) +{ + en_result_t enStat = ErrorInvalidMode; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if(0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN)) + { + enStat = OperationInProgress; + + if(READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_DA1SF) == 0U) + { + enStat = Ok; + } + } + + return enStat; +} + +/** + * @brief Get convert status of channel 2 in ADC priority mode + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @retval An en_dac_conv_sate_t enumeration value: + * - ErrorInvalidMode: Could not get convert status when adc priority is not enabled + * - Ok: Data convert completed + * - OperationInProgress: Data convert is ongoing + */ +en_result_t DAC_GetChannel2ConvState(const M4_DAC_TypeDef *DACx) +{ + en_result_t enStat = ErrorInvalidMode; + + DDL_ASSERT(IS_VALID_UNIT(DACx)); + + if(0U != READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_ADPEN)) + { + enStat = OperationInProgress; + + if(READ_REG16_BIT(DACx->DAADPCR, DAC_DAADPCR_DA2SF) == 0U) + { + enStat = Ok; + } + } + + return enStat; +} + +/** + * @brief Fills each pstcInit member with its default value + * @param [in] pstcInit pointer to a stc_dac_init_t structure which will + * be initialized. + * @retval An en_result_t enumeration value. + * - Ok: No errors occurred. + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t DAC_StructInit(stc_dac_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if(pstcInit != NULL) + { + pstcInit->u16Src = DAC_DATA_SRC_DATAREG; + pstcInit->enOutput = Enable; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Initialize the DAC peripheral according to the specified parameters + * in the stc_dac_init_t + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @param [in] u16Ch Specify the DAC channel @ref DAC_CH. + * This parameter can be one of the following values: + * @arg DAC_CH_1 + * @arg DAC_CH_2 + * @param [in] pstcInit pointer to a stc_dac_init_t structure that contains + * the configuration information for the specified DAC channel. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t DAC_Init(M4_DAC_TypeDef *DACx, uint16_t u16Ch, const stc_dac_init_t *pstcInit) +{ + DDL_ASSERT(IS_VALID_UNIT(DACx)); + DDL_ASSERT(IS_VALID_CH(u16Ch)); + + en_result_t enRet = ErrorInvalidParameter; + + if(pstcInit != NULL) + { + DDL_ASSERT(IS_VALID_DATA_SRC(pstcInit->u16Src)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(pstcInit->enOutput)); + + DAC_SetDataSource(DACx, u16Ch, pstcInit->u16Src); + DAC_OutputCmd(DACx, u16Ch, pstcInit->enOutput); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Deinitialize the DAC peripheral registers to their default reset values. + * @param [in] DACx Pointer to the DAC peripheral register. + * This parameter can be one of the following values: + * @arg M4_DAC1 + * @arg M4_DAC2 + * @retval None + */ +void DAC_DeInit(M4_DAC_TypeDef *DACx) +{ + DAC_DualChannelStop(DACx); + + DAC_SetDataSource(DACx, DAC_CH_1, DAC_DATA_SRC_DATAREG); + DAC_SetDataSource(DACx, DAC_CH_2, DAC_DATA_SRC_DATAREG); + + DAC_DataRegAlignConfig(DACx, DAC_DATA_ALIGN_R); + + (void)DAC_AMPCmd(DACx, DAC_CH_1,Disable); + (void)DAC_AMPCmd(DACx, DAC_CH_2,Disable); + + DAC_OutputCmd(DACx, DAC_CH_1, Enable); + DAC_OutputCmd(DACx, DAC_CH_2, Enable); + + DAC_ADCPrioConfig(DACx, DAC_ADP_SELECT_ALL, Disable); + DAC_ADCPrioCmd(DACx, Disable); +} + +/** + * @} + */ + +#endif /* DDL_DAC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dcu.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dcu.c new file mode 100644 index 0000000000000000000000000000000000000000..7817362a6f59028c300e9e3768b9b908316ac81e --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dcu.c @@ -0,0 +1,1015 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dcu.c + * @brief This file provides firmware functions to manage the DCU(Data Computing + * Unit). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-23 Hongjh 1. Modify macro define for interrupt, flag and mode; + 2. Rename API: from DCU_IntFuncCmd to DCU_GlobalIntCmd; + 3. Refine API: DCU_IntCmd and delete DCU_SetCmpIntMode; + 4. Refine API: DCU DATA read/write. + 2020-09-07 Hongjh Refine API: DCU_SetTriggerSrc + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_dcu.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_DCU DCU + * @brief DCU Driver Library + * @{ + */ + +#if (DDL_DCU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DCU_Local_Macros DCU Local Macros + * @{ + */ + +/** + * @defgroup DCU_Check_Parameters_Validity DCU Check Parameters Validity + * @{ + */ +#define IS_DCU_BASE_FUNC_UNIT(x) \ +( (M4_DCU5 == (x)) || \ + (M4_DCU6 == (x)) || \ + (M4_DCU7 == (x)) || \ + (M4_DCU8 == (x))) + +#define IS_DCU_WAVE_FUNC_UNIT(x) \ +( (M4_DCU1 == (x)) || \ + (M4_DCU2 == (x)) || \ + (M4_DCU3 == (x)) || \ + (M4_DCU4 == (x))) + +#define IS_DCU_UNIT(x) \ +( (IS_DCU_BASE_FUNC_UNIT(x)) || \ + (IS_DCU_WAVE_FUNC_UNIT(x))) + +#define IS_DCU_BASE_FUNC_UNIT_MODE(x) \ +( (DCU_CMP == (x)) || \ + (DCU_ADD == (x)) || \ + (DCU_SUB == (x)) || \ + (DCU_HW_ADD == (x)) || \ + (DCU_HW_SUB == (x))) + +#define IS_DCU_WAVE_FUNC_UNIT_MODE(x) \ +( (DCU_CMP == (x)) || \ + (DCU_ADD == (x)) || \ + (DCU_SUB == (x)) || \ + (DCU_HW_ADD == (x)) || \ + (DCU_HW_SUB == (x)) || \ + (DCU_TRIANGLE_WAVE == (x)) || \ + (DCU_SAWTOOTH_WAVE_INC == (x)) || \ + (DCU_SAWTOOTH_WAVE_DEC == (x))) + +#define IS_DCU_BASE_FUNC_UNIT_INT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_INT_MASK)))) + +#define IS_DCU_WAVE_FUNC_UNIT_INT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_WAVE_FUNC_UNIT_INT_MASK)))) + +#define IS_DCU_BASE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_BASE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_WAVE_FUNC_UNIT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_WAVE_FUNC_UNIT_FLAG_MASK)))) + +#define IS_DCU_INTERRUPT_STATE(x) \ +( (DCU_INT_ENABLE == (x)) || \ + (DCU_INT_DISABLE == (x))) + +#define IS_DCU_CMP_TRIG_MODE(x) \ +( (DCU_CMP_TRIG_DATA0 == (x)) || \ + (DCU_CMP_TRIG_DATA012 == (x))) + +#define IS_DCU_DATA_SIZE(x) \ +( (DCU_DATA_SIZE_8BIT == (x)) || \ + (DCU_DATA_SIZE_16BIT == (x)) || \ + (DCU_DATA_SIZE_32BIT == (x))) + +#define IS_DCU_INT_CATEGORY(x) \ +( ((x) == DCU_INT_OP) || \ + ((x) == DCU_INT_WAVE_MD) || \ + ((x) == DCU_INT_CMP_WIN) || \ + ((x) == DCU_INT_CMP_NON_WIN)) + +#define IS_DCU_INT_OP(x) ((x) == DCU_INT_OP_UDF_OVF) + +#define IS_DCU_INT_CMP_WIN(x) \ +( ((x) != 0UL) && \ + (((x) | DCU_INT_CMP_WIN_ALL) == DCU_INT_CMP_WIN_ALL)) + +#define IS_DCU_INT_WAVE_MD(x) \ +( ((x) != 0UL) && \ + (((x) | DCU_INT_WAVE_MD_ALL) == DCU_INT_WAVE_MD_ALL)) + +#define IS_DCU_INT_CMP_NON_WIN(x) \ +( ((x) != 0UL) || \ + (((x) | DCU_INT_CMP_NON_WIN_ALL) == DCU_INT_CMP_NON_WIN_ALL)) + +#define IS_DCU_DATA_REG(x) \ +( ((x) == DCU_DATA0_IDX) || \ + ((x) == DCU_DATA1_IDX) || \ + ((x) == DCU_DATA2_IDX)) + +#define IS_DCU_COM_TRIG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~DCU_COM_TRIG_MASK)))) + +#define IS_DCU_WAVE_UPPER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_LOWER_LIMIT(x) ((x) <= 0xFFFUL) + +#define IS_DCU_WAVE_STEP(x) ((x) <= 0xFFFUL) +/** + * @} + */ + +/** + * @defgroup DCU_Flag_Mask DCU Flag Mask + * @{ + */ +#define DCU_BASE_FUNC_UNIT_FLAG_MASK \ +( DCU_FLAG_DATA0_LS_DATA2 | \ + DCU_FLAG_DATA0_EQ_DATA2 | \ + DCU_FLAG_DATA0_GT_DATA2 | \ + DCU_FLAG_DATA0_LS_DATA1 | \ + DCU_FLAG_DATA0_EQ_DATA1 | \ + DCU_FLAG_DATA0_GT_DATA1) + +#define DCU_WAVE_FUNC_UNIT_FLAG_MASK \ +( DCU_FLAG_OPERATION | \ + DCU_FLAG_DATA0_LS_DATA2 | \ + DCU_FLAG_DATA0_EQ_DATA2 | \ + DCU_FLAG_DATA0_GT_DATA2 | \ + DCU_FLAG_DATA0_LS_DATA1 | \ + DCU_FLAG_DATA0_EQ_DATA1 | \ + DCU_FLAG_DATA0_GT_DATA1 | \ + DCU_FLAG_WAVE_SAWTOOTH_RELOAD | \ + DCU_FLAG_WAVE_TRIANGLE_BOTTOM | \ + DCU_FLAG_WAVE_TRIANGLE_TOP) +/** + * @} + */ + +#define DCU_DATA1_LOWER_LIMIT_POS (0UL) +#define DCU_DATA1_LOWER_LIMIT (0x00000FFFUL) + +#define DCU_DATA1_UPPER_LIMIT_POS (16UL) +#define DCU_DATA1_UPPER_LIMIT (0x0FFF0000UL) + +/** + * @defgroup DCU_Register_Address Get DCU register address + * @{ + */ +#define REG_ADDR(__REG__) ((uint32_t)(&(__REG__))) +#define DATA_REG_ADDR(__DCUx__, __IDX__) (REG_ADDR((__DCUx__)->DATA0) + ((__IDX__) << 2UL)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/** + * @addtogroup DCU_Local_Functions + * @{ + */ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx); +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DCU_Global_Functions DCU Global Functions + * @{ + */ + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] pstcInit Pointer to a @ref stc_dcu_init_t structure (DCU function configuration data structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit is NULL pointer + */ +en_result_t DCU_Init(M4_DCU_TypeDef *DCUx, const stc_dcu_init_t *pstcInit) +{ + uint32_t u32RegVal; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_MODE(pstcInit->u32Mode)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MODE(pstcInit->u32Mode))); + DDL_ASSERT(IS_DCU_DATA_SIZE(pstcInit->u32DataSize)); + DDL_ASSERT(IS_DCU_INTERRUPT_STATE(pstcInit->u32IntEn)); + DDL_ASSERT(IS_DCU_CMP_TRIG_MODE(pstcInit->u32CmpTriggerMode)); + + /* De-initialize DCU */ + WRITE_REG32(DCUx->CTL, 0x00000000UL); + WRITE_REG32(DCUx->INTEVTSEL, 0x00000000UL); + WRITE_REG32(DCUx->FLAGCLR, (IS_DCU_WAVE_FUNC_UNIT(DCUx)) ? 0x00000E7FUL:0x0000007FUL); + + /* Set register: CTL */ + u32RegVal = (pstcInit->u32Mode | \ + pstcInit->u32DataSize | \ + pstcInit->u32CmpTriggerMode | \ + pstcInit->u32IntEn); + WRITE_REG32(DCUx->CTL, u32RegVal); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_uart_init_t to default values. + * @param [out] pstcInit Pointer to a @ref stc_dcu_init_t structure (DCU function configuration data structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: pstcInit is NULL pointer + */ +en_result_t DCU_StructInit(stc_dcu_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check parameters */ + if (NULL != pstcInit) + { + pstcInit->u32Mode = DCU_SUB; + pstcInit->u32DataSize = DCU_DATA_SIZE_8BIT; + pstcInit->u32CmpTriggerMode = DCU_CMP_TRIG_DATA0; + pstcInit->u32IntEn = DCU_INT_DISABLE; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @retval None + */ +void DCU_DeInit(M4_DCU_TypeDef *DCUx) +{ + /* Configures the registers to reset value. */ + WRITE_REG32(DCUx->CTL, 0x00000000UL); + WRITE_REG32(DCUx->INTEVTSEL, 0x00000000UL); + WRITE_REG32(DCUx->FLAGCLR, 0x0000007FUL); + WRITE_REG32(DCUx->DATA0, 0x00000000UL); + WRITE_REG32(DCUx->DATA1, 0x00000000UL); + WRITE_REG32(DCUx->DATA2, 0x00000000UL); +} + +/** + * @brief Initialize DCU function. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @param [in] pstcCfg Pointer to a @ref stc_dcu_wave_cfg_t structure (DCU wave function configuration data structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcCfg is NULL pointer + * @note The DCU sawtooth/triangle wave mode is supported by M4_DCU1/2/3/4. + */ +en_result_t DCU_WaveCfg(M4_DCU_TypeDef *DCUx, + const stc_dcu_wave_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcCfg) + { + DDL_ASSERT(IS_DCU_WAVE_FUNC_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_WAVE_LOWER_LIMIT(pstcCfg->u32LowerLimit)); + DDL_ASSERT(IS_DCU_WAVE_UPPER_LIMIT(pstcCfg->u32UpperLimit)); + DDL_ASSERT(IS_DCU_WAVE_STEP(pstcCfg->u32Step)); + + WRITE_REG32(DCUx->DATA0, 0x00000000UL); + WRITE_REG32(DCUx->DATA1, ((pstcCfg->u32LowerLimit << DCU_DATA1_LOWER_LIMIT_POS) | \ + (pstcCfg->u32UpperLimit << DCU_DATA1_UPPER_LIMIT_POS))); + WRITE_REG32(DCUx->DATA2, pstcCfg->u32Step); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set DCU operation mode. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32Mode DCU mode + * This parameter can be one of the following values: + * @arg DCU_INVALID: DCU invalid + * @arg DCU_ADD: DCU add operation + * @arg DCU_SUB: DCU sub operation + * @arg DCU_HW_ADD: DCU hardware trigger add + * @arg DCU_HW_SUB: DCU hardware trigger sub + * @arg DCU_CMP: DCU compare + * @arg DCU_TRIANGLE_WAVE: DCU triangle wave output mode + * @arg DCU_SAWTOOTH_WAVE_INC:DCU increasing sawtooth wave output mode + * @arg DCU_SAWTOOTH_WAVE_DEC:DCU decreasing sawtooth wave output mode + * @retval None + * @note The DCU sawtooth/triangle wave mode is supported by M4_DCU1/2/3/4. + */ +void DCU_SetMode(M4_DCU_TypeDef *DCUx, uint32_t u32Mode) +{ + /* Check for parameters */ + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_MODE(u32Mode)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_MODE(u32Mode))); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_MODE, u32Mode); +} + +/** + * @brief Get DCU operation mode. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @retval Returned value can be one of the following values: + * @arg DCU_INVALID: DCU invalid + * @arg DCU_ADD: DCU add operation + * @arg DCU_SUB: DCU sub operation + * @arg DCU_HW_ADD: DCU hardware trigger add + * @arg DCU_HW_SUB: DCU hardware trigger sub + * @arg DCU_CMP: DCU compare + * @arg DCU_TRIANGLE_WAVE: DCU triangle wave output mode + * @arg DCU_SAWTOOTH_WAVE_INC:DCU increasing sawtooth wave output mode + * @arg DCU_SAWTOOTH_WAVE_DEC:DCU decreasing sawtooth wave output mode + * @note The DCU sawtooth/triangle wave mode is supported by M4_DCU1/2/3/4. + */ +uint32_t DCU_GetMode(const M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + + return READ_REG32_BIT(DCUx->CTL, DCU_CTL_MODE); +} + +/** + * @brief Set DCU data size. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataSize DCU data size + * This parameter can be one of the following values: + * @arg DCU_DATA_SIZE_8BIT: DCU data size 8 bits + * @arg DCU_DATA_SIZE_16BIT: DCU data size 16 bits + * @arg DCU_DATA_SIZE_32BIT: DCU data size 32 bits + * @retval None + */ +void DCU_SetDataSize(M4_DCU_TypeDef *DCUx, uint32_t u32DataSize) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_SIZE(u32DataSize)); + + MODIFY_REG32(DCUx->CTL, DCU_CTL_DATASIZE, u32DataSize); +} + +/** + * @brief Get DCU data size. + * @param [in] DCUx Pointer to DCU instance register base + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @retval Returned value can be one of the following values: + * @arg DCU_DATA_SIZE_8BIT: DCU data size 8 bits + * @arg DCU_DATA_SIZE_16BIT: DCU data size 16 bits + * @arg DCU_DATA_SIZE_32BIT: DCU data size 32 bits + */ +uint32_t DCU_GetDataSize(const M4_DCU_TypeDef *DCUx) +{ + /* Check for DCUx pointer */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + + return READ_REG32_BIT(DCUx->CTL, DCU_CTL_DATASIZE); +} + +/** + * @brief Get DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be one of the following values: + * @arg DCU_FLAG_OPERATION: DCU addition overflow or subtraction underflow flag + * @arg DCU_FLAG_DATA0_LS_DATA2: DCU DATA0 < DATA2 flag + * @arg DCU_FLAG_DATA0_EQ_DATA2: DCU DATA0 = DATA2 flag + * @arg DCU_FLAG_DATA0_GT_DATA2: DCU DATA0 > DATA2 flag + * @arg DCU_FLAG_DATA0_LS_DATA1: DCU DATA0 < DATA1 flag + * @arg DCU_FLAG_DATA0_EQ_DATA1: DCU DATA0 = DATA1 flag + * @arg DCU_FLAG_DATA0_GT_DATA1: DCU DATA0 > DATA1 flag + * @arg DCU_FLAG_SAWTOOTH_WAVE_RELOAD: DCU sawtooth wave mode reload flag + * @arg DCU_FLAG_TRIANGLE_WAVE_BOTTOM: DCU triangle wave mode bottom flag + * @arg DCU_FLAG_TRIANGLE_WAVE_TOP: DCU triangle wave mode top flag + * @retval Returned value can be one of the following values: + * @arg Set Flag is set. + * @arg Reset Flag is reset or enStatus is invalid. + */ +en_flag_status_t DCU_GetStatus(const M4_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_FLAG(u32Flag)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag))); + + return READ_REG32_BIT(DCUx->FLAG, u32Flag) ? Set : Reset; +} + +/** + * @brief Clear DCU flag. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32Flag The specified DCU flag + * This parameter can be one of the following values: + * @arg DCU_FLAG_OPERATION: DCU addition overflow or subtraction underflow flag + * @arg DCU_FLAG_DATA0_LS_DATA2: DCU DATA0 < DATA2 flag + * @arg DCU_FLAG_DATA0_EQ_DATA2: DCU DATA0 = DATA2 flag + * @arg DCU_FLAG_DATA0_GT_DATA2: DCU DATA0 > DATA2 flag + * @arg DCU_FLAG_DATA0_LS_DATA1: DCU DATA0 < DATA1 flag + * @arg DCU_FLAG_DATA0_EQ_DATA1: DCU DATA0 = DATA1 flag + * @arg DCU_FLAG_DATA0_GT_DATA1: DCU DATA0 > DATA1 flag + * @arg DCU_FLAG_SAWTOOTH_WAVE_RELOAD: DCU sawtooth wave mode reload flag + * @arg DCU_FLAG_TRIANGLE_WAVE_BOTTOM: DCU triangle wave mode bottom flag + * @arg DCU_FLAG_TRIANGLE_WAVE_TOP: DCU triangle wave mode top flag + * @retval None + */ +void DCU_ClearStatus(M4_DCU_TypeDef *DCUx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT((IS_DCU_WAVE_FUNC_UNIT(DCUx) && IS_DCU_WAVE_FUNC_UNIT_FLAG(u32Flag)) || \ + (IS_DCU_BASE_FUNC_UNIT(DCUx) && IS_DCU_BASE_FUNC_UNIT_FLAG(u32Flag))); + + WRITE_REG32(DCUx->FLAGCLR, u32Flag); +} + +/** + * @brief Enable/disable DCU the specified interrupt source. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32IntCategory DCU interrupt categorye + * This parameter can be one of the following values: + * @arg DCU_INT_OP: DCU operation result(overflow/underflow) interrupt + * @arg DCU_INT_WAVE_MD: DCU wave mode(sawtooth/triangle wave mode) interrupt + * @arg DCU_INT_CMP_WIN: DCU comparison(window) interrupt + * @arg DCU_INT_CMP_NON_WIN: DCU comparison(non-window) interrupt + * @param [in] u32IntType DCU interrupt type + * This parameter can be one of the following case: + * a. this parameter can be one of the following values when u16IntType = DCU_INT_OP: + * @arg DCU_INT_OP_UDF_OVF: DCU addition overflow or subtraction underflow interrupt + * b. this parameter can be any composed value of the following values when u16IntType = DCU_INT_CMP_WIN: + * @arg DCU_INT_CMP_WIN_INSIDE:DCU comparison(DATA2 <= DATA0 <= DATA1) interrupt + * @arg DCU_INT_CMP_WIN_OUTSIDE: DCU comparison(DATA0 < DATA2 & DATA0 > DATA1 ) interrupt + * @note Only one of the window inside and outside interrupt is valid. + * @note Both of the window inside and outside interrupt is disabled and the window interrupt is invalid. + * @note Both of the window inside and outside interrupt is enabled and the compare mode interrupt is invalid. + * c. this parameter can be any composed value of the following values when u16IntType = DCU_INT_CMP_NON_WIN: + * @arg DCU_INT_CMP_DATA0_LS_DATA2: DCU DATA0 < DATA2 interrupt + * @arg DCU_INT_CMP_DATA0_EQ_DATA2: DCU DATA0 = DATA2 interrupt + * @arg DCU_INT_CMP_DATA0_GT_DATA2: DCU DATA0 > DATA2 interrupt + * @arg DCU_INT_CMP_DATA0_LS_DATA1: DCU DATA0 < DATA1 interrupt + * @arg DCU_INT_CMP_DATA0_EQ_DATA1: DCU DATA0 = DATA1 interrupt + * @arg DCU_INT_CMP_DATA0_GT_DATA1: DCU DATA0 > DATA1 interrupt + * @note Both of the window inside and outside interrupt is disabled and the compare non-window interrupt is valid. + * d. this parameter can be any composed value of the following values when u16IntType = DCU_INT_WAVE_MD: + * @arg DCU_INT_WAVE_SAWTOOTH_RELOAD: DCU sawtooth wave mode reload interrupt + * @arg DCU_INT_WAVE_TRIANGLE_BOTTOM: DCU triangle wave mode bottom interrupt + * @arg DCU_INT_WAVE_TRIANGLE_TOP: DCU triangle wave mode top interrupt + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note The DCU sawtooth/triangle wave mode is supported by M4_DCU1/2/3/4. + */ +void DCU_IntCmd(M4_DCU_TypeDef *DCUx, + uint32_t u32IntCategory, + uint32_t u32IntType, + en_functional_state_t enNewState) +{ + uint32_t u32Type; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_CATEGORY(u32IntCategory)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (DCU_INT_OP == u32IntCategory) + { + DDL_ASSERT(IS_DCU_INT_OP(u32IntType)); + u32Type = (u32IntType & DCU_INT_OP_UDF_OVF); + } + else if (DCU_INT_CMP_WIN == u32IntCategory) + { + DDL_ASSERT(IS_DCU_INT_CMP_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_WIN_ALL); + } + else if (DCU_INT_CMP_NON_WIN == u32IntCategory) + { + DDL_ASSERT(IS_DCU_INT_CMP_NON_WIN(u32IntType)); + u32Type = (u32IntType & DCU_INT_CMP_NON_WIN_ALL); + } + else + { + DDL_ASSERT(IS_DCU_WAVE_FUNC_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_INT_WAVE_MD(u32IntType)); + u32Type = (u32IntType & DCU_INT_WAVE_MD_ALL); + } + + if (Enable == enNewState) + { + SET_REG32_BIT(DCUx->INTEVTSEL, u32Type); + } + else + { + CLEAR_REG32_BIT(DCUx->INTEVTSEL, u32Type); + } +} + +/** + * @brief Enable or disable DCU interrupt funtion. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void DCU_GlobalIntCmd(M4_DCU_TypeDef *DCUx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } + else + { + CLEAR_REG32_BIT(DCUx->CTL, DCU_CTL_INTEN); + } +} + +/** + * @brief AOS common trigger function config for DCU + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32ComTrig Common trigger event. + * This parameter can be one of the following values: + * @arg DCU_COM_TRIG1: Common trigger event 1. + * @arg DCU_COM_TRIG2: Common trigger event 2. + * @param [in] enNewState New state of common trigger function. + * @retval None + * @note This register belongs to AOS module, please ensure enable it in advance. + */ +void DCU_ComTriggerCmd(M4_DCU_TypeDef *DCUx, + uint32_t u32ComTrig, + en_functional_state_t enNewState) +{ + __IO uint32_t *const TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + DDL_ASSERT(IS_DCU_COM_TRIG(u32ComTrig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(*TRGSELx, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(*TRGSELx, u32ComTrig); + } + } +} + +/** + * @brief Set the specified event trigger source for DCU. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] enEventSrc The trigger external event source source. + * @arg This parameter can be any value of @ref en_event_src_t + * @retval None + * @note This register belongs to AOS module, please ensure enable it in advance. + */ +void DCU_SetTriggerSrc(const M4_DCU_TypeDef *DCUx, en_event_src_t enEventSrc) +{ + __IO uint32_t *const TRGSELx = DCU_TRGSELx(DCUx); + + if (NULL != TRGSELx) + { + MODIFY_REG32(*TRGSELx, AOS_DCU_1_TRGSEL_TRGSEL, enEventSrc); + } +} + +/** + * @brief Read DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the following values: + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for byte + */ +uint8_t DCU_ReadData8(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + __IO uint8_t *DATA; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = (__IO uint8_t *)DATA_REG_ADDR(DCUx, u32DataIndex); + return READ_REG8(*DATA); +} + +/** + * @brief Write DCU register DATA for byte. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the following values: + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u8Data The data to write. + * @retval None + */ +void DCU_WriteData8(M4_DCU_TypeDef *DCUx, + uint32_t u32DataIndex, + uint8_t u8Data) +{ + __IO uint8_t *DATA; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = (__IO uint8_t *)DATA_REG_ADDR(DCUx, u32DataIndex); + WRITE_REG8(*DATA, u8Data); +} + +/** + * @brief Read DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the following values: + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for half-word + */ +uint16_t DCU_ReadData16(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + __IO uint16_t *DATA; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = (__IO uint16_t *)DATA_REG_ADDR(DCUx, u32DataIndex); + return READ_REG16(*DATA); +} + +/** + * @brief Write DCU register DATA for half-word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the following values: + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u16Data The data to write. + * @retval None + */ +void DCU_WriteData16(M4_DCU_TypeDef *DCUx, + uint32_t u32DataIndex, + uint16_t u16Data) +{ + __IO uint16_t *DATA; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = (__IO uint16_t *)DATA_REG_ADDR(DCUx, u32DataIndex); + WRITE_REG16(*DATA, u16Data); +} + +/** + * @brief Read DCU register DATA for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the following values: + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @retval DCU register DATA value for word + */ +uint32_t DCU_ReadData32(const M4_DCU_TypeDef *DCUx, uint32_t u32DataIndex) +{ + __IO uint32_t *DATA; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = (__IO uint32_t *)DATA_REG_ADDR(DCUx, u32DataIndex); + return READ_REG32(*DATA); +} + +/** + * @brief Write DCU register DATA0 for word. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @param [in] u32DataIndex DCU data register index + * This parameter can be one of the following values: + * @arg DCU_DATA0_IDX: DCU DATA0 + * @arg DCU_DATA1_IDX: DCU DATA1 + * @arg DCU_DATA2_IDX: DCU DATA2 + * @param [in] u32Data The data to write. + * @retval None + */ +void DCU_WriteData32(M4_DCU_TypeDef *DCUx, + uint32_t u32DataIndex, + uint32_t u32Data) +{ + __IO uint32_t *DATA; + + /* Check parameters */ + DDL_ASSERT(IS_DCU_UNIT(DCUx)); + DDL_ASSERT(IS_DCU_DATA_REG(u32DataIndex)); + + DATA = (__IO uint32_t *)DATA_REG_ADDR(DCUx, u32DataIndex); + WRITE_REG32(*DATA, u32Data); +} + +/** + * @} + */ + +/** + * @defgroup DCU_Local_Functions DCU Local Functions + * @{ + */ + +/** + * @brief Get DCU trigger selection register of the specified DCU unit. + * @param [in] DCUx Pointer to DCU instance register base + * This parameter can be one of the following values: + * @arg M4_DCU1: DCU unit 1 instance register base + * @arg M4_DCU2: DCU unit 2 instance register base + * @arg M4_DCU3: DCU unit 3 instance register base + * @arg M4_DCU4: DCU unit 4 instance register base + * @arg M4_DCU5: DCU unit 5 instance register base + * @arg M4_DCU6: DCU unit 6 instance register base + * @arg M4_DCU7: DCU unit 7 instance register base + * @arg M4_DCU8: DCU unit 8 instance register base + * @retval DCU trigger selection register + */ +static __IO uint32_t* DCU_TRGSELx(const M4_DCU_TypeDef *DCUx) +{ + __IO uint32_t *TRGSELx; + + if ((M4_DCU1 == DCUx) || (M4_DCU5 == DCUx)) + { + TRGSELx = &M4_AOS->DCU_1_TRGSEL; + } + else if ((M4_DCU2 == DCUx) || (M4_DCU6 == DCUx)) + { + TRGSELx = &M4_AOS->DCU_2_TRGSEL; + } + else if ((M4_DCU3 == DCUx) || (M4_DCU7 == DCUx)) + { + TRGSELx = &M4_AOS->DCU_3_TRGSEL; + } + else if ((M4_DCU4 == DCUx) || (M4_DCU8 == DCUx)) + { + TRGSELx = &M4_AOS->DCU_4_TRGSEL; + } + else + { + TRGSELx = NULL; + } + + return TRGSELx; +} + +/** + * @} + */ + +#endif /* DDL_DCU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dma.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dma.c new file mode 100644 index 0000000000000000000000000000000000000000..702fdf900eee0e8b78ef107982001f595a26879c --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dma.c @@ -0,0 +1,1712 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dma.c + * @brief This file provides firmware functions to manage the Direct Memory + * Access (DMA). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-09-04 Chengy Typo revise in DMA_ReConfigInit() + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_dma.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_DMA DMA + * @brief Direct Memory Access Driver Library + * @{ + */ + +#if (DDL_DMA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DMA_Local_Macros DMA Local Macros + * @{ + */ +#define DMA_CH_REG(reg_base, ch) (*(uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +/** + * @defgroup DMA_Check_Parameters_Validity DMA Check Parameters Validity + * @{ + */ +/*! Parameter valid check for DMA unit. */ +#define IS_DMA_UNIT(unit) \ +( ((unit) == M4_DMA1) || \ + ((unit) == M4_DMA2)) + +/*! Parameter valid check for DMA channel. */ +#define IS_DMA_CH(ch) ((ch) <= DMA_CH7) + +/*! Parameter valid check for DMA multiplex channel. */ +#define IS_DMA_MX_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | DMA_MX_CH_ALL) == DMA_MX_CH_ALL)) + +/*! Parameter valid check for DMA block size. */ +#define IS_DMA_BLKSZ(bc) ((bc) <= 1024U) + +/*! Parameter valid check for DMA non-sequence transfer count. */ +#define IS_DMA_NS_TRANSCNT(tc) ((tc) <= 4096U) + +/*! Parameter valid check for DMA non-sequence offset. */ +#define IS_DMA_NS_OFFSET(ofs) ((ofs) <= ((1UL <<20U) - 1UL)) + +/*! Parameter valid check for DMA LLP pointer address. */ +#define IS_DMA_LLP_ADDR(llp) (((llp) & 0x03UL) == 0x00UL) + +/*! Parameter valid check for DMA LLP function. */ +#define IS_DMA_LLP_EN(en) \ +( ((en) == DMA_LLP_ENABLE) || \ + ((en) == DMA_LLP_DISABLE)) + +/*! Parameter valid check for DMA linked-list-pointer mode. */ +#define IS_DMA_LLP_MODE(mode) \ +( ((mode) == DMA_LLP_RUN) || \ + ((mode) == DMA_LLP_WAIT)) + +/*! Parameter valid check for DMA error interrupt. */ +#define IS_DMA_ERR_INT(it) \ +( ((it) != 0x00000000UL) && \ + (((it) | DMA_ERR_INT_MASK) == DMA_ERR_INT_MASK)) + +/*! Parameter valid check for DMA transfer interrupt. */ +#define IS_DMA_TRANS_INT(it) \ +( ((it) != 0x00000000UL) && \ + (((it) | DMA_TRANS_INT_MASK) == DMA_TRANS_INT_MASK)) + +/*! Parameter valid check for DMA request status. */ +#define IS_DMA_REQ_STAT(stat) \ +( ((stat) != 0x00000000UL) && \ + (((stat) | DMA_REQ_STAT_MASK) == DMA_REQ_STAT_MASK)) + +/*! Parameter valid check for DMA channel status. */ +#define IS_DMA_TRANS_STAT(stat) \ +( ((stat) != 0x00000000UL) && \ + (((stat) | DMA_TRANS_STAT_MASK) == DMA_TRANS_STAT_MASK)) + +/*! Parameter valid check for DMA transfer data width. */ +#define IS_DMA_DATA_WIDTH(dw) \ +( ((dw) == DMA_DATAWIDTH_8BIT) || \ + ((dw) == DMA_DATAWIDTH_16BIT) || \ + ((dw) == DMA_DATAWIDTH_32BIT)) + +/*! Parameter valid check for DMA source address mode. */ +#define IS_DMA_SADDR_MODE(mode) \ +( ((mode) == DMA_SRC_ADDR_FIX) || \ + ((mode) == DMA_SRC_ADDR_INC) || \ + ((mode) == DMA_SRC_ADDR_DEC)) + +/*! Parameter valid check for DMA destination address mode. */ +#define IS_DMA_DADDR_MODE(mode) \ +( ((mode) == DMA_DEST_ADDR_FIX) || \ + ((mode) == DMA_DEST_ADDR_INC) || \ + ((mode) == DMA_DEST_ADDR_DEC)) + +/*! Parameter valid check for DMA source address repeat selection. */ +#define IS_DMA_SRC_RPT(rpt) \ +( ((rpt) == DMA_SRC_RPT_ENABLE) || \ + ((rpt) == DMA_SRC_RPT_DISABLE)) + +/*! Parameter valid check for DMA destination address repeat selection. */ +#define IS_DMA_DEST_RPT(rpt) \ +( ((rpt) == DMA_DEST_RPT_ENABLE) || \ + ((rpt) == DMA_DEST_RPT_DISABLE)) + +/*! Parameter valid check for DMA source non-sequence selection. */ +#define IS_DMA_SRC_NS(ns) \ +( ((ns) == DMA_SRC_NS_ENABLE) || \ + ((ns) == DMA_SRC_NS_DISABLE)) + +/*! Parameter valid check for DMA destination non-sequence selection. */ +#define IS_DMA_DEST_NS(ns) \ +( ((ns) == DMA_DEST_NS_ENABLE) || \ + ((ns) == DMA_DEST_NS_DISABLE)) + +/*! Parameter valid check for DMA global interrupt function. */ +#define IS_DMA_INT_FUNC(func) \ +( ((func) == DMA_INT_ENABLE) || \ + ((func) == DMA_INT_DISABLE)) + +/*! Parameter valid check for DMA reconfig count mode. */ +#define IS_DMA_RC_CNT_MODE(mode) \ +( ((mode) == DMA_RC_CNT_FIX) || \ + ((mode) == DMA_RC_CNT_SRC) || \ + ((mode) == DMA_RC_CNT_DEST)) + +/*! Parameter valid check for DMA reconfig destination address mode. */ +#define IS_DMA_RC_DA_MODE(mode) \ +( ((mode) == DMA_RC_DA_FIX) || \ + ((mode) == DMA_RC_DA_NS ) || \ + ((mode) == DMA_RC_DA_RPT)) + +/*! Parameter valid check for DMA reconfig source address mode. */ +#define IS_DMA_RC_SA_MODE(mode) \ +( ((mode) == DMA_RC_SA_FIX) || \ + ((mode) == DMA_RC_SA_NS ) || \ + ((mode) == DMA_RC_SA_RPT)) + +/*! Parameter valid check for DMA common trigger config. */ +#define IS_DMA_COM_TRIG(trig) \ +( ((trig) != 0x00UL) && \ + (((trig) | DMA_COM_TRIG_MASK) == DMA_COM_TRIG_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DMA_Global_Functions DMA Global Functions + * @{ + */ + +/** + * @brief DMA global function config. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void DMA_Cmd(M4_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Global setting, Enable or Disable DMA */ + WRITE_REG32(DMAx->EN, enNewState); +} + +/** + * @brief DMA error IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32ErrInt DMA error IRQ flag. + * @arg DMA_REQ_ERR_CH0. + * @arg DMA_REQ_ERR_CH1. + * @arg DMA_REQ_ERR_CH2. + * @arg DMA_REQ_ERR_CH3. + * @arg DMA_REQ_ERR_CH4. + * @arg DMA_REQ_ERR_CH5. + * @arg DMA_REQ_ERR_CH6. + * @arg DMA_REQ_ERR_CH7. + * @arg DMA_TRANS_ERR_CH0. + * @arg DMA_TRANS_ERR_CH1. + * @arg DMA_TRANS_ERR_CH2. + * @arg DMA_TRANS_ERR_CH3. + * @arg DMA_TRANS_ERR_CH4. + * @arg DMA_TRANS_ERR_CH5. + * @arg DMA_TRANS_ERR_CH6. + * @arg DMA_TRANS_ERR_CH7. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void DMA_ErrIntCmd(M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable == enNewState) + { + SET_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } + else + { + CLEAR_REG32_BIT(DMAx->INTMASK0, u32ErrInt); + } +} + +/** + * @brief Get DMA error IRQ status. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32ErrInt DMA error IRQ flag. + * @arg DMA_REQ_ERR_CH0. + * @arg DMA_REQ_ERR_CH1. + * @arg DMA_REQ_ERR_CH2. + * @arg DMA_REQ_ERR_CH3. + * @arg DMA_REQ_ERR_CH4. + * @arg DMA_REQ_ERR_CH5. + * @arg DMA_REQ_ERR_CH6. + * @arg DMA_REQ_ERR_CH7. + * @arg DMA_TRANS_ERR_CH0. + * @arg DMA_TRANS_ERR_CH1. + * @arg DMA_TRANS_ERR_CH2. + * @arg DMA_TRANS_ERR_CH3. + * @arg DMA_TRANS_ERR_CH4. + * @arg DMA_TRANS_ERR_CH5. + * @arg DMA_TRANS_ERR_CH6. + * @arg DMA_TRANS_ERR_CH7. + * @retval en_flag_status_t + */ +en_flag_status_t DMA_GetErrIntStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + + return (READ_REG32_BIT(DMAx->INTSTAT0, u32ErrInt) ? Set : Reset); +} + +/** + * @brief Clear DMA error IRQ status. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32ErrInt DMA error IRQ flag. + * @arg DMA_REQ_ERR_CH0. + * @arg DMA_REQ_ERR_CH1. + * @arg DMA_REQ_ERR_CH2. + * @arg DMA_REQ_ERR_CH3. + * @arg DMA_REQ_ERR_CH4. + * @arg DMA_REQ_ERR_CH5. + * @arg DMA_REQ_ERR_CH6. + * @arg DMA_REQ_ERR_CH7. + * @arg DMA_TRANS_ERR_CH0. + * @arg DMA_TRANS_ERR_CH1. + * @arg DMA_TRANS_ERR_CH2. + * @arg DMA_TRANS_ERR_CH3. + * @arg DMA_TRANS_ERR_CH4. + * @arg DMA_TRANS_ERR_CH5. + * @arg DMA_TRANS_ERR_CH6. + * @arg DMA_TRANS_ERR_CH7. + * @retval None + */ +void DMA_ClearErrIntStatus(M4_DMA_TypeDef *DMAx, uint32_t u32ErrInt) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_ERR_INT(u32ErrInt)); + + SET_REG32_BIT(DMAx->INTCLR0, u32ErrInt); +} + +/** + * @brief DMA transfer IRQ function config. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32TransInt DMA transfer IRQ flag. + * @arg DMA_BTC_INT_CH0 + * @arg DMA_BTC_INT_CH1 + * @arg DMA_BTC_INT_CH2 + * @arg DMA_BTC_INT_CH3 + * @arg DMA_BTC_INT_CH4 + * @arg DMA_BTC_INT_CH5 + * @arg DMA_BTC_INT_CH6 + * @arg DMA_BTC_INT_CH7 + * @arg DMA_TC_INT_CH0 + * @arg DMA_TC_INT_CH1 + * @arg DMA_TC_INT_CH2 + * @arg DMA_TC_INT_CH3 + * @arg DMA_TC_INT_CH4 + * @arg DMA_TC_INT_CH5 + * @arg DMA_TC_INT_CH6 + * @arg DMA_TC_INT_CH7 + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void DMA_TransIntCmd(M4_DMA_TypeDef *DMAx, uint32_t u32TransInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable == enNewState) + { + SET_REG32_BIT(DMAx->INTMASK1, u32TransInt); + } + else + { + CLEAR_REG32_BIT(DMAx->INTMASK1, u32TransInt); + } +} + +/** + * @brief Get DMA transfer IRQ status. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32TransInt DMA transfer IRQ flag. + * @arg DMA_BTC_INT_CH0 + * @arg DMA_BTC_INT_CH1 + * @arg DMA_BTC_INT_CH2 + * @arg DMA_BTC_INT_CH3 + * @arg DMA_BTC_INT_CH4 + * @arg DMA_BTC_INT_CH5 + * @arg DMA_BTC_INT_CH6 + * @arg DMA_BTC_INT_CH7 + * @arg DMA_TC_INT_CH0 + * @arg DMA_TC_INT_CH1 + * @arg DMA_TC_INT_CH2 + * @arg DMA_TC_INT_CH3 + * @arg DMA_TC_INT_CH4 + * @arg DMA_TC_INT_CH5 + * @arg DMA_TC_INT_CH6 + * @arg DMA_TC_INT_CH7 + * @retval en_flag_status_t + */ +en_flag_status_t DMA_GetTransIntStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32TransInt) +{ + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransInt)); + return (READ_REG32_BIT(DMAx->INTSTAT1, u32TransInt) ? Set : Reset); +} + +/** + * @brief Clear DMA transfer IRQ status. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32TransInt DMA transfer IRQ flag. + * @arg DMA_BTC_INT_CH0 + * @arg DMA_BTC_INT_CH1 + * @arg DMA_BTC_INT_CH2 + * @arg DMA_BTC_INT_CH3 + * @arg DMA_BTC_INT_CH4 + * @arg DMA_BTC_INT_CH5 + * @arg DMA_BTC_INT_CH6 + * @arg DMA_BTC_INT_CH7 + * @arg DMA_TC_INT_CH0 + * @arg DMA_TC_INT_CH1 + * @arg DMA_TC_INT_CH2 + * @arg DMA_TC_INT_CH3 + * @arg DMA_TC_INT_CH4 + * @arg DMA_TC_INT_CH5 + * @arg DMA_TC_INT_CH6 + * @arg DMA_TC_INT_CH7 + * @retval None + */ +void DMA_ClearTransIntStatus(M4_DMA_TypeDef *DMAx, uint32_t u32TransInt) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_INT(u32TransInt)); + + SET_REG32_BIT(DMAx->INTCLR1, u32TransInt); +} + +/** + * @brief DMA multiplex channel function config. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8MxCh DMA multiplex channel. + * @arg DMA_MX_CH0. + * @arg DMA_MX_CH1. + * @arg DMA_MX_CH2. + * @arg DMA_MX_CH3. + * @arg DMA_MX_CH4. + * @arg DMA_MX_CH5. + * @arg DMA_MX_CH6. + * @arg DMA_MX_CH7. + * @arg DMA_MX_CH_ALL. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void DMA_MxChannelCmd(M4_DMA_TypeDef *DMAx, uint8_t u8MxCh, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_MX_CH(u8MxCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(DMAx->CHEN, u8MxCh); + } + else + { + SET_REG32_BIT(DMAx->CHENCLR, u8MxCh); + } +} + +/** + * @brief DMA channel function config. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void DMA_ChannelCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(DMAx->CHEN, ((1UL << u8Ch) & 0xFFUL)); + } + else + { + SET_REG32_BIT(DMAx->CHENCLR, ((1UL << u8Ch) & 0xFFUL)); + } +} + +/** + * @brief Get DMA request status. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32Status DMA request status. + * @arg DMA_REQ_CH0. + * @arg DMA_REQ_CH1. + * @arg DMA_REQ_CH2. + * @arg DMA_REQ_CH3. + * @arg DMA_REQ_CH4. + * @arg DMA_REQ_CH5. + * @arg DMA_REQ_CH6. + * @arg DMA_REQ_CH7. + * @arg DMA_REQ_RECONFIG. + * @retval en_flag_status_t + */ +en_flag_status_t DMA_GetReqStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_REQ_STAT(u32Status)); + + return (READ_REG32_BIT(DMAx->REQSTAT, u32Status) ? Set : Reset); +} + +/** + * @brief Get DMA transfer status. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u32Status DMA transfer status. + * @arg DMA_TRANS_CH0. + * @arg DMA_TRANS_CH1. + * @arg DMA_TRANS_CH2. + * @arg DMA_TRANS_CH3. + * @arg DMA_TRANS_CH4. + * @arg DMA_TRANS_CH5. + * @arg DMA_TRANS_CH6. + * @arg DMA_TRANS_CH7. + * @arg DMA_TRANS_RECONFIG. + * @arg DMA_TRANS_DMA. + * @retval en_flag_status_t + */ +en_flag_status_t DMA_GetTransStatus(const M4_DMA_TypeDef *DMAx, uint32_t u32Status) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_TRANS_STAT(u32Status)); + + return (READ_REG32_BIT(DMAx->CHSTAT, u32Status) ? Set : Reset); +} + +/** + * @brief DMA re-config mode trigger source. + * @param [in] enSrc DMA transfer trigger source. + * @arg This parameter can be @ref en_event_src_t + * @retval None + * @note This register belongs to AOS module, please ensure enable it in advance. + * DMA1 and DMA2 share this register. + */ +void DMA_SetReConfigTriggerSrc(en_event_src_t enSrc) +{ + MODIFY_REG32(M4_AOS->DMA_TRGSELRC, AOS_DMA_TRGSELRC_TRGSEL, enSrc); +} + +/** + * @brief AOS common trigger function config for DMA re-config mode. + * @param [in] u32ComTrig Common trigger event enable. + * This parameter can be one of the following values: + * @arg DMA_COM_TRIG1: Common trigger event 1 . + * @arg DMA_COM_TRIG2: Common trigger event 2. + * @param [in] enNewState New state of common trigger function. + * @retval None + * @note This register belongs to AOS module, please ensure enable it in advance. + */ +void DMA_RCComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_DMA_COM_TRIG(u32ComTrig)); + + if (Enable == enNewState) + { + SET_REG32_BIT(M4_AOS->DMA_TRGSELRC, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(M4_AOS->DMA_TRGSELRC, u32ComTrig); + } +} + +/** + * @brief Config DMA transfer trigger source. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] enSrc DMA transfer trigger source. + * @arg This parameter can be @ref en_event_src_t + * @retval None + * @note This register belongs to AOS module, please ensure enable it in advance. + */ +void DMA_SetTriggerSrc(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_event_src_t enSrc) +{ + __IO uint32_t *TRGSELx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (M4_DMA1 == DMAx) + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA_1_TRGSEL0) + u8Ch*4UL); + } + else + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA_2_TRGSEL0) + u8Ch*4UL); + } + MODIFY_REG32(*TRGSELx, AOS_DMA_1_TRGSEL_TRGSEL, enSrc); +} + +/** + * @brief AOS common trigger function config for DMA + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32ComTrig Common trigger event enable. + * This parameter can be one of the following values: + * @arg DMA_COM_TRIG1: Common trigger event 1 . + * @arg DMA_COM_TRIG2: Common trigger event 2. + * @param [in] enNewState New state of common trigger function. + * @retval None + * @note This register belongs to AOS module, please ensure enable it in advance. + */ +void DMA_ComTriggerCmd(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + __IO uint32_t *TRGSELx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_DMA_COM_TRIG(u32ComTrig)); + + if (M4_DMA1 == DMAx) + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA_1_TRGSEL0) + u8Ch*4UL); + } + else + { + TRGSELx = (uint32_t *)((uint32_t)(&M4_AOS->DMA_2_TRGSEL0) + u8Ch*4UL); + } + + if (Enable == enNewState) + { + SET_REG32_BIT(*TRGSELx, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(*TRGSELx, u32ComTrig); + } +} + +/** + * @brief Config DMA source address. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32Addr DMA source address. + * @retval None + */ +void DMA_SetSrcAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), u32Addr); +} + +/** + * @brief Config DMA destination address. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32Addr DMA destination address. + * @retval None + */ +void DMA_SetDestAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Addr) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), u32Addr); +} + +/** + * @brief Config DMA transfer count. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u16Cnt DMA transfer count (0: infinite, 1 ~ 65535). + * @retval None + */ +void DMA_SetTransCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Cnt) +{ + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_CNT, ((uint32_t)(u16Cnt) << DMA_DTCTL_CNT_POS)); +} + +/** + * @brief Config DMA block size per transfer. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u16Size DMA block size (0, 1024: 1024, 1 ~ 1023). + * @retval None + */ +void DMA_SetBlockSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + __IO uint32_t *DTCTLx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLKSZ(u16Size)); + + DTCTLx = &DMA_CH_REG(DMAx->DTCTL0, u8Ch); + MODIFY_REG32(*DTCTLx, DMA_DTCTL_BLKSIZE, ((uint32_t)u16Size << DMA_DTCTL_BLKSIZE_POS)); +} + +/** + * @brief Config DMA source repeat size. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u16Size DMA source repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval None + */ +void DMA_SetSrcRptSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + __IO uint32_t *RPTx; + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLKSZ(u16Size)); + + RPTx = &DMA_CH_REG(DMAx->RPT0, u8Ch); + MODIFY_REG32(*RPTx, DMA_RPT_SRPT, ((uint32_t)(u16Size) << DMA_RPT_SRPT_POS)); +} + +/** + * @brief Config DMA destination repeat size. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u16Size DMA destination repeat size (0, 1024: 1024, 1 ~ 1023). + * @retval None + */ +void DMA_SetDestRptSize(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint16_t u16Size) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_BLKSZ(u16Size)); + + MODIFY_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), DMA_RPT_DRPT, ((uint32_t)(u16Size) << DMA_RPT_DRPT_POS)); +} + +/** + * @brief Config DMA source transfter count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32Cnt DMA source transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval None + */ +void DMA_SetNonSeqSrcCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Cnt) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NS_TRANSCNT(u32Cnt)); + + MODIFY_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), DMA_SNSEQCTLB_SNSCNTB, (u32Cnt << DMA_SNSEQCTLB_SNSCNTB_POS)); +} + +/** + * @brief Config DMA destination transfter count under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32Cnt DMA destination transfer count (0, 4096: 4096, 1 ~ 4095). + * @retval None + */ +void DMA_SetNonSeqDestCnt(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Cnt) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NS_TRANSCNT(u32Cnt)); + + MODIFY_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), DMA_DNSEQCTL_DNSCNT, (u32Cnt << DMA_DNSEQCTL_DNSCNT_POS)); +} + +/** + * @brief Config DMA source offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32Ofs DMA source offset (0 ~ 2^20 - 1). + * @retval None + */ +void DMA_SetNonSeqSrcOffset(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Ofs) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NS_OFFSET(u32Ofs)); + + MODIFY_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET, u32Ofs); +} + +/** + * @brief Config DMA destination offset number under non-sequence mode. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32Ofs DMA destination offset (0 ~ 2^20 - 1). + * @retval None + */ +void DMA_SetNonSeqDestOffset(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32Ofs) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_NS_OFFSET(u32Ofs)); + + MODIFY_REG32(DMA_CH_REG(DMAx->DNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET, u32Ofs); +} + +/** + * @brief Initialize DMA config structure. Fill each pstcDmaInit with default value + * @param [in] pstcDmaInit Pointer to a stc_dma_init_t structure that + * contains configuration information. + * @retval Ok: DMA structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_StructInit(stc_dma_init_t *pstcDmaInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcDmaInit->u32IntEn = DMA_INT_ENABLE; + pstcDmaInit->u32SrcAddr = 0x00UL; + pstcDmaInit->u32DestAddr = 0x00UL; + pstcDmaInit->u32DataWidth = DMA_DATAWIDTH_8BIT; + pstcDmaInit->u32BlockSize = 0x00UL; + pstcDmaInit->u32TransCnt = 0x01UL; + pstcDmaInit->u32SrcInc = DMA_SRC_ADDR_FIX; + pstcDmaInit->u32DestInc = DMA_DEST_ADDR_FIX; + } + return enRet; +} + +/** + * @brief DMA basic function initialize. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] pstcDmaInit DMA config structure. + * @arg u32IntEn DMA interrupt enable or disable. + * @arg u32SrcAddr DMA source address. + * @arg u32DestAddr DMA destination address. + * @arg u32DataWidth DMA data width. + * @arg u32BlockSize DMA block size. + * @arg u32TransferCnt DMA transfer count. + * @arg u32SrcInc DMA source address direction. + * @arg u32DestInc DMA destination address direction. + * @retval Ok: DMA basic function initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_Init(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_init_t *pstcDmaInit) +{ + en_result_t enRet = Ok; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_DMA_INT_FUNC(pstcDmaInit->u32IntEn)); + DDL_ASSERT(IS_DMA_DATA_WIDTH(pstcDmaInit->u32DataWidth)); + DDL_ASSERT(IS_DMA_SADDR_MODE(pstcDmaInit->u32SrcInc)); + DDL_ASSERT(IS_DMA_DADDR_MODE(pstcDmaInit->u32DestInc)); + DDL_ASSERT(IS_DMA_BLKSZ(pstcDmaInit->u32BlockSize)); + + WRITE_REG32(DMA_CH_REG(DMAx->SAR0, u8Ch), pstcDmaInit->u32SrcAddr); + WRITE_REG32(DMA_CH_REG(DMAx->DAR0, u8Ch), pstcDmaInit->u32DestAddr); + WRITE_REG32(DMA_CH_REG(DMAx->DTCTL0, u8Ch), (pstcDmaInit->u32BlockSize| \ + (pstcDmaInit->u32TransCnt << DMA_DTCTL_CNT_POS))); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, \ + (DMA_CHCTL_SINC | DMA_CHCTL_DINC | DMA_CHCTL_HSIZE | DMA_CHCTL_IE), \ + (pstcDmaInit->u32IntEn | pstcDmaInit->u32DataWidth | \ + pstcDmaInit->u32SrcInc | pstcDmaInit->u32DestInc)); + } + return enRet; +} + +/** + * @brief Initialize DMA repeat mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaRptInit Pointer to a stc_dma_rpt_init_t structure that + * contains configuration information. + * @retval Ok: DMA repeat mode config structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_RepeatStructInit(stc_dma_rpt_init_t *pstcDmaRptInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaRptInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcDmaRptInit->u32SrcRptEn = DMA_SRC_RPT_DISABLE; + pstcDmaRptInit->u32SrcRptSize = 0x00UL; + pstcDmaRptInit->u32DestRptEn = DMA_DEST_RPT_DISABLE; + pstcDmaRptInit->u32DestRptSize = 0x00UL; + } + return enRet; +} + +/** + * @brief DMA repeat mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] pstcDmaRptInit DMA repeat mode config structure. + * @arg u32SrcRptEn DMA source repeat enable or disable. + * @arg u32SrcRptSize DMA source repeat size. + * @arg u32DestRptEn DMA destination repeat enable or disable. + * @arg u32DestRptSize DMA destination repeat size. + * @retval Ok: DMA repeat function initialize successful + * ErrorInvalidParameter: NULL pointer + * @note Call this function after DMA_Init(); + */ +en_result_t DMA_RepeatInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_rpt_init_t *pstcDmaRptInit) +{ + en_result_t enRet = Ok; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRptInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_DMA_SRC_RPT(pstcDmaRptInit->u32SrcRptEn)); + DDL_ASSERT(IS_DMA_DEST_RPT(pstcDmaRptInit->u32DestRptEn)); + DDL_ASSERT(IS_DMA_BLKSZ(pstcDmaRptInit->u32DestRptSize)); + DDL_ASSERT(IS_DMA_BLKSZ(pstcDmaRptInit->u32SrcRptSize)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, \ + (DMA_CHCTL_SRTPEN | DMA_CHCTL_DRPTEN), \ + (pstcDmaRptInit->u32SrcRptEn | pstcDmaRptInit->u32DestRptEn)); + + WRITE_REG32(DMA_CH_REG(DMAx->RPT0, u8Ch), \ + ((pstcDmaRptInit->u32DestRptSize << DMA_RPT_DRPT_POS) | \ + pstcDmaRptInit->u32SrcRptSize)); + } + return enRet; +} + +/** + * @brief Initialize DMA non-sequence mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaNonSeqInit Pointer to a stc_dma_nonseq_init_t structure that + * contains configuration information. + * @retval Ok: DMA non-sequence mode structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_NonSeqStructInit(stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaNonSeqInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcDmaNonSeqInit->u32SrcNonSeqEn = DMA_SRC_NS_DISABLE; + pstcDmaNonSeqInit->u32SrcNonSeqCnt = 0x00UL; + pstcDmaNonSeqInit->u32SrcNonSeqOfs = 0x00UL; + pstcDmaNonSeqInit->u32DestNonSeqEn = DMA_DEST_NS_DISABLE; + pstcDmaNonSeqInit->u32DestNonSeqCnt = 0x00UL; + pstcDmaNonSeqInit->u32DestNonSeqOfs = 0x00UL; + } + return enRet; +} + +/** + * @brief DMA non-sequence mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] pstcDmaNonSeqInit DMA non-sequence mode config structure. + * @arg u32SrcNonSeqEn DMA source non-sequence enable or disable. + * @arg u32SrcNonSeqCnt DMA source non-sequence count. + * @arg u32SrcNonSeqOfs DMA source non-sequence offset. + * @arg u32DestNonSeqEn DMA destination non-sequence enable or disable. + * @arg u32DestNonSeqCnt DMA destination non-sequence count. + * @arg u32DestNonSeqOfs DMA destination non-sequence offset. + * @retval Ok: DMA non-sequence function initialize successful + * ErrorInvalidParameter: NULL pointer + * @note Call this function after DMA_Init(); + */ +en_result_t DMA_NonSeqInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_nonseq_init_t *pstcDmaNonSeqInit) +{ + en_result_t enRet = Ok; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaNonSeqInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_DMA_SRC_NS(pstcDmaNonSeqInit->u32SrcNonSeqEn)); + DDL_ASSERT(IS_DMA_DEST_NS(pstcDmaNonSeqInit->u32DestNonSeqEn)); + DDL_ASSERT(IS_DMA_NS_TRANSCNT(pstcDmaNonSeqInit->u32SrcNonSeqCnt)); + DDL_ASSERT(IS_DMA_NS_TRANSCNT(pstcDmaNonSeqInit->u32DestNonSeqCnt)); + DDL_ASSERT(IS_DMA_NS_OFFSET(pstcDmaNonSeqInit->u32SrcNonSeqOfs)); + DDL_ASSERT(IS_DMA_NS_OFFSET(pstcDmaNonSeqInit->u32DestNonSeqOfs)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, \ + (DMA_CHCTL_SNSEQEN | DMA_CHCTL_DNSEQEN), \ + (pstcDmaNonSeqInit->u32SrcNonSeqEn | pstcDmaNonSeqInit->u32DestNonSeqEn)); + + WRITE_REG32(DMA_CH_REG(DMAx->SNSEQCTL0, u8Ch), \ + ((pstcDmaNonSeqInit->u32SrcNonSeqCnt << DMA_SNSEQCTL_SNSCNT_POS) | \ + pstcDmaNonSeqInit->u32SrcNonSeqOfs)); + } + return enRet; +} + +/** + * @brief Initialize DMA Linked List Pointer (hereafter, LLP) mode config structure. + * Fill each pstcDmaInit with default value + * @param [in] pstcDmaLlpInit Pointer to a stc_dma_llp_init_t structure that + * contains configuration information. + * @retval Ok: DMA LLP mode config structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_LlpStructInit(stc_dma_llp_init_t *pstcDmaLlpInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaLlpInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcDmaLlpInit->u32LlpEn = DMA_LLP_DISABLE; + pstcDmaLlpInit->u32LlpRun = DMA_LLP_WAIT; + pstcDmaLlpInit->u32LlpAddr = 0x00UL; + } + return enRet; +} + +/** + * @brief DMA LLP mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] pstcDmaLlpInit DMA LLP config structure. + * @arg u32LlpEn DMA LLP enable or disable. + * @arg u32LlpRun DMA LLP auto-run or wait request. + * @arg u32LlpAddr DMA LLP next list pointer address. + * @retval Ok: DMA LLP function initialize successful + * ErrorInvalidParameter: NULL pointer + * @note Call this function after DMA_Init(); + */ +en_result_t DMA_LlpInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_llp_init_t *pstcDmaLlpInit) +{ + en_result_t enRet = Ok; + __IO uint32_t *CHCTLx; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaLlpInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_DMA_LLP_EN(pstcDmaLlpInit->u32LlpEn)); + DDL_ASSERT(IS_DMA_LLP_ADDR(pstcDmaLlpInit->u32LlpAddr)); + DDL_ASSERT(IS_DMA_LLP_MODE(pstcDmaLlpInit->u32LlpRun)); + + CHCTLx = &DMA_CH_REG(DMAx->CHCTL0, u8Ch); + MODIFY_REG32(*CHCTLx, \ + (DMA_CHCTL_LLPEN | DMA_CHCTL_LLPRUN), \ + (pstcDmaLlpInit->u32LlpEn | pstcDmaLlpInit->u32LlpRun)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), pstcDmaLlpInit->u32LlpAddr); + } + + return enRet; +} + +/** + * @brief Config DMA LLP value. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] u32LlpAddr Next link pointer address for DMA LLP mode. + * @retval None + */ +void DMA_SetLlpAddr(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, uint32_t u32LlpAddr) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_DMA_LLP_ADDR(u32LlpAddr)); + + WRITE_REG32(DMA_CH_REG(DMAx->LLP0, u8Ch), (u32LlpAddr & 0xFFFFFFFCUL)); +} + +/** + * @brief DMA LLP enable or disable. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] enNewState New state of LLP function. + * @retval None + */ +void DMA_LlpCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + } + else + { + CLEAR_REG32_BIT(DMA_CH_REG(DMAx->CHCTL0, u8Ch), DMA_CHCTL_LLPEN); + } +} + +/** + * @brief DMA reconfig function enable or disable. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] enNewState New state of reconfig function. + * @retval None + */ +void DMA_ReConfigCmd(M4_DMA_TypeDef *DMAx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(DMAx->RCFGCTL, 1UL); + } + else + { + CLEAR_REG32_BIT(DMAx->RCFGCTL, 1UL); + } +} + +/** + * @brief DMA LLP enable or disable for reconfig function. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] enNewState New state of LLP function in reconfig case. + * @retval None + */ +void DMA_ReConfigLlpCmd(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(DMAx->RCFGCTL, DMA_RCFGCTL_RCFGCHS, ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS)); + WRITE_REG32(DMAx->RCFGCTL, enNewState); +} + +/** + * @brief Initialize DMA re-config mode config structure. + * Fill each pstcDmaRCInit with default value + * @param [in] pstcDmaRCInit Pointer to a stc_dma_reconfig_init_t structure that + * contains configuration information. + * @retval Ok: DMA reconfig mode config structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_ReConfigStructInit(stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaRCInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcDmaRCInit->u32CntMode = DMA_RC_CNT_FIX; + pstcDmaRCInit->u32DestAddrMode = DMA_RC_DA_FIX; + pstcDmaRCInit->u32SrcAddrMode = DMA_RC_SA_FIX; + } + return enRet; +} + +/** + * @brief DMA reconfig mode initialize. + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @param [in] pstcDmaRCInit DMA reconfig mode config structure + * @arg u32CntMode DMA reconfig count mode. + * @arg u32DestAddrMode DMA reconfig destination address mode. + * @arg u32SrcAddrMode DMA reconfig source address mode. + * @retval Ok: DMA reconfig function initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t DMA_ReConfigInit(M4_DMA_TypeDef *DMAx, uint8_t u8Ch, const stc_dma_reconfig_init_t *pstcDmaRCInit) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + if (NULL == pstcDmaRCInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_DMA_RC_CNT_MODE(pstcDmaRCInit->u32CntMode)); + DDL_ASSERT(IS_DMA_RC_DA_MODE(pstcDmaRCInit->u32DestAddrMode)); + DDL_ASSERT(IS_DMA_RC_SA_MODE(pstcDmaRCInit->u32SrcAddrMode)); + + MODIFY_REG32(DMAx->RCFGCTL, \ + (DMA_RCFGCTL_RCFGCHS | DMA_RCFGCTL_SARMD | DMA_RCFGCTL_DARMD | \ + DMA_RCFGCTL_CNTMD), \ + (pstcDmaRCInit->u32CntMode | pstcDmaRCInit->u32SrcAddrMode | \ + pstcDmaRCInit->u32DestAddrMode | ((uint32_t)(u8Ch) << DMA_RCFGCTL_RCFGCHS_POS))); + } + return enRet; +} + +/** + * @brief DMA get current source address + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current source address. + */ +uint32_t DMA_GetSrcAddr(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONSAR0, u8Ch)); +} + +/** + * @brief DMA get current destination address + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current destination address. + */ +uint32_t DMA_GetDestAddr(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return READ_REG32(DMA_CH_REG(DMAx->MONDAR0, u8Ch)); +} + +/** + * @brief DMA get current transfer count + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current transfer count. + */ +uint32_t DMA_GetTransCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch)) >> DMA_DTCTL_CNT_POS) & 0xFFFFUL); +} + +/** + * @brief DMA get current block size + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current block size. + */ +uint32_t DMA_GetBlockSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDTCTL0, u8Ch), DMA_DTCTL_BLKSIZE)); +} + +/** + * @brief DMA get current source repeat size + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current source repeat size. + */ +uint32_t DMA_GetSrcRptSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONRPT0, u8Ch), DMA_RPT_SRPT)); +} + +/** + * @brief DMA get current destination repeat size + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current destination repeat size. + */ +uint32_t DMA_GetDestRptSize(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONRPT0, u8Ch)) >> DMA_RPT_DRPT_POS) & 0x3FFUL); +} + +/** + * @brief DMA get current source count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current source count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch)) >> DMA_SNSEQCTLB_SNSCNTB_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current destination count in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current destination count in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestCnt(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return ((READ_REG32(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch)) >> DMA_DNSEQCTL_DNSCNT_POS) & 0xFFFUL); +} + +/** + * @brief DMA get current source offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current source offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqSrcOffset(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONSNSEQCTL0, u8Ch), DMA_SNSEQCTL_SOFFSET)); +} + +/** + * @brief DMA get current destination offset in non-sequence mode + * @param [in] DMAx DMA unit instance. + * @arg M4_DMA1 Unit1. + * @arg M4_DMA2 Unit2. + * @param [in] u8Ch DMA channel. + * @arg DMA_CH0. + * @arg DMA_CH1. + * @arg DMA_CH2. + * @arg DMA_CH3. + * @arg DMA_CH4. + * @arg DMA_CH5. + * @arg DMA_CH6. + * @arg DMA_CH7. + * @retval Current destination offset in non-sequence mode. + */ +uint32_t DMA_GetNonSeqDestOffset(const M4_DMA_TypeDef *DMAx, uint8_t u8Ch) +{ + DDL_ASSERT(IS_DMA_UNIT(DMAx)); + DDL_ASSERT(IS_DMA_CH(u8Ch)); + + return (READ_REG32_BIT(DMA_CH_REG(DMAx->MONDNSEQCTL0, u8Ch), DMA_DNSEQCTL_DOFFSET)); +} + +/** + * @} + */ + +#endif /* DDL_DMA_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dmc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dmc.c new file mode 100644 index 0000000000000000000000000000000000000000..c5a813b13587dd235a6c9e7d20162cd5526dbe45 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dmc.c @@ -0,0 +1,561 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dmc.c + * @brief This file provides firmware functions to manage the EXMC DMC + * (External Memory Controller: Dynamic Memory Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-14 Hongjh Merge API from EXMC_DMC_Enable/Disable to EXMC_DMC_Cmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_dmc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_EXMC_DMC EXMC_DMC + * @brief Dynamic Memory Controller Driver Library + * @{ + */ + +#if (DDL_DMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Local_Macros Dynamic Memory Controller Local Macros + * @{ + */ + +/** + * @defgroup EXMC_DMC_Check_Parameters_Validity EXMC DMC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_DMC_MEM_WIDTH(x) \ +( (EXMC_DMC_MEMORY_WIDTH_16BIT == (x)) || \ + (EXMC_DMC_MEMORY_WIDTH_32BIT == (x))) + +#define IS_EXMC_DMC_CHIP(x) \ +( (EXMC_DMC_CHIP_0 == (x)) || \ + (EXMC_DMC_CHIP_1 == (x)) || \ + (EXMC_DMC_CHIP_2 == (x)) || \ + (EXMC_DMC_CHIP_3 == (x))) + +#define IS_EXMC_DMC_BANK(x) \ +( (EXMC_DMC_BANK_0 == (x)) || \ + (EXMC_DMC_BANK_1 == (x)) || \ + (EXMC_DMC_BANK_2 == (x)) || \ + (EXMC_DMC_BANK_3 == (x))) + +#define IS_EXMC_DMC_CMD(x) \ +( (EXMC_DMC_CMD_PRECHARGEALL == (x)) || \ + (EXMC_DMC_CMD_AUTOREFRESH == (x)) || \ + (EXMC_DMC_CMD_MDREGCONFIG == (x)) || \ + (EXMC_DMC_CMD_NOP == (x))) + +#define IS_EXMC_DMC_CS_DECODE_MODE(x) \ +( (EXMC_DMC_CS_DECODE_ROWBANKCOL == (x)) || \ + (EXMC_DMC_CS_DECODE_BANKROWCOL == (x))) + +#define IS_EXMC_DMC_COLUMN_BITS_NUM(x) \ +( (EXMC_DMC_COLUMN_BITS_NUM_8 == (x)) || \ + (EXMC_DMC_COLUMN_BITS_NUM_9 == (x)) || \ + (EXMC_DMC_COLUMN_BITS_NUM_10 == (x)) || \ + (EXMC_DMC_COLUMN_BITS_NUM_11 == (x)) || \ + (EXMC_DMC_COLUMN_BITS_NUM_12 == (x))) + +#define IS_EXMC_DMC_ROW_BITS_NUM(x) \ +( (EXMC_DMC_ROW_BITS_NUM_11 == (x)) || \ + (EXMC_DMC_ROW_BITS_NUM_12 == (x)) || \ + (EXMC_DMC_ROW_BITS_NUM_13 == (x)) || \ + (EXMC_DMC_ROW_BITS_NUM_14 == (x)) || \ + (EXMC_DMC_ROW_BITS_NUM_15 == (x)) || \ + (EXMC_DMC_ROW_BITS_NUM_16 == (x))) + +#define IS_EXMC_DMC_AUTO_PRECHARGE_PIN(x) \ +( (EXMC_DMC_AUTO_PRECHARGE_A8 == (x)) || \ + (EXMC_DMC_AUTO_PRECHARGE_A10 == (x))) + +#define IS_EXMC_DMC_CKE_OUTPUT_SEL(x) \ +( (EXMC_DMC_CKE_OUTPUT_ENABLE == (x)) || \ + (EXMC_DMC_CKE_OUTPUT_DISABLE == (x))) + +#define EXMC_DMC_MEMCLK_SEL(x) \ +( (EXMC_DMC_MEMCLK_NORMAL_OUTPUT == (x)) || \ + (EXMC_DMC_MEMCLK_NOP_STOP_OUTPUT == (x))) + +#define IS_EXMC_DMC_MEM_BURST(x) \ +( (EXMC_DMC_MEM_BURST_1 == (x)) || \ + (EXMC_DMC_MEM_BURST_2 == (x)) || \ + (EXMC_DMC_MEM_BURST_4 == (x)) || \ + (EXMC_DMC_MEM_BURST_8 == (x)) || \ + (EXMC_DMC_MEM_BURST_16 == (x))) + +#define IS_EXMC_DMC_AUTO_REFRESH_CHIPS(x) \ +( (EXMC_DMC_AUTO_REFRESH_CHIP_0 == (x)) || \ + (EXMC_DMC_AUTO_REFRESH_CHIPS_01 == (x)) || \ + (EXMC_DMC_AUTO_REFRESH_CHIPS_012 == (x)) || \ + (EXMC_DMC_AUTO_REFRESH_CHIPS_0123 == (x))) + +#define IS_EXMC_DMC_CS_ADDRESS_MASK(x) \ +( (EXMC_DMC_ADDR_MASK_16MB == (x)) || \ + (EXMC_DMC_ADDR_MASK_32MB == (x)) || \ + (EXMC_DMC_ADDR_MASK_64MB == (x)) || \ + (EXMC_DMC_ADDR_MASK_128MB == (x))) + +#define IS_EXMC_DMC_CS_ADDRESS_MATCH(x) \ +( (EXMC_DMC_ADDR_MATCH_0X80000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X81000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X82000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X83000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X84000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X85000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X86000000 == (x)) || \ + (EXMC_DMC_ADDR_MATCH_0X87000000 == (x))) + +#define IS_EXMC_DMC_ADDRESS(match, mask) \ +( (~((((mask) >> DMC_CSCR_ADDMSK_POS) ^ ((match) >> DMC_CSCR_ADDMAT_POS)) << 24UL)) <= 0x87FFFFFFUL) + +#define IS_EXMC_DMC_STATE(x) \ +( (EXMC_DMC_CTL_STATE_GO == (x)) || \ + (EXMC_DMC_CTL_STATE_SLEEP == (x)) || \ + (EXMC_DMC_CTL_STATE_WAKEUP == (x)) || \ + (EXMC_DMC_CTL_STATE_PAUSE == (x)) || \ + (EXMC_DMC_CTL_STATE_CONFIGURE == (x))) + +#define IS_EXMC_DMC_TIMING_CASL_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_DQSS_CYCLE(x) ((x) <= 3UL) + +#define IS_EXMC_DMC_TIMING_MRD_CYCLE(x) ((x) <= 0x7FUL) + +#define IS_EXMC_DMC_TIMING_RAS_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_DMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_DMC_TIMING_RCD_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_RFC_CYCLE(x) ((x) <= 0x1FUL) + +#define IS_EXMC_DMC_TIMING_RP_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_RRD_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_DMC_TIMING_WR_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_WTR_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_DMC_TIMING_XP_CYCLE(x) ((x) <= 0xFFUL) + +#define IS_EXMC_DMC_TIMING_XSR_CYCLE(x) ((x) <= 0xFFUL) + +#define IS_EXMC_DMC_TIMING_ESR_CYCLE(x) ((x) <= 0xFFUL) + +#define IS_EXMC_DMC_CKE_DISABLE_PERIOD(x) ((x) <= 0x3FUL) + +#define IS_EXMC_DMC_CMDADD(x) ((x) <= 0x7FFFUL) + +#define IS_EXMC_DMC_REFRESH_PERIOD(x) ((x) <= 0x7FFFUL) + +/** + * @} + */ + +/** + * @defgroup EXMC_DMC_Register EXMC DMC Register + * @{ + */ +#define EXMC_DMC_CSCRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&M4_DMC->CSCR0)) + (4UL * (__CHIPx__)))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EXMC_DMC_Global_Functions Dynamic Memory Controller Global Functions + * @{ + */ + +/** + * @brief Initialize EXMC DMC function. + * @param [in] pstcInit Pointer to a @ref stc_exmc_dmc_init_t structure (EXMC DMC function configuration structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EXMC_DMC_Init(const stc_exmc_dmc_init_t *pstcInit) +{ + uint32_t u32RegVal; + en_result_t enRet = ErrorInvalidParameter; + + /* Check the pointer pstcInit */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_DMC_MEM_WIDTH(pstcInit->u32DmcMemWidth)); + DDL_ASSERT(IS_EXMC_DMC_REFRESH_PERIOD(pstcInit->u32RefreshPeriod)); + DDL_ASSERT(IS_EXMC_DMC_COLUMN_BITS_NUM(pstcInit->stcChipCfg.u32ColumnBitsNumber)); + DDL_ASSERT(IS_EXMC_DMC_ROW_BITS_NUM(pstcInit->stcChipCfg.u32RowBitsNumber)); + DDL_ASSERT(IS_EXMC_DMC_AUTO_PRECHARGE_PIN(pstcInit->stcChipCfg.u32AutoPrechargePin)); + DDL_ASSERT(IS_EXMC_DMC_CKE_OUTPUT_SEL(pstcInit->stcChipCfg.u32CkeOutputSel)); + DDL_ASSERT(EXMC_DMC_MEMCLK_SEL(pstcInit->stcChipCfg.u32MemClkSel)); + DDL_ASSERT(IS_EXMC_DMC_CKE_DISABLE_PERIOD(pstcInit->stcChipCfg.u32CkeDisablePeriod)); + DDL_ASSERT(IS_EXMC_DMC_MEM_BURST(pstcInit->stcChipCfg.u32MemBurst)); + DDL_ASSERT(IS_EXMC_DMC_AUTO_REFRESH_CHIPS(pstcInit->stcChipCfg.u32AutoRefreshChips)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_CASL_CYCLE(pstcInit->stcTimingCfg.u32CASL)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_DQSS_CYCLE(pstcInit->stcTimingCfg.u32DQSS)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_MRD_CYCLE(pstcInit->stcTimingCfg.u32MRD)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RAS_CYCLE(pstcInit->stcTimingCfg.u32RAS)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RC_CYCLE(pstcInit->stcTimingCfg.u32RC)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RCD_CYCLE(pstcInit->stcTimingCfg.u32RCD)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RFC_CYCLE(pstcInit->stcTimingCfg.u32RFC)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RP_CYCLE(pstcInit->stcTimingCfg.u32RP)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_RRD_CYCLE(pstcInit->stcTimingCfg.u32RRD)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_WR_CYCLE(pstcInit->stcTimingCfg.u32WR)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_WTR_CYCLE(pstcInit->stcTimingCfg.u32WTR)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_XP_CYCLE(pstcInit->stcTimingCfg.u32XP)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_XSR_CYCLE(pstcInit->stcTimingCfg.u32XSR)); + DDL_ASSERT(IS_EXMC_DMC_TIMING_ESR_CYCLE(pstcInit->stcTimingCfg.u32ESR)); + + /* Set memrory width(16bit or 32bit) for DMC.*/ + MODIFY_REG32(M4_DMC->BACR, DMC_BACR_DMCMW, pstcInit->u32DmcMemWidth); + + /* set auto refresh period*/ + WRITE_REG32(M4_DMC->RFTR, pstcInit->u32RefreshPeriod); + + /* Set timing parameters for DMC.*/ + WRITE_REG32(M4_DMC->TMCR_T_CASL, pstcInit->stcTimingCfg.u32CASL); + WRITE_REG32(M4_DMC->TMCR_T_DQSS, pstcInit->stcTimingCfg.u32DQSS); + WRITE_REG32(M4_DMC->TMCR_T_MRD, pstcInit->stcTimingCfg.u32MRD); + WRITE_REG32(M4_DMC->TMCR_T_RAS, pstcInit->stcTimingCfg.u32RAS); + WRITE_REG32(M4_DMC->TMCR_T_RC, pstcInit->stcTimingCfg.u32RC); + WRITE_REG32(M4_DMC->TMCR_T_RRD, pstcInit->stcTimingCfg.u32RRD); + WRITE_REG32(M4_DMC->TMCR_T_WR, pstcInit->stcTimingCfg.u32WR); + WRITE_REG32(M4_DMC->TMCR_T_WTR, pstcInit->stcTimingCfg.u32WTR); + WRITE_REG32(M4_DMC->TMCR_T_XP, pstcInit->stcTimingCfg.u32XP); + WRITE_REG32(M4_DMC->TMCR_T_XSR, pstcInit->stcTimingCfg.u32XSR); + WRITE_REG32(M4_DMC->TMCR_T_ESR, pstcInit->stcTimingCfg.u32ESR); + MODIFY_REG32(M4_DMC->TMCR_T_RP, DMC_TMCR_T_RP_T_RP, pstcInit->stcTimingCfg.u32RP); + MODIFY_REG32(M4_DMC->TMCR_T_RCD, DMC_TMCR_T_RCD_T_RCD, pstcInit->stcTimingCfg.u32RCD); + MODIFY_REG32(M4_DMC->TMCR_T_RFC, DMC_TMCR_T_RFC_T_RFC, pstcInit->stcTimingCfg.u32RFC); + + /* Set base parameters for DMC: burst lenth, Rowbitwidth,ColbitWidth etc.*/ + u32RegVal = (pstcInit->stcChipCfg.u32ColumnBitsNumber | \ + pstcInit->stcChipCfg.u32RowBitsNumber | \ + pstcInit->stcChipCfg.u32AutoPrechargePin | \ + pstcInit->stcChipCfg.u32CkeOutputSel | \ + pstcInit->stcChipCfg.u32MemClkSel | \ + (pstcInit->stcChipCfg.u32CkeDisablePeriod << DMC_CPCR_CKEDISPRD_POS) | \ + pstcInit->stcChipCfg.u32MemBurst | \ + pstcInit->stcChipCfg.u32AutoRefreshChips); + WRITE_REG32(M4_DMC->CPCR, u32RegVal); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize EXMC DMC function. + * @param None + * @retval None + */ +void EXMC_DMC_DeInit(void) +{ + /* Disable */ + WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.DMCEN, 0UL); + + /* Configures the registers to reset value. */ + WRITE_REG32(M4_DMC->CPCR, 0x00020040UL); + + WRITE_REG32(M4_DMC->TMCR_T_CASL, 0x00000003UL); + WRITE_REG32(M4_DMC->TMCR_T_DQSS, 0x00000001UL); + WRITE_REG32(M4_DMC->TMCR_T_MRD, 0x00000002UL); + WRITE_REG32(M4_DMC->TMCR_T_RAS, 0x00000007UL); + WRITE_REG32(M4_DMC->TMCR_T_RC, 0x0000000BUL); + WRITE_REG32(M4_DMC->TMCR_T_RCD, 0x00000035UL); + WRITE_REG32(M4_DMC->TMCR_T_RFC, 0x00001012UL); + WRITE_REG32(M4_DMC->TMCR_T_RP, 0x00000035UL); + WRITE_REG32(M4_DMC->TMCR_T_RRD, 0x00000002UL); + WRITE_REG32(M4_DMC->TMCR_T_WR, 0x00000003UL); + WRITE_REG32(M4_DMC->TMCR_T_WTR, 0x00000002UL); + WRITE_REG32(M4_DMC->TMCR_T_XP, 0x00000001UL); + WRITE_REG32(M4_DMC->TMCR_T_XSR, 0x0000000AUL); + WRITE_REG32(M4_DMC->TMCR_T_ESR, 0x00000014UL); +} + +/** + * @brief Set the fields of structure stc_exmc_dmc_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_exmc_dmc_init_t structure (EXMC DMC function configuration structure) + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EXMC_DMC_StructInit(stc_exmc_dmc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + pstcInit->u32DmcMemWidth = EXMC_DMC_MEMORY_WIDTH_16BIT; + pstcInit->u32RefreshPeriod = 0xA60UL; + pstcInit->stcChipCfg.u32ColumnBitsNumber = EXMC_DMC_COLUMN_BITS_NUM_8; + pstcInit->stcChipCfg.u32RowBitsNumber = EXMC_DMC_ROW_BITS_NUM_15; + pstcInit->stcChipCfg.u32AutoPrechargePin = EXMC_DMC_AUTO_PRECHARGE_A10; + pstcInit->stcChipCfg.u32CkeOutputSel = EXMC_DMC_CKE_OUTPUT_ENABLE; + pstcInit->stcChipCfg.u32MemClkSel = EXMC_DMC_MEMCLK_NORMAL_OUTPUT; + pstcInit->stcChipCfg.u32CkeDisablePeriod = 0UL; + pstcInit->stcChipCfg.u32MemBurst = EXMC_DMC_MEM_BURST_4; + pstcInit->stcChipCfg.u32AutoRefreshChips = EXMC_DMC_AUTO_REFRESH_CHIP_0; + + pstcInit->stcTimingCfg.u32CASL = 0x3UL; + pstcInit->stcTimingCfg.u32DQSS = 0x1UL; + pstcInit->stcTimingCfg.u32MRD = 0x02UL; + pstcInit->stcTimingCfg.u32RAS = 0x07UL; + pstcInit->stcTimingCfg.u32RC = 0x0BUL; + pstcInit->stcTimingCfg.u32RCD = 0x05UL; + pstcInit->stcTimingCfg.u32RFC = 0x12UL; + pstcInit->stcTimingCfg.u32RP = 0x05UL; + pstcInit->stcTimingCfg.u32RRD = 0x02UL; + pstcInit->stcTimingCfg.u32WR = 0x03UL; + pstcInit->stcTimingCfg.u32WTR = 0x02UL; + pstcInit->stcTimingCfg.u32XP = 0x01UL; + pstcInit->stcTimingCfg.u32XSR = 0x0AUL; + pstcInit->stcTimingCfg.u32ESR = 0x14UL; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable/disable DMC. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void EXMC_DMC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.DMCEN, enNewState); +} + +/** + * @brief Configure EXMC DMC CS function. + * @param [in] u32Chip The command chip number. + * This parameter can be one of the following values: + * @arg EXMC_DMC_CHIP_0: Chip 0 + * @arg EXMC_DMC_CHIP_1: Chip 1 + * @arg EXMC_DMC_CHIP_2: Chip 2 + * @arg EXMC_DMC_CHIP_3: Chip 3 + * @param [in] pstcCfg Pointer to a @ref stc_exmc_dmc_cs_cfg_t structure (EXMC DMC CS function configuration structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: pstcCfg = NULL + */ +en_result_t EXMC_DMC_CsConfig(uint32_t u32Chip, + const stc_exmc_dmc_cs_cfg_t *pstcCfg) +{ + uint32_t u32RegVal; + __IO uint32_t *DMC_CSCRx; + en_result_t enRet = ErrorInvalidParameter; + + /* Check the pointer pstcInit */ + if (NULL != pstcCfg) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_DMC_CS_ADDRESS_MASK(pstcCfg->u32AddrMask)); + DDL_ASSERT(IS_EXMC_DMC_CS_ADDRESS_MATCH(pstcCfg->u32AddrMatch)); + DDL_ASSERT(IS_EXMC_DMC_CS_DECODE_MODE(pstcCfg->u32AddrDecodeMode)); + DDL_ASSERT(IS_EXMC_DMC_ADDRESS(pstcCfg->u32AddrMatch, pstcCfg->u32AddrMask)); + + /* Set chip selection for DMC.*/ + DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip); + u32RegVal = (pstcCfg->u32AddrMask | pstcCfg->u32AddrMatch | pstcCfg->u32AddrDecodeMode); + WRITE_REG32(*DMC_CSCRx, u32RegVal); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Get the start address of the specified DMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_DMC_CHIP_0: Chip 0 + * @arg EXMC_DMC_CHIP_1: Chip 1 + * @arg EXMC_DMC_CHIP_2: Chip 2 + * @arg EXMC_DMC_CHIP_3: Chip 3 + * @retval The start address of the specified DMC chip. + */ +uint32_t EXMC_DMC_ChipStartAddress(uint32_t u32Chip) +{ + __IO uint32_t *DMC_CSCRx; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + + DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip); + return (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMAT) << 16UL); +} + +/** + * @brief Get the end address of the specified DMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_DMC_CHIP_0: Chip 0 + * @arg EXMC_DMC_CHIP_1: Chip 1 + * @arg EXMC_DMC_CHIP_2: Chip 2 + * @arg EXMC_DMC_CHIP_3: Chip 3 + * @retval The end address of the specified DMC chip + */ +uint32_t EXMC_DMC_ChipEndAddress(uint32_t u32Chip) +{ + uint32_t u32Mask; + uint32_t u32Match; + __IO uint32_t *DMC_CSCRx; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + + DMC_CSCRx = EXMC_DMC_CSCRx(u32Chip); + u32Mask = (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMSK) >> DMC_CSCR_ADDMSK_POS); + u32Match = (READ_REG32_BIT(*DMC_CSCRx, DMC_CSCR_ADDMAT) >> DMC_CSCR_ADDMAT_POS); + + return (~((u32Match ^ u32Mask) << 24UL)); +} + +/** + * @brief Set EXMC SMC command. + * @param [in] u32Chip The command chip number. + * This parameter can be one of the following values: + * @arg EXMC_DMC_CHIP_0: Chip 0 + * @arg EXMC_DMC_CHIP_1: Chip 1 + * @arg EXMC_DMC_CHIP_2: Chip 2 + * @arg EXMC_DMC_CHIP_3: Chip 3 + * @param [in] u32Bank The command bank. + * This parameter can be one of the following values: + * @arg EXMC_DMC_BANK_0: Bank 0 + * @arg EXMC_DMC_BANK_1: Bank 1 + * @arg EXMC_DMC_BANK_2: Bank 2 + * @arg EXMC_DMC_BANK_3: Bank 3 + * @param [in] u32Cmd The command. + * This parameter can be one of the following values: + * @arg EXMC_DMC_CMD_PRECHARGEALL:Precharge all + * @arg EXMC_DMC_CMD_AUTOREFRESH: Auto refresh + * @arg EXMC_DMC_CMD_MDREGCONFIG: Set memory device mode register + * @arg EXMC_DMC_CMD_NOP: NOP + * @param [in] u32Address The address parameter for CMD MdRegConfig only. + * This parameter can be a value between Min_Data = 0 and Max_Data = 0x7FFFUL + * @retval An en_result_t enumeration value: + * - Ok: Command success + */ +en_result_t EXMC_DMC_SetCommand(uint32_t u32Chip, + uint32_t u32Bank, + uint32_t u32Cmd, + uint32_t u32Address) +{ + uint32_t u32DmcCmdr; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_DMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_DMC_BANK(u32Bank)); + DDL_ASSERT(IS_EXMC_DMC_CMD(u32Cmd)); + DDL_ASSERT(IS_EXMC_DMC_CMDADD(u32Address)); + + /* Set DMC_CMDR register for DMC.*/ + u32DmcCmdr = (u32Address | \ + (u32Bank << DMC_CMDR_CMDBA_POS) | \ + u32Cmd | \ + (u32Chip << DMC_CMDR_CMDCHIP_POS)); + WRITE_REG32(M4_DMC->CMDR, u32DmcCmdr); + + return Ok; +} + +/** + * @brief Set EXMC DMC state. + * @param [in] u32State The command chip number. + * @arg EXMC_DMC_CTL_STATE_GO: Go + * @arg EXMC_DMC_CTL_STATE_SLEEP: Sleep for low power + * @arg EXMC_DMC_CTL_STATE_WAKEUP: Wake up + * @arg EXMC_DMC_CTL_STATE_PAUSE: Pause + * @arg EXMC_DMC_CTL_STATE_CONFIGURE: Configure + * @retval None + */ +void EXMC_DMC_SetState(uint32_t u32State) +{ + DDL_ASSERT(IS_EXMC_DMC_STATE(u32State)); + + WRITE_REG32(M4_DMC->STCR, u32State); +} + +/** + * @} + */ + +#endif /* DDL_DMC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dvp.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dvp.c new file mode 100644 index 0000000000000000000000000000000000000000..d40516d8c4fce305e83886c3bb223444e89e1bb8 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dvp.c @@ -0,0 +1,484 @@ +/** + ******************************************************************************* + * @file hc32f4a0_dvp.c + * @brief This file provides firmware functions to manage the DVP(Digital Video + * Processor) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-08-20 Hongjh First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_dvp.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_DVP DVP + * @brief Digital Video Processor Driver Library + * @{ + */ + +#if (DDL_DVP_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup DVP_Local_Macros DVP Local Macros + * @{ + */ + +/** + * @defgroup DVP_Check_Parameters_Validity DVP Check Parameters Validity + * @{ + */ + +#define IS_DVP_CAPT_MD(x) \ +( ((x) == DVP_CAPT_MD_CONTINUOS_FRAME) || \ + ((x) == DVP_CAPT_MD_SINGLE_FRAME)) + +#define IS_DVP_SYNC_MD(x) \ +( ((x) == DVP_SYNC_MD_HW) || \ + ((x) == DVP_SYNC_MD_SW)) + +#define IS_DVP_PIXCLK_POLARITY(x) \ +( ((x) == DVP_PIXCLK_RISING) || \ + ((x) == DVP_PIXCLK_FALLING)) + +#define IS_DVP_HSYNC_POLARITY(x) \ +( ((x) == DVP_HSYNC_LOW) || \ + ((x) == DVP_HSYNC_HIGH)) + +#define IS_DVP_VSYNC_POLARITY(x) \ +( ((x) == DVP_VSYNC_LOW) || \ + ((x) == DVP_VSYNC_HIGH)) + +#define IS_DVP_CAPT_FREQ(x) \ +( ((x) == DVP_CAPT_FREQ_ALL_FRAME) || \ + ((x) == DVP_CAPT_FREQ_ONT_TIME_2FRAME) || \ + ((x) == DVP_CAPT_FREQ_ONT_TIME_4FRAME)) + +#define IS_DVP_DATA_WIDTH(x) \ +( ((x) == DVP_DATA_WIDTH_8BIT) || \ + ((x) == DVP_DATA_WIDTH_10BIT) || \ + ((x) == DVP_DATA_WIDTH_12BIT) || \ + ((x) == DVP_DATA_WIDTH_14BIT)) + +#define IS_DVP_FLAG(x) \ +( ((x) != 0UL) || \ + (((x) | DVP_FLAG_ALL) == DVP_FLAG_ALL)) + +#define IS_DVP_INT(x) \ +( ((x) != 0UL) || \ + (((x) | DVP_INT_ALL) == DVP_INT_ALL)) + +#define IS_DVP_CROP_WIN_X(x) ((x) <= 0x3FFFUL) + +#define IS_DVP_CROP_WIN_Y(x) ((x) <= 0x3FFFUL) + +#define IS_DVP_CROP_WIN_XSIZE(x) ((x) <= 0x3FFFUL) + +#define IS_DVP_CROP_WIN_YSIZE(x) ((x) <= 0x3FFFUL) + +#define IS_DVP_SYNC_CODE(x) ((x) <= 0xFFUL) + +#define IS_DVP_MASK_CODE(x) ((x) <= 0xFFUL) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup DVP_Global_Functions DVP Global Functions + * @{ + */ + +/** + * @brief Initialize DVP function. + * @param [in] pstcDvpInit Pointer to a @ref stc_dvp_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: The parameter pstcDvpInit is NULL + */ +en_result_t DVP_Init(const stc_dvp_init_t *pstcDvpInit) +{ + uint32_t u32RegValue; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcDvpInit) + { + /* Check parameters */ + DDL_ASSERT(IS_DVP_SYNC_MD(pstcDvpInit->u32SyncMode)); + DDL_ASSERT(IS_DVP_DATA_WIDTH(pstcDvpInit->u32DataWidth)); + DDL_ASSERT(IS_DVP_CAPT_MD(pstcDvpInit->u32CaptureMode)); + DDL_ASSERT(IS_DVP_CAPT_FREQ(pstcDvpInit->u32CaptureFreq)); + DDL_ASSERT(IS_DVP_PIXCLK_POLARITY(pstcDvpInit->u32PIXCLKPolarity)); + DDL_ASSERT(IS_DVP_HSYNC_POLARITY(pstcDvpInit->u32HSYNCPolarity)); + DDL_ASSERT(IS_DVP_VSYNC_POLARITY(pstcDvpInit->u32VSYNCPolarity)); + + /* De-init DVP*/ + WRITE_REG32(M4_DVP->CTR, 0UL); + WRITE_REG32(M4_DVP->STR, 0UL); + WRITE_REG32(M4_DVP->IER, 0UL); + WRITE_REG32(M4_DVP->SSYNDR, 0UL); + WRITE_REG32(M4_DVP->SSYNMR, 0xFFFFFFFFUL); + WRITE_REG32(M4_DVP->CPSFTR, 0UL); + WRITE_REG32(M4_DVP->CPSZER, 0UL); + + u32RegValue = (pstcDvpInit->u32SyncMode | \ + pstcDvpInit->u32DataWidth | \ + pstcDvpInit->u32CaptureMode | \ + pstcDvpInit->u32CaptureFreq | \ + pstcDvpInit->u32PIXCLKPolarity | \ + pstcDvpInit->u32HSYNCPolarity | \ + pstcDvpInit->u32VSYNCPolarity); + + /* Configure DVP */ + WRITE_REG32(M4_DVP->CTR, u32RegValue); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize DVP function. + * @param None + * @retval None + */ +void DVP_DeInit(void) +{ + WRITE_REG32(M4_DVP->CTR, 0UL); + WRITE_REG32(M4_DVP->STR, 0UL); + WRITE_REG32(M4_DVP->IER, 0UL); + WRITE_REG32(M4_DVP->SSYNDR, 0UL); + WRITE_REG32(M4_DVP->SSYNMR, 0xFFFFFFFFUL); + WRITE_REG32(M4_DVP->CPSFTR, 0UL); + WRITE_REG32(M4_DVP->CPSZER, 0UL); +} + +/** + * @brief Set the fields of structure stc_dvp_init_t to default values + * @param [out] pstcDvpInit Pointer to a @ref stc_dvp_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: The parameter pstcDvpInit is NULL + */ +en_result_t DVP_StructInit(stc_dvp_init_t *pstcDvpInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcDvpInit) + { + pstcDvpInit->u32SyncMode = DVP_SYNC_MD_HW; + pstcDvpInit->u32DataWidth = DVP_DATA_WIDTH_8BIT; + pstcDvpInit->u32CaptureMode = DVP_CAPT_MD_CONTINUOS_FRAME; + pstcDvpInit->u32CaptureFreq = DVP_CAPT_FREQ_ALL_FRAME; + pstcDvpInit->u32PIXCLKPolarity = DVP_PIXCLK_FALLING; + pstcDvpInit->u32HSYNCPolarity = DVP_HSYNC_LOW; + pstcDvpInit->u32VSYNCPolarity = DVP_VSYNC_LOW; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable/disable DVP. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void DVP_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_DVP->CTR_b.DVPEN, enNewState); +} + +/** + * @brief Enable/disable the specified DVP interrupt. + * @param [in] u32IntType DVP interrupt type + * This parameter can be any composed value of the following values: + * @arg DVP_INT_FRAME_START: Frame start interrupt + * @arg DVP_INT_LINE_START: Line start interrupt + * @arg DVP_INT_LINE_END: Line end interrupt + * @arg DVP_INT_FRAME_END: Frame end interrupt + * @arg DVP_INT_FIFO_OVF: FIFO overflow error interrupt + * @arg DVP_INT_SYNC_ERR: Sync error interrupt + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void DVP_IntCmd(uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_DVP_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(M4_DVP->IER, u32IntType); + } + else + { + CLEAR_REG32_BIT(M4_DVP->IER, u32IntType); + } +} + +/** + * @brief Enable/disable DVP crop. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void DVP_CropCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_DVP->CTR_b.CROPEN, enNewState); +} + +/** + * @brief Enable/disable DVP JPEG format. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void DVP_JPEGCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_DVP->CTR_b.JPEGEN, enNewState); +} + +/** + * @brief Enable/disable DVP capture. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void DVP_CaptrueCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_DVP->CTR_b.CAPEN, enNewState); +} + +/** + * @brief Get DVP capture function state. + * @param None + * @retval An en_flag_status_t enumeration value: + * - Enable: Capture function is enabled. + * - Disable: Capture function is disabled. + */ +en_functional_state_t DVP_GetCaptrueCmdState(void) +{ + return ((0UL == READ_REG32(bM4_DVP->CTR_b.CAPEN)) ? Disable : Enable); +} + +/** + * @brief Get the specified DVP flag status. + * @param [in] u32Flag DVP flag + * This parameter can be any composed value of the following values: + * @arg DVP_FLAG_FRAME_START: Frame start flag + * @arg DVP_FLAG_LINE_START: Line start flag + * @arg DVP_FLAG_LINE_END: Line end flag + * @arg DVP_FLAG_FRAME_END: Frame end flag + * @arg DVP_FLAG_FIFO_OVF: FIFO overflow error flag + * @arg DVP_FLAG_SYNC_ERR: Sync error interrupt + * @retval An en_flag_status_t enumeration value: + * - Set: Any bit of the composed flag is set. + * - Reset: All bit of the composed flag is reset. + */ +en_flag_status_t DVP_GetStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_DVP_FLAG(u32Flag)); + + return ((READ_REG32_BIT(M4_DVP->STR, u32Flag) == 0UL) ? Reset : Set); +} + +/** + * @brief Clear the specified DVP flag status. + * @param [in] u32Flag DVP flag + * This parameter can be any composed value of the following values: + * @arg DVP_FLAG_FRAME_START: Frame start flag + * @arg DVP_FLAG_LINE_START: Line start flag + * @arg DVP_FLAG_LINE_END: Line end flag + * @arg DVP_FLAG_FRAME_END: Frame end flag + * @arg DVP_FLAG_FIFO_OVF: FIFO overflow error flag + * @arg DVP_FLAG_SYNC_ERR: Sync error interrupt + * @retval None + */ +void DVP_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_DVP_FLAG(u32Flag)); + + CLEAR_REG32_BIT(M4_DVP->STR, u32Flag); +} + +/** + * @brief Set DVP software sync code. + * @param [in] pstcSyncCode Pointer to a @ref stc_dvp_sw_sync_code_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: The parameter pstcSyncCode is NULL + */ +en_result_t DVP_SetSWSyncCode(const stc_dvp_sw_sync_code_t *pstcSyncCode) +{ + uint32_t u32RegValue; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcSyncCode) + { + /* Check parameters */ + DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32FrameStartSyncCode)); + DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32LineStartSyncCode)); + DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32LineEndSyncCode)); + DDL_ASSERT(IS_DVP_SYNC_CODE(pstcSyncCode->u32FrameEndSyncCode)); + + /* Set sync code. */ + u32RegValue = ((pstcSyncCode->u32FrameStartSyncCode << DVP_SSYNDR_FSDAT_POS) | \ + (pstcSyncCode->u32LineStartSyncCode << DVP_SSYNDR_LSDAT_POS) | \ + (pstcSyncCode->u32LineEndSyncCode << DVP_SSYNDR_LEDAT_POS) | \ + (pstcSyncCode->u32FrameEndSyncCode << DVP_SSYNDR_FEDAT_POS)); + WRITE_REG32(M4_DVP->SSYNDR, u32RegValue); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set DVP software sync mask code. + * @param [in] pstcMaskCode Pointer to a @ref stc_dvp_sw_mask_code_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: The parameter pstcMaskCode is NULL + */ +en_result_t DVP_SetSWMaskCode(const stc_dvp_sw_mask_code_t *pstcMaskCode) +{ + uint32_t u32RegValue; + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcMaskCode) + { + /* Check parameters */ + DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32FrameStartMaskCode)); + DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32LineStartMaskCode)); + DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32LineEndMaskCode)); + DDL_ASSERT(IS_DVP_MASK_CODE(pstcMaskCode->u32FrameEndMaskCode)); + + /* Set sync code. */ + u32RegValue = ((pstcMaskCode->u32FrameStartMaskCode << DVP_SSYNMR_FSMSK_POS) | \ + (pstcMaskCode->u32LineStartMaskCode << DVP_SSYNMR_LSMSK_POS) | \ + (pstcMaskCode->u32LineEndMaskCode << DVP_SSYNMR_LEMSK_POS) | \ + (pstcMaskCode->u32FrameEndMaskCode << DVP_SSYNMR_FEMSK_POS)); + WRITE_REG32(M4_DVP->SSYNMR, u32RegValue); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set DVP software sync mask code. + * @param [in] pstcConfig Pointer to a @ref stc_dvp_crop_window_config_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: The parameter pstcConfig is NULL + */ +en_result_t DVP_CropWindowConfig(const stc_dvp_crop_window_config_t *pstcConfig) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcConfig) + { + /* Check parameters */ + DDL_ASSERT(IS_DVP_CROP_WIN_X(pstcConfig->u32X)); + DDL_ASSERT(IS_DVP_CROP_WIN_Y(pstcConfig->u32Y)); + DDL_ASSERT(IS_DVP_CROP_WIN_XSIZE(pstcConfig->u32XSize)); + DDL_ASSERT(IS_DVP_CROP_WIN_YSIZE(pstcConfig->u32YSize)); + + /* Configure crop window */ + WRITE_REG32(M4_DVP->CPSFTR, (pstcConfig->u32X | (pstcConfig->u32Y << DVP_CPSFTR_CSHIFT_POS))); + WRITE_REG32(M4_DVP->CPSZER, (pstcConfig->u32XSize | (pstcConfig->u32YSize << DVP_CPSZER_CSIZE_POS))); + enRet = Ok; + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_DVP_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_efm.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_efm.c new file mode 100644 index 0000000000000000000000000000000000000000..444407e41c96daf4537994c721e8b21c9180d129 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_efm.c @@ -0,0 +1,1329 @@ +/** + ******************************************************************************* + * @file hc32f4a0_efm.c + * @brief This file provides firmware functions to manage the Embedded Flash + * Memory unit (EFM). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + 2020-07-03 Heqb Add flag judgment when operate SWAP + 2020-07-07 Heqb Add flag judgment for EFM_SetOperateMode function + 2020-08-11 Heqb 1.Refine function EFM_SequenceProgram() + 2.Typo + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_efm.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_EFM EFM + * @brief Embedded Flash Management Driver Library + * @{ + */ + +#if (DDL_EFM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EFM_Local_Macros EFM Local Macros + * @{ + */ +#define SECTOR_SIZE (0x2000UL) +#define REG_LENGTH (32U) +#define OTP_LOCK_ADDR_START (0x03001800UL) +#define OTP_LOCK_ADDR_END (0x03001AD7UL) +#define OTP_ENABLE_ADDR (0x03001AD8UL) +#define EFM_PGM_TIMEOUT (HCLK_VALUE / 20000UL) /* EFM Program timeout */ +#define EFM_ERASE_TIMEOUT (HCLK_VALUE / 20UL) /* EFM Erase timeout */ +#define EFM_SEQ_PGM_TIMEOUT (HCLK_VALUE / 2000000UL) /* EFM Sequence Program timeout */ +/** + * @defgroup EFM_Configuration_Bit_Mask EFM Configuration Bit Mask + * @{ + */ +#define EFM_CLR_FLAG_MASK (EFM_FLAG_CLR_OTPWERR0 | EFM_FLAG_CLR_PRTWERR0 | EFM_FLAG_CLR_PGSZERR0 | \ + EFM_FLAG_CLR_MISMTCH0 | EFM_FLAG_CLR_OPTEND0 | EFM_FLAG_CLR_CLOLERR0 | \ + EFM_FLAG_CLR_PRTWERR1 | EFM_FLAG_CLR_PGSZERR1 | EFM_FLAG_CLR_MISMTCH1 | \ + EFM_FLAG_CLR_OPTEND1 | EFM_FLAG_CLR_CLOLERR1) + +#define EFM_CACHE_MASK (EFM_FRMC_CRST | EFM_FRMC_PREFE | EFM_FRMC_DCACHE | EFM_FRMC_ICACHE) + +#define EFM_FLAG_MASK (EFM_FLAG_OTPWERR0 | EFM_FLAG_PRTWERR0 | EFM_FLAG_PGSZERR0 | \ + EFM_FLAG_MISMTCH0 | EFM_FLAG_OPTEND0 | EFM_FLAG_CLOLERR0 | \ + EFM_FLAG_PRTWERR1 | EFM_FLAG_PGSZERR1 | EFM_FLAG_MISMTCH1 | \ + EFM_FLAG_OPTEND1 | EFM_FLAG_CLOLERR1 | EFM_FLAG_RDY0 | EFM_FLAG_RDY1) + +/** + * @} + */ + +/** + * @defgroup EFM_Check_Parameters_Validity EFM Check Parameters Validity + * @{ + */ + +/*! Parameter validity check for flash latency. */ +#define IS_VALID_EFM_WAIT_CYCLE(x) ((x) <= EFM_WAIT_CYCLE_15) + +/*! Parameter validity check for operate mode. */ +#define IS_VALID_EFM_OPERATE_MD(x) \ +( ((x) == EFM_MODE_PROGRAMSINGLE) || \ + ((x) == EFM_MODE_PROGRAMREADBACK) || \ + ((x) == EFM_MODE_PROGRAMSEQUENCE) || \ + ((x) == EFM_MODE_ERASESECTOR) || \ + ((x) == EFM_MODE_ERASECHIP1) || \ + ((x) == EFM_MODE_ERASEFULL) || \ + ((x) == EFM_MODE_READONLY)) + +/*! Parameter validity check for flash interrupt select. */ +#define IS_VALID_EFM_INT_SEL(x) (((x) | EFM_INT_MASK) == EFM_INT_MASK) + +/*! Parameter validity check for flash flag. */ +#define IS_VALID_EFM_FLAG(x) (((x) | EFM_FLAG_MASK) == EFM_FLAG_MASK) + +/*! Parameter validity check for flash clear flag. */ +#define IS_VALID_EFM_CLRFLAG(x) (((x) | EFM_CLR_FLAG_MASK) == EFM_CLR_FLAG_MASK) + +/*! Parameter validity check for bus status while flash program or erase. */ +#define IS_VALID_EFM_BUS_STATUS(x) \ +( ((x) == EFM_BUS_BUSY) || \ + ((x) == EFM_BUS_RELEASE)) + +/*! Parameter validity check for efm data cache reset function. */ +#define IS_VALID_EFM_CACHERST_FUNC(x) \ +( ((x) == EFM_CACHERST_ON) || \ + ((x) == EFM_CACHERST_OFF)) + +/*! Parameter validity check for efm prefetch function. */ +#define IS_VALID_EFM_PREFETCH_FUNC(x) \ +( ((x) == EFM_PREFETCH_ON) || \ + ((x) == EFM_PREFETCH_OFF)) + +/*! Parameter validity check for efm data cache function. */ +#define IS_VALID_EFM_DCHEEN_FUNC(x) \ +( ((x) == EFM_DATACACHE_ON) || \ + ((x) == EFM_DATACACHE_OFF)) + +/*! Parameter validity check for efm instruction cache function. */ +#define IS_VALID_EFM_ICHEEN_FUNC(x) \ +( ((x) == EFM_INSCACHE_ON) || \ + ((x) == EFM_INSCACHE_OFF)) + +/*! Parameter validity check for efm status. */ +#define IS_VALID_EFM_STATUS(x) \ +( ((x) == EFM_FLASH0_ACT_FLASH1_ACT) || \ + ((x) == EFM_FLASH0_STP_FLASH1_ACT) || \ + ((x) == EFM_FLASH0_ACT_FLASH1_STP) || \ + ((x) == EFM_FLASH0_STP_FLASH1_STP)) + +/*! Parameter validity check for efm address. */ +#define IS_VALID_EFM_ADDR(x) \ +( ((x) <= EFM_END_ADDR) || \ + (((x) >= EFM_OTP_BLOCK16) && ((x) <= EFM_OTP_BLOCK181))) + +/*! Parameter validity check for efm chip erase address. */ +#define IS_VALID_EFM_CHIP_ERASE_ADDR(x) ((x) <= EFM_END_ADDR) + +/*! Parameter validity check for sector protected register locking. */ +#define IS_VALID_EFM_REG_LOCK(x) ((x) <= 0xFFU) + +/*! Parameter validity check for efm protect register . */ +#define IS_VALID_EFM_PRTREG(x) \ +( ((x) == EFM_PROTECT_FWMC) || \ + ((x) == EFM_PROTECT_OTP)) + +/*! Parameter validity check for efm chip . */ +#define IS_VALID_EFM_CHIP(x) (((x) | EFM_FLASH0_STP_FLASH1_STP) == EFM_FLASH0_STP_FLASH1_STP) + +/*! Parameter validity check for efm read mode . */ +#define IS_VALID_EFM_LVREAD_MODE(x) \ +( ((x) == EFM_LOWVOLREAD_ON) || \ + ((x) == EFM_LOWVOLREAD_OFF)) + +/*! Parameter validity check for efm erase mode . */ +#define IS_VALID_EFM_ERASE_MODE(x) \ +( ((x) == EFM_MODE_ERASECHIP1) || \ + ((x) == EFM_MODE_ERASEFULL)) + +/*! Parameter validity check for efm address alignment . */ +#define IS_VALID_EFM_ADDR_ALIGNMENT(x) (((x) | 0xFFFFFFFCUL) == 0xFFFFFFFCUL) + +/*! Parameter validity check for efm sector . */ +#define IS_VALID_EFM_SECTOR(x) ((x) <= EFM_SECTOR_255) + +/*! Parameter validity check for EFM lock status. */ +#define IS_VALID_EFM_UNLOCK() (M4_EFM->FAPRT == 0x00000001UL) + +/*! Parameter validity check for EFM_FWMC register lock status. */ +#define IS_VALID_EFM_FWMC_UNLOCK() (bM4_EFM->FWMC_b.KEY1LOCK == 0U) + +/*! Parameter validity check for OTP lock status. */ +#define IS_VALID_EFM_OTP_UNLOCK() (bM4_EFM->FWMC_b.KEY2LOCK == 0U) + +/*! Parameter validity check for EFM sector number */ +#define IS_VALID_EFM_SECTOR_NUM(x) ((x) <= 256U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EFM_Global_Functions EFM Global Functions + * @{ + */ + +/** + * @brief EFM_FWMC register unlock. + * @param None + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_FWMC_Unlock(void) +{ + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(M4_EFM->KEY1, 0x01234567UL); + WRITE_REG32(M4_EFM->KEY1, 0xFEDCBA98UL); +} + +/** + * @brief EFM_FWMC register lock. + * @param None + * @retval None + * @note Call EFM_Unlock() and EFM_FWMC_Unlock() unlock EFM_FWMC register first. + */ +void EFM_FWMC_Lock(void) +{ + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_FWMC_UNLOCK()); + + SET_REG32_BIT(M4_EFM->FWMC, EFM_FWMC_KEY1LOCK); +} + +/** + * @brief EFM OTP operate unlock. + * @param None + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_OTP_WP_Unlock(void) +{ + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(M4_EFM->KEY2, 0x10325476UL); + WRITE_REG32(M4_EFM->KEY2, 0xEFCDAB89UL); +} + +/** + * @brief EFM OTP write protect lock. + * @param None + * @retval None + * @note Call EFM_Unlock() and EFM_FWMC_Unlock() unlock OTP write protect first. + */ +void EFM_OTP_WP_Lock(void) +{ + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_FWMC_UNLOCK()); + + SET_REG32_BIT(M4_EFM->FWMC, EFM_FWMC_KEY2LOCK); +} + +/** + * @brief Enable or disable EFM. + * @param [in] u32EfmStatus Specifies the flash Chip. + * @arg EFM_FLASH0_ACT_FLASH1_ACT: Flash 0 and 1 activity 0 + * @arg EFM_FLASH0_STP_FLASH1_ACT: Flash 0 stop,Flash 1 activity + * @arg EFM_FLASH0_ACT_FLASH1_STP: Flash 0 activity,Flash 1 stop + * @arg EFM_FLASH0_STP_FLASH1_STP: Flash 0 and 1 stop + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_Cmd(uint32_t u32EfmStatus) +{ + DDL_ASSERT(IS_VALID_EFM_STATUS(u32EfmStatus)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + WRITE_REG32(M4_EFM->FSTP, u32EfmStatus); +} + +/** + * @brief Init efm config structure with default value. + * @param [in] pstcEfmCfg The pointer of efm config structure. + * @arg u32WaitCycle: Specifies the efm read wait cycles. + * @arg u32Prefetch: Specifies the prefetch on or off. + * @arg u32CacheRst: Specifies the data cache reset on or off. + * @arg u32InsCache: Specifies the instruction cache on or off. + * @arg u32DataCache: Specifies the data cache on or off. + * @arg u32LowVolRead: Specifies the read of low-voltage mode on or off. + * @arg u32BusStatus: Specifies the bus status busy or release while program & erase. + * @arg u32OperateMode: Specifies the operate mode. + * @arg u32FlashStatus: Specifies the Flash status. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t EFM_StructInit(stc_efm_cfg_t *pstcEfmCfg) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcEfmCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcEfmCfg->u32WaitCycle = EFM_WAIT_CYCLE_0; + pstcEfmCfg->u32Prefetch = EFM_PREFETCH_OFF; + pstcEfmCfg->u32CacheRst = EFM_CACHERST_OFF; + pstcEfmCfg->u32InsCache = EFM_INSCACHE_OFF; + pstcEfmCfg->u32DataCache = EFM_DATACACHE_OFF; + pstcEfmCfg->u32LowVolRead = EFM_LOWVOLREAD_OFF; + pstcEfmCfg->u32BusStatus = EFM_BUS_BUSY; + pstcEfmCfg->u32OperateMode = EFM_MODE_READONLY; + pstcEfmCfg->u32FlashStatus = EFM_FLASH0_ACT_FLASH1_ACT; + } + + return enRet; +} + + +/** + * @brief Efm initialize. + * @param [in] pstcEfmCfg The pointer of efm config structure. + * @arg u32WaitCycle: Specifies the efm read wait cycles. + * @arg u32Prefetch: Specifies the prefetch on or off. + * @arg u32CacheRst: Specifies the data cache reset on or off. + * @arg u32InsCache: Specifies the instruction cache on or off. + * @arg u32DataCache: Specifies the data cache on or off. + * @arg u32LowVolRead: Specifies the read of low-voltage mode on or off. + * @arg u32BusStatus: Specifies the bus status busy or release while program & erase. + * @arg u32OperateMode: Specifies the operate mode. + * @arg u32FlashStatus: Specifies the Flash status. + * @retval An en_result_t enumeration value: + * - Ok: Configure success + * - ErrorInvalidParameter: Invalid parameter + * @note Call EFM_Unlock() and EFM_FWMC_Unlock() unlock EFM_FWMC register first. + */ +en_result_t EFM_Init(const stc_efm_cfg_t *pstcEfmCfg) +{ + en_result_t enRet = Ok; + uint32_t u32Temp; + /* Check if pointer is NULL */ + if (NULL == pstcEfmCfg) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Param valid check */ + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_FWMC_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_WAIT_CYCLE(pstcEfmCfg->u32WaitCycle)); + DDL_ASSERT(IS_VALID_EFM_BUS_STATUS(pstcEfmCfg->u32BusStatus)); + DDL_ASSERT(IS_VALID_EFM_CACHERST_FUNC(pstcEfmCfg->u32CacheRst)); + DDL_ASSERT(IS_VALID_EFM_PREFETCH_FUNC(pstcEfmCfg->u32Prefetch)); + DDL_ASSERT(IS_VALID_EFM_DCHEEN_FUNC(pstcEfmCfg->u32DataCache)); + DDL_ASSERT(IS_VALID_EFM_ICHEEN_FUNC(pstcEfmCfg->u32InsCache)); + DDL_ASSERT(IS_VALID_EFM_LVREAD_MODE(pstcEfmCfg->u32LowVolRead)); + DDL_ASSERT(IS_VALID_EFM_OPERATE_MD(pstcEfmCfg->u32OperateMode)); + DDL_ASSERT(IS_VALID_EFM_STATUS(pstcEfmCfg->u32FlashStatus)); + + u32Temp = pstcEfmCfg->u32WaitCycle | pstcEfmCfg->u32InsCache | pstcEfmCfg->u32DataCache | \ + pstcEfmCfg->u32Prefetch | pstcEfmCfg->u32CacheRst | pstcEfmCfg->u32LowVolRead; + /* Config efm. */ + MODIFY_REG32(M4_EFM->FRMC, EFM_FRMC_FLWT | EFM_FRMC_PREFE | EFM_FRMC_LVM | \ + EFM_FRMC_ICACHE | EFM_FRMC_DCACHE | EFM_FRMC_CRST, u32Temp); + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_BUSHLDCTL | EFM_FWMC_PEMOD, \ + pstcEfmCfg->u32BusStatus | pstcEfmCfg->u32OperateMode); + MODIFY_REG32(M4_EFM->FSTP, EFM_FSTP_F0STP | EFM_FSTP_F1STP, pstcEfmCfg->u32FlashStatus); + } + + return enRet; +} + +/** + * @brief Set the efm read wait cycles. + * @param [in] u32WaitCycle Specifies the efm read wait cycles. + * This parameter can be one of the following values: + * @arg EFM_WAIT_CYCLE_0: Don't insert read wait cycle + * @arg EFM_WAIT_CYCLE_1: Insert 1 read wait cycles + * @arg EFM_WAIT_CYCLE_2: Insert 2 read wait cycles + * @arg EFM_WAIT_CYCLE_3: Insert 3 read wait cycles + * @arg EFM_WAIT_CYCLE_4: Insert 4 read wait cycles + * @arg EFM_WAIT_CYCLE_5: Insert 5 read wait cycles + * @arg EFM_WAIT_CYCLE_6: Insert 6 read wait cycles + * @arg EFM_WAIT_CYCLE_7: Insert 7 read wait cycles + * @arg EFM_WAIT_CYCLE_8: Insert 8 read wait cycles + * @arg EFM_WAIT_CYCLE_9: Insert 9 read wait cycles + * @arg EFM_WAIT_CYCLE_10: Insert 10 read wait cycles + * @arg EFM_WAIT_CYCLE_11: Insert 11 read wait cycles + * @arg EFM_WAIT_CYCLE_12: Insert 12 read wait cycles + * @arg EFM_WAIT_CYCLE_13: Insert 13 read wait cycles + * @arg EFM_WAIT_CYCLE_14: Insert 14 read wait cycles + * @arg EFM_WAIT_CYCLE_15: Insert 15 read wait cycles + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_SetWaitCycle(uint32_t u32WaitCycle) +{ + /* Param valid check */ + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_WAIT_CYCLE(u32WaitCycle)); + /* Set the code latency value. */ + MODIFY_REG32(M4_EFM->FRMC, EFM_FRMC_FLWT, u32WaitCycle); +} + +/** + * @brief Enable or disable the flash data cache reset. + * @param [in] enNewState The new status of the flash data cache reset. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_DataCacheRstCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(bM4_EFM->FRMC_b.CRST, enNewState); +} + +/** + * @brief Enable or disable the flash prefetch. + * @param [in] enNewState The new state of the flash prefetch. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_PrefetchCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(bM4_EFM->FRMC_b.PREFE, enNewState); +} + +/** + * @brief Enable or disable the flash data cache. + * @param [in] enNewState The new state of the flash data cache. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_DataCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(bM4_EFM->FRMC_b.DCACHE, enNewState); +} + +/** + * @brief Enable or disable the flash instruction cache. + * @param [in] enNewState The new state of the flash instruction cache. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_InsCacheCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(bM4_EFM->FRMC_b.ICACHE, enNewState); +} + +/** + * @brief Enable or disable the Read of low-voltage mode. + * @param [in] enNewState The new state of the flash Low voltage read mode. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_LowVolReadCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + WRITE_REG32(bM4_EFM->FRMC_b.LVM, enNewState); +} + +/** + * @brief Set the FLASH erase program mode . + * @param [in] u32PgmMode Specifies the FLASH erase program mode. + * This parameter can be one of the following values: + * @arg EFM_MODE_PROGRAMSINGLE: Program single at a specified address + * @arg EFM_MODE_PROGRAMREADBACK: Program and read back at a specified address + * @arg EFM_MODE_PROGRAMSEQUENCE: Program sequence at sequence address + * @arg EFM_MODE_ERASESECTOR: Sector erase + * @arg EFM_MODE_ERASECHIP1: A flash Chip erase + * @arg EFM_MODE_ERASEFULL: Two flash Chip erase + * @arg EFM_MODE_READONLY: Read only + * @retval An en_result_t enumeration value: + * - Ok: Success + * - ErrorTimeout: Process timeout + * @note Call EFM_Unlock() and EFM_FWMC_Unlock() unlock EFM_FWMC register first. + */ +en_result_t EFM_SetOperateMode(uint32_t u32PgmMode) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout = 0UL; + DDL_ASSERT(IS_VALID_EFM_OPERATE_MD(u32PgmMode)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_FWMC_UNLOCK()); + while ((READ_REG32(M4_EFM->FSR) & 0x01000100UL) != 0x01000100UL) + { + u32Timeout ++; + if (u32Timeout > EFM_SEQ_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + /* Set the program or erase mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, u32PgmMode); + } + return enRet; +} + +/** + * @brief Enable or Disable EFM interrupt. + * @param [in] u32EfmInt Specifies the FLASH interrupt source and status. + * @arg EFM_INT_OPTEND: End of EFM Operation Interrupt source + * @arg EFM_INT_PEERR: Program/erase error Interrupt source + * @arg EFM_INT_RDCOLERR: Read collide error Interrupt source + * @param [in] enNewState The new state of specified interrupt. + * This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_InterruptCmd(uint32_t u32EfmInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_EFM_INT_SEL(u32EfmInt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + if(Enable == enNewState) + { + SET_REG32_BIT(M4_EFM->FITE, u32EfmInt); + } + else + { + CLEAR_REG32_BIT(M4_EFM->FITE, u32EfmInt); + } +} + +/** + * @brief Checks whether the specified FLASH flag is set or not. + * @param [in] u32Flag Specifies the FLASH flag to check. + * @arg EFM_FLAG_OTPWERR0: Flash0 otp Programming/erase error flag. + * @arg EFM_FLAG_PRTWERR0: Flash0 write protect address error flag. + * @arg EFM_FLAG_PGSZERR0: Flash0 programming size error flag. + * @arg EFM_FLAG_MISMTCH0: Flash0 programming missing match error flag. + * @arg EFM_FLAG_OPTEND0: Flash0 end of operation flag. + * @arg EFM_FLAG_CLOLERR0: Flash0 read write error flag. + * @arg EFM_FLAG_RDY0: Flash0 ready flag. + * @arg EFM_FLAG_PRTWERR1: Flash1 write protect address error flag. + * @arg EFM_FLAG_PGSZERR1: Flash1 programming size error flag. + * @arg EFM_FLAG_MISMTCH1: Flash1 programming missing match error flag. + * @arg EFM_FLAG_OPTEND1: Flash1 end of operation flag. + * @arg EFM_FLAG_CLOLERR1: Flash1 read write error flag. + * @arg EFM_FLAG_RDY1: Flash1 ready flag. + * @retval An en_flag_status_t enumeration value: + * - Set: flag is set + * - Reset: flag is reset + */ +en_flag_status_t EFM_GetFlagStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_EFM_FLAG(u32Flag)); + return ((0UL == READ_REG32_BIT(M4_EFM->FSR, u32Flag)) ? Reset :Set); +} + +/** + * @brief Clear the flash flag. + * @param [in] u32Flag Specifies the FLASH flag to clear. + * @arg EFM_FLAG_CLR_OTPWERR0: Clear Flash0 otp Programming/erase error flag + * @arg EFM_FLAG_CLR_PRTWERR0: Clear Flash0 write protect address error flag + * @arg EFM_FLAG_CLR_PGSZERR0: Clear Flash0 programming size error flag + * @arg EFM_FLAG_CLR_MISMTCH0: Clear Flash0 programming miss match error flag + * @arg EFM_FLAG_CLR_OPTEND0: Clear Flash0 end of operation flag + * @arg EFM_FLAG_CLR_CLOLERR0: Clear Flash0 read collide error flag + * @arg EFM_FLAG_CLR_PRTWERR1: Clear Flash1 write protect address error flag + * @arg EFM_FLAG_CLR_PGSZERR1: Clear Flash1 programming size error flag + * @arg EFM_FLAG_CLR_MISMTCH1: Clear Flash1 programming miss match error flag + * @arg EFM_FLAG_CLR_OPTEND1: Clear Flash1 end of operation flag + * @arg EFM_FLAG_CLR_CLOLERR1: Clear Flash1 read collide error flag + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_ClearFlag(uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_EFM_CLRFLAG(u32Flag)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + SET_REG32_BIT(M4_EFM->FSCLR, u32Flag); +} + +/** + * @brief Sector protected register lock. + * @param [in] u32EfmRegLock Specifies sector protected register locking. + * @arg EFM_WRLOCK0: F0NWPRT0 controlled sector lock + * @arg EFM_WRLOCK1: F0NWPRT1 controlled sector lock + * @arg EFM_WRLOCK2: F0NWPRT2 controlled sector lock + * @arg EFM_WRLOCK3: F0NWPRT3 controlled sector lock + * @arg EFM_WRLOCK4: F1NWPRT0 controlled sector lock + * @arg EFM_WRLOCK5: F1NWPRT1 controlled sector lock + * @arg EFM_WRLOCK6: F1NWPRT2 controlled sector lock + * @arg EFM_WRLOCK7: F1NWPRT3 controlled sector lock + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + */ +void EFM_SectorRegLock(uint32_t u32EfmRegLock) +{ + DDL_ASSERT(IS_VALID_EFM_REG_LOCK(u32EfmRegLock)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + SET_REG32_BIT(M4_EFM->WLOCK, u32EfmRegLock); +} + +/** + * @brief Set sector lock or unlock (Single). + * @param [in] u8SectorNum Specifies sector for unlock. + * This parameter can be set 0~255 + * @param [in] enNewState The new status of specified sector lock or unlock. + * This parameter can be: Enable or Disable. + * @retval None + * @note Call EFM_Unlock() unlock EFM register first. + * If you want to unlock sequential sectors,Please call EFM_SectorCmd_Sequential function + */ +void EFM_SectorCmd_Single(uint8_t u8SectorNum, en_functional_state_t enNewState) +{ + __IO uint32_t *EFM_FxNWPRTy; + const uint8_t u8RegIndex = u8SectorNum / REG_LENGTH; + const uint8_t u8BitPos = u8SectorNum % REG_LENGTH; + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + EFM_FxNWPRTy = (__IO uint32_t*)((uint32_t)(&M4_EFM->F0NWPRT0) + ((uint32_t)u8RegIndex << 2UL)); + MODIFY_REG32(*EFM_FxNWPRTy, 1UL<F0NWPRT0) + ((uint32_t)StartRegIndex << 2UL)); + + if(StartRegIndex == EndRegIndex) + { + for(Num = StartBitPos; Num <= EndBitPos; Num++) + { + MODIFY_REG32(*EFM_FxNWPRTy,(uint32_t)1UL<F0NWPRT0) + ((uint32_t)EndRegIndex << 2U)); + for(Num = 0U;Num <= EndBitPos;Num++) + { + MODIFY_REG32(*EFM_FxNWPRTy, (uint32_t)1UL<F0NWPRT0) + ((uint32_t)StartRegIndex << 2U)); + if(enNewState == Enable) + { + WRITE_REG32(*EFM_FxNWPRTy, 0xFFFFFFFFUL); + } + else + { + WRITE_REG32(*EFM_FxNWPRTy, 0x0UL); + } + StartRegIndex += 1U; + } + enRet = Ok; + } + } + return enRet; +} + +/** + * @brief Set bus status while flash program or erase. + * @param [in] u32Status Specifies the new bus status while flash program or erase. + * This parameter can be one of the following values: + * @arg EFM_BUS_BUSY: Bus busy while flash program or erase. + * @arg EFM_BUS_RELEASE: Bus releas while flash program or erase. + * @retval None + * @note Call EFM_Unlock() and EFM_FWMC_Unlock() unlock EFM_FWMC register first. + */ +void EFM_SetBusStatus(uint32_t u32Status) +{ + DDL_ASSERT(IS_VALID_EFM_BUS_STATUS(u32Status)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_FWMC_UNLOCK()); + + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_BUSHLDCTL, u32Status); +} + +/** + * @brief Flash single program mode. + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval An en_result_t enumeration value: + * - Ok: program success + * - Error: program error + * - ErrorTimeout: program error timeout + * @note The address should be word align. + * Call EFM_Unlock() unlock EFM register first. + */ +en_result_t EFM_SingleProgram(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout = 0UL; + uint32_t u32tmp; + uint32_t u32EfmFlag = EFM_FLAG_RDY1; + uint32_t u32EfmClrFlag = EFM_FLAG_CLR_OPTEND1; + + DDL_ASSERT(IS_VALID_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_ADDR_ALIGNMENT(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + /* Clear the error flag. */ + EFM_ClearFlag(EFM_CLR_FLAG_MASK); + /* Get CACHE status */ + u32tmp = READ_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Disable CACHE function */ + CLEAR_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Set single program mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_PROGRAMSINGLE); + /* Program data. */ + RW_MEM32(u32Addr) = (uint32_t)u32Data; + if((u32Addr < EFM_ADDR_SECTOR128) || (u32Addr >= EFM_OTP_BLOCK16)) + { + u32EfmFlag = EFM_FLAG_RDY0; + u32EfmClrFlag = EFM_FLAG_CLR_OPTEND0; + } + /* Wait for operation end */ + while(Set != EFM_GetFlagStatus(u32EfmFlag)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if(u32Data != RW_MEM32(u32Addr)) + { + enRet = Error; + } + /* CLear the end of operate flag */ + EFM_ClearFlag(u32EfmClrFlag); + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + /* Recover CACHE function */ + MODIFY_REG32(M4_EFM->FRMC, EFM_CACHE_MASK, u32tmp); + + return enRet; +} + +/** + * @brief Flash single program with read back. + * @param [in] u32Addr The specified program address. + * @param [in] u32Data The specified program data. + * @retval An en_result_t enumeration value: + * - Ok: program success + * - Error: program error + * - ErrorTimeout: program error timeout + * @note The address should be word align. + * Call EFM_Unlock() unlock EFM register first. + */ +en_result_t EFM_ProgramReadBack(uint32_t u32Addr, uint32_t u32Data) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout = 0UL; + uint32_t u32tmp; + uint32_t u32EfmFlag = EFM_FLAG_RDY1; + uint32_t u32EfmClrFlag = EFM_FLAG_CLR_OPTEND1; + uint32_t u32EfmFlag1 = EFM_FLAG_MISMTCH1; + uint32_t u32EfmClrFlag1 = EFM_FLAG_CLR_MISMTCH1; + + DDL_ASSERT(IS_VALID_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_ADDR_ALIGNMENT(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + /* Clear the error flag. */ + EFM_ClearFlag(EFM_CLR_FLAG_MASK); + /* Get CACHE status */ + u32tmp = READ_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Disable CACHE */ + CLEAR_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Set Program and read back mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_PROGRAMREADBACK); + /* Program data. */ + RW_MEM32(u32Addr) = (uint32_t)u32Data; + if((u32Addr < EFM_ADDR_SECTOR128) || (u32Addr >= EFM_OTP_BLOCK16)) + { + u32EfmFlag = EFM_FLAG_RDY0; + u32EfmClrFlag = EFM_FLAG_CLR_OPTEND0; + u32EfmFlag1 = EFM_FLAG_MISMTCH0; + u32EfmClrFlag1 = EFM_FLAG_CLR_MISMTCH0; + } + while(Set != EFM_GetFlagStatus(u32EfmFlag)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* Get the flag MISMTCH0*/ + if(Set == EFM_GetFlagStatus(u32EfmFlag1)) + { + /* Clear flag PGMISMTCH */ + EFM_ClearFlag(u32EfmClrFlag1); + enRet = Error; + } + /* CLear the end of operate flag */ + EFM_ClearFlag(u32EfmClrFlag); + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + /* recover CACHE function */ + MODIFY_REG32(M4_EFM->FRMC, EFM_CACHE_MASK, u32tmp); + + return enRet; +} + +/** + * @brief Flash sequence program. + * @param [in] u32Addr The specified program address. + * @param [in] u32Len The len of specified program data. + * @param [in] pu32Buf The pointer of specified program data. + * @retval An en_result_t enumeration value: + * - Ok: program success + * - ErrorTimeout: program error timeout + * @note The address should be word align. + * Call EFM_Unlock() unlock EFM register first. + */ +en_result_t EFM_SequenceProgram(uint32_t u32Addr, uint32_t u32Len, const uint32_t *pu32Buf) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout; + uint32_t u32tmp; + uint32_t u32LoopWords = u32Len >> 2UL; + uint32_t u32EfmFlag = EFM_FLAG_OPTEND0; + uint32_t u32EfmFlag1 = EFM_FLAG_RDY0; + uint32_t u32EfmClrFlag = EFM_FLAG_CLR_OPTEND0; + uint32_t u32SrcDataAddr = (uint32_t)pu32Buf; + DDL_ASSERT(IS_VALID_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_ADDR_ALIGNMENT(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_CLR_FLAG_MASK); + /* Get CACHE status */ + u32tmp = READ_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Disable CACHE */ + CLEAR_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Set sequence program mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_PROGRAMSEQUENCE); + /* program data. */ + while((u32LoopWords--) > 0UL) + { + RW_MEM32(u32Addr) = RW_MEM32(u32SrcDataAddr); + /* wait operate end. */ + if((u32Addr >= EFM_ADDR_SECTOR128) && (u32Addr < EFM_END_ADDR)) + { + u32EfmFlag = EFM_FLAG_OPTEND1; + u32EfmFlag1 = EFM_FLAG_RDY1; + u32EfmClrFlag = EFM_FLAG_CLR_OPTEND1; + } + u32Timeout = 0UL; + while(Set != EFM_GetFlagStatus(u32EfmFlag)) + { + if(u32Timeout++ >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + u32Timeout = 0UL; + /* Clear operation end flag */ + while(Reset != EFM_GetFlagStatus(u32EfmFlag)) + { + if(u32Timeout++ >= EFM_SEQ_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + /* clear end flag. */ + EFM_ClearFlag(u32EfmClrFlag); + } + if (enRet != Ok) + { + break; + } + u32Addr += 4UL; + u32SrcDataAddr += 4UL; + if (u32Addr == EFM_ADDR_SECTOR128) + { + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + u32Timeout = 0UL; + /* wait for flash ready . */ + while(Set != EFM_GetFlagStatus(u32EfmFlag1)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + /* Set sequence program mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_PROGRAMSEQUENCE); + } + } + } + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + u32Timeout = 0UL; + /* wait for flash ready . */ + while(Set != EFM_GetFlagStatus(u32EfmFlag1)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* Recover CACHE */ + MODIFY_REG32(M4_EFM->FRMC, EFM_CACHE_MASK, u32tmp); + return enRet; +} + +/** + * @brief Flash sector erase. + * @param [in] u32Addr The address in the specified sector. + * @retval An en_result_t enumeration value: + * - Ok: erase success + * - ErrorTimeout: program error timeout + * @note The address should be word align. + * Call EFM_Unlock() unlock EFM register first. + */ +en_result_t EFM_SectorErase(uint32_t u32Addr) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout = 0UL; + uint32_t u32tmp; + uint32_t u32EfmFlag = EFM_FLAG_RDY1; + uint32_t u32EfmClrFlag = EFM_FLAG_CLR_OPTEND1; + + DDL_ASSERT(IS_VALID_EFM_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_CLR_FLAG_MASK); + /* Get CACHE status */ + u32tmp = READ_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Disable CACHE */ + CLEAR_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Set sector erase mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_ERASESECTOR); + /* Erase */ + RW_MEM32(u32Addr & 0xFFFFFFFCUL) = (uint32_t)0UL; + if((u32Addr < EFM_ADDR_SECTOR128) || (u32Addr >= EFM_OTP_BLOCK16)) + { + u32EfmFlag = EFM_FLAG_RDY0; + u32EfmClrFlag = EFM_FLAG_CLR_OPTEND0; + } + while(Set != EFM_GetFlagStatus(u32EfmFlag)) + { + u32Timeout ++; + if(u32Timeout >= EFM_ERASE_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* Clear the end of operate flag */ + EFM_ClearFlag(u32EfmClrFlag); + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + /* Recover CACHE */ + MODIFY_REG32(M4_EFM->FRMC, EFM_CACHE_MASK, u32tmp); + + return enRet; +} + +/** + * @brief Flash OTP lock. + * @param [in] u32Addr Specifies the OTP block + * @retval An en_result_t enumeration value: + * - Ok: program success + * - ErrorInvalidParameter: Invalid parameter + * @note The address should be word align. + * Call EFM_Unlock() and EFM_OTP_WP_Unlock() unlock EFM_FWMC register first. + */ +en_result_t EFM_OTPLock(uint32_t u32Addr) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32Timeout = 0UL; + + if((u32Addr >= OTP_LOCK_ADDR_START) && (u32Addr < OTP_LOCK_ADDR_END )) + { + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_VALID_EFM_OTP_UNLOCK()); + + enRet = Ok; + /* Set single program mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_PROGRAMSINGLE); + /* Enable OTP */ + RW_MEM32(OTP_ENABLE_ADDR) = (uint32_t)0UL; + /* Wait for operation end */ + while(Set != EFM_GetFlagStatus(EFM_FLAG_RDY0)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND0); + if (enRet == Ok) + { + /* OTP latch */ + RW_MEM32(u32Addr & 0xFFFFFFFCUL) = (uint32_t)0UL; + /* Wait for operation end */ + u32Timeout = 0UL; + while(Set != EFM_GetFlagStatus(EFM_FLAG_RDY0)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND0); + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + } + + return enRet; +} + +/** + * @brief Flash chip erase. + * @param [in] EraseMode Specifies the FLASH erase mode. + * @arg EFM_MODE_ERASECHIP1 A flash Chip erase mode + * @arg EFM_MODE_ERASECHIP1 Two flash Chip erase mode + * @param [in] u32Addr Specifies the FLASH block + * @retval An en_result_t enumeration value: + * - Ok: program success + * - ErrorTimeout: program error timeout + * @note The address should be word align. + * Call EFM_Unlock() unlock EFM register first. + */ +en_result_t EFM_ChipErase(uint32_t EraseMode, uint32_t u32Addr) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout = 0UL; + uint32_t u32tmp; + uint32_t u32EfmFlag; + uint32_t u32EfmClrFlag; + + DDL_ASSERT(IS_VALID_EFM_ERASE_MODE(EraseMode)); + DDL_ASSERT(IS_VALID_EFM_CHIP_ERASE_ADDR(u32Addr)); + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + + /* CLear the error flag. */ + EFM_ClearFlag(EFM_CLR_FLAG_MASK); + /* Get CACHE status */ + u32tmp = READ_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* Disable CACHE */ + CLEAR_REG32_BIT(M4_EFM->FRMC, EFM_CACHE_MASK); + /* If wsap enable, Disable it */ + if (RW_MEM32(EFM_SWAP_ADDR) == EFM_SWAP_DATA) + { + /* Set Sector erase mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_ERASESECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + while(Set != EFM_GetFlagStatus(EFM_FLAG_OPTEND0)) + { + u32Timeout ++; + if(u32Timeout >= EFM_ERASE_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND0); + } + /* Set chip erase mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EraseMode); + if(EraseMode == EFM_MODE_ERASECHIP1) + { + if (u32Addr >= EFM_ADDR_SECTOR128) + { + u32EfmFlag = EFM_FLAG_RDY1; + u32EfmClrFlag = EFM_FLAG_CLR_OPTEND1; + /* Flash1 disables write protection */ + WRITE_REG32(M4_EFM->F1NWPRT0, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT1, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT2, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT3, 0xFFFFFFFFUL); + } + else + { + u32EfmFlag = EFM_FLAG_RDY0; + u32EfmClrFlag = EFM_FLAG_CLR_OPTEND0; + /* Flash0 disables write protection */ + WRITE_REG32(M4_EFM->F0NWPRT0, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F0NWPRT1, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F0NWPRT2, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F0NWPRT3, 0xFFFFFFFFUL); + } + + /* Erase */ + RW_MEM32(u32Addr & 0xFFFFFFFCUL) = (uint32_t)0UL; + while(Set != EFM_GetFlagStatus(u32EfmFlag)) + { + u32Timeout ++; + if(u32Timeout >= EFM_ERASE_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(u32EfmClrFlag); + } + else + { + /* Flash0 and Flash1 disables write protection */ + WRITE_REG32(M4_EFM->F0NWPRT0, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F0NWPRT1, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F0NWPRT2, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F0NWPRT3, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT0, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT1, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT2, 0xFFFFFFFFUL); + WRITE_REG32(M4_EFM->F1NWPRT3, 0xFFFFFFFFUL); + /* Erase */ + RW_MEM32(u32Addr & 0xFFFFFFFCUL) = (uint32_t)0UL; + while(Set != EFM_GetFlagStatus(EFM_FLAG_RDY0)) + { + u32Timeout ++; + if(u32Timeout >= EFM_ERASE_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND0); + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND1); + } + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + /* recover CACHE */ + MODIFY_REG32(M4_EFM->FRMC, EFM_CACHE_MASK, u32tmp); + return enRet; +} + +/** + * @brief Enable or disable the EFM swap function. + * @param [in] enNewState The new state of the flash swap function. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: program success + * - ErrorTimeout: program error timeout + * @note Call EFM_Unlock() unlock EFM register first. + */ +en_result_t EFM_SwapCmd(en_functional_state_t enNewState) +{ + en_result_t enRet = Ok; + uint32_t u32Timeout = 0UL; + + DDL_ASSERT(IS_VALID_EFM_UNLOCK()); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState ==Enable) + { + /* Set Program single mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_PROGRAMSINGLE); + /* Enable flash swap function */ + RW_MEM32(EFM_SWAP_ADDR) = EFM_SWAP_DATA; + while(Set != EFM_GetFlagStatus(EFM_FLAG_OPTEND0)) + { + u32Timeout ++; + if(u32Timeout >= EFM_PGM_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND0); + } + else{ + /* Set Sector erase mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_ERASESECTOR); + /* Disable flash switch function */ + RW_MEM32(EFM_SWAP_ADDR) = 0x0UL; + while(Set != EFM_GetFlagStatus(EFM_FLAG_OPTEND0)) + { + u32Timeout ++; + if(u32Timeout >= EFM_ERASE_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + /* CLear the end of operate flag */ + EFM_ClearFlag(EFM_FLAG_CLR_OPTEND0); + } + /* Set read only mode. */ + MODIFY_REG32(M4_EFM->FWMC, EFM_FWMC_PEMOD, EFM_MODE_READONLY); + + return enRet; +} + +/** + * @brief Get chip ID. + * @param None + * @retval Returns the value of the Chip ID + */ +uint32_t EFM_GetCID(void) +{ + uint32_t u32CID; + u32CID = M4_EFM->FHDFG; + return u32CID; +} + +/** + * @brief Get unique ID. + * @param [out] stcUID Unique ID struct + * @retval Returns the value of the unique ID + */ +void EFM_GetUID(stc_efm_unique_id_t *stcUID) +{ + stcUID->u32UniqueID0 = READ_REG32(M4_EFM->UQID0); + stcUID->u32UniqueID1 = READ_REG32(M4_EFM->UQID1); + stcUID->u32UniqueID2 = READ_REG32(M4_EFM->UQID2); +} + +/** + * @} + */ + +#endif /* DDL_EFM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_emb.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_emb.c new file mode 100644 index 0000000000000000000000000000000000000000..dadd1a91e73ef43f770e5e82c0aff5e4d0ccf3ef --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_emb.c @@ -0,0 +1,923 @@ +/** + ******************************************************************************* + * @file hc32f4a0_emb.c + * @brief This file provides firmware functions to manage the EMB + * (Emergency Brake). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-07 Hongjh Replace the word Timer with TMR abbreviation + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_emb.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_EMB EMB + * @brief Emergency Brake Driver Library + * @{ + */ + +#if (DDL_EMB_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EMB_Local_Macros EMB Local Macros + * @{ + */ + +/** + * @defgroup EMB_Check_Parameters_Validity EMB Check Parameters Validity + * @{ + */ + +#define IS_VALID_EMB(x) \ +( ((x) == M4_EMB0) || \ + ((x) == M4_EMB1) || \ + ((x) == M4_EMB2) || \ + ((x) == M4_EMB3) || \ + ((x) == M4_EMB4) || \ + ((x) == M4_EMB5) || \ + ((x) == M4_EMB6)) + +#define IS_VALID_EMB_TMR6(x) \ +( ((x) == M4_EMB0) || \ + ((x) == M4_EMB1) || \ + ((x) == M4_EMB2) || \ + ((x) == M4_EMB3)) + +#define IS_VALID_EMB_TIMER4(x) \ +( ((x) == M4_EMB4) || \ + ((x) == M4_EMB5) || \ + ((x) == M4_EMB6)) + +#define IS_VALID_EMB_CMP1_SEL(x) \ +( ((x) == EMB_CMP1_ENABLE) || \ + ((x) == EMB_CMP1_DISABLE)) + +#define IS_VALID_EMB_CMP2_SEL(x) \ +( ((x) == EMB_CMP2_ENABLE) || \ + ((x) == EMB_CMP2_DISABLE)) + +#define IS_VALID_EMB_CMP3_SEL(x) \ +( ((x) == EMB_CMP3_ENABLE) || \ + ((x) == EMB_CMP3_DISABLE)) + +#define IS_VALID_EMB_CMP4_SEL(x) \ +( ((x) == EMB_CMP4_ENABLE) || \ + ((x) == EMB_CMP4_DISABLE)) + +#define IS_VALID_EMB_PORT1_SEL(x) \ +( ((x) == EMB_PORT1_ENABLE) || \ + ((x) == EMB_PORT1_DISABLE)) + +#define IS_VALID_EMB_PORT2_SEL(x) \ +( ((x) == EMB_PORT2_ENABLE) || \ + ((x) == EMB_PORT2_DISABLE)) + +#define IS_VALID_EMB_PORT3_SEL(x) \ +( ((x) == EMB_PORT3_ENABLE) || \ + ((x) == EMB_PORT3_DISABLE)) + +#define IS_VALID_EMB_PORT4_SEL(x) \ +( ((x) == EMB_PORT4_ENABLE) || \ + ((x) == EMB_PORT4_DISABLE)) + +#define IS_VALID_EMB_OSC_SEL(x) \ +( ((x) == EMB_OSC_ENABLE) || \ + ((x) == EMB_OSC_DISABLE)) + +#define IS_VALID_EMB_TMR4_PWM_W_SEL(x) \ +( ((x) == EMB_TMR4_PWM_W_ENABLE) || \ + ((x) == EMB_TMR4_PWM_W_DISABLE)) + +#define IS_VALID_EMB_TMR4_PWM_V_SEL(x) \ +( ((x) == EMB_TMR4_PWM_V_ENABLE) || \ + ((x) == EMB_TMR4_PWM_V_DISABLE)) + +#define IS_VALID_EMB_TMR4_PWM_U_SEL(x) \ +( ((x) == EMB_TMR4_PWM_U_ENABLE) || \ + ((x) == EMB_TMR4_PWM_U_DISABLE)) + +#define IS_VALID_EMB_TMR6_1_PWM_SEL(x) \ +( ((x) == EMB_TMR6_1_PWM_ENABLE) || \ + ((x) == EMB_TMR6_1_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_2_PWM_SEL(x) \ +( ((x) == EMB_TMR6_2_PWM_ENABLE) || \ + ((x) == EMB_TMR6_2_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_3_PWM_SEL(x) \ +( ((x) == EMB_TMR6_3_PWM_ENABLE) || \ + ((x) == EMB_TMR6_3_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_4_PWM_SEL(x) \ +( ((x) == EMB_TMR6_4_PWM_ENABLE) || \ + ((x) == EMB_TMR6_4_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_5_PWM_SEL(x) \ +( ((x) == EMB_TMR6_5_PWM_ENABLE) || \ + ((x) == EMB_TMR6_5_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_6_PWM_SEL(x) \ +( ((x) == EMB_TMR6_6_PWM_ENABLE) || \ + ((x) == EMB_TMR6_6_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_7_PWM_SEL(x) \ +( ((x) == EMB_TMR6_7_PWM_ENABLE) || \ + ((x) == EMB_TMR6_7_PWM_DISABLE)) + +#define IS_VALID_EMB_TMR6_8_PWM_SEL(x) \ +( ((x) == EMB_TMR6_8_PWM_ENABLE) || \ + ((x) == EMB_TMR6_8_PWM_DISABLE)) + +#define IS_VALID_EMB_DETECT_PORT1_LEVEL(x) \ +( ((x) == EMB_DETECT_PORT1_LEVEL_LOW) || \ + ((x) == EMB_DETECT_PORT1_LEVEL_HIGH)) + +#define IS_VALID_EMB_DETECT_PORT2_LEVEL(x) \ +( ((x) == EMB_DETECT_PORT2_LEVEL_LOW) || \ + ((x) == EMB_DETECT_PORT2_LEVEL_HIGH)) + +#define IS_VALID_EMB_DETECT_PORT3_LEVEL(x) \ +( ((x) == EMB_DETECT_PORT3_LEVEL_LOW) || \ + ((x) == EMB_DETECT_PORT3_LEVEL_HIGH)) + +#define IS_VALID_EMB_DETECT_PORT4_LEVEL(x) \ +( ((x) == EMB_DETECT_PORT4_LEVEL_LOW) || \ + ((x) == EMB_DETECT_PORT4_LEVEL_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR4_PWM_W_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_W_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR4_PWM_V_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_V_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR4_PWM_U_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR4_PWM_U_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_1_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_1_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_2_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_2_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_3_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_3_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_4_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_4_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_5_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_5_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_6_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_6_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_7_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_7_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_DETECT_TMR6_8_PWM_LEVEL(x) \ +( ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_LOW) || \ + ((x) == EMB_DETECT_TMR6_8_PWM_BOTH_HIGH)) + +#define IS_VALID_EMB_INT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~IS_EMB_INT_MASK)))) + +#define IS_VALID_EMB_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~IS_EMB_FLAG_MASK)))) + +#define IS_VALID_EMB_STATUS(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~IS_EMB_STATUS_MASK)))) + +#define IS_VALID_EMB_PORT1_FILTER_DIV(x) \ +( ((x) == EMB_PORT1_FILTER_NONE) || \ + ((x) == EMB_PORT1_FILTER_CLK_DIV1) || \ + ((x) == EMB_PORT1_FILTER_CLK_DIV8) || \ + ((x) == EMB_PORT1_FILTER_CLK_DIV32) || \ + ((x) == EMB_PORT1_FILTER_CLK_DIV128)) + +#define IS_VALID_EMB_PORT2_FILTER_DIV(x) \ +( ((x) == EMB_PORT2_FILTER_NONE) || \ + ((x) == EMB_PORT2_FILTER_CLK_DIV1) || \ + ((x) == EMB_PORT2_FILTER_CLK_DIV8) || \ + ((x) == EMB_PORT2_FILTER_CLK_DIV32) || \ + ((x) == EMB_PORT2_FILTER_CLK_DIV128)) + +#define IS_VALID_EMB_PORT3_FILTER_DIV(x) \ +( ((x) == EMB_PORT3_FILTER_NONE) || \ + ((x) == EMB_PORT3_FILTER_CLK_DIV1) || \ + ((x) == EMB_PORT3_FILTER_CLK_DIV8) || \ + ((x) == EMB_PORT3_FILTER_CLK_DIV32) || \ + ((x) == EMB_PORT3_FILTER_CLK_DIV128)) + +#define IS_VALID_EMB_PORT4_FILTER_DIV(x) \ +( ((x) == EMB_PORT4_FILTER_NONE) || \ + ((x) == EMB_PORT4_FILTER_CLK_DIV1) || \ + ((x) == EMB_PORT4_FILTER_CLK_DIV8) || \ + ((x) == EMB_PORT4_FILTER_CLK_DIV32) || \ + ((x) == EMB_PORT4_FILTER_CLK_DIV128)) + +#define IS_VALID_EMB_RELEASE_PWM_SEL(x) \ +( ((x) == EMB_RELEASE_PWM_SEL_FLAG_ZERO) || \ + ((x) == EMB_RELEASE_PWM_SEL_STATE_ZERO)) + +#define IS_VALID_EMB_MONITOR_EVENT(x) \ +( ((x) == EMB_EVENT_PWMS) || \ + ((x) == EMB_EVENT_CMP) || \ + ((x) == EMB_EVENT_OSC) || \ + ((x) == EMB_EVENT_PORT1) || \ + ((x) == EMB_EVENT_PORT2) || \ + ((x) == EMB_EVENT_PORT3) || \ + ((x) == EMB_EVENT_PORT4)) +/** + * @} + */ + +/** + * @defgroup EMB_INT_Mask EMB interrupt mask definition + * @{ + */ +#define IS_EMB_INT_MASK (EMB_INT_PWMS | \ + EMB_INT_CMP | \ + EMB_INT_OSC | \ + EMB_INT_PORT1 | \ + EMB_INT_PORT2 | \ + EMB_INT_PORT3 | \ + EMB_INT_PORT4) +/** + * @} + */ + +/** + * @defgroup EMB_Flag_Mask EMB flag mask definition + * @{ + */ +#define IS_EMB_FLAG_MASK (EMB_FLAG_PWMS | \ + EMB_FLAG_CMP | \ + EMB_FLAG_OSC | \ + EMB_FLAG_PORT1 | \ + EMB_FLAG_PORT2 | \ + EMB_FLAG_PORT3 | \ + EMB_FLAG_PORT4) +/** + * @} + */ + +/** + * @defgroup EMB_Status_Mask EMB status mask definition + * @{ + */ +#define IS_EMB_STATUS_MASK (EMB_STATE_PWMS | \ + EMB_STATE_CMP | \ + EMB_STATE_OSC | \ + EMB_STATE_PORT1 | \ + EMB_STATE_PORT2 | \ + EMB_STATE_PORT3 | \ + EMB_STATE_PORT4) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup EMB_Global_Functions EMB Global Functions + * @{ + */ + +/** + * @brief Initialize EMB for TMR4. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] pstcInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + * @note TMR4 feature is supported by M4_EMB4/M4_EMB5/M4_EMB6 + */ +en_result_t EMB_Tmr4Init(M4_EMB_TypeDef *EMBx, + const stc_emb_tmr4_init_t *pstcInit) +{ + uint32_t u32RegVal; + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_TIMER4(EMBx)); + DDL_ASSERT(IS_VALID_EMB_CMP1_SEL(pstcInit->u32Cmp1)); + DDL_ASSERT(IS_VALID_EMB_CMP2_SEL(pstcInit->u32Cmp2)); + DDL_ASSERT(IS_VALID_EMB_CMP3_SEL(pstcInit->u32Cmp3)); + DDL_ASSERT(IS_VALID_EMB_CMP4_SEL(pstcInit->u32Cmp4)); + DDL_ASSERT(IS_VALID_EMB_OSC_SEL(pstcInit->u32Osc)); + DDL_ASSERT(IS_VALID_EMB_PORT1_SEL(pstcInit->stcPort1.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT1_LEVEL(pstcInit->stcPort1.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT1_FILTER_DIV(pstcInit->stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_PORT2_SEL(pstcInit->stcPort2.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT2_LEVEL(pstcInit->stcPort2.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT2_FILTER_DIV(pstcInit->stcPort2.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_PORT3_SEL(pstcInit->stcPort3.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT3_LEVEL(pstcInit->stcPort3.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT3_FILTER_DIV(pstcInit->stcPort3.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_PORT4_SEL(pstcInit->stcPort4.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT4_LEVEL(pstcInit->stcPort4.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT4_FILTER_DIV(pstcInit->stcPort4.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_TMR4_PWM_U_SEL(pstcInit->stcTmr4PwmU.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR4_PWM_U_LEVEL(pstcInit->stcTmr4PwmU.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR4_PWM_V_SEL(pstcInit->stcTmr4PwmV.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR4_PWM_V_LEVEL(pstcInit->stcTmr4PwmV.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR4_PWM_W_SEL(pstcInit->stcTmr4PwmW.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR4_PWM_W_LEVEL(pstcInit->stcTmr4PwmW.u32PwmLevel)); + + /* Set default value && clear flag */ + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->RLSSEL, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); + WRITE_REG32(EMBx->STATCLR, (EMB_STATCLR_PWMSFCLR | \ + EMB_STATCLR_CMPFCLR | \ + EMB_STATCLR_OSFCLR | \ + EMB_STATCLR_PORTINFCLR1 | \ + EMB_STATCLR_PORTINFCLR2 | \ + EMB_STATCLR_PORTINFCLR3 | \ + EMB_STATCLR_PORTINFCLR4)); + + /* Set EMB_CTL register */ + u32RegVal = (pstcInit->u32Cmp1 | \ + pstcInit->u32Cmp2 | \ + pstcInit->u32Cmp3 | \ + pstcInit->u32Cmp4 | \ + pstcInit->u32Osc | \ + pstcInit->stcTmr4PwmW.u32PwmSel | \ + pstcInit->stcTmr4PwmV.u32PwmSel | \ + pstcInit->stcTmr4PwmU.u32PwmSel | \ + pstcInit->stcPort1.u32PortSel | \ + pstcInit->stcPort2.u32PortSel | \ + pstcInit->stcPort3.u32PortSel | \ + pstcInit->stcPort4.u32PortSel | \ + pstcInit->stcPort1.u32PortLevel | \ + pstcInit->stcPort2.u32PortLevel | \ + pstcInit->stcPort3.u32PortLevel | \ + pstcInit->stcPort4.u32PortLevel); + WRITE_REG32(EMBx->CTL1, u32RegVal); + + /* Check writing EMB_CTL1 because EMB_CTL1 can write once only after reset */ + if (READ_REG32(EMBx->CTL1) == u32RegVal) + { + u32RegVal = (pstcInit->stcTmr4PwmW.u32PwmLevel | \ + pstcInit->stcTmr4PwmV.u32PwmLevel | \ + pstcInit->stcTmr4PwmU.u32PwmLevel | \ + pstcInit->stcPort1.u32PortFilterDiv | \ + pstcInit->stcPort2.u32PortFilterDiv | \ + pstcInit->stcPort3.u32PortFilterDiv | \ + pstcInit->stcPort4.u32PortFilterDiv); + WRITE_REG32(EMBx->CTL2, u32RegVal); + + /* Check writing EMB_CTL2 because EMB_CTL2 can write once only after reset */ + if (READ_REG32(EMBx->CTL2) == u32RegVal) + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_emb_tmr4_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_emb_tmr4_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EMB_Tmr4StructInit(stc_emb_tmr4_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Cmp1 = EMB_CMP1_DISABLE; + pstcInit->u32Cmp2 = EMB_CMP2_DISABLE; + pstcInit->u32Cmp3 = EMB_CMP3_DISABLE; + pstcInit->u32Cmp4 = EMB_CMP4_DISABLE; + pstcInit->u32Osc = EMB_OSC_DISABLE; + pstcInit->stcPort1.u32PortSel = EMB_PORT1_DISABLE; + pstcInit->stcPort1.u32PortLevel = EMB_DETECT_PORT1_LEVEL_HIGH; + pstcInit->stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_NONE; + pstcInit->stcPort2.u32PortSel = EMB_PORT2_DISABLE; + pstcInit->stcPort2.u32PortLevel = EMB_DETECT_PORT2_LEVEL_HIGH; + pstcInit->stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_NONE; + pstcInit->stcPort3.u32PortSel = EMB_PORT3_DISABLE; + pstcInit->stcPort3.u32PortLevel = EMB_DETECT_PORT3_LEVEL_HIGH; + pstcInit->stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_NONE; + pstcInit->stcPort4.u32PortSel = EMB_PORT4_DISABLE; + pstcInit->stcPort4.u32PortLevel = EMB_DETECT_PORT4_LEVEL_HIGH; + pstcInit->stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_NONE; + pstcInit->stcTmr4PwmU.u32PwmSel = EMB_TMR4_PWM_U_DISABLE; + pstcInit->stcTmr4PwmU.u32PwmLevel = EMB_DETECT_TMR4_PWM_U_BOTH_LOW; + pstcInit->stcTmr4PwmV.u32PwmSel = EMB_TMR4_PWM_V_DISABLE; + pstcInit->stcTmr4PwmV.u32PwmLevel = EMB_DETECT_TMR4_PWM_V_BOTH_LOW; + pstcInit->stcTmr4PwmW.u32PwmSel = EMB_TMR4_PWM_W_DISABLE; + pstcInit->stcTmr4PwmW.u32PwmLevel = EMB_DETECT_TMR4_PWM_W_BOTH_LOW; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Initialize EMB for TMR6. + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @param [in] pstcInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + * @note TMR6 feature is supported by M4_EMB0/M4_EMB1/M4_EMB2/M4_EMB3 + */ +en_result_t EMB_Tmr6Init(M4_EMB_TypeDef *EMBx, + const stc_emb_tmr6_init_t *pstcInit) +{ + uint32_t u32RegVal; + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB_TMR6(EMBx)); + DDL_ASSERT(IS_VALID_EMB_CMP1_SEL(pstcInit->u32Cmp1)); + DDL_ASSERT(IS_VALID_EMB_CMP2_SEL(pstcInit->u32Cmp2)); + DDL_ASSERT(IS_VALID_EMB_CMP3_SEL(pstcInit->u32Cmp3)); + DDL_ASSERT(IS_VALID_EMB_CMP4_SEL(pstcInit->u32Cmp4)); + DDL_ASSERT(IS_VALID_EMB_OSC_SEL(pstcInit->u32Osc)); + DDL_ASSERT(IS_VALID_EMB_PORT1_SEL(pstcInit->stcPort1.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT1_LEVEL(pstcInit->stcPort1.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT1_FILTER_DIV(pstcInit->stcPort1.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_PORT2_SEL(pstcInit->stcPort2.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT2_LEVEL(pstcInit->stcPort2.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT2_FILTER_DIV(pstcInit->stcPort2.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_PORT3_SEL(pstcInit->stcPort3.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT3_LEVEL(pstcInit->stcPort3.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT3_FILTER_DIV(pstcInit->stcPort3.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_PORT4_SEL(pstcInit->stcPort4.u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_PORT4_LEVEL(pstcInit->stcPort4.u32PortLevel)); + DDL_ASSERT(IS_VALID_EMB_PORT4_FILTER_DIV(pstcInit->stcPort4.u32PortFilterDiv)); + DDL_ASSERT(IS_VALID_EMB_TMR6_1_PWM_SEL(pstcInit->stcTmr6_1.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_1_PWM_LEVEL(pstcInit->stcTmr6_1.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_2_PWM_SEL(pstcInit->stcTmr6_2.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_2_PWM_LEVEL(pstcInit->stcTmr6_2.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_3_PWM_SEL(pstcInit->stcTmr6_3.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_3_PWM_LEVEL(pstcInit->stcTmr6_3.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_4_PWM_SEL(pstcInit->stcTmr6_4.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_4_PWM_LEVEL(pstcInit->stcTmr6_4.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_5_PWM_SEL(pstcInit->stcTmr6_5.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_5_PWM_LEVEL(pstcInit->stcTmr6_5.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_6_PWM_SEL(pstcInit->stcTmr6_6.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_6_PWM_LEVEL(pstcInit->stcTmr6_6.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_7_PWM_SEL(pstcInit->stcTmr6_7.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_7_PWM_LEVEL(pstcInit->stcTmr6_7.u32PwmLevel)); + DDL_ASSERT(IS_VALID_EMB_TMR6_8_PWM_SEL(pstcInit->stcTmr6_8.u32PwmSel)); + DDL_ASSERT(IS_VALID_EMB_DETECT_TMR6_8_PWM_LEVEL(pstcInit->stcTmr6_8.u32PwmLevel)); + + /* Set default value && clear flag */ + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->RLSSEL, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); + WRITE_REG32(EMBx->STATCLR, (EMB_STATCLR_PWMSFCLR | \ + EMB_STATCLR_CMPFCLR | \ + EMB_STATCLR_OSFCLR | \ + EMB_STATCLR_PORTINFCLR1 | \ + EMB_STATCLR_PORTINFCLR2 | \ + EMB_STATCLR_PORTINFCLR3 | \ + EMB_STATCLR_PORTINFCLR4)); + + /* Set EMB_CTL register */ + u32RegVal = (pstcInit->u32Cmp1 | \ + pstcInit->u32Cmp2 | \ + pstcInit->u32Cmp3 | \ + pstcInit->u32Cmp4 | \ + pstcInit->u32Osc | \ + pstcInit->stcTmr6_1.u32PwmSel | \ + pstcInit->stcTmr6_2.u32PwmSel | \ + pstcInit->stcTmr6_3.u32PwmSel | \ + pstcInit->stcTmr6_4.u32PwmSel | \ + pstcInit->stcTmr6_5.u32PwmSel | \ + pstcInit->stcTmr6_6.u32PwmSel | \ + pstcInit->stcTmr6_7.u32PwmSel | \ + pstcInit->stcTmr6_8.u32PwmSel | \ + pstcInit->stcPort1.u32PortSel | \ + pstcInit->stcPort2.u32PortSel | \ + pstcInit->stcPort3.u32PortSel | \ + pstcInit->stcPort4.u32PortSel | \ + pstcInit->stcPort1.u32PortLevel | \ + pstcInit->stcPort2.u32PortLevel | \ + pstcInit->stcPort3.u32PortLevel | \ + pstcInit->stcPort4.u32PortLevel); + WRITE_REG32(EMBx->CTL1, u32RegVal); + + /* Check writing EMB_CTL1 because EMB_CTL1 can write once only after reset */ + if (READ_REG32(EMBx->CTL1) == u32RegVal) + { + u32RegVal = (pstcInit->stcTmr6_1.u32PwmLevel | \ + pstcInit->stcTmr6_2.u32PwmLevel | \ + pstcInit->stcTmr6_3.u32PwmLevel | \ + pstcInit->stcTmr6_4.u32PwmLevel | \ + pstcInit->stcTmr6_5.u32PwmLevel | \ + pstcInit->stcTmr6_6.u32PwmLevel | \ + pstcInit->stcTmr6_7.u32PwmLevel | \ + pstcInit->stcTmr6_8.u32PwmLevel | \ + pstcInit->stcPort1.u32PortFilterDiv | \ + pstcInit->stcPort2.u32PortFilterDiv | \ + pstcInit->stcPort3.u32PortFilterDiv | \ + pstcInit->stcPort4.u32PortFilterDiv); + WRITE_REG32(EMBx->CTL2, u32RegVal); + + /* Check writing EMB_CTL2 because EMB_CTL2 can write once only after reset */ + if (READ_REG32(EMBx->CTL2) == u32RegVal) + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_emb_tmr6_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_emb_tmr6_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EMB_Tmr6StructInit(stc_emb_tmr6_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Cmp1 = EMB_CMP1_DISABLE; + pstcInit->u32Cmp2 = EMB_CMP2_DISABLE; + pstcInit->u32Cmp3 = EMB_CMP3_DISABLE; + pstcInit->u32Cmp4 = EMB_CMP4_DISABLE; + pstcInit->u32Osc = EMB_OSC_DISABLE; + pstcInit->stcPort1.u32PortSel = EMB_PORT1_DISABLE; + pstcInit->stcPort1.u32PortLevel = EMB_DETECT_PORT1_LEVEL_HIGH; + pstcInit->stcPort1.u32PortFilterDiv = EMB_PORT1_FILTER_NONE; + pstcInit->stcPort2.u32PortSel = EMB_PORT2_DISABLE; + pstcInit->stcPort2.u32PortLevel = EMB_DETECT_PORT2_LEVEL_HIGH; + pstcInit->stcPort2.u32PortFilterDiv = EMB_PORT2_FILTER_NONE; + pstcInit->stcPort3.u32PortSel = EMB_PORT3_DISABLE; + pstcInit->stcPort3.u32PortLevel = EMB_DETECT_PORT3_LEVEL_HIGH; + pstcInit->stcPort3.u32PortFilterDiv = EMB_PORT3_FILTER_NONE; + pstcInit->stcPort4.u32PortSel = EMB_PORT4_DISABLE; + pstcInit->stcPort4.u32PortLevel = EMB_DETECT_PORT4_LEVEL_HIGH; + pstcInit->stcPort4.u32PortFilterDiv = EMB_PORT4_FILTER_NONE; + pstcInit->stcTmr6_1.u32PwmSel = EMB_TMR6_1_PWM_DISABLE; + pstcInit->stcTmr6_1.u32PwmLevel = EMB_DETECT_TMR6_1_PWM_BOTH_LOW; + pstcInit->stcTmr6_2.u32PwmSel = EMB_TMR6_2_PWM_DISABLE; + pstcInit->stcTmr6_2.u32PwmLevel = EMB_DETECT_TMR6_2_PWM_BOTH_LOW; + pstcInit->stcTmr6_3.u32PwmSel = EMB_TMR6_3_PWM_DISABLE; + pstcInit->stcTmr6_3.u32PwmLevel = EMB_DETECT_TMR6_3_PWM_BOTH_LOW; + pstcInit->stcTmr6_4.u32PwmSel = EMB_TMR6_4_PWM_DISABLE; + pstcInit->stcTmr6_4.u32PwmLevel = EMB_DETECT_TMR6_4_PWM_BOTH_LOW; + pstcInit->stcTmr6_5.u32PwmSel = EMB_TMR6_5_PWM_DISABLE; + pstcInit->stcTmr6_5.u32PwmLevel = EMB_DETECT_TMR6_5_PWM_BOTH_LOW; + pstcInit->stcTmr6_6.u32PwmSel = EMB_TMR6_6_PWM_DISABLE; + pstcInit->stcTmr6_6.u32PwmLevel = EMB_DETECT_TMR6_6_PWM_BOTH_LOW; + pstcInit->stcTmr6_7.u32PwmSel = EMB_TMR6_7_PWM_DISABLE; + pstcInit->stcTmr6_7.u32PwmLevel = EMB_DETECT_TMR6_7_PWM_BOTH_LOW; + pstcInit->stcTmr6_8.u32PwmSel = EMB_TMR6_8_PWM_DISABLE; + pstcInit->stcTmr6_8.u32PwmLevel = EMB_DETECT_TMR6_8_PWM_BOTH_LOW; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize EMB function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @retval None + */ +void EMB_DeInit(M4_EMB_TypeDef *EMBx) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(EMBx->SOE, 0x00UL); + WRITE_REG32(EMBx->RLSSEL, 0x00UL); + WRITE_REG32(EMBx->INTEN, 0x00UL); + WRITE_REG32(EMBx->STATCLR, (EMB_STATCLR_PWMSFCLR | \ + EMB_STATCLR_CMPFCLR | \ + EMB_STATCLR_OSFCLR | \ + EMB_STATCLR_PORTINFCLR1 | \ + EMB_STATCLR_PORTINFCLR2 | \ + EMB_STATCLR_PORTINFCLR3 | \ + EMB_STATCLR_PORTINFCLR4)); +} + +/** + * @brief Set the EMB interrupt function + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] u32IntSource EMB interrupt source + * This parameter can be one of the following values: + * @arg EMB_INT_PWMS: PWM same phase event interrupt + * @arg EMB_INT_CMP: CMP result event interrupt + * @arg EMB_INT_OSC: OSC stop event interrupt + * @arg EMB_INT_PORT1: Port1 input event interrupt + * @arg EMB_INT_PORT2: Port2 input event interrupt + * @arg EMB_INT_PORT3: Port3 input event interrupt + * @arg EMB_INT_PORT4: Port4 input event interrupt + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void EMB_IntCmd(M4_EMB_TypeDef *EMBx, + uint32_t u32IntSource, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + DDL_ASSERT(IS_VALID_EMB_INT(u32IntSource)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(EMBx->INTEN, u32IntSource); + } + else + { + CLEAR_REG32_BIT(EMBx->INTEN, u32IntSource); + } +} + +/** + * @brief Set EMB release PWM mode + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] u32Event Monitor event + * This parameter can be any composed value of the following values: + * @arg EMB_EVENT_PWMS: PWM same phase event + * @arg EMB_EVENT_CMP: CMP result event + * @arg EMB_EVENT_OSC: OSC stop event + * @arg EMB_EVENT_PORT1: Port1 input event + * @arg EMB_EVENT_PORT2: Port2 input event + * @arg EMB_EVENT_PORT3: Port3 input event + * @arg EMB_EVENT_PORT4: Port4 input event + * @param [in] u32Mode Release mode + * This parameter can be one of the following values: + * @arg EMB_RELEASE_PWM_SEL_FLAG_ZERO: Release PWM when flag bit is zero + * @arg EMB_RELEASE_PWM_SEL_STATE_ZERO: Release PWM when state bit is zero + * @retval None + */ +void EMB_SetReleasePwmMode(M4_EMB_TypeDef *EMBx, + uint32_t u32Event, + uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + DDL_ASSERT(IS_VALID_EMB_MONITOR_EVENT(u32Event)); + DDL_ASSERT(IS_VALID_EMB_RELEASE_PWM_SEL(u32Mode)); + + if (EMB_RELEASE_PWM_SEL_FLAG_ZERO == u32Mode) + { + CLEAR_REG32_BIT(EMBx->RLSSEL, u32Event); + } + else + { + SET_REG32_BIT(EMBx->RLSSEL, u32Event); + } +} + +/** + * @brief Get EMB status + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] u32Flag EMB flag + * This parameter can be one of the following values: + * @arg EMB_FLAG_PWMS: PWM same phase trigger stop PWM + * @arg EMB_FLAG_CMP: CMP trigger stop PWM + * @arg EMB_FLAG_OSC: OSC trigger stop PWM + * @arg EMB_FLAG_PORT1: EMB Port1 input trigger stop PWM + * @arg EMB_FLAG_PORT2: EMB Port2 input trigger stop PWM + * @arg EMB_FLAG_PORT3: EMB Port3 input trigger stop PWM + * @arg EMB_FLAG_PORT4: EMB Port4 input trigger stop PWM + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t EMB_GetFlag(const M4_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + DDL_ASSERT(IS_VALID_EMB_FLAG(u32Flag)); + + return READ_REG32_BIT(EMBx->STAT, u32Flag) ? Set : Reset; +} + +/** + * @brief Get EMB status + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] u32Flag EMB flag + * This parameter can be one of the following values: + * @arg EMB_FLAG_PWMS: PWM same phase trigger stop PWM + * @arg EMB_FLAG_CMP: CMP trigger stop PWM + * @arg EMB_FLAG_OSC: OSC trigger stop PWM + * @arg EMB_FLAG_PORT1: EMB Port1 input trigger stop PWM + * @arg EMB_FLAG_PORT2: EMB Port2 input trigger stop PWM + * @arg EMB_FLAG_PORT3: EMB Port3 input trigger stop PWM + * @arg EMB_FLAG_PORT4: EMB Port4 input trigger stop PWM + * @retval None + */ +void EMB_ClearFlag(M4_EMB_TypeDef *EMBx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + DDL_ASSERT(IS_VALID_EMB_FLAG(u32Flag)); + + SET_REG32_BIT(EMBx->STATCLR, u32Flag); +} + +/** + * @brief Get EMB status + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] u32Status EMB state + * This parameter can be one of the following values: + * @arg EMB_STATE_PWMS: PWM same phase occur + * @arg EMB_STATE_CMP: CMP comapre event occur + * @arg EMB_STATE_OSC: OSC stop event occur + * @arg EMB_STATE_PORT1: EMB Port1 input control state + * @arg EMB_STATE_PORT2: EMB Port2 input control state + * @arg EMB_STATE_PORT3: EMB Port3 input control state + * @arg EMB_STATE_PORT4: EMB Port4 input control state + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t EMB_GetStatus(const M4_EMB_TypeDef *EMBx, + uint32_t u32Status) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + DDL_ASSERT(IS_VALID_EMB_STATUS(u32Status)); + + return READ_REG32_BIT(EMBx->STAT, u32Status) ? Set : Reset; +} + +/** + * @brief Start/stop EMB software brake + * @param [in] EMBx Pointer to EMB instance register base + * This parameter can be one of the following values: + * @arg M4_EMB0: EMB group 0 instance register base + * @arg M4_EMB1: EMB group 1 instance register base + * @arg M4_EMB2: EMB group 2 instance register base + * @arg M4_EMB3: EMB group 3 instance register base + * @arg M4_EMB4: EMB group 4 instance register base + * @arg M4_EMB5: EMB group 5 instance register base + * @arg M4_EMB6: EMB group 6 instance register base + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void EMB_SwBrake(M4_EMB_TypeDef *EMBx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_EMB(EMBx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(EMBx->SOE, enNewState); +} + +/** + * @} + */ + +#endif /* DDL_EMB_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_eth.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_eth.c new file mode 100644 index 0000000000000000000000000000000000000000..61da6d24429a819c762b9e3976d34d16afc1c2fd --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_eth.c @@ -0,0 +1,4709 @@ +/** + ******************************************************************************* + * @file hc32f4a0_eth.c + * @brief This file provides firmware functions to manage the Ethernet MAC + * Controller(ETH). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-07-03 Yangjp Optimize stc_eth_mac_init_t structure + 2020-08-11 Yangjp Fixed a known potential risk in ETH_Init function + 2020-09-04 Yangjp Optimize timeout handling in functions + 2020-11-26 Yangjp Fixed a known potential risk in ETH_DMA_GetReceiveFrame_Interrupt function + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_eth.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_ETH ETH + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (DDL_ETH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup ETH_Local_Macros ETH Local Macros + * @{ + */ + +/* Ethernet MAC_IFCONFR register Mask */ +#define ETH_MAC_IFCONFR_CLEAR_MASK (ETH_MAC_IFCONFR_RCKINV | ETH_MAC_IFCONFR_TCKINV) + +/* Ethernet MAC_CONFIGR register Mask */ +#define ETH_MAC_CONFIGR_CLEAR_MASK (0x72CF7EF0UL) + +/* Ethernet MAC_FLOCTLR register Mask */ +#define ETH_MAC_FLOCTLR_CLEAR_MASK (0xFFFF00BEUL) + +/* Ethernet MAC_FLTCTLR register Mask */ +#define ETH_MAC_FLTCTLR_CLEAR_MASK (0x802107FFUL) + +/* Ethernet MAC_SMIADDR register Mask */ +#define ETH_MAC_SMIADDR_CLEAR_MASK (0x0000FFC3UL) + +/* Ethernet DMA_BUSMODR register Mask */ +#define ETH_DMA_BUSMODR_CLEAR_MASK (0x0FFFFFFEUL) + +/* Ethernet DMA_OPRMODR register Mask */ +#define ETH_DMA_OPRMODR_CLEAR_MASK (0x0721C0FCUL) + +/* Ethernet PTP_TSPCTLR register Mask */ +#define ETH_PTP_TSPCTLR_CLEAR_MASK (0x0007FE02UL) + +/* Ethernet MAC Address byte length */ +#define ETH_MAC_ADDRESS_BYTE_LENGTH (6U) + +/* Ethernet DMA Tx descriptors Collision Count Shift */ +#define ETH_DMATXDESC_COLLISION_COUNTSHIFT (3UL) + +/* Ethernet DMA Rx descriptors Frame Length Shift */ +#define ETH_DMARXDESC_FRAME_LENGTHSHIFT (16UL) + +/* Ethernet DMA Tx/Rx descriptors Buffer2 Size Shift */ +#define ETH_DMADESC_BUFFER2_SIZESHIFT (16UL) + +/* Ethernet Remote Wake-up frame register length */ +#define ETH_WAKEUP_REGISTER_LENGTH (8U) + +/* Ethernet PTP PPS channel 1 time register address Shift */ +#define ETH_PTP_PPS1_TIME_REG_ADDRSHIFT (0x64U) + +/* Wait timeout(ms) */ +#define ETH_TIMEOUT_WRITE_REGISTER (50UL) +#define ETH_TIMEOUT_SOFTWARE_RESET (200UL) +#define ETH_TIMEOUT_LINK_STATUS (500UL) +#define ETH_TIMEOUT_AUTONEGO_COMPLETE (1000UL) + + +/** + * @defgroup ETH_MAC_Address_Register ETH MAC Address Register + * @brief Get the specified register address of the ETH MAC Address + * @{ + */ +#define ETH_MAC_MACADHRx(__SHIFT__) ((uint32_t)(&(M4_ETH->MAC_MACADHR0)) + (uint32_t)(__SHIFT__)) +#define ETH_MAC_MACADLRx(__SHIFT__) ((uint32_t)(&(M4_ETH->MAC_MACADLR0)) + (uint32_t)(__SHIFT__)) +/** + * @} + */ + +/** + * @defgroup ETH_PTP_Register ETH PTP Register + * @brief Get the specified register address of the ETH PTP PPS channel + * @{ + */ +#define ETH_PTP_TMTSECRx(__SHIFT__) ((uint32_t)(&(M4_ETH->PTP_TMTSECR0)) + (uint32_t)(__SHIFT__)) +#define ETH_PTP_TMTNSERx(__SHIFT__) ((uint32_t)(&(M4_ETH->PTP_TMTNSER0)) + (uint32_t)(__SHIFT__)) +/** + * @} + */ + +/** + * @defgroup ETH_Check_Parameters_Validity ETH Check Parameters Validity + * @{ + */ +#define IS_ETH_PHY_ADDRESS(x) ((x) < 0x20U) + +#define IS_ETH_PHY_REGISTER(x) ((x) < 0x20U) + +#define IS_ETH_AUTO_NEGOTIATION(x) \ +( ((x) == ETH_AUTO_NEGOTIATION_DISABLE) || \ + ((x) == ETH_AUTO_NEGOTIATION_ENABLE)) + +#define IS_ETH_MAC_CHECKSUM_MODE(x) \ +( ((x) == ETH_MAC_CHECKSUM_MODE_SOFTWARE) || \ + ((x) == ETH_MAC_CHECKSUM_MODE_HARDWARE)) + +#define IS_ETH_RX_MODE(x) \ +( ((x) == ETH_RX_MODE_POLLING) || \ + ((x) == ETH_RX_MODE_INTERRUPT)) + +#define IS_ETH_MAC_MEDIA_INTERFACE(x) \ +( ((x) == ETH_MAC_MEDIA_INTERFACE_MII) || \ + ((x) == ETH_MAC_MEDIA_INTERFACE_RMII)) + +#define IS_ETH_MAC_SPEED(x) \ +( ((x) == ETH_MAC_SPEED_10M) || \ + ((x) == ETH_MAC_SPEED_100M)) + +#define IS_ETH_MAC_DUPLEX_MODE(x) \ +( ((x) == ETH_MAC_MODE_HALFDUPLEX) || \ + ((x) == ETH_MAC_MODE_FULLDUPLEX)) + +#define IS_ETH_MAC_TX_CLK_POLARITY(x) \ +( ((x) == ETH_MAC_TX_CLK_POLARITY_KEEP) || \ + ((x) == ETH_MAC_TX_CLK_POLARITY_INVERSE)) + +#define IS_ETH_MAC_RX_REF_CLK_POLARITY(x) \ +( ((x) == ETH_MAC_RX_REF_CLK_POLARITY_KEEP) || \ + ((x) == ETH_MAC_RX_REF_CLK_POLARITY_INVERSE)) + +#define IS_ETH_MAC_SA_MODE(x) \ +( ((x) == ETH_MAC_SA_MODE_BY_DMATXDESC) || \ + ((x) == ETH_MAC_SA_MODE_INSTER_MACADDR0) || \ + ((x) == ETH_MAC_SA_MODE_REPLACE_MACADDR0) || \ + ((x) == ETH_MAC_SA_MODE_INSTER_MACADDR1) || \ + ((x) == ETH_MAC_SA_MODE_REPLACE_MACADDR1)) + +#define IS_ETH_MAC_TYPEFRAME_STRIP_FCS(x) \ +( ((x) == ETH_MAC_TYPEFRAME_STRIP_FCS_DISABLE) || \ + ((x) == ETH_MAC_TYPEFRAME_STRIP_FCS_ENABLE)) + +#define IS_ETH_MAC_WATCHDOG(x) \ +( ((x) == ETH_MAC_WATCHDOG_DISABLE) || \ + ((x) == ETH_MAC_WATCHDOG_ENABLE)) + +#define IS_ETH_MAC_JABBER(x) \ +( ((x) == ETH_MAC_JABBER_DISABLE) || \ + ((x) == ETH_MAC_JABBER_ENABLE)) + +#define IS_ETH_MAC_INTERFRAME_GAP(x) \ +( ((x) == ETH_MAC_INTERFRAME_GAP_96BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_88BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_80BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_72BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_64BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_56BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_48BIT) || \ + ((x) == ETH_MAC_INTERFRAME_GAP_40BIT)) + +#define IS_ETH_MAC_CARRIER_SENCE(x) \ +( ((x) == ETH_MAC_CARRIER_SENCE_DISABLE) || \ + ((x) == ETH_MAC_CARRIER_SENCE_ENABLE)) + +#define IS_ETH_MAC_RECEIVE_OWN(x) \ +( ((x) == ETH_MAC_RECEIVE_OWN_DISABLE) || \ + ((x) == ETH_MAC_RECEIVE_OWN_ENABLE)) + +#define IS_ETH_MAC_CHECKSUM_OFFLAOD(x) \ +( ((x) == ETH_MAC_CHECKSUM_OFFLAOD_DISABLE) || \ + ((x) == ETH_MAC_CHECKSUM_OFFLAOD_ENABLE)) + +#define IS_ETH_MAC_RETRY_TRANSMIT(x) \ +( ((x) == ETH_MAC_RETRY_TRANSMIT_DISABLE) || \ + ((x) == ETH_MAC_RETRY_TRANSMIT_ENABLE)) + +#define IS_ETH_MAC_AUTO_STRIP_PAD_FCS(x) \ +( ((x) == ETH_MAC_AUTO_STRIP_PAD_FCS_DISABLE) || \ + ((x) == ETH_MAC_AUTO_STRIP_PAD_FCS_ENABLE)) + +#define IS_ETH_MAC_BACKOFF_LIMIT(x) \ +( ((x) == ETH_MAC_BACKOFF_LIMIT_10) || \ + ((x) == ETH_MAC_BACKOFF_LIMIT_8) || \ + ((x) == ETH_MAC_BACKOFF_LIMIT_4) || \ + ((x) == ETH_MAC_BACKOFF_LIMIT_1)) + +#define IS_ETH_MAC_DEFFERRAL_CHECK(x) \ +( ((x) == ETH_MAC_DEFFERRAL_CHECK_DISABLE) || \ + ((x) == ETH_MAC_DEFFERRAL_CHECK_ENABLE)) + +#define IS_ETH_MAC_ZERO_QUANTA_PAUSE(x) \ +( ((x) == ETH_MAC_ZERO_QUANTA_PAUSE_DISABLE) || \ + ((x) == ETH_MAC_ZERO_QUANTA_PAUSE_ENABLE)) + +#define IS_ETH_MAC_PAUSE_LOWTHRESHOLD(x) \ +( ((x) == ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS4) || \ + ((x) == ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS28) || \ + ((x) == ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS144) || \ + ((x) == ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS256)) + +#define IS_ETH_MAC_UNICAST_PAUSEFRAME_DETECT(x) \ +( ((x) == ETH_MAC_UNICAST_PAUSEFRAME_DETECT_DISABLE) || \ + ((x) == ETH_MAC_UNICAST_PAUSEFRAME_DETECT_ENABLE)) + +#define IS_ETH_MAC_RECEIVE_FLOWCONTROL(x) \ +( ((x) == ETH_MAC_RECEIVE_FLOWCONTROL_DISABLE) || \ + ((x) == ETH_MAC_RECEIVE_FLOWCONTROL_ENABLE)) + +#define IS_ETH_MAC_TRANSMIT_FLOWCONTROL(x) \ +( ((x) == ETH_MAC_TRANSMIT_FLOWCONTROL_DISABLE) || \ + ((x) == ETH_MAC_TRANSMIT_FLOWCONTROL_ENABLE)) + +#define IS_ETH_MAC_RECEIVE_All(x) \ +( ((x) == ETH_MAC_RECEIVE_All_DISABLE) || \ + ((x) == ETH_MAC_RECEIVE_ALL_ENABLE)) + +#define IS_ETH_MAC_DROP_NOT_TCPUDP(x) \ +( ((x) == ETH_MAC_DROP_NOT_TCPUDP_DISABLE) || \ + ((x) == ETH_MAC_DROP_NOT_TCPUDP_ENABLE)) + +#define IS_ETH_MAC_VLAN_TAG_FILTER(x) \ +( ((x) == ETH_MAC_VLAN_TAG_FILTER_DISABLE) || \ + ((x) == ETH_MAC_VLAN_TAG_FILTER_ENABLE)) + +#define IS_ETH_MAC_SOURCE_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_SOURCE_ADDR_FILTER_DISABLE) || \ + ((x) == ETH_MAC_SOURCE_ADDR_FILTER_NORMAL) || \ + ((x) == ETH_MAC_SOURCE_ADDR_FILTER_INVERSE)) + +#define IS_ETH_MAC_PASS_CTRLFRAME(x) \ +( ((x) == ETH_MAC_PASS_CTRLFRAME_BLOCK_ALL) || \ + ((x) == ETH_MAC_PASS_CTRLFRAME_FORWARD_NOTPAUSE_ALL) || \ + ((x) == ETH_MAC_PASS_CTRLFRAME_FORWARD_ALL) || \ + ((x) == ETH_MAC_PASS_CTRLFRAME_FORWARD_PASSADDRFILTER)) + +#define IS_ETH_MAC_BROADCASTFRAME_RECEPTION(x) \ +( ((x) == ETH_MAC_BROADCASTFRAME_RECEPTION_DISABLE) || \ + ((x) == ETH_MAC_BROADCASTFRAME_RECEPTION_ENABLE)) + +#define IS_ETH_MAC_DESTINATION_ADDR_FILTER(x) \ +( ((x) == ETH_MAC_DESTINATION_ADDR_FILTER_NORMAL) || \ + ((x) == ETH_MAC_DESTINATION_ADDR_FILTER_INVERSE)) + +#define IS_ETH_MAC_MULTICASTFRAME_FILTER(x) \ +( ((x) == ETH_MAC_MULTICASTFRAME_FILTER_NONE) || \ + ((x) == ETH_MAC_MULTICASTFRAME_FILTER_PERFECT) || \ + ((x) == ETH_MAC_MULTICASTFRAME_FILTER_HASHTABLE) || \ + ((x) == ETH_MAC_MULTICASTFRAME_FILTER_PERFECTHASHTABLE)) + +#define IS_ETH_MAC_UNICASTFRAME_FILTER(x) \ +( ((x) == ETH_MAC_UNICASTFRAME_FILTER_PERFECT) || \ + ((x) == ETH_MAC_UNICASTFRAME_FILTER_HASHTABLE) || \ + ((x) == ETH_MAC_UNICASTFRAME_FILTER_PERFECTHASHTABLE)) + +#define IS_ETH_MAC_PROMISCUOUS_MODE(x) \ +( ((x) == ETH_MAC_PROMISCUOUS_MODE_DISABLE) || \ + ((x) == ETH_MAC_PROMISCUOUS_MODE_ENABLE)) + +#define IS_ETH_MAC_TXVLAN_MODE(x) \ +( ((x) == ETH_MAC_TXVLAN_MODE_BY_DMATXDESC) || \ + ((x) == ETH_MAC_TXVLAN_MODE_BYPASS) || \ + ((x) == ETH_MAC_TXVLAN_MODE_REMOVE_TAG) || \ + ((x) == ETH_MAC_TXVLAN_MODE_INSERT_TAG) || \ + ((x) == ETH_MAC_TXVLAN_MODE_REPLACE_TAG)) + +#define IS_ETH_MAC_RXVLAN_FILTER(x) \ +( ((x) == ETH_MAC_RXVLAN_FILTER_NORMAL) || \ + ((x) == ETH_MAC_RXVLAN_FILTER_INVERSE) || \ + ((x) == ETH_MAC_RXVLAN_FILTER_NORMAL_HASHTABLE) || \ + ((x) == ETH_MAC_RXVLAN_FILTER_INVERSE_HASHTABLE)) + +#define IS_ETH_MAC_RXVLAN_COMPARISON(x) \ +( ((x) == ETH_MAC_RXVLAN_COMPARISON_16BIT) || \ + ((x) == ETH_MAC_RXVLAN_COMPARISON_12BIT)) + +#define IS_ETH_MAC_L4_DESTPORT_FILTER(x) \ +( ((x) == ETH_MAC_L4_DESTPORT_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L4_DESTPORT_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L4_DESTPORT_FILTER_INVERSE)) + +#define IS_ETH_MAC_L4_SOURCEPORT_FILTER(x) \ +( ((x) == ETH_MAC_L4_SOURCEPORT_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L4_SOURCEPORT_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L4_SOURCEPORT_FILTER_INVERSE)) + +#define IS_ETH_MAC_L4_PORT_FILTER_PROTOCOL(x) \ +( ((x) == ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP) || \ + ((x) == ETH_MAC_L4_PORT_FILTER_PROTOCOL_UDP)) + +#define IS_ETH_MAC_L3_DA_FILTER_MASK(x) \ +( ((x) | ETH_MAC_L34CTLR_L3HDBM) == ETH_MAC_L34CTLR_L3HDBM) + +#define IS_ETH_MAC_L3_SA_FILTER_MASK(x) \ +( ((x) | ETH_MAC_L34CTLR_L3HSBM) == ETH_MAC_L34CTLR_L3HSBM) + +#define IS_ETH_MAC_L3_DA_SA_FILTER_MASK(x) \ +( 0UL == ((x) & ((uint32_t)(~(ETH_MAC_L34CTLR_L3HSBM | \ + ETH_MAC_L34CTLR_L3HDBM_0 | \ + ETH_MAC_L34CTLR_L3HDBM_1))))) + +#define IS_ETH_MAC_L3_DA_FILTER(x) \ +( ((x) == ETH_MAC_L3_DA_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L3_DA_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L3_DA_FILTER_INVERSE)) + +#define IS_ETH_MAC_L3_SA_FILTER(x) \ +( ((x) == ETH_MAC_L3_SA_FILTER_DISABLE) || \ + ((x) == ETH_MAC_L3_SA_FILTER_NORMAL) || \ + ((x) == ETH_MAC_L3_SA_FILTER_INVERSE)) + +#define IS_ETH_MAC_L3_ADDR_FILTER_PROTOCOL(x) \ +( ((x) == ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4) || \ + ((x) == ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV6)) + +#define IS_ETH_MAC_INTERRUPT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_MAC_INT_FLAG_TSPIS | \ + ETH_MAC_INT_FLAG_MMCTXIS | \ + ETH_MAC_INT_FLAG_MMCRXIS | \ + ETH_MAC_INT_FLAG_MMCIS | \ + ETH_MAC_INT_FLAG_PMTIS)))))) + +#define IS_ETH_MAC_INTERRUPT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_MAC_INT_TSPIM | \ + ETH_MAC_INT_PMTIM)))))) + +#define IS_ETH_MAC_ADDRESS_NORMAL_INDEX(x) \ +( ((x) == ETH_MAC_ADDRESS0) || \ + ((x) == ETH_MAC_ADDRESS1) || \ + ((x) == ETH_MAC_ADDRESS2) || \ + ((x) == ETH_MAC_ADDRESS3) || \ + ((x) == ETH_MAC_ADDRESS4)) + +#define IS_ETH_MAC_ADDRESS_SPECIAL_INDEX(x) \ +( ((x) == ETH_MAC_ADDRESS1) || \ + ((x) == ETH_MAC_ADDRESS2) || \ + ((x) == ETH_MAC_ADDRESS3) || \ + ((x) == ETH_MAC_ADDRESS4)) + +#define IS_ETH_MAC_ADDRESS_FILTER(x) \ +( ((x) == ETH_MAC_ADDRESS_FILTER_DISABLE) || \ + ((x) == ETH_MAC_ADDRESS_FILTER_PERFECT_DA) || \ + ((x) == ETH_MAC_ADDRESS_FILTER_PERFECT_SA)) + +#define IS_ETH_MAC_ADDRESS_MASK(x) \ +( ((x) | ETH_MAC_ADDRESS_MASK_ALL) == ETH_MAC_ADDRESS_MASK_ALL) + +#define IS_ETH_DMA_DESC_SKIP_LENGTH(x) ((x) < 0x20U) + +#define IS_ETH_DMA_BURST_MODE(x) \ +( ((x) == ETH_DMA_BURST_MODE_NORMAL) || \ + ((x) == ETH_DMA_BURST_MODE_FIXED) || \ + ((x) == ETH_DMA_BURST_MODE_MIXED)) + +#define IS_ETH_DMA_ADDRESS_ALIGN(x) \ +( ((x) == ETH_DMA_ADDRESS_ALIGN_DISABLE) || \ + ((x) == ETH_DMA_ADDRESS_ALIGN_ENABLE)) + +#define IS_ETH_DMA_RX_BURST_LENGTH(x) \ +( ((x) == ETH_DMA_RX_BURST_LENGTH_1BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_2BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_4BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_16BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_32BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8XPBL_8BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8XPBL_16BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8XPBL_32BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8XPBL_64BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8XPBL_128BEAT) || \ + ((x) == ETH_DMA_RX_BURST_LENGTH_8XPBL_256BEAT)) + +#define IS_ETH_DMA_TX_BURST_LENGTH(x) \ +( ((x) == ETH_DMA_TX_BURST_LENGTH_1BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_2BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_4BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_16BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_32BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8XPBL_8BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8XPBL_16BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8XPBL_32BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8XPBL_64BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8XPBL_128BEAT) || \ + ((x) == ETH_DMA_TX_BURST_LENGTH_8XPBL_256BEAT)) + +#define IS_ETH_DMA_ENHANCE_DESCRIPTOR(x) \ +( ((x) == ETH_DMA_ENHANCE_DESCRIPTOR_DISABLE) || \ + ((x) == ETH_DMA_ENHANCE_DESCRIPTOR_ENABLE)) + +#define IS_ETH_DMA_PRIORITY_ARBITRATION(x) \ +( ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_1_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_2_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_3_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_RXTX_4_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_1_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_2_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_3_1) || \ + ((x) == ETH_DMA_ARBITRATION_LOOP_TXRX_4_1) || \ + ((x) == ETH_DMA_ARBITRATION_FIXED_RXPRIORTX) || \ + ((x) == ETH_DMA_ARBITRATION_FIXED_TXPRIORRX)) + +#define IS_ETH_DMA_DROP_CHECKSUM_ERRORFRAME(x) \ +( ((x) == ETH_DMA_DROP_CHECKSUM_ERRORFRAME_DISABLE) || \ + ((x) == ETH_DMA_DROP_CHECKSUM_ERRORFRAME_ENABLE)) + +#define IS_ETH_DMA_RECEIVE_STORE_FORWARD(x) \ +( ((x) == ETH_DMA_RECEIVE_STORE_FORWARD_DISABLE) || \ + ((x) == ETH_DMA_RECEIVE_STORE_FORWARD_ENABLE)) + +#define IS_ETH_DMA_FLUSH_RECEIVEDFRAME(x) \ +( ((x) == ETH_DMA_FLUSH_RECEIVEDFRAME_DISABLE) || \ + ((x) == ETH_DMA_FLUSH_RECEIVEDFRAME_ENABLE)) + +#define IS_ETH_DMA_TRANSMIT_STORE_FORWARD(x) \ +( ((x) == ETH_DMA_TRANSMIT_STORE_FORWARD_DISABLE) || \ + ((x) == ETH_DMA_TRANSMIT_STORE_FORWARD_ENABLE)) + +#define IS_ETH_DMA_TRANSMIT_THRESHOLD(x) \ +( ((x) == ETH_DMA_TRANSMIT_THRESHOLD_64BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_128BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_192BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_256BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_40BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_32BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_24BYTE) || \ + ((x) == ETH_DMA_TRANSMIT_THRESHOLD_16BYTE)) + +#define IS_ETH_DMA_FORWARD_ERRORFRAME(x) \ +( ((x) == ETH_DMA_FORWARD_ERRORFRAME_DISABLE) || \ + ((x) == ETH_DMA_FORWARD_ERRORFRAME_ENABLE)) + +#define IS_ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME(x) \ +( ((x) == ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME_DISABLE) || \ + ((x) == ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME_ENABLE)) + +#define IS_ETH_DMA_DROP_JUMBO_FRAME(x) \ +( ((x) == ETH_DMA_DROP_JUMBO_FRAME_DISABLE) || \ + ((x) == ETH_DMA_DROP_JUMBO_FRAME_ENABLE)) + +#define IS_ETH_DMA_RECEIVE_THRESHOLD(x) \ +( ((x) == ETH_DMA_RECEIVE_THRESHOLD_64BYTE) || \ + ((x) == ETH_DMA_RECEIVE_THRESHOLD_32BYTE) || \ + ((x) == ETH_DMA_RECEIVE_THRESHOLD_96BYTE) || \ + ((x) == ETH_DMA_RECEIVE_THRESHOLD_128BYTE)) + +#define IS_ETH_DMA_SECONDFRAME_OPERARTE(x) \ +( ((x) == ETH_DMA_SECONDFRAME_OPERARTE_DISABLE) || \ + ((x) == ETH_DMA_SECONDFRAME_OPERARTE_ENABLE)) + +#define IS_ETH_DMA_INTERRUPT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_DMA_INT_NIE | \ + ETH_DMA_INT_AIE | \ + ETH_DMA_INT_ERE | \ + ETH_DMA_INT_FBE | \ + ETH_DMA_INT_ETE | \ + ETH_DMA_INT_RWE | \ + ETH_DMA_INT_RSE | \ + ETH_DMA_INT_RUE | \ + ETH_DMA_INT_RIE | \ + ETH_DMA_INT_UNE | \ + ETH_DMA_INT_OVE | \ + ETH_DMA_INT_TJE | \ + ETH_DMA_INT_TUE | \ + ETH_DMA_INT_TSE | \ + ETH_DMA_INT_TIE)))))) + +#define IS_ETH_DMA_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_DMA_FLAG_PTPS | \ + ETH_DMA_FLAG_PMTS | \ + ETH_DMA_FLAG_MMCS | \ + ETH_DMA_FLAG_NIS | \ + ETH_DMA_FLAG_AIS | \ + ETH_DMA_FLAG_ERS | \ + ETH_DMA_FLAG_FBS | \ + ETH_DMA_FLAG_ETS | \ + ETH_DMA_FLAG_RWS | \ + ETH_DMA_FLAG_RSS | \ + ETH_DMA_FLAG_RUS | \ + ETH_DMA_FLAG_RIS | \ + ETH_DMA_FLAG_UNS | \ + ETH_DMA_FLAG_OVS | \ + ETH_DMA_FLAG_TJS | \ + ETH_DMA_FLAG_TUS | \ + ETH_DMA_FLAG_TSS | \ + ETH_DMA_FLAG_TIS)))))) + +#define IS_ETH_DMA_MISS_FRAME_TYPE(x) \ +( ((x) == ETH_DMA_OVERFLOW_RXFIFO_COUNTER) || \ + ((x) == ETH_DMA_OVERFLOW_MISSFRAME_COUNTER)) + +#define IS_ETH_DMATXDESC_BUFFER_SIZE(x) ((x) <= 0x1FFFFFFFUL) + +#define IS_ETH_DMATXDESC_CHECKSUM_CONTROL(x) \ +( ((x) == ETH_DMATXDESC_CHECKSUM_BYPASS) || \ + ((x) == ETH_DMATXDESC_CHECKSUM_IPV4HEADER) || \ + ((x) == ETH_DMATXDESC_CHECKSUM_TCPUDPICMP_SEGMENT) || \ + ((x) == ETH_DMATXDESC_CHECKSUM_TCPUDPICMP_FULL)) + +#define IS_ETH_DMATXDESC_VLAN_CONTROL(x) \ +( ((x) == ETH_DMATXDESC_VLAN_BYPASS) || \ + ((x) == ETH_DMATXDESC_VLAN_REMOVE_TAG) || \ + ((x) == ETH_DMATXDESC_VLAN_INSERT_TAG) || \ + ((x) == ETH_DMATXDESC_VLAN_REPLACE_TAG)) + +#define IS_ETH_DMATXDESC_SA_CONTROL(x) \ +( ((x) == ETH_DMATXDESC_SA_BYPASS) || \ + ((x) == ETH_DMATXDESC_SA_INSTER_MACADDR0) || \ + ((x) == ETH_DMATXDESC_SA_REPLACE_MACADDR0) || \ + ((x) == ETH_DMATXDESC_SA_INSTER_MACADDR1) || \ + ((x) == ETH_DMATXDESC_SA_REPLACE_MACADDR1)) + +#define IS_ETH_DMATXDESC_STATUS(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_DMATXDESC_OWN | \ + ETH_DMATXDESC_IOC | \ + ETH_DMATXDESC_TLS | \ + ETH_DMATXDESC_TFS | \ + ETH_DMATXDESC_DCRC | \ + ETH_DMATXDESC_DPAD | \ + ETH_DMATXDESC_TTSE | \ + ETH_DMATXDESC_CRCR | \ + ETH_DMATXDESC_TER | \ + ETH_DMATXDESC_TSAC | \ + ETH_DMATXDESC_TTSS | \ + ETH_DMATXDESC_IHE | \ + ETH_DMATXDESC_ETSUM | \ + ETH_DMATXDESC_JTE | \ + ETH_DMATXDESC_FFF | \ + ETH_DMATXDESC_TPCE | \ + ETH_DMATXDESC_LOCE | \ + ETH_DMATXDESC_NCE | \ + ETH_DMATXDESC_TLCE | \ + ETH_DMATXDESC_ECE | \ + ETH_DMATXDESC_VLF | \ + ETH_DMATXDESC_EDE | \ + ETH_DMATXDESC_UDE | \ + ETH_DMATXDESC_DEE)))))) + +#define IS_ETH_DMARXDESC_STATUS(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_DMARXDESC_OWN | \ + ETH_DMARXDESC_DAF | \ + ETH_DMARXDESC_ERSUM | \ + ETH_DMARXDESC_DPE | \ + ETH_DMARXDESC_SAF | \ + ETH_DMARXDESC_LEE | \ + ETH_DMARXDESC_OVE | \ + ETH_DMARXDESC_VLAT | \ + ETH_DMARXDESC_RFS | \ + ETH_DMARXDESC_RLS | \ + ETH_DMARXDESC_IPE_TSPA_GF | \ + ETH_DMARXDESC_RLCE | \ + ETH_DMARXDESC_FRAT | \ + ETH_DMARXDESC_WTE | \ + ETH_DMARXDESC_REE | \ + ETH_DMARXDESC_DBE | \ + ETH_DMARXDESC_CRE | \ + ETH_DMARXDESC_DAS_ESA)))))) + +#define IS_ETH_DMARXDESC_EXTEND_STATUS(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_DMARXDESC_L4FMS | \ + ETH_DMARXDESC_L3FMS | \ + ETH_DMARXDESC_TSPD | \ + ETH_DMARXDESC_PTPV | \ + ETH_DMARXDESC_PTPFT | \ + ETH_DMARXDESC_IPV6DR | \ + ETH_DMARXDESC_IPV4DR | \ + ETH_DMARXDESC_IPCB | \ + ETH_DMARXDESC_IPPE | \ + ETH_DMARXDESC_IPHE)))))) + +#define IS_ETH_DMADESC_OWN(x) \ +( ((x) == ETH_DMADESC_OWN_CPU) || \ + ((x) == ETH_DMADESC_OWN_DMA)) + +#define IS_ETH_DMADESC_BUFFER(x) \ +( ((x) == ETH_DMADESC_BUFFER1) || \ + ((x) == ETH_DMADESC_BUFFER2)) + +#define IS_ETH_PMT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_PMT_FLAG_RTWKFR | \ + ETH_PMT_FLAG_WKFR | \ + ETH_PMT_FLAG_MPFR)))))) + +#define IS_ETH_MMC_COUNTER_PRESETMODE(x) \ +( ((x) == ETH_MMC_COUNTER_PRESETMODE_DISABLE) || \ + ((x) == ETH_MMC_COUNTER_PRESETMODE_HALFVALUE) || \ + ((x) == ETH_MMC_COUNTER_PRESETMODE_FULLVALUE)) + +#define IS_ETH_MMC_READ_RESET(x) \ +( ((x) == ETH_MMC_READ_RESET_ENABLE) || \ + ((x) == ETH_MMC_READ_RESET_DISABLE)) + +#define IS_ETH_MMC_COUNTER_RELOAD(x) \ +( ((x) == ETH_MMC_COUNTER_RELOAD_ENABLE) || \ + ((x) == ETH_MMC_COUNTER_RELOAD_DISABLE)) + +#define IS_ETH_MMC_TX_INTERRUPT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_MMC_INT_TXEDEIM | \ + ETH_MMC_INT_TXUGIM | \ + ETH_MMC_INT_TXCAEIM | \ + ETH_MMC_INT_TXECEIM | \ + ETH_MMC_INT_TXLCEIM | \ + ETH_MMC_INT_TXDEEIM | \ + ETH_MMC_INT_TXMGIM | \ + ETH_MMC_INT_TXBGIM)))))) + +#define IS_ETH_MMC_RX_INTERRUPT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_MMC_INT_RXOEIM | \ + ETH_MMC_INT_RXLEIM | \ + ETH_MMC_INT_RXUGIM | \ + ETH_MMC_INT_RXREIM | \ + ETH_MMC_INT_RXAEIM | \ + ETH_MMC_INT_RXCEIM | \ + ETH_MMC_INT_RXMGIM | \ + ETH_MMC_INT_RXBGIM)))))) + +#define IS_ETH_MMC_TX_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_MMC_FLAG_TXEDEIS | \ + ETH_MMC_FLAG_TXUGIS | \ + ETH_MMC_FLAG_TXCAEIS | \ + ETH_MMC_FLAG_TXECEIS | \ + ETH_MMC_FLAG_TXLCEIS | \ + ETH_MMC_FLAG_TXDEEIS | \ + ETH_MMC_FLAG_TXMGIS | \ + ETH_MMC_FLAG_TXBGIS)))))) + +#define IS_ETH_MMC_RX_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_MMC_FLAG_RXOEIS | \ + ETH_MMC_FLAG_RXLEIS | \ + ETH_MMC_FLAG_RXUGIS | \ + ETH_MMC_FLAG_RXREIS | \ + ETH_MMC_FLAG_RXAEIS | \ + ETH_MMC_FLAG_RXCEIS | \ + ETH_MMC_FLAG_RXMGIS | \ + ETH_MMC_FLAG_RXBGIS)))))) + +#define IS_ETH_MMC_REG(x) \ +( ((x) == ETH_MMC_REG_TXBRGFR) || \ + ((x) == ETH_MMC_REG_TXMUGFR) || \ + ((x) == ETH_MMC_REG_TXDEEFR) || \ + ((x) == ETH_MMC_REG_TXLCEFR) || \ + ((x) == ETH_MMC_REG_TXECEFR) || \ + ((x) == ETH_MMC_REG_TXCAEFR) || \ + ((x) == ETH_MMC_REG_TXUNGFR) || \ + ((x) == ETH_MMC_REG_TXEDEFR) || \ + ((x) == ETH_MMC_REG_RXBRGFR) || \ + ((x) == ETH_MMC_REG_RXMUGFR) || \ + ((x) == ETH_MMC_REG_RXCREFR) || \ + ((x) == ETH_MMC_REG_RXALEFR) || \ + ((x) == ETH_MMC_REG_RXRUEFR) || \ + ((x) == ETH_MMC_REG_RXUNGFR) || \ + ((x) == ETH_MMC_REG_RXLEEFR) || \ + ((x) == ETH_MMC_REG_RXOREFR)) + +#define IS_ETH_PTP_FRAME_DA_FILTER(x) \ +( ((x) == ETH_PTP_FRAME_DA_FILTER_ENABLE) || \ + ((x) == ETH_PTP_FRAME_DA_FILTER_DISABLE)) + +#define IS_ETH_PTP_DATAGRAM_VERSION(x) \ +( ((x) == ETH_PTP_DATAGRAM_VERSION_IEEE1588V1) || \ + ((x) == ETH_PTP_DATAGRAM_VERSION_IEEE1588V2)) + +#define IS_ETH_PTP_SUBSECOND_SCALE(x) \ +( ((x) == ETH_PTP_SUBSECOND_SCALE_HEX) || \ + ((x) == ETH_PTP_SUBSECOND_SCALE_DEC)) + +#define IS_ETH_PTP_DATAGRAM_TYPE(x) \ +( ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_DELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY_PDELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_PDELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_DELAY_PDEALY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_SYNC_DELAY) || \ + ((x) == ETH_PTP_DATAGRAM_TYPE_PDELAY)) + +#define IS_ETH_PTP_FRAME_TYPE(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_PTP_FRAME_TYPE_IPV4FRAME | \ + ETH_PTP_FRAME_TYPE_IPV6FRAME | \ + ETH_PTP_FRAME_TYPE_ETHERNETFRAME | \ + ETH_PTP_FRAME_TYPE_ALL_RECEIVEFRAME)))))) + +#define IS_ETH_PTP_CALIBRATION_MODE(x) \ +( ((x) == ETH_PTP_CALIBRATION_MODE_COARSE) || \ + ((x) == ETH_PTP_CALIBRATION_MODE_FINE)) + +#define IS_ETH_PTP_TIME_UPDATE_SIGN(x) \ +( ((x) == ETH_PTP_TIME_UPDATE_SIGN_MINUS) || \ + ((x) == ETH_PTP_TIME_UPDATE_SIGN_PLUS)) + +#define IS_ETH_PTP_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(ETH_PTP_FLAG_TSERR1 | \ + ETH_PTP_FLAG_TSTAR1 | \ + ETH_PTP_FLAG_TSERR0 | \ + ETH_PTP_FLAG_TSTAR0 | \ + ETH_PTP_FLAG_TSOVF)))))) + +#define IS_ETH_PPS1_COMPLEX_FUNC(ch, mode, freq) \ +( ((ch) == ETH_PPS_TARGET_CH0) || \ + (((mode) == ETH_PPS_OUTPUT_MODE_CONTINUE) && \ + ((freq) == ETH_PPS_OUTPUT_ONE_PULSE))) + +#define IS_ETH_PTP_SUB_SECOND(x) ((x) <= 0x7FFFFFFFUL) + +#define IS_ETH_PPS_TARGET_TIME_FUNC(x) \ +( ((x) == ETH_PPS_TARGET_TIME_FUNC_INT_EVENT) || \ + ((x) == ETH_PPS_TARGET_TIME_FUNC_INT_PPS_EVENT) || \ + ((x) == ETH_PPS_TARGET_TIME_FUNC_PPS_EVENT)) + +#define IS_ETH_PPS_TARGET_CH(x) \ +( ((x) == ETH_PPS_TARGET_CH0) || \ + ((x) == ETH_PPS_TARGET_CH1)) + +#define IS_ETH_PPS_OUTPUT_MODE(x) \ +( ((x) == ETH_PPS_OUTPUT_MODE_CONTINUE) || \ + ((x) == ETH_PPS_OUTPUT_MODE_SINGLE)) + +#define IS_ETH_PPS_OUTPUT_FREQ(x) \ +( ((x) == ETH_PPS_OUTPUT_FREQ_1HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_2HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_4HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_8HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_16HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_32HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_64HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_128HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_256HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_512HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_1024HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_2048HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_4096HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_8192HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_16384HZ) || \ + ((x) == ETH_PPS_OUTPUT_FREQ_32768HZ) || \ + ((x) == ETH_PPS_OUTPUT_ONE_PULSE)) +/** + * @} + */ + +/** + * @} + */ + + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup ETH_Global_Functions ETH Global Functions + * @{ + */ + +/** + * @brief De-Initialize ETH. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: De-Initialize success + * - ErrorTimeout: De-Initialize timeout + */ +en_result_t ETH_DeInit(void) +{ + en_result_t enRet; + + ETH_MAC_DeInit(); + ETH_DMA_DeInit(); + ETH_MACADDR_DeInit(ETH_MAC_ADDRESS0); + ETH_MACADDR_DeInit(ETH_MAC_ADDRESS1); + ETH_MACADDR_DeInit(ETH_MAC_ADDRESS2); + ETH_MACADDR_DeInit(ETH_MAC_ADDRESS3); + ETH_MACADDR_DeInit(ETH_MAC_ADDRESS4); + ETH_MAC_L3L4FilterDeInit(); + ETH_PTP_DeInit(); + ETH_PPS_DeInit(ETH_PPS_TARGET_CH0); + ETH_PPS_DeInit(ETH_PPS_TARGET_CH1); + enRet = ETH_MMC_DeInit(); + if (Ok == enRet) + { + enRet = ETH_DMA_SoftwareReset(); + } + + return enRet; +} + +/** + * @brief Initialize ETH. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] pstcEthInit Pointer to a @ref stc_eth_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: ETH Initialize success + * - ErrorInvalidParameter: pstcEthHandle == NULL or pstcEthInit == NULL or + * PHY Address error + * - ErrorTimeout: Initialize timeout + */ +en_result_t ETH_Init(stc_eth_handle_t *pstcEthHandle, stc_eth_init_t *pstcEthInit) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + uint32_t u32TempReg; + uint32_t u32BusClk; + uint32_t u32PhyTimeout; + uint16_t u16PhyReg = 0U; + + if ((NULL == pstcEthHandle) || (NULL == pstcEthInit)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_AUTO_NEGOTIATION(pstcEthHandle->stcCommInit.u16AutoNegotiation)); + DDL_ASSERT(IS_ETH_MAC_CHECKSUM_MODE(pstcEthHandle->stcCommInit.u32ChecksumMode)); + DDL_ASSERT(IS_ETH_RX_MODE(pstcEthHandle->stcCommInit.u32RxMode)); + DDL_ASSERT(IS_ETH_MAC_MEDIA_INTERFACE(pstcEthHandle->stcCommInit.u32MediaInterface)); + + /* Select MII or RMII Mode*/ + MODIFY_REG32(M4_ETH->MAC_IFCONFR, ETH_MAC_IFCONFR_IFSEL, pstcEthHandle->stcCommInit.u32MediaInterface); + /* ETH software reset */ + if (Ok != ETH_DMA_SoftwareReset()) + { + enRet = ErrorTimeout; + } + else + { + /* Get ETH frequency value */ + u32BusClk = SystemCoreClock / (0x01UL << (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + /* Set SMIC bits depending on PCLK1 clock value */ + /* PCLK1 Clock Range between 20-35 MHz */ + if ((u32BusClk >= 20000000UL) && (u32BusClk < 35000000UL)) + { + u32TempReg = ETH_MAC_SMIADDR_SMIC_1; + } + /* PCLK1 Clock Range between 35-60 MHz */ + else if ((u32BusClk >= 35000000UL) && (u32BusClk < 60000000UL)) + { + u32TempReg = ETH_MAC_SMIADDR_SMIC_1 | ETH_MAC_SMIADDR_SMIC_0; + } + /* PCLK1 Clock Range between 60-100 MHz */ + else if ((u32BusClk >= 60000000UL) && (u32BusClk < 100000000UL)) + { + u32TempReg = 0UL; + } + /* PCLK1 Clock Range between 100-120 MHz */ + else + { + u32TempReg = ETH_MAC_SMIADDR_SMIC_0; + } + /* Configure the ETH MDC Clock Range */ + MODIFY_REG32(M4_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_SMIC, u32TempReg); + + /* PHY initialization and configuration */ + /* Reset the PHY */ + if (Ok != (ETH_PHY_WriteRegister(pstcEthHandle, PHY_BCR, PHY_SOFT_RESET))) + { + enRet = ErrorTimeout; + } + else + { + /* Delay to assure PHY reset */ + DDL_DelayMS(PHY_RESET_DELAY); + + if (ETH_AUTO_NEGOTIATION_DISABLE != pstcEthHandle->stcCommInit.u16AutoNegotiation) + { + u32PhyTimeout = PHY_READ_TIMEOUT * (HCLK_VALUE / 20000UL); + /* Wait for linke status */ + u32Count = ETH_TIMEOUT_LINK_STATUS * (HCLK_VALUE / 20000UL); + while (PHY_LINK_STATUS != (u16PhyReg & PHY_LINK_STATUS)) + { + if (0UL == u32Count) + { + break; + } + if (ErrorTimeout == ETH_PHY_ReadRegister(pstcEthHandle, PHY_BSR, &u16PhyReg)) + { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - u32PhyTimeout) : 0UL; + } + else + { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - (u32PhyTimeout / 150U)) : 0UL; + } + } + + if ((0x0000U == u16PhyReg) || (0xFFFFU == u16PhyReg)) + { + enRet = ErrorInvalidParameter; + } + else if (PHY_LINK_STATUS != (u16PhyReg & PHY_LINK_STATUS)) + { + enRet = ErrorTimeout; + } + else + { + /* Enable Auto-Negotiation */ + if (Ok != (ETH_PHY_WriteRegister(pstcEthHandle, PHY_BCR, PHY_AUTONEGOTIATION))) + { + enRet = ErrorTimeout; + } + else + { + /* Wait until the auto-negotiation will be completed */ + u32Count = ETH_TIMEOUT_AUTONEGO_COMPLETE * (HCLK_VALUE / 20000UL); + while (PHY_AUTONEGO_COMPLETE != (u16PhyReg & PHY_AUTONEGO_COMPLETE)) + { + if (0UL == u32Count) + { + break; + } + if (ErrorTimeout == ETH_PHY_ReadRegister(pstcEthHandle, PHY_BSR, &u16PhyReg)) + { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - u32PhyTimeout) : 0UL; + } + else + { + u32Count = (u32Count > u32PhyTimeout) ? (u32Count - (u32PhyTimeout / 150U)) : 0UL; + } + } + + if (PHY_AUTONEGO_COMPLETE != (u16PhyReg & PHY_AUTONEGO_COMPLETE)) + { + enRet = ErrorTimeout; + } + else + { + /* Read the result of the auto-negotiation */ + /* Configure ETH duplex mode according to the result of automatic negotiation */ + if (0U != (u16PhyReg & (uint16_t)(PHY_100BASE_TX_FD | PHY_10BASE_T_FD))) + { + pstcEthHandle->stcCommInit.u32DuplexMode = ETH_MAC_MODE_FULLDUPLEX; + } + else + { + pstcEthHandle->stcCommInit.u32DuplexMode = ETH_MAC_MODE_HALFDUPLEX; + } + + /* Configure ETH speed according to the result of automatic negotiation */ + if (0U != (u16PhyReg & (uint16_t)(PHY_100BASE_TX_FD | PHY_100BASE_TX_HD))) + { + pstcEthHandle->stcCommInit.u32Speed = ETH_MAC_SPEED_100M; + } + else + { + pstcEthHandle->stcCommInit.u32Speed = ETH_MAC_SPEED_10M; + } + } + } + } + } + /* AutoNegotiation Disable */ + else + { + DDL_ASSERT(IS_ETH_MAC_SPEED(pstcEthHandle->stcCommInit.u32Speed)); + DDL_ASSERT(IS_ETH_MAC_DUPLEX_MODE(pstcEthHandle->stcCommInit.u32DuplexMode)); + + if (Ok != ETH_PHY_WriteRegister(pstcEthHandle, PHY_BCR, + ((uint16_t)(pstcEthHandle->stcCommInit.u32DuplexMode >> 3U) | + (uint16_t)(pstcEthHandle->stcCommInit.u32Speed >> 1U)))) + { + enRet = ErrorTimeout; + } + else + { + /* Delay to assure PHY configuration */ + DDL_DelayMS(PHY_CONFIG_DELAY); + } + } + } + + /* Auto-negotiation failed */ + if (Ok != enRet) + { + pstcEthHandle->stcCommInit.u32DuplexMode = ETH_MAC_MODE_FULLDUPLEX; + pstcEthHandle->stcCommInit.u32Speed = ETH_MAC_SPEED_100M; + } + + /* Config checksum offload */ + if(ETH_MAC_CHECKSUM_MODE_HARDWARE == pstcEthHandle->stcCommInit.u32ChecksumMode) + { + pstcEthInit->stcMacInit.u32ChecksumOffload = ETH_MAC_CHECKSUM_OFFLAOD_ENABLE; + } + else + { + pstcEthInit->stcMacInit.u32ChecksumOffload = ETH_MAC_CHECKSUM_OFFLAOD_DISABLE; + } + + /* Config MAC,DMA,MMC and PTP */ + (void)ETH_MAC_Init(pstcEthHandle, &pstcEthInit->stcMacInit); + (void)ETH_DMA_Init(&pstcEthInit->stcDmaInit); + /* Enable the ETH Rx Interrupt */ + if(ETH_RX_MODE_INTERRUPT == pstcEthHandle->stcCommInit.u32RxMode) + { + ETH_DMA_IntCmd(ETH_DMA_INT_NIE | ETH_DMA_INT_RIE, Enable); + } + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_comm_init_t to default values. + * @param [out] pstcCommInit Pointer to a @ref stc_eth_comm_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcCommInit == NULL + */ +en_result_t ETH_CommStructInit(stc_eth_comm_init_t *pstcCommInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcCommInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcCommInit->u16AutoNegotiation = ETH_AUTO_NEGOTIATION_ENABLE; + pstcCommInit->u16PHYAddress = PHY_ADDRESS; + pstcCommInit->au8MACAddr[0] = ETH_MAC_ADDR0; + pstcCommInit->au8MACAddr[1] = ETH_MAC_ADDR1; + pstcCommInit->au8MACAddr[2] = ETH_MAC_ADDR2; + pstcCommInit->au8MACAddr[3] = ETH_MAC_ADDR3; + pstcCommInit->au8MACAddr[4] = ETH_MAC_ADDR4; + pstcCommInit->au8MACAddr[5] = ETH_MAC_ADDR5; + pstcCommInit->u32MediaInterface = ETH_MAC_MEDIA_INTERFACE_MII; + pstcCommInit->u32Speed = ETH_MAC_SPEED_100M; + pstcCommInit->u32DuplexMode = ETH_MAC_MODE_FULLDUPLEX; + pstcCommInit->u32ChecksumMode = ETH_MAC_CHECKSUM_MODE_HARDWARE; + pstcCommInit->u32RxMode = ETH_RX_MODE_POLLING; + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_init_t to default values. + * @param [out] pstcEthInit Pointer to a @ref stc_eth_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcEthInit == NULL + */ +en_result_t ETH_StructInit(stc_eth_init_t *pstcEthInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcEthInit) + { + enRet = ErrorInvalidParameter; + } + else + { + (void)ETH_MAC_StructInit(&pstcEthInit->stcMacInit); + (void)ETH_DMA_StructInit(&pstcEthInit->stcDmaInit); + } + + return enRet; +} + +/** + * @brief Enable MAC and DMA Transmission/Reception + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Enable success + * - ErrorTimeout: Enable timeout + */ +en_result_t ETH_Start(void) +{ + en_result_t enRet; + + /* Flush Transmit FIFO */ + enRet = ETH_DMA_FlushTransmitFIFO(); + if (Ok == enRet) + { + /* Enable MAC Transmit */ + ETH_MAC_TransmitCmd(Enable); + /* Enable MAC Receive */ + ETH_MAC_ReceiveCmd(Enable); + /* Enable DMA Transmit */ + ETH_DMA_TransmitCmd(Enable); + /* Enable DMA Receive */ + ETH_DMA_ReceiveCmd(Enable); + } + + return enRet; +} + +/** + * @brief Disable MAC and DMA Transmission/Reception + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Disable success + * - ErrorTimeout: Disable timeout + */ +en_result_t ETH_Stop(void) +{ + en_result_t enRet; + + /* Disable DMA Transmit */ + ETH_DMA_TransmitCmd(Disable); + /* Disable DMA Receive */ + ETH_DMA_ReceiveCmd(Disable); + /* Disable MAC Receive */ + ETH_MAC_ReceiveCmd(Disable); + /* Disable MAC Transmit */ + ETH_MAC_TransmitCmd(Disable); + /* Flush Transmit FIFO */ + enRet = ETH_DMA_FlushTransmitFIFO(); + + return enRet; +} + +/******************************************************************************/ +/* PHY Functions */ +/******************************************************************************/ +/** + * @brief Write PHY register + * @note More PHY register could be written depending on the used PHY. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] u16Reg PHY register address + * This parameter can be one of the following values: + * @arg PHY_BCR: PHY Basic Control Register + * @arg other value: The value range from 1 to 31 + * @param [in] u16RegVal PHY register value + * @retval An en_result_t enumeration value: + * - Ok: Write register success + * - ErrorInvalidParameter: pstcEthHandle == NULL + * - ErrorTimeout: Write timeout + */ +en_result_t ETH_PHY_WriteRegister(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t u16RegVal) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + if (NULL == pstcEthHandle) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PHY_ADDRESS(pstcEthHandle->stcCommInit.u16PHYAddress)); + DDL_ASSERT(IS_ETH_PHY_REGISTER(u16Reg)); + + /* Set the MAC_SMIDATR register */ + WRITE_REG32(M4_ETH->MAC_SMIDATR, u16RegVal); + /* Set the MAC_SMIADDR register */ + /* Keep only the MDC Clock Range SMIC[3:0] bits value */ + MODIFY_REG32(M4_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_CLEAR_MASK, + (((uint32_t)(pstcEthHandle->stcCommInit.u16PHYAddress) << ETH_MAC_SMIADDR_SMIA_POS) | + ((uint32_t)u16Reg << ETH_MAC_SMIADDR_SMIR_POS) | ETH_MAC_SMIADDR_SMIW | ETH_MAC_SMIADDR_SMIB)); + /* Check for the Busy flag */ + u32Count = PHY_WRITE_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(M4_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_SMIB)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + } + + return enRet; +} + +/** + * @brief Read PHY register. + * @note More PHY register could be read depending on the used PHY. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] u16Reg PHY register address + * This parameter can be one of the following values: + * @arg PHY_BCR: PHY Basic Control Register + * @arg PHY_BSR: PHY Basic Status Register + * @arg other value: The value range from 2 to 31 + * @param [out] pu16RegVal Pointer to PHY register value + * @retval An en_result_t enumeration value: + * - Ok: Read register success + * - ErrorInvalidParameter: pstcEthHandle == NULL or pu16RegVal == NULL + * - ErrorTimeout: Read timeout + */ +en_result_t ETH_PHY_ReadRegister(stc_eth_handle_t *pstcEthHandle, uint16_t u16Reg, uint16_t *pu16RegVal) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + if ((NULL == pstcEthHandle) || (NULL == pu16RegVal)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PHY_ADDRESS(pstcEthHandle->stcCommInit.u16PHYAddress)); + DDL_ASSERT(IS_ETH_PHY_REGISTER(u16Reg)); + + *pu16RegVal = 0U; + /* Set the MAC_SMIADDR register */ + /* Keep only the MDC Clock Range SMIC[3:0] bits value */ + MODIFY_REG32(M4_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_CLEAR_MASK, + (((uint32_t)(pstcEthHandle->stcCommInit.u16PHYAddress) << ETH_MAC_SMIADDR_SMIA_POS) | + ((uint32_t)u16Reg << ETH_MAC_SMIADDR_SMIR_POS) | ETH_MAC_SMIADDR_SMIB)); + /* Check for the Busy flag */ + u32Count = PHY_READ_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(M4_ETH->MAC_SMIADDR, ETH_MAC_SMIADDR_SMIB)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (ErrorTimeout != enRet) + { + /* Get the MAC_SMIDATR value */ + *pu16RegVal = (uint16_t)(READ_REG32(M4_ETH->MAC_SMIDATR)); + } + } + + return enRet; +} + +/** + * @brief Enabele or disable PHY loopback. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Set loopback success + * - ErrorInvalidParameter: pstcEthHandle == NULL + * - Error: Communication error + */ +en_result_t ETH_PHY_LoopBackCmd(stc_eth_handle_t *pstcEthHandle, en_functional_state_t enNewSta) +{ + en_result_t enRet; + uint16_t u16RegVal; + + if (NULL == pstcEthHandle) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PHY_ADDRESS(pstcEthHandle->stcCommInit.u16PHYAddress)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + enRet = ETH_PHY_ReadRegister(pstcEthHandle, PHY_BCR, &u16RegVal); + if (enRet == Ok) + { + if (Disable != enNewSta) + { + SET_REG16_BIT(u16RegVal, PHY_LOOPBACK); + } + else + { + CLEAR_REG16_BIT(u16RegVal, PHY_LOOPBACK); + } + if (Ok != ETH_PHY_WriteRegister(pstcEthHandle, PHY_BCR, u16RegVal)) + { + enRet = Error; + } + } + } + + return enRet; +} + +/******************************************************************************/ +/* MAC Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MAC. + * @param None + * @retval None + */ +void ETH_MAC_DeInit(void) +{ + WRITE_REG32(M4_ETH->MAC_IFCONFR, 0UL); + WRITE_REG32(M4_ETH->MAC_CONFIGR, 0x00008000UL); + MODIFY_REG32(M4_ETH->MAC_FLTCTLR, ETH_MAC_FLTCTLR_CLEAR_MASK, 0UL); + WRITE_REG32(M4_ETH->MAC_FLOCTLR, 0UL); + WRITE_REG32(M4_ETH->MAC_INTMSKR, 0UL); + WRITE_REG32(M4_ETH->MAC_SMIADDR, 0UL); + WRITE_REG32(M4_ETH->MAC_SMIDATR, 0UL); + WRITE_REG32(M4_ETH->MAC_RTWKFFR, 0UL); + WRITE_REG32(M4_ETH->MAC_PMTCTLR, 0UL); + WRITE_REG32(M4_ETH->MAC_HASHTLR, 0UL); + WRITE_REG32(M4_ETH->MAC_HASHTHR, 0UL); + WRITE_REG32(M4_ETH->MAC_VTACTLR, 0UL); + WRITE_REG32(M4_ETH->MAC_VTAFLTR, 0UL); + WRITE_REG32(M4_ETH->MAC_VLAHTBR, 0UL); +} + +/** + * @brief Initialize MAC. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] pstcMacInit Pointer to a @ref stc_eth_mac_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: MAC Initialize success + * - ErrorInvalidParameter: pstcEthHandle == NULL or pstcMacInit == NULL + */ +en_result_t ETH_MAC_Init(stc_eth_handle_t *pstcEthHandle, const stc_eth_mac_init_t *pstcMacInit) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcEthHandle) || (NULL == pstcMacInit)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_TX_CLK_POLARITY(pstcMacInit->u32TxClkPolarity)); + DDL_ASSERT(IS_ETH_MAC_RX_REF_CLK_POLARITY(pstcMacInit->u32RxRefClkPolarity)); + DDL_ASSERT(IS_ETH_MAC_SA_MODE(pstcMacInit->u32SAInsertMode)); + DDL_ASSERT(IS_ETH_MAC_TYPEFRAME_STRIP_FCS(pstcMacInit->u32TypeFrameStripFCS)); + DDL_ASSERT(IS_ETH_MAC_WATCHDOG(pstcMacInit->u32Watchdog)); + DDL_ASSERT(IS_ETH_MAC_JABBER(pstcMacInit->u32Jabber)); + DDL_ASSERT(IS_ETH_MAC_INTERFRAME_GAP(pstcMacInit->u32InterFrameGap)); + DDL_ASSERT(IS_ETH_MAC_CARRIER_SENCE(pstcMacInit->u32CarrierSense)); + DDL_ASSERT(IS_ETH_MAC_SPEED(pstcEthHandle->stcCommInit.u32Speed)); + DDL_ASSERT(IS_ETH_MAC_RECEIVE_OWN(pstcMacInit->u32ReceiveOwn)); + DDL_ASSERT(IS_ETH_MAC_DUPLEX_MODE(pstcEthHandle->stcCommInit.u32DuplexMode)); + DDL_ASSERT(IS_ETH_MAC_CHECKSUM_OFFLAOD(pstcMacInit->u32ChecksumOffload)); + DDL_ASSERT(IS_ETH_MAC_RETRY_TRANSMIT(pstcMacInit->u32RetryTransmit)); + DDL_ASSERT(IS_ETH_MAC_AUTO_STRIP_PAD_FCS(pstcMacInit->u32AutoStripPadFCS)); + DDL_ASSERT(IS_ETH_MAC_BACKOFF_LIMIT(pstcMacInit->u32BackOffLimit)); + DDL_ASSERT(IS_ETH_MAC_DEFFERRAL_CHECK(pstcMacInit->u32DeferralCheck)); + DDL_ASSERT(IS_ETH_MAC_ZERO_QUANTA_PAUSE(pstcMacInit->u32ZeroQuantaPause)); + DDL_ASSERT(IS_ETH_MAC_PAUSE_LOWTHRESHOLD(pstcMacInit->u32PauseLowThreshold)); + DDL_ASSERT(IS_ETH_MAC_UNICAST_PAUSEFRAME_DETECT(pstcMacInit->u32UnicastPauseFrameDetect)); + DDL_ASSERT(IS_ETH_MAC_RECEIVE_FLOWCONTROL(pstcMacInit->u32ReceiveFlowControl)); + DDL_ASSERT(IS_ETH_MAC_TRANSMIT_FLOWCONTROL(pstcMacInit->u32TransmitFlowControl)); + DDL_ASSERT(IS_ETH_MAC_RECEIVE_All(pstcMacInit->u32ReceiveAll)); + DDL_ASSERT(IS_ETH_MAC_DROP_NOT_TCPUDP(pstcMacInit->u32DropNotTcpUdp)); + DDL_ASSERT(IS_ETH_MAC_VLAN_TAG_FILTER(pstcMacInit->u32VlanTagFilter)); + DDL_ASSERT(IS_ETH_MAC_SOURCE_ADDR_FILTER(pstcMacInit->u32SAFilter)); + DDL_ASSERT(IS_ETH_MAC_PASS_CTRLFRAME(pstcMacInit->u32PassControlFrame)); + DDL_ASSERT(IS_ETH_MAC_BROADCASTFRAME_RECEPTION(pstcMacInit->u32BroadcastFrameReception)); + DDL_ASSERT(IS_ETH_MAC_DESTINATION_ADDR_FILTER(pstcMacInit->u32DAFilter)); + DDL_ASSERT(IS_ETH_MAC_MULTICASTFRAME_FILTER(pstcMacInit->u32MulticastFrameFilter)); + DDL_ASSERT(IS_ETH_MAC_UNICASTFRAME_FILTER(pstcMacInit->u32UnicastFrameFilter)); + DDL_ASSERT(IS_ETH_MAC_PROMISCUOUS_MODE(pstcMacInit->u32PromiscuousMode)); + DDL_ASSERT(IS_ETH_MAC_TXVLAN_MODE(pstcMacInit->u32TxVlanInsertMode)); + DDL_ASSERT(IS_ETH_MAC_RXVLAN_FILTER(pstcMacInit->u32RxVlanFilter)); + DDL_ASSERT(IS_ETH_MAC_RXVLAN_COMPARISON(pstcMacInit->u32RxVlanComparison)); + + /* Set MAC_IFCONFR register */ + MODIFY_REG32(M4_ETH->MAC_IFCONFR, ETH_MAC_IFCONFR_CLEAR_MASK, + (pstcMacInit->u32TxClkPolarity | pstcMacInit->u32RxRefClkPolarity)); + /* Set MAC_CONFIGR register */ + MODIFY_REG32(M4_ETH->MAC_CONFIGR, ETH_MAC_CONFIGR_CLEAR_MASK, + (pstcMacInit->u32SAInsertMode | pstcMacInit->u32TypeFrameStripFCS | + pstcMacInit->u32Watchdog | pstcMacInit->u32Jabber | + pstcMacInit->u32InterFrameGap | pstcMacInit->u32CarrierSense | + pstcEthHandle->stcCommInit.u32Speed | pstcMacInit->u32ReceiveOwn | + pstcMacInit->u32DeferralCheck | pstcEthHandle->stcCommInit.u32DuplexMode | + pstcMacInit->u32ChecksumOffload | pstcMacInit->u32RetryTransmit | + pstcMacInit->u32AutoStripPadFCS | pstcMacInit->u32BackOffLimit)); + /* Set MAC_FLOCTLR register */ + MODIFY_REG32(M4_ETH->MAC_FLOCTLR, ETH_MAC_FLOCTLR_CLEAR_MASK, + ((((uint32_t)pstcMacInit->u16PauseTime) << 16U) | pstcMacInit->u32ZeroQuantaPause | + pstcMacInit->u32PauseLowThreshold | pstcMacInit->u32UnicastPauseFrameDetect | + pstcMacInit->u32ReceiveFlowControl | pstcMacInit->u32TransmitFlowControl)); + /* Set MAC_FLTCTLR register */ + MODIFY_REG32(M4_ETH->MAC_FLTCTLR, ETH_MAC_FLTCTLR_CLEAR_MASK, + (pstcMacInit->u32ReceiveAll | pstcMacInit->u32DropNotTcpUdp | + pstcMacInit->u32PromiscuousMode | pstcMacInit->u32VlanTagFilter | + pstcMacInit->u32SAFilter | pstcMacInit->u32PassControlFrame | + pstcMacInit->u32BroadcastFrameReception | pstcMacInit->u32DAFilter | + pstcMacInit->u32MulticastFrameFilter | pstcMacInit->u32UnicastFrameFilter)); + /* Set Hash table register */ + WRITE_REG32(M4_ETH->MAC_HASHTLR, pstcMacInit->u32HashTableLow); + WRITE_REG32(M4_ETH->MAC_HASHTHR, pstcMacInit->u32HashTableHigh); + /* Set Tx VLAN register */ + WRITE_REG32(M4_ETH->MAC_VTACTLR, (pstcMacInit->u32TxVlanInsertMode | pstcMacInit->u16TxVlanTag)); + /* Set Rx VLAN register */ + WRITE_REG32(M4_ETH->MAC_VTAFLTR, (pstcMacInit->u32RxVlanFilter | + pstcMacInit->u32RxVlanComparison | pstcMacInit->u16RxVlanTag)); + WRITE_REG32(M4_ETH->MAC_VLAHTBR, pstcMacInit->u16RxVlanHashTable); + /* Config MAC address in ETH MAC0 */ + (void)ETH_MACADDR_SetAddress(ETH_MAC_ADDRESS0, pstcEthHandle->stcCommInit.au8MACAddr); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_mac_init_t to default values. + * @param [out] pstcMacInit Pointer to a @ref stc_eth_mac_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcMacInit == NULL + */ +en_result_t ETH_MAC_StructInit(stc_eth_mac_init_t *pstcMacInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcMacInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcMacInit->u32TxClkPolarity = ETH_MAC_TX_CLK_POLARITY_KEEP; + pstcMacInit->u32RxRefClkPolarity = ETH_MAC_RX_REF_CLK_POLARITY_KEEP; + pstcMacInit->u32SAInsertMode = ETH_MAC_SA_MODE_BY_DMATXDESC; + pstcMacInit->u32TypeFrameStripFCS = ETH_MAC_TYPEFRAME_STRIP_FCS_DISABLE; + pstcMacInit->u32Watchdog = ETH_MAC_WATCHDOG_ENABLE; + pstcMacInit->u32Jabber = ETH_MAC_JABBER_ENABLE; + pstcMacInit->u32InterFrameGap = ETH_MAC_INTERFRAME_GAP_96BIT; + pstcMacInit->u32CarrierSense = ETH_MAC_CARRIER_SENCE_ENABLE; + pstcMacInit->u32ReceiveOwn = ETH_MAC_RECEIVE_OWN_ENABLE; + pstcMacInit->u32ChecksumOffload = ETH_MAC_CHECKSUM_OFFLAOD_DISABLE; + pstcMacInit->u32RetryTransmit = ETH_MAC_RETRY_TRANSMIT_DISABLE; + pstcMacInit->u32AutoStripPadFCS = ETH_MAC_AUTO_STRIP_PAD_FCS_DISABLE; + pstcMacInit->u32BackOffLimit = ETH_MAC_BACKOFF_LIMIT_10; + pstcMacInit->u32DeferralCheck = ETH_MAC_DEFFERRAL_CHECK_DISABLE; + pstcMacInit->u16PauseTime = 0U; + pstcMacInit->u32ZeroQuantaPause = ETH_MAC_ZERO_QUANTA_PAUSE_DISABLE; + pstcMacInit->u32PauseLowThreshold = ETH_MAC_PAUSE_LOWTHRESHOLD_MINUS4; + pstcMacInit->u32UnicastPauseFrameDetect = ETH_MAC_UNICAST_PAUSEFRAME_DETECT_DISABLE; + pstcMacInit->u32ReceiveFlowControl = ETH_MAC_RECEIVE_FLOWCONTROL_DISABLE; + pstcMacInit->u32TransmitFlowControl = ETH_MAC_TRANSMIT_FLOWCONTROL_DISABLE; + pstcMacInit->u32ReceiveAll = ETH_MAC_RECEIVE_All_DISABLE; + pstcMacInit->u32DropNotTcpUdp = ETH_MAC_DROP_NOT_TCPUDP_DISABLE; + + pstcMacInit->u32VlanTagFilter = ETH_MAC_VLAN_TAG_FILTER_DISABLE; + pstcMacInit->u32SAFilter = ETH_MAC_SOURCE_ADDR_FILTER_DISABLE; + pstcMacInit->u32PassControlFrame = ETH_MAC_PASS_CTRLFRAME_FORWARD_NOTPAUSE_ALL; + pstcMacInit->u32BroadcastFrameReception = ETH_MAC_BROADCASTFRAME_RECEPTION_ENABLE; + pstcMacInit->u32DAFilter = ETH_MAC_DESTINATION_ADDR_FILTER_NORMAL; + pstcMacInit->u32MulticastFrameFilter = ETH_MAC_MULTICASTFRAME_FILTER_PERFECT; + pstcMacInit->u32UnicastFrameFilter = ETH_MAC_UNICASTFRAME_FILTER_PERFECT; + pstcMacInit->u32PromiscuousMode = ETH_MAC_PROMISCUOUS_MODE_DISABLE; + pstcMacInit->u32HashTableHigh = 0UL; + pstcMacInit->u32HashTableLow = 0UL; + pstcMacInit->u32TxVlanInsertMode = ETH_MAC_TXVLAN_MODE_BYPASS; + pstcMacInit->u16TxVlanTag = 0U; + pstcMacInit->u32RxVlanFilter = ETH_MAC_RXVLAN_FILTER_NORMAL; + pstcMacInit->u32RxVlanComparison = ETH_MAC_RXVLAN_COMPARISON_16BIT; + pstcMacInit->u16RxVlanTag = 0U; + pstcMacInit->u16RxVlanHashTable = 0U; + } + + return enRet; +} + +/** + * @brief Set MAC duplex mode and speed. + * @param [in] u32DuplexMode MAC duplex mode + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_MODE_HALFDUPLEX: Half duplex mode + * @arg ETH_MAC_MODE_FULLDUPLEX: Full duplex mode + * @param [in] u32Speed MAC speed + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_SPEED_10M: 10Mbps + * @arg ETH_MAC_SPEED_100M: 100Mbps + * @retval None + */ +void ETH_MAC_SetDuplexSpeed(uint32_t u32DuplexMode, uint32_t u32Speed) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_DUPLEX_MODE(u32DuplexMode)); + DDL_ASSERT(IS_ETH_MAC_SPEED(u32Speed)); + + MODIFY_REG32(M4_ETH->MAC_CONFIGR, (ETH_MAC_CONFIGR_FES | ETH_MAC_CONFIGR_DM), + (u32DuplexMode | u32Speed)); +} + +/** + * @brief Set MAC hash table. + * @param [in] u32HashHigh Hash table high value. + * @param [in] u32HashLow Hash table low value. + * @retval None + */ +void ETH_MAC_SetHashTable(uint32_t u32HashHigh, uint32_t u32HashLow) +{ + WRITE_REG32(M4_ETH->MAC_HASHTLR, u32HashLow); + WRITE_REG32(M4_ETH->MAC_HASHTHR, u32HashHigh); +} + +/** + * @brief Set MAC Tx VLAN tag value. + * @param [in] u16TxTag The tag value of Tx VLAN. + * @retval None + */ +void ETH_MAC_SetTxVlanTagVal(uint16_t u16TxTag) +{ + MODIFY_REG32(M4_ETH->MAC_VTACTLR, ETH_MAC_VTACTLR_VLANV, u16TxTag); +} + +/** + * @brief Set MAC Rx VLAN tag value. + * @param [in] u16RxTag The tag value of Rx VLAN. + * @retval None + */ +void ETH_MAC_SetRxVlanTagVal(uint16_t u16RxTag) +{ + MODIFY_REG32(M4_ETH->MAC_VTAFLTR, ETH_MAC_VTAFLTR_VLFLT, u16RxTag); +} + +/** + * @brief Set MAC Rx VLAN hash table. + * @param [in] u16HashVal The value of Rx VLAN hash table. + * @retval None + */ +void ETH_MAC_SetRxVlanHashTable(uint16_t u16HashVal) +{ + WRITE_REG32(M4_ETH->MAC_VLAHTBR, u16HashVal); +} + +/** + * @brief Enable or disable MAC loopback. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MAC_LoopBackCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MAC_CONFIGR_b.LM, enNewSta); +} + +/** + * @brief Enable or disable MAC Back Pressure. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MAC_BackPressureCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MAC_FLOCTLR_b.FCA_BPA, enNewSta); +} + +/** + * @brief Enable or disable MAC Transmit. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MAC_TransmitCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MAC_CONFIGR_b.TE, enNewSta); +} + +/** + * @brief Enable or disable MAC Receive. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MAC_ReceiveCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MAC_CONFIGR_b.RE, enNewSta); +} + +/** + * @brief Enable or disable MAC interrupt. + * @param [in] u32IntSrc MAC interrupt source type + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_INT_TSPIM: Time stamp trigger interrupt (on MAC) + * @arg ETH_MAC_INT_PMTIM: PMT interrupt (on MAC) + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MAC_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_INTERRUPT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + CLEAR_REG32_BIT(M4_ETH->MAC_INTMSKR, u32IntSrc); + } + else + { + SET_REG32_BIT(M4_ETH->MAC_INTMSKR, u32IntSrc); + } +} + +/** + * @brief Get MAC interrupt status. + * @param [in] u32Flag MAC interrupt flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_MAC_INT_FLAG_TSPIS: Time stamp trigger flag (on MAC) + * @arg ETH_MAC_INT_FLAG_MMCTXIS: MMC transmit flag + * @arg ETH_MAC_INT_FLAG_MMCRXIS: MMC receive flag + * @arg ETH_MAC_INT_FLAG_MMCIS: MMC flag (on MAC) + * @arg ETH_MAC_INT_FLAG_PMTIS: PMT flag (on MAC) + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_MAC_GetIntStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_INTERRUPT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->MAC_INTSTSR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* MAC Address Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0: MAC address 0 + * @arg ETH_MAC_ADDRESS1: MAC address 1 + * @arg ETH_MAC_ADDRESS2: MAC address 2 + * @arg ETH_MAC_ADDRESS3: MAC address 3 + * @arg ETH_MAC_ADDRESS4: MAC address 4 + * @retval None + */ +void ETH_MACADDR_DeInit(uint32_t u32Index) +{ + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32MacHigh = 0x0000FFFFUL; + + DDL_ASSERT(IS_ETH_MAC_ADDRESS_NORMAL_INDEX(u32Index)); + + MACADHR = (__IO uint32_t *)ETH_MAC_MACADHRx(u32Index); + MACADLR = (__IO uint32_t *)ETH_MAC_MACADLRx(u32Index); + if (ETH_MAC_ADDRESS0 == u32Index) + { + u32MacHigh |= 0x80000000UL; + } + WRITE_REG32(*MACADHR, u32MacHigh); + WRITE_REG32(*MACADLR, 0xFFFFFFFFUL); +} + +/** + * @brief Initialize MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0: MAC address 0 + * @arg ETH_MAC_ADDRESS1: MAC address 1 + * @arg ETH_MAC_ADDRESS2: MAC address 2 + * @arg ETH_MAC_ADDRESS3: MAC address 3 + * @arg ETH_MAC_ADDRESS4: MAC address 4 + * @param [in] pstcMacAddrInit Pointer to a @ref stc_eth_mac_addr_config_t structure + * @retval An en_result_t enumeration value: + * - Ok: MAC Address Initialize success + * - ErrorInvalidParameter: pstcMacAddrInit == NULL + */ +en_result_t ETH_MACADDR_Init(uint32_t u32Index, const stc_eth_mac_addr_config_t *pstcMacAddrInit) +{ + en_result_t enRet = Ok; + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32TempReg; + uint32_t *pu32AddrLow; + + if (NULL == pstcMacAddrInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDRESS_NORMAL_INDEX(u32Index)); + DDL_ASSERT(IS_ETH_MAC_ADDRESS_FILTER(pstcMacAddrInit->u32MacAddrFilter)); + DDL_ASSERT(IS_ETH_MAC_ADDRESS_MASK(pstcMacAddrInit->u32MacAddrMask)); + + MACADHR = (__IO uint32_t *)ETH_MAC_MACADHRx(u32Index); + MACADLR = (__IO uint32_t *)ETH_MAC_MACADLRx(u32Index); + /* Set MAC address high register */ + u32TempReg = ((uint32_t)pstcMacAddrInit->au8MACAddr[5] << 8U) | (uint32_t)pstcMacAddrInit->au8MACAddr[4]; + if (ETH_MAC_ADDRESS0 != u32Index) + { + u32TempReg |= pstcMacAddrInit->u32MacAddrFilter | pstcMacAddrInit->u32MacAddrMask; + } + WRITE_REG32(*MACADHR, u32TempReg); + /* Set MAC address low register */ + pu32AddrLow = (uint32_t *)((uint32_t)&(pstcMacAddrInit->au8MACAddr[0])); + WRITE_REG32(*MACADLR, *pu32AddrLow); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_mac_addr_config_t to default values. + * @param [out] pstcMacAddrInit Pointer to a @ref stc_eth_mac_addr_config_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcMacAddrInit == NULL + */ +en_result_t ETH_MACADDR_StructInit(stc_eth_mac_addr_config_t *pstcMacAddrInit) +{ + en_result_t enRet = Ok; + uint8_t i; + + if (NULL == pstcMacAddrInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcMacAddrInit->u32MacAddrFilter = ETH_MAC_ADDRESS_FILTER_DISABLE; + pstcMacAddrInit->u32MacAddrMask = ETH_MAC_ADDRESS_MASK_DISABLE; + for (i=0U; iau8MACAddr[i] = 0x00U; + } + } + + return enRet; +} + +/** + * @brief Set MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0: MAC address 0 + * @arg ETH_MAC_ADDRESS1: MAC address 1 + * @arg ETH_MAC_ADDRESS2: MAC address 2 + * @arg ETH_MAC_ADDRESS3: MAC address 3 + * @arg ETH_MAC_ADDRESS4: MAC address 4 + * @param [in] au8Addr Pointer to MAC address buffer(6 bytes). + * @retval An en_result_t enumeration value: + * - Ok: Set address success + * - ErrorInvalidParameter: au8Addr == NULL + */ +en_result_t ETH_MACADDR_SetAddress(uint32_t u32Index, uint8_t au8Addr[]) +{ + en_result_t enRet = Ok; + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32TempReg; + uint32_t *pu32AddrLow; + + if (NULL == au8Addr) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDRESS_NORMAL_INDEX(u32Index)); + + MACADHR = (__IO uint32_t *)ETH_MAC_MACADHRx(u32Index); + MACADLR = (__IO uint32_t *)ETH_MAC_MACADLRx(u32Index); + /* Set MAC address high register */ + u32TempReg = ((uint32_t)au8Addr[5] << 8U) | (uint32_t)au8Addr[4]; + WRITE_REG32(*MACADHR, u32TempReg); + /* Set MAC address low register */ + pu32AddrLow = (uint32_t *)((uint32_t)&(au8Addr[0])); + WRITE_REG32(*MACADLR, *pu32AddrLow); + } + + return enRet; +} + +/** + * @brief Get MAC Address. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS0: MAC address 0 + * @arg ETH_MAC_ADDRESS1: MAC address 1 + * @arg ETH_MAC_ADDRESS2: MAC address 2 + * @arg ETH_MAC_ADDRESS3: MAC address 3 + * @arg ETH_MAC_ADDRESS4: MAC address 4 + * @param [out] au8Addr Pointer to MAC address buffer(6 bytes). + * @retval An en_result_t enumeration value: + * - Ok: Set address success + * - ErrorInvalidParameter: au8Addr == NULL + */ +en_result_t ETH_MACADDR_GetAddress(uint32_t u32Index, uint8_t au8Addr[]) +{ + en_result_t enRet = Ok; + __IO uint32_t *MACADHR; + __IO uint32_t *MACADLR; + uint32_t u32TempReg; + uint32_t *pu32AddrLow; + + if (NULL == au8Addr) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDRESS_NORMAL_INDEX(u32Index)); + + MACADHR = (__IO uint32_t *)ETH_MAC_MACADHRx(u32Index); + MACADLR = (__IO uint32_t *)ETH_MAC_MACADLRx(u32Index); + /* Get MAC address high */ + u32TempReg = READ_REG32(*MACADHR); + au8Addr[5] = (uint8_t)((u32TempReg >> 8U) & 0x000000FFUL); + au8Addr[4] = (uint8_t)(u32TempReg & 0x000000FFUL); + /* Get MAC address low */ + pu32AddrLow = (uint32_t *)((uint32_t)&(au8Addr[0])); + *pu32AddrLow = READ_REG32(*MACADLR); + } + + return enRet; +} + +/** + * @brief Set MAC Address filter mode. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1: MAC address 1 + * @arg ETH_MAC_ADDRESS2: MAC address 2 + * @arg ETH_MAC_ADDRESS3: MAC address 3 + * @arg ETH_MAC_ADDRESS4: MAC address 4 + * @param [in] u32Mode MAC address filter mode. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS_FILTER_DISABLE: Disable perfect filter with MAC address. + * @arg ETH_MAC_ADDRESS_FILTER_PERFECT_DA: Filter the DA address of the received frame with MAC address. + * @arg ETH_MAC_ADDRESS_FILTER_PERFECT_SA: Filter the SA address of the received frame with MAC address. + * @retval None + */ +void ETH_MACADDR_SetFilterMode(uint32_t u32Index, uint32_t u32Mode) +{ + __IO uint32_t *MACADHR; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDRESS_SPECIAL_INDEX(u32Index)); + DDL_ASSERT(IS_ETH_MAC_ADDRESS_FILTER(u32Mode)); + + MACADHR = (__IO uint32_t *)ETH_MAC_MACADHRx(u32Index); + MODIFY_REG32(*MACADHR, (ETH_MAC_MACADHR1_SA1 | ETH_MAC_MACADHR1_AE1), u32Mode); +} + +/** + * @brief Set MAC Address Transmit priority ratio. + * @param [in] u32Index MAC address index. + * This parameter can be one of the following values: + * @arg ETH_MAC_ADDRESS1: MAC address 1 + * @arg ETH_MAC_ADDRESS2: MAC address 2 + * @arg ETH_MAC_ADDRESS3: MAC address 3 + * @arg ETH_MAC_ADDRESS4: MAC address 4 + * @param [in] u32Mask MAC address filter mask. + * This parameter can be one of the following values or any combination + * of BYTE1 through BYTE6: + * @arg ETH_MAC_ADDRESS_MASK_DISABLE: Disable MAC Address Mask + * @arg ETH_MAC_ADDRESS_MASK_BYTE6: Mask MAC Address high reg bits [15:8] + * @arg ETH_MAC_ADDRESS_MASK_BYTE5: Mask MAC Address high reg bits [7:0] + * @arg ETH_MAC_ADDRESS_MASK_BYTE4: Mask MAC Address low reg bits [31:24] + * @arg ETH_MAC_ADDRESS_MASK_BYTE3: Mask MAC Address low reg bits [23:16] + * @arg ETH_MAC_ADDRESS_MASK_BYTE2: Mask MAC Address low reg bits [15:8] + * @arg ETH_MAC_ADDRESS_MASK_BYTE1: Mask MAC Address low reg bits [7:0] + * @arg ETH_MAC_ADDRESS_MASK_ALL: Mask MAC Address low reg bits [31:0] and low high bits [15:0] + * @retval None + */ +void ETH_MACADDR_SetFilterMask(uint32_t u32Index, uint32_t u32Mask) +{ + __IO uint32_t *MACADHR; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_ADDRESS_SPECIAL_INDEX(u32Index)); + DDL_ASSERT(IS_ETH_MAC_ADDRESS_MASK(u32Mask)); + + MACADHR = (__IO uint32_t *)ETH_MAC_MACADHRx(u32Index); + MODIFY_REG32(*MACADHR, ETH_MAC_MACADHR1_MBC1, u32Mask); +} + +/******************************************************************************/ +/* MAC L3L4 Filter Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MAC L3L4 Filter. + * @param None + * @retval None + */ +void ETH_MAC_L3L4FilterDeInit(void) +{ + WRITE_REG32(bM4_ETH->MAC_FLTCTLR_b.IPFE, Disable); + WRITE_REG32(M4_ETH->MAC_L34CTLR, 0UL); + WRITE_REG32(M4_ETH->MAC_L4PORTR, 0UL); + WRITE_REG32(M4_ETH->MAC_L3ADDRR0, 0UL); + WRITE_REG32(M4_ETH->MAC_L3ADDRR1, 0UL); + WRITE_REG32(M4_ETH->MAC_L3ADDRR2, 0UL); + WRITE_REG32(M4_ETH->MAC_L3ADDRR3, 0UL); +} + +/** + * @brief Initialize MAC L3L4 Filter. + * @param [in] pstcL3L4FilterInit Pointer to a @ref stc_eth_l3l4_filter_config_t structure + * @retval An en_result_t enumeration value: + * - Ok: MAC L3L4 Filter Initialize success + * - ErrorInvalidParameter: pstcL3L4FilterInit == NULL + */ +en_result_t ETH_MAC_L3L4FilterInit(const stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcL3L4FilterInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_L4_DESTPORT_FILTER(pstcL3L4FilterInit->u32L4DestPortFilter)); + DDL_ASSERT(IS_ETH_MAC_L4_SOURCEPORT_FILTER(pstcL3L4FilterInit->u32L4SourcePortFilter)); + DDL_ASSERT(IS_ETH_MAC_L4_PORT_FILTER_PROTOCOL(pstcL3L4FilterInit->u32L4PortFilterProtocol)); + DDL_ASSERT(IS_ETH_MAC_L3_DA_FILTER_MASK(pstcL3L4FilterInit->u32L3Ipv4DAFilterMask)); + DDL_ASSERT(IS_ETH_MAC_L3_SA_FILTER_MASK(pstcL3L4FilterInit->u32L3Ipv4SAFilterMask)); + DDL_ASSERT(IS_ETH_MAC_L3_DA_SA_FILTER_MASK(pstcL3L4FilterInit->u32L3Ipv6AddrFilterMask)); + DDL_ASSERT(IS_ETH_MAC_L3_DA_FILTER(pstcL3L4FilterInit->u32L3DAFilter)); + DDL_ASSERT(IS_ETH_MAC_L3_SA_FILTER(pstcL3L4FilterInit->u32L3SAFilter)); + DDL_ASSERT(IS_ETH_MAC_L3_ADDR_FILTER_PROTOCOL(pstcL3L4FilterInit->u32L3AddrFilterProtocol)); + + /* Set L3/L4 control register */ + if (ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4 != pstcL3L4FilterInit->u32L3AddrFilterProtocol) + { + WRITE_REG32(M4_ETH->MAC_L34CTLR, + (pstcL3L4FilterInit->u32L4DestPortFilter | pstcL3L4FilterInit->u32L4SourcePortFilter | + pstcL3L4FilterInit->u32L4PortFilterProtocol | pstcL3L4FilterInit->u32L3Ipv6AddrFilterMask | + pstcL3L4FilterInit->u32L3DAFilter | pstcL3L4FilterInit->u32L3SAFilter | + pstcL3L4FilterInit->u32L3AddrFilterProtocol)); + WRITE_REG32(M4_ETH->MAC_L3ADDRR0, pstcL3L4FilterInit->au32L3Ipv6AddrFilterValue[0]); + WRITE_REG32(M4_ETH->MAC_L3ADDRR1, pstcL3L4FilterInit->au32L3Ipv6AddrFilterValue[1]); + WRITE_REG32(M4_ETH->MAC_L3ADDRR2, pstcL3L4FilterInit->au32L3Ipv6AddrFilterValue[2]); + WRITE_REG32(M4_ETH->MAC_L3ADDRR3, pstcL3L4FilterInit->au32L3Ipv6AddrFilterValue[3]); + } + /* IPv4 protocol*/ + else + { + WRITE_REG32(M4_ETH->MAC_L34CTLR, + (pstcL3L4FilterInit->u32L4DestPortFilter | pstcL3L4FilterInit->u32L4SourcePortFilter | + pstcL3L4FilterInit->u32L4PortFilterProtocol | pstcL3L4FilterInit->u32L3Ipv4DAFilterMask | + pstcL3L4FilterInit->u32L3Ipv4SAFilterMask | pstcL3L4FilterInit->u32L3DAFilter | + pstcL3L4FilterInit->u32L3SAFilter | pstcL3L4FilterInit->u32L3AddrFilterProtocol)); + WRITE_REG32(M4_ETH->MAC_L3ADDRR0, pstcL3L4FilterInit->u32L3Ipv4SAFilterValue); + WRITE_REG32(M4_ETH->MAC_L3ADDRR1, pstcL3L4FilterInit->u32L3Ipv4DAFilterValue); + } + WRITE_REG32(M4_ETH->MAC_L4PORTR, ((((uint32_t)pstcL3L4FilterInit->u16L4DestProtFilterValue) << ETH_MAC_L4PORTR_L4DPVAL_POS) | + pstcL3L4FilterInit->u16L4SourceProtFilterValue)); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_l3l4_filter_config_t to default values. + * @param [out] pstcL3L4FilterInit Pointer to a @ref stc_eth_l3l4_filter_config_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcL3L4FilterInit == NULL + */ +en_result_t ETH_MAC_L3L4FilterStructInit(stc_eth_l3l4_filter_config_t *pstcL3L4FilterInit) +{ + en_result_t enRet = Ok; + uint8_t i; + + if (NULL == pstcL3L4FilterInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcL3L4FilterInit->u32L4DestPortFilter = ETH_MAC_L4_DESTPORT_FILTER_DISABLE; + pstcL3L4FilterInit->u32L4SourcePortFilter = ETH_MAC_L4_SOURCEPORT_FILTER_DISABLE; + pstcL3L4FilterInit->u32L4PortFilterProtocol = ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP; + pstcL3L4FilterInit->u32L3Ipv4DAFilterMask = ETH_MAC_L3_DA_FILTER_MASK_NONE; + pstcL3L4FilterInit->u32L3Ipv4SAFilterMask = ETH_MAC_L3_SA_FILTER_MASK_NONE; + pstcL3L4FilterInit->u32L3Ipv6AddrFilterMask = ETH_MAC_L3_DA_SA_FILTER_MASK_NONE; + pstcL3L4FilterInit->u32L3DAFilter = ETH_MAC_L3_DA_FILTER_DISABLE; + pstcL3L4FilterInit->u32L3SAFilter = ETH_MAC_L3_SA_FILTER_DISABLE; + pstcL3L4FilterInit->u32L3AddrFilterProtocol = ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4; + pstcL3L4FilterInit->u16L4DestProtFilterValue = 0U; + pstcL3L4FilterInit->u16L4SourceProtFilterValue = 0U; + pstcL3L4FilterInit->u32L3Ipv4DAFilterValue = 0UL; + pstcL3L4FilterInit->u32L3Ipv4SAFilterValue = 0UL; + for (i=0U; i<4U; i++) + { + pstcL3L4FilterInit->au32L3Ipv6AddrFilterValue[i] = 0UL; + } + } + + return enRet; +} + +/** + * @brief Enable or disable MAC L3L4 Filter function. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MAC_L3L4FilterCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MAC_FLTCTLR_b.IPFE, enNewSta); +} + +/** + * @brief Set L4 port filter protocol. + * @param [in] u32PortProtocol MAC L4 port filter protocol. + * This parameter can be one of the following values: + * @arg ETH_MAC_L4_PORT_FILTER_PROTOCOL_TCP: Port filter for TCP frame + * @arg ETH_MAC_L4_PORT_FILTER_PROTOCOL_UDP: Port filter for UDP frame + * @retval None + */ +void ETH_MAC_SetPortFilterProtocol(uint32_t u32PortProtocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_L4_PORT_FILTER_PROTOCOL(u32PortProtocol)); + + WRITE_REG32(bM4_ETH->MAC_L34CTLR_b.L4PEN, (u32PortProtocol >> ETH_MAC_L34CTLR_L4PEN_POS)); +} + +/** + * @brief Set L4 Destination port filter value. + * @param [in] u16Port The value of Destination port. + * @retval None + */ +void ETH_MAC_SetDestPortFilterVal(uint16_t u16Port) +{ + MODIFY_REG32(M4_ETH->MAC_L4PORTR, ETH_MAC_L4PORTR_L4DPVAL, ((uint32_t)u16Port << 16U)); +} + +/** + * @brief Set L4 Source port filter value. + * @param [in] u16Port The value of Source port. + * @retval None + */ +void ETH_MAC_SetSrcPortFilterVal(uint16_t u16Port) +{ + MODIFY_REG32(M4_ETH->MAC_L4PORTR, ETH_MAC_L4PORTR_L4SPVAL, u16Port); +} + +/** + * @brief Set L3 address filter protocol. + * @param [in] u32AddrProtocol MAC L3 address filter protocol. + * This parameter can be one of the following values: + * @arg ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV4: Ip Address filter for IPv4 + * @arg ETH_MAC_L3_ADDR_FILTER_PROTOCOL_IPV6: Ip Address filter for IPv6 + * @retval None + */ +void ETH_MAC_SetAddrFilterProtocol(uint32_t u32AddrProtocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MAC_L3_ADDR_FILTER_PROTOCOL(u32AddrProtocol)); + + WRITE_REG32(bM4_ETH->MAC_L34CTLR_b.L3PEN, u32AddrProtocol); +} + +/** + * @brief Set L3 Destination address filter value of IPv4. + * @param [in] u32Addr The value of Destination address. + * @retval None + */ +void ETH_MAC_SetIpv4DestAddrFilterVal(uint32_t u32Addr) +{ + WRITE_REG32(M4_ETH->MAC_L3ADDRR1, u32Addr); +} + +/** + * @brief Set L3 Source address filter value of IPv4. + * @param [in] u32Addr The value of Source address. + * @retval None + */ +void ETH_MAC_SetIpv4SrcAddrFilterVal(uint32_t u32Addr) +{ + WRITE_REG32(M4_ETH->MAC_L3ADDRR0, u32Addr); +} + +/** + * @brief Set L3 Destination/Source Address filter value of IPv6. + * @param [in] au32Addr Pointer to Destination/Source Address buffer(4 words). + * @retval An en_result_t enumeration value: + * - Ok: Set Address filter value success + * - ErrorInvalidParameter: au32Addr == NULL + */ +en_result_t ETH_MAC_SetIpv6AddrFilterVal(const uint32_t au32Addr[]) +{ + en_result_t enRet = Ok; + + if (NULL == au32Addr) + { + enRet = ErrorInvalidParameter; + } + else + { + WRITE_REG32(M4_ETH->MAC_L3ADDRR0, au32Addr[0]); + WRITE_REG32(M4_ETH->MAC_L3ADDRR1, au32Addr[1]); + WRITE_REG32(M4_ETH->MAC_L3ADDRR2, au32Addr[2]); + WRITE_REG32(M4_ETH->MAC_L3ADDRR3, au32Addr[3]); + } + + return enRet; +} + +/******************************************************************************/ +/* DMA Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize DMA. + * @param None + * @retval None + */ +void ETH_DMA_DeInit(void) +{ + WRITE_REG32(M4_ETH->DMA_BUSMODR, 0x00020101UL); + WRITE_REG32(M4_ETH->DMA_OPRMODR, 0U); + WRITE_REG32(M4_ETH->DMA_INTENAR, 0U); + WRITE_REG32(M4_ETH->DMA_REVWDTR, 0U); + WRITE_REG32(M4_ETH->DMA_TXDLADR, 0U); + WRITE_REG32(M4_ETH->DMA_RXDLADR, 0U); +} + +/** + * @brief Initialize DMA. + * @param [in] pstcDmaInit Pointer to a @ref stc_eth_dma_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: DMA Initialize success + * - ErrorInvalidParameter: pstcDmaInit == NULL + */ +en_result_t ETH_DMA_Init(const stc_eth_dma_init_t *pstcDmaInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_BURST_MODE(pstcDmaInit->u32BurstMode)); + DDL_ASSERT(IS_ETH_DMA_ADDRESS_ALIGN(pstcDmaInit->u32AddressAlign)); + DDL_ASSERT(IS_ETH_DMA_RX_BURST_LENGTH(pstcDmaInit->u32RxDMABurstLength)); + DDL_ASSERT(IS_ETH_DMA_TX_BURST_LENGTH(pstcDmaInit->u32TxDMABurstLength)); + DDL_ASSERT(IS_ETH_DMA_ENHANCE_DESCRIPTOR(pstcDmaInit->u32EnhanceDescriptor)); + DDL_ASSERT(IS_ETH_DMA_DESC_SKIP_LENGTH(pstcDmaInit->u32DescriptorSkipLength)); + DDL_ASSERT(IS_ETH_DMA_PRIORITY_ARBITRATION(pstcDmaInit->u32DMAArbitration)); + DDL_ASSERT(IS_ETH_DMA_DROP_CHECKSUM_ERRORFRAME(pstcDmaInit->u32DropChecksumErrorFrame)); + DDL_ASSERT(IS_ETH_DMA_RECEIVE_STORE_FORWARD(pstcDmaInit->u32ReceiveStoreForward)); + DDL_ASSERT(IS_ETH_DMA_FLUSH_RECEIVEDFRAME(pstcDmaInit->u32FlushReceiveFrame)); + DDL_ASSERT(IS_ETH_DMA_TRANSMIT_STORE_FORWARD(pstcDmaInit->u32TransmitStoreForward)); + DDL_ASSERT(IS_ETH_DMA_TRANSMIT_THRESHOLD(pstcDmaInit->u32TransmitThreshold)); + DDL_ASSERT(IS_ETH_DMA_FORWARD_ERRORFRAME(pstcDmaInit->u32ForwardErrorFrame)); + DDL_ASSERT(IS_ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME(pstcDmaInit->u32ForwardUndersizeGoodFrame)); + DDL_ASSERT(IS_ETH_DMA_DROP_JUMBO_FRAME(pstcDmaInit->u32DropJumboFrame)); + DDL_ASSERT(IS_ETH_DMA_RECEIVE_THRESHOLD(pstcDmaInit->u32ReceiveThreshold)); + DDL_ASSERT(IS_ETH_DMA_SECONDFRAME_OPERARTE(pstcDmaInit->u32SecondFrameOperate)); + + /* Set Bus mode register */ + MODIFY_REG32(M4_ETH->DMA_BUSMODR, ETH_DMA_BUSMODR_CLEAR_MASK, + (pstcDmaInit->u32BurstMode | pstcDmaInit->u32AddressAlign | pstcDmaInit->u32RxDMABurstLength | + pstcDmaInit->u32TxDMABurstLength | pstcDmaInit->u32EnhanceDescriptor | pstcDmaInit->u32DescriptorSkipLength | + pstcDmaInit->u32DMAArbitration | ETH_DMA_BUSMODR_SPBL)); + /* Set Operation mode register */ + MODIFY_REG32(M4_ETH->DMA_OPRMODR, ETH_DMA_OPRMODR_CLEAR_MASK, + (pstcDmaInit->u32DropChecksumErrorFrame | pstcDmaInit->u32ReceiveStoreForward | pstcDmaInit->u32FlushReceiveFrame | + pstcDmaInit->u32TransmitStoreForward | pstcDmaInit->u32TransmitThreshold | pstcDmaInit->u32ForwardErrorFrame | + pstcDmaInit->u32ForwardUndersizeGoodFrame | pstcDmaInit->u32DropJumboFrame | pstcDmaInit->u32ReceiveThreshold | + pstcDmaInit->u32SecondFrameOperate)); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_dma_init_t to default values. + * @param [out] pstcDmaInit Pointer to a @ref stc_eth_dma_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcDmaInit == NULL + */ +en_result_t ETH_DMA_StructInit(stc_eth_dma_init_t *pstcDmaInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcDmaInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcDmaInit->u32BurstMode = ETH_DMA_BURST_MODE_FIXED; + pstcDmaInit->u32AddressAlign = ETH_DMA_ADDRESS_ALIGN_ENABLE; + pstcDmaInit->u32RxDMABurstLength = ETH_DMA_RX_BURST_LENGTH_32BEAT; + pstcDmaInit->u32TxDMABurstLength = ETH_DMA_TX_BURST_LENGTH_32BEAT; + pstcDmaInit->u32EnhanceDescriptor = ETH_DMA_ENHANCE_DESCRIPTOR_ENABLE; + pstcDmaInit->u32DescriptorSkipLength = 0U; + pstcDmaInit->u32DMAArbitration = ETH_DMA_ARBITRATION_LOOP_RXTX_1_1; + pstcDmaInit->u32DropChecksumErrorFrame = ETH_DMA_DROP_CHECKSUM_ERRORFRAME_ENABLE; + pstcDmaInit->u32ReceiveStoreForward = ETH_DMA_RECEIVE_STORE_FORWARD_ENABLE; + pstcDmaInit->u32FlushReceiveFrame = ETH_DMA_FLUSH_RECEIVEDFRAME_ENABLE; + pstcDmaInit->u32TransmitStoreForward = ETH_DMA_TRANSMIT_STORE_FORWARD_ENABLE; + pstcDmaInit->u32TransmitThreshold = ETH_DMA_TRANSMIT_THRESHOLD_64BYTE; + pstcDmaInit->u32ForwardErrorFrame = ETH_DMA_FORWARD_ERRORFRAME_DISABLE; + pstcDmaInit->u32ForwardUndersizeGoodFrame = ETH_DMA_FORWARD_UNDERSIZE_GOODFRAME_DISABLE; + pstcDmaInit->u32DropJumboFrame = ETH_DMA_DROP_JUMBO_FRAME_DISABLE; + pstcDmaInit->u32ReceiveThreshold = ETH_DMA_RECEIVE_THRESHOLD_64BYTE; + pstcDmaInit->u32SecondFrameOperate = ETH_DMA_SECONDFRAME_OPERARTE_ENABLE; + } + + return enRet; +} + +/** + * @brief Set DMA software reset. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Software reset success + * - ErrorTimeout: Reset timeout + */ +en_result_t ETH_DMA_SoftwareReset(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + WRITE_REG32(bM4_ETH->DMA_BUSMODR_b.SWR, 1U); + u32Count = ETH_TIMEOUT_SOFTWARE_RESET * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->DMA_BUSMODR_b.SWR)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @brief Set DMA Transmit priority ratio. + * @param [in] u32PrioRatio Priority ratio + * This parameter can be one of the following values: + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_1_1: Rx:Tx = 1:1 + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_2_1: Rx:Tx = 2:1 + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_3_1: Rx:Tx = 3:1 + * @arg ETH_DMA_ARBITRATION_LOOP_RXTX_4_1: Rx:Tx = 4:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_1_1: Tx:Rx = 1:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_2_1: Tx:Rx = 2:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_3_1: Tx:Rx = 3:1 + * @arg ETH_DMA_ARBITRATION_LOOP_TXRX_4_1: Tx:Rx = 4:1 + * @arg ETH_DMA_ARBITRATION_FIXED_RXPRIORTX: Fixed priority: Rx is higher than Tx + * @arg ETH_DMA_ARBITRATION_FIXED_TXPRIORRX: Fixed priority: Tx is higher than Rx + * @retval None + */ +void ETH_DMA_SetTransPrioRatio(uint32_t u32PrioRatio) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_PRIORITY_ARBITRATION(u32PrioRatio)); + + MODIFY_REG32(M4_ETH->DMA_BUSMODR, + (ETH_DMA_BUSMODR_TXPR | ETH_DMA_BUSMODR_PRAT | ETH_DMA_BUSMODR_DMAA), + u32PrioRatio); +} + +/** + * @brief Set DMA Rx watchdog counter. + * @param [in] u8Value The value of Watchdog timer + * @retval None + */ +void ETH_DMA_SetRxWatchdogCounter(uint8_t u8Value) +{ + WRITE_REG32(M4_ETH->DMA_REVWDTR, u8Value); +} + +/** + * @brief Flush transmit FIFO. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Flush transmit FIFO success + * - ErrorTimeout: Flush timeout + */ +en_result_t ETH_DMA_FlushTransmitFIFO(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + WRITE_REG32(bM4_ETH->DMA_OPRMODR_b.FTF, 1U); + u32Count = ETH_TIMEOUT_WRITE_REGISTER * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->DMA_OPRMODR_b.FTF)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @brief Enable or disable DMA transmit. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_DMA_TransmitCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->DMA_OPRMODR_b.STT, enNewSta); +} + +/** + * @brief Enable or disable DMA receive. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_DMA_ReceiveCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->DMA_OPRMODR_b.STR, enNewSta); +} + +/** + * @brief Enable or disable DMA interrupt. + * @param [in] u32IntSrc DMA interrupt source + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_INT_NIE: Normal interrupt summary + * @arg ETH_DMA_INT_AIE: Abnormal interrupt summary + * @arg ETH_DMA_INT_ERE: Early receive interrupt + * @arg ETH_DMA_INT_FBE: Fatal bus error interrupt + * @arg ETH_DMA_INT_ETE: Early transmit interrupt + * @arg ETH_DMA_INT_RWE: Receive watchdog timeout interrupt + * @arg ETH_DMA_INT_RSE: Receive process stopped interrupt + * @arg ETH_DMA_INT_RUE: Receive buffer unavailable interrupt + * @arg ETH_DMA_INT_RIE: Receive interrupt + * @arg ETH_DMA_INT_UNE: Transmit Underflow interrupt + * @arg ETH_DMA_INT_OVE: Receive Overflow interrupt + * @arg ETH_DMA_INT_TJE: Transmit jabber timeout interrupt + * @arg ETH_DMA_INT_TUE: Transmit buffer unavailable interrupt + * @arg ETH_DMA_INT_TSE: Transmit process stopped interrupt + * @arg ETH_DMA_INT_TIE: Transmit interrupt + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_DMA_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_INTERRUPT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG32_BIT(M4_ETH->DMA_INTENAR, u32IntSrc); + } + else + { + CLEAR_REG32_BIT(M4_ETH->DMA_INTENAR, u32IntSrc); + } +} + +/** + * @brief Get DMA flag status. + * @param [in] u32Flag DMA flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMA_FLAG_PTPS: Time-stamp trigger status + * @arg ETH_DMA_FLAG_PMTS: PMT trigger status + * @arg ETH_DMA_FLAG_MMCS: MMC trigger status + * @arg ETH_DMA_FLAG_NIS: Normal interrupt summary flag + * @arg ETH_DMA_FLAG_AIS: Abnormal interrupt summary flag + * @arg ETH_DMA_FLAG_ERS: Early receive flag + * @arg ETH_DMA_FLAG_FBS: Fatal bus error flag + * @arg ETH_DMA_FLAG_ETS: Early transmit flag + * @arg ETH_DMA_FLAG_RWS: Receive watchdog timeout flag + * @arg ETH_DMA_FLAG_RSS: Receive stopped flag + * @arg ETH_DMA_FLAG_RUS: Receive buffer unavailable flag + * @arg ETH_DMA_FLAG_RIS: Receive flag + * @arg ETH_DMA_FLAG_UNS: Transmit Underflow flag + * @arg ETH_DMA_FLAG_OVS: Receive Overflow flag + * @arg ETH_DMA_FLAG_TJS: Transmit jabber timeout flag + * @arg ETH_DMA_FLAG_TUS: Transmit buffer unavailable flag + * @arg ETH_DMA_FLAG_TSS: Transmit stopped flag + * @arg ETH_DMA_FLAG_TIS: Transmit interrupt flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_DMA_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->DMA_DMASTSR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Get DMA overflow flag status. + * @param [in] u32Flag DMA overflow flag type + * This parameter can be one of the following values: + * @arg ETH_DMA_OVERFLOW_RXFIFO_COUNTER: Overflow bit for FIFO overflow counter + * @arg ETH_DMA_OVERFLOW_MISSFRAME_COUNTER: Overflow bit for miss frame counter + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_DMA_GetOvfStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMA_MISS_FRAME_TYPE(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->DMA_RFRCNTR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* DMA descriptor Functions */ +/******************************************************************************/ +/** + * @brief Initializes DMA Tx descriptor in chain mode. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] astcTxDescTab Pointer to the first Tx desc list + * @param [in] au8TxBuffer Pointer to the first TxBuffer list + * @param [in] u32TxBufferCnt Number of the Tx desc in the list + * @retval An en_result_t enumeration value: + * - Ok: Initializes Tx chain mode success + * - ErrorInvalidParameter: pstcEthHandle == NULL or astcTxDescTab == NULL or + * au8TxBuffer == NULL or u32TxBufferCnt == 0 + */ +en_result_t ETH_DMA_TxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcTxDescTab[], const uint8_t au8TxBuffer[], uint32_t u32TxBufferCnt) +{ + uint32_t i; + stc_eth_dma_desc_t *pstcTxDesc; + en_result_t enRet = Ok; + + if ((NULL == pstcEthHandle) || (NULL == astcTxDescTab) || (NULL == au8TxBuffer) || (0UL== u32TxBufferCnt)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Set the DMATxDesc pointer with the first in the astcTxDescTab list */ + pstcEthHandle->stcTxDesc = astcTxDescTab; + + /* Fill each DMATxDesc descriptor */ + for (i=0U; iu32ControlStatus = ETH_DMATXDESC_TSAC; + /* Set Buffer1 address pointer */ + pstcTxDesc->u32Buffer1Addr = (uint32_t)(&au8TxBuffer[i * ETH_TXBUF_SIZE]); + /* Set the DMA Tx descriptors checksum insertion */ + if (ETH_MAC_CHECKSUM_MODE_HARDWARE == pstcEthHandle->stcCommInit.u32ChecksumMode) + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_CIC_TCPUDPICMP_FULL); + } + + /* Initialize the next descriptor with the Next Descriptor Polling */ + if (i < (u32TxBufferCnt - 1U)) + { + pstcTxDesc->u32Buffer2NextDescAddr = (uint32_t)(&astcTxDescTab[i + 1U]); + } + else + { + pstcTxDesc->u32Buffer2NextDescAddr = (uint32_t)astcTxDescTab; + } + } + + /* Set Transmit Descriptor List Address Register */ + WRITE_REG32(M4_ETH->DMA_TXDLADR, (uint32_t)astcTxDescTab); + } + + return enRet; +} + +/** + * @brief Initializes DMA Rx descriptor in chain mode. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] astcRxDescTab Pointer to the first Rx desc list + * @param [in] au8RxBuffer Pointer to the first RxBuffer list + * @param [in] u32RxBufferCnt Number of the Rx desc in the list + * @retval An en_result_t enumeration value: + * - Ok: Initializes Rx chain mode success + * - ErrorInvalidParameter: pstcEthHandle == NULL or astcRxDescTab == NULL or + * au8RxBuffer == NULL or u32RxBufferCnt == 0 + */ +en_result_t ETH_DMA_RxDescListInit(stc_eth_handle_t *pstcEthHandle, stc_eth_dma_desc_t astcRxDescTab[], const uint8_t au8RxBuffer[], uint32_t u32RxBufferCnt) +{ + uint32_t i; + stc_eth_dma_desc_t *pstcRxDesc; + en_result_t enRet = Ok; + + if ((NULL == pstcEthHandle) || (NULL == astcRxDescTab) || (NULL == au8RxBuffer) || (0UL == u32RxBufferCnt)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Set the DMARxDesc pointer with the first in the astcRxDescTab list */ + pstcEthHandle->stcRxDesc = astcRxDescTab; + + /* Fill each DMARxDesc descriptor */ + for (i=0UL; iu32ControlStatus = ETH_DMARXDESC_OWN; + /* Set Buffer1 size and Second Address Chained */ + pstcRxDesc->u32ControlBufferSize = ETH_RXBUF_SIZE | ETH_DMARXDESC_RSAC; + /* Set Buffer1 address pointer */ + pstcRxDesc->u32Buffer1Addr = (uint32_t)(&au8RxBuffer[i * ETH_RXBUF_SIZE]); + /* Set the DMA Rx Descriptor interrupt */ + if (ETH_RX_MODE_INTERRUPT == pstcEthHandle->stcCommInit.u32RxMode) + { + CLEAR_REG32_BIT(pstcRxDesc->u32ControlBufferSize, ETH_DMARXDESC_DIC); + } + + /* Initialize the next descriptor with the Next Descriptor Polling */ + if (i < (u32RxBufferCnt - 1U)) + { + pstcRxDesc->u32Buffer2NextDescAddr = (uint32_t)(&astcRxDescTab[i + 1U]); + } + else + { + pstcRxDesc->u32Buffer2NextDescAddr = (uint32_t)astcRxDescTab; + } + } + + /* Set Receive Descriptor List Address Register */ + WRITE_REG32(M4_ETH->DMA_RXDLADR, (uint32_t)astcRxDescTab); + } + + return enRet; +} + +/** + * @brief Set DMA transmit frame. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @param [in] u32FrameLength Total of data to be transmit + * @retval An en_result_t enumeration value: + * - Ok: Set transmit frame success + * - ErrorInvalidParameter: pstcEthHandle == NULL + * - ErrorInvalidMode: Descriptor is owned by the DMA + */ +en_result_t ETH_DMA_SetTransmitFrame(stc_eth_handle_t *pstcEthHandle, uint32_t u32FrameLength) +{ + uint32_t i; + uint32_t u32BufCnt; + uint32_t u32Size; + en_result_t enRet = Ok; + + if ((NULL == pstcEthHandle) || (0U == u32FrameLength)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check if the descriptor is owned by the CPU */ + if (0UL != (pstcEthHandle->stcTxDesc->u32ControlStatus & ETH_DMATXDESC_OWN)) + { + enRet = ErrorInvalidMode; + } + else + { + /* Get the number of needed Tx buffers for the current frame */ + if (u32FrameLength > ETH_TXBUF_SIZE) + { + u32BufCnt = u32FrameLength / ETH_TXBUF_SIZE; + if (0UL != (u32FrameLength % ETH_TXBUF_SIZE)) + { + u32BufCnt++; + } + } + else + { + u32BufCnt = 1U; + } + + if (1U == u32BufCnt) + { + /* Set FIRST and LAST segment */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, (ETH_DMATXDESC_TFS | ETH_DMATXDESC_TLS)); + /* Set frame size */ + MODIFY_REG32(pstcEthHandle->stcTxDesc->u32ControlBufferSize, ETH_DMATXDESC_TBS1, (u32FrameLength & ETH_DMATXDESC_TBS1)); + /* Set Own bit of the Tx descriptor */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMATXDESC_OWN); + /* Point to next descriptor */ + pstcEthHandle->stcTxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcTxDesc->u32Buffer2NextDescAddr); + } + else + { + for (i=0U; istcTxDesc->u32ControlStatus, (ETH_DMATXDESC_TFS | ETH_DMATXDESC_TLS)); + if (0U == i) + { + /* Set the FIRST segment bit */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMATXDESC_TFS); + } + + if ((u32BufCnt - 1U) == i) + { + /* Set the last segment bit */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMATXDESC_TLS); + u32Size = u32FrameLength - ((u32BufCnt - 1U) * ETH_TXBUF_SIZE); + MODIFY_REG32(pstcEthHandle->stcTxDesc->u32ControlBufferSize, ETH_DMATXDESC_TBS1, (u32Size & ETH_DMATXDESC_TBS1)); + } + else + { + /* Set frame size */ + MODIFY_REG32(pstcEthHandle->stcTxDesc->u32ControlBufferSize, ETH_DMATXDESC_TBS1, (ETH_TXBUF_SIZE & ETH_DMATXDESC_TBS1)); + } + + /* Set Own bit of the Tx descriptor */ + SET_REG32_BIT(pstcEthHandle->stcTxDesc->u32ControlStatus, ETH_DMATXDESC_OWN); + /* Pointer to next descriptor */ + pstcEthHandle->stcTxDesc = (stc_eth_dma_desc_t *)(pstcEthHandle->stcTxDesc->u32Buffer2NextDescAddr); + } + } + + /* When Tx Buffer unavailable flag is set: clear it and resume transmission */ + if (0UL != (READ_REG32_BIT(M4_ETH->DMA_DMASTSR, ETH_DMA_FLAG_TUS))) + { + /* Clear DMA TUS flag */ + WRITE_REG32(M4_ETH->DMA_DMASTSR, ETH_DMA_FLAG_TUS); + /* Resume DMA transmission */ + WRITE_REG32(M4_ETH->DMA_TXPOLLR, 0UL); + } + } + } + + return enRet; +} + +/** + * @brief Get DMA receive frame. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @retval An en_result_t enumeration value: + * - Ok: Get receive frame success + * - ErrorInvalidParameter: pstcEthHandle == NULL + * - Error: Not completed frame received + */ +en_result_t ETH_DMA_GetReceiveFrame(stc_eth_handle_t *pstcEthHandle) +{ + en_result_t enRet = Error; + + if (NULL == pstcEthHandle) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check if segment is not owned by DMA */ + if (0UL == (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMARXDESC_OWN)) + { + /* Check if last segment */ + if (0UL != (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMARXDESC_RLS)) + { + pstcEthHandle->stcRxFrame.u32SegCount++; + pstcEthHandle->stcRxFrame.pstcLSDesc = pstcEthHandle->stcRxDesc; + /* Check if last segment is first segment */ + if (1U == pstcEthHandle->stcRxFrame.u32SegCount) + { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + } + + /* Get the Frame Length of the received packet: Strip FCS */ + pstcEthHandle->stcRxFrame.u32Length = ((pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMARXDESC_FRAL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4U; + /* Get the address of the buffer start address */ + pstcEthHandle->stcRxFrame.u32Buffer = (pstcEthHandle->stcRxFrame.pstcFSDesc)->u32Buffer1Addr; + /* Pointer to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t*)(pstcEthHandle->stcRxDesc->u32Buffer2NextDescAddr); + /* Get success */ + enRet = Ok; + } + /* Check if first segment */ + else if (0UL != (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMARXDESC_RFS)) + { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + pstcEthHandle->stcRxFrame.pstcLSDesc = NULL; + pstcEthHandle->stcRxFrame.u32SegCount = 1U; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t*)(pstcEthHandle->stcRxDesc->u32Buffer2NextDescAddr); + } + /* Check if intermediate segment */ + else + { + pstcEthHandle->stcRxFrame.u32SegCount++; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t*)(pstcEthHandle->stcRxDesc->u32Buffer2NextDescAddr); + } + } + } + + return enRet; +} + +/** + * @brief Get DMA receive frame in interrupt mode. + * @param [in] pstcEthHandle Pointer to a @ref stc_eth_handle_t structure + * @retval An en_result_t enumeration value: + * - Ok: Get receive frame success + * - ErrorInvalidParameter: pstcEthHandle == NULL + * - Error: Not completed frame received + */ +en_result_t ETH_DMA_GetReceiveFrame_Interrupt(stc_eth_handle_t *pstcEthHandle) +{ + uint32_t u32DescCnt = 0U; + en_result_t enRet = Error; + + if (NULL == pstcEthHandle) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Scan descriptor owned by CPU */ + while ((0UL == (pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMARXDESC_OWN)) && (u32DescCnt < ETH_RXBUF_SIZE)) + { + u32DescCnt++; + /* Check if first segment in frame */ + if (ETH_DMARXDESC_RFS == (pstcEthHandle->stcRxDesc->u32ControlStatus & (ETH_DMARXDESC_RFS | ETH_DMARXDESC_RLS))) + { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + pstcEthHandle->stcRxFrame.pstcLSDesc = NULL; + pstcEthHandle->stcRxFrame.u32SegCount = 1U; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t*)(pstcEthHandle->stcRxDesc->u32Buffer2NextDescAddr); + } + /* Check if intermediate segment */ + else if (0UL == (pstcEthHandle->stcRxDesc->u32ControlStatus & (ETH_DMARXDESC_RFS | ETH_DMARXDESC_RLS))) + { + pstcEthHandle->stcRxFrame.u32SegCount++; + /* Point to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t*)(pstcEthHandle->stcRxDesc->u32Buffer2NextDescAddr); + } + /* Last segment */ + else + { + pstcEthHandle->stcRxFrame.u32SegCount++; + /* Last segment */ + pstcEthHandle->stcRxFrame.pstcLSDesc = pstcEthHandle->stcRxDesc; + /* Check if last segment is first segment */ + if (1U == pstcEthHandle->stcRxFrame.u32SegCount) + { + pstcEthHandle->stcRxFrame.pstcFSDesc = pstcEthHandle->stcRxDesc; + } + + /* Get the Frame Length of the received packet: Strip FCS */ + pstcEthHandle->stcRxFrame.u32Length = ((pstcEthHandle->stcRxDesc->u32ControlStatus & ETH_DMARXDESC_FRAL) >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) - 4U; + /* Get the address of the buffer start address */ + pstcEthHandle->stcRxFrame.u32Buffer = (pstcEthHandle->stcRxFrame.pstcFSDesc)->u32Buffer1Addr; + /* Pointer to next descriptor */ + pstcEthHandle->stcRxDesc = (stc_eth_dma_desc_t*)(pstcEthHandle->stcRxDesc->u32Buffer2NextDescAddr); + /* Get success */ + enRet = Ok; + break; + } + } + } + + return enRet; +} + +/** + * @brief Set DMA Tx descriptor own bit. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Owner DMA Tx descriptor owner + * This parameter can be one of the following values: + * @arg ETH_DMADESC_OWN_CPU: Descriptor is owned by CPU + * @arg ETH_DMADESC_OWN_DMA: Descriptor is owned by DMA + * @retval An en_result_t enumeration value: + * - Ok: Set Tx descriptor own bit success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_SetTxDescOwn(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Owner) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMADESC_OWN(u32Owner)); + + if (ETH_DMADESC_OWN_CPU != u32Owner) + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_OWN); + } + else + { + CLEAR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_OWN); + } + } + + return enRet; +} + +/** + * @brief Set DMA Tx descriptor buffer size. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u8BufferNum Buffer sequence number + * This parameter can be one of the following values: + * @arg ETH_DMADESC_BUFFER1: DMA Tx Desc Buffer1 + * @arg ETH_DMADESC_BUFFER2: DMA Tx Desc Buffer2 + * @param [in] u32BufferSize DMA Tx buffer size + * @retval An en_result_t enumeration value: + * - Ok: Set Tx descriptor buffer size success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_SetTxDescBufferSize(stc_eth_dma_desc_t *pstcTxDesc, uint8_t u8BufferNum, uint32_t u32BufferSize) +{ + en_result_t enRet = Ok; + uint32_t u32ShiftBit = 0UL; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMADESC_BUFFER(u8BufferNum)); + DDL_ASSERT(IS_ETH_DMATXDESC_BUFFER_SIZE(u32BufferSize)); + + /* DMA Tx Desc buffer2 */ + if (ETH_DMADESC_BUFFER1 != u8BufferNum) + { + u32ShiftBit = ETH_DMADESC_BUFFER2_SIZESHIFT; + } + MODIFY_REG32(pstcTxDesc->u32ControlBufferSize, (ETH_DMATXDESC_TBS1 << u32ShiftBit), + (u32BufferSize << u32ShiftBit)); + } + + return enRet; +} + +/** + * @brief Configure DMA Tx descriptor checksum insert. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32ChecksumMode Checksum insert mode + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_CHECKSUM_BYPASS: Checksum Engine is bypassed + * @arg ETH_DMATXDESC_CHECKSUM_IPV4HEADER: IPv4 header checksum insertion + * @arg ETH_DMATXDESC_CHECKSUM_TCPUDPICMP_SEGMENT: TCP/UDP/ICMP Checksum Insertion calculated over segment only + * @arg ETH_DMATXDESC_CHECKSUM_TCPUDPICMP_FULL: TCP/UDP/ICMP Checksum Insertion fully calculated + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx descriptor checksum insert success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescChecksumInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32ChecksumMode) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMATXDESC_CHECKSUM_CONTROL(u32ChecksumMode)); + + MODIFY_REG32(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_CIC, u32ChecksumMode); + } + + return enRet; +} + +/** + * @brief Configure DMA Tx descriptor VLAN insert. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32VlanMode VLAN insert mode + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_VLAN_BYPASS: VLAN Insertion is bypassed + * @arg ETH_DMATXDESC_VLAN_REMOVE_TAG: Remove Tag and Type fields in VLAN frame + * @arg ETH_DMATXDESC_VLAN_INSERT_TAG: Insert VLAN Tag value in ETH_MAC_VTACTLR Register into transmit frame + * @arg ETH_DMATXDESC_VLAN_REPLACE_TAG: Replace VLAN tag value in transmit frame with VLAN tag value in ETH_MAC_VTACTLR register + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx descriptor VLAN insert success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescVlanInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32VlanMode) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMATXDESC_VLAN_CONTROL(u32VlanMode)); + + MODIFY_REG32(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_VLANC, u32VlanMode); + } + + return enRet; +} + +/** + * @brief Configure DMA Tx descriptor SA insert. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32SAMode SA insert mode + * This parameter can be one of the following values: + * @arg ETH_DMATXDESC_SA_BYPASS: Source Address Insertion or Replace Control is bypassed + * @arg ETH_DMATXDESC_SA_INSTER_MACADDR0: Insert address value in MAC address register 0 into transmit frame as SA address + * @arg ETH_DMATXDESC_SA_REPLACE_MACADDR0: Replace SA address in transmit frame with address value in MAC address register 0 + * @arg ETH_DMATXDESC_SA_INSTER_MACADDR1: Insert address value in MAC address register 1 into transmit frame as SA address + * @arg ETH_DMATXDESC_SA_REPLACE_MACADDR1: Replace SA address in transmit frame with address value in MAC address register 1 + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx descriptor SA insert success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescSAInsertConfig(stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32SAMode) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMATXDESC_SA_CONTROL(u32SAMode)); + + MODIFY_REG32(pstcTxDesc->u32ControlBufferSize, ETH_DMATXDESC_SAIRC, u32SAMode); + } + + return enRet; +} + +/** + * @brief Enable or disable DMA Tx descriptor add CRC. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx add CRC success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescCRCCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + CLEAR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_DCRC); + } + else + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_DCRC); + } + } + + return enRet; +} + +/** + * @brief Enable or disable DMA Tx descriptor padding. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx padding success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescPADCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + CLEAR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_DPAD); + } + else + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_DPAD); + } + } + + return enRet; +} + +/** + * @brief Enable or disable DMA Tx descriptor timestamp. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx padding success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescTimestamp(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_TTSE); + } + else + { + CLEAR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_TTSE); + } + } + + return enRet; +} + +/** + * @brief Enable or disable DMA Tx descriptor replace CRC. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx replace CRC success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescReplaceCRCCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_CRCR); + } + else + { + CLEAR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_CRCR); + } + } + + return enRet; +} + +/** + * @brief Enable or disable DMA Tx finished interrupt. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Configure Tx interrupt configure success + * - ErrorInvalidParameter: pstcTxDesc == NULL + */ +en_result_t ETH_DMA_TxDescIntCmd(stc_eth_dma_desc_t *pstcTxDesc, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_IOC); + } + else + { + CLEAR_REG32_BIT(pstcTxDesc->u32ControlStatus, ETH_DMATXDESC_IOC); + } + } + + return enRet; +} + +/** + * @brief Get DMA Tx descriptor flag status. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Flag DMA Tx descriptor flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMATXDESC_OWN: OWN bit + * @arg ETH_DMATXDESC_IOC: Interrupt on Completion + * @arg ETH_DMATXDESC_TLS: Transmit Last Segment + * @arg ETH_DMATXDESC_TFS: Transmit First Segment + * @arg ETH_DMATXDESC_DCRC: Disable CRC + * @arg ETH_DMATXDESC_DPAD: Disable Padding + * @arg ETH_DMATXDESC_TTSE: Transmit Time Stamp Enable + * @arg ETH_DMATXDESC_CRCR: CRC Replace Control + * @arg ETH_DMATXDESC_TER: Transmit End of Ring + * @arg ETH_DMATXDESC_TSAC: Second Address Chained + * @arg ETH_DMATXDESC_TTSS: Tx Time Stamp Status + * @arg ETH_DMATXDESC_IHE: IP Header Error + * @arg ETH_DMATXDESC_ETSUM: Tx Error summary + * @arg ETH_DMATXDESC_JTE: Jabber Timeout Error + * @arg ETH_DMATXDESC_FFF: Frame Flushed + * @arg ETH_DMATXDESC_TPCE: Payload Checksum Error + * @arg ETH_DMATXDESC_LOCE: Loss Carrier Error + * @arg ETH_DMATXDESC_NCE: No Carrier Error + * @arg ETH_DMATXDESC_TLCE: Late Collision Error + * @arg ETH_DMATXDESC_ECE: Excessive Collision Error + * @arg ETH_DMATXDESC_VLF: VLAN Frame + * @arg ETH_DMATXDESC_EDE: Excessive Deferral Error + * @arg ETH_DMATXDESC_UDE: Underflow Error + * @arg ETH_DMATXDESC_DEE: Deferred Error + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_DMA_GetTxDescStatus(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMATXDESC_STATUS(u32Flag)); + + if (NULL != pstcTxDesc) + { + if (0UL != (pstcTxDesc->u32ControlStatus & u32Flag)) + { + enFlagSta = Set; + } + } + + return enFlagSta; +} + +/** + * @brief Get DMA Tx descriptor collision count + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32ColliCnt Pointer to DMA Tx collision count + * @retval An en_result_t enumeration value: + * - Ok: Get collision count success + * - ErrorInvalidParameter: pstcTxDesc == NULL or pu32ColliCnt == NULL + */ +en_result_t ETH_DMA_GetTxDescCollisionCnt(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32ColliCnt) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcTxDesc) || (NULL == pu32ColliCnt)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32ColliCnt = (pstcTxDesc->u32ControlStatus >> ETH_DMATXDESC_COLLISION_COUNTSHIFT) & ((uint32_t)0x0000000FUL); + } + + return enRet; +} + +/** + * @brief Get DMA Tx descriptor timestamp. + * @param [in] pstcTxDesc Pointer to a DMA Tx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32High Timestamp high bit time + * @param [out] pu32Low Timestamp low bit time + * @retval An en_result_t enumeration value: + * - Ok: Get timestamp success + * - ErrorInvalidParameter: pstcTxDesc == NULL or pu32High == NULL or pu32Low == NULL + */ +en_result_t ETH_DMA_GetTxDescTimeStamp(const stc_eth_dma_desc_t *pstcTxDesc, uint32_t *pu32High, uint32_t *pu32Low) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcTxDesc) || (NULL == pu32High) || (NULL == pu32Low)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32Low = pstcTxDesc->u32TimeStampLow; + *pu32High = pstcTxDesc->u32TimeStampHigh; + } + + return enRet; +} + +/** + * @brief Set DMA Rx descriptor own bit. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Owner DMA Rx descriptor owner + * This parameter can be one of the following values: + * @arg ETH_DMADESC_OWN_CPU: Descriptor is owned by CPU + * @arg ETH_DMADESC_OWN_DMA: Descriptor is owned by DMA + * @retval An en_result_t enumeration value: + * - Ok: Set Rx descriptor own bit success + * - ErrorInvalidParameter: pstcRxDesc == NULL + */ +en_result_t ETH_DMA_SetRxDescOwn(stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Owner) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMADESC_OWN(u32Owner)); + + if (ETH_DMADESC_OWN_CPU != u32Owner) + { + SET_REG32_BIT(pstcRxDesc->u32ControlStatus, ETH_DMARXDESC_OWN); + } + else + { + CLEAR_REG32_BIT(pstcRxDesc->u32ControlStatus, ETH_DMARXDESC_OWN); + } + } + + return enRet; +} + +/** + * @brief Enable or disable DMA Rx finished interrupt. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval An en_result_t enumeration value: + * - Ok: Rx interrupt configure success + * - ErrorInvalidParameter: pstcRxDesc == NULL + */ +en_result_t ETH_DMA_RxDescIntCmd(stc_eth_dma_desc_t *pstcRxDesc, en_functional_state_t enNewSta) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRxDesc) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + CLEAR_REG32_BIT(pstcRxDesc->u32ControlBufferSize, ETH_DMARXDESC_DIC); + } + else + { + SET_REG32_BIT(pstcRxDesc->u32ControlBufferSize, ETH_DMARXDESC_DIC); + } + } + + return enRet; +} + +/** + * @brief Get DMA Rx descriptor flag status. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Flag DMA Rx descriptor flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMARXDESC_OWN: OWN bit + * @arg ETH_DMARXDESC_DAF: DA Filter Fail for the received frame + * @arg ETH_DMARXDESC_ERSUM: Rx Error summary + * @arg ETH_DMARXDESC_DPE: Descriptor Error + * @arg ETH_DMARXDESC_SAF: SA Filter Fail for the received frame + * @arg ETH_DMARXDESC_LEE: Length Error + * @arg ETH_DMARXDESC_OVE: Overflow Error + * @arg ETH_DMARXDESC_VLAT VLAN Tag + * @arg ETH_DMARXDESC_RFS: First descriptor + * @arg ETH_DMARXDESC_RLS: Last descriptor + * @arg ETH_DMARXDESC_IPE_TSPA_GF: COE Error or Time stamp valid or jumbo frame + * @arg ETH_DMARXDESC_RLCE: Late collision Error + * @arg ETH_DMARXDESC_FRAT: Frame type + * @arg ETH_DMARXDESC_WTE: Receive Watchdog Timeout + * @arg ETH_DMARXDESC_REE: Receive error + * @arg ETH_DMARXDESC_DBE: Dribble bit error + * @arg ETH_DMARXDESC_CRE: CRC error + * @arg ETH_DMARXDESC_DAS_ESA: MAC Address Filter/Status bit extension + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_DMA_GetRxDescStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMARXDESC_STATUS(u32Flag)); + + if (NULL != pstcRxDesc) + { + if (0UL != (pstcRxDesc->u32ControlStatus & u32Flag)) + { + enFlagSta = Set; + } + } + + return enFlagSta; +} + +/** + * @brief Get DMA Rx descriptor extend flag status. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u32Flag DMA Rx descriptor extend flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_DMARXDESC_L4FMS: L4 Port Filter Status + * @arg ETH_DMARXDESC_L3FMS: L3 Address Filter Status + * @arg ETH_DMARXDESC_TSPD: Discard Time Stamp + * @arg ETH_DMARXDESC_PTPV: PTP Version + * @arg ETH_DMARXDESC_PTPFT: PTP Frame Type + * @arg ETH_DMARXDESC_IPV6DR: IPv6 Packet Received + * @arg ETH_DMARXDESC_IPV4DR: IPv4 Packet Received + * @arg ETH_DMARXDESC_IPCB: COE engine Bypassed + * @arg ETH_DMARXDESC_IPPE: IP Payload Error + * @arg ETH_DMARXDESC_IPHE: IP Header Error + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_DMA_GetRxDescExtendStatus(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMARXDESC_EXTEND_STATUS(u32Flag)); + + if (NULL != pstcRxDesc) + { + if (0UL != (pstcRxDesc->u32ExtendStatus & u32Flag)) + { + enFlagSta = Set; + } + } + + return enFlagSta; +} + +/** + * @brief Get DMA Rx descriptor payload type. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32PayloadType Pointer to DMA Rx payload type + * The payload type may be one of the following values: + * - ETH_DMARXDESC_IPPT_UNKNOWN: Unknown + * - ETH_DMARXDESC_IPPT_UDP: UDP + * - ETH_DMARXDESC_IPPT_TCP: TCP + * - ETH_DMARXDESC_IPPT_ICMP: ICMP + * @retval An en_result_t enumeration value: + * - Ok: Get payload type success + * - ErrorInvalidParameter: pstcRxDesc == NULL or pu32PayloadType == NULL + */ +en_result_t ETH_DMA_GetRxDescPayloadType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32PayloadType) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcRxDesc) || (NULL == pu32PayloadType)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32PayloadType = pstcRxDesc->u32ExtendStatus & ETH_DMARXDESC_IPPT; + } + + return enRet; +} + +/** + * @brief Get DMA Rx descriptor datagram type. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32DatagramType Pointer to DMA Rx datagram type + * The payload type may be one of the following values: + * - ETH_DMARXDESC_MTP_NONE: No PTP messages + * - ETH_DMARXDESC_MTP_SYNC: SYNC message (all clock types) + * - ETH_DMARXDESC_MTP_FOLLOWUP: Follow_Up message (all clock types) + * - ETH_DMARXDESC_MTP_DELAYREQ: Delay_Req message (all clock types) + * - ETH_DMARXDESC_MTP_DELAYRESP: Delay_Resp message (all clock types) + * - ETH_DMARXDESC_MTP_PDELAYREQ: Pdelay_Req message (peer-to-peer transparent clock) + * - ETH_DMARXDESC_MTP_PDELAYRESP: Pdelay_Resp message (peer-to-peer transparent clock) + * - ETH_DMARXDESC_MTP_PDELAYRESP_FOLLOWUP: Pdelay_Resp_Follow_Up message (peer-to-peer transparent clock) + * - ETH_DMARXDESC_MTP_ANNOUNCE: Announce message (Ordinary or Boundary clock) + * - ETH_DMARXDESC_MTP_MANAGEMENT: Management message (Ordinary or Boundary clock) + * - ETH_DMARXDESC_MTP_SIGNALING: Signaling message (Ordinary or Boundary clock) + * - ETH_DMARXDESC_MTP_DEFAULT: Default Datagram Type + * @retval An en_result_t enumeration value: + * - Ok: Get datagram type success + * - ErrorInvalidParameter: pstcRxDesc == NULL or pu32DatagramType == NULL + */ +en_result_t ETH_DMA_GetRxDescDatagramType(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32DatagramType) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcRxDesc) || (NULL == pu32DatagramType)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32DatagramType = pstcRxDesc->u32ExtendStatus & ETH_DMARXDESC_MTP; + } + + return enRet; +} + +/** + * @brief Get DMA Rx descriptor frame length. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32FrameLength Pointer to DMA Rx frame length + * @retval An en_result_t enumeration value: + * - Ok: Get frame length success + * - ErrorInvalidParameter: pstcRxDesc == NULL or pu32FrameLength == NULL + */ +en_result_t ETH_DMA_GetRxDescFrameLength(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32FrameLength) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcRxDesc) || (NULL == pu32FrameLength)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32FrameLength = (pstcRxDesc->u32ControlStatus >> ETH_DMARXDESC_FRAME_LENGTHSHIFT) & ((uint32_t)0x00003FFFUL); + } + + return enRet; +} + +/** + * @brief Get DMA Rx descriptor buffer size. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [in] u8BufferNum Buffer sequence number + * This parameter can be one of the following values: + * @arg ETH_DMADESC_BUFFER1: DMA Rx Desc Buffer1 + * @arg ETH_DMADESC_BUFFER2: DMA Rx Desc Buffer2 + * @param [out] pu32BufferSize Pointer to DMA Rx buffer size + * @retval An en_result_t enumeration value: + * - Ok: Get buffer size success + * - ErrorInvalidParameter: pstcRxDesc == NULL or pu32BufferSize == NULL + */ +en_result_t ETH_DMA_GetRxDescBufferSize(const stc_eth_dma_desc_t *pstcRxDesc, uint8_t u8BufferNum, uint32_t *pu32BufferSize) +{ + en_result_t enRet = Ok; + uint32_t u32ShiftBit = 0UL; + + if ((NULL == pstcRxDesc) || (NULL == pu32BufferSize)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_DMADESC_BUFFER(u8BufferNum)); + + /* DMA Rx Desc buffer2 */ + if (ETH_DMADESC_BUFFER1 != u8BufferNum) + { + u32ShiftBit = ETH_DMADESC_BUFFER2_SIZESHIFT; + } + *pu32BufferSize = (pstcRxDesc->u32ControlBufferSize >> u32ShiftBit) & ((uint32_t)0x00001FFFUL); + } + + return enRet; +} + +/** + * @brief Get DMA Rx descriptor timestamp. + * @param [in] pstcRxDesc Pointer to a DMA Rx descriptor @ref stc_eth_dma_desc_t + * @param [out] pu32High Timestamp high bit time + * @param [out] pu32Low Timestamp low bit time + * @retval An en_result_t enumeration value: + * - Ok: Get timestamp success + * - ErrorInvalidParameter: pstcRxDesc == NULL or pu32High == NULL or pu32Low == NULL + */ +en_result_t ETH_DMA_GetRxDescTimeStamp(const stc_eth_dma_desc_t *pstcRxDesc, uint32_t *pu32High, uint32_t *pu32Low) +{ + en_result_t enRet = Ok; + + if ((NULL == pstcRxDesc) || (NULL == pu32High) || (NULL == pu32Low)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32Low = pstcRxDesc->u32TimeStampLow; + *pu32High = pstcRxDesc->u32TimeStampHigh; + } + + return enRet; +} + +/******************************************************************************/ +/* PMT Functions */ +/******************************************************************************/ +/** + * @brief Reset PMT wakeup frame pointer. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Reset pointer success + * - ErrorTimeout: Reset timeout + */ +en_result_t ETH_PMT_ResetWakeupFramePointer(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + WRITE_REG32(bM4_ETH->MAC_PMTCTLR_b.RTWKFR, 1U); + u32Count = ETH_TIMEOUT_WRITE_REGISTER * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->MAC_PMTCTLR_b.RTWKFR)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} +/** + * @brief Write PMT wakeup frame register. + * @param [in] au32RegBuffer Pointer to wakeup frame filter register buffer(8 words). + * @retval An en_result_t enumeration value: + * - Ok: Write register success + * - ErrorInvalidParameter: au32RegBuffer == NULL + */ +en_result_t ETH_PMT_WriteWakeupFrameRegister(const uint32_t au32RegBuffer[]) +{ + uint32_t i; + en_result_t enRet = Ok; + + if (NULL == au32RegBuffer) + { + enRet = ErrorInvalidParameter; + } + else + { + for (i=0U; iMAC_RTWKFFR, au32RegBuffer[i]); + } + } + + return enRet; +} + +/** + * @brief Enable or disable PMT forward wakeup frame. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_PMT_ForwardWakeupFrameCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MAC_PMTCTLR_b.RTWKTR, enNewSta); +} + +/** + * @brief Enable or disable PMT wakeup source. + * @param [in] u32WakeupSrc Wakeup source + * This parameter can be one or any combination of the following values: + * @arg ETH_PMT_WAKEUP_GLOBAL_UNICAST: Global unicast + * @arg ETH_PMT_WAKEUP_WAKEUP_FRAME: Wake-Up Frame + * @arg ETH_PMT_WAKEUP_MAGIC_PACKET: Magic Packet + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_PMT_WakeupSourceCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG32_BIT(M4_ETH->MAC_PMTCTLR, u32WakeupSrc); + } + else + { + CLEAR_REG32_BIT(M4_ETH->MAC_PMTCTLR, u32WakeupSrc); + } +} + +/** + * @brief Enable or disable PMT powerdown mode. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Set powerdown mode success + * - Error: Set powerdown mode failed + */ +en_result_t ETH_PMT_EnterPowerDown(void) +{ + en_result_t enRet = Error; + + if (0UL != READ_REG32(bM4_ETH->MAC_PMTCTLR_b.MPEN)) + { + if (0UL != READ_REG32(bM4_ETH->MAC_PMTCTLR_b.WKEN)) + { + WRITE_REG32(bM4_ETH->MAC_PMTCTLR_b.PWDN, Enable); + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Get PMT flag status. + * @param [in] u32Flag PMT flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_PMT_FLAG_RTWKFR: Wake-Up Frame Filter Register Pointer Reset + * @arg ETH_PMT_FLAG_WKFR: Wake-Up Frame Received + * @arg ETH_PMT_FLAG_MPFR: Magic Packet Received + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_PMT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PMT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->MAC_PMTCTLR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* MMC Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize MMC. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: MMC De-Initialize success +* - ErrorTimeout: De-Initialize timeout + */ +en_result_t ETH_MMC_DeInit(void) +{ + WRITE_REG32(M4_ETH->MMC_MMCCTLR, 0UL); + WRITE_REG32(M4_ETH->MMC_RITCTLR, 0UL); + WRITE_REG32(M4_ETH->MMC_TITCTLR, 0UL); + + return ETH_MMC_CounterReset(); +} + +/** + * @brief Initialize MMC. + * @param [in] pstcMmcInit Pointer to a @ref stc_eth_mmc_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: MMC Initialize success + * - ErrorInvalidParameter: pstcMmcInit == NULL + */ +en_result_t ETH_MMC_Init(const stc_eth_mmc_init_t *pstcMmcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcMmcInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_COUNTER_PRESETMODE(pstcMmcInit->u32PresetMode)); + DDL_ASSERT(IS_ETH_MMC_READ_RESET(pstcMmcInit->u32ReadReset)); + DDL_ASSERT(IS_ETH_MMC_COUNTER_RELOAD(pstcMmcInit->u32ReloadMode)); + + MODIFY_REG32(M4_ETH->MMC_MMCCTLR, + (ETH_MMC_MMCCTLR_MCPSEL | ETH_MMC_MMCCTLR_MCPSET | + ETH_MMC_MMCCTLR_ROR | ETH_MMC_MMCCTLR_COS), + (pstcMmcInit->u32PresetMode | pstcMmcInit->u32ReadReset | + pstcMmcInit->u32ReloadMode)); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_mmc_init_t to default values. + * @param [out] pstcMmcInit Pointer to a @ref stc_eth_mmc_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcMmcInit == NULL + */ +en_result_t ETH_MMC_StructInit(stc_eth_mmc_init_t *pstcMmcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcMmcInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcMmcInit->u32PresetMode = ETH_MMC_COUNTER_PRESETMODE_DISABLE; + pstcMmcInit->u32ReadReset = ETH_MMC_READ_RESET_ENABLE; + pstcMmcInit->u32ReloadMode = ETH_MMC_COUNTER_RELOAD_ENABLE; + } + + return enRet; +} + +/** + * @brief MMC all counter software reset. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Reset success + * - ErrorTimeout: Reset timeout + */ +en_result_t ETH_MMC_CounterReset(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + WRITE_REG32(bM4_ETH->MMC_MMCCTLR_b.CRST, 1U); + u32Count = ETH_TIMEOUT_WRITE_REGISTER * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->MMC_MMCCTLR_b.CRST)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @brief Enable or disable the reset of all MMC counter after reading. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MMC_ResetAfterReadCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->MMC_MMCCTLR_b.ROR, enNewSta); +} + +/** + * @brief Enable or disable MMC function. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MMC_Cmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + WRITE_REG32(bM4_ETH->MMC_MMCCTLR_b.MCF, Disable); + } + else + { + WRITE_REG32(bM4_ETH->MMC_MMCCTLR_b.MCF, Enable); + } +} + +/** + * @brief Enable or disable MMC transmit interrupt. + * @param [in] u32IntSrc MMC interrupt source + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_INT_TXEDEIM: Tx excessive deferral error frame interrupt + * @arg ETH_MMC_INT_TXUGIM: Tx unicast good frame interrupt + * @arg ETH_MMC_INT_TXCAEIM: Tx carrier error frame interrupt + * @arg ETH_MMC_INT_TXECEIM: Tx excessive collision error frame interrupt + * @arg ETH_MMC_INT_TXLCEIM: Tx deferral collision error frame interrupt + * @arg ETH_MMC_INT_TXDEEIM: Tx deferral error frame interrupt + * @arg ETH_MMC_INT_TXMGIM: Tx multicast good frame interrupt + * @arg ETH_MMC_INT_TXBGIM: Tx broadcast good frame interrupt + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MMC_TxIntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_TX_INTERRUPT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + CLEAR_REG32_BIT(M4_ETH->MMC_TITCTLR, u32IntSrc); + } + else + { + SET_REG32_BIT(M4_ETH->MMC_TITCTLR, u32IntSrc); + } +} + +/** + * @brief Enable or disable MMC receive interrupt. + * @param [in] u32IntSrc MMC interrupt source + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_INT_RXOEIM: Rx out of scope error frame interrupt + * @arg ETH_MMC_INT_RXLEIM: Rx length error frame interrupt + * @arg ETH_MMC_INT_RXUGIM: Rx unicast good frame interrupt + * @arg ETH_MMC_INT_RXREIM: Rx short error frame interrupt + * @arg ETH_MMC_INT_RXAEIM: Rx alignment error frame interrupt + * @arg ETH_MMC_INT_RXCEIM: Rx crc error frame interrupt + * @arg ETH_MMC_INT_RXMGIM: Rx multicast good frame interrupt + * @arg ETH_MMC_INT_RXBGIM: Rx broadcast good frame interrupt + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_MMC_RxIntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_RX_INTERRUPT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + CLEAR_REG32_BIT(M4_ETH->MMC_RITCTLR, u32IntSrc); + } + else + { + SET_REG32_BIT(M4_ETH->MMC_RITCTLR, u32IntSrc); + } +} + +/** + * @brief Get MMC flag transmit status. + * @param [in] u32Flag MMC flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_FLAG_TXEDEIS: Tx excessive deferral error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXUGIS: Tx unicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXCAEIS: Tx carrier error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXECEIS: Tx excessive collision error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXLCEIS: Tx deferral collision error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXDEEIS: Tx deferral error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXMGIS: Tx multicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_TXBGIS: Tx broadcast good frame counter reaches half or all the maximum value + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_MMC_GetTxStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_TX_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->MMC_TRSSTSR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Get MMC receive flag status. + * @param [in] u32Flag MMC flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_MMC_FLAG_RXOEIS: Rx out of scope error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXLEIS: Rx length error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXUGIS: Rx unicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXREIS: Rx short error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXAEIS: Rx alignment error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXCEIS: Rx crc error frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXMGIS: Rx multicast good frame counter reaches half or all the maximum value + * @arg ETH_MMC_FLAG_RXBGIS: Rx broadcast good frame counter reaches half or all the maximum value + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_MMC_GetRxStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_RX_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->MMC_REVSTSR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Get MMC register. + * @param [in] u32Reg MMC statistics register + * This parameter can be one of the following values: + * @arg ETH_MMC_REG_TXBRGFR: Tx broadcast good frame Statistical Register + * @arg ETH_MMC_REG_TXMUGFR: Tx multicast good frame Statistical Register + * @arg ETH_MMC_REG_TXDEEFR: Tx deferral error frame Statistical Register + * @arg ETH_MMC_REG_TXLCEFR: Tx deferral collision error frame Statistical Register + * @arg ETH_MMC_REG_TXECEFR: Tx excessive collision error frame Statistical Register + * @arg ETH_MMC_REG_TXCAEFR: Tx carrier error frame Statistical Register + * @arg ETH_MMC_REG_TXUNGFR: Tx unicast good frame Statistical Register + * @arg ETH_MMC_REG_TXEDEFR: Tx excessive deferral error frame Statistical Register + * @arg ETH_MMC_REG_RXBRGFR: Rx broadcast good frame Statistical Register + * @arg ETH_MMC_REG_RXMUGFR: Rx multicast good frame Statistical Register + * @arg ETH_MMC_REG_RXCREFR: Rx crc error frame Statistical Register + * @arg ETH_MMC_REG_RXALEFR: Rx alignment error frame Statistical Register + * @arg ETH_MMC_REG_RXRUEFR: Rx short error frame Statistical Register + * @arg ETH_MMC_REG_RXUNGFR: Rx unicast good frame Statistical Register + * @arg ETH_MMC_REG_RXLEEFR: Rx length error frame Statistical Register + * @arg ETH_MMC_REG_RXOREFR: Rx out of scope error frame Statistical Register + * @retval uint32_t MMC statistics Register value + */ +uint32_t ETH_MMC_GetRegister(uint32_t u32Reg) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_MMC_REG(u32Reg)); + + return (*(__IO uint32_t *)((uint32_t)(&M4_ETH->MAC_CONFIGR) + u32Reg)); +} + +/******************************************************************************/ +/* PTP Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize PTP. + * @param None + * @retval None + */ +void ETH_PTP_DeInit(void) +{ + WRITE_REG32(M4_ETH->PTP_TSPCTLR, 0x00002000UL); + WRITE_REG32(M4_ETH->PTP_TSPADDR, 0UL); + WRITE_REG32(M4_ETH->PTP_TSPNSAR, 0UL); + WRITE_REG32(M4_ETH->PTP_TMUSECR, 0UL); + WRITE_REG32(M4_ETH->PTP_TMUNSER, 0UL); +} + +/** + * @brief Initialize PTP. + * @param [in] pstcPtpInit Pointer to a @ref stc_eth_ptp_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: PTP Initialize success + * - Error: PTP Initialize failed + * - ErrorInvalidParameter: pstcPtpInit == NULL + */ +en_result_t ETH_PTP_Init(const stc_eth_ptp_init_t *pstcPtpInit) +{ + en_result_t enRet; + + if (NULL == pstcPtpInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_FRAME_DA_FILTER(pstcPtpInit->u32DAFilter)); + DDL_ASSERT(IS_ETH_PTP_DATAGRAM_VERSION(pstcPtpInit->u32DatagramVersion)); + DDL_ASSERT(IS_ETH_PTP_SUBSECOND_SCALE(pstcPtpInit->u32SubSecScale)); + DDL_ASSERT(IS_ETH_PTP_DATAGRAM_TYPE(pstcPtpInit->u32SnapDatagramType)); + DDL_ASSERT(IS_ETH_PTP_FRAME_TYPE(pstcPtpInit->u32SnapFrameType)); + DDL_ASSERT(IS_ETH_PTP_CALIBRATION_MODE(pstcPtpInit->u32CalibMode)); + DDL_ASSERT(IS_ETH_PTP_SUB_SECOND(pstcPtpInit->u32InitValueSubSec)); + + /* Set increase value registers */ + WRITE_REG32(M4_ETH->PTP_TSPNSAR, pstcPtpInit->u8IncValueSubSec); + WRITE_REG32(M4_ETH->PTP_TSPADDR, pstcPtpInit->u32IncValueBasic); + enRet = ETH_PTP_UpdateBasicIncValue(); + if (Ok == enRet) + { + /* Set timestamp control register */ + MODIFY_REG32(M4_ETH->PTP_TSPCTLR, ETH_PTP_TSPCTLR_CLEAR_MASK, + (pstcPtpInit->u32DAFilter | pstcPtpInit->u32SnapDatagramType | pstcPtpInit->u32SnapFrameType | + pstcPtpInit->u32DatagramVersion | pstcPtpInit->u32SubSecScale | pstcPtpInit->u32CalibMode)); + /* Set initialize value */ + WRITE_REG32(M4_ETH->PTP_TMUSECR, pstcPtpInit->u32InitValueSec); + WRITE_REG32(M4_ETH->PTP_TMUNSER, pstcPtpInit->u32InitValueSubSec); + enRet = ETH_PTP_SystemTimeInit(); + if (Ok != enRet) + { + enRet = Error; + } + } + else + { + enRet = Error; + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_ptp_init_t to default values. + * @param [out] pstcPtpInit Pointer to a @ref stc_eth_ptp_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcPtpInit == NULL + */ +en_result_t ETH_PTP_StructInit(stc_eth_ptp_init_t *pstcPtpInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcPtpInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcPtpInit->u32DAFilter = ETH_PTP_FRAME_DA_FILTER_DISABLE; + pstcPtpInit->u32SnapDatagramType = ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY; + pstcPtpInit->u32SnapFrameType = ETH_PTP_FRAME_TYPE_IPV4FRAME; + pstcPtpInit->u32DatagramVersion = ETH_PTP_DATAGRAM_VERSION_IEEE1588V1; + pstcPtpInit->u32SubSecScale = ETH_PTP_SUBSECOND_SCALE_HEX; + pstcPtpInit->u32CalibMode = ETH_PTP_CALIBRATION_MODE_COARSE; + pstcPtpInit->u32IncValueBasic = 0UL; + pstcPtpInit->u8IncValueSubSec = 0U; + pstcPtpInit->u32InitValueSec = 0UL; + pstcPtpInit->u32InitValueSubSec = 0UL; + } + + return enRet; +} + +/** + * @brief Set PTP snapshot datagram type. + * @param [in] u32DatagramType Snapshot datagram type + * This parameter can be one of the following values: + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY: SYNC Follow_Up Delay_Req Delay_Resp + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC: SYNC + * @arg ETH_PTP_DATAGRAM_TYPE_DELAY: Delay_Req + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_FOLLOW_DELAY_PDELAY: SYNC Follow_Up Delay_Req Delay_Resp Pdelay_Req Pdelay_Resp Pdelay_Resp_Follow_Up + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_PDELAY: SYNC Pdelay_Req Pdelay_Resp + * @arg ETH_PTP_DATAGRAM_TYPE_DELAY_PDEALY: Delay_Req Pdelay_Req Pdelay_Resp + * @arg ETH_PTP_DATAGRAM_TYPE_SYNC_DELAY: SYNC Delay_Req + * @arg ETH_PTP_DATAGRAM_TYPE_PDELAY: Pdelay_Req Pdelay_Resp + * @retval None + */ +void ETH_PTP_SetSnapDatagramType(uint32_t u32DatagramType) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_DATAGRAM_TYPE(u32DatagramType)); + + MODIFY_REG32(M4_ETH->PTP_TSPCTLR, ETH_PTP_TSPCTLR_TSPMTSEL, u32DatagramType); +} + +/** + * @brief Set PTP snapshot frame type. + * @param [in] u32FrameType Snapshot frame type + * This parameter can be one or any combination of the following values: + * @arg ETH_PTP_FRAME_TYPE_IPV4FRAME: snapshot of IPv4 frame + * @arg ETH_PTP_FRAME_TYPE_IPV6FRAME: snapshot of IPv6 frame + * @arg ETH_PTP_FRAME_TYPE_ETHERNETFRAME: snapshot of PTP over ethernet frame + * @arg ETH_PTP_FRAME_TYPE_ALL_RECEIVEFRAME: snapshot of all received frame + * @retval None + */ +void ETH_PTP_SetSnapFrameType(uint32_t u32FrameType) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_FRAME_TYPE(u32FrameType)); + + MODIFY_REG32(M4_ETH->PTP_TSPCTLR, + (ETH_PTP_TSPCTLR_TSPOVIPV4 | ETH_PTP_TSPCTLR_TSPOVIPV6 | + ETH_PTP_TSPCTLR_TSPOVETH | ETH_PTP_TSPCTLR_TSPEALL), + u32FrameType); +} + +/** + * @brief Set PTP timestamp calibration mode. + * @param [in] u32CalibMode Timestamp calibration mode + * This parameter can be one of the following values: + * @arg ETH_PTP_CALIBRATION_MODE_COARSE: Coarse calibration + * @arg ETH_PTP_CALIBRATION_MODE_FINE: Fine calibration + * @retval None + */ +void ETH_PTP_SetCalibMode(uint32_t u32CalibMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_CALIBRATION_MODE(u32CalibMode)); + + WRITE_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPUPSEL, u32CalibMode >> ETH_PTP_TSPCTLR_TSPUPSEL_POS); +} + +/** + * @brief Update PTP timestamp basic increase value. + * @note Update Timestamp increase value by basic increase register. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Update timestamp increase value success + * - Error: Current state cannot be updated + * - ErrorTimeout: Update timeout + */ +en_result_t ETH_PTP_UpdateBasicIncValue(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Error; + + if (0UL == READ_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPADUP)) + { + WRITE_REG32(bM4_ETH->MMC_MMCCTLR_b.CRST, 1U); + u32Count = ETH_TIMEOUT_WRITE_REGISTER * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->MMC_MMCCTLR_b.CRST)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (ErrorTimeout != enRet) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Update PTP timestamp system time. + * @note Update Timestamp system time by update second and update subsecond registers. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Update timestamp system time success + * - Error: Current state cannot be updated + * - ErrorTimeout: Update timeout + */ +en_result_t ETH_PTP_UpdateSystemTime(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Error; + + if (0UL == READ_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPINI)) + { + if (0UL == READ_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPUP)) + { + WRITE_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPUP, 1U); + u32Count = ETH_TIMEOUT_WRITE_REGISTER * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPUP)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (ErrorTimeout != enRet) + { + enRet = Ok; + } + } + } + + return enRet; +} + +/** + * @brief Initialize PTP timestamp system time. + * @note Initialize Timestamp system time by update second and update subsecond registers. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Initialize timestamp system time success + * - Error: Current state cannot be initialized + * - ErrorTimeout: Initialize timeout + */ +en_result_t ETH_PTP_SystemTimeInit(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Error; + + if (0UL == READ_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPINI)) + { + WRITE_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPINI, 1U); + u32Count = ETH_TIMEOUT_WRITE_REGISTER * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPINI)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (ErrorTimeout != enRet) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Get PTP timestamp system time. + * @param [out] pu32Sec Pointer to Timestamp system time of Second + * @param [out] pu32SubSec Pointer to Timestamp system time of Subsecond + * @retval An en_result_t enumeration value: + * - Ok: Get timestamp system time success + * - ErrorInvalidParameter: pu32Sec == NULL or pu32SubSec == NULL + */ +en_result_t ETH_PTP_GetSystemTime(uint32_t *pu32Sec, uint32_t *pu32SubSec) +{ + en_result_t enRet = Ok; + + if ((NULL == pu32Sec) || (NULL == pu32SubSec)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32Sec = READ_REG32(M4_ETH->PTP_TMSSECR); + *pu32SubSec = READ_REG32(M4_ETH->PTP_TMSNSER); + } + + return enRet; +} + +/** + * @brief Set PTP timestamp increase value. + * @param [in] u32BasicVal Timestamp increase value of Second (Between 0x0 and 0xFFFFFFFF) + * @param [in] u8SubSecVal Timestamp increase value of Subsecond (Between 0x0 and 0xFF) + * @retval None + */ +void ETH_PTP_SetIncValue(uint32_t u32BasicVal, uint8_t u8SubSecVal) +{ + WRITE_REG32(M4_ETH->PTP_TSPADDR, u32BasicVal); + WRITE_REG32(M4_ETH->PTP_TSPNSAR, u8SubSecVal); +} + +/** + * @brief Get PTP timestamp increase value. + * @param [out] pu32BasicVal Pointer to Timestamp increase value of basic + * @param [out] pu8SubSecVal Pointer to Timestamp increase value of Subsecond + * @retval An en_result_t enumeration value: + * - Ok: Get timestamp increase value success + * - ErrorInvalidParameter: pu32BasicVal == NULL or pu8SubSecVal == NULL + */ +en_result_t ETH_PTP_GetIncValue(uint32_t *pu32BasicVal, uint8_t *pu8SubSecVal) +{ + en_result_t enRet = Ok; + + if ((NULL == pu32BasicVal) || (NULL == pu8SubSecVal)) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32BasicVal = READ_REG32(M4_ETH->PTP_TSPADDR); + *pu8SubSecVal = (uint8_t)(READ_REG32(M4_ETH->PTP_TSPNSAR) & ETH_PTP_TSPNSAR_TSPNSEADD); + } + + return enRet; +} + +/** + * @brief Set PTP timestamp update time. + * @param [in] u32Sign Timestamp Update Sign + * @arg ETH_PTP_TIME_UPDATE_SIGN_MINUS: Minus + * @arg ETH_PTP_TIME_UPDATE_SIGN_PLUS: Plus + * @param [in] u32Sec Update time of Second (Between 0x0 and 0xFFFFFFFF) + * @param [in] u32SubSec Update time of Subsecond (Between 0x0 and 0x7FFFFFFF) + * @retval None + */ +void ETH_PTP_SetUpdateTime(uint32_t u32Sign, uint32_t u32Sec, uint32_t u32SubSec) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_TIME_UPDATE_SIGN(u32Sign)); + DDL_ASSERT(IS_ETH_PTP_SUB_SECOND(u32SubSec)); + + WRITE_REG32(M4_ETH->PTP_TMUSECR, u32Sec); + WRITE_REG32(M4_ETH->PTP_TMUNSER, (u32Sign | u32SubSec)); +} + +/** + * @brief Enable or disable PTP function. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_PTP_Cmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPEN, enNewSta); +} + +/** + * @brief Enable or disable PTP interrupt. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void ETH_PTP_IntCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_ETH->PTP_TSPCTLR_b.TSPINT, enNewSta); +} + +/** + * @brief Get PTP flag status. + * @param [in] u32Flag PTP flag type + * This parameter can be one or any combination of the following values: + * @arg ETH_PTP_FLAG_TSERR1: Target time 1 error + * @arg ETH_PTP_FLAG_TSTAR1: Target time 1 reached + * @arg ETH_PTP_FLAG_TSERR0: Target time 0 error + * @arg ETH_PTP_FLAG_TSTAR0: Target time 0 reached + * @arg ETH_PTP_FLAG_TSOVF: System time overflow + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t ETH_PTP_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PTP_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_ETH->PTP_TSPSTSR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/******************************************************************************/ +/* PTP PPS Functions */ +/******************************************************************************/ +/** + * @brief De-Initialize PTP PPS. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_TARGET_CH0: PPS Channel 0 + * @arg ETH_PPS_TARGET_CH1: PPS Channel 1 + * @retval None + */ +void ETH_PPS_DeInit(uint8_t u8Ch) +{ + uint32_t u32ShiftStep = 0UL; + uint32_t u32ShiftBit = 0UL; + __IO uint32_t *PTP_TMTSECR; + __IO uint32_t *PTP_TMTNSER; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_TARGET_CH(u8Ch)); + + if (ETH_PPS_TARGET_CH1 == u8Ch) + { + u32ShiftBit = ETH_PTP_PPSCTLR_PPSFRE1_POS; + u32ShiftStep = ETH_PTP_PPS1_TIME_REG_ADDRSHIFT; + } + CLEAR_REG32_BIT(M4_ETH->PTP_PPSCTLR, + ((ETH_PTP_PPSCTLR_PPSFRE0 | ETH_PTP_PPSCTLR_PPSOMD | + ETH_PTP_PPSCTLR_TT0SEL) << u32ShiftBit)); + /* Clear target time registers */ + PTP_TMTSECR = (__IO uint32_t *)ETH_PTP_TMTSECRx(u32ShiftStep); + PTP_TMTNSER = (__IO uint32_t *)ETH_PTP_TMTNSERx(u32ShiftStep); + WRITE_REG32(*PTP_TMTSECR, 0UL); + WRITE_REG32(*PTP_TMTNSER, 0UL); +} + +/** + * @brief Initialize PTP PPS. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_TARGET_CH0: PPS Channel 0 + * @arg ETH_PPS_TARGET_CH1: PPS Channel 1 + * @param [in] pstcPpsInit Pointer to a @ref stc_eth_pps_config_t structure + * @retval An en_result_t enumeration value: + * - Ok: PPS Initialize success + * - ErrorInvalidParameter: pstcPpsInit == NULL + */ +en_result_t ETH_PPS_Init(uint8_t u8Ch, const stc_eth_pps_config_t *pstcPpsInit) +{ + en_result_t enRet = Ok; + uint32_t u32ShiftStep = 0UL; + uint32_t u32ShiftBit = 0UL; + uint32_t u32RegVal; + __IO uint32_t *PTP_TMTSECR; + __IO uint32_t *PTP_TMTNSER; + + if (NULL == pstcPpsInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_TARGET_CH(u8Ch)); + DDL_ASSERT(IS_ETH_PTP_SUB_SECOND(pstcPpsInit->u32TargetTimeSubSec)); + DDL_ASSERT(IS_ETH_PPS_TARGET_TIME_FUNC(pstcPpsInit->u32TargetTimeFunc)); + DDL_ASSERT(IS_ETH_PPS_OUTPUT_MODE(pstcPpsInit->u32OutputMode)); + DDL_ASSERT(IS_ETH_PPS_OUTPUT_FREQ(pstcPpsInit->u32OutputFreq)); + DDL_ASSERT(IS_ETH_PPS1_COMPLEX_FUNC(u8Ch, pstcPpsInit->u32OutputMode, pstcPpsInit->u32OutputFreq)); + + u32RegVal = pstcPpsInit->u32OutputFreq | pstcPpsInit->u32TargetTimeFunc; + if (ETH_PPS_TARGET_CH1 == u8Ch) + { + u32ShiftBit = ETH_PTP_PPSCTLR_PPSFRE1_POS; + u32ShiftStep = ETH_PTP_PPS1_TIME_REG_ADDRSHIFT; + } + else + { + u32RegVal |= pstcPpsInit->u32OutputMode; + } + MODIFY_REG32(M4_ETH->PTP_PPSCTLR, + ((ETH_PTP_PPSCTLR_PPSFRE0 | ETH_PTP_PPSCTLR_PPSOMD | + ETH_PTP_PPSCTLR_TT0SEL) << u32ShiftBit), + (u32RegVal << u32ShiftBit)); + /* Set target time registers */ + PTP_TMTSECR = (__IO uint32_t *)ETH_PTP_TMTSECRx(u32ShiftStep); + PTP_TMTNSER = (__IO uint32_t *)ETH_PTP_TMTNSERx(u32ShiftStep); + WRITE_REG32(*PTP_TMTSECR, pstcPpsInit->u32TargetTimeSec); + WRITE_REG32(*PTP_TMTNSER, pstcPpsInit->u32TargetTimeSubSec); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_eth_pps_config_t to default values. + * @param [out] pstcPpsInit Pointer to a @ref stc_eth_pps_config_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcPpsInit == NULL + */ +en_result_t ETH_PPS_StructInit(stc_eth_pps_config_t *pstcPpsInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcPpsInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcPpsInit->u32TargetTimeFunc = ETH_PPS_TARGET_TIME_FUNC_INT_EVENT; + pstcPpsInit->u32OutputMode = ETH_PPS_OUTPUT_MODE_SINGLE; + pstcPpsInit->u32OutputFreq = ETH_PPS_OUTPUT_ONE_PULSE; + pstcPpsInit->u32TargetTimeSec = 0UL; + pstcPpsInit->u32TargetTimeSubSec = 0UL; + } + + return enRet; +} + +/** + * @brief Set PTP Target time function. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_TARGET_CH0: PPS Channel 0 + * @arg ETH_PPS_TARGET_CH1: PPS Channel 1 + * @param [in] u32Sec Target time of Second (Between 0x0 and 0xFFFFFFFF) + * @param [in] u32SubSec Target time of Subsecond (Between 0x0 and 0x7FFFFFFF) + * @retval None + */ +void ETH_PPS_SetTargetTime(uint8_t u8Ch, uint32_t u32Sec, uint32_t u32SubSec) +{ + uint32_t u32ShiftStep = 0UL; + __IO uint32_t *PTP_TMTSECR; + __IO uint32_t *PTP_TMTNSER; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_TARGET_CH(u8Ch)); + DDL_ASSERT(IS_ETH_PTP_SUB_SECOND(u32SubSec)); + + if (ETH_PPS_TARGET_CH1 == u8Ch) + { + u32ShiftStep = ETH_PTP_PPS1_TIME_REG_ADDRSHIFT; + } + PTP_TMTSECR = (__IO uint32_t *)ETH_PTP_TMTSECRx(u32ShiftStep); + PTP_TMTNSER = (__IO uint32_t *)ETH_PTP_TMTNSERx(u32ShiftStep); + WRITE_REG32(*PTP_TMTSECR, u32Sec); + WRITE_REG32(*PTP_TMTNSER, u32SubSec); +} + +/** + * @brief Set PTP Target time function. + * @param [in] u8Ch PPS output channel + * This parameter can be one of the following values: + * @arg ETH_PPS_TARGET_CH0: PPS Channel 0 + * @arg ETH_PPS_TARGET_CH1: PPS Channel 1 + * @param [in] u32Func Arrival time trigger the function + * This parameter can be one of the following values: + * @arg ETH_PPS_TARGET_TIME_FUNC_INT_EVENT: Interrupt output event + * @arg ETH_PPS_TARGET_TIME_FUNC_INT_PPS_EVENT: Interrupt out event and PPS single output event + * @arg ETH_PPS_TARGET_TIME_FUNC_PPS_EVENT: PPS Single output event + * @retval None + */ +void ETH_PPS_SetTargetTimeFunc(uint8_t u8Ch, uint32_t u32Func) +{ + uint32_t u32ShiftBit = 0UL; + + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_TARGET_CH(u8Ch)); + DDL_ASSERT(IS_ETH_PPS_TARGET_TIME_FUNC(u32Func)); + + if (ETH_PPS_TARGET_CH1 == u8Ch) + { + u32ShiftBit = ETH_PTP_PPSCTLR_PPSFRE1_POS; + } + MODIFY_REG32(M4_ETH->PTP_PPSCTLR, (ETH_PTP_PPSCTLR_TT0SEL << u32ShiftBit), (u32Func << u32ShiftBit)); +} + +/** + * @brief Set PTP PPS0 output mode. + * @param [in] u32OutputMode PPS output mode + * This parameter can be one of the following values: + * @arg ETH_PPS_OUTPUT_MODE_CONTINUE: Continuous output mode + * @arg ETH_PPS_OUTPUT_MODE_SINGLE: Single output mode + * @retval None + */ +void ETH_PPS_SetPps0OutputMode(uint32_t u32OutputMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_OUTPUT_MODE(u32OutputMode)); + + WRITE_REG32(bM4_ETH->PTP_PPSCTLR_b.PPSOMD, u32OutputMode >> ETH_PTP_PPSCTLR_PPSOMD_POS); +} + +/** + * @brief Set PTP PPS0 output frequency. + * @param [in] u32OutputFreq PPS output frequency + * This parameter can be one of the following values: + * @arg ETH_PPS_OUTPUT_FREQ_1HZ: Ouput pulse is 1HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_2HZ: Ouput pulse is 2HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_4HZ: Ouput pulse is 4HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_8HZ: Ouput pulse is 8HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_16HZ: Ouput pulse is 16HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_32HZ: Ouput pulse is 32HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_64HZ: Ouput pulse is 64HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_128HZ: Ouput pulse is 128HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_256HZ: Ouput pulse is 256HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_512HZ: Ouput pulse is 512HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_1024HZ: Ouput pulse is 1024HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_2048HZ: Ouput pulse is 2048HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_4096HZ: Ouput pulse is 4096HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_8192HZ: Ouput pulse is 8192HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_16384HZ: Ouput pulse is 16384HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_FREQ_32768HZ: Ouput pulse is 32768HZ in continuous ouput mode + * @arg ETH_PPS_OUTPUT_ONE_PULSE: One pulse is generated in single ouput mode + * @retval None + */ +void ETH_PPS_SetPps0OutputFreq(uint32_t u32OutputFreq) +{ + /* Check parameters */ + DDL_ASSERT(IS_ETH_PPS_OUTPUT_FREQ(u32OutputFreq)); + + MODIFY_REG32(M4_ETH->PTP_PPSCTLR, ETH_PTP_PPSCTLR_PPSFRE0, u32OutputFreq); +} + +/** + * @} + */ + +#endif /* DDL_ETH_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_fcm.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_fcm.c new file mode 100644 index 0000000000000000000000000000000000000000..5d40baaec96a8930e009e939516d3c9578d75b3f --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_fcm.c @@ -0,0 +1,383 @@ +/** + ******************************************************************************* + * @file hc32f4a0_fcm.c + * @brief This file provides firmware functions to manage the Frequency Clock + * Measurement (FCM). + @verbatim + Change Logs: + Date Author Notes + 2020-03-09 Zhangxl First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_fcm.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_FCM FCM + * @brief FCM Driver Library + * @{ + */ + +#if (DDL_FCM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FCM_Local_Macros FCM Local Macros + * @{ + */ + +/** + * @defgroup FCM_Check_Parameters_Validity FCM Check Parameters Validity + * @{ + */ +/*! Parameter validity check for FCM target clock source. */ +#define IS_FCM_TAR_SOURCE(src) \ +( ((src) == FCM_TAR_CLK_XTAL) || \ + ((src) == FCM_TAR_CLK_XTAL32) || \ + ((src) == FCM_TAR_CLK_HRC) || \ + ((src) == FCM_TAR_CLK_LRC) || \ + ((src) == FCM_TAR_CLK_SWDTLRC) || \ + ((src) == FCM_TAR_CLK_PCLK1) || \ + ((src) == FCM_TAR_CLK_PLLAP) || \ + ((src) == FCM_TAR_CLK_MRC) || \ + ((src) == FCM_TAR_CLK_PLLHP) || \ + ((src) == FCM_TAR_CLK_RTCLRC)) + +/*! Parameter validity check for FCM target clock division. */ +#define IS_FCM_TAR_DIV(div) \ +( ((div) == FCM_TAR_CLK_DIV1) || \ + ((div) == FCM_TAR_CLK_DIV4) || \ + ((div) == FCM_TAR_CLK_DIV8) || \ + ((div) == FCM_TAR_CLK_DIV32)) + +/*! Parameter validity check for FCM external reference input function. */ +#define IS_FCM_EX_REF_FUNC(func) \ +( ((func) == FCM_EX_REF_OFF) || \ + ((func) == FCM_EX_REF_ON)) + +/*! Parameter validity check for FCM reference clock edge. */ +#define IS_FCM_REF_EDGE(edge) \ +( ((edge) == FCM_REF_CLK_RISING) || \ + ((edge) == FCM_REF_CLK_FALLING) || \ + ((edge) == FCM_REF_CLK_BOTH)) + +/*! Parameter validity check for FCM digital filter function. */ +#define IS_FCM_DF(df) \ +( ((df) == FCM_DF_OFF) || \ + ((df) == FCM_DF_MCKS_DIV1) || \ + ((df) == FCM_DF_MCKS_DIV4) || \ + ((df) == FCM_DF_MCKS_DIV16)) + +/*! Parameter validity check for FCM reference clock source. */ +#define IS_FCM_REF_SOURCE(src) \ +( ((src) == FCM_REF_CLK_EXINPUT) || \ + ((src) == FCM_REF_CLK_XTAL) || \ + ((src) == FCM_REF_CLK_XTAL32) || \ + ((src) == FCM_REF_CLK_HRC) || \ + ((src) == FCM_REF_CLK_LRC) || \ + ((src) == FCM_REF_CLK_SWDTLRC) || \ + ((src) == FCM_REF_CLK_PCLK1) || \ + ((src) == FCM_REF_CLK_PCLKAP) || \ + ((src) == FCM_REF_CLK_MRC) || \ + ((src) == FCM_REF_CLK_PLLHP) || \ + ((src) == FCM_REF_CLK_RTCLRC)) + +/*! Parameter validity check for FCM reference clock division. */ +#define IS_FCM_REF_DIV(div) \ +( ((div) == FCM_REF_CLK_DIV32) || \ + ((div) == FCM_REF_CLK_DIV128) || \ + ((div) == FCM_REF_CLK_DIV1024) || \ + ((div) == FCM_REF_CLK_DIV8192)) + +/*! Parameter validity check for FCM abnormal reset function. */ +#define IS_FCM_RESET_FUNC(func) \ +( ((func) == FCM_RST_OFF) || \ + ((func) == FCM_RST_ON)) + +/*! Parameter validity check for FCM abnormal behavior function. */ +#define IS_FCM_ERR_HANDLE(hd) \ +( ((hd) == FCM_ERR_INT) || \ + ((hd) == FCM_ERR_RESET)) + +/*! Parameter validity check for FCM interrupt. */ +#define IS_FCM_INT(it) (((it) | FCM_INT_MSK) == FCM_INT_MSK) + +/*! Parameter validity check for FCM flag state. */ +#define IS_FCM_FLAG(flag) \ +( ((flag) != 0x00UL) && \ + (((flag) | FCM_FLAG_MSK) == FCM_FLAG_MSK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FCM_Global_Functions FCM Global Functions + * @{ + */ + +/** + * @brief Initialize FCM. + * @param [in] pstcFcmInit Pointer to a stc_fcm_init_t structure + * that contains configuration information. + * @retval Ok: FCM initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t FCM_Init(const stc_fcm_init_t *pstcFcmInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Parameter validity checking */ + DDL_ASSERT(IS_FCM_TAR_SOURCE(pstcFcmInit->u32TarClk)); + DDL_ASSERT(IS_FCM_TAR_DIV(pstcFcmInit->u32TarClkDiv)); + DDL_ASSERT(IS_FCM_EX_REF_FUNC(pstcFcmInit->u32ExRefClkEn)); + DDL_ASSERT(IS_FCM_REF_EDGE(pstcFcmInit->u32RefClkEdge)); + DDL_ASSERT(IS_FCM_DF(pstcFcmInit->u32DigFilter)); + DDL_ASSERT(IS_FCM_REF_SOURCE(pstcFcmInit->u32RefClk)); + DDL_ASSERT(IS_FCM_REF_DIV(pstcFcmInit->u32RefClkDiv)); + DDL_ASSERT(IS_FCM_RESET_FUNC(pstcFcmInit->u32RstEn)); + DDL_ASSERT(IS_FCM_ERR_HANDLE(pstcFcmInit->u32IntRstSel)); + DDL_ASSERT(IS_FCM_INT(pstcFcmInit->u32IntType)); + + WRITE_REG32(M4_FCM->LVR, pstcFcmInit->u16LowerLimit); + WRITE_REG32(M4_FCM->UVR, pstcFcmInit->u16UpperLimit); + WRITE_REG32(M4_FCM->MCCR, (pstcFcmInit->u32TarClk | pstcFcmInit->u32TarClkDiv)); + WRITE_REG32(M4_FCM->RCCR, (pstcFcmInit->u32ExRefClkEn | pstcFcmInit->u32RefClkEdge | \ + pstcFcmInit->u32DigFilter | pstcFcmInit->u32RefClk | \ + pstcFcmInit->u32RefClkDiv)); + WRITE_REG32(M4_FCM->RIER, (pstcFcmInit->u32RstEn | pstcFcmInit->u32IntRstSel | \ + pstcFcmInit->u32IntType)); + } + return enRet; +} + +/** + * @brief Initialize FCM structure. Fill each pstcFcmInit with + * default value + * @param [in] pstcFcmInit Pointer to a stc_fcm_init_t structure + * that contains configuration information. + * @retval Ok: FCM structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t FCM_StructInit(stc_fcm_init_t *pstcFcmInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcFcmInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Reset FCM init structure parameters values */ + pstcFcmInit->u16LowerLimit = 0U; + pstcFcmInit->u16UpperLimit = 0U; + pstcFcmInit->u32TarClk = FCM_TAR_CLK_XTAL; + pstcFcmInit->u32TarClkDiv = FCM_TAR_CLK_DIV1; + pstcFcmInit->u32ExRefClkEn = FCM_EX_REF_OFF; + pstcFcmInit->u32RefClkEdge = FCM_REF_CLK_RISING; + pstcFcmInit->u32DigFilter = FCM_DF_OFF; + pstcFcmInit->u32RefClk = FCM_REF_CLK_XTAL; + pstcFcmInit->u32RefClkDiv = FCM_REF_CLK_DIV32; + pstcFcmInit->u32RstEn = FCM_RST_OFF; + pstcFcmInit->u32IntRstSel = FCM_ERR_INT; + pstcFcmInit->u32IntType = (FCM_ERR_INT_OFF | FCM_END_INT_OFF | FCM_OVF_INT_OFF); + } + return enRet; +} + +/** + * @brief De-Initialize FCM. + * @param None + * @retval None + */ +void FCM_DeInit(void) +{ + WRITE_REG32(M4_FCM->STR, FCM_REG_RESET_VALUE); + WRITE_REG32(M4_FCM->CLR, FCM_FLAG_MSK); + WRITE_REG32(M4_FCM->LVR, FCM_REG_RESET_VALUE); + WRITE_REG32(M4_FCM->UVR, FCM_REG_RESET_VALUE); + WRITE_REG32(M4_FCM->MCCR,FCM_REG_RESET_VALUE); + WRITE_REG32(M4_FCM->RCCR,FCM_REG_RESET_VALUE); + WRITE_REG32(M4_FCM->RIER,FCM_REG_RESET_VALUE); +} + +/** + * @brief Get FCM state, get FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags. + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @retval en_flag_status_t: FCM flag status. + */ +en_flag_status_t FCM_GetStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + return (READ_REG32_BIT(M4_FCM->SR, u32Flag) ? Set : Reset); +} + +/** + * @brief Clear FCM state, Clear FCM overflow, complete, error flag. + * @param [in] u32Flag FCM flags. + * @arg FCM_FLAG_ERR: FCM error. + * @arg FCM_FLAG_END: FCM measure end. + * @arg FCM_FLAG_OVF: FCM overflow. + * @arg FCM_FLAG_MSK: All above 3 flags of FCM. + * @retval None. + */ +void FCM_ClearStatus(uint32_t u32Flag) +{ + DDL_ASSERT(IS_FCM_FLAG(u32Flag)); + + SET_REG32_BIT(M4_FCM->CLR, u32Flag); +} + +/** + * @brief Get FCM counter value. + * @param None + * @retval FCM counter value. + */ +uint16_t FCM_GetCounter(void) +{ + return (uint16_t)(READ_REG32(M4_FCM->CNTR) & 0xFFFFU); +} + +/** + * @brief FCM target clock type and division config. + * @param [in] u32Tar Target clock type. + * @arg FCM_TAR_CLK_XTAL + * @arg FCM_TAR_CLK_XTAL32 + * @arg FCM_TAR_CLK_HRC + * @arg FCM_TAR_CLK_LRC + * @arg FCM_TAR_CLK_SWDTLRC + * @arg FCM_TAR_CLK_PCLK1 + * @arg FCM_TAR_CLK_PLLAP + * @arg FCM_TAR_CLK_MRC + * @arg FCM_TAR_CLK_PLLHP + * @arg FCM_TAR_CLK_RTCLRC + * @param [in] u32Div Target clock division. + * @arg FCM_TAR_CLK_DIV1 + * @arg FCM_TAR_CLK_DIV4 + * @arg FCM_TAR_CLK_DIV8 + * @arg FCM_TAR_CLK_DIV32 + * @retval None. + */ +void FCM_SetTarClk(uint32_t u32Tar, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_TAR_SOURCE(u32Tar)); + DDL_ASSERT(IS_FCM_TAR_DIV(u32Div)); + WRITE_REG32(M4_FCM->MCCR, (u32Tar | u32Div)); +} + +/** + * @brief FCM reference clock type and division config. + * @param [in] u32Ref Reference clock type. + * @arg FCM_REF_CLK_EXINPUT + * @arg FCM_REF_CLK_XTAL + * @arg FCM_REF_CLK_XTAL32 + * @arg FCM_REF_CLK_HRC + * @arg FCM_REF_CLK_LRC + * @arg FCM_REF_CLK_SWDTLRC + * @arg FCM_REF_CLK_PCLK1 + * @arg FCM_REF_CLK_PCLKAP + * @arg FCM_REF_CLK_MRC + * @arg FCM_REF_CLK_PLLHP + * @arg FCM_REF_CLK_RTCLRC + * @param [in] u32Div Reference clock division. + * @arg FCM_REF_CLK_DIV32 + * @arg FCM_REF_CLK_DIV128 + * @arg FCM_REF_CLK_DIV1024 + * @arg FCM_REF_CLK_DIV8192 + * @retval None. + */ +void FCM_SetRefClk(uint32_t u32Ref, uint32_t u32Div) +{ + DDL_ASSERT(IS_FCM_REF_SOURCE(u32Ref)); + DDL_ASSERT(IS_FCM_REF_DIV(u32Div)); + MODIFY_REG32(M4_FCM->RCCR, \ + (FCM_RCCR_INEXS | FCM_RCCR_RCKS | FCM_RCCR_RDIVS), \ + (u32Ref | u32Div)); +} + +/** + * @brief FCM function config. + * @param [in] enNewState + * @arg Enable + * @arg Disable + * @retval None. + */ +void FCM_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bM4_FCM->STR_b.START, enNewState); +} + +/** + * @} + */ + +#endif /* DDL_FCM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_fmac.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_fmac.c new file mode 100644 index 0000000000000000000000000000000000000000..84ce965685df2058474cda5e6fff9553fa626f8a --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_fmac.c @@ -0,0 +1,350 @@ +/** + ******************************************************************************* + * @file hc32f4a0_fmac.c + * @brief This file provides firmware functions to manage the Filter Math + * Accelerate (FMAC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_fmac.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_FMAC FMAC + * @brief FMAC Driver Library + * @{ + */ + +#if (DDL_FMAC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup FMAC_Local_Macros FMAC Local Macros + * @{ + */ + +/** + * @defgroup FMAC_Check_Parameters_Validity FMAC Check Parameters Validity + * @{ + */ +#define IS_FMAC_FILTER_SHIFT(x) ((x) <= FMAC_FILTER_SHIFT_21BIT) + + +#define IS_FMAC_FILTER_STAGE(x) ((x) <= FMAC_FILTER_STAGE_16) + +#define IS_FMAC_INT_FUNC(x) \ +( ((x) == FMAC_INT_ENABLE) || \ + ((x) == FMAC_INT_DISABLE)) + +#define IS_VALID_UNIT(x) \ +( ((x) == M4_FMAC1) || \ + ((x) == M4_FMAC2) || \ + ((x) == M4_FMAC3) || \ + ((x) == M4_FMAC4)) +/** + * @} + */ + + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup FMAC_Global_Functions FMAC Global Functions + * @{ + */ + +/** + * @brief FMAC peripheral initialization stucture clear + * @param [in] pstcInitStruct FMAC function structure + * @arg See the structure definition for @ref stc_fmac_init_t + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + */ +en_result_t FMAC_StructInit(stc_fmac_init_t* pstcInitStruct) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInitStruct != NULL) + { + pstcInitStruct->u32FiltStage = FMAC_FILTER_STAGE_0; + pstcInitStruct->u32FiltShift = FMAC_FILTER_SHIFT_0BIT; + pstcInitStruct->i16FiltFactor = 0; + pstcInitStruct->u32IntCmd = FMAC_INT_DISABLE; + enRet = Ok; + } + return enRet; +} + +/** + * @brief De-Initialize FMAC function + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @retval None + */ +void FMAC_DeInit(M4_FMAC_TypeDef* FMACx) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + + WRITE_REG32(FMACx->CTR, 0UL); + WRITE_REG32(FMACx->IER, 0UL); + WRITE_REG32(FMACx->DTR, 0UL); + WRITE_REG32(FMACx->RTR0, 0UL); + WRITE_REG32(FMACx->RTR1, 0UL); + WRITE_REG32(FMACx->STR, 0UL); +} + +/** + * @brief FMAC peripheral function initialize + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [in] pstcFmacInit FMAC function base parameter structure + * @arg See the structure definition for @ref stc_fmac_init_t + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + */ +en_result_t FMAC_Init(M4_FMAC_TypeDef* FMACx, const stc_fmac_init_t *pstcFmacInit) +{ + en_result_t enRet = ErrorInvalidParameter; + __IO uint32_t *FMAC_CORx; + uint32_t u32temp; + if(pstcFmacInit != NULL) + { + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FMAC_FILTER_SHIFT(pstcFmacInit->u32FiltShift)); + DDL_ASSERT(IS_FMAC_FILTER_STAGE(pstcFmacInit->u32FiltStage)); + DDL_ASSERT(IS_FMAC_INT_FUNC(pstcFmacInit->u32IntCmd)); + u32temp = pstcFmacInit->u32FiltStage; + /* Configure filter stage and results right shift bits */ + WRITE_REG32(FMACx->CTR, (pstcFmacInit->u32FiltStage | \ + (pstcFmacInit->u32FiltShift << FMAC_CTR_SHIFT_POS))); + /* Configure interrupt command */ + WRITE_REG32(FMACx->IER, pstcFmacInit->u32IntCmd); + do{ + FMAC_CORx = (__IO uint32_t *)((uint32_t)(&FMACx->COR0) + (u32temp << 2UL)); + WRITE_REG32(*FMAC_CORx, pstcFmacInit->i16FiltFactor); + }while((u32temp--) > 0UL); + enRet = Ok; + } + return enRet; +} + +/** + * @brief Enable or Disable FMAC + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void FMAC_Cmd(M4_FMAC_TypeDef* FMACx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(FMACx->ENR, enNewState); +} + +/** + * @brief Set Filter result shift bits. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [in] u32ShiftNum Result shift times. + * This parameter can be set 0-21 + * @retval None + */ +void FMAC_SetResultShift(M4_FMAC_TypeDef* FMACx, uint32_t u32ShiftNum) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FMAC_FILTER_SHIFT(u32ShiftNum)); + /* Set Filter result shift bits */ + MODIFY_REG32(FMACx->CTR, FMAC_CTR_SHIFT, u32ShiftNum << FMAC_CTR_SHIFT_POS); +} + +/** + * @brief Set filter stage and filter factor. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [in] u32FilterStage FMAC filter stage. + * This parameter can be set 0 ~ 16 + * @param [in] i16Factor FMAC filter factor. + * This parameter can be set -32768 ~ 32767 + * @retval None + */ +void FMAC_SetStageFactor(M4_FMAC_TypeDef* FMACx, uint32_t u32FilterStage, int16_t i16Factor) +{ + __IO uint32_t *FMAC_CORx; + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FMAC_FILTER_STAGE(u32FilterStage)); + /* FMAC Software reset */ + CLEAR_REG32_BIT(FMACx->ENR, FMAC_ENR_FMACEN); + SET_REG32_BIT(FMACx->ENR, FMAC_ENR_FMACEN); + /* Set the filter stage */ + MODIFY_REG32(FMACx->CTR, FMAC_CTR_STAGE_NUM, u32FilterStage); + do + { + FMAC_CORx = (__IO uint32_t*)((uint32_t)(&FMACx->COR0) + (u32FilterStage << 2UL)); + WRITE_REG32(*FMAC_CORx, i16Factor); + }while((u32FilterStage--) > 0UL); +} + +/** + * @brief Configure interrupt command. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [in] enNewState Disable or Enable the function. + * @retval None + */ +void FMAC_IntCmd(M4_FMAC_TypeDef* FMACx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(FMACx->IER, enNewState); +} + +/** + * @brief Data input. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [in] i16Factor Data that needs to be processed. + * @retval None + */ +void FMAC_FIRInput(M4_FMAC_TypeDef* FMACx, int16_t i16Factor) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + WRITE_REG32(FMACx->DTR, i16Factor); +} + +/** + * @brief Get FMAC status. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @retval Set Calculate complete + * Reset Calculation in progress + */ +en_flag_status_t FMAC_GetStatus(const M4_FMAC_TypeDef* FMACx) +{ + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + return (READ_REG32_BIT(FMACx->STR, FMAC_STR_READY) ? Set : Reset); +} + +/** + * @brief Get calculation results. + * @param [in] FMACx Pointer to FMAC instance register base. + * This parameter can be a value of the following: + * @arg M4_FMAC1: FMAC unit 1 instance register base + * @arg M4_FMAC2: FMAC unit 2 instance register base + * @arg M4_FMAC3: FMAC unit 3 instance register base + * @arg M4_FMAC4: FMAC unit 4 instance register base + * @param [out] stcResult Get result. + * u32ResultHigh: The high value of the result + * u32ResultLow: The low value of the result + * @retval Ok: Success + * ErrorInvalidParameter: stcResult == NULL + */ +en_result_t FMAC_GetResult(const M4_FMAC_TypeDef* FMACx, stc_fmac_result_t *stcResult) +{ + en_result_t enRet = ErrorInvalidParameter; + DDL_ASSERT(IS_VALID_UNIT(FMACx)); + + if (stcResult != NULL) + { + stcResult->u32ResultHigh = READ_REG32(FMACx->RTR0); + stcResult->u32ResultLow = READ_REG32(FMACx->RTR1); + enRet = Ok; + } + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_FMAC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ + diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_gpio.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..4c0c9ccef0f461c9b42ad5649963ea6f81f10be8 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_gpio.c @@ -0,0 +1,651 @@ +/** + ******************************************************************************* + * @file hc32f4a0_gpio.c + * @brief This file provides firmware functions to manage the General Purpose + * Input/Output(GPIO). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-09-18 Zhangxl Optimize GPIO_DeInit() API + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_gpio.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_GPIO GPIO + * @brief GPIO Driver Library + * @{ + */ + +#if (DDL_GPIO_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup GPIO_Local_Macros GPIO Local Macros + * @{ + */ +/** + * @defgroup GPIO_Registers_Reset_Value GPIO Registers Reset Value + * @{ + */ +#define GPIO_PSPCR_RESET_VALUE (0x001FU) +#define GPIO_PCCR_RESET_VALUE (0x1000U) +#define GPIO_PINAER_RESET_VALUE (0x0000U) +/** + * @} + */ + +/** + * @defgroup GPIO_Check_Parameters_Validity GPIO Check Parameters Validity + * @{ + */ +/*! Parameter validity check for pin state. */ +#define IS_GPIO_PIN_STATE(state) \ +( ((state) == PIN_STATE_RESET) || \ + ((state) == PIN_STATE_SET)) + +/*! Parameter validity check for pin direction. */ +#define IS_GPIO_DIR(dir) \ +( ((dir) == PIN_DIR_IN) || \ + ((dir) == PIN_DIR_OUT)) + +/*! Parameter validity check for pin output type. */ +#define IS_GPIO_OTYPE(otype) \ +( ((otype) == PIN_OTYPE_CMOS) || \ + ((otype) == PIN_OTYPE_NMOS)) + +/*! Parameter validity check for pin driver capacity. */ +#define IS_GPIO_PIN_DRV(drv) \ +( ((drv) == PIN_DRV_LOW) || \ + ((drv) == PIN_DRV_MID) || \ + ((drv) == PIN_DRV_HIGH)) + +/*! Parameter validity check for pin latch function. */ +#define IS_GPIO_LATCH(latch) \ +( ((latch) == PIN_LATCH_OFF) || \ + ((latch) == PIN_LATCH_ON)) + +/*! Parameter validity check for internal pull-up resistor. */ +#define IS_GPIO_PIN_PU(pu) \ +( ((pu) == PIN_PU_OFF) || \ + ((pu) == PIN_PU_ON)) + +/*! Parameter validity check for pin state invert. */ +#define IS_GPIO_PIN_INVERT(invert) \ +( ((invert) == PIN_INVERT_OFF) || \ + ((invert) == PIN_INVERT_ON)) + +/*! Parameter validity check for pin input type. */ +#define IS_GPIO_ITYPE(itype) \ +( ((itype) == PIN_ITYPE_SMT) || \ + ((itype) == PIN_ITYPE_CMOS)) + +/*! Parameter validity check for external interrupt function. */ +#define IS_GPIO_EXINT(exint) \ +( ((exint) == PIN_EXINT_OFF) || \ + ((exint) == PIN_EXINT_ON)) + +/*! Parameter validity check for pin attribute. */ +#define IS_GPIO_ATTR(attr) \ +( ((attr) == PIN_ATTR_DIGITAL) || \ + ((attr) == PIN_ATTR_ANALOG)) + +/*! Parameter validity check for pin number. */ +#define IS_GPIO_PIN(pin) (((pin) & GPIO_PIN_MASK ) != 0x0000U) + +/*! Parameter validity check for port source. */ +#define IS_GPIO_PORT(port) \ +( ((port) != 0x00U) && \ + (((port) | GPIO_PORT_MASK) == GPIO_PORT_MASK)) + +/*! Parameter validity check for port source. */ +#define IS_GPIO_PORT_SOURCE(port) \ +( ((port) == GPIO_PORT_A) || \ + ((port) == GPIO_PORT_B) || \ + ((port) == GPIO_PORT_C) || \ + ((port) == GPIO_PORT_D) || \ + ((port) == GPIO_PORT_E) || \ + ((port) == GPIO_PORT_F) || \ + ((port) == GPIO_PORT_G) || \ + ((port) == GPIO_PORT_H) || \ + ((port) == GPIO_PORT_I)) + +/*! Parameter validity check for pin function. */ +#define IS_GPIO_FUNC(func) \ +( ((func) <= GPIO_FUNC_20) || \ + (((func) >= GPIO_FUNC_32) && ((func) <= GPIO_FUNC_63))) + +/*! Parameter validity check for debug pin definition. */ +#define IS_GPIO_DEBUG_PORT(port) \ +( ((port) != 0x00U) && \ + (((port) | GPIO_PIN_DEBUG_JTAG) == GPIO_PIN_DEBUG_JTAG)) + +/*! Parameter validity check for pin sub-function setting. */ +#define IS_GPIO_PIN_BFE(bfe) \ +( ((bfe) == PIN_SUBFUNC_ENABLE) || \ + ((bfe) == PIN_SUBFUNC_DISABLE)) + +/*! Parameter validity check for pin read wait cycle. */ +#define IS_GPIO_READ_WAIT(wait) \ +( ((wait) == GPIO_READ_WAIT_0) || \ + ((wait) == GPIO_READ_WAIT_1) || \ + ((wait) == GPIO_READ_WAIT_2) || \ + ((wait) == GPIO_READ_WAIT_3) || \ + ((wait) == GPIO_READ_WAIT_4) || \ + ((wait) == GPIO_READ_WAIT_5) || \ + ((wait) == GPIO_READ_WAIT_6) || \ + ((wait) == GPIO_READ_WAIT_7)) + +/* Check GPIO register lock status. */ +#define IS_GPIO_UNLOCKED() (GPIO_PWPR_WE == (M4_GPIO->PWPR & GPIO_PWPR_WE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup GPIO_Global_Functions GPIO Global Functions + * @{ + */ + +/** + * @brief Initialize GPIO. + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval Ok: GPIO initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t GPIO_Init(uint8_t u8Port, uint16_t u16Pin, const stc_gpio_init_t *pstcGpioInit) +{ + __IO uint16_t *PCRx; + uint16_t u16PinPos; + uint16_t u16PCRVal; + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_PIN_STATE(pstcGpioInit->u16PinState)); + DDL_ASSERT(IS_GPIO_DIR(pstcGpioInit->u16PinDir)); + DDL_ASSERT(IS_GPIO_OTYPE(pstcGpioInit->u16PinOType)); + DDL_ASSERT(IS_GPIO_PIN_DRV(pstcGpioInit->u16PinDrv)); + DDL_ASSERT(IS_GPIO_LATCH(pstcGpioInit->u16Latch)); + DDL_ASSERT(IS_GPIO_PIN_PU(pstcGpioInit->u16PullUp)); + DDL_ASSERT(IS_GPIO_PIN_INVERT(pstcGpioInit->u16Invert)); + DDL_ASSERT(IS_GPIO_ITYPE(pstcGpioInit->u16PinIType)); + DDL_ASSERT(IS_GPIO_EXINT(pstcGpioInit->u16ExInt)); + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + for (u16PinPos = 0U; u16PinPos < 16U; u16PinPos++) + { + if ((u16Pin & (1UL<PCRA0) + \ + ((uint32_t)(u8Port) * 0x40UL) + u16PinPos * 4UL); + + u16PCRVal = pstcGpioInit->u16ExInt | pstcGpioInit->u16PinIType | \ + pstcGpioInit->u16Invert | pstcGpioInit->u16PullUp | \ + pstcGpioInit->u16Latch | pstcGpioInit->u16PinDrv | \ + pstcGpioInit->u16PinOType | pstcGpioInit->u16PinState | \ + pstcGpioInit->u16PinDir | pstcGpioInit->u16PinAttr; + WRITE_REG16(*PCRx, u16PCRVal); + } + } + } + return enRet; +} + +/** + * @brief De-init GPIO register to default value + * @param None + * @retval None + */ +void GPIO_DeInit(void) +{ + stc_gpio_init_t stcGpioInit; + + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + (void)GPIO_StructInit(&stcGpioInit); + + /* PORTA reset */ + (void)GPIO_Init(GPIO_PORT_A, GPIO_PIN_ALL, &stcGpioInit); + /* PORTB reset */ + (void)GPIO_Init(GPIO_PORT_B, GPIO_PIN_ALL, &stcGpioInit); + /* PORTC reset */ + (void)GPIO_Init(GPIO_PORT_C, GPIO_PIN_ALL, &stcGpioInit); + /* PORTD reset */ + (void)GPIO_Init(GPIO_PORT_D, GPIO_PIN_ALL, &stcGpioInit); + /* PORTE reset */ + (void)GPIO_Init(GPIO_PORT_E, GPIO_PIN_ALL, &stcGpioInit); + /* PORTF reset */ + (void)GPIO_Init(GPIO_PORT_F, GPIO_PIN_ALL, &stcGpioInit); + /* PORTG reset */ + (void)GPIO_Init(GPIO_PORT_G, GPIO_PIN_ALL, &stcGpioInit); + /* PORTH reset */ + (void)GPIO_Init(GPIO_PORT_H, GPIO_PIN_ALL, &stcGpioInit); + /* PORTI reset */ + (void)GPIO_Init(GPIO_PORT_I, (GPIO_PIN_00 | GPIO_PIN_01 | GPIO_PIN_02 | \ + GPIO_PIN_03 | GPIO_PIN_04 | GPIO_PIN_05 | \ + GPIO_PIN_06 | GPIO_PIN_07 | GPIO_PIN_08 | \ + GPIO_PIN_09 | GPIO_PIN_10 | GPIO_PIN_11 | \ + GPIO_PIN_12 | GPIO_PIN_13), &stcGpioInit); + /* PORT global register reset */ + WRITE_REG16(M4_GPIO->PSPCR, GPIO_PSPCR_RESET_VALUE); + WRITE_REG16(M4_GPIO->PCCR, GPIO_PCCR_RESET_VALUE); + WRITE_REG16(M4_GPIO->PINAER, GPIO_PINAER_RESET_VALUE); +} + +/** + * @brief Initialize GPIO config structure. Fill each pstcGpioInit with default value + * @param [in] pstcGpioInit: Pointer to a stc_gpio_init_t structure that + * contains configuration information. + * @retval Ok: GPIO structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t GPIO_StructInit(stc_gpio_init_t *pstcGpioInit) +{ + en_result_t enRet = Ok; + /* Check if pointer is NULL */ + if (NULL == pstcGpioInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Reset GPIO init structure parameters values */ + pstcGpioInit->u16PinState = PIN_STATE_RESET; + pstcGpioInit->u16PinDir = PIN_DIR_IN; + pstcGpioInit->u16PinOType = PIN_OTYPE_CMOS; + pstcGpioInit->u16PinDrv = PIN_DRV_LOW; + pstcGpioInit->u16Latch = PIN_LATCH_OFF; + pstcGpioInit->u16PullUp = PIN_PU_OFF; + pstcGpioInit->u16Invert = PIN_INVERT_OFF; + pstcGpioInit->u16PinIType = PIN_ITYPE_SMT; + pstcGpioInit->u16ExInt = PIN_EXINT_OFF; + pstcGpioInit->u16PinAttr = PIN_ATTR_DIGITAL; + } + return enRet; +} + +/** + * @brief GPIO debug port configure. Set debug pins to GPIO + * @param [in] u8DebugPort + * @arg GPIO_PIN_SWDIO + * @arg GPIO_PIN_SWCLK + * @arg GPIO_PIN_SWO + * @arg GPIO_PIN_DEBUG_SWD + * @arg GPIO_PIN_TCK + * @arg GPIO_PIN_TMS + * @arg GPIO_PIN_TDO + * @arg GPIO_PIN_TDI + * @arg GPIO_PIN_TRST + * @arg GPIO_PIN_DEBUG_JTAG + * @param [in] enNewState + * @arg Enable: set to debug port (SWD/JTAG) + * @arg Disable: set to GPIO + * @retval None + */ +void GPIO_SetDebugPort(uint8_t u8DebugPort, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_DEBUG_PORT(u8DebugPort)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + if (Enable == enNewState) + { + SET_REG16_BIT(M4_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } + else + { + CLEAR_REG16_BIT(M4_GPIO->PSPCR, ((uint16_t)u8DebugPort & GPIO_PSPCR_SPFE)); + } +} + +/** + * @brief Set specified Port Pin function , and turn ON/OFF its sub-function + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @param [in] u8Func: GPIO_FUNC_x, x can be selected from GPIO function definitions + * @param [in] u16BFE: GPIO Sub-function enable setting + * @arg PIN_SUBFUNC_ENABLE + * @arg PIN_SUBFUNC_DISABLE + * @retval None + */ +void GPIO_SetFunc(uint8_t u8Port, uint16_t u16Pin, uint8_t u8Func, uint16_t u16BFE) +{ + __IO uint16_t *PFSRx; + uint8_t u8PinPos; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_GPIO_FUNC(u8Func)); + DDL_ASSERT(IS_GPIO_PIN_BFE(u16BFE)); + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + for (u8PinPos = 0U; u8PinPos < 16U; u8PinPos++) + { + if ((u16Pin & (uint16_t)(1UL << u8PinPos)) != 0U) + { + PFSRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PFSRA0) + \ + (uint32_t)(u8Port * 0x40UL) + u8PinPos * 4UL); + WRITE_REG16(*PFSRx, (u16BFE | (uint16_t)u8Func)); + } + } +} + +/** + * @brief Set the sub-function, it's a global configuration + * @param [in] u8Func: GPIO_FUNC_x, x can be selected from GPIO function definitions + * @retval None + */ +void GPIO_SetSubFunc(uint8_t u8Func) +{ + DDL_ASSERT(IS_GPIO_FUNC(u8Func)); + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + MODIFY_REG16(M4_GPIO->PCCR, GPIO_PCCR_BFSEL, u8Func); +} + +/** + * @brief Initialize GPIO. + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @param [in] enNewState + * @arg Enable: set specified pin output enable + * @arg Disable: set specified pin output disable + * @retval None + */ +void GPIO_OE(uint8_t u8Port, uint16_t u16Pin, en_functional_state_t enNewState) +{ + __IO uint16_t *POERx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + POERx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POERA) + 0x10UL * u8Port); + + if (Enable == enNewState) + { + SET_REG16_BIT(*POERx, u16Pin); + } + else + { + CLEAR_REG16_BIT(*POERx, u16Pin); + } +} + +/** + * @brief GPIO read wait cycle configure. + * @param [in] u16ReadWait + * @arg GPIO_READ_WAIT_0: ~ 50MHz + * @arg GPIO_READ_WAIT_1: 50 ~ 100MHz + * @arg GPIO_READ_WAIT_2: 100 ~ 150MHz + * @arg GPIO_READ_WAIT_3: 150 ~ 200MHz + * @arg GPIO_READ_WAIT_4: 200 ~ 250MHz + * @arg GPIO_READ_WAIT_5: 250MHz above + * @arg GPIO_READ_WAIT_6: 250MHz above + * @arg GPIO_READ_WAIT_7: 250MHz above + * @retval None + */ +void GPIO_SetReadWaitCycle(uint16_t u16ReadWait) +{ + DDL_ASSERT(IS_GPIO_READ_WAIT(u16ReadWait)); + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + MODIFY_REG16(M4_GPIO->PCCR, GPIO_PCCR_RDWT, u16ReadWait); +} + +/** + * @brief GPIO input MOS always ON configure. + * @param [in] u16PortIdx: Port index + * @arg GPIO_PORTA_IDX + * @arg GPIO_PORTB_IDX + * @arg GPIO_PORTC_IDX + * @arg GPIO_PORTD_IDX + * @arg GPIO_PORTE_IDX + * @arg GPIO_PORTF_IDX + * @arg GPIO_PORTG_IDX + * @arg GPIO_PORTH_IDX + * @arg GPIO_PORTI_IDX + * @arg GPIO_PORT_ALL + * @param [in] enNewState + * @arg Enable: set input MOS always ON + * @arg Disable: set input MOS turns on while read operation + * @retval None + */ +void GPIO_InMOSCmd(uint16_t u16PortIdx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_GPIO_PORT(u16PortIdx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_GPIO_UNLOCKED()); + + if (Enable == enNewState) + { + SET_REG16_BIT(M4_GPIO->PINAER, u16PortIdx); + } + else + { + CLEAR_REG16_BIT(M4_GPIO->PINAER, u16PortIdx); + } +} + +/** + * @brief Read specified GPIO input data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @retval Specified GPIO port pin input value + */ +en_pin_state_t GPIO_ReadInputPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO uint16_t *PIDRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PIDRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PIDRA) + 0x10UL * u8Port); + + return ((READ_REG16(*PIDRx) & (u16Pin)) != 0U) ? Pin_Set : Pin_Reset; +} + +/** + * @brief Read specified GPIO input data port + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @retval Specified GPIO port input value + */ +uint16_t GPIO_ReadInputPort(uint8_t u8Port) +{ + __IO uint16_t *PIDRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + + PIDRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PIDRA) + 0x10UL * u8Port); + + return READ_REG16(*PIDRx); +} + +/** + * @brief Read specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @retval Specified GPIO port pin output value + */ +en_pin_state_t GPIO_ReadOutputPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO uint16_t *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port); + + return ((*PODRx & (u16Pin)) != 0U) ? Pin_Set : Pin_Reset; +} + +/** + * @brief Read specified GPIO output data port + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @retval Specified GPIO port output value + */ +uint16_t GPIO_ReadOutputPort(uint8_t u8Port) +{ + __IO uint16_t *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + + PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port); + + return READ_REG16(*PODRx); +} + +/** + * @brief Set specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @retval None + */ +void GPIO_SetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO uint16_t *POSRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POSRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POSRA) + 0x10UL * u8Port); + SET_REG16_BIT(*POSRx, u16Pin); +} + +/** + * @brief Reset specified GPIO output data port pins + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @retval None + */ +void GPIO_ResetPins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO uint16_t *PORRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + PORRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PORRA) + 0x10UL * u8Port); + SET_REG16_BIT(*PORRx, u16Pin); +} + +/** + * @brief Write specified GPIO data port + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16PortVal: Pin output value + * @retval None + */ +void GPIO_WritePort(uint8_t u8Port, uint16_t u16PortVal) +{ + __IO uint16_t *PODRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + + PODRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PODRA) + 0x10UL * u8Port); + WRITE_REG16(*PODRx, u16PortVal); + +} + +/** + * @brief Toggle specified GPIO output data port pin + * @param [in] u8Port: GPIO_PORT_x, x can be (A~I) to select the GPIO peripheral + * @param [in] u16Pin: GPIO_PIN_x, x can be (00~15) to select the PIN index + * @retval None + */ +void GPIO_TogglePins(uint8_t u8Port, uint16_t u16Pin) +{ + __IO uint16_t *POTRx; + + /* Parameter validity checking */ + DDL_ASSERT(IS_GPIO_PORT_SOURCE(u8Port)); + DDL_ASSERT(IS_GPIO_PIN(u16Pin)); + + POTRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->POTRA) + 0x10UL * u8Port); + SET_REG16_BIT(*POTRx, u16Pin); +} + +/** + * @} + */ + +#endif /* DDL_GPIO_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_hash.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_hash.c new file mode 100644 index 0000000000000000000000000000000000000000..102ab0ab33d3ad59d6f363b1ec767f27627f2315 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_hash.c @@ -0,0 +1,732 @@ +/** + ******************************************************************************* + * @file hc32f4a0_hash.c + * @brief This file provides firmware functions to manage the HASH + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_hash.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_HASH HASH + * @brief HASH Driver Library + * @{ + */ + +#if (DDL_HASH_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HASH_Local_Macros HASH Local Macros + * @{ + */ +#define HASH_TIMEOUT (6000U) + +#define HASH_INT_MASK (HASH_INT_GROUP | HASH_INT_ALL) + +#define HASH_FLAG_MASK (HASH_FLAG_START | HASH_FLAG_BUSY | \ + HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END) + +#define HASH_CLR_FLAG_MASK (HASH_FLAG_CYC_END | HASH_FLAG_HMAC_END) +/** + * @defgroup HASH_Check_Parameters_Validity HASH Check Parameters Validity + * @{ + */ +#define IS_VALID_MODE(x) \ +( ((x) == HASH_MODE_SHA_256) || \ + ((x) == HASH_MODE_HMAC)) + +#define IS_VALID_KEY_LEN(x) \ +( ((x) == HASH_KEY_LEN_LONG) || \ + ((x) == HASH_KEY_LEN_SHORT)) + +#define IS_VALID_INT_CMD(x) (((x) | HASH_INT_MASK) == HASH_INT_MASK) + +#define IS_VALID_FLAG(x) (((x) | HASH_FLAG_MASK) == HASH_FLAG_MASK) + +#define IS_VALID_MSG_GRP(x) \ +( ((x) == HASH_MSG_GRP_FIRST) || \ + ((x) == HASH_MSG_GRP_END) || \ + ((x) == HASH_MSG_GRP_ONLY_ONE)) + +#define IS_VALID_FLAG_CLR(x) \ +( ((x) != 0x0UL) && \ + (((x) | HASH_CLR_FLAG_MASK) == HASH_CLR_FLAG_MASK)) + +#define IS_VALID_COM_TRIG(x) \ +( ((x) != 0x0UL) && \ + (((x) | HASH_COM_TRIG_MASk) == HASH_COM_TRIG_MASk)) + +#define IS_VALID_TRG_REG_SEL(x) \ +( ((x) == HASH_TRIG_REG_BLKCOM) || \ + ((x) == HASH_TRIG_REG_TRNCOM)) + +#define IS_VALID_TRG_SRC_SEL(x) \ +( ((x) == HASH_TRG_SRC_DMA1_BTC0) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC1) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC2) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC3) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC4) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC5) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC6) || \ + ((x) == HASH_TRG_SRC_DMA1_BTC7) || \ + ((x) == HASH_TRG_SRC_DMA1_TC0) || \ + ((x) == HASH_TRG_SRC_DMA1_TC1) || \ + ((x) == HASH_TRG_SRC_DMA1_TC2) || \ + ((x) == HASH_TRG_SRC_DMA1_TC3) || \ + ((x) == HASH_TRG_SRC_DMA1_TC4) || \ + ((x) == HASH_TRG_SRC_DMA1_TC5) || \ + ((x) == HASH_TRG_SRC_DMA1_TC6) || \ + ((x) == HASH_TRG_SRC_DMA1_TC7) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC0) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC1) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC2) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC3) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC4) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC5) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC6) || \ + ((x) == HASH_TRG_SRC_DMA2_BTC7) || \ + ((x) == HASH_TRG_SRC_DMA2_TC0) || \ + ((x) == HASH_TRG_SRC_DMA2_TC1) || \ + ((x) == HASH_TRG_SRC_DMA2_TC2) || \ + ((x) == HASH_TRG_SRC_DMA2_TC3) || \ + ((x) == HASH_TRG_SRC_DMA2_TC4) || \ + ((x) == HASH_TRG_SRC_DMA2_TC5) || \ + ((x) == HASH_TRG_SRC_DMA2_TC6) || \ + ((x) == HASH_TRG_SRC_DMA2_TC7)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void HASH_WriteData(uint8_t u8Data[]); +static en_result_t HASH_Fill_Calc_Data(const uint8_t au8Data[], uint32_t u32DataSize); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup HASH_Global_Functions HASH Global Functions + * @{ + */ + +/** + * @brief HASH calculate. + * @param [in] pvSrcData Pointer to the source data buffer + * @param [in] u32SrcDataSize Length of the input buffer in bytes + * @param [out] au8MsgDigest Buffer of the digest. The size must be 32 bytes + * @retval Ok: Success + * ErrorBufferFull: Filling Error + * ErrorInvalidParameter: Parameter error + */ +en_result_t HASH_Calculate(const void *pvSrcData, + uint32_t u32SrcDataSize, + uint8_t au8MsgDigest[]) +{ + en_result_t enRet = ErrorInvalidParameter; + if((pvSrcData != NULL) && + (u32SrcDataSize != 0UL) && + (au8MsgDigest != NULL)) + { + /* Set HMAC Mode */ + + (void)HASH_SetMode(HASH_MODE_SHA_256); + if(HASH_Fill_Calc_Data(pvSrcData, u32SrcDataSize) == Ok) + { + /* Get the message digest result */ + HASH_GetResult(au8MsgDigest); + enRet = Ok; + } + else + { + enRet = ErrorBufferFull; + } + } + return enRet; +} + +/** + * @brief HMAC calculate. + * @param [in] pvSrcData Pointer to the source data buffer + * @param [in] u32SrcDataSize Length of the input buffer in bytes + * @param [in] au8Key Buffer of the secret key + * @param [in] u32KeyLength Length of the input secret key in bytes + * @param [out] au8MsgDigest Buffer of the digest data buffer. The size must be 32 bytes + * @retval Ok: Success + * Error: Filling Error + * ErrorInvalidParameter: Parameter error + * ErrorTimeout: Process timeout + */ +en_result_t HMAC_Calculate(const void *pvSrcData, + uint32_t u32SrcDataSize, + const uint8_t au8Key[], + uint32_t u32KeyLength, + uint8_t au8MsgDigest[]) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TimeCount = 0UL; + uint8_t u8FillBuffer[HASH_GROUP_LEN] = {0UL}; + if ((pvSrcData != NULL) && + (u32SrcDataSize != 0UL) && + (au8Key != NULL) && + (u32KeyLength != 0UL) && + (au8MsgDigest != NULL)) + { + enRet = Ok; + /* Set HMAC Mode */ + (void)HASH_SetMode(HASH_MODE_HMAC); + if (u32KeyLength > HASH_GROUP_LEN) + { + SET_REG32_BIT(M4_HASH->CR, HASH_CR_LKEY); + /* Write the key to the data register */ + (void)HASH_Fill_Calc_Data(au8Key, u32KeyLength); + } + else + { + (void)memcpy(u8FillBuffer, &au8Key[0U], u32KeyLength); + /* Write the key to the data register */ + HASH_WriteData(u8FillBuffer); + /* Set first group. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_FST_GRP); + /* Set last group. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_KMSG_END); + /* Start hash calculating. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_START); + /* Wait for operation completion */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_BUSY)) + { + if(u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + /* Clear operation completion flag */ + CLEAR_REG32_BIT(M4_HASH->CR, HASH_CR_CYC_END); + if (enRet == Ok) + { + u32TimeCount =0UL; + /* Write the message to the data register */ + if (HASH_Fill_Calc_Data(pvSrcData, u32SrcDataSize) == Ok) + { + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_HMAC_END) == 0UL) + { + if (u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + /* Clear operation completion flag */ + CLEAR_REG32_BIT(M4_HASH->CR, HASH_CR_CYC_END); + CLEAR_REG32_BIT(M4_HASH->CR, HASH_CR_HMAC_END); + /* Get the message digest result */ + HASH_GetResult(au8MsgDigest); + } + } + } + } + return enRet; +} + +/** + * @brief Start HASH. + * @param None + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +en_result_t HASH_Start(void) +{ + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if (u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + /* Start hash calculating. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_START); + } + return enRet; +} + +/** + * @brief Enable or Disable HASH interrupt. + * @param [in] u32HashInt Specifies the HASH interrupt to check. + * This parameter can be following values: + * @arg HASH_INT_GROUP: A set of data operations complete interrupt + * @arg HASH_INT_ALL: All data operations complete interrupt + * @param [in] enNewState The new state of specified interrupt. + * This parameter can be: Enable or Disable. + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +en_result_t HASH_IntCmd(uint32_t u32HashInt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_INT_CMD(u32HashInt)); + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if(u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + if (enNewState == Enable) + { + SET_REG32_BIT(M4_HASH->CR, u32HashInt); + } + else + { + CLEAR_REG32_BIT(M4_HASH->CR, u32HashInt); + } + } + return enRet; +} + +/** + * @brief Set mode for the HASH + * @param [in] u32HashMode HASH mode selection + * This parameter can be one of the following values: + * @arg HASH_MODE_SHA_256: SHA_256 Operating mode + * @arg HASH_MODE_HMAC: HMAC Operating mode + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +en_result_t HASH_SetMode(uint32_t u32HashMode) +{ + DDL_ASSERT(IS_VALID_MODE(u32HashMode)); + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if (u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + MODIFY_REG32(M4_HASH->CR, HASH_CR_MODE, u32HashMode); + } + return enRet; +} + +/** + * @brief Get HASH status + * @param [in] u32HashFlag Specifies the flag to query. + * @arg HASH_FLAG_START: Operation in progress + * @arg HASH_FLAG_BUSY: Operation in progress + * @arg HASH_FLAG_CYC_END: key or message operation completed + * @arg HASH_FLAG_HMAC_END: HMAC operation completed + * @retval Set: Flag is set + * Reset: Flag is reset + */ +en_flag_status_t HASH_GetStatus(uint32_t u32HashFlag) +{ + en_flag_status_t enRet; + DDL_ASSERT(IS_VALID_FLAG(u32HashFlag)); + + enRet = (READ_REG32_BIT(M4_HASH->CR, u32HashFlag) ? Set :Reset); + return enRet; +} + +/** + * @brief Set HASH key length + * @param [in] u32KeyLen Key length. + * This parameter can be a value of the following: + * @arg HASH_KEY_LEN_LONG: Key length > 64 Bytes + * @arg HASH_KEY_LEN_SHORT: Key length <= 64 Bytes + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +en_result_t HASH_SetKeyLength(uint32_t u32KeyLen) +{ + DDL_ASSERT(IS_VALID_KEY_LEN(u32KeyLen)); + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if (u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + MODIFY_REG32(M4_HASH->CR, HASH_CR_LKEY, u32KeyLen); + } + return enRet; +} + +/** + * @brief Clear HASH status + * @param [in] u32ClearFlag Specifies the flag to clear. + * This parameter can be a value of the following: + * @arg HASH_FLAG_CYC_END: Clear the key or message operation completed flag + * @arg HASH_FLAG_HMAC_END: Clear the HMAC operation completed flag + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +en_result_t HASH_ClearStatus(uint32_t u32ClearFlag) +{ + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + DDL_ASSERT(IS_VALID_FLAG_CLR(u32ClearFlag)); + + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if (u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + CLEAR_REG32_BIT(M4_HASH->CR, u32ClearFlag); + } + return enRet; +} + +/** + * @brief Set trigger source for HASH + * @param [in] enSrc Specifies the Event as trigger source. + * This parameter can be a value of the following: + * @arg HASH_TRG_SRC_DMA1_BTC0: Select the DMA1 channel_0 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC1: Select the DMA1 channel_1 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC2: Select the DMA1 channel_2 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC3: Select the DMA1 channel_3 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC4: Select the DMA1 channel_4 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC5: Select the DMA1 channel_5 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC6: Select the DMA1 channel_6 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_BTC7: Select the DMA1 channel_7 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC0: Select the DMA1 channel_0 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC1: Select the DMA1 channel_1 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC2: Select the DMA1 channel_2 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC3: Select the DMA1 channel_3 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC4: Select the DMA1 channel_4 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC5: Select the DMA1 channel_5 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC6: Select the DMA1 channel_6 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA1_TC7: Select the DMA1 channel_7 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC0: Select the DMA2 channel_0 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC1: Select the DMA2 channel_1 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC2: Select the DMA2 channel_2 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC3: Select the DMA2 channel_3 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC4: Select the DMA2 channel_4 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC5: Select the DMA2 channel_5 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC6: Select the DMA2 channel_6 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_BTC7: Select the DMA2 channel_7 block transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC0: Select the DMA2 channel_0 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC1: Select the DMA2 channel_1 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC2: Select the DMA2 channel_2 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC3: Select the DMA2 channel_3 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC4: Select the DMA2 channel_4 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC5: Select the DMA2 channel_5 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC6: Select the DMA2 channel_6 transfer complete as trigger source + * @arg HASH_TRG_SRC_DMA2_TC7: Select the DMA2 channel_7 transfer complete as trigger source + * @retval None + */ +void HASH_SetTriggerSrc(en_event_src_t enSrc) +{ + DDL_ASSERT(IS_VALID_TRG_SRC_SEL(enSrc)); + + if(((enSrc >= HASH_TRG_SRC_DMA1_TC0) && (enSrc <= HASH_TRG_SRC_DMA1_TC7)) || \ + ((enSrc >= HASH_TRG_SRC_DMA2_TC0) && (enSrc <= HASH_TRG_SRC_DMA2_TC7))) + { + MODIFY_REG32(M4_AOS->HASH_ITRGSELA, AOS_HASH_ITRGSELA_TRGSEL, enSrc); + } + else + { + MODIFY_REG32(M4_AOS->HASH_ITRGSELB, AOS_HASH_ITRGSELB_TRGSEL, enSrc); + } +} + +/** + * @brief Enable or Disable common trigger source for HASH + * @param [in] u8TrigReg HASH common trigger source select. + * This parameter can be a value of @ref HASH_Common_Trigger_Reg_Sel + * @arg HASH_TRIG_REG_BLKCOM: DMA block transfer complete register. + * @arg HASH_TRID_REG_TRNCOM: DMA transfer complete register + * @param [in] u32ComTrig Common trigger event enable bit mask. + * This parameter can be value of @ref HASH_Common_Trigger_Sel + * @arg HASH_COM_TRIG1: Common trigger source 1. + * @arg HASH_COM_TRIG2: Common trigger source 2. + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void HASH_ComTriggerCmd(uint8_t u8TrigReg, uint32_t u32ComTrig, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TRG_REG_SEL(u8TrigReg)); + DDL_ASSERT(IS_VALID_COM_TRIG(u32ComTrig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + __IO uint32_t *HASH_ITRGSELx = (__IO uint32_t *)((uint32_t)&M4_AOS->HASH_ITRGSELA + 4UL * u8TrigReg); + + if (enNewState == Enable) + { + SET_REG32_BIT(*HASH_ITRGSELx, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(*HASH_ITRGSELx, u32ComTrig); + } +} + +/** + * @brief Set the group of messages. + * @param [in] u32MsgGroup First group or Last group of messages. + * This parameter can be a value of the following: + * @arg HASH_MSG_GRP_FIRST: The first group of messages or keys + * @arg HASH_MSG_GRP_END: The last group of messages or keys + * @arg HASH_MSG_GRP_ONLY_ONE: Only one set of message or key + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +en_result_t HASH_MsgGrpConfig(uint32_t u32MsgGroup) +{ + DDL_ASSERT(IS_VALID_MSG_GRP(u32MsgGroup)); + en_result_t enRet = Ok; + uint32_t u32TimeCount = 0UL; + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if (u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + SET_REG32_BIT(M4_HASH->CR, u32MsgGroup); + } + return enRet; +} + +/** + * @brief Provides the message digest result. + * @param [out] au8MsgDigest Buffer for message digest. + * @retval None + */ +void HASH_GetResult(uint8_t au8MsgDigest[]) +{ + uint8_t i; + uint32_t u32Temp1; + uint32_t u32HashHr = (uint32_t)(&M4_HASH->HR7); + uint32_t u32DigestHr = (uint32_t)(&au8MsgDigest[0U]); + for (i = 0U; i < 8U; i++) + { + u32Temp1 = __REV(RW_MEM32(u32HashHr)); + *(uint32_t *)(u32DigestHr) = u32Temp1; + u32HashHr += 4U; + u32DigestHr += 4U; + } +} + +/** + * @brief HASH Filling data + * @param [in] au8Data The source data buffer + * @param [in] u32DataSize Length of the input buffer in bytes + * @retval Ok: Success + * ErrorTimeout: Process timeout + */ +static en_result_t HASH_Fill_Calc_Data(const uint8_t au8Data[], uint32_t u32DataSize) +{ + en_result_t enRet = Ok; + uint8_t au8FillBuffer[HASH_GROUP_LEN]; + uint8_t u8FirstGroup = 0U; + uint8_t u8LastGroup = 0U; + uint8_t u8FillFlag = 0U; + uint32_t u32TimeCount = 0UL; + uint32_t u32GroupCount = 0UL; + uint32_t u32BitLenHi; + uint32_t u32BitLenLo; + uint32_t u32Index; + u32BitLenHi = (u32DataSize >> 29UL) & 0x7UL; + u32BitLenLo = (u32DataSize << 3UL); + while(u32DataSize > 0UL) + { + /* Wait for the HASH to stop */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_START)) + { + if(u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if (enRet == Ok) + { + u32Index = u32GroupCount * HASH_GROUP_LEN; + if((u32DataSize >= HASH_GROUP_LEN)) + { + (void)memset(au8FillBuffer, 0, HASH_GROUP_LEN); + (void)memcpy(au8FillBuffer, &au8Data[u32Index], HASH_GROUP_LEN); + HASH_WriteData(au8FillBuffer); + u32GroupCount++; + u32DataSize -= HASH_GROUP_LEN; + } + else + { + (void)memset(au8FillBuffer, 0, HASH_GROUP_LEN); + if(u32DataSize >= LAST_GROUP_MAX_LEN) + { + if(u8FillFlag == 0U) + { + (void)memcpy(au8FillBuffer, &au8Data[u32Index], u32DataSize); + au8FillBuffer[u32DataSize] = 0x80U; + u8FillFlag = 1U; + } + else + { + u32DataSize = 0UL; + } + } + else + { + (void)memcpy(au8FillBuffer, &au8Data[u32Index], u32DataSize); + au8FillBuffer[u32DataSize] = 0x80U; + u32DataSize = 0UL; + } + if(0U == u32DataSize) + { + au8FillBuffer[63U] = (uint8_t)(u32BitLenLo); + au8FillBuffer[62U] = (uint8_t)(u32BitLenLo >> 8U); + au8FillBuffer[61U] = (uint8_t)(u32BitLenLo >> 16U); + au8FillBuffer[60U] = (uint8_t)(u32BitLenLo >> 24U); + au8FillBuffer[59U] = (uint8_t)(u32BitLenHi); + au8FillBuffer[58U] = (uint8_t)(u32BitLenHi >> 8U); + au8FillBuffer[57U] = (uint8_t)(u32BitLenHi >> 16U); + au8FillBuffer[56U] = (uint8_t)(u32BitLenHi >> 24U); + u8LastGroup = 1U; + } + HASH_WriteData(au8FillBuffer); + } + /* check if first group */ + if (0U == u8FirstGroup) + { + u8FirstGroup = 1U; + /* Set first group. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_FST_GRP); + } + /* check if last group */ + if (1U == u8LastGroup) + { + u8LastGroup = 0U; + /* Set last group. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_KMSG_END); + } + /* Start hash calculating. */ + SET_REG32_BIT(M4_HASH->CR, HASH_CR_START); + /* Wait for operation completion */ + while(READ_REG32_BIT(M4_HASH->CR, HASH_CR_BUSY)) + { + if(u32TimeCount++ > HASH_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + } + } + return enRet; +} + +/** + * @brief Writes the input buffer in data register. + * @param [in] au8Data The buffer for source data + * @retval None + */ +static void HASH_WriteData(uint8_t au8Data[]) +{ + uint8_t i; + uint32_t u32Temp1; + uint32_t u32HashDr = (uint32_t)&(M4_HASH->DR15); + + for (i = 0U; i < 16U; i++) + { + u32Temp1 = __REV(RW_MEM32(&au8Data[i*4U])); + RW_MEM32(u32HashDr) = u32Temp1; + u32HashDr += 4U; + } +} + +/** + * @} + */ + +#endif /* DDL_HASH_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_hrpwm.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_hrpwm.c new file mode 100644 index 0000000000000000000000000000000000000000..0e32563c5936ee2eb32271239396fe8713eb1ab2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_hrpwm.c @@ -0,0 +1,413 @@ +/** + ******************************************************************************* + * @file hc32f4a0_hrpwm.c + * @brief This file provides firmware functions to manage the High Resolution + * Pulse-Width Modulation(HRPWM). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-09-07 Wangmin Modify channel delay configure function + parameter type. + 2020-10-13 Wangmin Define variable for count as __IO type + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_hrpwm.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_HRPWM HRPWM + * @brief HRPWM Driver Library + * @{ + */ + +#if (DDL_HRPWM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup HRPWM_Local_Macros HRPWM Local Macros + * @{ + */ +/* About 1mS timeout */ +#define HRPWM_CAL_TIMEOUT (HCLK_VALUE/1000UL) +#define HRPWM_PCLK0_MIN (120000000UL) + +#define HRPWM_SYSCLKSOURCE_HRC (0x00U) +#define HRPWM_SYSCLKSOURCE_MRC (0x01U) +#define HRPWM_SYSCLKSOURCE_LRC (0x02U) +#define HRPWM_SYSCLKSOURCE_XTAL (0x03U) +#define HRPWM_SYSCLKSOURCE_XTAL32 (0x04U) +#define HRPWM_SYSCLKSOURCE_PLLH (0x05U) + +#define HRPWM_PLLSRC_XTAL (0x00UL) +#define HRPWM_PLLSRC_HRC (0x01UL) + +/** + * @defgroup HRPWM_Check_Parameters_Validity HRPWM Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for HRPWM output channel */ +#define IS_VALID_HRPWM_CH(x) \ +( ((x) >= HRPWM_CH_MIN) && \ + ((x) <= HRPWM_CH_MAX)) + +/*! Parameter valid check for HRPWM caliration unit */ +#define IS_VALID_HRPWM_CAL_UNIT(x) \ +( (HRPWM_CAL_UNIT0 == (x)) || \ + (HRPWM_CAL_UNIT1 == (x))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup HRPWM_Global_Functions HRPWM Global Functions + * @{ + */ + +/** + * @brief Process for getting HRPWM Calibrate function code + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @param [out] pu8Code The pointer to get calibrate code. + * @retval Ok: Success + * @retval ErrorTimeout: Time out + * @retval ErrorInvalidParameter: Parameter error + */ +en_result_t HRPWM_CalibrateProcess(uint32_t u32Unit, uint8_t* pu8Code) +{ + __IO uint32_t u32Timeout = HRPWM_CAL_TIMEOUT; + en_result_t enRet = Ok; + + if(NULL != pu8Code) + { + /* Enable calibrate */ + HRPWM_CalibrateCmd(u32Unit, Enable); + /* Wait calibrate finish flag */ + while(Disable == HRPWM_GetCalibrateStd(u32Unit)) + { + if(0UL == u32Timeout--) + { + enRet = ErrorTimeout; + break; + } + } + + if(Ok == enRet) + { + /* Get calibrate code */ + *pu8Code = HRPWM_GetCalCode(u32Unit); + } + } + else + { + enRet = ErrorInvalidParameter; + } + return enRet; +} + +/** + * @brief HRPWM Calibrate function enable or disable for specified unit + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void HRPWM_CalibrateCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CALCRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CALCRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CALCR0) + 4UL*u32Unit); + + if(Enable == enNewState) + { + SET_REG32_BIT(*CALCRx, HRPWM_CALCR_CALEN); + + } + else + { + CLEAR_REG32_BIT(*CALCRx, HRPWM_CALCR_CALEN); + } +} + +/** + * @brief HRPWM Calibrate function status get for specified unit + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @retval Enable: Calibration function is on. + * @retval Disable: Calibration function is off. + */ +en_functional_state_t HRPWM_GetCalibrateStd(uint32_t u32Unit) +{ + en_functional_state_t enRet; + __IO uint32_t *CALCRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit)); + + CALCRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CALCR0) + 4UL*u32Unit); + + if( 0UL != READ_REG32_BIT(*CALCRx, HRPWM_CALCR_ENDF)) + { + enRet = Enable; + } + else + { + enRet = Disable; + } + return enRet; +} + +/** + * @brief HRPWM Calibrate code get for specified unit + * @param [in] u32Unit Calibrate unit, the parameter should be HRPWM_CAL_UNIT0 or HRPWM_CAL_UNIT1 + * @retval uint8_t: The calibration code. + */ +uint8_t HRPWM_GetCalCode(uint32_t u32Unit) +{ + __IO uint32_t *CALCRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CAL_UNIT(u32Unit)); + + CALCRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CALCR0) + 4UL*u32Unit); + + return ((uint8_t)(READ_REG32(*CALCRx))); +} + +/** + * @brief HRPWM function enable or disable for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void HRPWM_CHCmd(uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL)); + if(Enable == enNewState) + { + SET_REG32_BIT(*CRx, HRPWM_CR_EN); + } + else + { + CLEAR_REG32_BIT(*CRx, HRPWM_CR_EN); + } +} + +/** + * @brief HRPWM positive edge adjust enable or disable for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void HRPWM_CHPositAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL)); + if(Enable == enNewState) + { + SET_REG32_BIT(*CRx, HRPWM_CR_PE); + } + else + { + CLEAR_REG32_BIT(*CRx, HRPWM_CR_PE); + } +} + +/** + * @brief HRPWM negative edge adjust enable or disable for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void HRPWM_CHNegatAdjCmd(uint32_t u32Ch, en_functional_state_t enNewState) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL)); + if(Enable == enNewState) + { + SET_REG32_BIT(*CRx, HRPWM_CR_NE); + } + else + { + CLEAR_REG32_BIT(*CRx, HRPWM_CR_NE); + } +} + +/** + * @brief HRPWM positive edge adjust delay counts configration for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] u8DelayNum Delay counts of minimum delay time. + * @retval None + */ +void HRPWM_CHPositCfg(uint32_t u32Ch, uint8_t u8DelayNum) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + + CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL)); + MODIFY_REG32(*CRx, HRPWM_CR_PSEL, ((uint32_t)u8DelayNum-1UL) << HRPWM_CR_PSEL_POS); +} + +/** + * @brief HRPWM negative edge adjust delay counts configration for specified channel + * @param [in] u32Ch Channel, the parameter should range from HRPWM_CH_MIN to HRPWM_CH_MAX + * @param [in] u8DelayNum Delay counts of minimum delay time. + * @retval None + */ +void HRPWM_CHNegatCfg(uint32_t u32Ch, uint8_t u8DelayNum) +{ + __IO uint32_t *CRx; + /* Check parameters */ + DDL_ASSERT(IS_VALID_HRPWM_CH(u32Ch)); + + CRx = (__IO uint32_t*)(((uint32_t)&M4_HRPWM->CR1) + 4UL*(u32Ch - 1UL)); + MODIFY_REG32(*CRx, HRPWM_CR_NSEL, ((uint32_t)u8DelayNum-1UL) << HRPWM_CR_NSEL_POS); +} + +/** + * @brief HRPWM Judge the condition of calibration function. + * @param None + * @retval Enable: Condition is ready. + * @retval Disable: Condition is not ready. + */ +en_functional_state_t HRPWM_ConditionConfirm(void) +{ + en_functional_state_t enRet = Enable; + uint32_t plln; + uint32_t pllp; + uint32_t pllm; + uint32_t sysclkFreq; + uint32_t pclk0Freq; + + switch (READ_REG8_BIT(M4_CMU->CKSWR, CMU_CKSWR_CKSW)) + { + case HRPWM_SYSCLKSOURCE_HRC: + /* HRC is used to system clock */ + sysclkFreq = HRC_VALUE; + break; + case HRPWM_SYSCLKSOURCE_MRC: + /* MRC is used to system clock */ + sysclkFreq = MRC_VALUE; + break; + case HRPWM_SYSCLKSOURCE_LRC: + /* LRC is used to system clock */ + sysclkFreq = LRC_VALUE; + break; + case HRPWM_SYSCLKSOURCE_XTAL: + /* XTAL is used to system clock */ + sysclkFreq = XTAL_VALUE; + break; + case HRPWM_SYSCLKSOURCE_XTAL32: + /* XTAL32 is used to system clock */ + sysclkFreq = HRC_VALUE; + break; + case HRPWM_SYSCLKSOURCE_PLLH: + /* PLLHP is used as system clock. */ + pllp = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHP_POS) & 0x0FUL); + plln = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL); + pllm = (uint32_t)((M4_CMU->PLLHCFGR >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL); + + /* fpll = ((pllin / pllm) * plln) / pllp */ + if (HRPWM_PLLSRC_XTAL == READ_REG32_BIT(M4_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC)) + { + sysclkFreq = ((XTAL_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL); + } + else + { + sysclkFreq = ((HRC_VALUE/(pllm + 1UL))*(plln + 1UL))/(pllp + 1UL); + } + break; + default: + sysclkFreq = HRC_VALUE; + enRet = Disable; + break; + } + + if(Enable == enRet) + { + /* Get pclk0. */ + pclk0Freq = sysclkFreq >> (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK0S) >> CMU_SCFGR_PCLK0S_POS); + + if(pclk0Freq < HRPWM_PCLK0_MIN) + { + enRet = Disable; + } + } + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_HRPWM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2c.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..31c3d8c56531acd9aaf0457abe6a8b353630f0aa --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2c.c @@ -0,0 +1,1631 @@ +/** + ******************************************************************************* + * @file hc32f4a0_i2c.c + * @brief This file provides firmware functions to manage the Inter-Integrated + * Circuit(I2C). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hexiao First version + 2020-07-15 Hexiao Modify I2C_SmBusCmd to I2C_SetMode + 2020-08-31 Hexiao Refine I2C_Init/I2C_SendData/I2C_RcvData + 2020-09-15 Hexiao Modify I2C_RcvData for manually ack and nack + 2020-10-30 Hexiao Optimize data transfer api,etc. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_i2c.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_I2C I2C + * @brief I2C Driver Library + * @{ + */ + +#if (DDL_I2C_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2C_Local_Macros I2C Local Macros + * @{ + */ + +#define I2C_CLR_MASK (0x00F052DFUL) +#define I2C_INT_MASK (0x00F052DFUL) +#define I2C_SCL_HIGHT_LOW_LVL_SUM_MAX ((float32_t)0x1F*(float32_t)2) + + +/** + * @defgroup I2C_Check_Parameters_Validity I2C Check Parameters Validity + * @{ + */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_I2C1) || \ + ((x) == M4_I2C2) || \ + ((x) == M4_I2C3) || \ + ((x) == M4_I2C4) || \ + ((x) == M4_I2C5) || \ + ((x) == M4_I2C6)) + +#define IS_VALID_MODE(x) \ +( ((x) == I2C_MODE_I2C) || \ + ((x) == I2C_MODE_SMBUS)) + +#define IS_VALID_CLEARBIT(x) ((0U != (x)) && (0U == ((x) & (~I2C_CLR_MASK)))) + +#define IS_VALID_INT(x) ((0U != (x)) && (0U == ((x) & (~I2C_INT_MASK)))) + +#define IS_VALID_SPEED(speed) ((0U != (speed)) && ((speed) <= (I2C_BAUDRATE_MAX))) + +#define IS_VALID_DIGITAL_FILTER(x) ((x) <= I2C_DIG_FILTMODE_4CYCLE) + +#define IS_VALID_RD_STATUS_BIT(x) \ +( ((x) == I2C_SR_STARTF) || \ + ((x) == I2C_SR_SLADDR0F) || \ + ((x) == I2C_SR_SLADDR1F) || \ + ((x) == I2C_SR_TENDF) || \ + ((x) == I2C_SR_STOPF) || \ + ((x) == I2C_SR_RFULLF) || \ + ((x) == I2C_SR_TEMPTYF) || \ + ((x) == I2C_SR_ARLOF) || \ + ((x) == I2C_SR_ACKRF) || \ + ((x) == I2C_SR_NACKF) || \ + ((x) == I2C_SR_TMOUTF) || \ + ((x) == I2C_SR_MSL) || \ + ((x) == I2C_SR_BUSY) || \ + ((x) == I2C_SR_TRA) || \ + ((x) == I2C_SR_GENCALLF) || \ + ((x) == I2C_SR_SMBDEFAULTF) || \ + ((x) == I2C_SR_SMBHOSTF) || \ + ((x) == I2C_SR_SMBALRTF)) + +#define IS_VALID_SMBUS_CONFIG(x) ((0U != (x)) && \ + (0U == ((x) & (~(uint32_t)I2C_SMBUS_CONFIG_CLEARMASK)))) + +#define IS_VALID_7BIT_ADDR(x) ((x) <= 0x7FUL) +#define IS_VALID_10BIT_ADDR(x) ((x) <= 0x3FFUL) + + +#define IS_VALID_ADDR_NUM(x) \ +( ((x) == I2C_ADDR_0) || \ + ((x) == I2C_ADDR_1)) + +#define IS_VALID_CLK_DIV(x) \ +( ((x) == I2C_CLK_DIV1) || \ + ((x) == I2C_CLK_DIV2) || \ + ((x) == I2C_CLK_DIV4) || \ + ((x) == I2C_CLK_DIV8) || \ + ((x) == I2C_CLK_DIV16) || \ + ((x) == I2C_CLK_DIV32) || \ + ((x) == I2C_CLK_DIV64) || \ + ((x) == I2C_CLK_DIV128)) + +#define IS_VALID_DIR(x) \ +( ((x) == I2C_DIR_TX) || \ + ((x) == I2C_DIR_RX)) + +#define IS_VALID_ACK_CONFIG(x) \ +( ((x) == I2C_ACK) || \ + ((x) == I2C_NACK)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32Flags, en_flag_status_t enStatus, uint32_t u32Timeout); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup I2C_Global_Functions I2C Global Functions + * @{ + */ + +/** + * @brief Set the baudrate for I2C peripheral. + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] pstcI2C_InitStruct Pointer to I2C configuration structure + * @ref stc_i2c_init_t + * @arg pstcI2C_InitStruct->u32ClkDiv: Division of Pclk3, reference as: + * step1: calculate div = (Pclk3/Baudrate/(68+2*dnfsum+SclTime) + * Pclk3 -- system clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * step2: chose a division item which is similar and bigger than div + * from @ref I2C_Clock_division. + * @arg pstcI2C_InitStruct->u32Baudrate : Baudrate configuration + * @arg pstcI2C_InitStruct->u32SclTime : Indicate SCL pin rising and + * falling time, should be number of T(i2c clock period time) + * @param [out] pf32Err Baudrate error + * @retval en_result_t + */ +en_result_t I2C_BaudrateConfig(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + en_result_t enRet = Ok; + uint32_t u32Pclk3; + uint32_t I2cDivClk; + uint32_t SclCnt; + uint32_t Baudrate; + uint32_t dnfsum = 0UL; + uint32_t divsum = 2UL; + float32_t WidthTotal; + float32_t SumTotal; + float32_t WidthHL; + float32_t fErr = 0.0F; + + if ((NULL == pstcI2C_InitStruct) || (NULL == pf32Err)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_SPEED(pstcI2C_InitStruct->u32Baudrate)); + DDL_ASSERT(IS_VALID_CLK_DIV(pstcI2C_InitStruct->u32ClkDiv)); + + /* Get configuration for i2c */ + u32Pclk3 = SystemCoreClock >> ((M4_CMU->SCFGR & CMU_SCFGR_PCLK3S) >> CMU_SCFGR_PCLK3S_POS); + I2cDivClk = 1UL << pstcI2C_InitStruct->u32ClkDiv; + SclCnt = pstcI2C_InitStruct->u32SclTime; + Baudrate = pstcI2C_InitStruct->u32Baudrate; + + /* Judge digital filter status*/ + if(0U != READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNFEN)) + { + dnfsum = (READ_REG32_BIT(I2Cx->FLTR, I2C_FLTR_DNF) >> I2C_FLTR_DNF_POS) + 1U; + } + + /* Judge if clock divider on*/ + if(I2C_CLK_DIV1 == I2cDivClk) + { + divsum = 3UL; + } + + WidthTotal = (float32_t)u32Pclk3 / (float32_t)Baudrate / (float32_t)I2cDivClk; + SumTotal = 2.0F*(float32_t)divsum + 2.0F*(float32_t)dnfsum + (float32_t)SclCnt; + WidthHL = WidthTotal - SumTotal; + + if(WidthTotal <= SumTotal) + { + /* Err, Should set a smaller division value for pstcI2C_InitStruct->u32ClkDiv */ + enRet = ErrorInvalidParameter; + } + else if(WidthHL > I2C_SCL_HIGHT_LOW_LVL_SUM_MAX) + { + /* Err, Should set a bigger division value for pstcI2C_InitStruct->u32ClkDiv */ + enRet = ErrorInvalidParameter; + } + else + { + fErr =(WidthHL - (float32_t)((uint32_t)WidthHL)) / WidthHL; + WRITE_REG32(I2Cx->CCR, (pstcI2C_InitStruct->u32ClkDiv << I2C_CCR_FREQ_POS) \ + | (((uint32_t)WidthHL/2U) << I2C_CCR_SLOWW_POS) \ + | (((uint32_t)WidthHL - (uint32_t)WidthHL/2U) << I2C_CCR_SHIGHW_POS)); + } + } + + if((NULL != pf32Err)&&(Ok == enRet)) + { + *pf32Err = fErr; + } + + return enRet; +} + +/** + * @brief De-initialize I2C unit + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @retval None + */ +void I2C_DeInit(M4_I2C_TypeDef* I2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + /* Reset peripheral register and internal status*/ + CLEAR_REG32_BIT(I2Cx->CR1,I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1,I2C_CR1_SWRST); +} + +/** + * @brief Initialize structure stc_i2c_init_t variable with default value. + * @param [out] pstcI2C_InitStruct Pointer to a stc_i2c_init_t structure variable + * which will be initialized. + * @arg See the struct @ref stc_i2c_init_t. + * @retval en_result_t + */ +en_result_t I2C_StructInit(stc_i2c_init_t* pstcI2C_InitStruct) +{ + en_result_t enRet = Ok; + + if (pstcI2C_InitStruct == NULL) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcI2C_InitStruct->u32Baudrate = 50000UL; + pstcI2C_InitStruct->u32ClkDiv = I2C_CLK_DIV1; + pstcI2C_InitStruct->u32SclTime = 0UL; + } + + return enRet; +} + +/** + * @brief Initialize I2C peripheral according to the structure + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] pstcI2C_InitStruct Pointer to I2C configuration structure + * @ref stc_i2c_init_t + * @arg pstcI2C_InitStruct->u32ClkDiv: Division of Pclk3, reference as: + * step1: calculate div = (Pclk3/Baudrate/(68+2*dnfsum+SclTime) + * Pclk3 -- system clock + * Baudrate -- baudrate of i2c + * SclTime -- =(SCL rising time + SCL falling time)/period of i2c clock + * according to i2c bus hardware parameter. + * dnfsum -- 0 if digital filter off; + * Filter capacity if digital filter on(1 ~ 4) + * step2: chose a division item which is similar and bigger than div + * from @ref I2C_Clock_division. + * @arg pstcI2C_InitStruct->u32Baudrate : Baudrate configuration + * @arg pstcI2C_InitStruct->u32SclTime : Indicate SCL pin rising and + * falling time, should be number of T(i2c clock period time) + * @param [out] pf32Err Baudrate error + * @retval en_result_t + */ +en_result_t I2C_Init(M4_I2C_TypeDef* I2Cx, const stc_i2c_init_t *pstcI2C_InitStruct, float32_t *pf32Err) +{ + en_result_t enRet; + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + if (NULL == pstcI2C_InitStruct ) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_VALID_SPEED(pstcI2C_InitStruct->u32Baudrate)); + DDL_ASSERT(IS_VALID_CLK_DIV(pstcI2C_InitStruct->u32ClkDiv)); + + /* Register and internal status reset */ + CLEAR_REG32_BIT(I2Cx->CR1,I2C_CR1_PE); + SET_REG32_BIT(I2Cx->CR1,I2C_CR1_SWRST); + SET_REG32_BIT(I2Cx->CR1,I2C_CR1_PE); + + /* I2C baudrate config */ + enRet = I2C_BaudrateConfig(I2Cx, pstcI2C_InitStruct, pf32Err); + + if(enRet == Ok) + { + /* Disable global broadcast address function */ + CLEAR_REG32_BIT(I2Cx->CR1,I2C_CR1_ENGC); + + /* Release software reset */ + CLEAR_REG32_BIT(I2Cx->CR1,I2C_CR1_SWRST); + /* Disable I2C peripheral */ + CLEAR_REG32_BIT(I2Cx->CR1,I2C_CR1_PE); + } + } + + return enRet; +} + +/** + * @brief Enable or disable the specified I2C slave address function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * This parameter can be one of the following values: + * @arg I2C_ADDR_0 + * @arg I2C_ADDR_1 + * @param [in] enNewState New state of the I2Cx function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_SlaveAddrCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_ADDR_NUM(u32AddrNum)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + __IO uint32_t* pu32SLRx = (__IO uint32_t*)((uint32_t)&I2Cx->SLR0 + u32AddrNum * 4UL); + + if(Enable == enNewState) + { + SET_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN); + } + else + { + CLEAR_REG32_BIT(*pu32SLRx, I2C_SLR0_SLADDR0EN); + } +} + +/** + * @brief I2C slave address config + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32AddrNum I2C address 0 or address 1 @ref I2C_Address_Num + * This parameter can be one of the following values: + * @arg I2C_ADDR_0 + * @arg I2C_ADDR_1 + * @param [in] u32AddrMode Address mode configuration,@ref I2C_Addr_Config + * This parameter can be one of the following values: + * @arg I2C_ADDR_MODE_7BIT + * @arg I2C_ADDR_MODE_10BIT + * @param [in] u32Addr The slave address + * @retval None + */ +void I2C_SlaveAddrConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AddrNum, uint32_t u32AddrMode, uint32_t u32Addr) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_ADDR_NUM(u32AddrNum)); + + + __IO uint32_t* pu32SLRx = (__IO uint32_t*)((uint32_t)&I2Cx->SLR0 + u32AddrNum * 4UL); + + if(I2C_ADDR_MODE_10BIT == u32AddrMode) + { + DDL_ASSERT(IS_VALID_10BIT_ADDR(u32Addr)); + MODIFY_REG32(*pu32SLRx, I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0, u32AddrMode + u32Addr); + } + else + { + DDL_ASSERT(IS_VALID_7BIT_ADDR(u32Addr)); + MODIFY_REG32(*pu32SLRx, I2C_SLR0_ADDRMOD0 | I2C_SLR0_SLADDR0, u32AddrMode + (u32Addr << 1)); + } +} + +/** + * @brief Configure peripheral mode + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32Mode This parameter can be one of the following values: + * @arg I2C_MODE_I2C + * @arg I2C_MODE_SMBUS + * @retval None + */ +void I2C_SetMode(M4_I2C_TypeDef* I2Cx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_MODE(u32Mode)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SMBUS, u32Mode); +} + +/** + * @brief Enable or disable the specified I2C peripheral + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2Cx function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_Cmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_PE, (uint32_t)enNewState << I2C_CR1_PE_POS); +} + +/** + * @brief Enable or disable the I2C fast ack function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the fast ACK function, can be + * Disable or Enable the function + * @retval None + */ +void I2C_FastAckCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + CLEAR_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } + else + { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + } +} + +/** + * @brief Enable or disable the bus wait function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the bus wait function, can be + * Disable or Enable the function + * @retval None + */ +void I2C_BusWaitCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + uint32_t u32CR4_Reg = ((uint32_t)&I2Cx->CR3) + 4UL; + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + *(__IO uint32_t *)u32CR4_Reg |= (1UL << 10UL); + } + else + { + *(__IO uint32_t *)u32CR4_Reg &= ~(1UL << 10UL); + } +} + +/** + * @brief I2C SCL high level timeout configuration + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u16TimeoutH clock timeout period for high level + * @retval None + */ +void I2C_ClkHighTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutH) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + CLEAR_REG32_BIT(I2Cx->SLTR, I2C_SLTR_TOUTHIGH); + SET_REG32_BIT(I2Cx->SLTR, ((uint32_t)u16TimeoutH << 16U)); +} + +/** + * @brief I2C SCL low level timeout configuration + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u16TimeoutL clock timeout period for low level + * @retval None + */ +void I2C_ClkLowTimeoutConfig(M4_I2C_TypeDef* I2Cx, uint16_t u16TimeoutL) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + CLEAR_REG32_BIT(I2Cx->SLTR, I2C_SLTR_TOUTLOW); + SET_REG32_BIT(I2Cx->SLTR, u16TimeoutL); +} + +/** + * @brief Enable or disable I2C SCL high level timeout function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2C SCL high level timeout function, + * can be Disable or Enable the function + * @retval None + */ +void I2C_ClkHighTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } + else + { + CLEAR_REG32_BIT(I2Cx->CR3, I2C_CR3_HTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL low level timeout function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2C SCL low level timeout function + * can be Disable or Enable the function + * @retval None + */ +void I2C_ClkLowTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } + else + { + CLEAR_REG32_BIT(I2Cx->CR3, I2C_CR3_LTMOUT); + } +} + +/** + * @brief Enable or disable I2C SCL timeout function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2C SCL timeout function, can be + * Disable or Enable the function + * @retval None + */ +void I2C_ClkTimeoutCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } + else + { + CLEAR_REG32_BIT(I2Cx->CR3, I2C_CR3_TMOUTEN); + } +} + +/** + * @brief Config I2C SMBUS address match function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32SmbusConfig Indicate the SMBUS address match function configuration. + * This parameter can be one or any combination of the following values: + * @ref I2C_Smbus_Match_Cfg + * @arg I2C_SMBUS_MATCH_ALRT : Smbus alarm address + * @arg I2C_SMBUS_MATCH_DEFAULT : Smbus default address + * @arg I2C_SMBUS_MATCH_HOST : Smbus host address address + * @param [in] enNewState New state of the I2Cx SMBUS match config, + * @ref en_functional_state_t + * @retval None + */ +void I2C_SmbusConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32SmbusConfig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_SMBUS_CONFIG(u32SmbusConfig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } + else + { + CLEAR_REG32_BIT(I2Cx->CR1, u32SmbusConfig); + } +} + +/** + * @brief Config I2C digital filter mode + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32DigFilterMode Chose the digital filter mode, + * @ref I2C_Digital_Filter_mode + * This parameter can be one of the following values: + * @arg I2C_DIG_FILTMODE_1CYCLE + * @arg I2C_DIG_FILTMODE_2CYCLE + * @arg I2C_DIG_FILTMODE_3CYCLE + * @arg I2C_DIG_FILTMODE_4CYCLE + * @retval None + */ +void I2C_DigitalFilterConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32DigFilterMode) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_DIGITAL_FILTER(u32DigFilterMode)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNF, u32DigFilterMode); +} + +/** + * @brief Enable or disable I2C digital filter function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2Cx function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_DigitalFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_DNFEN, (uint32_t)enNewState << I2C_FLTR_DNFEN_POS); +} + +/** + * @brief Enable or disable I2C analog filter function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2Cx function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_AnalogFilterCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->FLTR, I2C_FLTR_ANFEN, (uint32_t)enNewState << I2C_FLTR_ANFEN_POS); +} + +/** + * @brief Enable or disable I2C general call function + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2Cx function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_GeneralCallCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ENGC, (uint32_t)enNewState << I2C_CR1_ENGC_POS); +} + +/** + * @brief Generate I2Cx communication start condition + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @retval None + */ +void I2C_GenerateStart(M4_I2C_TypeDef* I2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_START); +} + +/** + * @brief Generate I2Cx communication restart condition + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @retval None + */ +void I2C_GenerateReStart(M4_I2C_TypeDef* I2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_RESTART); +} + +/** + * @brief Generate I2Cx communication stop condition + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @retval None + */ +void I2C_GenerateStop(M4_I2C_TypeDef* I2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + SET_REG32_BIT(I2Cx->CR1, I2C_CR1_STOP); +} + +/** + * @brief Check whether the specified I2C flag is set or not + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32StatusBit specify the flag to check, + * This parameter can be one of the following values: + * @arg I2C_SR_STARTF : Start condition detected flag + * @arg I2C_SR_SLADDR0F : Address 0 detected flag + * @arg I2C_SR_SLADDR1F : Address 1 detected flag + * @arg I2C_SR_TENDF : Transfer end flag + * @arg I2C_SR_STOPF : Stop condition detected flag + * @arg I2C_SR_RFULLF : Receive buffer full flag + * @arg I2C_SR_TEMPTYF : Transfer buffer empty flag + * @arg I2C_SR_ARLOF : Arbitration fails flag + * @arg I2C_SR_ACKRF : ACK detected flag + * @arg I2C_SR_NACKF : NACK detected flag + * @arg I2C_SR_TMOUTF : Time out detected flag + * @arg I2C_SR_MSL : Master mode flag + * @arg I2C_SR_BUSY : Bus busy status flag + * @arg I2C_SR_TRA : Transfer mode flag + * @arg I2C_SR_GENCALLF : General call detected flag + * @arg I2C_SR_SMBDEFAULTF: Smbus default address detected flag + * @arg I2C_SR_SMBHOSTF : Smbus host address detected flag + * @arg I2C_SR_SMBALRTF : Smbus alarm address detected flag + * @retval The status of the I2C status flag, may be Set or Reset. + */ +en_flag_status_t I2C_GetStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32StatusBit) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_RD_STATUS_BIT(u32StatusBit)); + + return ((0UL != READ_REG32_BIT(I2Cx->SR, u32StatusBit)) ? Set : Reset); +} + +/** + * @brief Clear I2C status flag + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32StatusBit Specify the flag to clear, + * This parameter can be any combination of the following values: + * @arg I2C_CLR_STARTFCLR : Start flag clear + * @arg I2C_CLR_SLADDR0FCLR : Address 0 detected flag clear + * @arg I2C_CLR_SLADDR1FCLR : Address 1 detected flag clear + * @arg I2C_CLR_TENDFCLR : Transfer end flag clear + * @arg I2C_CLR_STOPFCLR : Stop flag clear + * @arg I2C_CLR_RFULLFCLR : Receive buffer full flag clear + * @arg I2C_CLR_TEMPTYFCLR : Transfer buffer empty flag clear + * @arg I2C_CLR_ARLOFCLR : Arbitration fails flag clear + * @arg I2C_CLR_NACKFCLR : NACK detected flag clear + * @arg I2C_CLR_TMOUTFCLR : Time out detected flag clear + * @arg I2C_CLR_GENCALLFCLR : General call address detected flag clear + * @arg I2C_CLR_SMBDEFAULTFCLR: Smbus default address detected flag clear + * @arg I2C_CLR_SMBHOSTFCLR : Smbus host address detected flag clear + * @arg I2C_CLR_SMBALRTFCLR : Smbus alarm address detected flag clear + * @retval None + */ +void I2C_ClearStatus(M4_I2C_TypeDef* I2Cx, uint32_t u32StatusBit) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_CLEARBIT(u32StatusBit)); + + WRITE_REG32(I2Cx->CLR,u32StatusBit); +} + +/** + * @brief I2C software reset function command + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] enNewState New state of the I2Cx function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_SoftwareResetCmd(M4_I2C_TypeDef* I2Cx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_SWRST, (uint32_t)enNewState << I2C_CR1_SWRST_POS); +} + +/** + * @brief Enable or disable the specified I2C interrupts + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32IntEn Specify the I2C interrupts sources to be configuration. + * This parameter can be any combination of the following values: + * @arg I2C_CR2_STARTIE : Start flag interrupt + * @arg I2C_CR2_SLADDR0IE : Address 0 detected interrupt + * @arg I2C_CR2_SLADDR1IE : Address 1 detected interrupt + * @arg I2C_CR2_TENDIE : Transfer end interrupt + * @arg I2C_CR2_STOPIE : Stop flag interrupt + * @arg I2C_CR2_RFULLIE : Receive buffer full interrupt + * @arg I2C_CR2_TEMPTYIE : Transfer buffer empty interrupt + * @arg I2C_CR2_ARLOIE : Arbitration fails interrupt + * @arg I2C_CR2_NACKIE : NACK flag detected interrupt + * @arg I2C_CR2_TMOUTIE : Time out detected interrupt + * @arg I2C_CR2_GENCALLIE : General call address detected interrupt + * @arg I2C_CR2_SMBDEFAULTIE : Smbus default address detected interrupt + * @arg I2C_CR2_SMBHOSTIE : Smbus host address detected interrupt + * @arg I2C_CR2_SMBALRTIE : Smbus alarm address detected interrupt + * @param [in] enNewState New state of the I2Cx interrupt function, + * @ref en_functional_state_t + * @retval None + */ +void I2C_IntCmd(M4_I2C_TypeDef* I2Cx, uint32_t u32IntEn, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_INT(u32IntEn)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(I2Cx->CR2, u32IntEn); + } + else + { + CLEAR_REG32_BIT(I2Cx->CR2, u32IntEn); + } +} + +/** + * @brief Send data byte + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u8Data The data to be send + * @retval None + */ +void I2C_WriteDataReg(M4_I2C_TypeDef* I2Cx, uint8_t u8Data) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + WRITE_REG8(I2Cx->DTR, u8Data); +} + +/** + * @brief Read the most recent received data byte + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @retval The value of the received data + */ +uint8_t I2C_ReadDataReg(const M4_I2C_TypeDef *I2Cx) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + return READ_REG8(I2Cx->DRR); +} + +/** + * @brief Config I2C ACK status + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32AckConfig Ack configuration + * This parameter can be one of the following values: + * @arg I2C_ACK + * @arg I2C_NACK + * @retval None + */ +void I2C_AckConfig(M4_I2C_TypeDef* I2Cx, uint32_t u32AckConfig) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_ACK_CONFIG(u32AckConfig)); + + MODIFY_REG32(I2Cx->CR1, I2C_CR1_ACK, u32AckConfig); +} + +/** + * @brief I2Cx Start + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Start successfully + * - Error: Start unsuccessfully + */ +en_result_t I2C_Start(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + en_result_t enRet; + + enRet = I2C_WaitStatus(I2Cx, I2C_SR_BUSY, Reset, u32Timeout); + + if(Ok == enRet) + { + /* generate start signal */ + I2C_GenerateStart(I2Cx); + /* Judge if start success*/ + enRet = I2C_WaitStatus(I2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + } + + return enRet; +} + +/** + * @brief I2Cx Restart + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Restart successfully + * - Error: Restart unsuccessfully + */ +en_result_t I2C_Restart(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + en_result_t enRet; + + /* Clear start status flag */ + I2C_ClearStatus(I2Cx, I2C_CLR_STARTFCLR); + /* Send restart condition */ + I2C_GenerateReStart(I2Cx); + /* Judge if start success*/ + enRet = I2C_WaitStatus(I2Cx, (I2C_SR_BUSY | I2C_SR_STARTF), Set, u32Timeout); + + return enRet; +} + +/** + * @brief Send 7bit address + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u8Addr The address to be sent + * @param [in] u8Dir Transfer direction, + * This parameter can be one of the following values: + * @arg I2C_DIR_TX + * @arg I2C_DIR_RX + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Send successfully + * - Error: Send unsuccessfully or NACK received + */ +en_result_t I2C_TransAddr(M4_I2C_TypeDef* I2Cx, uint8_t u8Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_7BIT_ADDR(u8Addr)); + DDL_ASSERT(IS_VALID_DIR(u8Dir)); + + en_result_t enRet; + + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Send I2C address */ + I2C_WriteDataReg(I2Cx, (uint8_t)(u8Addr << 1U) | u8Dir); + + if(I2C_DIR_TX == u8Dir) + { + /* If in master transfer process, wait transfer end */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TENDF, Set, u32Timeout); + } + else + { + /* If in master recevie process, wait I2C_SR_TRA changed to recevie */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TRA, Reset, u32Timeout); + } + + /* If receive NACK*/ + if(enRet == Ok) + { + if(I2C_GetStatus(I2Cx, I2C_SR_ACKRF) == Set) + { + enRet = Error; + } + } + } + + return enRet; +} + + +/** +* @brief Send 10bit Address +* @param [in] I2Cx Pointer to the I2C peripheral register +* This parameter can be one of the following values: +* @arg M4_I2C1 +* @arg M4_I2C2 +* @arg M4_I2C3 +* @arg M4_I2C4 +* @arg M4_I2C5 +* @arg M4_I2C6 +* @param [in] u16Addr The address to be sent +* @param [in] u8Dir Transfer direction, +* This parameter can be one of the following values: +* @arg I2C_DIR_TX +* @arg I2C_DIR_RX +* @param [in] u32Timeout Maximum count of trying to get a status of a +* flag in status register +* @retval An en_result_t enumeration value: +* - Ok: Send successfully +* - Error: Send unsuccessfully or NACK received +*/ +en_result_t I2C_Trans10BitAddr(M4_I2C_TypeDef* I2Cx, uint16_t u16Addr, uint8_t u8Dir, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + DDL_ASSERT(IS_VALID_10BIT_ADDR(u16Addr)); + DDL_ASSERT(IS_VALID_DIR(u8Dir)); + + en_result_t enRet; + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + W#(1bit) */ + I2C_WriteDataReg(I2Cx, (uint8_t)((u16Addr>>7U) & 0x06U) | 0xF0U | I2C_DIR_TX); + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + /* If receive ACK */ + if(I2C_GetStatus(I2Cx, I2C_SR_ACKRF) == Reset) + { + /* Write SLA(bit7:0)*/ + I2C_WriteDataReg(I2Cx, (uint8_t)(u16Addr & 0xFFU)); + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TENDF, Set, u32Timeout); + + if(Ok == enRet) + { + if(I2C_GetStatus(I2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + else + { + enRet = Error; + } + } + } + + if((u8Dir == I2C_DIR_RX) && (Ok == enRet)) + { + /* Restart */ + I2C_ClearStatus(I2Cx, I2C_CLR_STARTFCLR); + I2C_GenerateReStart(I2Cx); + enRet = I2C_WaitStatus(I2Cx, I2C_SR_STARTF, Set, u32Timeout); + + if(Ok == enRet) + { + /* Write 11110 + SLA(bit9:8) + R(1bit) */ + I2C_WriteDataReg(I2Cx, (uint8_t)((u16Addr>>7U) & 0x06U) | 0xF0U | I2C_DIR_RX); + /* If in master receive process, Need wait TRA flag */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TRA, Reset, u32Timeout); + + if(Ok == enRet) + { + /* If receive NACK */ + if(I2C_GetStatus(I2Cx, I2C_SR_ACKRF) != Reset) + { + enRet = Error; + } + } + } + } + + return enRet; +} + +/** + * @brief Send data bytes + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] pau8TxData The data array to be sent + * @param [in] u32Size Number of data in array pau8TxData + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Send successfully + * - Error: Send unsuccessfully or NACK received + * - ErrorInvalidParameter: pau8TxData is NULL + */ +en_result_t I2C_TransData(M4_I2C_TypeDef* I2Cx, uint8_t const pau8TxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + en_result_t enRet = Ok; + uint32_t u32Cnt = 0UL; + + if(pau8TxData != NULL) + { + while((u32Cnt != u32Size) &&(enRet == Ok)) + { + /* Wait tx buffer empty */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TEMPTYF, Set, u32Timeout); + + if(enRet == Ok) + { + /* Send one byte data */ + I2C_WriteDataReg(I2Cx, pau8TxData[u32Cnt]); + /* Wait transfer end */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_TENDF, Set, u32Timeout); + + /* If receive NACK*/ + if(I2C_GetStatus(I2Cx, I2C_SR_ACKRF) == Set) + { + break; + } + u32Cnt++; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + * @brief I2Cx Receive Data + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [out] pau8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Receive successfully + * - Error: Receive unsuccessfully + * - ErrorInvalidParameter: pau8RxData is NULL + */ +en_result_t I2C_Receive(M4_I2C_TypeDef* I2Cx, uint8_t pau8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + en_result_t enRet = Ok; + + if(pau8RxData != NULL) + { + uint32_t u32FastAckEn = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + for(uint32_t i=0UL; i= 2UL) && (i == (u32Size - 2UL))) + { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + else + { + if(i != (u32Size - 1UL)) + { + I2C_AckConfig(I2Cx, I2C_ACK); + } + else + { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if(enRet == Ok) + { + /* read data from register */ + pau8RxData[i] = I2C_ReadDataReg(I2Cx); + } + else + { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + * @brief Master receive data and stop + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] au8RxData Array to hold the received data + * @param [in] u32Size Number of data to be received + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Receive successfully + * - Error: Receive or Stop unsuccessfully + * - ErrorInvalidParameter: au8RxData is NULL + */ +en_result_t I2C_MasterReceiveAndStop(M4_I2C_TypeDef* I2Cx, uint8_t au8RxData[], uint32_t u32Size, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + if(au8RxData != NULL) + { + uint32_t u32FastAckEn = READ_REG32_BIT(I2Cx->CR3, I2C_CR3_FACKEN); + for(uint32_t i=0UL; i= 2UL) && (i == (u32Size - 2UL))) + { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + else + { + if(i != (u32Size - 1UL)) + { + I2C_AckConfig(I2Cx, I2C_ACK); + } + else + { + I2C_AckConfig(I2Cx, I2C_NACK); + } + } + + if(enRet == Ok) + { + /* Stop before read last data */ + if(i == (u32Size - 1UL)) + { + I2C_ClearStatus(I2Cx, I2C_SR_STOPF); + I2C_GenerateStop(I2Cx); + } + + /* read data from register */ + au8RxData[i] = I2C_ReadDataReg(I2Cx); + + if(i == (u32Size - 1UL)) + { + /* Wait stop flag after DRR read */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_STOPF, Set, u32Timeout); + } + } + else + { + break; + } + } + I2C_AckConfig(I2Cx, I2C_ACK); + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + + +/** + * @brief I2Cx Stop + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval An en_result_t enumeration value: + * - Ok: Stop successfully + * - Error: Stop unsuccessfully + */ +en_result_t I2C_Stop(M4_I2C_TypeDef* I2Cx, uint32_t u32Timeout) +{ + en_result_t enRet; + + DDL_ASSERT(IS_VALID_UNIT(I2Cx)); + + /* Clear stop flag */ + while((Set == I2C_GetStatus(I2Cx, I2C_SR_STOPF)) && (u32Timeout > 0UL)) + { + I2C_ClearStatus(I2Cx, I2C_CLR_STOPFCLR); + u32Timeout--; + } + I2C_GenerateStop(I2Cx); + /* Wait stop flag */ + enRet = I2C_WaitStatus(I2Cx, I2C_SR_STOPF, Set, u32Timeout); + + return enRet; +} +/** + * @} + */ + +/** +* @defgroup I2C_Local_Functions I2C Local Functions +* @{ +*/ + +/** + * @brief Try to wait a status of specified flags + * @param [in] I2Cx Pointer to the I2C peripheral register. + * This parameter can be one of the following values: + * @arg M4_I2C1 + * @arg M4_I2C2 + * @arg M4_I2C3 + * @arg M4_I2C4 + * @arg M4_I2C5 + * @arg M4_I2C6 + * @param [in] u32Flags specify the flags to check + * @param [in] enStatus expected status, + * This parameter can be any combination of the following values: + * @arg I2C_SR_STARTF : Start condition detected flag + * @arg I2C_SR_SLADDR0F : Address 0 detected flag + * @arg I2C_SR_SLADDR1F : Address 1 detected flag + * @arg I2C_SR_TENDF : Transfer end flag + * @arg I2C_SR_STOPF : Stop condition detected flag + * @arg I2C_SR_RFULLF : Receive buffer full flag + * @arg I2C_SR_TEMPTYF : Transfer buffer empty flag + * @arg I2C_SR_ARLOF : Arbitration fails flag + * @arg I2C_SR_ACKRF : ACK detected flag + * @arg I2C_SR_NACKF : NACK detected flag + * @arg I2C_SR_TMOUTF : Time out detected flag + * @arg I2C_SR_MSL : Master mode flag + * @arg I2C_SR_BUSY : Bus busy status flag + * @arg I2C_SR_TRA : Transfer mode flag + * @arg I2C_SR_GENCALLF : General call detected flag + * @arg I2C_SR_SMBDEFAULTF: Smbus default address detected flag + * @arg I2C_SR_SMBHOSTF : Smbus host address detected flag + * @arg I2C_SR_SMBALRTF : Smbus alarm address detected flag + * @param [in] u32Timeout Maximum count of trying to get a status of a + * flag in status register + * @retval Process result + * - Error Failed to get expected status of specified flags + * - Ok successfully gotten the expected status of the specified flags + */ +static en_result_t I2C_WaitStatus(const M4_I2C_TypeDef *I2Cx, uint32_t u32Flags, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + en_result_t enRet = Error; + uint32_t u32RegStatusBit; + + for(;;) + { + u32RegStatusBit = (READ_REG32_BIT(I2Cx->SR, u32Flags)); + if(((enStatus == Set) && (u32Flags == u32RegStatusBit)) + || ((enStatus == Reset) && (0UL == u32RegStatusBit))) + { + enRet = Ok; + } + + if((Ok == enRet) || (0UL == u32Timeout)) + { + break; + } + else + { + u32Timeout--; + } + } + + return enRet; +} + +/** +* @} +*/ + +#endif /* DDL_I2C_ENABLE */ + +/** +* @} +*/ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2s.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2s.c new file mode 100644 index 0000000000000000000000000000000000000000..79b18dc2429f420565bd35c7f48eb229639e8274 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2s.c @@ -0,0 +1,1184 @@ +/** + ******************************************************************************* + * @file hc32f4a0_i2s.c + * @brief This file provides firmware functions to manage the Inter IC Sound Bus + * (I2S). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_i2s.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_I2S I2S + * @brief Inter IC Sound Bus Driver Library + * @{ + */ + +#if (DDL_I2S_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup I2S_Local_Macros I2S Local Macros + * @{ + */ + +/* I2S CTRL register Mask */ +#define I2S_CTRL_CLEAR_MASK (I2S_CTRL_WMS | I2S_CTRL_ODD | I2S_CTRL_MCKOE | \ + I2S_CTRL_TXBIRQWL | I2S_CTRL_RXBIRQWL | I2S_CTRL_I2SPLLSEL | \ + I2S_CTRL_SDOE | I2S_CTRL_LRCKOE | I2S_CTRL_CKOE | \ + I2S_CTRL_DUPLEX | I2S_CTRL_CLKSEL) + +/** + * @defgroup I2S_Check_Parameters_Validity I2S Check Parameters Validity + * @{ + */ +#define IS_I2S_UNIT(x) \ +( ((x) == M4_I2S1) || \ + ((x) == M4_I2S2) || \ + ((x) == M4_I2S3) || \ + ((x) == M4_I2S4)) + +#define IS_I2S_CLK_SRC(x) \ +( ((x) == I2S_CLK_SRC_PLL) || \ + ((x) == I2S_CLK_SRC_EXT)) + +#define IS_I2S_MD(x) \ +( ((x) == I2S_MD_MASTER) || \ + ((x) == I2S_MD_SLAVE)) + +#define IS_I2S_COM_PROTOCOL(x) \ +( ((x) == I2S_COM_PROTOCOL_PHILLIPS) || \ + ((x) == I2S_COM_PROTOCOL_MSB) || \ + ((x) == I2S_COM_PROTOCOL_LSB) || \ + ((x) == I2S_COM_PROTOCOL_PCM_SHORT) || \ + ((x) == I2S_COM_PROTOCOL_PCM_LONG)) + +#define IS_I2S_TRANS_MD(x) \ +( ((x) == I2S_TRANS_MD_HALF_DUPLEX_RX) || \ + ((x) == I2S_TRANS_MD_HALF_DUPLEX_TX) || \ + ((x) == I2S_TRANS_MD_FULL_DUPLEX)) + +#define IS_I2S_AUDIO_FREQ(x) \ +( ((x) == I2S_AUDIO_FREQ_DEFAULT) || \ + (((x) >= I2S_AUDIO_FREQ_8K) && ((x) <= I2S_AUDIO_FREQ_192K))) + +#define IS_I2S_CH_LEN(x) \ +( ((x) == I2S_CH_LEN_16BIT) || \ + ((x) == I2S_CH_LEN_32BIT)) + +#define IS_I2S_DATA_LEN(x) \ +( ((x) == I2S_DATA_LEN_16BIT) || \ + ((x) == I2S_DATA_LEN_24BIT) || \ + ((x) == I2S_DATA_LEN_32BIT)) + +#define IS_I2S_MCK_OUTPUT(x) \ +( ((x) == I2S_MCK_OUTPUT_DISABLE) || \ + ((x) == I2S_MCK_OUTPUT_ENABLE)) + +#define IS_I2S_TRANS_LVL(x) \ +( ((x) == I2S_TRANS_LVL0) || \ + ((x) == I2S_TRANS_LVL1) || \ + ((x) == I2S_TRANS_LVL2) || \ + ((x) == I2S_TRANS_LVL3) || \ + ((x) == I2S_TRANS_LVL4)) + +#define IS_I2S_RECEIVE_LVL(x) \ +( ((x) == I2S_RECEIVE_LVL0) || \ + ((x) == I2S_RECEIVE_LVL1) || \ + ((x) == I2S_RECEIVE_LVL2) || \ + ((x) == I2S_RECEIVE_LVL3) || \ + ((x) == I2S_RECEIVE_LVL4)) + +#define IS_I2S_FUNC(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FUNC_ALL) == I2S_FUNC_ALL)) + +#define IS_I2S_RST_TYPE(x) \ +( ((x) != 0U) && \ + (((x) | I2S_RST_TYPE_ALL) == I2S_RST_TYPE_ALL)) + +#define IS_I2S_INT(x) \ +( ((x) != 0U) && \ + (((x) | I2S_INT_ALL) == I2S_INT_ALL)) + +#define IS_I2S_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_FLAG_ALL) == I2S_FLAG_ALL)) + +#define IS_I2S_CLR_FLAG(x) \ +( ((x) != 0U) && \ + (((x) | I2S_CLR_FLAG_ALL) == I2S_CLR_FLAG_ALL)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static uint32_t I2S_GetClockFreq(const M4_I2S_TypeDef *I2Sx); +static en_result_t I2S_WaitStatus(const M4_I2S_TypeDef *I2Sx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup I2S_Global_Functions I2S Global Functions + * @{ + */ + +/** + * @brief De-Initialize I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @retval None + */ +void I2S_DeInit(M4_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + /* Reset all registers of I2S */ + WRITE_REG32(I2Sx->CTRL, 0x00004400UL); + WRITE_REG32(I2Sx->ER, 0x00000003UL); + WRITE_REG32(I2Sx->CFGR, 0x00000000UL); + WRITE_REG32(I2Sx->PR, 0x00000002UL); + SET_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); + CLEAR_REG32_BIT(I2Sx->CTRL, I2S_RST_TYPE_ALL); +} + +/** + * @brief Initialize I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + * - Error: Initialize failed + */ +en_result_t I2S_Init(M4_I2S_TypeDef *I2Sx, const stc_i2s_init_t *pstcI2sInit) +{ + en_result_t enRet = Ok; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChLen; + + if (NULL == pstcI2sInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLK_SRC(pstcI2sInit->u32ClockSrc)); + DDL_ASSERT(IS_I2S_MD(pstcI2sInit->u32Mode)); + DDL_ASSERT(IS_I2S_COM_PROTOCOL(pstcI2sInit->u32ComProtocol)); + DDL_ASSERT(IS_I2S_TRANS_MD(pstcI2sInit->u32TransMode)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(pstcI2sInit->u32AudioFreq)); + DDL_ASSERT(IS_I2S_CH_LEN(pstcI2sInit->u32ChLen)); + DDL_ASSERT(IS_I2S_DATA_LEN(pstcI2sInit->u32DataLen)); + DDL_ASSERT(IS_I2S_MCK_OUTPUT(pstcI2sInit->u32MCKOutput)); + DDL_ASSERT(IS_I2S_TRANS_LVL(pstcI2sInit->u32TransFIFOLevel)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(pstcI2sInit->u32ReceiveFIFOLevel)); + + if (I2S_AUDIO_FREQ_DEFAULT != pstcI2sInit->u32AudioFreq) + { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == pstcI2sInit->u32ClockSrc) + { + /* If an external I2S clock has to be used, this define + should be set in the ddl_config.h file */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } + else + { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChLen) + { + u32ChLen = 32UL; + } + else + { + u32ChLen = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == pstcI2sInit->u32MCKOutput) + { + if (I2S_CH_LEN_16BIT != pstcI2sInit->u32ChLen) + { + u32Temp = (((u32I2sClk / (u32ChLen*2U * 4U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + else + { + u32Temp = (((u32I2sClk / (u32ChLen*2U * 8U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + } + else + { + u32Temp = (((u32I2sClk / (u32ChLen*2U)) * 10U) / pstcI2sInit->u32AudioFreq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) + { + /* Set the default values */ + u32I2sOdd = 0U; + u32I2sDiv = 2U; + enRet = Error; + } + + u32Temp = pstcI2sInit->u32ClockSrc | pstcI2sInit->u32Mode | + pstcI2sInit->u32ComProtocol | pstcI2sInit->u32TransMode | + pstcI2sInit->u32ChLen | pstcI2sInit->u32DataLen | + pstcI2sInit->u32MCKOutput | pstcI2sInit->u32TransFIFOLevel | + pstcI2sInit->u32ReceiveFIFOLevel | (u32I2sOdd << I2S_CTRL_ODD_POS); + if (I2S_MD_MASTER == pstcI2sInit->u32Mode) + { + u32Temp |= (I2S_CTRL_CKOE | I2S_CTRL_LRCKOE); + } + /* Set I2S_CFGR register */ + WRITE_REG32(I2Sx->CFGR, (pstcI2sInit->u32ComProtocol | pstcI2sInit->u32ChLen | pstcI2sInit->u32DataLen)); + /* set I2S_PR register */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + /* Set I2S_CTRL register */ + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_CLEAR_MASK, u32Temp); + } + + return enRet; +} + +/** + * @brief Fills each stc_i2s_init_t member with default value. + * @param [out] pstcI2sInit Pointer to a @ref stc_i2s_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: stc_i2s_init_t member initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t I2S_StructInit(stc_i2s_init_t *pstcI2sInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcI2sInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcI2sInit->u32ClockSrc = I2S_CLK_SRC_PLL; + pstcI2sInit->u32Mode = I2S_MD_MASTER; + pstcI2sInit->u32ComProtocol = I2S_COM_PROTOCOL_PHILLIPS; + pstcI2sInit->u32TransMode = I2S_TRANS_MD_HALF_DUPLEX_RX; + pstcI2sInit->u32AudioFreq = I2S_AUDIO_FREQ_DEFAULT; + pstcI2sInit->u32ChLen = I2S_CH_LEN_16BIT; + pstcI2sInit->u32DataLen = I2S_DATA_LEN_16BIT; + pstcI2sInit->u32MCKOutput = I2S_MCK_OUTPUT_DISABLE; + pstcI2sInit->u32TransFIFOLevel = I2S_TRANS_LVL2; + pstcI2sInit->u32ReceiveFIFOLevel = I2S_RECEIVE_LVL2; + } + + return enRet; +} + +/** + * @brief Set the software reset of I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32ResetType Software reset type + * This parameter can be one or any combination of the following values: + * @arg I2S_RST_TYPE_SW: I2S software reset + * @arg I2S_RST_TYPE_CODEC: Reset codec of I2S + * @arg I2S_RST_TYPE_FIFO: Reset FIFO of I2S + * @arg I2S_RST_TYPE_ALL: All of the above + * @retval None + */ +void I2S_SetSWReset(M4_I2S_TypeDef *I2Sx, uint32_t u32ResetType) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RST_TYPE(u32ResetType)); + + SET_REG32_BIT(I2Sx->CTRL, u32ResetType); + CLEAR_REG32_BIT(I2Sx->CTRL, u32ResetType); +} + +/** + * @brief Set the transfer mode for the I2S communication. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Mode Transfer mode + * This parameter can be one of the following values: + * @arg I2S_TRANS_MD_HALF_DUPLEX_RX: Receive only and half duplex mode + * @arg I2S_TRANS_MD_HALF_DUPLEX_TX: Send only and half duplex mode + * @arg I2S_TRANS_MD_FULL_DUPLEX: Full duplex mode + * @retval None + */ +void I2S_SetTransMode(M4_I2S_TypeDef *I2Sx, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_MD(u32Mode)); + + MODIFY_REG32(I2Sx->CTRL, (I2S_CTRL_DUPLEX | I2S_CTRL_SDOE), u32Mode); +} + +/** + * @brief Set the transfer FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Level Transfer FIFO level + * This parameter can be one of the following values: + * @arg I2S_TRANS_LVL0: Transfer FIFO level is 0 + * @arg I2S_TRANS_LVL1: Transfer FIFO level is 1 + * @arg I2S_TRANS_LVL2: Transfer FIFO level is 2 + * @arg I2S_TRANS_LVL3: Transfer FIFO level is 3 + * @arg I2S_TRANS_LVL4: Transfer FIFO level is 4 + * @retval None + */ +void I2S_SetTransFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_TRANS_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_TXBIRQWL, u32Level); +} + +/** + * @brief Set the receive FIFO level of I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Level Receive FIFO level + * This parameter can be one of the following values: + * @arg I2S_RECEIVE_LVL0: Receive FIFO level is 0 + * @arg I2S_RECEIVE_LVL1: Receive FIFO level is 1 + * @arg I2S_RECEIVE_LVL2: Receive FIFO level is 2 + * @arg I2S_RECEIVE_LVL3: Receive FIFO level is 3 + * @arg I2S_RECEIVE_LVL4: Receive FIFO level is 4 + * @retval None + */ +void I2S_SetReceiveFIFOLevel(M4_I2S_TypeDef *I2Sx, uint32_t u32Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_RECEIVE_LVL(u32Level)); + + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_RXBIRQWL, u32Level); +} + +/** + * @brief Set the communication protocol of I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Protocol Communication protocol + * This parameter can be one of the following values: + * @arg I2S_COM_PROTOCOL_PHILLIPS: Phillips protocol + * @arg I2S_COM_PROTOCOL_MSB: MSB justified protocol + * @arg I2S_COM_PROTOCOL_LSB: LSB justified protocol + * @arg I2S_COM_PROTOCOL_PCM_SHORT: PCM short-frame protocol + * @arg I2S_COM_PROTOCOL_PCM_LONG: PCM long-frame protocol + * @retval None + */ +void I2S_SetComProtocol(M4_I2S_TypeDef *I2Sx, uint32_t u32Protocol) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_COM_PROTOCOL(u32Protocol)); + + MODIFY_REG32(I2Sx->CFGR, (I2S_CFGR_I2SSTD | I2S_CFGR_PCMSYNC), u32Protocol); +} + +/** + * @brief Set the audio frequency for the I2S communication. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Freq Audio frequency + * This parameter can be 'I2S_AUDIO_FREQ_DEFAULT' or between + * 'I2S_AUDIO_FREQ_8K' and 'I2S_AUDIO_FREQ_192K': + * @arg I2S_AUDIO_FREQ_192K: FS = 192000Hz + * @arg I2S_AUDIO_FREQ_8K: FS = 8000Hz + * @arg I2S_AUDIO_FREQ_DEFAULT + * @retval An en_result_t enumeration value: + * - Ok: Set success + * - Error: Set failed + */ +en_result_t I2S_SetAudioFreq(M4_I2S_TypeDef *I2Sx, uint32_t u32Freq) +{ + en_result_t enRet = Ok; + uint32_t u32I2sClk; + uint32_t u32Temp; + uint32_t u32I2sDiv = 2UL; + uint32_t u32I2sOdd = 0UL; + uint32_t u32ChLen; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_AUDIO_FREQ(u32Freq)); + + if (I2S_AUDIO_FREQ_DEFAULT != u32Freq) + { + /* Get I2S source Clock frequency */ + if (I2S_CLK_SRC_EXT == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_CLKSEL)) + { + /* If an external I2S clock has to be used, this define + should be set in the ddl_config.h file */ + u32I2sClk = I2S_EXT_CLK_FREQ; + } + else + { + u32I2sClk = I2S_GetClockFreq(I2Sx); + } + + /* The actual frequency division value is calculated according to the output state of MCK */ + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) + { + u32ChLen = 32UL; + } + else + { + u32ChLen = 16UL; + } + + if (I2S_MCK_OUTPUT_ENABLE == READ_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE)) + { + if (I2S_CH_LEN_16BIT != READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_CHLEN)) + { + u32Temp = (((u32I2sClk / (u32ChLen*2U * 4U)) * 10U) / u32Freq) + 5U; + } + else + { + u32Temp = (((u32I2sClk / (u32ChLen*2U * 8U)) * 10U) / u32Freq) + 5U; + } + } + else + { + u32Temp = (((u32I2sClk / (u32ChLen*2U)) * 10U) / u32Freq) + 5U; + } + u32Temp = u32Temp / 10U; + u32I2sOdd = u32Temp & 0x01U; + u32I2sDiv = (u32Temp - u32I2sOdd) / 2U; + } + + if ((u32I2sDiv < 2U) || (u32I2sDiv > 0xFFU)) + { + enRet = Error; + } + else + { + /* Set clock division */ + WRITE_REG32(I2Sx->PR, u32I2sDiv); + MODIFY_REG32(I2Sx->CTRL, I2S_CTRL_ODD, (u32I2sOdd << I2S_CTRL_ODD_POS)); + } + + return enRet; +} + +/** + * @brief Enable or disable MCK clock output. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void I2S_MCKOutputCmd(M4_I2S_TypeDef *I2Sx, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable != enNewState) + { + SET_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } + else + { + CLEAR_REG32_BIT(I2Sx->CTRL, I2S_CTRL_MCKOE); + } +} + +/** + * @brief Enable or disable the function of I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Func I2S function + * This parameter can be one or any combination of the following values: + * @arg I2S_FUNC_TXE: Transfer function + * @arg I2S_FUNC_RXE: Receive function + * @arg I2S_FUNC_ALL: All of the above + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void I2S_FuncCmd(M4_I2S_TypeDef* I2Sx, uint32_t u32Func, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FUNC(u32Func)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable != enNewState) + { + SET_REG32_BIT(I2Sx->CTRL, u32Func); + } + else + { + CLEAR_REG32_BIT(I2Sx->CTRL, u32Func); + } +} + +/** + * @brief I2S send data. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Data Send data + * @retval None + */ +void I2S_WriteData(M4_I2S_TypeDef *I2Sx, uint32_t u32Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + WRITE_REG32(I2Sx->TXBUF, u32Data); +} + +/** + * @brief I2S receive data. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @retval uint32_t Receive data + */ +uint32_t I2S_ReadData(const M4_I2S_TypeDef *I2Sx) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + return READ_REG32(I2Sx->RXBUF); +} + +/** + * @brief I2S transmit data in polling mode. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval An en_result_t enumeration value: + * - Ok: Transmit data success + * - ErrorInvalidParameter: Invalid parameter + * - ErrorTimeout: Transmission timeout + */ +en_result_t I2S_Trans(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + uint32_t i; + uint32_t u32DataWidth; + + if ((NULL == pvTxBuf) || (0UL == u32Len)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDRESS_ALIGN_HALFWORD(pvTxBuf)) || + (IS_ADDRESS_ALIGN_WORD(pvTxBuf))) + { + for (i = 0UL; i < u32Len; i++) + { + enRet = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, Reset, u32Timeout); + if (Ok != enRet) + { + break; + } + + if (I2S_DATA_LEN_16BIT == u32DataWidth) + { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[i]); + } + else + { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[i]); + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + * @brief I2S receive data in polling mode. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval An en_result_t enumeration value: + * - Ok: Receive data success + * - ErrorInvalidParameter: Invalid parameter + * - ErrorTimeout: Transmission timeout + */ +en_result_t I2S_Receive(const M4_I2S_TypeDef *I2Sx, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + uint32_t i; + uint32_t u32DataWidth; + uint32_t u32Temp; + + if ((NULL == pvRxBuf) || (0UL == u32Len)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDRESS_ALIGN_HALFWORD(pvRxBuf)) || + (IS_ADDRESS_ALIGN_WORD(pvRxBuf))) + { + for (i = 0UL; i < u32Len; i++) + { + enRet = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, Reset, u32Timeout); + if (Ok != enRet) + { + break; + } + + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) + { + ((uint16_t *)pvRxBuf)[i] = (uint16_t)(u32Temp & 0xFFFFUL); + } + else if (I2S_DATA_LEN_24BIT == u32DataWidth) + { + ((uint32_t *)pvRxBuf)[i] = u32Temp & 0xFFFFFFUL; + } + else + { + ((uint32_t *)pvRxBuf)[i] = u32Temp; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + * @brief I2S transmit and receive data in polling mode. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] pvTxBuf The pointer to data transmitted buffer + * @param [in] pvRxBuf The pointer to data received buffer + * @param [in] u32Len Data length + * @param [in] u32Timeout Transfer timeout(ms) + * @retval An en_result_t enumeration value: + * - Ok: Receive data success + * - ErrorInvalidParameter: Invalid parameter + * - ErrorTimeout: Transmission timeout + */ +en_result_t I2S_TransReceive(M4_I2S_TypeDef *I2Sx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Len, uint32_t u32Timeout) +{ + en_result_t enRet; + uint32_t u32TxCnt = 0U; + uint32_t u32RxCnt = 0U; + uint32_t u32DataWidth; + uint32_t u32Temp; + uint8_t u8BreakFlag = 0U; + + if ((NULL == pvTxBuf) || (NULL == pvRxBuf) || (0UL == u32Len)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + + u32DataWidth = READ_REG32_BIT(I2Sx->CFGR, I2S_CFGR_DATLEN); + if (((I2S_DATA_LEN_16BIT == u32DataWidth) && IS_ADDRESS_ALIGN_HALFWORD(pvTxBuf) && IS_ADDRESS_ALIGN_HALFWORD(pvRxBuf)) || + (IS_ADDRESS_ALIGN_WORD(pvTxBuf) && IS_ADDRESS_ALIGN_WORD(pvRxBuf))) + { + enRet = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, Reset, u32Timeout); + if (Ok == enRet) + { + /* Preload data */ + if (I2S_DATA_LEN_16BIT == u32DataWidth) + { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } + else + { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + + for (;;) + { + /* Transmit data */ + if (u32TxCnt < u32Len) + { + enRet = I2S_WaitStatus(I2Sx, I2S_FLAG_TX_FULL, Reset, u32Timeout); + if (Ok != enRet) + { + u8BreakFlag = 1U; + } + else + { + if (I2S_DATA_LEN_16BIT == u32DataWidth) + { + WRITE_REG32(I2Sx->TXBUF, ((const uint16_t *)pvTxBuf)[u32TxCnt]); + } + else + { + WRITE_REG32(I2Sx->TXBUF, ((const uint32_t *)pvTxBuf)[u32TxCnt]); + } + u32TxCnt++; + } + } + /* Receive data */ + if ((1U != u8BreakFlag) && (u32RxCnt < u32Len)) + { + enRet = I2S_WaitStatus(I2Sx, I2S_FLAG_RX_EMPTY, Reset, u32Timeout); + if (Ok != enRet) + { + u8BreakFlag = 1U; + } + else + { + u32Temp = READ_REG32(I2Sx->RXBUF); + if (I2S_DATA_LEN_16BIT == u32DataWidth) + { + ((uint16_t *)pvRxBuf)[u32RxCnt] = (uint16_t)(u32Temp & 0xFFFFUL); + } + else if (I2S_DATA_LEN_24BIT == u32DataWidth) + { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp & 0xFFFFFFUL; + } + else + { + ((uint32_t *)pvRxBuf)[u32RxCnt] = u32Temp; + } + u32RxCnt++; + } + } + + /* Complete the transmission */ + if ((1U == u8BreakFlag) || ((u32Len == u32TxCnt) && (u32Len == u32RxCnt))) + { + break; + } + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + } + + return enRet; +} + +/** + * @brief Enable or disable specified I2S interrupt. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32IntType Interrupt type + * This parameter can be one or any combination of the following values: + * @arg I2S_INT_TX: Transfer interrupt + * @arg I2S_INT_RX: Receive interrupt + * @arg I2S_INT_ERR: Communication error interrupt + * @arg I2S_INT_ALL: All of the above + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void I2S_IntCmd(M4_I2S_TypeDef *I2Sx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_INT(u32IntType)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable != enNewState) + { + SET_REG32_BIT(I2Sx->CTRL, u32IntType); + } + else + { + CLEAR_REG32_BIT(I2Sx->CTRL, u32IntType); + } +} + +/** + * @brief Get I2S flag status. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_FLAG_ALL: All of the above + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t I2S_GetStatus(const M4_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + uint32_t u32NormalFlag; + uint32_t u32ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_FLAG(u32Flag)); + + u32NormalFlag = u32Flag & 0xFFFFUL; + u32ErrorFlag = u32Flag >> 16U; + if (0UL != u32NormalFlag) + { + if (0UL != (READ_REG32_BIT(I2Sx->SR, u32NormalFlag))) + { + enFlagSta = Set; + } + } + if ((Reset == enFlagSta) && (0UL != u32ErrorFlag)) + { + if (0UL != (READ_REG32_BIT(I2Sx->ER, u32ErrorFlag))) + { + enFlagSta = Set; + } + } + + return enFlagSta; +} + +/** + * @brief Clear I2S flag. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Flag I2S flag type + * This parameter can be one or any combination of the following values: + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @arg I2S_CLR_FLAG_ALL: All of the above + * @retval None + */ +void I2S_ClearStatus(M4_I2S_TypeDef *I2Sx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_I2S_UNIT(I2Sx)); + DDL_ASSERT(IS_I2S_CLR_FLAG(u32Flag)); + + CLEAR_REG32_BIT(I2Sx->ER, u32Flag); +} + +/** + * @brief Get I2S clock frequency. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @retval uint32_t The I2S clock frequency + */ +static uint32_t I2S_GetClockFreq(const M4_I2S_TypeDef *I2Sx) +{ + uint32_t u32ClockShift; + uint16_t u32ClockSrc; + uint32_t u32ClockFreq; + uint32_t u32PllP; + uint32_t u32PllQ; + uint32_t u32PllR; + uint32_t u32PllN; + uint32_t u32PllM; + uint32_t u32PllIn; + uint32_t u32Temp; + + /* Get the offset of the I2S clock source in CMU_I2SCKSEL */ + if (M4_I2S1 == I2Sx) + { + u32ClockShift = CMU_I2SCKSEL_I2S1CKSEL_POS; + } + else if (M4_I2S2 == I2Sx) + { + u32ClockShift = CMU_I2SCKSEL_I2S2CKSEL_POS; + } + else if (M4_I2S3 == I2Sx) + { + u32ClockShift = CMU_I2SCKSEL_I2S3CKSEL_POS; + } + else if (M4_I2S4 == I2Sx) + { + u32ClockShift = CMU_I2SCKSEL_I2S4CKSEL_POS; + } + else + { + u32ClockShift = 0UL; + } + + u32ClockSrc = (READ_REG16(M4_CMU->I2SCKSEL) >> u32ClockShift) & CMU_I2SCKSEL_I2S1CKSEL; + if (0UL != READ_REG32_BIT(M4_CMU->PLLHCFGR, CMU_PLLHCFGR_PLLSRC)) + { + u32PllIn = HRC_VALUE; + } + else + { + u32PllIn = XTAL_VALUE; + } + /* Calculate the clock frequency */ + switch(u32ClockSrc) + { + case 0x00U: /* PCLK1 */ + u32ClockFreq = SystemCoreClock >> ((READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + break; + case 0x08U: /* PLLHQ */ + u32Temp = READ_REG32(M4_CMU->PLLHCFGR); + u32PllM = (u32Temp >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL; + u32PllN = (u32Temp >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL; + u32PllQ = (u32Temp >> CMU_PLLHCFGR_PLLHQ_POS) & 0x0FUL; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case 0x09U: /* PLLHR */ + u32Temp = READ_REG32(M4_CMU->PLLHCFGR); + u32PllM = (u32Temp >> CMU_PLLHCFGR_PLLHM_POS) & 0x03UL; + u32PllN = (u32Temp >> CMU_PLLHCFGR_PLLHN_POS) & 0xFFUL; + u32PllR = (u32Temp >> CMU_PLLHCFGR_PLLHR_POS) & 0x0FUL; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + case 0x0AU: /* PLLAP */ + u32Temp = READ_REG32(M4_CMU->PLLACFGR); + u32PllM = (u32Temp >> CMU_PLLACFGR_PLLAM_POS) & 0x1FUL; + u32PllN = (u32Temp >> CMU_PLLACFGR_PLLAN_POS) & 0x1FFUL; + u32PllP = (u32Temp >> CMU_PLLACFGR_PLLAP_POS) & 0x0FUL; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllP + 1UL); + break; + case 0x0BU: /* PLLAQ */ + u32Temp = READ_REG32(M4_CMU->PLLACFGR); + u32PllM = (u32Temp >> CMU_PLLACFGR_PLLAM_POS) & 0x1FUL; + u32PllN = (u32Temp >> CMU_PLLACFGR_PLLAN_POS) & 0x1FFUL; + u32PllQ = (u32Temp >> CMU_PLLACFGR_PLLAQ_POS) & 0x0FUL; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllQ + 1UL); + break; + case 0x0CU: /* PLLAR */ + u32Temp = READ_REG32(M4_CMU->PLLACFGR); + u32PllM = (u32Temp >> CMU_PLLACFGR_PLLAM_POS) & 0x1FUL; + u32PllN = (u32Temp >> CMU_PLLACFGR_PLLAN_POS) & 0x1FFUL; + u32PllR = (u32Temp >> CMU_PLLACFGR_PLLAR_POS) & 0x0FUL; + u32ClockFreq = ((u32PllIn / (u32PllM + 1UL)) * (u32PllN + 1UL)) / (u32PllR + 1UL); + break; + default: + u32ClockFreq = 0UL; + break; + } + + return u32ClockFreq; +} + +/** + * @brief Wait for the flag status of I2S. + * @param [in] I2Sx Pointer to I2S instance register base + * This parameter can be one of the following values: + * @arg M4_I2S1: I2S unit 1 instance register base + * @arg M4_I2S2: I2S unit 2 instance register base + * @arg M4_I2S3: I2S unit 3 instance register base + * @arg M4_I2S4: I2S unit 4 instance register base + * @param [in] u32Flag I2S flag type + * This parameter can be one of the following values: + * @arg I2S_FLAG_TX_ALARM: Transfer buffer alarm flag + * @arg I2S_FLAG_RX_ALARM: Receive buffer alarm flag + * @arg I2S_FLAG_TX_EMPTY: Transfer buffer empty flag + * @arg I2S_FLAG_TX_FULL: Transfer buffer full flag + * @arg I2S_FLAG_RX_EMPTY: Receive buffer empty flag + * @arg I2S_FLAG_RX_FULL: Receive buffer full flag + * @arg I2S_FLAG_TX_ERR: Transfer overflow or underflow flag + * @arg I2S_FLAG_RX_ERR: Receive overflow flag + * @param [in] enStatus The flag status + * This parameter can be one of the following values: + * @arg Set: Wait for the flag to set + * @arg Reset: Wait for the flag to reset + * @param [in] u32Timeout Wait the flag timeout(ms) + * @retval An en_result_t enumeration value: + * - Ok: Wait status success + * - ErrorTimeout: Wait timeout + */ +static en_result_t I2S_WaitStatus(const M4_I2S_TypeDef *I2Sx, uint32_t u32Flag, en_flag_status_t enStatus, uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + __IO uint32_t u32Count; + + /* Waiting for the flag status to change to the enStatus */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (enStatus != I2S_GetStatus(I2Sx, u32Flag)) + { + if (u32Count == 0UL) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_I2S_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_icg.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_icg.c new file mode 100644 index 0000000000000000000000000000000000000000..7937465caa9bb5047c80f4aa0ff5914c4f09d8ae --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_icg.c @@ -0,0 +1,124 @@ +/** + ******************************************************************************* + * @file hc32f4a0_icg.c + * @brief This file provides firmware functions to manage the Initial + * Configuration(ICG). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-09-04 Yangjp Optimizing the definition method of ICG field + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_icg.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_ICG ICG + * @brief Initial Configuration Driver Library + * @{ + */ + +#if (DDL_ICG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @brief ICG parameters configuration + */ +#if defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050) +const uint32_t u32ICG[] __attribute__((section(".ARM.__at_0x400"))) = +#elif defined (__GNUC__) && !defined (__CC_ARM) +const uint32_t u32ICG[] __attribute__((section(".icg_sec"))) = +#elif defined (__CC_ARM) +const uint32_t u32ICG[] __attribute__((at(0x400))) = +#elif defined (__ICCARM__) +#pragma location = 0x400 +__root static const uint32_t u32ICG[] = +#else +#error "unsupported compiler!!" +#endif +{ + /* ICG 0~3 */ + ICG_REG_CFG0_CONSTANT, + ICG_REG_CFG1_CONSTANT, + ICG_REG_CFG2_CONSTANT, + ICG_REG_CFG3_CONSTANT, + /* Reserved 0~3 */ + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + /* Reserved 4~7 */ + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + /* Reserved 8~11 */ + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + /* Reserved 12~15 */ + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + /* Reserved 16~19 */ + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, + ICG_RESERVED_CONSTANT, +}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +#endif /* DDL_ICG_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.c new file mode 100644 index 0000000000000000000000000000000000000000..691a3e060c60b36230305da1ef35ddca13b900cc --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.c @@ -0,0 +1,7673 @@ +/** + ******************************************************************************* + * @file hc32f4a0_interrupts.c + * @brief This file provides firmware functions to manage the Interrupt Controller + * (INTC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-08-25 Zhangxl Modify for MISRAC2012-8.4, 8.6, 10.1 + 2020-09-09 Zhangxl Merge EFM0/1 share IRQ handler + 2020-10-30 Zhangxl Revise I2C TxEmpty & Complete share IRQ handler entry + 2020-11-15 Zhangxl SPII flag judgment for share IRQ. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_interrupts.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_INTERRUPTS INTERRUPTS + * @brief INTC Driver Library + * @{ + */ + +#if (DDL_INTERRUPTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Macros INTC Local Macros + * @{ + */ +/** + * @brief Maximum IRQ handler number + */ +#define IRQ_NUM_MAX (128U) + +/** + * @brief Wakeup event enable mask + */ +#define INTC_WUPEN_MASK \ + (INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \ + INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \ + INTC_WUPEN_CMPWUEN | INTC_WUPEN_WKTMWUEN | \ + INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \ + INTC_WUPEN_TMR0GCMWUEN | INTC_WUPEN_TMR2GCMWUEN | \ + INTC_WUPEN_TMR2OVFWUEN | INTC_WUPEN_RXWUEN | \ + INTC_WUPEN_USHWUEN | INTC_WUPEN_USFWUEN | \ + INTC_WUPEN_ETHWUEN) + +/** + * @} + */ + +/** + * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for wakeup source from stop mode. */ +#define IS_INTC_WKUP_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | INTC_WUPEN_MASK) == INTC_WUPEN_MASK)) + +/*! Parameter validity check for event index. */ +#define IS_INTC_EVENT(event) ((event) != 0x00UL) + +/*! Parameter validity check for interrupt index. */ +#define IS_INTC_INT(it) ((it) != 0x00UL) + +/*! Parameter validity check for software interrupt index. */ +#define IS_INTC_SWI(swi) ((swi) != 0x00UL) + +/*! Parameter validity check for NMI trigger source. */ +#define IS_NMI_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | NMI_SRC_MASK) == NMI_SRC_MASK)) + +/*! Parameter validity check for EXINT filter A function. */ +#define IS_EXINT_FAE(fae) \ +( ((fae) == EXINT_FILTER_A_OFF) || \ + ((fae) == EXINT_FILTER_A_ON)) + +/*! Parameter validity check for EXINT filter A clock division. */ +#define IS_EXINT_FACLK(faclk) \ +( ((faclk) == EXINT_FACLK_HCLK_DIV1) || \ + ((faclk) == EXINT_FACLK_HCLK_DIV8) || \ + ((faclk) == EXINT_FACLK_HCLK_DIV32) || \ + ((faclk) == EXINT_FACLK_HCLK_DIV64)) + +/*! Parameter validity check for EXINT filter B function. */ +#define IS_EXINT_FBE(fbe) \ +( ((fbe) == EXINT_FILTER_B_OFF) || \ + ((fbe) == EXINT_FILTER_B_ON)) + +/*! Parameter validity check for EXINT filter B time. */ +#define IS_EXINT_FBTIME(fbtime) \ +( ((fbtime) == EXINT_FBTIM_500NS) || \ + ((fbtime) == EXINT_FBTIM_1US) || \ + ((fbtime) == EXINT_FBTIM_2US) || \ + ((fbtime) == EXINT_FBTIM_4US)) + + +/*! Parameter validity check for EXINT trigger edge. */ +#define IS_EXINT_TRIGGER(trigger) \ +( ((trigger) == EXINT_TRIGGER_LOW) || \ + ((trigger) == EXINT_TRIGGER_RISING) || \ + ((trigger) == EXINT_TRIGGER_FALLING) || \ + ((trigger) == EXINT_TRIGGER_BOTH)) + +/*! Parameter validity check for EXINT channel. */ +#define IS_EXINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXINT_CH_MASK) == EXINT_CH_MASK)) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Variable INTC Local Variable + * @{ + */ +static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL}; +static func_ptr_t m_pfnNmiCallback; +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Functions INTC Global Functions + * @{ + */ +/** + * @brief IRQ sign in function + * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure + * @arg enIntSrc: can be any value @ref en_int_src_t + * @arg enIRQn: can be any value from Int000_IRQn ~ Int127_IRQn @ref IRQn_Type + * @arg pfnCallback: Callback function + * @retval Ok: IRQ register successfully + * ErrorInvalidParameter: IRQ No. and Peripheral Int source are not match; + * NULL pointer. + * ErrorUninitialized: Specified IRQ entry was signed before. + */ +en_result_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig) +{ + __IO uint32_t *INTC_SELx; + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcIrqSignConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + /* IRQ032~127 whether out of range */ + if ((((((uint32_t)pstcIrqSignConfig->enIntSrc / 0x20UL) * 6UL + 0x20UL) > (uint32_t)pstcIrqSignConfig->enIRQn) || \ + ((((uint32_t)pstcIrqSignConfig->enIntSrc / 0x20UL) * 6UL + 0x25U) < (uint32_t)pstcIrqSignConfig->enIRQn))&& \ + ((uint32_t)pstcIrqSignConfig->enIRQn >= 0x20UL)) + { + enRet = ErrorInvalidParameter; + } + else + { + INTC_SELx = (__IO uint32_t *)((uint32_t)(&M4_INTC->SEL0) + (4U * (uint32_t)pstcIrqSignConfig->enIRQn)); + /* for MISRAC2004-12.4 */ + if (0x1FFUL == ((*INTC_SELx) & 0x1FFUL)) + { + WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } + else if ((uint32_t)(pstcIrqSignConfig->enIntSrc) == ((*INTC_SELx) & 0x1FFUL)) + { + WRITE_REG32(*INTC_SELx, pstcIrqSignConfig->enIntSrc); + m_apfnIrqHandler[pstcIrqSignConfig->enIRQn] = pstcIrqSignConfig->pfnCallback; + } + else + { + enRet = ErrorUninitialized; + } + } + } + return enRet; +} + +/** + * @brief IRQ sign out function + * @param [in] enIRQn: can be any value from Int000_IRQn ~ Int127_IRQn @ref IRQn_Type + * @retval Ok: IRQ sign out successfully + * ErrorInvalidParameter: IRQ No. is out of range + */ +en_result_t INTC_IrqSignOut(IRQn_Type enIRQn) +{ + __IO uint32_t *INTC_SELx; + en_result_t enRet = Ok; + + if ((enIRQn < Int000_IRQn) || (enIRQn > Int127_IRQn)) + { + enRet = ErrorInvalidParameter; + } + else + { + INTC_SELx = (__IO uint32_t *)((uint32_t)(&M4_INTC->SEL0) + (4UL * (uint32_t)enIRQn)); + WRITE_REG32(*INTC_SELx, 0x1FFUL); + m_apfnIrqHandler[enIRQn] = NULL; + } + return enRet; +} + +/** + * @brief Share IRQ configure + * @param [in] enIntSrc: Peripheral interrupt source @ref en_int_src_t + * @param [in] enNewState: + * @arg Enable: Enable corresponding peripheral interrupt in share IRQ handler + * @arg Disable: Disable corresponding peripheral interrupt in share IRQ handler + * @retval Ok: Share IRQ configure successfully + */ +en_result_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState) +{ + __IO uint32_t *INTC_VSSELx; + + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + INTC_VSSELx = (__IO uint32_t *)(((uint32_t)&M4_INTC->VSSEL128) + (4U * ((uint32_t)enIntSrc / 0x20U))); + if (Enable == enNewState) + { + SET_REG32_BIT(*INTC_VSSELx, (uint32_t)(1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } + else + { + CLEAR_REG32_BIT(*INTC_VSSELx, (1UL << ((uint32_t)enIntSrc & 0x1FUL))); + } + return Ok; +} + +/** + * @brief Stop mode wake-up source configure + * @param [in] u32WakeupSrc: Wake-up source + * @arg INTC_WUPEN_EIRQWUEN + * @arg INTC_WUPEN_EIRQWUEN_0 + * @arg INTC_WUPEN_EIRQWUEN_1 + * @arg INTC_WUPEN_EIRQWUEN_2 + * @arg INTC_WUPEN_EIRQWUEN_3 + * @arg INTC_WUPEN_EIRQWUEN_4 + * @arg INTC_WUPEN_EIRQWUEN_5 + * @arg INTC_WUPEN_EIRQWUEN_6 + * @arg INTC_WUPEN_EIRQWUEN_7 + * @arg INTC_WUPEN_EIRQWUEN_8 + * @arg INTC_WUPEN_EIRQWUEN_9 + * @arg INTC_WUPEN_EIRQWUEN_10 + * @arg INTC_WUPEN_EIRQWUEN_11 + * @arg INTC_WUPEN_EIRQWUEN_12 + * @arg INTC_WUPEN_EIRQWUEN_13 + * @arg INTC_WUPEN_EIRQWUEN_14 + * @arg INTC_WUPEN_EIRQWUEN_15 + * @arg INTC_WUPEN_SWDTWUEN + * @arg INTC_WUPEN_PVD1WUEN + * @arg INTC_WUPEN_PVD2WUEN + * @arg INTC_WUPEN_CMPWUEN + * @arg INTC_WUPEN_WKTMWUEN + * @arg INTC_WUPEN_RTCALMWUEN + * @arg INTC_WUPEN_RTCPRDWUEN + * @arg INTC_WUPEN_TMR0GCMWUEN + * @arg INTC_WUPEN_TMR2GCMWUEN + * @arg INTC_WUPEN_TMR2OVFWUEN + * @arg INTC_WUPEN_RXWEN + * @arg INTC_WUPEN_USHWUEN + * @arg INTC_WUPEN_USFWUEN + * @arg INTC_WUPEN_ETHWUEN + * @param [in] enNewState + * @arg Enable: Enable corresponding wake up source + * @arg Disable: Disable corresponding wake up source + * @retval None + */ +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_WKUP_SRC(u32WakeupSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(M4_INTC->WUPEN, u32WakeupSrc); + } + else + { + CLEAR_REG32_BIT(M4_INTC->WUPEN, u32WakeupSrc); + } +} + +/** + * @brief Event or Interrupt output configure + * @param [in] u32Event: Event index + * @arg INTC_EVTER_EVTE0 + * @arg INTC_EVTER_EVTE1 + * @arg INTC_EVTER_EVTE2 + * @arg INTC_EVTER_EVTE3 + * @arg INTC_EVTER_EVTE4 + * @arg INTC_EVTER_EVTE5 + * @arg INTC_EVTER_EVTE6 + * @arg INTC_EVTER_EVTE7 + * @arg INTC_EVTER_EVTE8 + * @arg INTC_EVTER_EVTE9 + * @arg INTC_EVTER_EVTE10 + * @arg INTC_EVTER_EVTE11 + * @arg INTC_EVTER_EVTE12 + * @arg INTC_EVTER_EVTE13 + * @arg INTC_EVTER_EVTE14 + * @arg INTC_EVTER_EVTE15 + * @arg INTC_EVTER_EVTE16 + * @arg INTC_EVTER_EVTE17 + * @arg INTC_EVTER_EVTE18 + * @arg INTC_EVTER_EVTE19 + * @arg INTC_EVTER_EVTE20 + * @arg INTC_EVTER_EVTE21 + * @arg INTC_EVTER_EVTE22 + * @arg INTC_EVTER_EVTE23 + * @arg INTC_EVTER_EVTE24 + * @arg INTC_EVTER_EVTE25 + * @arg INTC_EVTER_EVTE26 + * @arg INTC_EVTER_EVTE27 + * @arg INTC_EVTER_EVTE28 + * @arg INTC_EVTER_EVTE29 + * @arg INTC_EVTER_EVTE30 + * @arg INTC_EVTER_EVTE31 + * @param [in] enNewState + * @arg Enable: Enable corresponding event to NVIC + * @arg Disable: Disable corresponding event but interrupt to NVIC + * @retval None + */ +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_EVENT(u32Event)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(M4_INTC->EVTER, u32Event); + } + else + { + CLEAR_REG32_BIT(M4_INTC->EVTER, u32Event); + } +} + +/** + * @brief Interrupt function configure + * @param [in] u32Int: Interrupt index + * @arg INTC_IER_IER0 + * @arg INTC_IER_IER1 + * @arg INTC_IER_IER2 + * @arg INTC_IER_IER3 + * @arg INTC_IER_IER4 + * @arg INTC_IER_IER5 + * @arg INTC_IER_IER6 + * @arg INTC_IER_IER7 + * @arg INTC_IER_IER8 + * @arg INTC_IER_IER9 + * @arg INTC_IER_IER10 + * @arg INTC_IER_IER11 + * @arg INTC_IER_IER12 + * @arg INTC_IER_IER13 + * @arg INTC_IER_IER14 + * @arg INTC_IER_IER15 + * @arg INTC_IER_IER16 + * @arg INTC_IER_IER17 + * @arg INTC_IER_IER18 + * @arg INTC_IER_IER19 + * @arg INTC_IER_IER20 + * @arg INTC_IER_IER21 + * @arg INTC_IER_IER22 + * @arg INTC_IER_IER23 + * @arg INTC_IER_IER24 + * @arg INTC_IER_IER25 + * @arg INTC_IER_IER26 + * @arg INTC_IER_IER27 + * @arg INTC_IER_IER28 + * @arg INTC_IER_IER29 + * @arg INTC_IER_IER30 + * @arg INTC_IER_IER31 + * @param [in] enNewState + * @arg Enable: Enable corresponding interrupt to NVIC + * @arg Disable: Disable corresponding interrupt to NVIC + * @retval None + */ +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_INT(u32Int)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(M4_INTC->IER, u32Int); + } + else + { + CLEAR_REG32_BIT(M4_INTC->IER, u32Int); + } +} + +/** + * @brief Software Interrupt function configure + * @param [in] u32SWI: Software Interrupt index + * @arg INTC_SWIER_SWIE0 + * @arg INTC_SWIER_SWIE1 + * @arg INTC_SWIER_SWIE2 + * @arg INTC_SWIER_SWIE3 + * @arg INTC_SWIER_SWIE4 + * @arg INTC_SWIER_SWIE5 + * @arg INTC_SWIER_SWIE6 + * @arg INTC_SWIER_SWIE7 + * @arg INTC_SWIER_SWIE8 + * @arg INTC_SWIER_SWIE9 + * @arg INTC_SWIER_SWIE10 + * @arg INTC_SWIER_SWIE11 + * @arg INTC_SWIER_SWIE12 + * @arg INTC_SWIER_SWIE13 + * @arg INTC_SWIER_SWIE14 + * @arg INTC_SWIER_SWIE15 + * @arg INTC_SWIER_SWIE16 + * @arg INTC_SWIER_SWIE17 + * @arg INTC_SWIER_SWIE18 + * @arg INTC_SWIER_SWIE19 + * @arg INTC_SWIER_SWIE20 + * @arg INTC_SWIER_SWIE21 + * @arg INTC_SWIER_SWIE22 + * @arg INTC_SWIER_SWIE23 + * @arg INTC_SWIER_SWIE24 + * @arg INTC_SWIER_SWIE25 + * @arg INTC_SWIER_SWIE26 + * @arg INTC_SWIER_SWIE27 + * @arg INTC_SWIER_SWIE28 + * @arg INTC_SWIER_SWIE29 + * @arg INTC_SWIER_SWIE30 + * @arg INTC_SWIER_SWIE31 + * @param [in] enNewState + * @arg Enable: Enable corresponding software interrupt + * @arg Disable: Disable corresponding software interrupt + * @retval None + */ +void INTC_SWICmd(uint32_t u32SWI, en_functional_state_t enNewState) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_INTC_SWI(u32SWI)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(M4_INTC->SWIER, u32SWI); + } + else + { + CLEAR_REG32_BIT(M4_INTC->SWIER, u32SWI); + } +} + +/** + * @brief Initialize NMI. Fill each pstcNmiInit with default value + * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that + * contains configuration information. + * @retval Ok: NMI structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcNmiInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcNmiInit->u32NmiSrc = 0UL; + pstcNmiInit->pfnNmiCallback = NULL; + } + return enRet; +} + +/** + * @brief Initialize NMI. + * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that + * contains configuration information. + * @retval Ok: NMI initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t NMI_Init(const stc_nmi_init_t *pstcNmiInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if ((NULL == pstcNmiInit) || (NULL == pstcNmiInit->pfnNmiCallback)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(pstcNmiInit->u32NmiSrc)); + + /* Clear all NMI trigger source before set */ + WRITE_REG32(M4_INTC->NMICFR, INTC_NMICLR_MASK); + + /* NMI trigger source configure */ + WRITE_REG32(M4_INTC->NMIENR, pstcNmiInit->u32NmiSrc); + + /* NMI callback function configure */ + m_pfnNmiCallback = pstcNmiInit->pfnNmiCallback; + } + return enRet; +} + +/** + * @brief Get NMI trigger source + * @param [in] u32NmiSrc: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @arg NMI_SRC_SWDT + * @arg NMI_SRC_PVD1 + * @arg NMI_SRC_PVD2 + * @arg NMI_SRC_XTAL + * @arg NMI_SRC_SRAM_PARITY + * @arg NMI_SRC_SRAM_ECC + * @arg NMI_SRC_BUS_ERR + * @arg NMI_SRC_WDT + * @retval Set: NMI is triggered by corresponding source + * Reset: NMI is not triggered by corresponding source + */ +en_flag_status_t NMI_GetNmiSrc(uint32_t u32NmiSrc) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32NmiSrc)); + + return (((READ_REG32(M4_INTC->NMIFR) & u32NmiSrc)) != 0UL) ? Set : Reset; +} + +/** + * @brief Set NMI trigger source + * @param [in] u32NmiSrc: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @arg NMI_SRC_SWDT + * @arg NMI_SRC_PVD1 + * @arg NMI_SRC_PVD2 + * @arg NMI_SRC_XTAL + * @arg NMI_SRC_SRAM_PARITY + * @arg NMI_SRC_SRAM_ECC + * @arg NMI_SRC_BUS_ERR + * @arg NMI_SRC_WDT + * @retval None + */ +void NMI_SetNmiSrc(uint32_t u32NmiSrc) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32NmiSrc)); + + WRITE_REG32(M4_INTC->NMIENR, u32NmiSrc); +} + +/** + * @brief Clear specified NMI trigger source + * @param [in] u32NmiSrc: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @arg NMI_SRC_SWDT + * @arg NMI_SRC_PVD1 + * @arg NMI_SRC_PVD2 + * @arg NMI_SRC_XTAL + * @arg NMI_SRC_SRAM_PARITY + * @arg NMI_SRC_SRAM_ECC + * @arg NMI_SRC_BUS_ERR + * @arg NMI_SRC_WDT + * @retval None + */ +void NMI_ClrNmiSrc(uint32_t u32NmiSrc) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_NMI_SRC(u32NmiSrc)); + + SET_REG32_BIT(M4_INTC->NMICFR, u32NmiSrc); +} + +/** + * @brief NMI IRQ handler + * @param None + * @retval None + */ +void NMI_IrqHandler(void) +{ + if (NULL != m_pfnNmiCallback) + { + m_pfnNmiCallback(); + } +} + +/** + * @brief Initialize External interrupt. + * @param [in] pstcExIntInit: Pointer to a stc_exint_init_t structure that + * contains configuration information. + * @retval Ok: EXINT initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t EXINT_Init(const stc_exint_init_t *pstcExIntInit) +{ + uint8_t u8ExIntPos; + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcExIntInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_FAE(pstcExIntInit->u32ExIntFAE)); + DDL_ASSERT(IS_EXINT_FACLK(pstcExIntInit->u32ExIntFAClk)); + DDL_ASSERT(IS_EXINT_FBE(pstcExIntInit->u32ExIntFBE)); + DDL_ASSERT(IS_EXINT_FBTIME(pstcExIntInit->u32ExIntFBTime)); + DDL_ASSERT(IS_EXINT_TRIGGER(pstcExIntInit->u32ExIntLvl)); + DDL_ASSERT(IS_EXINT_CH(pstcExIntInit->u32ExIntCh)); + + for (u8ExIntPos = 0U; u8ExIntPos < 16U; u8ExIntPos++) + { + if ((pstcExIntInit->u32ExIntCh & (1UL << u8ExIntPos)) != 0U) + { + WRITE_REG32(*(uint32_t *)((uint32_t)(&M4_INTC->EIRQCR0) + 4UL*u8ExIntPos), \ + (pstcExIntInit->u32ExIntFAE | \ + pstcExIntInit->u32ExIntFAClk | \ + pstcExIntInit->u32ExIntFBE | \ + pstcExIntInit->u32ExIntLvl)); + WRITE_REG32(M4_INTC->NOCCR, pstcExIntInit->u32ExIntFBTime); + } + } + } + return enRet; +} + +/** + * @brief Initialize ExInt. Fill each pstcExIntInit with default value + * @param [in] pstcExIntInit: Pointer to a stc_exint_init_t structure + * that contains configuration information. + * @retval Ok: EXINT structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t EXINT_StructInit(stc_exint_init_t *pstcExIntInit) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcExIntInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Configure to default value */ + pstcExIntInit->u32ExIntCh = (uint32_t)0UL; + pstcExIntInit->u32ExIntFAE = EXINT_FILTER_A_OFF; + pstcExIntInit->u32ExIntFAClk = EXINT_FACLK_HCLK_DIV1; + pstcExIntInit->u32ExIntFBE = EXINT_FILTER_B_OFF; + pstcExIntInit->u32ExIntFBTime = EXINT_FBTIM_500NS; + pstcExIntInit->u32ExIntLvl = EXINT_TRIGGER_FALLING; + } + return enRet; +} + +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval None + */ +void EXINT_ClrExIntSrc(uint32_t u32ExIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_CH(u32ExIntCh)); + + SET_REG32_BIT(M4_INTC->EICFR, u32ExIntCh); +} + +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval Set: Specified channel of external interrupt is triggered + * Reset: Specified channel of external interrupt is not triggered + */ +en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh) +{ + /* Parameter validity checking */ + DDL_ASSERT(IS_EXINT_CH(u32ExIntCh)); + + return ((READ_REG16(M4_INTC->EIFR) & u32ExIntCh) != 0U) ? Set : Reset; +} + +/** + * @brief NMI IRQ handler + * @param None + * @retval None + */ +void NMI_Handler(void) +{ + NMI_IrqHandler(); +} + +/** + * @brief Hard Fault IRQ handler + * @param None + * @retval None + */ +__WEAKDEF void HardFault_Handler(void) +{ + HardFault_IrqHandler(); +} + +/** + * @brief Mem manage fault IRQ handler + * @param None + * @retval None + */ +void MemManage_Handler(void) +{ + MemManage_IrqHandler(); +} + +/** + * @brief Bus fault IRQ handler + * @param None + * @retval None + */ +void BusFault_Handler(void) +{ + BusFault_IrqHandler(); +} + +/** + * @brief Usage fault IRQ handler + * @param None + * @retval None + */ +void UsageFault_Handler(void) +{ + UsageFault_IrqHandler(); +} + +/** + * @brief SVCall IRQ handler + * @param None + * @retval None + */ +void SVC_Handler(void) +{ + SVC_IrqHandler(); +} + +/** + * @brief Debbug monitor IRQ handler + * @param None + * @retval None + */ +void DebugMon_Handler(void) +{ + DebugMon_IrqHandler(); +} + +/** + * @brief PendSV IRQ handler + * @param None + * @retval None + */ +__WEAKDEF void PendSV_Handler(void) +{ + PendSV_IrqHandler(); +} + +/** + * @brief SysTick IRQ handler + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Handler(void) +{ + SysTick_IrqHandler(); +} + +/** + * @brief Interrupt No.000 IRQ handler + * @param None + * @retval None + */ +void IRQ000_Handler(void) +{ + m_apfnIrqHandler[Int000_IRQn](); +} + +/** + * @brief Interrupt No.001 IRQ handler + * @param None + * @retval None + */ +void IRQ001_Handler(void) +{ + m_apfnIrqHandler[Int001_IRQn](); +} + +/** + * @brief Interrupt No.002 IRQ handler + * @param None + * @retval None + */ +void IRQ002_Handler(void) +{ + m_apfnIrqHandler[Int002_IRQn](); +} + +/** + * @brief Interrupt No.003 IRQ handler + * @param None + * @retval None + */ +void IRQ003_Handler(void) +{ + m_apfnIrqHandler[Int003_IRQn](); +} + +/** + * @brief Interrupt No.004 IRQ handler + * @param None + * @retval None + */ +void IRQ004_Handler(void) +{ + m_apfnIrqHandler[Int004_IRQn](); +} + +/** + * @brief Interrupt No.005 IRQ handler + * @param None + * @retval None + */ +void IRQ005_Handler(void) +{ + m_apfnIrqHandler[Int005_IRQn](); +} + +/** + * @brief Interrupt No.006 IRQ handler + * @param None + * @retval None + */ +void IRQ006_Handler(void) +{ + m_apfnIrqHandler[Int006_IRQn](); +} + +/** + * @brief Interrupt No.007 IRQ handler + * @param None + * @retval None + */ +void IRQ007_Handler(void) +{ + m_apfnIrqHandler[Int007_IRQn](); +} + +/** + * @brief Interrupt No.008 IRQ handler + * @param None + * @retval None + */ +void IRQ008_Handler(void) +{ + m_apfnIrqHandler[Int008_IRQn](); +} + +/** + * @brief Interrupt No.009 IRQ handler + * @param None + * @retval None + */ +void IRQ009_Handler(void) +{ + m_apfnIrqHandler[Int009_IRQn](); +} + +/** + * @brief Interrupt No.010 IRQ handler + * @param None + * @retval None + */ +void IRQ010_Handler(void) +{ + m_apfnIrqHandler[Int010_IRQn](); +} + + +/** + * @brief Interrupt No.011 IRQ handler + * @param None + * @retval None + */ +void IRQ011_Handler(void) +{ + m_apfnIrqHandler[Int011_IRQn](); +} + +/** + * @brief Interrupt No.012 IRQ handler + * @param None + * @retval None + */ +void IRQ012_Handler(void) +{ + m_apfnIrqHandler[Int012_IRQn](); +} + +/** + * @brief Interrupt No.013 IRQ handler + * @param None + * @retval None + */ +void IRQ013_Handler(void) +{ + m_apfnIrqHandler[Int013_IRQn](); +} + +/** + * @brief Interrupt No.014 IRQ handler + * @param None + * @retval None + */ +void IRQ014_Handler(void) +{ + m_apfnIrqHandler[Int014_IRQn](); +} + +/** + * @brief Interrupt No.015 IRQ handler + * @param None + * @retval None + */ +void IRQ015_Handler(void) +{ + m_apfnIrqHandler[Int015_IRQn](); +} + +/** + * @brief Interrupt No.016 IRQ handler + * @param None + * @retval None + */ +void IRQ016_Handler(void) +{ + m_apfnIrqHandler[Int016_IRQn](); +} + +/** + * @brief Interrupt No.017 IRQ handler + * @param None + * @retval None + */ +void IRQ017_Handler(void) +{ + m_apfnIrqHandler[Int017_IRQn](); +} + +/** + * @brief Interrupt No.018 IRQ handler + * @param None + * @retval None + */ +void IRQ018_Handler(void) +{ + m_apfnIrqHandler[Int018_IRQn](); +} + +/** + * @brief Interrupt No.019 IRQ handler + * @param None + * @retval None + */ +void IRQ019_Handler(void) +{ + m_apfnIrqHandler[Int019_IRQn](); +} + +/** + * @brief Interrupt No.020 IRQ handler + * @param None + * @retval None + */ +void IRQ020_Handler(void) +{ + m_apfnIrqHandler[Int020_IRQn](); +} + +/** + * @brief Interrupt No.021 IRQ handler + * @param None + * @retval None + */ +void IRQ021_Handler(void) +{ + m_apfnIrqHandler[Int021_IRQn](); +} + +/** + * @brief Interrupt No.022 IRQ handler + * @param None + * @retval None + */ +void IRQ022_Handler(void) +{ + m_apfnIrqHandler[Int022_IRQn](); +} + +/** + * @brief Interrupt No.023 IRQ handler + * @param None + * @retval None + */ +void IRQ023_Handler(void) +{ + m_apfnIrqHandler[Int023_IRQn](); +} + +/** + * @brief Interrupt No.024 IRQ handler + * @param None + * @retval None + */ +void IRQ024_Handler(void) +{ + m_apfnIrqHandler[Int024_IRQn](); +} + +/** + * @brief Interrupt No.025 IRQ handler + * @param None + * @retval None + */ +void IRQ025_Handler(void) +{ + m_apfnIrqHandler[Int025_IRQn](); +} + +/** + * @brief Interrupt No.026 IRQ handler + * @param None + * @retval None + */ +void IRQ026_Handler(void) +{ + m_apfnIrqHandler[Int026_IRQn](); +} + +/** + * @brief Interrupt No.027 IRQ handler + * @param None + * @retval None + */ +void IRQ027_Handler(void) +{ + m_apfnIrqHandler[Int027_IRQn](); +} + +/** + * @brief Interrupt No.028 IRQ handler + * @param None + * @retval None + */ +void IRQ028_Handler(void) +{ + m_apfnIrqHandler[Int028_IRQn](); +} + +/** + * @brief Interrupt No.029 IRQ handler + * @param None + * @retval None + */ +void IRQ029_Handler(void) +{ + m_apfnIrqHandler[Int029_IRQn](); +} + +/** + * @brief Interrupt No.030 IRQ handler + * @param None + * @retval None + */ +void IRQ030_Handler(void) +{ + m_apfnIrqHandler[Int030_IRQn](); +} + +/** + * @brief Interrupt No.031 IRQ handler + * @param None + * @retval None + */ +void IRQ031_Handler(void) +{ + m_apfnIrqHandler[Int031_IRQn](); +} + +/** + * @brief Interrupt No.032 IRQ handler + * @param None + * @retval None + */ +void IRQ032_Handler(void) +{ + m_apfnIrqHandler[Int032_IRQn](); +} + +/** + * @brief Interrupt No.033 IRQ handler + * @param None + * @retval None + */ +void IRQ033_Handler(void) +{ + m_apfnIrqHandler[Int033_IRQn](); +} + +/** + * @brief Interrupt No.034 IRQ handler + * @param None + * @retval None + */ +void IRQ034_Handler(void) +{ + m_apfnIrqHandler[Int034_IRQn](); +} + +/** + * @brief Interrupt No.035 IRQ handler + * @param None + * @retval None + */ +void IRQ035_Handler(void) +{ + m_apfnIrqHandler[Int035_IRQn](); +} + +/** + * @brief Interrupt No.036 IRQ handler + * @param None + * @retval None + */ +void IRQ036_Handler(void) +{ + m_apfnIrqHandler[Int036_IRQn](); +} + +/** + * @brief Interrupt No.037 IRQ handler + * @param None + * @retval None + */ +void IRQ037_Handler(void) +{ + m_apfnIrqHandler[Int037_IRQn](); +} + +/** + * @brief Interrupt No.038 IRQ handler + * @param None + * @retval None + */ +void IRQ038_Handler(void) +{ + m_apfnIrqHandler[Int038_IRQn](); +} + +/** + * @brief Interrupt No.039 IRQ handler + * @param None + * @retval None + */ +void IRQ039_Handler(void) +{ + m_apfnIrqHandler[Int039_IRQn](); +} + +/** + * @brief Interrupt No.040 IRQ handler + * @param None + * @retval None + */ +void IRQ040_Handler(void) +{ + m_apfnIrqHandler[Int040_IRQn](); +} + +/** + * @brief Interrupt No.041 IRQ handler + * @param None + * @retval None + */ +void IRQ041_Handler(void) +{ + m_apfnIrqHandler[Int041_IRQn](); +} + +/** + * @brief Interrupt No.042 IRQ handler + * @param None + * @retval None + */ +void IRQ042_Handler(void) +{ + m_apfnIrqHandler[Int042_IRQn](); +} + +/** + * @brief Interrupt No.043 IRQ handler + * @param None + * @retval None + */ +void IRQ043_Handler(void) +{ + m_apfnIrqHandler[Int043_IRQn](); +} + +/** + * @brief Interrupt No.044 IRQ handler + * @param None + * @retval None + */ +void IRQ044_Handler(void) +{ + m_apfnIrqHandler[Int044_IRQn](); +} + +/** + * @brief Interrupt No.045 IRQ handler + * @param None + * @retval None + */ +void IRQ045_Handler(void) +{ + m_apfnIrqHandler[Int045_IRQn](); +} + +/** + * @brief Interrupt No.046 IRQ handler + * @param None + * @retval None + */ +void IRQ046_Handler(void) +{ + m_apfnIrqHandler[Int046_IRQn](); +} + +/** + * @brief Interrupt No.047 IRQ handler + * @param None + * @retval None + */ +void IRQ047_Handler(void) +{ + m_apfnIrqHandler[Int047_IRQn](); +} + +/** + * @brief Interrupt No.048 IRQ handler + * @param None + * @retval None + */ +void IRQ048_Handler(void) +{ + m_apfnIrqHandler[Int048_IRQn](); +} + +/** + * @brief Interrupt No.049 IRQ handler + * @param None + * @retval None + */ +void IRQ049_Handler(void) +{ + m_apfnIrqHandler[Int049_IRQn](); +} + +/** + * @brief Interrupt No.050 IRQ handler + * @param None + * @retval None + */ +void IRQ050_Handler(void) +{ + m_apfnIrqHandler[Int050_IRQn](); +} + +/** + * @brief Interrupt No.051 IRQ handler + * @param None + * @retval None + */ +void IRQ051_Handler(void) +{ + m_apfnIrqHandler[Int051_IRQn](); +} + +/** + * @brief Interrupt No.052 IRQ handler + * @param None + * @retval None + */ +void IRQ052_Handler(void) +{ + m_apfnIrqHandler[Int052_IRQn](); +} + +/** + * @brief Interrupt No.053 IRQ handler + * @param None + * @retval None + */ +void IRQ053_Handler(void) +{ + m_apfnIrqHandler[Int053_IRQn](); +} + +/** + * @brief Interrupt No.054 IRQ handler + * @param None + * @retval None + */ +void IRQ054_Handler(void) +{ + m_apfnIrqHandler[Int054_IRQn](); +} + +/** + * @brief Interrupt No.055 IRQ handler + * @param None + * @retval None + */ +void IRQ055_Handler(void) +{ + m_apfnIrqHandler[Int055_IRQn](); +} + +/** + * @brief Interrupt No.056 IRQ handler + * @param None + * @retval None + */ +void IRQ056_Handler(void) +{ + m_apfnIrqHandler[Int056_IRQn](); +} + +/** + * @brief Interrupt No.057 IRQ handler + * @param None + * @retval None + */ +void IRQ057_Handler(void) +{ + m_apfnIrqHandler[Int057_IRQn](); +} + +/** + * @brief Interrupt No.058 IRQ handler + * @param None + * @retval None + */ +void IRQ058_Handler(void) +{ + m_apfnIrqHandler[Int058_IRQn](); +} + +/** + * @brief Interrupt No.059 IRQ handler + * @param None + * @retval None + */ +void IRQ059_Handler(void) +{ + m_apfnIrqHandler[Int059_IRQn](); +} + +/** + * @brief Interrupt No.060 IRQ handler + * @param None + * @retval None + */ +void IRQ060_Handler(void) +{ + m_apfnIrqHandler[Int060_IRQn](); +} + +/** + * @brief Interrupt No.061 IRQ handler + * @param None + * @retval None + */ +void IRQ061_Handler(void) +{ + m_apfnIrqHandler[Int061_IRQn](); +} + +/** + * @brief Interrupt No.062 IRQ handler + * @param None + * @retval None + */ +void IRQ062_Handler(void) +{ + m_apfnIrqHandler[Int062_IRQn](); +} + +/** + * @brief Interrupt No.063 IRQ handler + * @param None + * @retval None + */ +void IRQ063_Handler(void) +{ + m_apfnIrqHandler[Int063_IRQn](); +} + +/** + * @brief Interrupt No.064 IRQ handler + * @param None + * @retval None + */ +void IRQ064_Handler(void) +{ + m_apfnIrqHandler[Int064_IRQn](); +} + +/** + * @brief Interrupt No.065 IRQ handler + * @param None + * @retval None + */ +void IRQ065_Handler(void) +{ + m_apfnIrqHandler[Int065_IRQn](); +} + +/** + * @brief Interrupt No.066 IRQ handler + * @param None + * @retval None + */ +void IRQ066_Handler(void) +{ + m_apfnIrqHandler[Int066_IRQn](); +} + +/** + * @brief Interrupt No.067 IRQ handler + * @param None + * @retval None + */ +void IRQ067_Handler(void) +{ + m_apfnIrqHandler[Int067_IRQn](); +} + +/** + * @brief Interrupt No.068 IRQ handler + * @param None + * @retval None + */ +void IRQ068_Handler(void) +{ + m_apfnIrqHandler[Int068_IRQn](); +} + +/** + * @brief Interrupt No.069 IRQ handler + * @param None + * @retval None + */ +void IRQ069_Handler(void) +{ + m_apfnIrqHandler[Int069_IRQn](); +} + +/** + * @brief Interrupt No.070 IRQ handler + * @param None + * @retval None + */ +void IRQ070_Handler(void) +{ + m_apfnIrqHandler[Int070_IRQn](); +} + +/** + * @brief Interrupt No.071 IRQ handler + * @param None + * @retval None + */ +void IRQ071_Handler(void) +{ + m_apfnIrqHandler[Int071_IRQn](); +} + +/** + * @brief Interrupt No.072 IRQ handler + * @param None + * @retval None + */ +void IRQ072_Handler(void) +{ + m_apfnIrqHandler[Int072_IRQn](); +} + +/** + * @brief Interrupt No.073 IRQ handler + * @param None + * @retval None + */ +void IRQ073_Handler(void) +{ + m_apfnIrqHandler[Int073_IRQn](); +} + +/** + * @brief Interrupt No.074 IRQ handler + * @param None + * @retval None + */ +void IRQ074_Handler(void) +{ + m_apfnIrqHandler[Int074_IRQn](); +} + +/** + * @brief Interrupt No.075 IRQ handler + * @param None + * @retval None + */ +void IRQ075_Handler(void) +{ + m_apfnIrqHandler[Int075_IRQn](); +} + +/** + * @brief Interrupt No.076 IRQ handler + * @param None + * @retval None + */ +void IRQ076_Handler(void) +{ + m_apfnIrqHandler[Int076_IRQn](); +} + +/** + * @brief Interrupt No.077 IRQ handler + * @param None + * @retval None + */ +void IRQ077_Handler(void) +{ + m_apfnIrqHandler[Int077_IRQn](); +} + +/** + * @brief Interrupt No.078 IRQ handler + * @param None + * @retval None + */ +void IRQ078_Handler(void) +{ + m_apfnIrqHandler[Int078_IRQn](); +} + +/** + * @brief Interrupt No.079 IRQ handler + * @param None + * @retval None + */ +void IRQ079_Handler(void) +{ + m_apfnIrqHandler[Int079_IRQn](); +} + +/** + * @brief Interrupt No.080 IRQ handler + * @param None + * @retval None + */ +void IRQ080_Handler(void) +{ + m_apfnIrqHandler[Int080_IRQn](); +} + +/** + * @brief Interrupt No.081 IRQ handler + * @param None + * @retval None + */ +void IRQ081_Handler(void) +{ + m_apfnIrqHandler[Int081_IRQn](); +} + +/** + * @brief Interrupt No.082 IRQ handler + * @param None + * @retval None + */ +void IRQ082_Handler(void) +{ + m_apfnIrqHandler[Int082_IRQn](); +} + +/** + * @brief Interrupt No.083 IRQ handler + * @param None + * @retval None + */ +void IRQ083_Handler(void) +{ + m_apfnIrqHandler[Int083_IRQn](); +} + +/** + * @brief Interrupt No.084 IRQ handler + * @param None + * @retval None + */ +void IRQ084_Handler(void) +{ + m_apfnIrqHandler[Int084_IRQn](); +} + +/** + * @brief Interrupt No.085 IRQ handler + * @param None + * @retval None + */ +void IRQ085_Handler(void) +{ + m_apfnIrqHandler[Int085_IRQn](); +} + +/** + * @brief Interrupt No.086 IRQ handler + * @param None + * @retval None + */ +void IRQ086_Handler(void) +{ + m_apfnIrqHandler[Int086_IRQn](); +} + +/** + * @brief Interrupt No.087 IRQ handler + * @param None + * @retval None + */ +void IRQ087_Handler(void) +{ + m_apfnIrqHandler[Int087_IRQn](); +} + +/** + * @brief Interrupt No.088 IRQ handler + * @param None + * @retval None + */ +void IRQ088_Handler(void) +{ + m_apfnIrqHandler[Int088_IRQn](); +} + +/** + * @brief Interrupt No.089 IRQ handler + * @param None + * @retval None + */ +void IRQ089_Handler(void) +{ + m_apfnIrqHandler[Int089_IRQn](); +} + +/** + * @brief Interrupt No.090 IRQ handler + * @param None + * @retval None + */ +void IRQ090_Handler(void) +{ + m_apfnIrqHandler[Int090_IRQn](); +} + +/** + * @brief Interrupt No.091 IRQ handler + * @param None + * @retval None + */ +void IRQ091_Handler(void) +{ + m_apfnIrqHandler[Int091_IRQn](); +} + +/** + * @brief Interrupt No.092 IRQ handler + * @param None + * @retval None + */ +void IRQ092_Handler(void) +{ + m_apfnIrqHandler[Int092_IRQn](); +} + +/** + * @brief Interrupt No.093 IRQ handler + * @param None + * @retval None + */ +void IRQ093_Handler(void) +{ + m_apfnIrqHandler[Int093_IRQn](); +} + +/** + * @brief Interrupt No.094 IRQ handler + * @param None + * @retval None + */ +void IRQ094_Handler(void) +{ + m_apfnIrqHandler[Int094_IRQn](); +} + +/** + * @brief Interrupt No.095 IRQ handler + * @param None + * @retval None + */ +void IRQ095_Handler(void) +{ + m_apfnIrqHandler[Int095_IRQn](); +} + +/** + * @brief Interrupt No.096 IRQ handler + * @param None + * @retval None + */ +void IRQ096_Handler(void) +{ + m_apfnIrqHandler[Int096_IRQn](); +} + +/** + * @brief Interrupt No.097 IRQ handler + * @param None + * @retval None + */ +void IRQ097_Handler(void) +{ + m_apfnIrqHandler[Int097_IRQn](); +} + +/** + * @brief Interrupt No.098 IRQ handler + * @param None + * @retval None + */ +void IRQ098_Handler(void) +{ + m_apfnIrqHandler[Int098_IRQn](); +} + +/** + * @brief Interrupt No.099 IRQ handler + * @param None + * @retval None + */ +void IRQ099_Handler(void) +{ + m_apfnIrqHandler[Int099_IRQn](); +} + +/** + * @brief Interrupt No.100 IRQ handler + * @param None + * @retval None + */ +void IRQ100_Handler(void) +{ + m_apfnIrqHandler[Int100_IRQn](); +} + +/** + * @brief Interrupt No.101 IRQ handler + * @param None + * @retval None + */ +void IRQ101_Handler(void) +{ + m_apfnIrqHandler[Int101_IRQn](); +} + +/** + * @brief Interrupt No.102 IRQ handler + * @param None + * @retval None + */ +void IRQ102_Handler(void) +{ + m_apfnIrqHandler[Int102_IRQn](); +} + +/** + * @brief Interrupt No.103 IRQ handler + * @param None + * @retval None + */ +void IRQ103_Handler(void) +{ + m_apfnIrqHandler[Int103_IRQn](); +} + +/** + * @brief Interrupt No.104 IRQ handler + * @param None + * @retval None + */ +void IRQ104_Handler(void) +{ + m_apfnIrqHandler[Int104_IRQn](); +} + +/** + * @brief Interrupt No.105 IRQ handler + * @param None + * @retval None + */ +void IRQ105_Handler(void) +{ + m_apfnIrqHandler[Int105_IRQn](); +} + +/** + * @brief Interrupt No.106 IRQ handler + * @param None + * @retval None + */ +void IRQ106_Handler(void) +{ + m_apfnIrqHandler[Int106_IRQn](); +} + +/** + * @brief Interrupt No.107 IRQ handler + * @param None + * @retval None + */ +void IRQ107_Handler(void) +{ + m_apfnIrqHandler[Int107_IRQn](); +} + +/** + * @brief Interrupt No.108 IRQ handler + * @param None + * @retval None + */ +void IRQ108_Handler(void) +{ + m_apfnIrqHandler[Int108_IRQn](); +} + +/** + * @brief Interrupt No.109 IRQ handler + * @param None + * @retval None + */ +void IRQ109_Handler(void) +{ + m_apfnIrqHandler[Int109_IRQn](); +} + +/** + * @brief Interrupt No.110 IRQ handler + * @param None + * @retval None + */ +void IRQ110_Handler(void) +{ + m_apfnIrqHandler[Int110_IRQn](); +} + +/** + * @brief Interrupt No.111 IRQ handler + * @param None + * @retval None + */ +void IRQ111_Handler(void) +{ + m_apfnIrqHandler[Int111_IRQn](); +} + +/** + * @brief Interrupt No.112 IRQ handler + * @param None + * @retval None + */ +void IRQ112_Handler(void) +{ + m_apfnIrqHandler[Int112_IRQn](); +} + +/** + * @brief Interrupt No.113 IRQ handler + * @param None + * @retval None + */ +void IRQ113_Handler(void) +{ + m_apfnIrqHandler[Int113_IRQn](); +} + +/** + * @brief Interrupt No.114 IRQ handler + * @param None + * @retval None + */ +void IRQ114_Handler(void) +{ + m_apfnIrqHandler[Int114_IRQn](); +} + +/** + * @brief Interrupt No.115 IRQ handler + * @param None + * @retval None + */ +void IRQ115_Handler(void) +{ + m_apfnIrqHandler[Int115_IRQn](); +} + +/** + * @brief Interrupt No.116 IRQ handler + * @param None + * @retval None + */ +void IRQ116_Handler(void) +{ + m_apfnIrqHandler[Int116_IRQn](); +} + +/** + * @brief Interrupt No.117 IRQ handler + * @param None + * @retval None + */ +void IRQ117_Handler(void) +{ + m_apfnIrqHandler[Int117_IRQn](); +} + +/** + * @brief Interrupt No.118 IRQ handler + * @param None + * @retval None + */ +void IRQ118_Handler(void) +{ + m_apfnIrqHandler[Int118_IRQn](); +} + +/** + * @brief Interrupt No.119 IRQ handler + * @param None + * @retval None + */ +void IRQ119_Handler(void) +{ + m_apfnIrqHandler[Int119_IRQn](); +} + +/** + * @brief Interrupt No.120 IRQ handler + * @param None + * @retval None + */ +void IRQ120_Handler(void) +{ + m_apfnIrqHandler[Int120_IRQn](); +} + +/** + * @brief Interrupt No.121 IRQ handler + * @param None + * @retval None + */ +void IRQ121_Handler(void) +{ + m_apfnIrqHandler[Int121_IRQn](); +} + +/** + * @brief Interrupt No.122 IRQ handler + * @param None + * @retval None + */ +void IRQ122_Handler(void) +{ + m_apfnIrqHandler[Int122_IRQn](); +} + +/** + * @brief Interrupt No.123 IRQ handler + * @param None + * @retval None + */ +void IRQ123_Handler(void) +{ + m_apfnIrqHandler[Int123_IRQn](); +} + +/** + * @brief Interrupt No.124 IRQ handler + * @param None + * @retval None + */ +void IRQ124_Handler(void) +{ + m_apfnIrqHandler[Int124_IRQn](); +} + +/** + * @brief Interrupt No.125 IRQ handler + * @param None + * @retval None + */ +void IRQ125_Handler(void) +{ + m_apfnIrqHandler[Int125_IRQn](); +} + +/** + * @brief Interrupt No.126 IRQ handler + * @param None + * @retval None + */ +void IRQ126_Handler(void) +{ + m_apfnIrqHandler[Int126_IRQn](); +} + +/** + * @brief Interrupt No.127 IRQ handler + * @param None + * @retval None + */ +void IRQ127_Handler(void) +{ + m_apfnIrqHandler[Int127_IRQn](); +} + +/** + * @brief Interrupt No.128 share IRQ handler + * @param None + * @retval None + */ +void IRQ128_Handler(void) +{ + const uint32_t VSSEL128 = M4_INTC->VSSEL128; + + /* external interrupt 00 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR0) && (0UL != (VSSEL128 & BIT_MASK_00))) + { + EXTINT_00_IrqHandler(); + } + /* external interrupt 01 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR1) && (0UL != (VSSEL128 & BIT_MASK_01))) + { + EXTINT_01_IrqHandler(); + } + /* external interrupt 02 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR2) && (0UL != (VSSEL128 & BIT_MASK_02))) + { + EXTINT_02_IrqHandler(); + } + /* external interrupt 03 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR3) && (0UL != (VSSEL128 & BIT_MASK_03))) + { + EXTINT_03_IrqHandler(); + } + /* external interrupt 04 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR4) && (0UL != (VSSEL128 & BIT_MASK_04))) + { + EXTINT_04_IrqHandler(); + } + /* external interrupt 05 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR5) && (0UL != (VSSEL128 & BIT_MASK_05))) + { + EXTINT_05_IrqHandler(); + } + /* external interrupt 06 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR6) && (0UL != (VSSEL128 & BIT_MASK_06))) + { + EXTINT_06_IrqHandler(); + } + /* external interrupt 07 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR7) && (0UL != (VSSEL128 & BIT_MASK_07))) + { + EXTINT_07_IrqHandler(); + } + /* external interrupt 08 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR8) && (0UL != (VSSEL128 & BIT_MASK_08))) + { + EXTINT_08_IrqHandler(); + } + /* external interrupt 09 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR9) && (0UL != (VSSEL128 & BIT_MASK_09))) + { + EXTINT_09_IrqHandler(); + } + /* external interrupt 10 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR10) && (0UL != (VSSEL128 & BIT_MASK_10))) + { + EXTINT_10_IrqHandler(); + } + /* external interrupt 11 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR11) && (0UL != (VSSEL128 & BIT_MASK_11))) + { + EXTINT_11_IrqHandler(); + } + /* external interrupt 12 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR12) && (0UL != (VSSEL128 & BIT_MASK_12))) + { + EXTINT_12_IrqHandler(); + } + /* external interrupt 13 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR13) && (0UL != (VSSEL128 & BIT_MASK_13))) + { + EXTINT_13_IrqHandler(); + } + /* external interrupt 14 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR14) && (0UL != (VSSEL128 & BIT_MASK_14))) + { + EXTINT_14_IrqHandler(); + } + /* external interrupt 15 */ + if ((1UL == bM4_INTC->EIFR_b.EIFR15) && (0UL != (VSSEL128 & BIT_MASK_15))) + { + EXTINT_15_IrqHandler(); + } +} + +/** + * @brief Interrupt No.129 share IRQ handler + * @param None + * @retval None + */ +void IRQ129_Handler(void) +{ + const uint32_t VSSEL129 = M4_INTC->VSSEL129; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* DMA1 Ch.0 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL0_b.IE) + { + /* DMA1 Ch.0 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC0) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC0) && (0UL != (VSSEL129 & BIT_MASK_00))) + { + DMA_1_Tc0_IrqHandler(); + } + } + /* DMA1 ch.0 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC0) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC0) && (0UL != (VSSEL129 & BIT_MASK_08))) + { + DMA_1_Btc0_IrqHandler(); + } + } + /* DMA1 ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err0_IrqHandler(); + } + } + /* DMA1 Ch.1 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL1_b.IE) + { + /* DMA1 Ch.1 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC1) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC1) && (0UL != (VSSEL129 & BIT_MASK_01))) + { + DMA_1_Tc1_IrqHandler(); + } + } + /* DMA1 ch.1 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC1) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC1) && (0UL != (VSSEL129 & BIT_MASK_09))) + { + DMA_1_Btc1_IrqHandler(); + } + } + /* DMA1 ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err1_IrqHandler(); + } + } + /* DMA1 Ch.2 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL2_b.IE) + { + /* DMA1 Ch.2 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC2) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC2) && (0UL != (VSSEL129 & BIT_MASK_02))) + { + DMA_1_Tc2_IrqHandler(); + } + } + /* DMA1 ch.2 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC2) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC2) && (0UL != (VSSEL129 & BIT_MASK_10))) + { + DMA_1_Btc2_IrqHandler(); + } + } + /* DMA1 ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err2_IrqHandler(); + } + } + /* DMA1 Ch.3 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL3_b.IE) + { + /* DMA1 Ch.3 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC3) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC3) && (0UL != (VSSEL129 & BIT_MASK_03))) + { + DMA_1_Tc3_IrqHandler(); + } + } + /* DMA1 ch.3 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC3) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC3) && (0UL != (VSSEL129 & BIT_MASK_11))) + { + DMA_1_Btc3_IrqHandler(); + } + } + /* DMA1 ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err3_IrqHandler(); + } + } + /* DMA1 Ch.4 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL4_b.IE) + { + /* DMA1 Ch.4 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC4) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC4) && (0UL != (VSSEL129 & BIT_MASK_04))) + { + DMA_1_Tc4_IrqHandler(); + } + } + /* DMA1 ch.4 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC4) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC4) && (0UL != (VSSEL129 & BIT_MASK_12))) + { + DMA_1_Btc4_IrqHandler(); + } + } + /* DMA1 ch.4 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_04 | BIT_MASK_20); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_04 | BIT_MASK_20)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err4_IrqHandler(); + } + } + /* DMA1 Ch.5 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL5_b.IE) + { + /* DMA1 Ch.5 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC5) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC5) && (0UL != (VSSEL129 & BIT_MASK_05))) + { + DMA_1_Tc5_IrqHandler(); + } + } + /* DMA1 ch.5 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC5) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC5) && (0UL != (VSSEL129 & BIT_MASK_13))) + { + DMA_1_Btc5_IrqHandler(); + } + } + /* DMA1 ch.5 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_05 | BIT_MASK_21); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_05 | BIT_MASK_21)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err5_IrqHandler(); + } + } + /* DMA1 Ch.6 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL6_b.IE) + { + /* DMA1 Ch.6 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC6) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC6) && (0UL != (VSSEL129 & BIT_MASK_06))) + { + DMA_1_Tc6_IrqHandler(); + } + } + /* DMA1 ch.6 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC6) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC6) && (0UL != (VSSEL129 & BIT_MASK_14))) + { + DMA_1_Btc6_IrqHandler(); + } + } + /* DMA1 ch.6 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_06 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_06 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err6_IrqHandler(); + } + } + /* DMA1 Ch.7 interrupt enabled */ + if (1UL == bM4_DMA1->CHCTL7_b.IE) + { + /* DMA1 Ch.7 Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKTC7) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.TC7) && (0UL != (VSSEL129 & BIT_MASK_07))) + { + DMA_1_Tc7_IrqHandler(); + } + } + /* DMA1 ch.7 Block Tx completed */ + if (0UL == bM4_DMA1->INTMASK1_b.MSKBTC7) + { + if ((1UL == bM4_DMA1->INTSTAT1_b.BTC7) && (0UL != (VSSEL129 & BIT_MASK_15))) + { + DMA_1_Btc7_IrqHandler(); + } + } + /* DMA1 ch.7 Transfer/Request Error */ + u32Tmp1 = M4_DMA1->INTSTAT0 & (BIT_MASK_07 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(M4_DMA1->INTMASK0) & (BIT_MASK_07 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL129 & BIT_MASK_16))) + { + DMA_1_Err7_IrqHandler(); + } + } + /* EFM error */ + if (0UL != bM4_EFM->FITE_b.PEERRITE) + { + /* EFM program/erase/protect/otp error */ + u32Tmp1 = M4_EFM->FSR & (EFM_FSR_PRTWERR0 | EFM_FSR_PGSZERR0 | EFM_FSR_MISMTCH0 | \ + EFM_FSR_PRTWERR1 | EFM_FSR_PGSZERR1 | EFM_FSR_MISMTCH1 | \ + EFM_FSR_OTPWERR0); + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_17))) + { + EFM_PgmEraseErr_IrqHandler(); + } + } + /* EFM read collision */ + if (0UL != bM4_EFM->FITE_b.COLERRITE) + { + /* EFM read collision */ + u32Tmp1 = M4_EFM->FSR & (EFM_FSR_COLERR0 | EFM_FSR_COLERR1); + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_18))) + { + EFM_ColErr_IrqHandler(); + } + } + /* EFM operate end */ + if (0UL != bM4_EFM->FITE_b.OPTENDITE) + { + /* EFM operate end */ + u32Tmp1 = M4_EFM->FSR & (EFM_FSR_OPTEND0 | EFM_FSR_OPTEND1); + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_19))) + { + EFM_OpEnd_IrqHandler(); + } + } + /* QSPI access error */ + u32Tmp1 = M4_QSPI->SR & QSPI_SR_RAER; + if ((0UL != u32Tmp1) && (0UL != (VSSEL129 & BIT_MASK_22))) + { + QSPI_Err_IrqHandler(); + } + /*DCU1 */ + u32Tmp1 = M4_DCU1->INTEVTSEL; + u32Tmp2 = M4_DCU1->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_23))) + { + DCU_1_IrqHandler(); + } + /*DCU2 */ + u32Tmp1 = M4_DCU2->INTEVTSEL; + u32Tmp2 = M4_DCU2->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_24))) + { + DCU_2_IrqHandler(); + } + /*DCU3 */ + u32Tmp1 = M4_DCU3->INTEVTSEL; + u32Tmp2 = M4_DCU3->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_25))) + { + DCU_3_IrqHandler(); + } + /*DCU4 */ + u32Tmp1 = M4_DCU4->INTEVTSEL; + u32Tmp2 = M4_DCU4->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_26))) + { + DCU_4_IrqHandler(); + } + /*DCU5 */ + u32Tmp1 = M4_DCU5->INTEVTSEL; + u32Tmp2 = M4_DCU5->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_27))) + { + DCU_5_IrqHandler(); + } + /*DCU6 */ + u32Tmp1 = M4_DCU6->INTEVTSEL; + u32Tmp2 = M4_DCU6->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_28))) + { + DCU_6_IrqHandler(); + } + /*DCU7 */ + u32Tmp1 = M4_DCU7->INTEVTSEL; + u32Tmp2 = M4_DCU7->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_29))) + { + DCU_7_IrqHandler(); + } + /*DCU8 */ + u32Tmp1 = M4_DCU8->INTEVTSEL; + u32Tmp2 = M4_DCU8->FLAG; + if ((0UL != ((u32Tmp1) & (u32Tmp2) & 0x0E7FUL)) && (0UL != (VSSEL129 & BIT_MASK_30))) + { + DCU_8_IrqHandler(); + } +} + +/** + * @brief Interrupt No.130 share IRQ handler + * @param None + * @retval None + */ +void IRQ130_Handler(void) +{ + const uint32_t VSSEL130 = M4_INTC->VSSEL130; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* MAU square */ + if (0UL != (VSSEL130 & BIT_MASK_19)) + { + MAU_Sqrt_IrqHandler(); + } + else + { + /* DMA2 Ch.0 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL0_b.IE) + { + /* DMA2 Ch.0 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC0) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC0) && (0UL != (VSSEL130 & BIT_MASK_00))) + { + DMA_2_Tc0_IrqHandler(); + } + } + /* DMA2 ch.0 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC0) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC0) && (0UL != (VSSEL130 & BIT_MASK_08))) + { + DMA_2_Btc0_IrqHandler(); + } + } + /* DMA2 ch.0 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_00 | BIT_MASK_16); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_00 | BIT_MASK_16)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err0_IrqHandler(); + } + } + /* DMA2 Ch.1 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL1_b.IE) + { + /* DMA2 Ch.1 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC1) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC1) && (0UL != (VSSEL130 & BIT_MASK_01))) + { + DMA_2_Tc1_IrqHandler(); + } + } + /* DMA2 ch.1 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC1) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC1) && (0UL != (VSSEL130 & BIT_MASK_09))) + { + DMA_2_Btc1_IrqHandler(); + } + } + /* DMA2 ch.1 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_01 | BIT_MASK_17); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_01 | BIT_MASK_17)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err1_IrqHandler(); + } + } + /* DMA2 Ch.2 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL2_b.IE) + { + /* DMA2 Ch.2 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC2) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC2) && (0UL != (VSSEL130 & BIT_MASK_02))) + { + DMA_2_Tc2_IrqHandler(); + } + } + /* DMA2 ch.2 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC2) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC2) && (0UL != (VSSEL130 & BIT_MASK_10))) + { + DMA_2_Btc2_IrqHandler(); + } + } + /* DMA2 ch.2 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_02 | BIT_MASK_18); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_02 | BIT_MASK_18)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err2_IrqHandler(); + } + } + /* DMA2 Ch.3 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL3_b.IE) + { + /* DMA2 Ch.3 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC3) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC3) && (0UL != (VSSEL130 & BIT_MASK_03))) + { + DMA_2_Tc3_IrqHandler(); + } + } + /* DMA2 ch.3 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC3) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC3) && (0UL != (VSSEL130 & BIT_MASK_11))) + { + DMA_2_Btc3_IrqHandler(); + } + } + /* DMA2 ch.3 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_03 | BIT_MASK_19); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_03 | BIT_MASK_19)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err3_IrqHandler(); + } + } + /* DMA2 Ch.4 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL4_b.IE) + { + /* DMA2 Ch.4 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC4) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC4) && (0UL != (VSSEL130 & BIT_MASK_04))) + { + DMA_2_Tc4_IrqHandler(); + } + } + /* DMA2 ch.4 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC4) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC4) && (0UL != (VSSEL130 & BIT_MASK_12))) + { + DMA_2_Btc4_IrqHandler(); + } + } + /* DMA2 ch.4 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_04 | BIT_MASK_20); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_04 | BIT_MASK_20)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err4_IrqHandler(); + } + } + /* DMA2 Ch.5 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL5_b.IE) + { + /* DMA2 Ch.5 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC5) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC5) && (0UL != (VSSEL130 & BIT_MASK_05))) + { + DMA_2_Tc5_IrqHandler(); + } + } + /* DMA2 ch.5 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC5) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC5) && (0UL != (VSSEL130 & BIT_MASK_13))) + { + DMA_2_Btc5_IrqHandler(); + } + } + /* DMA2 ch.5 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_05 | BIT_MASK_21); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_05 | BIT_MASK_21)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err5_IrqHandler(); + } + } + /* DMA2 Ch.6 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL6_b.IE) + { + /* DMA2 Ch.6 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC6) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC6) && (0UL != (VSSEL130 & BIT_MASK_06))) + { + DMA_2_Tc6_IrqHandler(); + } + } + /* DMA2 ch.6 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC6) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC6) && (0UL != (VSSEL130 & BIT_MASK_14))) + { + DMA_2_Btc6_IrqHandler(); + } + } + /* DMA2 ch.6 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_06 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_06 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err6_IrqHandler(); + } + } + /* DMA2 Ch.7 interrupt enabled */ + if (1UL == bM4_DMA2->CHCTL7_b.IE) + { + /* DMA2 Ch.7 Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKTC7) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.TC7) && (0UL != (VSSEL130 & BIT_MASK_07))) + { + DMA_2_Tc7_IrqHandler(); + } + } + /* DMA2 ch.7 Block Tx completed */ + if (0UL == bM4_DMA2->INTMASK1_b.MSKBTC7) + { + if ((1UL == bM4_DMA2->INTSTAT1_b.BTC7) && (0UL != (VSSEL130 & BIT_MASK_15))) + { + DMA_2_Btc7_IrqHandler(); + } + } + /* DMA2 ch.7 Transfer/Request Error */ + u32Tmp1 = M4_DMA2->INTSTAT0 & (BIT_MASK_07 | BIT_MASK_22); + u32Tmp2 = (uint32_t)(~(M4_DMA2->INTMASK0) & (BIT_MASK_07 | BIT_MASK_22)); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL130 & BIT_MASK_16))) + { + DMA_2_Err7_IrqHandler(); + } + } + /* DVP frame start */ + if (1UL == bM4_DVP->IER_b.FSIEN) + { + if ((1UL == bM4_DVP->STR_b.FSF) && (0UL != (VSSEL130 & BIT_MASK_20))) + { + DVP_FrameStart_IrqHandler(); + } + } + /* DVP line start */ + if (1UL == bM4_DVP->IER_b.LSIEN) + { + if ((1UL == bM4_DVP->STR_b.LSF) && (0UL != (VSSEL130 & BIT_MASK_21))) + { + DVP_LineStart_IrqHandler(); + } + } + /* DVP line end */ + if (1UL == bM4_DVP->IER_b.LEIEN) + { + if ((1UL == bM4_DVP->STR_b.LEF) && (0UL != (VSSEL130 & BIT_MASK_22))) + { + DVP_LineEnd_IrqHandler(); + } + } + /* DVP frame end */ + if (1UL == bM4_DVP->IER_b.FEIEN) + { + if ((1UL == bM4_DVP->STR_b.FEF) && (0UL != (VSSEL130 & BIT_MASK_23))) + { + DVP_FrameEnd_IrqHandler(); + } + } + /* DVP software sync err */ + if (1UL == bM4_DVP->IER_b.SQUERIEN) + { + if ((1UL == bM4_DVP->STR_b.SQUERF) && (0UL != (VSSEL130 & BIT_MASK_24))) + { + DVP_SwSyncErr_IrqHandler(); + } + } + /* DVP fifo overfolw err */ + if (1UL == bM4_DVP->IER_b.FIFOERIEN) + { + if ((1UL == bM4_DVP->STR_b.FIFOERF) && (0UL != (VSSEL130 & BIT_MASK_25))) + { + DVP_FifoErr_IrqHandler(); + } + } + /* FMAC 1 */ + if (1UL == bM4_FMAC1->IER_b.INTEN) + { + if ((1UL == bM4_FMAC1->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_27))) + { + FMAC_1_IrqHandler(); + } + } + /* FMAC 2 */ + if (1UL == bM4_FMAC2->IER_b.INTEN) + { + if ((1UL == bM4_FMAC2->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_28))) + { + FMAC_2_IrqHandler(); + } + } + /* FMAC 3 */ + if (1UL == bM4_FMAC3->IER_b.INTEN) + { + if ((1UL == bM4_FMAC3->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_29))) + { + FMAC_3_IrqHandler(); + } + } + /* FMAC 4 */ + if (1UL == bM4_FMAC4->IER_b.INTEN) + { + if ((1UL == bM4_FMAC4->STR_b.READY) && (0UL != (VSSEL130 & BIT_MASK_30))) + { + FMAC_4_IrqHandler(); + } + } + } +} + +/** + * @brief Interrupt No.131 share IRQ handler + * @param None + * @retval None + */ +void IRQ131_Handler(void) +{ + const uint32_t VSSEL131 = M4_INTC->VSSEL131; + uint32_t u32Tmp1; + + /* Timer0 unit1, Ch.A compare match */ + if (1UL == bM4_TMR0_1->BCONR_b.INTENA) + { + if ((1UL ==bM4_TMR0_1->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_00))) + { + TMR0_1_CmpA_IrqHandler(); + } + } + /* Timer0 unit1, Ch.B compare match */ + if (1UL == bM4_TMR0_1->BCONR_b.INTENB) + { + if ((1UL ==bM4_TMR0_1->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_01))) + { + TMR0_1_CmpB_IrqHandler(); + } + } + /* Timer0 unit2, Ch.A compare match */ + if (1UL == bM4_TMR0_2->BCONR_b.INTENA) + { + if ((1UL ==bM4_TMR0_2->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_02))) + { + TMR0_2_CmpA_IrqHandler(); + } + } + /* Timer0 unit2, Ch.B compare match */ + if (1UL == bM4_TMR0_2->BCONR_b.INTENB) + { + if ((1UL ==bM4_TMR0_2->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_03))) + { + TMR0_2_CmpB_IrqHandler(); + } + } + /* Timer2 unit1, Ch.A compare match */ + if (1UL == bM4_TMR2_1->ICONR_b.CMENA) + { + if ((1UL == bM4_TMR2_1->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_04))) + { + TMR2_1_CmpA_IrqHandler(); + } + } + /* Timer2 unit1, Ch.B compare match */ + if (1UL == bM4_TMR2_1->ICONR_b.CMENB) + { + if ((1UL == bM4_TMR2_1->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_05))) + { + TMR2_1_CmpB_IrqHandler(); + } + } + /* Timer2 unit1, Ch.A overflow */ + if (1UL == bM4_TMR2_1->ICONR_b.OVENA) + { + if ((1UL == bM4_TMR2_1->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_06))) + { + TMR2_1_OvfA_IrqHandler(); + } + } + /* Timer2 unit1, Ch.B overflow */ + if (1UL == bM4_TMR2_1->ICONR_b.OVENB) + { + if ((1UL == bM4_TMR2_1->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_07))) + { + TMR2_1_OvfB_IrqHandler(); + } + } + /* Timer2 unit2, Ch.A compare match */ + if (1UL == bM4_TMR2_2->ICONR_b.CMENA) + { + if ((1UL == bM4_TMR2_2->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_08))) + { + TMR2_2_CmpA_IrqHandler(); + } + } + /* Timer2 unit2, Ch.B compare match */ + if (1UL == bM4_TMR2_2->ICONR_b.CMENB) + { + if ((1UL == bM4_TMR2_2->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_09))) + { + TMR2_2_CmpB_IrqHandler(); + } + } + /* Timer2 unit2, Ch.A overflow */ + if (1UL == bM4_TMR2_2->ICONR_b.OVENA) + { + if ((1UL == bM4_TMR2_2->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_10))) + { + TMR2_2_OvfA_IrqHandler(); + } + } + /* Timer2 unit2, Ch.B overflow */ + if (1UL == bM4_TMR2_2->ICONR_b.OVENB) + { + if ((1UL == bM4_TMR2_2->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_11))) + { + TMR2_2_OvfB_IrqHandler(); + } + } + /* Timer2 unit3, Ch.A compare match */ + if (1UL == bM4_TMR2_3->ICONR_b.CMENA) + { + if ((1UL == bM4_TMR2_3->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_12))) + { + TMR2_3_CmpA_IrqHandler(); + } + } + /* Timer2 unit3, Ch.B compare match */ + if (1UL == bM4_TMR2_3->ICONR_b.CMENB) + { + if ((1UL == bM4_TMR2_3->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_13))) + { + TMR2_3_CmpB_IrqHandler(); + } + } + /* Timer2 unit3, Ch.A overflow */ + if (1UL == bM4_TMR2_3->ICONR_b.OVENA) + { + if ((1UL == bM4_TMR2_3->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_14))) + { + TMR2_3_OvfA_IrqHandler(); + } + } + /* Timer2 unit3, Ch.B overflow */ + if (1UL == bM4_TMR2_3->ICONR_b.OVENB) + { + if ((1UL == bM4_TMR2_3->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_15))) + { + TMR2_3_OvfB_IrqHandler(); + } + } + /* Timer2 unit4, Ch.A compare match */ + if (1UL == bM4_TMR2_4->ICONR_b.CMENA) + { + if ((1UL == bM4_TMR2_4->STFLR_b.CMFA) && (0UL != (VSSEL131 & BIT_MASK_16))) + { + TMR2_4_CmpA_IrqHandler(); + } + } + /* Timer2 unit4, Ch.B compare match */ + if (1UL == bM4_TMR2_4->ICONR_b.CMENB) + { + if ((1UL == bM4_TMR2_4->STFLR_b.CMFB) && (0UL != (VSSEL131 & BIT_MASK_17))) + { + TMR2_4_CmpB_IrqHandler(); + } + } + /* Timer2 unit4, Ch.A overflow */ + if (1UL == bM4_TMR2_4->ICONR_b.OVENA) + { + if ((1UL == bM4_TMR2_4->STFLR_b.OVFA) && (0UL != (VSSEL131 & BIT_MASK_18))) + { + TMR2_4_OvfA_IrqHandler(); + } + } + /* Timer2 unit4, Ch.B overflow */ + if (1UL == bM4_TMR2_4->ICONR_b.OVENB) + { + if ((1UL == bM4_TMR2_4->STFLR_b.OVFB) && (0UL != (VSSEL131 & BIT_MASK_19))) + { + TMR2_4_OvfB_IrqHandler(); + } + } + /* RTC time stamp 0 */ + if (1UL == bM4_RTC->TPCR0_b.TPIE0) + { + if ((1UL == bM4_RTC->TPSR_b.TPF0) && (0UL != (VSSEL131 & BIT_MASK_24))) + { + RTC_TimeStamp0_IrqHandler(); + } + } + /* RTC time stamp 1 */ + if (1UL == bM4_RTC->TPCR1_b.TPIE1) + { + if ((1UL == bM4_RTC->TPSR_b.TPF1) && (0UL != (VSSEL131 & BIT_MASK_24))) + { + RTC_TimeStamp1_IrqHandler(); + } + } + /* RTC alarm */ + if (1UL == bM4_RTC->CR2_b.ALMIE) + { + if ((1UL == bM4_RTC->CR2_b.ALMF) && (0UL != (VSSEL131 & BIT_MASK_25))) + { + RTC_Alarm_IrqHandler(); + } + } + /* RTC period */ + if (1UL == bM4_RTC->CR2_b.PRDIE) + { + if ((1UL == bM4_RTC->CR2_b.PRDF) && (0UL != (VSSEL131 & BIT_MASK_26))) + { + RTC_Period_IrqHandler(); + } + } + /* XTAL stop */ + if (1UL == bM4_CMU->XTALSTDCR_b.XTALSTDIE) + { + if ((1UL == bM4_CMU->XTALSTDSR_b.XTALSTDF) && (0UL != (VSSEL131 & BIT_MASK_29))) + { + CLK_XtalStop_IrqHandler(); + } + } + /* Wakeup timer overflow */ + if (1UL == bM4_PWC->WKTC2_b.WKTCE) + { + if ((1UL == bM4_PWC->WKTC2_b.WKOVF) && (0UL != (VSSEL131 & BIT_MASK_30))) + { + PWC_WakeupTimer_IrqHandler(); + } + } + /* SWDT underflow or refresh error */ + u32Tmp1 = M4_SWDT->SR & (SWDT_SR_UDF | SWDT_SR_REF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL131 & BIT_MASK_31))) + { + SWDT_IrqHandler(); + } +} + +/** + * @brief Interrupt No.132 share IRQ handler + * @param None + * @retval None + */ +void IRQ132_Handler(void) +{ + const uint32_t VSSEL132 = M4_INTC->VSSEL132; + + /* Timer6 Ch.1 general compare match A */ + if (1UL == bM4_TMR6_1->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMAF) && (0UL != (VSSEL132 & BIT_MASK_00))) + { + TMR6_1_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match B */ + if (1UL == bM4_TMR6_1->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMBF) && (0UL != (VSSEL132 & BIT_MASK_01))) + { + TMR6_1_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match C */ + if (1UL == bM4_TMR6_1->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMCF) && (0UL != (VSSEL132 & BIT_MASK_02))) + { + TMR6_1_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match D */ + if (1UL == bM4_TMR6_1->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMDF) && (0UL != (VSSEL132 & BIT_MASK_03))) + { + TMR6_1_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match E */ + if (1UL == bM4_TMR6_1->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMEF) && (0UL != (VSSEL132 & BIT_MASK_04))) + { + TMR6_1_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.1 general compare match F */ + if (1UL == bM4_TMR6_1->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMFF) && (0UL != (VSSEL132 & BIT_MASK_05))) + { + TMR6_1_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.1 overflow*/ + if (1UL == bM4_TMR6_1->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_1->STFLR_b.OVFF) && (0UL != (VSSEL132 & BIT_MASK_06))) + { + TMR6_1_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.1 underflow*/ + if (1UL == bM4_TMR6_1->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_1->STFLR_b.UDFF) && (0UL != (VSSEL132 & BIT_MASK_07))) + { + TMR6_1_GUdf_IrqHandler(); + } + } + /* Timer4 Ch.1 U phase higher compare match */ + if (1UL == bM4_TMR4_1->OCSRU_b.OCIEH) + { + if ((1UL == bM4_TMR4_1->OCSRU_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_08))) + { + TMR4_1_GCmpUH_IrqHandler(); + } + } + /* Timer4 Ch.1 U phase lower compare match */ + if (1UL == bM4_TMR4_1->OCSRU_b.OCIEL) + { + if ((1UL == bM4_TMR4_1->OCSRU_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_09))) + { + TMR4_1_GCmpUL_IrqHandler(); + } + } + /* Timer4 Ch.1 V phase higher compare match */ + if (1UL == bM4_TMR4_1->OCSRV_b.OCIEH) + { + if ((1UL == bM4_TMR4_1->OCSRV_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_10))) + { + TMR4_1_GCmpVH_IrqHandler(); + } + } + /* Timer4 Ch.1 V phase lower compare match */ + if (1UL == bM4_TMR4_1->OCSRV_b.OCIEL) + { + if ((1UL == bM4_TMR4_1->OCSRV_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_11))) + { + TMR4_1_GCmpVL_IrqHandler(); + } + } + /* Timer4 Ch.1 W phase higher compare match */ + if (1UL == bM4_TMR4_1->OCSRW_b.OCIEH) + { + if ((1UL == bM4_TMR4_1->OCSRW_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_12))) + { + TMR4_1_GCmpWH_IrqHandler(); + } + } + /* Timer4 Ch.1 W phase lower compare match */ + if (1UL == bM4_TMR4_1->OCSRW_b.OCIEL) + { + if ((1UL == bM4_TMR4_1->OCSRW_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_13))) + { + TMR4_1_GCmpWL_IrqHandler(); + } + } + /* Timer4 Ch.1 overflow */ + if (1UL == bM4_TMR4_1->CCSR_b.IRQPEN) + { + if ((1UL == bM4_TMR4_1->CCSR_b.IRQPF) && (0UL != (VSSEL132 & BIT_MASK_14))) + { + TMR4_1_Ovf_IrqHandler(); + } + } + /* Timer4 Ch.1 underflow */ + if (1UL == bM4_TMR4_1->CCSR_b.IRQZEN) + { + if ((1UL == bM4_TMR4_1->CCSR_b.IRQZF) && (0UL != (VSSEL132 & BIT_MASK_15))) + { + TMR4_1_Udf_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match A */ + if (1UL == bM4_TMR6_2->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMAF) && (0UL != (VSSEL132 & BIT_MASK_16))) + { + TMR6_2_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match B */ + if (1UL == bM4_TMR6_2->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMBF) && (0UL != (VSSEL132 & BIT_MASK_17))) + { + TMR6_2_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match C */ + if (1UL == bM4_TMR6_2->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMCF) && (0UL != (VSSEL132 & BIT_MASK_18))) + { + TMR6_2_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match D */ + if (1UL == bM4_TMR6_2->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMDF) && (0UL != (VSSEL132 & BIT_MASK_19))) + { + TMR6_2_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match E */ + if (1UL == bM4_TMR6_2->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMEF) && (0UL != (VSSEL132 & BIT_MASK_20))) + { + TMR6_2_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.2 general compare match F */ + if (1UL == bM4_TMR6_2->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMFF) && (0UL != (VSSEL132 & BIT_MASK_21))) + { + TMR6_2_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.2 overflow*/ + if (1UL == bM4_TMR6_2->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_2->STFLR_b.OVFF) && (0UL != (VSSEL132 & BIT_MASK_22))) + { + TMR6_2_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.2 underflow*/ + if (1UL == bM4_TMR6_2->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_2->STFLR_b.UDFF) && (0UL != (VSSEL132 & BIT_MASK_23))) + { + TMR6_2_GUdf_IrqHandler(); + } + } + /* Timer4 Ch.2 U phase higher compare match */ + if (1UL == bM4_TMR4_2->OCSRU_b.OCIEH) + { + if ((1UL == bM4_TMR4_2->OCSRU_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_24))) + { + TMR4_2_GCmpUH_IrqHandler(); + } + } + /* Timer4 Ch.2 U phase lower compare match */ + if (1UL == bM4_TMR4_2->OCSRU_b.OCIEL) + { + if ((1UL == bM4_TMR4_2->OCSRU_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_25))) + { + TMR4_2_GCmpUL_IrqHandler(); + } + } + /* Timer4 Ch.2 V phase higher compare match */ + if (1UL == bM4_TMR4_2->OCSRV_b.OCIEH) + { + if ((1UL == bM4_TMR4_2->OCSRV_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_26))) + { + TMR4_2_GCmpVH_IrqHandler(); + } + } + /* Timer4 Ch.2 V phase lower compare match */ + if (1UL == bM4_TMR4_2->OCSRV_b.OCIEL) + { + if ((1UL == bM4_TMR4_2->OCSRV_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_27))) + { + TMR4_2_GCmpVL_IrqHandler(); + } + } + /* Timer4 Ch.2 W phase higher compare match */ + if (1UL == bM4_TMR4_2->OCSRW_b.OCIEH) + { + if ((1UL == bM4_TMR4_2->OCSRW_b.OCFH) && (0UL != (VSSEL132 & BIT_MASK_28))) + { + TMR4_2_GCmpWH_IrqHandler(); + } + } + /* Timer4 Ch.2 W phase lower compare match */ + if (1UL == bM4_TMR4_2->OCSRW_b.OCIEL) + { + if ((1UL == bM4_TMR4_2->OCSRW_b.OCFL) && (0UL != (VSSEL132 & BIT_MASK_29))) + { + TMR4_2_GCmpWL_IrqHandler(); + } + } + /* Timer4 Ch.2 overflow */ + if (1UL == bM4_TMR4_2->CCSR_b.IRQPEN) + { + if ((1UL == bM4_TMR4_2->CCSR_b.IRQPF) && (0UL != (VSSEL132 & BIT_MASK_30))) + { + TMR4_2_Ovf_IrqHandler(); + } + } + /* Timer4 Ch.2 underflow */ + if (1UL == bM4_TMR4_2->CCSR_b.IRQZEN) + { + if ((1UL == bM4_TMR4_2->CCSR_b.IRQZF) && (0UL != (VSSEL132 & BIT_MASK_31))) + { + TMR4_2_Udf_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.133 share IRQ handler + * @param None + * @retval None + */ +void IRQ133_Handler(void) +{ + const uint32_t VSSEL133 = M4_INTC->VSSEL133; + + /* Timer6 Ch.3 general compare match A */ + if (1UL == bM4_TMR6_3->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMAF) && (0UL != (VSSEL133 & BIT_MASK_00))) + { + TMR6_3_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match B */ + if (1UL == bM4_TMR6_3->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMBF) && (0UL != (VSSEL133 & BIT_MASK_01))) + { + TMR6_3_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match C */ + if (1UL == bM4_TMR6_3->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMCF) && (0UL != (VSSEL133 & BIT_MASK_02))) + { + TMR6_3_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match D */ + if (1UL == bM4_TMR6_3->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMDF) && (0UL != (VSSEL133 & BIT_MASK_03))) + { + TMR6_3_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match E */ + if (1UL == bM4_TMR6_3->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMEF) && (0UL != (VSSEL133 & BIT_MASK_04))) + { + TMR6_3_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.3 general compare match F */ + if (1UL == bM4_TMR6_3->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMFF) && (0UL != (VSSEL133 & BIT_MASK_05))) + { + TMR6_3_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.3 overflow*/ + if (1UL == bM4_TMR6_3->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_3->STFLR_b.OVFF) && (0UL != (VSSEL133 & BIT_MASK_06))) + { + TMR6_3_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.3 underflow*/ + if (1UL == bM4_TMR6_3->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_3->STFLR_b.UDFF) && (0UL != (VSSEL133 & BIT_MASK_07))) + { + TMR6_3_GUdf_IrqHandler(); + } + } + /* Timer4 Ch.3 U phase higher compare match */ + if (1UL == bM4_TMR4_3->OCSRU_b.OCIEH) + { + if ((1UL == bM4_TMR4_3->OCSRU_b.OCFH) && (0UL != (VSSEL133 & BIT_MASK_08))) + { + TMR4_3_GCmpUH_IrqHandler(); + } + } + /* Timer4 Ch.3 U phase lower compare match */ + if (1UL == bM4_TMR4_3->OCSRU_b.OCIEL) + { + if ((1UL == bM4_TMR4_3->OCSRU_b.OCFL) && (0UL != (VSSEL133 & BIT_MASK_09))) + { + TMR4_3_GCmpUL_IrqHandler(); + } + } + /* Timer4 Ch.3 V phase higher compare match */ + if (1UL == bM4_TMR4_3->OCSRV_b.OCIEH) + { + if ((1UL == bM4_TMR4_3->OCSRV_b.OCFH) && (0UL != (VSSEL133 & BIT_MASK_10))) + { + TMR4_3_GCmpVH_IrqHandler(); + } + } + /* Timer4 Ch.3 V phase lower compare match */ + if (1UL == bM4_TMR4_3->OCSRV_b.OCIEL) + { + if ((1UL == bM4_TMR4_3->OCSRV_b.OCFL) && (0UL != (VSSEL133 & BIT_MASK_11))) + { + TMR4_3_GCmpVL_IrqHandler(); + } + } + /* Timer4 Ch.3 W phase higher compare match */ + if (1UL == bM4_TMR4_3->OCSRW_b.OCIEH) + { + if ((1UL == bM4_TMR4_3->OCSRW_b.OCFH) && (0UL != (VSSEL133 & BIT_MASK_12))) + { + TMR4_3_GCmpWH_IrqHandler(); + } + } + /* Timer4 Ch.3 W phase lower compare match */ + if (1UL == bM4_TMR4_3->OCSRW_b.OCIEL) + { + if ((1UL == bM4_TMR4_3->OCSRW_b.OCFL) && (0UL != (VSSEL133 & BIT_MASK_13))) + { + TMR4_3_GCmpWL_IrqHandler(); + } + } + /* Timer4 Ch.3 overflow */ + if (1UL == bM4_TMR4_3->CCSR_b.IRQPEN) + { + if ((1UL == bM4_TMR4_3->CCSR_b.IRQPF) && (0UL != (VSSEL133 & BIT_MASK_14))) + { + TMR4_3_Ovf_IrqHandler(); + } + } + /* Timer4 Ch.3 underflow */ + if (1UL == bM4_TMR4_3->CCSR_b.IRQZEN) + { + if ((1UL == bM4_TMR4_3->CCSR_b.IRQZF) && (0UL != (VSSEL133 & BIT_MASK_15))) + { + TMR4_3_Udf_IrqHandler(); + } + } + /* Timer6 Ch.1 dead time */ + if (1UL == bM4_TMR6_1->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_1->STFLR_b.DTEF) && (0UL != (VSSEL133 & BIT_MASK_16))) + { + TMR6_1_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.1 specified up compare match A*/ + if (1UL == bM4_TMR6_1->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMSAUF) && (0UL != (VSSEL133 & BIT_MASK_19))) + { + TMR6_1_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.1 specified down compare match A*/ + if (1UL == bM4_TMR6_1->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMSADF) && (0UL != (VSSEL133 & BIT_MASK_19))) + { + TMR6_1_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.1 specified up compare match B*/ + if (1UL == bM4_TMR6_1->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMSBUF) && (0UL != (VSSEL133 & BIT_MASK_20))) + { + TMR6_1_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.1 specified down compare match B*/ + if (1UL == bM4_TMR6_1->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_1->STFLR_b.CMSBDF) && (0UL != (VSSEL133 & BIT_MASK_20))) + { + TMR6_1_SCmpDownB_IrqHandler(); + } + } + /* Timer4 Ch.1 U phase reload */ + if (0UL == bM4_TMR4_1->RCSR_b.RTIDU) + { + if ((1UL == bM4_TMR4_1->RCSR_b.RTIFU) && (0UL != (VSSEL133 & BIT_MASK_21))) + { + TMR4_1_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.1 V phase reload */ + if (0UL == bM4_TMR4_1->RCSR_b.RTIDV) + { + if ((1UL == bM4_TMR4_1->RCSR_b.RTIFV) && (0UL != (VSSEL133 & BIT_MASK_22))) + { + TMR4_1_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.1 W phase reload */ + if (0UL == bM4_TMR4_1->RCSR_b.RTIDW) + { + if ((1UL == bM4_TMR4_1->RCSR_b.RTIFW) && (0UL != (VSSEL133 & BIT_MASK_23))) + { + TMR4_1_ReloadU_IrqHandler(); + } + } + /* Timer6 Ch.2 dead time */ + if (1UL == bM4_TMR6_2->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_2->STFLR_b.DTEF) && (0UL != (VSSEL133 & BIT_MASK_24))) + { + TMR6_2_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.2 specified up compare match A*/ + if (1UL == bM4_TMR6_2->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMSAUF) && (0UL != (VSSEL133 & BIT_MASK_27))) + { + TMR6_2_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.2 specified down compare match A*/ + if (1UL == bM4_TMR6_2->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMSADF) && (0UL != (VSSEL133 & BIT_MASK_27))) + { + TMR6_2_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.2 specified up compare match B*/ + if (1UL == bM4_TMR6_2->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMSBUF) && (0UL != (VSSEL133 & BIT_MASK_28))) + { + TMR6_2_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.2 specified down compare match B*/ + if (1UL == bM4_TMR6_2->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_2->STFLR_b.CMSBDF) && (0UL != (VSSEL133 & BIT_MASK_28))) + { + TMR6_2_SCmpDownB_IrqHandler(); + } + } + /* Timer4 Ch.2 U phase reload */ + if (0UL == bM4_TMR4_2->RCSR_b.RTIDU) + { + if ((1UL == bM4_TMR4_2->RCSR_b.RTIFU) && (0UL != (VSSEL133 & BIT_MASK_29))) + { + TMR4_2_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.2 V phase reload */ + if (0UL == bM4_TMR4_2->RCSR_b.RTIDV) + { + if ((1UL == bM4_TMR4_2->RCSR_b.RTIFV) && (0UL != (VSSEL133 & BIT_MASK_30))) + { + TMR4_2_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.2 W phase reload */ + if (0UL == bM4_TMR4_2->RCSR_b.RTIDW) + { + if ((1UL == bM4_TMR4_2->RCSR_b.RTIFW) && (0UL != (VSSEL133 & BIT_MASK_31))) + { + TMR4_2_ReloadU_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.134 share IRQ handler + * @param None + * @retval None + */ +void IRQ134_Handler(void) +{ + const uint32_t VSSEL134 = M4_INTC->VSSEL134; + + /* Timer6 Ch.3 dead time */ + if (1UL == bM4_TMR6_3->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_3->STFLR_b.DTEF) && (0UL != (VSSEL134 & BIT_MASK_00))) + { + TMR6_3_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.3 specified up compare match A*/ + if (1UL == bM4_TMR6_3->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMSAUF) && (0UL != (VSSEL134 & BIT_MASK_03))) + { + TMR6_3_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.3 specified down compare match A*/ + if (1UL == bM4_TMR6_3->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMSADF) && (0UL != (VSSEL134 & BIT_MASK_03))) + { + TMR6_3_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.3 specified up compare match B*/ + if (1UL == bM4_TMR6_3->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMSBUF) && (0UL != (VSSEL134 & BIT_MASK_04))) + { + TMR6_3_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.3 specified down compare match B*/ + if (1UL == bM4_TMR6_3->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_3->STFLR_b.CMSBDF) && (0UL != (VSSEL134 & BIT_MASK_04))) + { + TMR6_3_SCmpDownB_IrqHandler(); + } + } + /* Timer4 Ch.3 U phase reload */ + if (0UL == bM4_TMR4_3->RCSR_b.RTIDU) + { + if ((1UL == bM4_TMR4_3->RCSR_b.RTIFU) && (0UL != (VSSEL134 & BIT_MASK_05))) + { + TMR4_3_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.3 V phase reload */ + if (0UL == bM4_TMR4_3->RCSR_b.RTIDV) + { + if ((1UL == bM4_TMR4_3->RCSR_b.RTIFV) && (0UL != (VSSEL134 & BIT_MASK_06))) + { + TMR4_3_ReloadU_IrqHandler(); + } + } + /* Timer4 Ch.3 W phase reload */ + if (0UL == bM4_TMR4_3->RCSR_b.RTIDW) + { + if ((1UL == bM4_TMR4_3->RCSR_b.RTIFW) && (0UL != (VSSEL134 & BIT_MASK_07))) + { + TMR4_3_ReloadU_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match A */ + if (1UL == bM4_TMR6_4->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMAF) && (0UL != (VSSEL134 & BIT_MASK_16))) + { + TMR6_4_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match B */ + if (1UL == bM4_TMR6_4->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMBF) && (0UL != (VSSEL134 & BIT_MASK_17))) + { + TMR6_4_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match C */ + if (1UL == bM4_TMR6_4->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMCF) && (0UL != (VSSEL134 & BIT_MASK_18))) + { + TMR6_4_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match D */ + if (1UL == bM4_TMR6_4->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMDF) && (0UL != (VSSEL134 & BIT_MASK_19))) + { + TMR6_4_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match E */ + if (1UL == bM4_TMR6_4->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMEF) && (0UL != (VSSEL134 & BIT_MASK_20))) + { + TMR6_4_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.4 general compare match F */ + if (1UL == bM4_TMR6_4->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMFF) && (0UL != (VSSEL134 & BIT_MASK_21))) + { + TMR6_4_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.4 overflow*/ + if (1UL == bM4_TMR6_4->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_4->STFLR_b.OVFF) && (0UL != (VSSEL134 & BIT_MASK_22))) + { + TMR6_4_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.4 underflow*/ + if (1UL == bM4_TMR6_4->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_4->STFLR_b.UDFF) && (0UL != (VSSEL134 & BIT_MASK_23))) + { + TMR6_4_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.4 dead time */ + if (1UL == bM4_TMR6_4->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_4->STFLR_b.DTEF) && (0UL != (VSSEL134 & BIT_MASK_24))) + { + TMR6_4_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.4 specified up compare match A*/ + if (1UL == bM4_TMR6_4->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMSAUF) && (0UL != (VSSEL134 & BIT_MASK_27))) + { + TMR6_4_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.4 specified down compare match A*/ + if (1UL == bM4_TMR6_4->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMSADF) && (0UL != (VSSEL134 & BIT_MASK_27))) + { + TMR6_4_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.4 specified up compare match B*/ + if (1UL == bM4_TMR6_4->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMSBUF) && (0UL != (VSSEL134 & BIT_MASK_28))) + { + TMR6_4_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.4 specified down compare match B*/ + if (1UL == bM4_TMR6_4->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_4->STFLR_b.CMSBDF) && (0UL != (VSSEL134 & BIT_MASK_28))) + { + TMR6_4_SCmpDownB_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.135 share IRQ handler + * @param None + * @retval None + */ +void IRQ135_Handler(void) +{ + const uint32_t VSSEL135 = M4_INTC->VSSEL135; + + /* Timer6 Ch.5 general compare match A */ + if (1UL == bM4_TMR6_5->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMAF) && (0UL != (VSSEL135 & BIT_MASK_00))) + { + TMR6_5_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match B */ + if (1UL == bM4_TMR6_5->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMBF) && (0UL != (VSSEL135 & BIT_MASK_01))) + { + TMR6_5_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match C */ + if (1UL == bM4_TMR6_5->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMCF) && (0UL != (VSSEL135 & BIT_MASK_02))) + { + TMR6_5_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match D */ + if (1UL == bM4_TMR6_5->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMDF) && (0UL != (VSSEL135 & BIT_MASK_03))) + { + TMR6_5_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match E */ + if (1UL == bM4_TMR6_5->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMEF) && (0UL != (VSSEL135 & BIT_MASK_04))) + { + TMR6_5_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.5 general compare match F */ + if (1UL == bM4_TMR6_5->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMFF) && (0UL != (VSSEL135 & BIT_MASK_05))) + { + TMR6_5_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.5 overflow*/ + if (1UL == bM4_TMR6_5->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_5->STFLR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_06))) + { + TMR6_5_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.5 underflow*/ + if (1UL == bM4_TMR6_5->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_5->STFLR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_07))) + { + TMR6_5_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.5 dead time */ + if (1UL == bM4_TMR6_5->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_5->STFLR_b.DTEF) && (0UL != (VSSEL135 & BIT_MASK_08))) + { + TMR6_5_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.5 specified up compare match A*/ + if (1UL == bM4_TMR6_5->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMSAUF) && (0UL != (VSSEL135 & BIT_MASK_11))) + { + TMR6_5_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.5 specified down compare match A*/ + if (1UL == bM4_TMR6_5->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMSADF) && (0UL != (VSSEL135 & BIT_MASK_11))) + { + TMR6_5_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.5 specified up compare match B*/ + if (1UL == bM4_TMR6_5->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMSBUF) && (0UL != (VSSEL135 & BIT_MASK_12))) + { + TMR6_5_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.5 specified down compare match B*/ + if (1UL == bM4_TMR6_5->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_5->STFLR_b.CMSBDF) && (0UL != (VSSEL135 & BIT_MASK_12))) + { + TMR6_5_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.1 overflow */ + if (1UL == bM4_TMRA_1->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_1->BCSTR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_13))) + { + TMRA_1_Ovf_IrqHandler(); + } + } + /* TimerA Ch.1 underflow */ + if (1UL == bM4_TMRA_1->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_1->BCSTR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_14))) + { + TMRA_1_Udf_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 1 */ + if (1UL == bM4_TMRA_1->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_1->STFLR_b.CMPF1) && (0UL != (VSSEL135 & BIT_MASK_15))) + { + TMRA_1_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 2 */ + if (1UL == bM4_TMRA_1->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_1->STFLR_b.CMPF2) && (0UL != (VSSEL135 & BIT_MASK_15))) + { + TMRA_1_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 3 */ + if (1UL == bM4_TMRA_1->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_1->STFLR_b.CMPF3) && (0UL != (VSSEL135 & BIT_MASK_15))) + { + TMRA_1_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.1 compare match 4 */ + if (1UL == bM4_TMRA_1->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_1->STFLR_b.CMPF4) && (0UL != (VSSEL135 & BIT_MASK_15))) + { + TMRA_1_Cmp4_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match A */ + if (1UL == bM4_TMR6_6->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMAF) && (0UL != (VSSEL135 & BIT_MASK_16))) + { + TMR6_6_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match B */ + if (1UL == bM4_TMR6_6->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMBF) && (0UL != (VSSEL135 & BIT_MASK_17))) + { + TMR6_6_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match C */ + if (1UL == bM4_TMR6_6->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMCF) && (0UL != (VSSEL135 & BIT_MASK_18))) + { + TMR6_6_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match D */ + if (1UL == bM4_TMR6_6->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMDF) && (0UL != (VSSEL135 & BIT_MASK_19))) + { + TMR6_6_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match E */ + if (1UL == bM4_TMR6_6->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMEF) && (0UL != (VSSEL135 & BIT_MASK_20))) + { + TMR6_6_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.6 general compare match F */ + if (1UL == bM4_TMR6_6->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMFF) && (0UL != (VSSEL135 & BIT_MASK_21))) + { + TMR6_6_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.6 overflow*/ + if (1UL == bM4_TMR6_6->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_6->STFLR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_22))) + { + TMR6_6_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.6 underflow*/ + if (1UL == bM4_TMR6_6->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_6->STFLR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_23))) + { + TMR6_6_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.6 dead time */ + if (1UL == bM4_TMR6_6->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_6->STFLR_b.DTEF) && (0UL != (VSSEL135 & BIT_MASK_24))) + { + TMR6_6_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.6 specified up compare match A*/ + if (1UL == bM4_TMR6_6->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMSAUF) && (0UL != (VSSEL135 & BIT_MASK_27))) + { + TMR6_6_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.6 specified down compare match A*/ + if (1UL == bM4_TMR6_6->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMSADF) && (0UL != (VSSEL135 & BIT_MASK_27))) + { + TMR6_6_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.6 specified up compare match B*/ + if (1UL == bM4_TMR6_6->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMSBUF) && (0UL != (VSSEL135 & BIT_MASK_28))) + { + TMR6_6_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.6 specified down compare match B*/ + if (1UL == bM4_TMR6_6->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_6->STFLR_b.CMSBDF) && (0UL != (VSSEL135 & BIT_MASK_28))) + { + TMR6_6_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.2 overflow */ + if (1UL == bM4_TMRA_2->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_2->BCSTR_b.OVFF) && (0UL != (VSSEL135 & BIT_MASK_29))) + { + TMRA_2_Ovf_IrqHandler(); + } + } + /* TimerA Ch.2 underflow */ + if (1UL == bM4_TMRA_2->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_2->BCSTR_b.UDFF) && (0UL != (VSSEL135 & BIT_MASK_30))) + { + TMRA_2_Udf_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 1 */ + if (1UL == bM4_TMRA_2->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_2->STFLR_b.CMPF1) && (0UL != (VSSEL135 & BIT_MASK_31))) + { + TMRA_2_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 2 */ + if (1UL == bM4_TMRA_2->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_2->STFLR_b.CMPF2) && (0UL != (VSSEL135 & BIT_MASK_31))) + { + TMRA_2_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 3 */ + if (1UL == bM4_TMRA_2->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_2->STFLR_b.CMPF3) && (0UL != (VSSEL135 & BIT_MASK_31))) + { + TMRA_2_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.2 compare match 4 */ + if (1UL == bM4_TMRA_2->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_2->STFLR_b.CMPF4) && (0UL != (VSSEL135 & BIT_MASK_31))) + { + TMRA_2_Cmp4_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.136 share IRQ handler + * @param None + * @retval None + */ +void IRQ136_Handler(void) +{ + const uint32_t VSSEL136 = M4_INTC->VSSEL136; + + /* Timer6 Ch.7 general compare match A */ + if (1UL == bM4_TMR6_7->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMAF) && (0UL != (VSSEL136 & BIT_MASK_00))) + { + TMR6_7_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match B */ + if (1UL == bM4_TMR6_7->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMBF) && (0UL != (VSSEL136 & BIT_MASK_01))) + { + TMR6_7_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match C */ + if (1UL == bM4_TMR6_7->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMCF) && (0UL != (VSSEL136 & BIT_MASK_02))) + { + TMR6_7_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match D */ + if (1UL == bM4_TMR6_7->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMDF) && (0UL != (VSSEL136 & BIT_MASK_03))) + { + TMR6_7_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match E */ + if (1UL == bM4_TMR6_7->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMEF) && (0UL != (VSSEL136 & BIT_MASK_04))) + { + TMR6_7_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.7 general compare match F */ + if (1UL == bM4_TMR6_7->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMFF) && (0UL != (VSSEL136 & BIT_MASK_05))) + { + TMR6_7_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.7 overflow*/ + if (1UL == bM4_TMR6_7->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_7->STFLR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_06))) + { + TMR6_7_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.7 underflow*/ + if (1UL == bM4_TMR6_7->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_7->STFLR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_07))) + { + TMR6_7_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.7 dead time */ + if (1UL == bM4_TMR6_7->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_7->STFLR_b.DTEF) && (0UL != (VSSEL136 & BIT_MASK_08))) + { + TMR6_7_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.7 specified up compare match A*/ + if (1UL == bM4_TMR6_7->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMSAUF) && (0UL != (VSSEL136 & BIT_MASK_11))) + { + TMR6_7_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.7 specified down compare match A*/ + if (1UL == bM4_TMR6_7->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMSADF) && (0UL != (VSSEL136 & BIT_MASK_11))) + { + TMR6_7_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.7 specified up compare match B*/ + if (1UL == bM4_TMR6_7->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMSBUF) && (0UL != (VSSEL136 & BIT_MASK_12))) + { + TMR6_7_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.7 specified down compare match B*/ + if (1UL == bM4_TMR6_7->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_7->STFLR_b.CMSBDF) && (0UL != (VSSEL136 & BIT_MASK_12))) + { + TMR6_7_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.3 overflow */ + if (1UL == bM4_TMRA_3->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_3->BCSTR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_13))) + { + TMRA_3_Ovf_IrqHandler(); + } + } + /* TimerA Ch.3 underflow */ + if (1UL == bM4_TMRA_3->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_3->BCSTR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_14))) + { + TMRA_3_Udf_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 1 */ + if (1UL == bM4_TMRA_3->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_3->STFLR_b.CMPF1) && (0UL != (VSSEL136 & BIT_MASK_15))) + { + TMRA_3_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 2 */ + if (1UL == bM4_TMRA_3->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_3->STFLR_b.CMPF2) && (0UL != (VSSEL136 & BIT_MASK_15))) + { + TMRA_3_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 3 */ + if (1UL == bM4_TMRA_3->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_3->STFLR_b.CMPF3) && (0UL != (VSSEL136 & BIT_MASK_15))) + { + TMRA_3_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.3 compare match 4 */ + if (1UL == bM4_TMRA_3->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_3->STFLR_b.CMPF4) && (0UL != (VSSEL136 & BIT_MASK_15))) + { + TMRA_3_Cmp4_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match A */ + if (1UL == bM4_TMR6_8->ICONR_b.INTENA) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMAF) && (0UL != (VSSEL136 & BIT_MASK_16))) + { + TMR6_8_GCmpA_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match B */ + if (1UL == bM4_TMR6_8->ICONR_b.INTENB) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMBF) && (0UL != (VSSEL136 & BIT_MASK_17))) + { + TMR6_8_GCmpB_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match C */ + if (1UL == bM4_TMR6_8->ICONR_b.INTENC) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMCF) && (0UL != (VSSEL136 & BIT_MASK_18))) + { + TMR6_8_GCmpC_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match D */ + if (1UL == bM4_TMR6_8->ICONR_b.INTEND) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMDF) && (0UL != (VSSEL136 & BIT_MASK_19))) + { + TMR6_8_GCmpD_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match E */ + if (1UL == bM4_TMR6_8->ICONR_b.INTENE) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMEF) && (0UL != (VSSEL136 & BIT_MASK_20))) + { + TMR6_8_GCmpE_IrqHandler(); + } + } + /* Timer6 Ch.8 general compare match F */ + if (1UL == bM4_TMR6_8->ICONR_b.INTENF) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMFF) && (0UL != (VSSEL136 & BIT_MASK_21))) + { + TMR6_8_GCmpF_IrqHandler(); + } + } + /* Timer6 Ch.8 overflow*/ + if (1UL == bM4_TMR6_8->ICONR_b.INTENOVF) + { + if ((1UL == bM4_TMR6_8->STFLR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_22))) + { + TMR6_8_GOvf_IrqHandler(); + } + } + /* Timer6 Ch.8 underflow*/ + if (1UL == bM4_TMR6_8->ICONR_b.INTENUDF) + { + if ((1UL == bM4_TMR6_8->STFLR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_23))) + { + TMR6_8_GUdf_IrqHandler(); + } + } + /* Timer6 Ch.8 dead time */ + if (1UL == bM4_TMR6_8->ICONR_b.INTENDTE) + { + if ((1UL == bM4_TMR6_8->STFLR_b.DTEF) && (0UL != (VSSEL136 & BIT_MASK_24))) + { + TMR6_8_Gdte_IrqHandler(); + } + } + /* Timer6 Ch.8 specified up compare match A*/ + if (1UL == bM4_TMR6_8->ICONR_b.INTENSAU) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMSAUF) && (0UL != (VSSEL136 & BIT_MASK_27))) + { + TMR6_8_SCmpUpA_IrqHandler(); + } + } + /* Timer6 Ch.8 specified down compare match A*/ + if (1UL == bM4_TMR6_8->ICONR_b.INTENSAD) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMSADF) && (0UL != (VSSEL136 & BIT_MASK_27))) + { + TMR6_8_SCmpDownA_IrqHandler(); + } + } + /* Timer6 Ch.8 specified up compare match B*/ + if (1UL == bM4_TMR6_8->ICONR_b.INTENSBU) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMSBUF) && (0UL != (VSSEL136 & BIT_MASK_28))) + { + TMR6_8_SCmpUpB_IrqHandler(); + } + } + /* Timer6 Ch.8 specified down compare match B*/ + if (1UL == bM4_TMR6_8->ICONR_b.INTENSBD) + { + if ((1UL == bM4_TMR6_8->STFLR_b.CMSBDF) && (0UL != (VSSEL136 & BIT_MASK_28))) + { + TMR6_8_SCmpDownB_IrqHandler(); + } + } + /* TimerA Ch.4 overflow */ + if (1UL == bM4_TMRA_4->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_4->BCSTR_b.OVFF) && (0UL != (VSSEL136 & BIT_MASK_29))) + { + TMRA_4_Ovf_IrqHandler(); + } + } + /* TimerA Ch.4 underflow */ + if (1UL == bM4_TMRA_4->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_4->BCSTR_b.UDFF) && (0UL != (VSSEL136 & BIT_MASK_30))) + { + TMRA_4_Udf_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 1 */ + if (1UL == bM4_TMRA_4->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_4->STFLR_b.CMPF1) && (0UL != (VSSEL136 & BIT_MASK_31))) + { + TMRA_4_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 2 */ + if (1UL == bM4_TMRA_4->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_4->STFLR_b.CMPF2) && (0UL != (VSSEL136 & BIT_MASK_31))) + { + TMRA_4_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 3 */ + if (1UL == bM4_TMRA_4->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_4->STFLR_b.CMPF3) && (0UL != (VSSEL136 & BIT_MASK_31))) + { + TMRA_4_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.4 compare match 4 */ + if (1UL == bM4_TMRA_4->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_4->STFLR_b.CMPF4) && (0UL != (VSSEL136 & BIT_MASK_31))) + { + TMRA_4_Cmp4_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.137 share IRQ handler + * @param None + * @retval None + */ +void IRQ137_Handler(void) +{ + const uint32_t VSSEL137 = M4_INTC->VSSEL137; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* EMB0 */ + u32Tmp1 = M4_EMB0->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB0->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_00))) + { + EMB_GR0_IrqHandler(); + } + /* EMB1 */ + u32Tmp1 = M4_EMB1->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB1->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_01))) + { + EMB_GR1_IrqHandler(); + } + /* EMB2 */ + u32Tmp1 = M4_EMB2->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB2->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_02))) + { + EMB_GR2_IrqHandler(); + } + /* EMB3 */ + u32Tmp1 = M4_EMB3->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB3->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_03))) + { + EMB_GR3_IrqHandler(); + } + /* EMB4 */ + u32Tmp1 = M4_EMB4->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB4->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_04))) + { + EMB_GR4_IrqHandler(); + } + /* EMB5 */ + u32Tmp1 = M4_EMB5->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB5->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_05))) + { + EMB_GR5_IrqHandler(); + } + /* EMB6 */ + u32Tmp1 = M4_EMB6->INTEN & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + u32Tmp2 = M4_EMB6->STAT & (BIT_MASK_01 | BIT_MASK_02 | BIT_MASK_03 | \ + BIT_MASK_08 | BIT_MASK_09 | BIT_MASK_10 | BIT_MASK_11); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL137 & BIT_MASK_06))) + { + EMB_GR6_IrqHandler(); + } + /* USB HS EP1 out */ + + /* USB HS EP1 in */ + + /* USB HS global */ + + /* USB HS wakeup */ + + if (1UL == bM4_USART1->CR1_b.RIE) + { + /* USART Ch.1 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART1->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_12))) + { + USART_1_RxErr_IrqHandler(); + } + /* USART Ch.1 Rx end */ + if ((1UL == bM4_USART1->SR_b.RXNE) && (0UL != (VSSEL137 & BIT_MASK_13))) + { + USART_1_RxEnd_IrqHandler(); + } + } + /* USART Ch.1 Tx buffer empty */ + if (1UL == bM4_USART1->CR1_b.TXEIE) + { + if ((1UL == bM4_USART1->SR_b.TXE) && (0UL != (VSSEL137 & BIT_MASK_14))) + { + USART_1_TxEmpty_IrqHandler(); + } + } + /* USART Ch.1 Tx end */ + if (1UL == bM4_USART1->CR1_b.TCIE) + { + if ((1UL == bM4_USART1->SR_b.TC) && (0UL != (VSSEL137 & BIT_MASK_15))) + { + USART_1_TxEnd_IrqHandler(); + } + } + /* USART Ch.1 Tx timeout */ + if (1UL == bM4_USART1->CR1_b.RTOIE) + { + if ((1UL == bM4_USART1->SR_b.RTOF) && (0UL != (VSSEL137 & BIT_MASK_16))) + { + USART_1_RxTO_IrqHandler(); + } + } + if (1UL == bM4_USART2->CR1_b.RIE) + { + /* USART Ch.2 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART2->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_17))) + { + USART_2_RxErr_IrqHandler(); + } + /* USART Ch.2 Rx end */ + if ((1UL == bM4_USART2->SR_b.RXNE) && (0UL != (VSSEL137 & BIT_MASK_18))) + { + USART_2_RxEnd_IrqHandler(); + } + } + /* USART Ch.2 Tx buffer empty */ + if (1UL == bM4_USART2->CR1_b.TXEIE) + { + if ((1UL == bM4_USART2->SR_b.TXE) && (0UL != (VSSEL137 & BIT_MASK_19))) + { + USART_2_TxEmpty_IrqHandler(); + } + } + /* USART Ch.2 Tx end */ + if (1UL == bM4_USART2->CR1_b.TCIE) + { + if ((1UL == bM4_USART2->SR_b.TC) && (0UL != (VSSEL137 & BIT_MASK_20))) + { + USART_2_TxEnd_IrqHandler(); + } + } + /* USART Ch.2 Tx timeout */ + if (1UL == bM4_USART2->CR1_b.RTOIE) + { + if ((1UL == bM4_USART2->SR_b.RTOF) && (0UL != (VSSEL137 & BIT_MASK_21))) + { + USART_2_RxTO_IrqHandler(); + } + } + /* SPI Ch.1 Rx end */ + if (1UL == bM4_SPI1->CR1_b.RXIE) + { + if ((1UL == bM4_SPI1->SR_b.RDFF) && (0UL != (VSSEL137 & BIT_MASK_22))) + { + SPI_1_RxEnd_IrqHandler(); + } + } + /* SPI Ch.1 Tx buffer empty */ + if (1UL == bM4_SPI1->CR1_b.TXIE) + { + if ((1UL == bM4_SPI1->SR_b.TDEF) && (0UL != (VSSEL137 & BIT_MASK_23))) + { + SPI_1_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.1 Bus idle */ + if (1UL == bM4_SPI1->CR1_b.IDIE) + { + if ((0UL == bM4_SPI1->SR_b.IDLNF) && (0UL != (VSSEL137 & BIT_MASK_24))) + { + SPI_1_Idle_IrqHandler(); + } + } + /* SPI Ch.1 parity/overflow/underflow/mode error */ + if (1UL == bM4_SPI1->CR1_b.EIE) + { + u32Tmp1 = M4_SPI1->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_25))) + { + SPI_1_Err_IrqHandler(); + } + } + /* SPI Ch.2 Rx end */ + if (1UL == bM4_SPI2->CR1_b.RXIE) + { + if ((1UL == bM4_SPI2->SR_b.RDFF) && (0UL != (VSSEL137 & BIT_MASK_27))) + { + SPI_2_RxEnd_IrqHandler(); + } + } + /* SPI Ch.2 Tx buffer empty */ + if (1UL == bM4_SPI2->CR1_b.TXIE) + { + if ((1UL == bM4_SPI2->SR_b.TDEF) && (0UL != (VSSEL137 & BIT_MASK_28))) + { + SPI_2_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.2 Bus idle */ + if (1UL == bM4_SPI2->CR1_b.IDIE) + { + if ((0UL == bM4_SPI2->SR_b.IDLNF) && (0UL != (VSSEL137 & BIT_MASK_29))) + { + SPI_2_Idle_IrqHandler(); + } + } + /* SPI Ch.2 parity/overflow/underflow/mode error */ + if (1UL == bM4_SPI2->CR1_b.EIE) + { + u32Tmp1 = M4_SPI2->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL137 & BIT_MASK_30))) + { + SPI_2_Err_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.138 share IRQ handler + * @param None + * @retval None + */ +void IRQ138_Handler(void) +{ + const uint32_t VSSEL138 = M4_INTC->VSSEL138; + uint32_t u32Tmp1; + uint8_t RTIF; + uint8_t RTIE; + uint8_t ERRINT; + uint8_t TTCFG; + + /* TimerA Ch.5 overflow */ + if (1UL == bM4_TMRA_5->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_5->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_00))) + { + TMRA_5_Ovf_IrqHandler(); + } + } + /* TimerA Ch.5 underflow */ + if (1UL == bM4_TMRA_5->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_5->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_01))) + { + TMRA_5_Udf_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 1 */ + if (1UL == bM4_TMRA_5->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_5->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_02))) + { + TMRA_5_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 2 */ + if (1UL == bM4_TMRA_5->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_5->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_02))) + { + TMRA_5_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 3 */ + if (1UL == bM4_TMRA_5->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_5->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_02))) + { + TMRA_5_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.5 compare match 4 */ + if (1UL == bM4_TMRA_5->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_5->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_02))) + { + TMRA_5_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.6 overflow */ + if (1UL == bM4_TMRA_6->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_6->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_03))) + { + TMRA_6_Ovf_IrqHandler(); + } + } + /* TimerA Ch.6 underflow */ + if (1UL == bM4_TMRA_6->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_6->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_04))) + { + TMRA_6_Udf_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 1 */ + if (1UL == bM4_TMRA_6->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_6->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_05))) + { + TMRA_6_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 2 */ + if (1UL == bM4_TMRA_6->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_6->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_05))) + { + TMRA_6_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 3 */ + if (1UL == bM4_TMRA_6->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_6->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_05))) + { + TMRA_6_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.6 compare match 4 */ + if (1UL == bM4_TMRA_6->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_6->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_05))) + { + TMRA_6_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.7 overflow */ + if (1UL == bM4_TMRA_7->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_7->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_06))) + { + TMRA_7_Ovf_IrqHandler(); + } + } + /* TimerA Ch.7 underflow */ + if (1UL == bM4_TMRA_7->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_7->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_07))) + { + TMRA_7_Udf_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 1 */ + if (1UL == bM4_TMRA_7->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_7->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_08))) + { + TMRA_7_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 2 */ + if (1UL == bM4_TMRA_7->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_7->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_08))) + { + TMRA_7_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 3 */ + if (1UL == bM4_TMRA_7->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_7->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_08))) + { + TMRA_7_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.7 compare match 4 */ + if (1UL == bM4_TMRA_7->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_7->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_08))) + { + TMRA_7_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.8 overflow */ + if (1UL == bM4_TMRA_8->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_8->BCSTR_b.OVFF) && (0UL != (VSSEL138 & BIT_MASK_09))) + { + TMRA_8_Ovf_IrqHandler(); + } + } + /* TimerA Ch.8 underflow */ + if (1UL == bM4_TMRA_8->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_8->BCSTR_b.UDFF) && (0UL != (VSSEL138 & BIT_MASK_10))) + { + TMRA_8_Udf_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 1 */ + if (1UL == bM4_TMRA_8->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_8->STFLR_b.CMPF1) && (0UL != (VSSEL138 & BIT_MASK_11))) + { + TMRA_8_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 2 */ + if (1UL == bM4_TMRA_8->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_8->STFLR_b.CMPF2) && (0UL != (VSSEL138 & BIT_MASK_11))) + { + TMRA_8_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 3 */ + if (1UL == bM4_TMRA_8->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_8->STFLR_b.CMPF3) && (0UL != (VSSEL138 & BIT_MASK_11))) + { + TMRA_8_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.8 compare match 4 */ + if (1UL == bM4_TMRA_8->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_8->STFLR_b.CMPF4) && (0UL != (VSSEL138 & BIT_MASK_11))) + { + TMRA_8_Cmp4_IrqHandler(); + } + } + if (1UL == bM4_USART3->CR1_b.RIE) + { + /* USART Ch.3 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART3->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_12))) + { + USART_3_RxErr_IrqHandler(); + } + /* USART Ch.3 Rx end */ + if ((1UL == bM4_USART3->SR_b.RXNE) && (0UL != (VSSEL138 & BIT_MASK_13))) + { + USART_3_RxEnd_IrqHandler(); + } + } + /* USART Ch.3 Tx buffer empty */ + if (1UL == bM4_USART3->CR1_b.TXEIE) + { + if ((1UL == bM4_USART3->SR_b.TXE) && (0UL != (VSSEL138 & BIT_MASK_14))) + { + USART_3_TxEmpty_IrqHandler(); + } + } + /* USART Ch.3 Tx end */ + if (1UL == bM4_USART3->CR1_b.TCIE) + { + if ((1UL == bM4_USART3->SR_b.TC) && (0UL != (VSSEL138 & BIT_MASK_15))) + { + USART_3_TxEnd_IrqHandler(); + } + } + if (1UL == bM4_USART4->CR1_b.RIE) + { + /* USART Ch.4 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART4->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_16))) + { + USART_4_RxErr_IrqHandler(); + } + /* USART Ch.4 Rx end */ + if ((1UL == bM4_USART4->SR_b.RXNE) && (0UL != (VSSEL138 & BIT_MASK_17))) + { + USART_4_RxEnd_IrqHandler(); + } + } + /* USART Ch.4 Tx buffer empty */ + if (1UL == bM4_USART4->CR1_b.TXEIE) + { + if ((1UL == bM4_USART4->SR_b.TXE) && (0UL != (VSSEL138 & BIT_MASK_18))) + { + USART_4_TxEmpty_IrqHandler(); + } + } + /* USART Ch.4 Tx end */ + if (1UL == bM4_USART4->CR1_b.TCIE) + { + if ((1UL == bM4_USART4->SR_b.TC) && (0UL != (VSSEL138 & BIT_MASK_19))) + { + USART_4_TxEnd_IrqHandler(); + } + } + /* CAN Ch.1 */ + if (0UL != (0UL != (VSSEL138 & BIT_MASK_20))) + { + RTIF = M4_CAN1->RTIF; + RTIE = M4_CAN1->RTIE; + ERRINT = M4_CAN1->ERRINT; + TTCFG = M4_CAN1->TTCFG; + if ((0U != (TTCFG & CAN_TTCFG_TEIF)) || \ + (0U != (RTIF & CAN_RTIF_AIF)) || \ + (0U != (RTIF & RTIE & 0xFEU)) || \ + ((0U != (ERRINT & CAN_ERRINT_BEIE)) && \ + (0U != (ERRINT & CAN_ERRINT_BEIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_ALIE)) && \ + (0U != (ERRINT & CAN_ERRINT_ALIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_EPIE)) && \ + (0U != (ERRINT & CAN_ERRINT_EPIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_TTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_TTIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_WTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_WTIF)))) + { + CAN_1_IrqHandler(); + } + } + /* CAN Ch.2 */ + if (0UL != (0UL != (VSSEL138 & BIT_MASK_21))) + { + RTIF = M4_CAN2->RTIF; + RTIE = M4_CAN2->RTIE; + ERRINT = M4_CAN2->ERRINT; + TTCFG = M4_CAN2->TTCFG; + if ((0U != (TTCFG & CAN_TTCFG_TEIF)) || \ + (0U != (RTIF & CAN_RTIF_AIF)) || \ + (0U != (RTIF & RTIE & 0xFEU)) || \ + ((0U != (ERRINT & CAN_ERRINT_BEIE)) && \ + (0U != (ERRINT & CAN_ERRINT_BEIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_ALIE)) && \ + (0U != (ERRINT & CAN_ERRINT_ALIF))) || \ + ((0U != (ERRINT & CAN_ERRINT_EPIE)) && \ + (0U != (ERRINT & CAN_ERRINT_EPIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_TTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_TTIF))) || \ + ((0U != (TTCFG & CAN_TTCFG_WTIE)) && \ + (0U != (TTCFG & CAN_TTCFG_WTIF)))) + { + CAN_2_IrqHandler(); + } + } + /* SPI Ch.3 Rx end */ + if (1UL == bM4_SPI3->CR1_b.RXIE) + { + if ((1UL == bM4_SPI3->SR_b.RDFF) && (0UL != (VSSEL138 & BIT_MASK_22))) + { + SPI_3_RxEnd_IrqHandler(); + } + } + /* SPI Ch.3 Tx buffer empty */ + if (1UL == bM4_SPI3->CR1_b.TXIE) + { + if ((1UL == bM4_SPI3->SR_b.TDEF) && (0UL != (VSSEL138 & BIT_MASK_23))) + { + SPI_3_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.3 Bus idle */ + if (1UL == bM4_SPI3->CR1_b.IDIE) + { + if ((0UL == bM4_SPI3->SR_b.IDLNF) && (0UL != (VSSEL138 & BIT_MASK_24))) + { + SPI_3_Idle_IrqHandler(); + } + } + /* SPI Ch.3 parity/overflow/underflow/mode error */ + if (1UL == bM4_SPI3->CR1_b.EIE) + { + u32Tmp1 = M4_SPI3->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_25))) + { + SPI_3_Err_IrqHandler(); + } + } + /* SPI Ch.4 Rx end */ + if (1UL == bM4_SPI4->CR1_b.RXIE) + { + if ((1UL == bM4_SPI4->SR_b.RDFF) && (0UL != (VSSEL138 & BIT_MASK_27))) + { + SPI_4_RxEnd_IrqHandler(); + } + } + /* SPI Ch.4 Tx buffer empty */ + if (1UL == bM4_SPI4->CR1_b.TXIE) + { + if ((1UL == bM4_SPI4->SR_b.TDEF) && (0UL != (VSSEL138 & BIT_MASK_28))) + { + SPI_4_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.4 Bus idle */ + if (1UL == bM4_SPI4->CR1_b.IDIE) + { + if ((0UL == bM4_SPI4->SR_b.IDLNF) && (0UL != (VSSEL138 & BIT_MASK_29))) + { + SPI_4_Idle_IrqHandler(); + } + } + /* SPI Ch.4 parity/overflow/underflow/mode error */ + if (1UL == bM4_SPI4->CR1_b.EIE) + { + u32Tmp1 = M4_SPI4->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL138 & BIT_MASK_30))) + { + SPI_4_Err_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.139 share IRQ handler + * @param None + * @retval None + */ +void IRQ139_Handler(void) +{ + const uint32_t VSSEL139 = M4_INTC->VSSEL139; + uint32_t u32Tmp1; + + /* TimerA Ch.9 overflow */ + if (1UL == bM4_TMRA_9->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_9->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_00))) + { + TMRA_9_Ovf_IrqHandler(); + } + } + /* TimerA Ch.9 underflow */ + if (1UL == bM4_TMRA_9->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_9->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_01))) + { + TMRA_9_Udf_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 1 */ + if (1UL == bM4_TMRA_9->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_9->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_02))) + { + TMRA_9_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 2 */ + if (1UL == bM4_TMRA_9->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_9->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_02))) + { + TMRA_9_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 3 */ + if (1UL == bM4_TMRA_9->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_9->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_02))) + { + TMRA_9_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.9 compare match 4 */ + if (1UL == bM4_TMRA_9->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_9->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_02))) + { + TMRA_9_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.10 overflow */ + if (1UL == bM4_TMRA_10->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_10->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_03))) + { + TMRA_10_Ovf_IrqHandler(); + } + } + /* TimerA Ch.10 underflow */ + if (1UL == bM4_TMRA_10->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_10->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_04))) + { + TMRA_10_Udf_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 1 */ + if (1UL == bM4_TMRA_10->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_10->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_05))) + { + TMRA_10_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 2 */ + if (1UL == bM4_TMRA_10->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_10->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_05))) + { + TMRA_10_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 3 */ + if (1UL == bM4_TMRA_10->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_10->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_05))) + { + TMRA_10_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.10 compare match 4 */ + if (1UL == bM4_TMRA_10->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_10->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_05))) + { + TMRA_10_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.11 overflow */ + if (1UL == bM4_TMRA_11->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_11->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_06))) + { + TMRA_11_Ovf_IrqHandler(); + } + } + /* TimerA Ch.11 underflow */ + if (1UL == bM4_TMRA_11->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_11->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_07))) + { + TMRA_11_Udf_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 1 */ + if (1UL == bM4_TMRA_11->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_11->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_08))) + { + TMRA_11_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 2 */ + if (1UL == bM4_TMRA_11->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_11->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_08))) + { + TMRA_11_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 3 */ + if (1UL == bM4_TMRA_11->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_11->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_08))) + { + TMRA_11_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.11 compare match 4 */ + if (1UL == bM4_TMRA_11->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_11->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_08))) + { + TMRA_11_Cmp4_IrqHandler(); + } + } + /* TimerA Ch.12 overflow */ + if (1UL == bM4_TMRA_12->BCSTR_b.ITENOVF) + { + if ((1UL == bM4_TMRA_12->BCSTR_b.OVFF) && (0UL != (VSSEL139 & BIT_MASK_09))) + { + TMRA_12_Ovf_IrqHandler(); + } + } + /* TimerA Ch.12 underflow */ + if (1UL == bM4_TMRA_12->BCSTR_b.ITENUDF) + { + if ((1UL == bM4_TMRA_12->BCSTR_b.UDFF) && (0UL != (VSSEL139 & BIT_MASK_10))) + { + TMRA_12_Udf_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 1 */ + if (1UL == bM4_TMRA_12->ICONR_b.ITEN1) + { + if ((1UL == bM4_TMRA_12->STFLR_b.CMPF1) && (0UL != (VSSEL139 & BIT_MASK_11))) + { + TMRA_12_Cmp1_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 2 */ + if (1UL == bM4_TMRA_12->ICONR_b.ITEN2) + { + if ((1UL == bM4_TMRA_12->STFLR_b.CMPF2) && (0UL != (VSSEL139 & BIT_MASK_11))) + { + TMRA_12_Cmp2_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 3 */ + if (1UL == bM4_TMRA_12->ICONR_b.ITEN3) + { + if ((1UL == bM4_TMRA_12->STFLR_b.CMPF3) && (0UL != (VSSEL139 & BIT_MASK_11))) + { + TMRA_12_Cmp3_IrqHandler(); + } + } + /* TimerA Ch.12 compare match 4 */ + if (1UL == bM4_TMRA_12->ICONR_b.ITEN4) + { + if ((1UL == bM4_TMRA_12->STFLR_b.CMPF4) && (0UL != (VSSEL139 & BIT_MASK_11))) + { + TMRA_12_Cmp4_IrqHandler(); + } + } + /* USART Ch.5 LIN bus break */ + if (1UL == bM4_USART5->CR2_b.LBDIE) + { + if ((1UL == bM4_USART5->SR_b.LBD) && (0UL != (VSSEL139 & BIT_MASK_12))) + { + USART_5_LinBreakField_IrqHandler(); + } + } + /* USART Ch.5 LIN bus wakeup */ + if (1UL == bM4_USART5->CR2_b.WKUPE) + { + if ((1UL == bM4_USART5->SR_b.WKUP) && (0UL != (VSSEL139 & BIT_MASK_12))) + { + USART_5_LinWakeup_IrqHandler(); + } + } + if (1UL == bM4_USART5->CR1_b.RIE) + { + /* USART Ch.5 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART5->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_13))) + { + USART_5_RxErr_IrqHandler(); + } + /* USART Ch.5 Rx end */ + if ((1UL == bM4_USART5->SR_b.RXNE) && (0UL != (VSSEL139 & BIT_MASK_14))) + { + USART_5_RxEnd_IrqHandler(); + } + } + /* USART Ch.5 Tx buffer empty */ + if (1UL == bM4_USART5->CR1_b.TXEIE) + { + if ((1UL == bM4_USART5->SR_b.TXE) && (0UL != (VSSEL139 & BIT_MASK_15))) + { + USART_5_TxEmpty_IrqHandler(); + } + } + /* USART Ch.5 Tx end */ + if (1UL == bM4_USART5->CR1_b.TCIE) + { + if ((1UL == bM4_USART5->SR_b.TC) && (0UL != (VSSEL139 & BIT_MASK_16))) + { + USART_5_TxEnd_IrqHandler(); + } + } + if (1UL == bM4_USART6->CR1_b.RIE) + { + /* USART Ch.6 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART6->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_17))) + { + USART_6_RxErr_IrqHandler(); + } + /* USART Ch.6 Rx end */ + if ((1UL == bM4_USART6->SR_b.RXNE) && (0UL != (VSSEL139 & BIT_MASK_18))) + { + USART_6_RxEnd_IrqHandler(); + } + } + /* USART Ch.6 Tx buffer empty */ + if (1UL == bM4_USART6->CR1_b.TXEIE) + { + if ((1UL == bM4_USART6->SR_b.TXE) && (0UL != (VSSEL139 & BIT_MASK_19))) + { + USART_6_TxEmpty_IrqHandler(); + } + } + /* USART Ch.6 Tx end */ + if (1UL == bM4_USART6->CR1_b.TCIE) + { + if ((1UL == bM4_USART6->SR_b.TC) && (0UL != (VSSEL139 & BIT_MASK_20))) + { + USART_6_TxEnd_IrqHandler(); + } + } + /* USART Ch.6 Tx timeout */ + if (1UL == bM4_USART6->CR1_b.RTOIE) + { + if ((1UL == bM4_USART6->SR_b.RTOF) && (0UL != (VSSEL139 & BIT_MASK_21))) + { + USART_6_RxTO_IrqHandler(); + } + } + /* SPI Ch.5 Rx end */ + if (1UL == bM4_SPI5->CR1_b.RXIE) + { + if ((1UL == bM4_SPI5->SR_b.RDFF) && (0UL != (VSSEL139 & BIT_MASK_22))) + { + SPI_5_RxEnd_IrqHandler(); + } + } + /* SPI Ch.5 Tx buffer empty */ + if (1UL == bM4_SPI5->CR1_b.TXIE) + { + if ((1UL == bM4_SPI5->SR_b.TDEF) && (0UL != (VSSEL139 & BIT_MASK_23))) + { + SPI_5_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.5 Bus idle */ + if (1UL == bM4_SPI5->CR1_b.IDIE) + { + if ((0UL == bM4_SPI5->SR_b.IDLNF) && (0UL != (VSSEL139 & BIT_MASK_24))) + { + SPI_5_Idle_IrqHandler(); + } + } + /* SPI Ch.5 parity/overflow/underflow/mode error */ + if (1UL == bM4_SPI5->CR1_b.EIE) + { + u32Tmp1 = M4_SPI5->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_25))) + { + SPI_5_Err_IrqHandler(); + } + } + /* SPI Ch.6 Rx end */ + if (1UL == bM4_SPI6->CR1_b.RXIE) + { + if ((1UL == bM4_SPI6->SR_b.RDFF) && (0UL != (VSSEL139 & BIT_MASK_27))) + { + SPI_6_RxEnd_IrqHandler(); + } + } + /* SPI Ch.6 Tx buffer empty */ + if (1UL == bM4_SPI6->CR1_b.TXIE) + { + if ((1UL == bM4_SPI6->SR_b.TDEF) && (0UL != (VSSEL139 & BIT_MASK_28))) + { + SPI_6_TxEmpty_IrqHandler(); + } + } + /* SPI Ch.6 Bus idle */ + if (1UL == bM4_SPI6->CR1_b.IDIE) + { + if ((0UL == bM4_SPI6->SR_b.IDLNF) && (0UL != (VSSEL139 & BIT_MASK_29))) + { + SPI_6_Idle_IrqHandler(); + } + } + /* SPI Ch.6 parity/overflow/underflow/mode error */ + if (1UL == bM4_SPI6->CR1_b.EIE) + { + u32Tmp1 = M4_SPI6->SR & (SPI_SR_OVRERF | SPI_SR_MODFERF | SPI_SR_PERF | SPI_SR_UDRERF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL139 & BIT_MASK_30))) + { + SPI_6_Err_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.140 share IRQ handler + * @param None + * @retval None + */ +void IRQ140_Handler(void) +{ + const uint32_t VSSEL140 = M4_INTC->VSSEL140; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + uint16_t NORINTST; + uint16_t NORINTSGEN; + uint16_t ERRINTSGEN; + uint32_t MMC_REVSTSR; + uint32_t MMC_TRSSTSR; + uint32_t MMC_RITCTLR; + uint32_t MMC_TITCTLR; + uint32_t DMA_DMASTSR; + uint32_t DMA_INTENAR; + uint32_t PTP_INTE; + uint32_t PMT_INTMASK; + uint32_t PMT_INTSTSR; + uint32_t PTP_INTMASK; + uint32_t PTP_INTSTSR; + + /* I2S Ch.1 Tx */ + if (1UL == bM4_I2S1->CTRL_b.TXIE) + { + if ((1UL == bM4_I2S1->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_00))) + { + I2S_1_Tx_IrqHandler(); + } + } + /* I2S Ch.1 Rx */ + if (1UL == bM4_I2S1->CTRL_b.RXIE) + { + if ((1UL == bM4_I2S1->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_01))) + { + I2S_1_Rx_IrqHandler(); + } + } + /* I2S Ch.1 Error */ + if (1UL == bM4_I2S1->CTRL_b.EIE) + { + u32Tmp1 = M4_I2S1->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_02))) + { + I2S_1_Err_IrqHandler(); + } + } + /* I2S Ch.2 Tx */ + if (1UL == bM4_I2S2->CTRL_b.TXIE) + { + if ((1UL == bM4_I2S2->SR_b.TXBA) && (0UL != (VSSEL140 & BIT_MASK_03))) + { + I2S_2_Tx_IrqHandler(); + } + } + /* I2S Ch.2 Rx */ + if (1UL == bM4_I2S2->CTRL_b.RXIE) + { + if ((1UL == bM4_I2S2->SR_b.RXBA) && (0UL != (VSSEL140 & BIT_MASK_04))) + { + I2S_2_Rx_IrqHandler(); + } + } + /* I2S Ch.2 Error */ + if (1UL == bM4_I2S2->CTRL_b.EIE) + { + u32Tmp1 = M4_I2S2->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_05))) + { + I2S_2_Err_IrqHandler(); + } + } + if (1UL == bM4_USART7->CR1_b.RIE) + { + /* USART Ch.7 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART7->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_06))) + { + USART_7_RxErr_IrqHandler(); + } + /* USART Ch.7 Rx end */ + if ((1UL == bM4_USART7->SR_b.RXNE) && (0UL != (VSSEL140 & BIT_MASK_07))) + { + USART_7_RxEnd_IrqHandler(); + } + } + /* USART Ch.7 Tx buffer empty */ + if (1UL == bM4_USART7->CR1_b.TXEIE) + { + if ((1UL == bM4_USART7->SR_b.TXE) && (0UL != (VSSEL140 & BIT_MASK_08))) + { + USART_7_TxEmpty_IrqHandler(); + } + } + /* USART Ch.7 Tx end */ + if (1UL == bM4_USART7->CR1_b.TCIE) + { + if ((1UL == bM4_USART7->SR_b.TC) && (0UL != (VSSEL140 & BIT_MASK_09))) + { + USART_7_TxEnd_IrqHandler(); + } + } + /* USART Ch.7 Tx timeout */ + if (1UL == bM4_USART7->CR1_b.RTOIE) + { + if ((1UL == bM4_USART7->SR_b.RTOF) && (0UL != (VSSEL140 & BIT_MASK_10))) + { + USART_7_RxTO_IrqHandler(); + } + } + if (1UL == bM4_USART8->CR1_b.RIE) + { + /* USART Ch.8 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART8->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL140 & BIT_MASK_11))) + { + USART_8_RxErr_IrqHandler(); + } + /* USART Ch.8 Rx end */ + if ((1UL == bM4_USART8->SR_b.RXNE) && (0UL != (VSSEL140 & BIT_MASK_12))) + { + USART_8_RxEnd_IrqHandler(); + } + } + /* USART Ch.8 Tx buffer empty */ + if (1UL == bM4_USART8->CR1_b.TXEIE) + { + if ((1UL == bM4_USART8->SR_b.TXE) && (0UL != (VSSEL140 & BIT_MASK_13))) + { + USART_8_TxEmpty_IrqHandler(); + } + } + /* USART Ch.8 Tx end */ + if (1UL == bM4_USART8->CR1_b.TCIE) + { + if ((1UL == bM4_USART8->SR_b.TC) && (0UL != (VSSEL140 & BIT_MASK_14))) + { + USART_8_TxEnd_IrqHandler(); + } + } + /* USB FS global interrupt */ + if (1UL == bM4_USBFS->GAHBCFG_b.GLBLINTRMSK) + { + u32Tmp1 = M4_USBFS->GINTMSK & 0xF77CFCFBUL; + u32Tmp2 = M4_USBFS->GINTSTS & 0xF77CFCFBUL; + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL140 & BIT_MASK_15))) + { + USBFS_Global_IrqHandler(); + } + } + /* SDIO unit 1 */ + if (0UL != (VSSEL140 & BIT_MASK_20)) + { + NORINTST = M4_SDIOC1->NORINTST & (SDIOC_NORINTST_CINT | SDIOC_NORINTST_CRM | SDIOC_NORINTST_CIST | \ + SDIOC_NORINTST_BRR | SDIOC_NORINTST_BWR | SDIOC_NORINTST_BGE | \ + SDIOC_NORINTST_TC | SDIOC_NORINTST_CC); + NORINTSGEN = M4_SDIOC1->NORINTSGEN & (SDIOC_NORINTSTEN_CINTEN | SDIOC_NORINTSTEN_CRMEN | \ + SDIOC_NORINTSTEN_CISTEN | SDIOC_NORINTSTEN_BRREN | \ + SDIOC_NORINTSTEN_BWREN | SDIOC_NORINTSTEN_BGEEN | \ + SDIOC_NORINTSTEN_TCEN | SDIOC_NORINTSTEN_CCEN); + ERRINTSGEN = M4_SDIOC1->ERRINTSGEN & (SDIOC_ERRINTSTEN_ACEEN | SDIOC_ERRINTSTEN_DEBEEN | \ + SDIOC_ERRINTSTEN_DCEEN | SDIOC_ERRINTSTEN_DTOEEN | \ + SDIOC_ERRINTSTEN_CIEEN | SDIOC_ERRINTSTEN_CEBEEN | \ + SDIOC_ERRINTSTEN_CCEEN | SDIOC_ERRINTSTEN_CTOEEN); + if (0U != (NORINTST & NORINTSGEN)) + { + SDIOC_1_Normal_IrqHandler(); + } + if ((1UL == bM4_SDIOC1->NORINTST_b.EI) && (0U != ERRINTSGEN)) + { + SDIOC_1_Error_IrqHandler(); + } + } + /* SDIO unit 2 */ + if (0UL != (VSSEL140 & BIT_MASK_23)) + { + NORINTST = M4_SDIOC2->NORINTST & (SDIOC_NORINTST_CINT | SDIOC_NORINTST_CRM | SDIOC_NORINTST_CIST | \ + SDIOC_NORINTST_BRR | SDIOC_NORINTST_BWR | SDIOC_NORINTST_BGE | \ + SDIOC_NORINTST_TC | SDIOC_NORINTST_CC); + NORINTSGEN = M4_SDIOC2->NORINTSGEN & (SDIOC_NORINTSTEN_CINTEN | SDIOC_NORINTSTEN_CRMEN | \ + SDIOC_NORINTSTEN_CISTEN | SDIOC_NORINTSTEN_BRREN | \ + SDIOC_NORINTSTEN_BWREN | SDIOC_NORINTSTEN_BGEEN | \ + SDIOC_NORINTSTEN_TCEN | SDIOC_NORINTSTEN_CCEN); + ERRINTSGEN = M4_SDIOC2->ERRINTSGEN & (SDIOC_ERRINTSTEN_ACEEN | SDIOC_ERRINTSTEN_DEBEEN | \ + SDIOC_ERRINTSTEN_DCEEN | SDIOC_ERRINTSTEN_DTOEEN | \ + SDIOC_ERRINTSTEN_CIEEN | SDIOC_ERRINTSTEN_CEBEEN | \ + SDIOC_ERRINTSTEN_CCEEN | SDIOC_ERRINTSTEN_CTOEEN); + if (0U != (NORINTST & NORINTSGEN)) + { + SDIOC_2_Normal_IrqHandler(); + } + if ((1UL == bM4_SDIOC2->NORINTST_b.EI) && (0U != ERRINTSGEN)) + { + SDIOC_2_Error_IrqHandler(); + } + } + /* Ethernat global */ + MMC_REVSTSR = M4_ETH->MMC_REVSTSR & (ETH_MMC_REVSTSR_RXOEIS | ETH_MMC_REVSTSR_RXLEIS | \ + ETH_MMC_REVSTSR_RXUGIS | ETH_MMC_REVSTSR_RXREIS | \ + ETH_MMC_REVSTSR_RXAEIS | ETH_MMC_REVSTSR_RXCEIS | \ + ETH_MMC_REVSTSR_RXMGIS | ETH_MMC_REVSTSR_RXBGIS); + MMC_TRSSTSR = M4_ETH->MMC_TRSSTSR & (ETH_MMC_TRSSTSR_TXEDEIS| ETH_MMC_TRSSTSR_TXUGIS | \ + ETH_MMC_TRSSTSR_TXCAEIS| ETH_MMC_TRSSTSR_TXECEIS| \ + ETH_MMC_TRSSTSR_TXLCEIS| ETH_MMC_TRSSTSR_TXDEEIS| \ + ETH_MMC_TRSSTSR_TXMGIS | ETH_MMC_TRSSTSR_TXBGIS); + MMC_RITCTLR = M4_ETH->MMC_RITCTLR & (ETH_MMC_RITCTLR_RXBGIM | ETH_MMC_RITCTLR_RXMGIM | \ + ETH_MMC_RITCTLR_RXCEIM | ETH_MMC_RITCTLR_RXAEIM | \ + ETH_MMC_RITCTLR_RXREIM | ETH_MMC_RITCTLR_RXUGIM | \ + ETH_MMC_RITCTLR_RXLEIM | ETH_MMC_RITCTLR_RXOEIM); + MMC_TITCTLR = M4_ETH->MMC_TITCTLR & (ETH_MMC_TITCTLR_TXBGIM | ETH_MMC_TITCTLR_TXMGIM | \ + ETH_MMC_TITCTLR_TXDEEIM| ETH_MMC_TITCTLR_TXLCEIM| \ + ETH_MMC_TITCTLR_TXECEIM| ETH_MMC_TITCTLR_TXCAEIM| \ + ETH_MMC_TITCTLR_TXUGIM | ETH_MMC_TITCTLR_TXEDEIM); + PMT_INTMASK = bM4_ETH->MAC_INTMSKR_b.PMTIM; + PMT_INTSTSR = bM4_ETH->MAC_INTSTSR_b.PMTIS; + PTP_INTMASK = bM4_ETH->MAC_INTMSKR_b.TSPIM; + PTP_INTSTSR = bM4_ETH->MAC_INTSTSR_b.TSPIS; + PTP_INTE = bM4_ETH->PTP_TSPCTLR_b.TSPINT; + + DMA_DMASTSR = M4_ETH->DMA_DMASTSR & (ETH_DMA_DMASTSR_AIS | ETH_DMA_DMASTSR_NIS); + DMA_INTENAR = M4_ETH->DMA_INTENAR & (ETH_DMA_INTENAR_AIE | ETH_DMA_INTENAR_NIE); + if (0UL != (VSSEL140 & BIT_MASK_28)) + { + if ((0UL != (MMC_REVSTSR & (~MMC_RITCTLR))) || \ + (0UL != (MMC_TRSSTSR & (~MMC_TITCTLR))) || \ + (0UL != (PMT_INTSTSR & (~PMT_INTMASK))) || \ + (0UL != (PTP_INTSTSR & (~PTP_INTMASK) & PTP_INTE)) || \ + (0UL != (DMA_DMASTSR & DMA_INTENAR))) + { + ETH_Global_IrqHandler(); + } + } + + /* Ethernat wakeup */ + if (0UL == bM4_ETH->MAC_INTMSKR_b.PMTIM) + { + if ((1UL == bM4_ETH->MAC_INTSTSR_b.PMTIS) && (0UL != (VSSEL140 & BIT_MASK_29))) + { + ETH_Wakeup_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.141 share IRQ handler + * @param None + * @retval None + */ +void IRQ141_Handler(void) +{ + const uint32_t VSSEL141 = M4_INTC->VSSEL141; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* I2S Ch.3 Tx */ + if (1UL == bM4_I2S3->CTRL_b.TXIE) + { + if ((1UL == bM4_I2S3->SR_b.TXBA) && (0UL != (VSSEL141 & BIT_MASK_00))) + { + I2S_3_Tx_IrqHandler(); + } + } + /* I2S Ch.3 Rx */ + if (1UL == bM4_I2S3->CTRL_b.RXIE) + { + if ((1UL == bM4_I2S3->SR_b.RXBA) && (0UL != (VSSEL141 & BIT_MASK_01))) + { + I2S_3_Rx_IrqHandler(); + } + } + /* I2S Ch.3 Error */ + if (1UL == bM4_I2S3->CTRL_b.EIE) + { + u32Tmp1 = M4_I2S3->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_02))) + { + I2S_3_Err_IrqHandler(); + } + } + /* I2S Ch.4 Tx */ + if (1UL == bM4_I2S4->CTRL_b.TXIE) + { + if ((1UL == bM4_I2S4->SR_b.TXBA) && (0UL != (VSSEL141 & BIT_MASK_03))) + { + I2S_4_Tx_IrqHandler(); + } + } + /* I2S Ch.4 Rx */ + if (1UL == bM4_I2S4->CTRL_b.RXIE) + { + if ((1UL == bM4_I2S4->SR_b.RXBA) && (0UL != (VSSEL141 & BIT_MASK_04))) + { + I2S_4_Rx_IrqHandler(); + } + } + /* I2S Ch.4 Error */ + if (1UL == bM4_I2S4->CTRL_b.EIE) + { + u32Tmp1 = M4_I2S4->ER & (I2S_ER_TXERR | I2S_ER_RXERR); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_05))) + { + I2S_4_Err_IrqHandler(); + } + } + if (1UL == bM4_USART9->CR1_b.RIE) + { + /* USART Ch.9 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART9->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_06))) + { + USART_9_RxErr_IrqHandler(); + } + /* USART Ch.9 Rx end */ + if ((1UL == bM4_USART9->SR_b.RXNE) && (0UL != (VSSEL141 & BIT_MASK_07))) + { + USART_9_RxEnd_IrqHandler(); + } + } + /* USART Ch.9 Tx buffer empty */ + if (1UL == bM4_USART9->CR1_b.TXEIE) + { + if ((1UL == bM4_USART9->SR_b.TXE) && (0UL != (VSSEL141 & BIT_MASK_08))) + { + USART_9_TxEmpty_IrqHandler(); + } + } + /* USART Ch.9 Tx end */ + if (1UL == bM4_USART9->CR1_b.TCIE) + { + if ((1UL == bM4_USART9->SR_b.TC) && (0UL != (VSSEL141 & BIT_MASK_09))) + { + USART_9_TxEnd_IrqHandler(); + } + } + /* USART Ch.10 LIN bus break */ + if (1UL == bM4_USART10->CR2_b.LBDIE) + { + if ((1UL == bM4_USART10->SR_b.LBD) && (0UL != (VSSEL141 & BIT_MASK_10))) + { + USART_10_LinBreakField_IrqHandler(); + } + } + /* USART Ch.10 LIN bus wakeup */ + if (1UL == bM4_USART10->CR2_b.WKUPE) + { + if ((1UL == bM4_USART10->SR_b.WKUP) && (0UL != (VSSEL141 & BIT_MASK_10))) + { + USART_10_LinWakeup_IrqHandler(); + } + } + if (1UL == bM4_USART10->CR1_b.RIE) + { + /* USART Ch.10 Rx ORE/FE/PE error */ + u32Tmp1 = M4_USART10->SR & (USART_SR_PE | USART_SR_FE | USART_SR_ORE); + if ((0UL != u32Tmp1) && (0UL != (VSSEL141 & BIT_MASK_11))) + { + USART_10_RxErr_IrqHandler(); + } + /* USART Ch.10 Rx end */ + if ((1UL == bM4_USART10->SR_b.RXNE) && (0UL != (VSSEL141 & BIT_MASK_12))) + { + USART_10_RxEnd_IrqHandler(); + } + } + /* USART Ch.10 Tx buffer empty */ + if (1UL == bM4_USART10->CR1_b.TXEIE) + { + if ((1UL == bM4_USART10->SR_b.TXE) && (0UL != (VSSEL141 & BIT_MASK_13))) + { + USART_10_TxEmpty_IrqHandler(); + } + } + /* USART Ch.10 Tx end */ + if (1UL == bM4_USART10->CR1_b.TCIE) + { + if ((1UL == bM4_USART10->SR_b.TC) && (0UL != (VSSEL141 & BIT_MASK_14))) + { + USART_10_TxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Rx end */ + if (1UL == bM4_I2C1->CR2_b.RFULLIE) + { + if ((1UL == bM4_I2C1->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_16))) + { + I2C_1_RxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Tx buffer empty */ + if (1UL == bM4_I2C1->CR2_b.TEMPTYIE) + { + if ((1UL == bM4_I2C1->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_17))) + { + I2C_1_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.1 Tx end */ + if (1UL == bM4_I2C1->CR2_b.TENDIE) + { + if ((1UL == bM4_I2C1->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_18))) + { + I2C_1_TxEnd_IrqHandler(); + } + } + /* I2C Ch.1 Error */ + u32Tmp1 = M4_I2C1->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = M4_I2C1->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_19))) + { + I2C_1_Err_IrqHandler(); + } + /* I2C Ch.2 Rx end */ + if (1UL == bM4_I2C2->CR2_b.RFULLIE) + { + if ((1UL == bM4_I2C2->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_20))) + { + I2C_2_RxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Tx buffer empty */ + if (1UL == bM4_I2C2->CR2_b.TEMPTYIE) + { + if ((1UL == bM4_I2C2->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_21))) + { + I2C_2_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.2 Tx end */ + if (1UL == bM4_I2C2->CR2_b.TENDIE) + { + if ((1UL == bM4_I2C2->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_22))) + { + I2C_2_TxEnd_IrqHandler(); + } + } + /* I2C Ch.2 Error */ + u32Tmp1 = M4_I2C2->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = M4_I2C2->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_23))) + { + I2C_2_Err_IrqHandler(); + } + /* I2C Ch.3 Rx end */ + if (1UL == bM4_I2C3->CR2_b.RFULLIE) + { + if ((1UL == bM4_I2C3->SR_b.RFULLF) && (0UL != (VSSEL141 & BIT_MASK_24))) + { + I2C_3_RxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Tx buffer empty */ + if (1UL == bM4_I2C3->CR2_b.TEMPTYIE) + { + if ((1UL == bM4_I2C3->SR_b.TEMPTYF) && (0UL != (VSSEL141 & BIT_MASK_25))) + { + I2C_3_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.3 Tx end */ + if (1UL == bM4_I2C3->CR2_b.TENDIE) + { + if ((1UL == bM4_I2C3->SR_b.TENDF) && (0UL != (VSSEL141 & BIT_MASK_26))) + { + I2C_3_TxEnd_IrqHandler(); + } + } + /* I2C Ch.3 Error */ + u32Tmp1 = M4_I2C3->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = M4_I2C3->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL141 & BIT_MASK_27))) + { + I2C_3_Err_IrqHandler(); + } +} + +/** + * @brief Interrupt No.142 share IRQ handler + * @param None + * @retval None + */ +void IRQ142_Handler(void) +{ + const uint32_t VSSEL142 = M4_INTC->VSSEL142; + uint32_t u32Tmp1; + uint32_t u32Tmp2; + + /* I2C Ch.4 Rx end */ + if (1UL == bM4_I2C4->CR2_b.RFULLIE) + { + if ((1UL == bM4_I2C4->SR_b.RFULLF) && (0UL != (VSSEL142 & BIT_MASK_00))) + { + I2C_4_RxEnd_IrqHandler(); + } + } + /* I2C Ch.4 Tx buffer empty */ + if (1UL == bM4_I2C4->CR2_b.TEMPTYIE) + { + if ((1UL == bM4_I2C4->SR_b.TEMPTYF) && (0UL != (VSSEL142 & BIT_MASK_01))) + { + I2C_4_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.4 Tx end */ + if (1UL == bM4_I2C4->CR2_b.TENDIE) + { + if ((1UL == bM4_I2C4->SR_b.TENDF) && (0UL != (VSSEL142 & BIT_MASK_02))) + { + I2C_4_TxEnd_IrqHandler(); + } + } + /* I2C Ch.4 Error */ + u32Tmp1 = M4_I2C4->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = M4_I2C4->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL142 & BIT_MASK_03))) + { + I2C_4_Err_IrqHandler(); + } + /* I2C Ch.5 Rx end */ + if (1UL == bM4_I2C5->CR2_b.RFULLIE) + { + if ((1UL == bM4_I2C5->SR_b.RFULLF) && (0UL != (VSSEL142 & BIT_MASK_04))) + { + I2C_5_RxEnd_IrqHandler(); + } + } + /* I2C Ch.5 Tx buffer empty */ + if (1UL == bM4_I2C5->CR2_b.TEMPTYIE) + { + if ((1UL == bM4_I2C5->SR_b.TEMPTYF) && (0UL != (VSSEL142 & BIT_MASK_05))) + { + I2C_5_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.5 Tx end */ + if (1UL == bM4_I2C5->CR2_b.TENDIE) + { + if ((1UL == bM4_I2C5->SR_b.TENDF) && (0UL != (VSSEL142 & BIT_MASK_06))) + { + I2C_5_TxEnd_IrqHandler(); + } + } + /* I2C Ch.5 Error */ + u32Tmp1 = M4_I2C5->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = M4_I2C5->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL142 & BIT_MASK_07))) + { + I2C_5_Err_IrqHandler(); + } + /* I2C Ch.6 Rx end */ + if (1UL == bM4_I2C6->CR2_b.RFULLIE) + { + if ((1UL == bM4_I2C6->SR_b.RFULLF) && (0UL != (VSSEL142 & BIT_MASK_08))) + { + I2C_6_RxEnd_IrqHandler(); + } + } + /* I2C Ch.6 Tx buffer empty */ + if (1UL == bM4_I2C6->CR2_b.TEMPTYIE) + { + if ((1UL == bM4_I2C6->SR_b.TEMPTYF) && (0UL != (VSSEL142 & BIT_MASK_09))) + { + I2C_6_TxEmpty_IrqHandler(); + } + } + /* I2C Ch.6 Tx end */ + if (1UL == bM4_I2C6->CR2_b.TENDIE) + { + if ((1UL == bM4_I2C6->SR_b.TENDF) && (0UL != (VSSEL142 & BIT_MASK_10))) + { + I2C_6_TxEnd_IrqHandler(); + } + } + /* I2C Ch.6 Error */ + u32Tmp1 = M4_I2C6->CR2 & (I2C_CR2_SMBALRTIE | I2C_CR2_SMHOSTIE | I2C_CR2_SMBDEFAULTIE | \ + I2C_CR2_GENCALLIE | I2C_CR2_TMOUTIE | I2C_CR2_NACKIE | \ + I2C_CR2_ARLOIE | I2C_CR2_STOPIE | I2C_CR2_SLADDR1IE | \ + I2C_CR2_SLADDR0IE | I2C_CR2_STARTIE); + u32Tmp2 = M4_I2C6->SR & (I2C_SR_SMBALRTF | I2C_SR_SMBHOSTF | I2C_SR_SMBDEFAULTF | \ + I2C_SR_GENCALLF | I2C_SR_TMOUTF | I2C_SR_NACKF | \ + I2C_SR_ARLOF | I2C_SR_STOPF | I2C_SR_SLADDR1F | \ + I2C_SR_SLADDR0F | I2C_SR_STARTF); + if ((0UL != (u32Tmp1 & u32Tmp2)) && (0UL != (VSSEL142 & BIT_MASK_11))) + { + I2C_6_Err_IrqHandler(); + } + /* PVD Ch.1 */ + if (1UL == bM4_PWC->PVDCR1_b.PVD1IRE) + { + if ((1UL ==bM4_PWC->PVDDSR_b.PVD1DETFLG) && (0UL != (VSSEL142 & BIT_MASK_13))) + { + PWC_Pvd1_IrqHandler(); + } + } + /* PVD Ch.2 */ + if (1UL == bM4_PWC->PVDCR1_b.PVD2IRE) + { + if ((1UL ==bM4_PWC->PVDDSR_b.PVD2DETFLG) && (0UL != (VSSEL142 & BIT_MASK_14))) + { + PWC_Pvd2_IrqHandler(); + } + } + /* FCM error */ + if (1UL == bM4_FCM->RIER_b.ERRIE) + { + if ((1UL == bM4_FCM->SR_b.ERRF) && (0UL != (VSSEL142 & BIT_MASK_16))) + { + FCM_Err_IrqHandler(); + } + } + /* FCM end */ + if (1UL == bM4_FCM->RIER_b.MENDIE) + { + if ((1UL == bM4_FCM->SR_b.MENDF) && (0UL != (VSSEL142 & BIT_MASK_17))) + { + FCM_End_IrqHandler(); + } + } + /* FCM overflow */ + if (1UL == bM4_FCM->RIER_b.OVFIE) + { + if ((1UL == bM4_FCM->SR_b.OVF) && (0UL != (VSSEL142 & BIT_MASK_18))) + { + FCM_Ovf_IrqHandler(); + } + } + /* WDT underflow or refresh error */ + u32Tmp1 = M4_WDT->SR & (WDT_SR_UDF | WDT_SR_REF); + if ((0UL != u32Tmp1) && (0UL != (VSSEL142 & BIT_MASK_19))) + { + WDT_IrqHandler(); + } + /* CTC overflow or underflow error */ + if (1UL == bM4_CTC->CR1_b.ERRIE) + { + /* underflow */ + if ((1UL == bM4_CTC->STR_b.TRMUDF) && (0UL != (VSSEL142 & BIT_MASK_20))) + { + CTC_Udf_IrqHandler(); + } + /* overflow */ + if ((1UL == bM4_CTC->STR_b.TRMOVF) && (0UL != (VSSEL142 & BIT_MASK_20))) + { + CTC_Ovf_IrqHandler(); + } + } +} + +/** + * @brief Interrupt No.143 share IRQ handler + * @param None + * @retval None + */ +void IRQ143_Handler(void) +{ + const uint32_t VSSEL143 = M4_INTC->VSSEL143; + uint32_t u32Tmp1; + + /* ADC unit1 sequence A */ + if (1UL == bM4_ADC1->ICR_b.EOCAIEN) + { + if ((1UL == bM4_ADC1->ISR_b.EOCAF) && (0UL != (VSSEL143 & BIT_MASK_00))) + { + ADC_1_SeqA_IrqHandler(); + } + } + /* ADC unit1 sequence B */ + if (1UL == bM4_ADC1->ICR_b.EOCBIEN) + { + if ((1UL == bM4_ADC1->ISR_b.EOCBF) && (0UL != (VSSEL143 & BIT_MASK_01))) + { + ADC_1_SeqB_IrqHandler(); + } + } + /* ADC unit1 window 0 compare */ + if (1UL == bM4_ADC1->AWDCR_b.AWD0IEN) + { + if ((1UL == bM4_ADC1->AWDSR_b.AWD0F) && (0UL != (VSSEL143 & BIT_MASK_02))) + { + ADC_1_Cmp0_IrqHandler(); + } + } + /* ADC unit1 window 1 compare */ + if (1UL == bM4_ADC1->AWDCR_b.AWD1IEN) + { + /* independence use */ + u32Tmp1 = (uint16_t)(M4_ADC1->AWDCR & ADC_AWDCR_AWDCM); + if ((1UL == bM4_ADC1->AWDSR_b.AWD1F) && (0UL == u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_03))) + { + ADC_1_Cmp1Ind_IrqHandler(); + } + /* combination use */ + if ((1UL == bM4_ADC1->AWDSR_b.AWDCMF) && (0UL != u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_03))) + { + ADC_1_Cmp1Comb_IrqHandler(); + } + } + /* ADC unit2 sequence A */ + if (1UL == bM4_ADC2->ICR_b.EOCAIEN) + { + if ((1UL == bM4_ADC2->ISR_b.EOCAF) && (0UL != (VSSEL143 & BIT_MASK_04))) + { + ADC_2_SeqA_IrqHandler(); + } + } + /* ADC unit2 sequence B */ + if (1UL == bM4_ADC2->ICR_b.EOCBIEN) + { + if ((1UL == bM4_ADC2->ISR_b.EOCBF) && (0UL != (VSSEL143 & BIT_MASK_05))) + { + ADC_2_SeqB_IrqHandler(); + } + } + /* ADC unit2 window 0 compare */ + if (1UL == bM4_ADC2->AWDCR_b.AWD0IEN) + { + if ((1UL == bM4_ADC2->AWDSR_b.AWD0F) && (0UL != (VSSEL143 & BIT_MASK_06))) + { + ADC_2_Cmp0_IrqHandler(); + } + } + /* ADC unit2 window 1 compare */ + if (1UL == bM4_ADC2->AWDCR_b.AWD1IEN) + { + /* independence use */ + u32Tmp1 = ((uint16_t)(M4_ADC2->AWDCR & ADC_AWDCR_AWDCM)); + if ((1UL == bM4_ADC2->AWDSR_b.AWD1F) && (0UL == u32Tmp1) && (0UL != (0UL != (VSSEL143 & BIT_MASK_07)))) + { + ADC_2_Cmp1Ind_IrqHandler(); + } + /* combination use */ + if ((1UL == bM4_ADC2->AWDSR_b.AWDCMF) && (0UL != u32Tmp1) && (0UL != (0UL != (VSSEL143 & BIT_MASK_07)))) + { + ADC_2_Cmp1Comb_IrqHandler(); + } + } + /* ADC unit3 sequence A */ + if (1UL == bM4_ADC3->ICR_b.EOCAIEN) + { + if ((1UL == bM4_ADC3->ISR_b.EOCAF) && (0UL != (VSSEL143 & BIT_MASK_04))) + { + ADC_3_SeqA_IrqHandler(); + } + } + /* ADC unit3 sequence B */ + if (1UL == bM4_ADC3->ICR_b.EOCBIEN) + { + if ((1UL == bM4_ADC3->ISR_b.EOCBF) && (0UL != (VSSEL143 & BIT_MASK_08))) + { + ADC_3_SeqB_IrqHandler(); + } + } + /* ADC unit3 window 0 compare */ + if (1UL == bM4_ADC3->AWDCR_b.AWD0IEN) + { + if ((1UL == bM4_ADC3->AWDSR_b.AWD0F) && (0UL != (VSSEL143 & BIT_MASK_09))) + { + ADC_3_Cmp0_IrqHandler(); + } + } + /* ADC unit3 window 1 compare */ + if (1UL == bM4_ADC3->AWDCR_b.AWD1IEN) + { + /* independence use */ + u32Tmp1 = (uint16_t)(M4_ADC3->AWDCR & ADC_AWDCR_AWDCM); + if ((1UL == bM4_ADC3->AWDSR_b.AWD1F) && (0UL == u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_10))) + { + ADC_3_Cmp1Ind_IrqHandler(); + } + /* combination use */ + if ((1UL == bM4_ADC3->AWDSR_b.AWDCMF) && (0UL != u32Tmp1) && (0UL != (VSSEL143 & BIT_MASK_10))) + { + ADC_3_Cmp1Comb_IrqHandler(); + } + } + if (0UL != (VSSEL143 & BIT_MASK_16)) + { + if (0UL != (M4_NFC->IRSR & (NFC_IRSR_RBRS | NFC_IRSR_ECCERS | \ + NFC_IRSR_ECCCRS | NFC_IRSR_ECCECRS | NFC_IRSR_ECCEURS))) + { + NFC_IrqHandler(); + } + } +} +/** + * @} + */ + +/** + * @defgroup INTC_Weakdef_Prototypes INTC weak function prototypes + * @{ + */ +__WEAKDEF void HardFault_IrqHandler(void) +{ +} +__WEAKDEF void MemManage_IrqHandler(void) +{ +} +__WEAKDEF void BusFault_IrqHandler(void) +{ +} +__WEAKDEF void UsageFault_IrqHandler(void) +{ +} +__WEAKDEF void SVC_IrqHandler(void) +{ +} +__WEAKDEF void DebugMon_IrqHandler(void) +{ +} +__WEAKDEF void PendSV_IrqHandler(void) +{ +} +__WEAKDEF void SysTick_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_00_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_01_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_02_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_03_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_04_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_05_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_06_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_07_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_08_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_09_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_10_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_11_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_12_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_13_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_14_IrqHandler(void) +{ +} +__WEAKDEF void EXTINT_15_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc0_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc1_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc2_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc3_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc4_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc5_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc6_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Tc7_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc0_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc1_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc2_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc3_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc4_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc5_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc6_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Btc7_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err0_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err1_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err2_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err3_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err4_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err5_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err6_IrqHandler(void) +{ +} +__WEAKDEF void DMA_1_Err7_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc0_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc1_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc2_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc3_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc4_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc5_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc6_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Tc7_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc0_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc1_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc2_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc3_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc4_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc5_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc6_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Btc7_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err0_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err1_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err2_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err3_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err4_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err5_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err6_IrqHandler(void) +{ +} +__WEAKDEF void DMA_2_Err7_IrqHandler(void) +{ +} +__WEAKDEF void EFM_PgmEraseErr_IrqHandler(void) +{ +} +__WEAKDEF void EFM_ColErr_IrqHandler(void) +{ +} +__WEAKDEF void EFM_OpEnd_IrqHandler(void) +{ +} +__WEAKDEF void QSPI_Err_IrqHandler(void) +{ +} +__WEAKDEF void MAU_Sqrt_IrqHandler(void) +{ +} +__WEAKDEF void DVP_FrameStart_IrqHandler(void) +{ +} +__WEAKDEF void DVP_FrameEnd_IrqHandler(void) +{ +} +__WEAKDEF void DVP_LineStart_IrqHandler(void) +{ +} +__WEAKDEF void DVP_LineEnd_IrqHandler(void) +{ +} +__WEAKDEF void DVP_SwSyncErr_IrqHandler(void) +{ +} +__WEAKDEF void DVP_FifoErr_IrqHandler(void) +{ +} +__WEAKDEF void FMAC_1_IrqHandler(void) +{ +} +__WEAKDEF void FMAC_2_IrqHandler(void) +{ +} +__WEAKDEF void FMAC_3_IrqHandler(void) +{ +} +__WEAKDEF void FMAC_4_IrqHandler(void) +{ +} +__WEAKDEF void DCU_1_IrqHandler(void) +{ +} +__WEAKDEF void DCU_2_IrqHandler(void) +{ +} +__WEAKDEF void DCU_3_IrqHandler(void) +{ +} +__WEAKDEF void DCU_4_IrqHandler(void) +{ +} +__WEAKDEF void DCU_5_IrqHandler(void) +{ +} +__WEAKDEF void DCU_6_IrqHandler(void) +{ +} +__WEAKDEF void DCU_7_IrqHandler(void) +{ +} +__WEAKDEF void DCU_8_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_1_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR0_2_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_1_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_2_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_3_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_CmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_CmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_OvfA_IrqHandler(void) +{ +} +__WEAKDEF void TMR2_4_OvfB_IrqHandler(void) +{ +} +__WEAKDEF void RTC_TimeStamp0_IrqHandler(void) +{ +} +__WEAKDEF void RTC_TimeStamp1_IrqHandler(void) +{ +} +__WEAKDEF void RTC_Alarm_IrqHandler(void) +{ +} +__WEAKDEF void RTC_Period_IrqHandler(void) +{ +} +__WEAKDEF void CLK_XtalStop_IrqHandler(void) +{ +} +__WEAKDEF void SWDT_IrqHandler(void) +{ +} +__WEAKDEF void WDT_IrqHandler(void) +{ +} +__WEAKDEF void PWC_WakeupTimer_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_1_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_2_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_3_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_4_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_5_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_6_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_7_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpC_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpD_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpE_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GCmpF_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GOvf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_GUdf_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_Gdte_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpUpA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpDownA_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpUpB_IrqHandler(void) +{ +} +__WEAKDEF void TMR6_8_SCmpDownB_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_1_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_2_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpUL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpVL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWH_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_GCmpWL_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadU_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadV_IrqHandler(void) +{ +} +__WEAKDEF void TMR4_3_ReloadW_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_1_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_2_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_3_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_4_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_5_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_6_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_7_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_8_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_9_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_10_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_11_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Udf_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp1_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp2_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp3_IrqHandler(void) +{ +} +__WEAKDEF void TMRA_12_Cmp4_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR0_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR1_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR2_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR3_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR4_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR5_IrqHandler(void) +{ +} +__WEAKDEF void EMB_GR6_IrqHandler(void) +{ +} +__WEAKDEF void USART_1_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_1_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_1_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_1_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART_2_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_2_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_2_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_2_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART_3_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_3_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_3_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_4_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_4_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_4_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_5_LinBreakField_IrqHandler(void) +{ +} +__WEAKDEF void USART_5_LinWakeup_IrqHandler(void) +{ +} +__WEAKDEF void USART_5_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_5_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_5_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_5_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_6_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_6_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_6_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_6_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_6_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART_7_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_7_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_7_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_7_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_7_RxTO_IrqHandler(void) +{ +} +__WEAKDEF void USART_8_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_8_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_8_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_8_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_9_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_9_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_9_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_9_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_10_LinBreakField_IrqHandler(void) +{ +} +__WEAKDEF void USART_10_LinWakeup_IrqHandler(void) +{ +} +__WEAKDEF void USART_10_RxErr_IrqHandler(void) +{ +} +__WEAKDEF void USART_10_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void USART_10_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void USART_10_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_1_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI_1_Err_IrqHandler(void) +{ +} +__WEAKDEF void SPI_1_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI_2_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI_2_Err_IrqHandler(void) +{ +} +__WEAKDEF void SPI_2_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI_3_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI_3_Err_IrqHandler(void) +{ +} +__WEAKDEF void SPI_3_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI_4_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI_4_Err_IrqHandler(void) +{ +} +__WEAKDEF void SPI_4_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI_5_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_5_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI_5_Err_IrqHandler(void) +{ +} +__WEAKDEF void SPI_5_Idle_IrqHandler(void) +{ +} +__WEAKDEF void SPI_6_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void SPI_6_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void SPI_6_Err_IrqHandler(void) +{ +} +__WEAKDEF void SPI_6_Idle_IrqHandler(void) +{ +} +__WEAKDEF void CAN_1_IrqHandler(void) +{ +} +__WEAKDEF void CAN_2_IrqHandler(void) +{ +} +__WEAKDEF void I2S_1_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_1_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_1_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2S_2_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_2_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_2_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2S_3_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_3_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_3_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2S_4_Tx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_4_Rx_IrqHandler(void) +{ +} +__WEAKDEF void I2S_4_Err_IrqHandler(void) +{ +} +__WEAKDEF void USBFS_Global_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC_1_Normal_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC_1_Error_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC_2_Normal_IrqHandler(void) +{ +} +__WEAKDEF void SDIOC_2_Error_IrqHandler(void) +{ +} +__WEAKDEF void ETH_Global_IrqHandler(void) +{ +} +__WEAKDEF void ETH_Wakeup_IrqHandler(void) +{ +} +__WEAKDEF void I2C_1_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_1_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_1_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C_1_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2C_2_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_2_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_2_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C_2_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2C_3_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_3_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_3_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C_3_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2C_4_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_4_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_4_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C_4_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2C_5_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_5_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_5_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C_5_Err_IrqHandler(void) +{ +} +__WEAKDEF void I2C_6_RxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_6_TxEnd_IrqHandler(void) +{ +} +__WEAKDEF void I2C_6_TxEmpty_IrqHandler(void) +{ +} +__WEAKDEF void I2C_6_Err_IrqHandler(void) +{ +} + +__WEAKDEF void PWC_Pvd1_IrqHandler(void) +{ +} +__WEAKDEF void PWC_Pvd2_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Err_IrqHandler(void) +{ +} +__WEAKDEF void FCM_End_IrqHandler(void) +{ +} +__WEAKDEF void FCM_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void CTC_Udf_IrqHandler(void) +{ +} +__WEAKDEF void CTC_Ovf_IrqHandler(void) +{ +} +__WEAKDEF void ADC_1_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC_1_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC_1_Cmp0_IrqHandler(void) +{ +} +__WEAKDEF void ADC_1_Cmp1Ind_IrqHandler(void) +{ +} +__WEAKDEF void ADC_1_Cmp1Comb_IrqHandler(void) +{ +} +__WEAKDEF void ADC_2_SeqA_IrqHandler(void) +{ +} +__WEAKDEF void ADC_2_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC_2_Cmp0_IrqHandler(void) +{ +} +__WEAKDEF void ADC_2_Cmp1Ind_IrqHandler(void) +{ +} +__WEAKDEF void ADC_2_Cmp1Comb_IrqHandler(void) +{ +} +__WEAKDEF extern void ADC_3_SeqA_IrqHandler(void) +{ +} +__WEAKDEF extern void ADC_3_SeqB_IrqHandler(void) +{ +} +__WEAKDEF void ADC_3_Cmp0_IrqHandler(void) +{ +} +__WEAKDEF void ADC_3_Cmp1Ind_IrqHandler(void) +{ +} +__WEAKDEF void ADC_3_Cmp1Comb_IrqHandler(void) +{ +} +__WEAKDEF void NFC_IrqHandler(void) +{ +} +/** + * @} + */ + +#endif /* DDL_INTERRUPTS_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.txt b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.txt new file mode 100644 index 0000000000000000000000000000000000000000..575caaed7908eee89068d96eea3c280000eefbaa --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.txt @@ -0,0 +1,1657 @@ + + +/** + * @brief Maximum IRQ handler number + */ +#define IRQ_NUM_MAX (128U) + +/** + * @brief Wakeup event enable mask + */ +#define INTC_WUPEN_MASK \ + (INTC_WUPEN_EIRQWUEN | INTC_WUPEN_SWDTWUEN | \ + INTC_WUPEN_PVD1WUEN | INTC_WUPEN_PVD2WUEN | \ + INTC_WUPEN_CMPWUEN | INTC_WUPEN_WKTMWUEN | \ + INTC_WUPEN_RTCALMWUEN | INTC_WUPEN_RTCPRDWUEN | \ + INTC_WUPEN_TMR0GCMWUEN | INTC_WUPEN_TMR2GCMWUEN | \ + INTC_WUPEN_TMR2OVFWUEN | INTC_WUPEN_RXWUEN | \ + INTC_WUPEN_USHWUEN | INTC_WUPEN_USFWUEN | \ + INTC_WUPEN_ETHWUEN) + +/** + * @} + */ + +/** + * @defgroup INTC_Check_Parameters_Validity INTC Check Parameters Validity + * @{ + */ +/*! Parameter validity check for wakeup source from stop mode. */ +#define IS_INTC_WKUP_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | INTC_WUPEN_MASK) == INTC_WUPEN_MASK)) + +/*! Parameter validity check for event index. */ +#define IS_INTC_EVENT(event) ((event) != 0x00UL) + +/*! Parameter validity check for interrupt index. */ +#define IS_INTC_INT(it) ((it) != 0x00UL) + +/*! Parameter validity check for software interrupt index. */ +#define IS_INTC_SWI(swi) ((swi) != 0x00UL) + +/*! Parameter validity check for NMI trigger source. */ +#define IS_NMI_SRC(src) \ +( ((src) != 0x00UL) && \ + (((src) | NMI_SRC_MASK) == NMI_SRC_MASK)) + +/*! Parameter validity check for EXINT filter A function. */ +#define IS_EXINT_FAE(fae) \ +( ((fae) == EXINT_FILTER_A_OFF) || \ + ((fae) == EXINT_FILTER_A_ON)) + +/*! Parameter validity check for EXINT filter A clock division. */ +#define IS_EXINT_FACLK(faclk) \ +( ((faclk) == EXINT_FACLK_HCLK_DIV1) || \ + ((faclk) == EXINT_FACLK_HCLK_DIV8) || \ + ((faclk) == EXINT_FACLK_HCLK_DIV32) || \ + ((faclk) == EXINT_FACLK_HCLK_DIV64)) + +/*! Parameter validity check for EXINT filter B function. */ +#define IS_EXINT_FBE(fbe) \ +( ((fbe) == EXINT_FILTER_B_OFF) || \ + ((fbe) == EXINT_FILTER_B_ON)) + +/*! Parameter validity check for EXINT filter B time. */ +#define IS_EXINT_FBTIME(fbtime) \ +( ((fbtime) == EXINT_FBTIM_500NS) || \ + ((fbtime) == EXINT_FBTIM_1US) || \ + ((fbtime) == EXINT_FBTIM_2US) || \ + ((fbtime) == EXINT_FBTIM_4US)) + + +/*! Parameter validity check for EXINT trigger edge. */ +#define IS_EXINT_TRIGGER(trigger) \ +( ((trigger) == EXINT_TRIGGER_LOW) || \ + ((trigger) == EXINT_TRIGGER_RISING) || \ + ((trigger) == EXINT_TRIGGER_FALLING) || \ + ((trigger) == EXINT_TRIGGER_BOTH)) + +/*! Parameter validity check for EXINT channel. */ +#define IS_EXINT_CH(ch) \ +( ((ch) != 0x00UL) && \ + (((ch) | EXINT_CH_MASK) == EXINT_CH_MASK)) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Local_Variable INTC Local Variable + * @{ + */ +static func_ptr_t m_apfnIrqHandler[IRQ_NUM_MAX] = {NULL}; +static func_ptr_t m_pfnNmiCallback; +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup INTC_Global_Functions INTC Global Functions + * @{ + */ +/** + * @brief IRQ sign in function + * @param [in] pstcIrqSignConfig: pointer of IRQ registration structure + * @arg enIntSrc: can be any value @ref en_int_src_t + * @arg enIRQn: can be any value from Int000_IRQn ~ Int127_IRQn @ref IRQn_Type + * @arg pfnCallback: Callback function + * @retval Ok: IRQ register successfully + * ErrorInvalidParameter: IRQ No. and Peripheral Int source are not match; + * NULL pointer. + * ErrorUninitialized: Specified IRQ entry was signed before. + */ +en_result_t INTC_IrqSignIn(const stc_irq_signin_config_t *pstcIrqSignConfig) + + +/** + * @brief IRQ sign out function + * @param [in] enIRQn: can be any value from Int000_IRQn ~ Int127_IRQn @ref IRQn_Type + * @retval Ok: IRQ sign out successfully + * ErrorInvalidParameter: IRQ No. is out of range + */ +en_result_t INTC_IrqSignOut(IRQn_Type enIRQn) + + +/** + * @brief Share IRQ configure + * @param [in] enIntSrc: Peripheral interrupt source @ref en_int_src_t + * @param [in] enNewState: + * @arg Enable: Enable corresponding peripheral interrupt in share IRQ handler + * @arg Disable: Disable corresponding peripheral interrupt in share IRQ handler + * @retval Ok: Share IRQ configure successfully + */ +en_result_t INTC_ShareIrqCmd(en_int_src_t enIntSrc, en_functional_state_t enNewState) + + +/** + * @brief Stop mode wake-up source configure + * @param [in] u32WakeupSrc: Wake-up source + * @arg INTC_WUPEN_EIRQWUEN + * @arg INTC_WUPEN_EIRQWUEN_0 + * @arg INTC_WUPEN_EIRQWUEN_1 + * @arg INTC_WUPEN_EIRQWUEN_2 + * @arg INTC_WUPEN_EIRQWUEN_3 + * @arg INTC_WUPEN_EIRQWUEN_4 + * @arg INTC_WUPEN_EIRQWUEN_5 + * @arg INTC_WUPEN_EIRQWUEN_6 + * @arg INTC_WUPEN_EIRQWUEN_7 + * @arg INTC_WUPEN_EIRQWUEN_8 + * @arg INTC_WUPEN_EIRQWUEN_9 + * @arg INTC_WUPEN_EIRQWUEN_10 + * @arg INTC_WUPEN_EIRQWUEN_11 + * @arg INTC_WUPEN_EIRQWUEN_12 + * @arg INTC_WUPEN_EIRQWUEN_13 + * @arg INTC_WUPEN_EIRQWUEN_14 + * @arg INTC_WUPEN_EIRQWUEN_15 + * @arg INTC_WUPEN_SWDTWUEN + * @arg INTC_WUPEN_PVD1WUEN + * @arg INTC_WUPEN_PVD2WUEN + * @arg INTC_WUPEN_CMPWUEN + * @arg INTC_WUPEN_WKTMWUEN + * @arg INTC_WUPEN_RTCALMWUEN + * @arg INTC_WUPEN_RTCPRDWUEN + * @arg INTC_WUPEN_TMR0GCMWUEN + * @arg INTC_WUPEN_TMR2GCMWUEN + * @arg INTC_WUPEN_TMR2OVFWUEN + * @arg INTC_WUPEN_RXWEN + * @arg INTC_WUPEN_USHWUEN + * @arg INTC_WUPEN_USFWUEN + * @arg INTC_WUPEN_ETHWUEN + * @param [in] enNewState + * @arg Enable: Enable corresponding wake up source + * @arg Disable: Disable corresponding wake up source + * @retval None + */ +void INTC_WakeupSrcCmd(uint32_t u32WakeupSrc, en_functional_state_t enNewState) + + +/** + * @brief Event or Interrupt output configure + * @param [in] u32Event: Event index + * @arg INTC_EVTER_EVTE0 + * @arg INTC_EVTER_EVTE1 + * @arg INTC_EVTER_EVTE2 + * @arg INTC_EVTER_EVTE3 + * @arg INTC_EVTER_EVTE4 + * @arg INTC_EVTER_EVTE5 + * @arg INTC_EVTER_EVTE6 + * @arg INTC_EVTER_EVTE7 + * @arg INTC_EVTER_EVTE8 + * @arg INTC_EVTER_EVTE9 + * @arg INTC_EVTER_EVTE10 + * @arg INTC_EVTER_EVTE11 + * @arg INTC_EVTER_EVTE12 + * @arg INTC_EVTER_EVTE13 + * @arg INTC_EVTER_EVTE14 + * @arg INTC_EVTER_EVTE15 + * @arg INTC_EVTER_EVTE16 + * @arg INTC_EVTER_EVTE17 + * @arg INTC_EVTER_EVTE18 + * @arg INTC_EVTER_EVTE19 + * @arg INTC_EVTER_EVTE20 + * @arg INTC_EVTER_EVTE21 + * @arg INTC_EVTER_EVTE22 + * @arg INTC_EVTER_EVTE23 + * @arg INTC_EVTER_EVTE24 + * @arg INTC_EVTER_EVTE25 + * @arg INTC_EVTER_EVTE26 + * @arg INTC_EVTER_EVTE27 + * @arg INTC_EVTER_EVTE28 + * @arg INTC_EVTER_EVTE29 + * @arg INTC_EVTER_EVTE30 + * @arg INTC_EVTER_EVTE31 + * @param [in] enNewState + * @arg Enable: Enable corresponding event to NVIC + * @arg Disable: Disable corresponding event but interrupt to NVIC + * @retval None + */ +void INTC_EventCmd(uint32_t u32Event, en_functional_state_t enNewState) + + +/** + * @brief Interrupt function configure + * @param [in] u32Int: Interrupt index + * @arg INTC_IER_IER0 + * @arg INTC_IER_IER1 + * @arg INTC_IER_IER2 + * @arg INTC_IER_IER3 + * @arg INTC_IER_IER4 + * @arg INTC_IER_IER5 + * @arg INTC_IER_IER6 + * @arg INTC_IER_IER7 + * @arg INTC_IER_IER8 + * @arg INTC_IER_IER9 + * @arg INTC_IER_IER10 + * @arg INTC_IER_IER11 + * @arg INTC_IER_IER12 + * @arg INTC_IER_IER13 + * @arg INTC_IER_IER14 + * @arg INTC_IER_IER15 + * @arg INTC_IER_IER16 + * @arg INTC_IER_IER17 + * @arg INTC_IER_IER18 + * @arg INTC_IER_IER19 + * @arg INTC_IER_IER20 + * @arg INTC_IER_IER21 + * @arg INTC_IER_IER22 + * @arg INTC_IER_IER23 + * @arg INTC_IER_IER24 + * @arg INTC_IER_IER25 + * @arg INTC_IER_IER26 + * @arg INTC_IER_IER27 + * @arg INTC_IER_IER28 + * @arg INTC_IER_IER29 + * @arg INTC_IER_IER30 + * @arg INTC_IER_IER31 + * @param [in] enNewState + * @arg Enable: Enable corresponding interrupt to NVIC + * @arg Disable: Disable corresponding interrupt to NVIC + * @retval None + */ +void INTC_IntCmd(uint32_t u32Int, en_functional_state_t enNewState) + + +/** + * @brief Software Interrupt function configure + * @param [in] u32SWI: Software Interrupt index + * @arg INTC_SWIER_SWIE0 + * @arg INTC_SWIER_SWIE1 + * @arg INTC_SWIER_SWIE2 + * @arg INTC_SWIER_SWIE3 + * @arg INTC_SWIER_SWIE4 + * @arg INTC_SWIER_SWIE5 + * @arg INTC_SWIER_SWIE6 + * @arg INTC_SWIER_SWIE7 + * @arg INTC_SWIER_SWIE8 + * @arg INTC_SWIER_SWIE9 + * @arg INTC_SWIER_SWIE10 + * @arg INTC_SWIER_SWIE11 + * @arg INTC_SWIER_SWIE12 + * @arg INTC_SWIER_SWIE13 + * @arg INTC_SWIER_SWIE14 + * @arg INTC_SWIER_SWIE15 + * @arg INTC_SWIER_SWIE16 + * @arg INTC_SWIER_SWIE17 + * @arg INTC_SWIER_SWIE18 + * @arg INTC_SWIER_SWIE19 + * @arg INTC_SWIER_SWIE20 + * @arg INTC_SWIER_SWIE21 + * @arg INTC_SWIER_SWIE22 + * @arg INTC_SWIER_SWIE23 + * @arg INTC_SWIER_SWIE24 + * @arg INTC_SWIER_SWIE25 + * @arg INTC_SWIER_SWIE26 + * @arg INTC_SWIER_SWIE27 + * @arg INTC_SWIER_SWIE28 + * @arg INTC_SWIER_SWIE29 + * @arg INTC_SWIER_SWIE30 + * @arg INTC_SWIER_SWIE31 + * @param [in] enNewState + * @arg Enable: Enable corresponding software interrupt + * @arg Disable: Disable corresponding software interrupt + * @retval None + */ +void INTC_SWICmd(uint32_t u32SWI, en_functional_state_t enNewState) + + +/** + * @brief Initialize NMI. Fill each pstcNmiInit with default value + * @param [in] pstcNmiInit: Pointer to a stc_nmi_init_t structure that + * contains configuration information. + * @retval Ok: NMI structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t NMI_StructInit(stc_nmi_init_t *pstcNmiInit) + + +/** + * @brief Initialize NMI. + * @param [in] pstcNmiInit: Pointer to a pstcNmiInit structure that + * contains configuration information. + * @retval Ok: NMI initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t NMI_Init(const stc_nmi_init_t *pstcNmiInit) + + +/** + * @brief Get NMI trigger source + * @param [in] u32NmiSrc: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @arg NMI_SRC_SWDT + * @arg NMI_SRC_PVD1 + * @arg NMI_SRC_PVD2 + * @arg NMI_SRC_XTAL + * @arg NMI_SRC_SRAM_PARITY + * @arg NMI_SRC_SRAM_ECC + * @arg NMI_SRC_BUS_ERR + * @arg NMI_SRC_WDT + * @retval Set: NMI is triggered by corresponding source + * Reset: NMI is not triggered by corresponding source + */ +en_flag_status_t NMI_GetNmiSrc(uint32_t u32NmiSrc) + + +/** + * @brief Set NMI trigger source + * @param [in] u32NmiSrc: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @arg NMI_SRC_SWDT + * @arg NMI_SRC_PVD1 + * @arg NMI_SRC_PVD2 + * @arg NMI_SRC_XTAL + * @arg NMI_SRC_SRAM_PARITY + * @arg NMI_SRC_SRAM_ECC + * @arg NMI_SRC_BUS_ERR + * @arg NMI_SRC_WDT + * @retval None + */ +void NMI_SetNmiSrc(uint32_t u32NmiSrc) + + +/** + * @brief Clear specified NMI trigger source + * @param [in] u32NmiSrc: NMI trigger source, @ref NMI_TriggerSrc_Sel for details + * @arg NMI_SRC_SWDT + * @arg NMI_SRC_PVD1 + * @arg NMI_SRC_PVD2 + * @arg NMI_SRC_XTAL + * @arg NMI_SRC_SRAM_PARITY + * @arg NMI_SRC_SRAM_ECC + * @arg NMI_SRC_BUS_ERR + * @arg NMI_SRC_WDT + * @retval None + */ +void NMI_ClrNmiSrc(uint32_t u32NmiSrc) + + +/** + * @brief NMI IRQ handler + * @param None + * @retval None + */ +void NMI_IrqHandler(void) + + +/** + * @brief Initialize External interrupt. + * @param [in] pstcExIntInit: Pointer to a stc_exint_init_t structure that + * contains configuration information. + * @retval Ok: EXINT initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t EXINT_Init(const stc_exint_init_t *pstcExIntInit) + + +/** + * @brief Initialize ExInt. Fill each pstcExIntInit with default value + * @param [in] pstcExIntInit: Pointer to a stc_exint_init_t structure + * that contains configuration information. + * @retval Ok: EXINT structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t EXINT_StructInit(stc_exint_init_t *pstcExIntInit) + + +/** + * @brief Clear specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval None + */ +void EXINT_ClrExIntSrc(uint32_t u32ExIntCh) + + +/** + * @brief Get specified External interrupt trigger source + * @param [in] u32ExIntCh: External interrupt channel, @ref EXINT_Channel_Sel for details + * @arg EXINT_CH00 + * @arg EXINT_CH01 + * @arg EXINT_CH02 + * @arg EXINT_CH03 + * @arg EXINT_CH04 + * @arg EXINT_CH05 + * @arg EXINT_CH06 + * @arg EXINT_CH07 + * @arg EXINT_CH08 + * @arg EXINT_CH09 + * @arg EXINT_CH10 + * @arg EXINT_CH11 + * @arg EXINT_CH12 + * @arg EXINT_CH13 + * @arg EXINT_CH14 + * @arg EXINT_CH15 + * @retval Set: Specified channel of external interrupt is triggered + * Reset: Specified channel of external interrupt is not triggered + */ +en_flag_status_t EXINT_GetExIntSrc(uint32_t u32ExIntCh) + + +/** + * @brief NMI IRQ handler + * @param None + * @retval None + */ +void NMI_Handler(void) + + +/** + * @brief Hard Fault IRQ handler + * @param None + * @retval None + */ +void HardFault_Handler(void) + + +/** + * @brief SVCall IRQ handler + * @param None + * @retval None + */ +void SVC_Handler(void) + + +/** + * @brief PendSV IRQ handler + * @param None + * @retval None + */ +void PendSV_Handler(void) + + +/** + * @brief SysTick IRQ handler + * @param None + * @retval None + */ +void SysTick_Handler(void) + + +/** + * @brief Interrupt No.000 IRQ handler + * @param None + * @retval None + */ +void IRQ000_Handler(void) + + +/** + * @brief Interrupt No.001 IRQ handler + * @param None + * @retval None + */ +void IRQ001_Handler(void) + + +/** + * @brief Interrupt No.002 IRQ handler + * @param None + * @retval None + */ +void IRQ002_Handler(void) + + +/** + * @brief Interrupt No.003 IRQ handler + * @param None + * @retval None + */ +void IRQ003_Handler(void) + + +/** + * @brief Interrupt No.004 IRQ handler + * @param None + * @retval None + */ +void IRQ004_Handler(void) + + +/** + * @brief Interrupt No.005 IRQ handler + * @param None + * @retval None + */ +void IRQ005_Handler(void) + + +/** + * @brief Interrupt No.006 IRQ handler + * @param None + * @retval None + */ +void IRQ006_Handler(void) + + +/** + * @brief Interrupt No.007 IRQ handler + * @param None + * @retval None + */ +void IRQ007_Handler(void) + + +/** + * @brief Interrupt No.008 IRQ handler + * @param None + * @retval None + */ +void IRQ008_Handler(void) + + +/** + * @brief Interrupt No.009 IRQ handler + * @param None + * @retval None + */ +void IRQ009_Handler(void) + + +/** + * @brief Interrupt No.010 IRQ handler + * @param None + * @retval None + */ +void IRQ010_Handler(void) + + +/** + * @brief Interrupt No.011 IRQ handler + * @param None + * @retval None + */ +void IRQ011_Handler(void) + + +/** + * @brief Interrupt No.012 IRQ handler + * @param None + * @retval None + */ +void IRQ012_Handler(void) + + +/** + * @brief Interrupt No.013 IRQ handler + * @param None + * @retval None + */ +void IRQ013_Handler(void) + + +/** + * @brief Interrupt No.014 IRQ handler + * @param None + * @retval None + */ +void IRQ014_Handler(void) + + +/** + * @brief Interrupt No.015 IRQ handler + * @param None + * @retval None + */ +void IRQ015_Handler(void) + + +/** + * @brief Interrupt No.016 IRQ handler + * @param None + * @retval None + */ +void IRQ016_Handler(void) + + +/** + * @brief Interrupt No.017 IRQ handler + * @param None + * @retval None + */ +void IRQ017_Handler(void) + + +/** + * @brief Interrupt No.018 IRQ handler + * @param None + * @retval None + */ +void IRQ018_Handler(void) + + +/** + * @brief Interrupt No.019 IRQ handler + * @param None + * @retval None + */ +void IRQ019_Handler(void) + + +/** + * @brief Interrupt No.020 IRQ handler + * @param None + * @retval None + */ +void IRQ020_Handler(void) + + +/** + * @brief Interrupt No.021 IRQ handler + * @param None + * @retval None + */ +void IRQ021_Handler(void) + + +/** + * @brief Interrupt No.022 IRQ handler + * @param None + * @retval None + */ +void IRQ022_Handler(void) + + +/** + * @brief Interrupt No.023 IRQ handler + * @param None + * @retval None + */ +void IRQ023_Handler(void) + + +/** + * @brief Interrupt No.024 IRQ handler + * @param None + * @retval None + */ +void IRQ024_Handler(void) + + +/** + * @brief Interrupt No.025 IRQ handler + * @param None + * @retval None + */ +void IRQ025_Handler(void) + + +/** + * @brief Interrupt No.026 IRQ handler + * @param None + * @retval None + */ +void IRQ026_Handler(void) + + +/** + * @brief Interrupt No.027 IRQ handler + * @param None + * @retval None + */ +void IRQ027_Handler(void) + + +/** + * @brief Interrupt No.028 IRQ handler + * @param None + * @retval None + */ +void IRQ028_Handler(void) + + +/** + * @brief Interrupt No.029 IRQ handler + * @param None + * @retval None + */ +void IRQ029_Handler(void) + + +/** + * @brief Interrupt No.030 IRQ handler + * @param None + * @retval None + */ +void IRQ030_Handler(void) + + +/** + * @brief Interrupt No.031 IRQ handler + * @param None + * @retval None + */ +void IRQ031_Handler(void) + + +/** + * @brief Interrupt No.032 IRQ handler + * @param None + * @retval None + */ +void IRQ032_Handler(void) + + +/** + * @brief Interrupt No.033 IRQ handler + * @param None + * @retval None + */ +void IRQ033_Handler(void) + + +/** + * @brief Interrupt No.034 IRQ handler + * @param None + * @retval None + */ +void IRQ034_Handler(void) + + +/** + * @brief Interrupt No.035 IRQ handler + * @param None + * @retval None + */ +void IRQ035_Handler(void) + + +/** + * @brief Interrupt No.036 IRQ handler + * @param None + * @retval None + */ +void IRQ036_Handler(void) + + +/** + * @brief Interrupt No.037 IRQ handler + * @param None + * @retval None + */ +void IRQ037_Handler(void) + + +/** + * @brief Interrupt No.038 IRQ handler + * @param None + * @retval None + */ +void IRQ038_Handler(void) + + +/** + * @brief Interrupt No.039 IRQ handler + * @param None + * @retval None + */ +void IRQ039_Handler(void) + + +/** + * @brief Interrupt No.040 IRQ handler + * @param None + * @retval None + */ +void IRQ040_Handler(void) + + +/** + * @brief Interrupt No.041 IRQ handler + * @param None + * @retval None + */ +void IRQ041_Handler(void) + + +/** + * @brief Interrupt No.042 IRQ handler + * @param None + * @retval None + */ +void IRQ042_Handler(void) + + +/** + * @brief Interrupt No.043 IRQ handler + * @param None + * @retval None + */ +void IRQ043_Handler(void) + + +/** + * @brief Interrupt No.044 IRQ handler + * @param None + * @retval None + */ +void IRQ044_Handler(void) + + +/** + * @brief Interrupt No.045 IRQ handler + * @param None + * @retval None + */ +void IRQ045_Handler(void) + + +/** + * @brief Interrupt No.046 IRQ handler + * @param None + * @retval None + */ +void IRQ046_Handler(void) + + +/** + * @brief Interrupt No.047 IRQ handler + * @param None + * @retval None + */ +void IRQ047_Handler(void) + + +/** + * @brief Interrupt No.048 IRQ handler + * @param None + * @retval None + */ +void IRQ048_Handler(void) + + +/** + * @brief Interrupt No.049 IRQ handler + * @param None + * @retval None + */ +void IRQ049_Handler(void) + + +/** + * @brief Interrupt No.050 IRQ handler + * @param None + * @retval None + */ +void IRQ050_Handler(void) + + +/** + * @brief Interrupt No.051 IRQ handler + * @param None + * @retval None + */ +void IRQ051_Handler(void) + + +/** + * @brief Interrupt No.052 IRQ handler + * @param None + * @retval None + */ +void IRQ052_Handler(void) + + +/** + * @brief Interrupt No.053 IRQ handler + * @param None + * @retval None + */ +void IRQ053_Handler(void) + + +/** + * @brief Interrupt No.054 IRQ handler + * @param None + * @retval None + */ +void IRQ054_Handler(void) + + +/** + * @brief Interrupt No.055 IRQ handler + * @param None + * @retval None + */ +void IRQ055_Handler(void) + + +/** + * @brief Interrupt No.056 IRQ handler + * @param None + * @retval None + */ +void IRQ056_Handler(void) + + +/** + * @brief Interrupt No.057 IRQ handler + * @param None + * @retval None + */ +void IRQ057_Handler(void) + + +/** + * @brief Interrupt No.058 IRQ handler + * @param None + * @retval None + */ +void IRQ058_Handler(void) + + +/** + * @brief Interrupt No.059 IRQ handler + * @param None + * @retval None + */ +void IRQ059_Handler(void) + + +/** + * @brief Interrupt No.060 IRQ handler + * @param None + * @retval None + */ +void IRQ060_Handler(void) + + +/** + * @brief Interrupt No.061 IRQ handler + * @param None + * @retval None + */ +void IRQ061_Handler(void) + + +/** + * @brief Interrupt No.062 IRQ handler + * @param None + * @retval None + */ +void IRQ062_Handler(void) + + +/** + * @brief Interrupt No.063 IRQ handler + * @param None + * @retval None + */ +void IRQ063_Handler(void) + + +/** + * @brief Interrupt No.064 IRQ handler + * @param None + * @retval None + */ +void IRQ064_Handler(void) + + +/** + * @brief Interrupt No.065 IRQ handler + * @param None + * @retval None + */ +void IRQ065_Handler(void) + + +/** + * @brief Interrupt No.066 IRQ handler + * @param None + * @retval None + */ +void IRQ066_Handler(void) + + +/** + * @brief Interrupt No.067 IRQ handler + * @param None + * @retval None + */ +void IRQ067_Handler(void) + + +/** + * @brief Interrupt No.068 IRQ handler + * @param None + * @retval None + */ +void IRQ068_Handler(void) + + +/** + * @brief Interrupt No.069 IRQ handler + * @param None + * @retval None + */ +void IRQ069_Handler(void) + + +/** + * @brief Interrupt No.070 IRQ handler + * @param None + * @retval None + */ +void IRQ070_Handler(void) + + +/** + * @brief Interrupt No.071 IRQ handler + * @param None + * @retval None + */ +void IRQ071_Handler(void) + + +/** + * @brief Interrupt No.072 IRQ handler + * @param None + * @retval None + */ +void IRQ072_Handler(void) + + +/** + * @brief Interrupt No.073 IRQ handler + * @param None + * @retval None + */ +void IRQ073_Handler(void) + + +/** + * @brief Interrupt No.074 IRQ handler + * @param None + * @retval None + */ +void IRQ074_Handler(void) + + +/** + * @brief Interrupt No.075 IRQ handler + * @param None + * @retval None + */ +void IRQ075_Handler(void) + + +/** + * @brief Interrupt No.076 IRQ handler + * @param None + * @retval None + */ +void IRQ076_Handler(void) + + +/** + * @brief Interrupt No.077 IRQ handler + * @param None + * @retval None + */ +void IRQ077_Handler(void) + + +/** + * @brief Interrupt No.078 IRQ handler + * @param None + * @retval None + */ +void IRQ078_Handler(void) + + +/** + * @brief Interrupt No.079 IRQ handler + * @param None + * @retval None + */ +void IRQ079_Handler(void) + + +/** + * @brief Interrupt No.080 IRQ handler + * @param None + * @retval None + */ +void IRQ080_Handler(void) + + +/** + * @brief Interrupt No.081 IRQ handler + * @param None + * @retval None + */ +void IRQ081_Handler(void) + + +/** + * @brief Interrupt No.082 IRQ handler + * @param None + * @retval None + */ +void IRQ082_Handler(void) + + +/** + * @brief Interrupt No.083 IRQ handler + * @param None + * @retval None + */ +void IRQ083_Handler(void) + + +/** + * @brief Interrupt No.084 IRQ handler + * @param None + * @retval None + */ +void IRQ084_Handler(void) + + +/** + * @brief Interrupt No.085 IRQ handler + * @param None + * @retval None + */ +void IRQ085_Handler(void) + + +/** + * @brief Interrupt No.086 IRQ handler + * @param None + * @retval None + */ +void IRQ086_Handler(void) + + +/** + * @brief Interrupt No.087 IRQ handler + * @param None + * @retval None + */ +void IRQ087_Handler(void) + + +/** + * @brief Interrupt No.088 IRQ handler + * @param None + * @retval None + */ +void IRQ088_Handler(void) + + +/** + * @brief Interrupt No.089 IRQ handler + * @param None + * @retval None + */ +void IRQ089_Handler(void) + + +/** + * @brief Interrupt No.090 IRQ handler + * @param None + * @retval None + */ +void IRQ090_Handler(void) + + +/** + * @brief Interrupt No.091 IRQ handler + * @param None + * @retval None + */ +void IRQ091_Handler(void) + + +/** + * @brief Interrupt No.092 IRQ handler + * @param None + * @retval None + */ +void IRQ092_Handler(void) + + +/** + * @brief Interrupt No.093 IRQ handler + * @param None + * @retval None + */ +void IRQ093_Handler(void) + + +/** + * @brief Interrupt No.094 IRQ handler + * @param None + * @retval None + */ +void IRQ094_Handler(void) + + +/** + * @brief Interrupt No.095 IRQ handler + * @param None + * @retval None + */ +void IRQ095_Handler(void) + + +/** + * @brief Interrupt No.096 IRQ handler + * @param None + * @retval None + */ +void IRQ096_Handler(void) + + +/** + * @brief Interrupt No.097 IRQ handler + * @param None + * @retval None + */ +void IRQ097_Handler(void) + + +/** + * @brief Interrupt No.098 IRQ handler + * @param None + * @retval None + */ +void IRQ098_Handler(void) + + +/** + * @brief Interrupt No.099 IRQ handler + * @param None + * @retval None + */ +void IRQ099_Handler(void) + + +/** + * @brief Interrupt No.100 IRQ handler + * @param None + * @retval None + */ +void IRQ100_Handler(void) + + +/** + * @brief Interrupt No.101 IRQ handler + * @param None + * @retval None + */ +void IRQ101_Handler(void) + + +/** + * @brief Interrupt No.102 IRQ handler + * @param None + * @retval None + */ +void IRQ102_Handler(void) + + +/** + * @brief Interrupt No.103 IRQ handler + * @param None + * @retval None + */ +void IRQ103_Handler(void) + + +/** + * @brief Interrupt No.104 IRQ handler + * @param None + * @retval None + */ +void IRQ104_Handler(void) + + +/** + * @brief Interrupt No.105 IRQ handler + * @param None + * @retval None + */ +void IRQ105_Handler(void) + + +/** + * @brief Interrupt No.106 IRQ handler + * @param None + * @retval None + */ +void IRQ106_Handler(void) + + +/** + * @brief Interrupt No.107 IRQ handler + * @param None + * @retval None + */ +void IRQ107_Handler(void) + + +/** + * @brief Interrupt No.108 IRQ handler + * @param None + * @retval None + */ +void IRQ108_Handler(void) + + +/** + * @brief Interrupt No.109 IRQ handler + * @param None + * @retval None + */ +void IRQ109_Handler(void) + + +/** + * @brief Interrupt No.110 IRQ handler + * @param None + * @retval None + */ +void IRQ110_Handler(void) + + +/** + * @brief Interrupt No.111 IRQ handler + * @param None + * @retval None + */ +void IRQ111_Handler(void) + + +/** + * @brief Interrupt No.112 IRQ handler + * @param None + * @retval None + */ +void IRQ112_Handler(void) + + +/** + * @brief Interrupt No.113 IRQ handler + * @param None + * @retval None + */ +void IRQ113_Handler(void) + + +/** + * @brief Interrupt No.114 IRQ handler + * @param None + * @retval None + */ +void IRQ114_Handler(void) + + +/** + * @brief Interrupt No.115 IRQ handler + * @param None + * @retval None + */ +void IRQ115_Handler(void) + + +/** + * @brief Interrupt No.116 IRQ handler + * @param None + * @retval None + */ +void IRQ116_Handler(void) + + +/** + * @brief Interrupt No.117 IRQ handler + * @param None + * @retval None + */ +void IRQ117_Handler(void) + + +/** + * @brief Interrupt No.118 IRQ handler + * @param None + * @retval None + */ +void IRQ118_Handler(void) + + +/** + * @brief Interrupt No.119 IRQ handler + * @param None + * @retval None + */ +void IRQ119_Handler(void) + + +/** + * @brief Interrupt No.120 IRQ handler + * @param None + * @retval None + */ +void IRQ120_Handler(void) + + +/** + * @brief Interrupt No.121 IRQ handler + * @param None + * @retval None + */ +void IRQ121_Handler(void) + + +/** + * @brief Interrupt No.122 IRQ handler + * @param None + * @retval None + */ +void IRQ122_Handler(void) + + +/** + * @brief Interrupt No.123 IRQ handler + * @param None + * @retval None + */ +void IRQ123_Handler(void) + + +/** + * @brief Interrupt No.124 IRQ handler + * @param None + * @retval None + */ +void IRQ124_Handler(void) + + +/** + * @brief Interrupt No.125 IRQ handler + * @param None + * @retval None + */ +void IRQ125_Handler(void) + + +/** + * @brief Interrupt No.126 IRQ handler + * @param None + * @retval None + */ +void IRQ126_Handler(void) + + +/** + * @brief Interrupt No.127 IRQ handler + * @param None + * @retval None + */ +void IRQ127_Handler(void) + + +/** + * @brief Interrupt No.128 share IRQ handler + * @param None + * @retval None + */ +void IRQ128_Handler(void) + + +/** + * @brief Interrupt No.129 share IRQ handler + * @param None + * @retval None + */ +void IRQ129_Handler(void) + + +/** + * @brief Interrupt No.130 share IRQ handler + * @param None + * @retval None + */ +void IRQ130_Handler(void) + + +/** + * @brief Interrupt No.131 share IRQ handler + * @param None + * @retval None + */ +void IRQ131_Handler(void) + + +/** + * @brief Interrupt No.132 share IRQ handler + * @param None + * @retval None + */ +void IRQ132_Handler(void) + + +/** + * @brief Interrupt No.133 share IRQ handler + * @param None + * @retval None + */ +void IRQ133_Handler(void) + + +/** + * @brief Interrupt No.134 share IRQ handler + * @param None + * @retval None + */ +void IRQ134_Handler(void) + + +/** + * @brief Interrupt No.135 share IRQ handler + * @param None + * @retval None + */ +void IRQ135_Handler(void) + + +/** + * @brief Interrupt No.136 share IRQ handler + * @param None + * @retval None + */ +void IRQ136_Handler(void) + + +/** + * @brief Interrupt No.137 share IRQ handler + * @param None + * @retval None + */ +void IRQ137_Handler(void) + + +/** + * @brief Interrupt No.138 share IRQ handler + * @param None + * @retval None + */ +void IRQ138_Handler(void) + + +/** + * @brief Interrupt No.139 share IRQ handler + * @param None + * @retval None + */ +void IRQ139_Handler(void) + + +/** + * @brief Interrupt No.140 share IRQ handler + * @param None + * @retval None + */ +void IRQ140_Handler(void) + + +/** + * @brief Interrupt No.141 share IRQ handler + * @param None + * @retval None + */ +void IRQ141_Handler(void) + + +/** + * @brief Interrupt No.142 share IRQ handler + * @param None + * @retval None + */ +void IRQ142_Handler(void) + + +/** + * @brief Interrupt No.143 share IRQ handler + * @param None + * @retval None + */ +void IRQ143_Handler(void) diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_keyscan.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_keyscan.c new file mode 100644 index 0000000000000000000000000000000000000000..e89b654d52ff615237df1fe1aa44531a31daedf7 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_keyscan.c @@ -0,0 +1,232 @@ +/** + ******************************************************************************* + * @file hc32f4a0_keyscan.c + * @brief This file provides firmware functions to manage the matrix keyscan + * function (KEYSCAN). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_keyscan.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_KEYSCAN KEYSCAN + * @brief Matrix keyscan Driver Library + * @{ + */ + +#if (DDL_KEYSCAN_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Local_Macros KEYSCAN Local Macros + * @{ + */ + +/** + * @defgroup KEYSCAN_Check_Parameters_Validity KEYSCAN Check Parameters Validity + * @{ + */ +/*! Parameter valid check for KEYSCAN HiZ state cycles. */ +#define IS_KEYSCAN_HIZ_CLC(clc) \ +( ((clc) == KEYSCAN_HIZ_CLC_4) || \ + ((clc) == KEYSCAN_HIZ_CLC_8) || \ + ((clc) == KEYSCAN_HIZ_CLC_16) || \ + ((clc) == KEYSCAN_HIZ_CLC_32) || \ + ((clc) == KEYSCAN_HIZ_CLC_64) || \ + ((clc) == KEYSCAN_HIZ_CLC_256) || \ + ((clc) == KEYSCAN_HIZ_CLC_512) || \ + ((clc) == KEYSCAN_HIZ_CLC_1024)) + +/*! Parameter valid check for KEYSCAN low level output cycles. */ +#define IS_KEYSCAN_LOW_CLC(clc) \ +( ((clc) == KEYSCAN_LOW_CLC_4) || \ + ((clc) == KEYSCAN_LOW_CLC_8) || \ + ((clc) == KEYSCAN_LOW_CLC_16) || \ + ((clc) == KEYSCAN_LOW_CLC_32) || \ + ((clc) == KEYSCAN_LOW_CLC_64) || \ + ((clc) == KEYSCAN_LOW_CLC_128) || \ + ((clc) == KEYSCAN_LOW_CLC_256) || \ + ((clc) == KEYSCAN_LOW_CLC_512) || \ + ((clc) == KEYSCAN_LOW_CLC_1K) || \ + ((clc) == KEYSCAN_LOW_CLC_2K) || \ + ((clc) == KEYSCAN_LOW_CLC_4K) || \ + ((clc) == KEYSCAN_LOW_CLC_8K) || \ + ((clc) == KEYSCAN_LOW_CLC_16K) || \ + ((clc) == KEYSCAN_LOW_CLC_32K) || \ + ((clc) == KEYSCAN_LOW_CLC_64K) || \ + ((clc) == KEYSCAN_LOW_CLC_128K) || \ + ((clc) == KEYSCAN_LOW_CLC_256K) || \ + ((clc) == KEYSCAN_LOW_CLC_512K) || \ + ((clc) == KEYSCAN_LOW_CLC_1M) || \ + ((clc) == KEYSCAN_LOW_CLC_2M) || \ + ((clc) == KEYSCAN_LOW_CLC_4M) || \ + ((clc) == KEYSCAN_LOW_CLC_8M) || \ + ((clc) == KEYSCAN_LOW_CLC_16M)) + +/*! Parameter valid check for KEYSCAN scan clock. */ +#define IS_KEYSCAN_CLK(clk) \ +( ((clk) == KEYSCAN_CLK_HCLK) || \ + ((clk) == KEYSCAN_CLK_LRC) || \ + ((clk) == KEYSCAN_CLK_XTAL32)) + +/*! Parameter valid check for KEYSCAN keyout pins. */ +#define IS_KEYSCAN_OUT(out) \ +( ((out) == KEYSCAN_OUT_0T1) || \ + ((out) == KEYSCAN_OUT_0T2) || \ + ((out) == KEYSCAN_OUT_0T3) || \ + ((out) == KEYSCAN_OUT_0T4) || \ + ((out) == KEYSCAN_OUT_0T5) || \ + ((out) == KEYSCAN_OUT_0T6) || \ + ((out) == KEYSCAN_OUT_0T7)) + +/*! Parameter valid check for KEYSCAN keyin(EIRQ) pins. */ +#define IS_KEYSCAN_IN(in) \ +( ((in) != 0x00U) && \ + (((in) | KEYSCAN_IN_MASK) == KEYSCAN_IN_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup KEYSCAN_Global_Functions KEYSCAN Global Functions + * @{ + */ + +/** + * @brief KEYSCAN function config. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void KEYSCAN_Cmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(M4_KEYSCAN->SER, enNewState); +} + +/** + * @brief Initialize KEYSCAN config structure. Fill each pstcKeyscanInit with default value + * @param [in] pstcKeyscanInit Pointer to a stc_keyscan_init_t structure that + * contains configuration information. + * @retval Ok: KEYSCAN structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t KEYSCAN_StructInit(stc_keyscan_init_t *pstcKeyscanInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcKeyscanInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcKeyscanInit->u32HizCycle= KEYSCAN_HIZ_CLC_4; + pstcKeyscanInit->u32LowCycle= KEYSCAN_LOW_CLC_4; + pstcKeyscanInit->u32KeyClk = KEYSCAN_CLK_HCLK; + pstcKeyscanInit->u32KeyOut = KEYSCAN_OUT_0T1; + pstcKeyscanInit->u32KeyIn = KEYSCAN_IN_0; + } + return enRet; +} + +/** + * @brief KEYSCAN initialize. + * @param [in] pstcKeyscanInit KEYSCAN config structure. + * @arg u32HizCycle Hiz state keep cycles during low level output. + * @arg u32LowCycle Low level output cycles. + * @arg u32KeyClk Scan clock. + * @arg u32KeyOut KEYOUT selection. + * @arg u32KeyIn KEYIN(EIRQ) selection. + * @retval Ok: KEYSCAN function initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t KEYSCAN_Init(const stc_keyscan_init_t *pstcKeyscanInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcKeyscanInit) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_KEYSCAN_HIZ_CLC(pstcKeyscanInit->u32HizCycle)); + DDL_ASSERT(IS_KEYSCAN_LOW_CLC(pstcKeyscanInit->u32LowCycle)); + DDL_ASSERT(IS_KEYSCAN_CLK(pstcKeyscanInit->u32KeyClk)); + DDL_ASSERT(IS_KEYSCAN_OUT(pstcKeyscanInit->u32KeyOut)); + DDL_ASSERT(IS_KEYSCAN_IN(pstcKeyscanInit->u32KeyIn)); + + WRITE_REG32(M4_KEYSCAN->SCR, \ + (pstcKeyscanInit->u32HizCycle | pstcKeyscanInit->u32LowCycle | \ + pstcKeyscanInit->u32KeyClk | pstcKeyscanInit->u32KeyOut | \ + pstcKeyscanInit->u32KeyIn )); + } + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_KEYSCAN_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_mau.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_mau.c new file mode 100644 index 0000000000000000000000000000000000000000..6753a970640b6db5e4a0c593c8335ddb606d8c51 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_mau.c @@ -0,0 +1,283 @@ +/** + ******************************************************************************* + * @file hc32f4a0_mau.c + * @brief This file provides firmware functions to manage the MAU. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hexiao First version + 2020-07-15 Hexiao Modify MAU_SqrtStartCmd to MAU_SqrtStart + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_mau.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_MAU MAU + * @brief MAU Driver Library + * @{ + */ + +#if (DDL_MAU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MAU_Local_Macros MAU Local Macros + * @{ + */ + +/** + * @defgroup MAU_Check_Parameters_Validity MAU Check Parameters Validity + * @{ + */ +#define IS_VALID_UNIT(x) ((x) == M4_MAU) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup MAU_Global_Functions MAU Global Functions + * @{ + */ + +/** + * @brief Sqrt result left shift config + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @param [in] u8LShBitsNumber number of left shift bits + * max value is MAU_SQRT_OUTPUT_LSHIFT_MAX + * @retval None + */ +void MAU_SqrtResultLShiftCfg(M4_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(u8LShBitsNumber <= MAU_SQRT_OUTPUT_LSHIFT_MAX); + + MODIFY_REG32(MAUx->CSR, MAU_CSR_SHIFT, ((uint32_t)u8LShBitsNumber << MAU_CSR_SHIFT_POS)); +} + +/** + * @brief Sqrt interrupt function command + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @param [in] enNewState New state of the MAUx sqrt interrupt function, + * @ref en_functional_state_t + * @retval None + */ +void MAU_SqrtIntCmd(M4_MAU_TypeDef *MAUx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(MAUx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(MAUx->CSR, MAU_CSR_INTEN, (uint32_t)enNewState << MAU_CSR_INTEN_POS); +} + +/** + * @brief Input radicand for sqrt + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @param [in] u32Radicand data to be square rooted + * @retval None + */ +void MAU_SqrtWriteDataReg(M4_MAU_TypeDef* MAUx, uint32_t u32Radicand) +{ + DDL_ASSERT(M4_MAU == MAUx); + + WRITE_REG32(MAUx->DTR0, u32Radicand); +} + +/** + * @brief Start sqrt calculation + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @retval None + */ +void MAU_SqrtStart(M4_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(M4_MAU == MAUx); + + SET_REG32_BIT(MAUx->CSR, MAU_CSR_START); +} + +/** + * @brief Read if sqrt calculation is ongoing or not + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @retval An en_flag_status_t enumeration value: + * - Set: calculation is ongoing + * - Reset: calculation is not ongoing + */ +en_flag_status_t MAU_SqrtGetStatus(const M4_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(M4_MAU == MAUx); + + return (0UL != READ_REG32_BIT(MAUx->CSR, MAU_CSR_BUSY)) ? Set : Reset; +} + +/** + * @brief Read result of sqrt + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @retval Result of sqrt,range is [0,0x10000] + */ +uint32_t MAU_SqrtReadDataReg(const M4_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(M4_MAU == MAUx); + + return READ_REG32(MAUx->RTR0); +} + +/** + * @brief Initialize the specified DAC peripheral according to the specified parameters. + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @param [in] u8LShBitsNumber Sqrt result left shift bits number + * max value is @ref MAU_SQRT_OUTPUT_LSHIFT_MAX + * @param [in] enIntNewState Enable or Disable sqrt interrupt + * @ref en_functional_state_t + * @retval None + */ +void MAU_SqrtInit(M4_MAU_TypeDef *MAUx, uint8_t u8LShBitsNumber, en_functional_state_t enIntNewState) +{ + DDL_ASSERT(M4_MAU == MAUx); + DDL_ASSERT(u8LShBitsNumber <= MAU_SQRT_OUTPUT_LSHIFT_MAX); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enIntNewState)); + + MODIFY_REG32(MAUx->CSR, MAU_CSR_SHIFT | MAU_CSR_INTEN, + ((((uint32_t)u8LShBitsNumber << MAU_CSR_SHIFT_POS)) | ((uint32_t)enIntNewState << MAU_CSR_INTEN_POS))); +} + +/** + * @brief De-initialize the DAC peripheral. Reset the registers of the specified DAC unit. + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @retval None + */ +void MAU_SqrtDeInit(M4_MAU_TypeDef *MAUx) +{ + DDL_ASSERT(M4_MAU == MAUx); + + CLEAR_REG32_BIT(MAUx->CSR, MAU_CSR_SHIFT | MAU_CSR_INTEN); +} + +/** + * @brief Square root + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @param [in] u32Radicand data to be square rooted + * @param [out] pu32Result Result of sqrt,range is [0,0x10000] + * @retval An en_result_t enumeration value + * - Ok: No errors occurred + * - Error: errors occurred + */ +en_result_t MAU_Sqrt(M4_MAU_TypeDef *MAUx, uint32_t u32Radicand, uint32_t *pu32Result) +{ + DDL_ASSERT(M4_MAU == MAUx); + DDL_ASSERT(pu32Result != (void *)0UL); + + uint32_t u32TimeCount = 0UL; + en_result_t enRet = Ok; + + WRITE_REG32(MAUx->DTR0, u32Radicand); + SET_REG32_BIT(MAUx->CSR, MAU_CSR_START); + __ASM("NOP"); + __ASM("NOP"); + __ASM("NOP"); + + while((MAUx->CSR & MAU_CSR_BUSY) != 0UL) + { + if(u32TimeCount++ > MAU_SQRT_TIMEOUT) + { + enRet = Error; + break; + } + } + + if(Ok == enRet) + { + *pu32Result = READ_REG32(MAUx->RTR0); + } + + return enRet; +} + +/** + * @brief Sine + * @param [in] MAUx Pointer to MAU instance register base. + * This parameter can only be: @arg M4_MAU + * @param u16AngleIdx: Angle index,range is [0,0xFFF], calculation method for reference: + AngleIdx = (uint16_t)(Angle * 4096.0F / 360.0F + 0.5F) % 4096U + * @retval Result of Sine in Q15 format + */ +int16_t MAU_Sin(M4_MAU_TypeDef *MAUx, uint16_t u16AngleIdx) +{ + DDL_ASSERT(M4_MAU == MAUx); + DDL_ASSERT(MAU_SIN_ANGIDX_TOTAL > u16AngleIdx); + + WRITE_REG16(MAUx->DTR1, u16AngleIdx); + __ASM("NOP"); + + return (int16_t)READ_REG16(MAUx->RTR1); +} + +/** + * @} + */ + +#endif /* DDL_MAU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_mpu.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_mpu.c new file mode 100644 index 0000000000000000000000000000000000000000..6fa6849735cf48175b9fdc67fb76b731d9161787 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_mpu.c @@ -0,0 +1,1106 @@ +/** + ******************************************************************************* + * @file hc32f4a0_mpu.c + * @brief This file provides firmware functions to manage the Memory Protection + * Unit(MPU). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_mpu.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_MPU MPU + * @brief Memory Protection Unit Driver Library + * @{ + */ + +#if (DDL_MPU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup MPU_Local_Macros MPU Local Macros + * @{ + */ + +/* Number of MPU unit */ +#define MPU_UNIT_NUM (5UL) +/* Number of MPU region */ +#define MPU_REGION_NUM (16UL) + +/* MPU Register Combination Mask */ +#define MPU_UNIT_CONFIG_MASK (MPU_S1CR_SMPU1BRP | MPU_S1CR_SMPU1BWP | MPU_S1CR_SMPU1ACT) + +/* DMA units with only 8 regions */ +#define MPU_NORMAL_UNIT (MPU_UNIT_USBFS_DMA | MPU_UNIT_USBHS_DMA | MPU_UNIT_ETH_DMA) + +/* Get the specified register address of the MPU Intrusion Control */ +#define MPU_RGD(__NUM__) ((uint32_t)(&(M4_MPU->RGD0)) + ((uint32_t)(__NUM__) << 2U)) + +#define MPU_RGE(__UNIT__) ((uint32_t)(&(M4_MPU->S1RGE)) + (uint32_t)(__UNIT__)) +#define MPU_RGWP(__UNIT__) ((uint32_t)(&(M4_MPU->S1RGWP)) + (uint32_t)(__UNIT__)) +#define MPU_RGRP(__UNIT__) ((uint32_t)(&(M4_MPU->S1RGRP)) + (uint32_t)(__UNIT__)) +#define MPU_CR(__UNIT__) ((uint32_t)(&(M4_MPU->S1CR)) + (uint32_t)(__UNIT__)) + +/** + * @defgroup MPU_Check_Parameters_Validity MPU Check Parameters Validity + * @{ + */ +#define IS_MPU_UNIT(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_UNIT_ALL) == MPU_UNIT_ALL)) + +#define IS_MPU_REGION(x) \ +( ((x) == MPU_REGION_NUM0) || \ + ((x) == MPU_REGION_NUM1) || \ + ((x) == MPU_REGION_NUM2) || \ + ((x) == MPU_REGION_NUM3) || \ + ((x) == MPU_REGION_NUM4) || \ + ((x) == MPU_REGION_NUM5) || \ + ((x) == MPU_REGION_NUM6) || \ + ((x) == MPU_REGION_NUM7) || \ + ((x) == MPU_REGION_NUM8) || \ + ((x) == MPU_REGION_NUM9) || \ + ((x) == MPU_REGION_NUM10) || \ + ((x) == MPU_REGION_NUM11) || \ + ((x) == MPU_REGION_NUM12) || \ + ((x) == MPU_REGION_NUM13) || \ + ((x) == MPU_REGION_NUM14) || \ + ((x) == MPU_REGION_NUM15)) + +#define IS_MPU_UNIT_REGION(unit, region) \ +( (((unit) & MPU_NORMAL_UNIT) == 0UL) || \ + (((region) == MPU_REGION_NUM0) || \ + ((region) == MPU_REGION_NUM1) || \ + ((region) == MPU_REGION_NUM2) || \ + ((region) == MPU_REGION_NUM3) || \ + ((region) == MPU_REGION_NUM4) || \ + ((region) == MPU_REGION_NUM5) || \ + ((region) == MPU_REGION_NUM6) || \ + ((region) == MPU_REGION_NUM7))) + +#define IS_MPU_BKGRD_WR_PROTECT(x) \ +( ((x) == MPU_BKGRD_WR_PROTECT_DISABLE) || \ + ((x) == MPU_BKGRD_WR_PROTECT_ENABLE)) + +#define IS_MPU_BKGRD_RD_PROTECT(x) \ +( ((x) == MPU_BKGRD_RD_PROTECT_DISABLE) || \ + ((x) == MPU_BKGRD_RD_PROTECT_ENABLE)) + +#define IS_MPU_EXP_TYPE(x) \ +( ((x) == MPU_EXP_TYPE_NONE) || \ + ((x) == MPU_EXP_TYPE_BUS_ERR) || \ + ((x) == MPU_EXP_TYPE_NMI) || \ + ((x) == MPU_EXP_TYPE_RST)) + +#define IS_MPU_REGION_WR_PROTECT(x) \ +( ((x) == MPU_REGION_WR_PROTECT_DISABLE) || \ + ((x) == MPU_REGION_WR_PROTECT_ENABLE)) + +#define IS_MPU_REGION_RD_PROTECT(x) \ +( ((x) == MPU_REGION_RD_PROTECT_DISABLE) || \ + ((x) == MPU_REGION_RD_PROTECT_ENABLE)) + +#define IS_MPU_REGION_SIZE(x) \ +( ((x) == MPU_REGION_SIZE_32BYTE) || \ + ((x) == MPU_REGION_SIZE_64BYTE) || \ + ((x) == MPU_REGION_SIZE_128BYTE) || \ + ((x) == MPU_REGION_SIZE_256BYTE) || \ + ((x) == MPU_REGION_SIZE_512BYTE) || \ + ((x) == MPU_REGION_SIZE_1KBYTE) || \ + ((x) == MPU_REGION_SIZE_2KBYTE) || \ + ((x) == MPU_REGION_SIZE_4KBYTE) || \ + ((x) == MPU_REGION_SIZE_8KBYTE) || \ + ((x) == MPU_REGION_SIZE_16KBYTE) || \ + ((x) == MPU_REGION_SIZE_32KBYTE) || \ + ((x) == MPU_REGION_SIZE_64KBYTE) || \ + ((x) == MPU_REGION_SIZE_128KBYTE) || \ + ((x) == MPU_REGION_SIZE_256KBYTE) || \ + ((x) == MPU_REGION_SIZE_512KBYTE) || \ + ((x) == MPU_REGION_SIZE_1MBYTE) || \ + ((x) == MPU_REGION_SIZE_2MBYTE) || \ + ((x) == MPU_REGION_SIZE_4MBYTE) || \ + ((x) == MPU_REGION_SIZE_8MBYTE) || \ + ((x) == MPU_REGION_SIZE_16MBYTE) || \ + ((x) == MPU_REGION_SIZE_32MBYTE) || \ + ((x) == MPU_REGION_SIZE_64MBYTE) || \ + ((x) == MPU_REGION_SIZE_128MBYTE) || \ + ((x) == MPU_REGION_SIZE_256MBYTE) || \ + ((x) == MPU_REGION_SIZE_512MBYTE) || \ + ((x) == MPU_REGION_SIZE_1GBYTE) || \ + ((x) == MPU_REGION_SIZE_2GBYTE) || \ + ((x) == MPU_REGION_SIZE_4GBYTE)) + +#define IS_MPU_REGION_BASE_ADDER(addr, size) \ +( ((addr) & ((uint32_t)(~((uint64_t)0xFFFFFFFFUL << ((size) + 1U))))) == 0UL) + +#define IS_MPU_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_FLAG_ALL) == MPU_FLAG_ALL)) + +#define IS_MPU_IP_TYPE(x) \ +( ((x) != 0UL) && \ + (((x) | MPU_IP_ALL) == MPU_IP_ALL)) + +#define IS_MPU_IP_EXP_TYPE(x) \ +( ((x) == MPU_IP_EXP_TYPE_NONE) || \ + ((x) == MPU_IP_EXP_TYPE_BUS_ERR)) + +#define IS_MPU_UNLOCK() ((M4_MPU->WP & MPU_WP_MPUWE) == MPU_WP_MPUWE) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup MPU_Global_Functions MPU Global Functions + * @{ + */ + +/** + * @brief De-Initialize MPU. + * @param None + * @retval None + */ +void MPU_DeInit(void) +{ + uint32_t i; + __IO uint32_t *RGD; + __IO uint32_t *RGE; + __IO uint32_t *RGWP; + __IO uint32_t *RGRP; + __IO uint32_t *CR; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + + for (i = 0UL; i < MPU_REGION_NUM; i++) + { + RGD = (__IO uint32_t *)MPU_RGD(i); + WRITE_REG32(*RGD, 0UL); + } + WRITE_REG32(M4_MPU->ECLR, 0x1FUL); + WRITE_REG32(M4_MPU->IPPR, 0UL); + for (i = 0UL; i < MPU_UNIT_NUM; i++) + { + RGE = (__IO uint32_t *)MPU_RGE(i << 4); + WRITE_REG32(*RGE, 0UL); + RGWP = (__IO uint32_t *)MPU_RGWP(i << 4); + WRITE_REG32(*RGWP, 0UL); + RGRP = (__IO uint32_t *)MPU_RGRP(i << 4); + WRITE_REG32(*RGRP, 0UL); + CR = (__IO uint32_t *)MPU_CR(i << 4); + WRITE_REG32(*CR, 0UL); + } +} + +/** + * @brief Initialize MPU. + * @param [in] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t MPU_Init(const stc_mpu_init_t *pstcMpuInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcMpuInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma1.u32ExceptionType)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcDma2.u32ExceptionType)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbFSDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcUsbHSDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_EXP_TYPE(pstcMpuInit->stcEthDma.u32ExceptionType)); + DDL_ASSERT(IS_MPU_BKGRD_WR_PROTECT(pstcMpuInit->stcDma1.u32BackgroundWriteProtect)); + DDL_ASSERT(IS_MPU_BKGRD_WR_PROTECT(pstcMpuInit->stcDma2.u32BackgroundWriteProtect)); + DDL_ASSERT(IS_MPU_BKGRD_WR_PROTECT(pstcMpuInit->stcUsbFSDma.u32BackgroundWriteProtect)); + DDL_ASSERT(IS_MPU_BKGRD_WR_PROTECT(pstcMpuInit->stcUsbHSDma.u32BackgroundWriteProtect)); + DDL_ASSERT(IS_MPU_BKGRD_WR_PROTECT(pstcMpuInit->stcEthDma.u32BackgroundWriteProtect)); + DDL_ASSERT(IS_MPU_BKGRD_RD_PROTECT(pstcMpuInit->stcDma1.u32BackgroundReadProtect)); + DDL_ASSERT(IS_MPU_BKGRD_RD_PROTECT(pstcMpuInit->stcDma2.u32BackgroundReadProtect)); + DDL_ASSERT(IS_MPU_BKGRD_RD_PROTECT(pstcMpuInit->stcUsbFSDma.u32BackgroundReadProtect)); + DDL_ASSERT(IS_MPU_BKGRD_RD_PROTECT(pstcMpuInit->stcUsbHSDma.u32BackgroundReadProtect)); + DDL_ASSERT(IS_MPU_BKGRD_RD_PROTECT(pstcMpuInit->stcEthDma.u32BackgroundReadProtect)); + + MODIFY_REG32(M4_MPU->S1CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma1.u32ExceptionType | + pstcMpuInit->stcDma1.u32BackgroundWriteProtect | pstcMpuInit->stcDma1.u32BackgroundReadProtect)); + MODIFY_REG32(M4_MPU->S2CR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcDma2.u32ExceptionType | + pstcMpuInit->stcDma2.u32BackgroundWriteProtect | pstcMpuInit->stcDma2.u32BackgroundReadProtect)); + MODIFY_REG32(M4_MPU->FCR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcUsbFSDma.u32ExceptionType | + pstcMpuInit->stcUsbFSDma.u32BackgroundWriteProtect | pstcMpuInit->stcUsbFSDma.u32BackgroundReadProtect)); + MODIFY_REG32(M4_MPU->HCR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcUsbHSDma.u32ExceptionType | + pstcMpuInit->stcUsbHSDma.u32BackgroundWriteProtect | pstcMpuInit->stcUsbHSDma.u32BackgroundReadProtect)); + MODIFY_REG32(M4_MPU->ECR, MPU_UNIT_CONFIG_MASK, + (pstcMpuInit->stcEthDma.u32ExceptionType | + pstcMpuInit->stcEthDma.u32BackgroundWriteProtect | pstcMpuInit->stcEthDma.u32BackgroundReadProtect)); + } + + return enRet; +} + +/** + * @brief Fills each stc_mpu_init_t member with default value. + * @param [out] pstcMpuInit Pointer to a @ref stc_mpu_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: stc_mpu_init_t member initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t MPU_StructInit(stc_mpu_init_t *pstcMpuInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcMpuInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcMpuInit->stcDma1.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma2.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcUsbFSDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcUsbHSDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcEthDma.u32ExceptionType = MPU_EXP_TYPE_NONE; + pstcMpuInit->stcDma1.u32BackgroundWriteProtect = MPU_BKGRD_WR_PROTECT_DISABLE; + pstcMpuInit->stcDma2.u32BackgroundWriteProtect = MPU_BKGRD_WR_PROTECT_DISABLE; + pstcMpuInit->stcUsbFSDma.u32BackgroundWriteProtect = MPU_BKGRD_WR_PROTECT_DISABLE; + pstcMpuInit->stcUsbHSDma.u32BackgroundWriteProtect = MPU_BKGRD_WR_PROTECT_DISABLE; + pstcMpuInit->stcEthDma.u32BackgroundWriteProtect = MPU_BKGRD_WR_PROTECT_DISABLE; + pstcMpuInit->stcDma1.u32BackgroundReadProtect = MPU_BKGRD_RD_PROTECT_DISABLE; + pstcMpuInit->stcDma2.u32BackgroundReadProtect = MPU_BKGRD_RD_PROTECT_DISABLE; + pstcMpuInit->stcUsbFSDma.u32BackgroundReadProtect = MPU_BKGRD_RD_PROTECT_DISABLE; + pstcMpuInit->stcUsbHSDma.u32BackgroundReadProtect = MPU_BKGRD_RD_PROTECT_DISABLE; + pstcMpuInit->stcEthDma.u32BackgroundReadProtect = MPU_BKGRD_RD_PROTECT_DISABLE; + } + + return enRet; +} + +/** + * @brief Set the exception type of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] u32ExceptionType Exception type of MPU unit. + * This parameter can be one of the following values: + * @arg MPU_EXP_TYPE_NONE: The host unit access protection regions will be ignored + * @arg MPU_EXP_TYPE_BUS_ERR: The host unit access protection regions will be ignored and a bus error will be triggered + * @arg MPU_EXP_TYPE_NMI: The host unit access protection regions will be ignored and a NMI interrupt will be triggered + * @arg MPU_EXP_TYPE_RST: The host unit access protection regions will trigger the reset + * @retval None + */ +void MPU_SetExceptionType(uint32_t u32Unit, uint32_t u32ExceptionType) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_EXP_TYPE(u32ExceptionType)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + CR = (__IO uint32_t *)MPU_CR(u32UnitPos); + MODIFY_REG32(*CR, MPU_S1CR_SMPU1ACT, u32ExceptionType); + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Enable or disable the write protection of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_BackgroundWriteProtectCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + CR = (__IO uint32_t *)MPU_CR(u32UnitPos); + if (Disable != enNewState) + { + SET_REG32_BIT(*CR, MPU_S1CR_SMPU1BWP); + } + else + { + CLEAR_REG32_BIT(*CR, MPU_S1CR_SMPU1BWP); + } + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Enable or disable the read protection of the unit for background space. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_BackgroundReadProtectCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + CR = (__IO uint32_t *)MPU_CR(u32UnitPos); + if (Disable != enNewState) + { + SET_REG32_BIT(*CR, MPU_S1CR_SMPU1BRP); + } + else + { + CLEAR_REG32_BIT(*CR, MPU_S1CR_SMPU1BRP); + } + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Enable or disable the access control of the unit. + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_UnitCmd(uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *CR; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + CR = (__IO uint32_t *)MPU_CR(u32UnitPos); + if (Disable != enNewState) + { + SET_REG32_BIT(*CR, MPU_S1CR_SMPU1E); + } + else + { + CLEAR_REG32_BIT(*CR, MPU_S1CR_SMPU1E); + } + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Gets the status of MPU flag. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg MPU_FLAG_SMPU1EAF: System DMA_1 error flag + * @arg MPU_FLAG_SMPU2EAF: System DMA_2 error flag + * @arg MPU_FLAG_FMPUEAF: USBFS_DMA error flag + * @arg MPU_FLAG_HMPUEAF: USBHS_DMA error flag + * @arg MPU_FLAG_EMPUEAF: ETH_DMA error flag + * @arg MPU_FLAG_ALL: All of the above + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t MPU_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_MPU->SR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Clear the flag of MPU. + * @param [in] u32Flag The type of MPU flag. + * This parameter can be one or any combination of the following values: + * @arg MPU_FLAG_SMPU1EAF: System DMA_1 error flag + * @arg MPU_FLAG_SMPU2EAF: System DMA_2 error flag + * @arg MPU_FLAG_FMPUEAF: USBFS_DMA error flag + * @arg MPU_FLAG_HMPUEAF: USBHS_DMA error flag + * @arg MPU_FLAG_EMPUEAF: ETH_DMA error flag + * @arg MPU_FLAG_ALL: All of the above + * @retval None + */ +void MPU_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_FLAG(u32Flag)); + + SET_REG32_BIT(M4_MPU->ECLR, u32Flag); +} + +/** + * @brief Initialize the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @note The effective bits of the 'u32BaseAddr' are related to the 'u32Size' of the region, + * and the low 'u32Size+1' bits are fixed at 0. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t MPU_RegionInit(uint32_t u32Num, const stc_mpu_region_init_t *pstcRegionInit) +{ + en_result_t enRet = Ok; + __IO uint32_t *RGD; + __IO uint32_t *RGWP; + __IO uint32_t *RGRP; + uint32_t i; + uint32_t u32UnitNum = MPU_UNIT_NUM; + stc_mpu_region_permission_t RegionBuffer[MPU_UNIT_NUM]; + + if (NULL == pstcRegionInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(pstcRegionInit->u32BaseAddr, pstcRegionInit->u32Size)); + DDL_ASSERT(IS_MPU_REGION_WR_PROTECT(pstcRegionInit->stcDma1.u32WriteProtect)); + DDL_ASSERT(IS_MPU_REGION_WR_PROTECT(pstcRegionInit->stcDma2.u32WriteProtect)); + DDL_ASSERT(IS_MPU_REGION_WR_PROTECT(pstcRegionInit->stcUsbFSDma.u32WriteProtect)); + DDL_ASSERT(IS_MPU_REGION_WR_PROTECT(pstcRegionInit->stcUsbHSDma.u32WriteProtect)); + DDL_ASSERT(IS_MPU_REGION_WR_PROTECT(pstcRegionInit->stcEthDma.u32WriteProtect)); + DDL_ASSERT(IS_MPU_REGION_RD_PROTECT(pstcRegionInit->stcDma1.u32ReadProtect)); + DDL_ASSERT(IS_MPU_REGION_RD_PROTECT(pstcRegionInit->stcDma2.u32ReadProtect)); + DDL_ASSERT(IS_MPU_REGION_RD_PROTECT(pstcRegionInit->stcUsbFSDma.u32ReadProtect)); + DDL_ASSERT(IS_MPU_REGION_RD_PROTECT(pstcRegionInit->stcUsbHSDma.u32ReadProtect)); + DDL_ASSERT(IS_MPU_REGION_RD_PROTECT(pstcRegionInit->stcEthDma.u32ReadProtect)); + + RGD = (__IO uint32_t *)MPU_RGD(u32Num); + WRITE_REG32(*RGD, (pstcRegionInit->u32Size | pstcRegionInit->u32BaseAddr)); + /* Configure the read/write permission for the region */ + RegionBuffer[0] = pstcRegionInit->stcDma1; + RegionBuffer[1] = pstcRegionInit->stcDma2; + RegionBuffer[2] = pstcRegionInit->stcUsbFSDma; + RegionBuffer[3] = pstcRegionInit->stcUsbHSDma; + RegionBuffer[4] = pstcRegionInit->stcEthDma; + if ((u32Num >= MPU_REGION_NUM8) && (u32Num <= MPU_REGION_NUM15)) + { + u32UnitNum = 2UL; + } + for (i = 0UL; i < u32UnitNum; i++) + { + /* Configure the write permission for the region */ + RGWP = (__IO uint32_t *)MPU_RGWP(i << 4); + if (MPU_REGION_WR_PROTECT_DISABLE != RegionBuffer[i].u32WriteProtect) + { + SET_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + else + { + CLEAR_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + /* Configure the read permission for the region */ + RGRP = (__IO uint32_t *)MPU_RGRP(i << 4); + if (MPU_REGION_WR_PROTECT_DISABLE != RegionBuffer[i].u32ReadProtect) + { + SET_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + else + { + CLEAR_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + } + } + + return enRet; +} + +/** + * @brief Fills each stc_mpu_region_init_t member with default value. + * @param [out] pstcRegionInit Pointer to a @ref stc_mpu_region_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: stc_mpu_region_init_t member initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t MPU_RegionStructInit(stc_mpu_region_init_t *pstcRegionInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRegionInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcRegionInit->u32BaseAddr = 0UL; + pstcRegionInit->u32Size = MPU_REGION_SIZE_32BYTE; + pstcRegionInit->stcDma1.u32WriteProtect = MPU_REGION_WR_PROTECT_DISABLE; + pstcRegionInit->stcDma2.u32WriteProtect = MPU_REGION_WR_PROTECT_DISABLE; + pstcRegionInit->stcUsbFSDma.u32WriteProtect = MPU_REGION_WR_PROTECT_DISABLE; + pstcRegionInit->stcUsbHSDma.u32WriteProtect = MPU_REGION_WR_PROTECT_DISABLE; + pstcRegionInit->stcEthDma.u32WriteProtect = MPU_REGION_WR_PROTECT_DISABLE; + pstcRegionInit->stcDma1.u32ReadProtect = MPU_REGION_RD_PROTECT_DISABLE; + pstcRegionInit->stcDma2.u32ReadProtect = MPU_REGION_RD_PROTECT_DISABLE; + pstcRegionInit->stcUsbFSDma.u32ReadProtect = MPU_REGION_RD_PROTECT_DISABLE; + pstcRegionInit->stcUsbHSDma.u32ReadProtect = MPU_REGION_RD_PROTECT_DISABLE; + pstcRegionInit->stcEthDma.u32ReadProtect = MPU_REGION_RD_PROTECT_DISABLE; + } + + return enRet; +} + +/** + * @brief Set the base address of the region. + * @note The effective bits of the 'u32Addr' are related to the 'size' of the region, + * and the low 'size+1' bits are fixed at 0. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Addr The base address of the region. + * @retval None + */ +void MPU_SetRegionBaseAddr(uint32_t u32Num, uint32_t u32Addr) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + + RGD = (__IO uint32_t *)MPU_RGD(u32Num); + /* Check parameters */ + DDL_ASSERT(IS_MPU_REGION_BASE_ADDER(u32Addr, READ_REG32_BIT(*RGD, MPU_RGD_MPURGSIZE))); + + MODIFY_REG32(*RGD, MPU_RGD_MPURGADDR, u32Addr); +} + +/** + * @brief Set the size of the region. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Size The size of the region. + * This parameter can be one of the following values: + * @arg MPU_REGION_SIZE_32BYTE: 32 Byte + * @arg MPU_REGION_SIZE_64BYTE: 64 Byte + * @arg MPU_REGION_SIZE_128BYTE: 126 Byte + * @arg MPU_REGION_SIZE_256BYTE: 256 Byte + * @arg MPU_REGION_SIZE_512BYTE: 512 Byte + * @arg MPU_REGION_SIZE_1KBYTE: 1K Byte + * @arg MPU_REGION_SIZE_2KBYTE: 2K Byte + * @arg MPU_REGION_SIZE_4KBYTE: 4K Byte + * @arg MPU_REGION_SIZE_8KBYTE: 8K Byte + * @arg MPU_REGION_SIZE_16KBYTE: 16K Byte + * @arg MPU_REGION_SIZE_32KBYTE: 32K Byte + * @arg MPU_REGION_SIZE_64KBYTE: 64K Byte + * @arg MPU_REGION_SIZE_128KBYTE: 128K Byte + * @arg MPU_REGION_SIZE_256KBYTE: 256K Byte + * @arg MPU_REGION_SIZE_512KBYTE: 512K Byte + * @arg MPU_REGION_SIZE_1MBYTE: 1M Byte + * @arg MPU_REGION_SIZE_2MBYTE: 2M Byte + * @arg MPU_REGION_SIZE_4MBYTE: 4M Byte + * @arg MPU_REGION_SIZE_8MBYTE: 8M Byte + * @arg MPU_REGION_SIZE_16MBYTE: 16M Byte + * @arg MPU_REGION_SIZE_32MBYTE: 32M Byte + * @arg MPU_REGION_SIZE_64MBYTE: 64M Byte + * @arg MPU_REGION_SIZE_128MBYTE: 128M Byte + * @arg MPU_REGION_SIZE_256MBYTE: 256M Byte + * @arg MPU_REGION_SIZE_512MBYTE: 512M Byte + * @arg MPU_REGION_SIZE_1GBYTE: 1G Byte + * @arg MPU_REGION_SIZE_2GBYTE: 2G Byte + * @arg MPU_REGION_SIZE_4GBYTE: 4G Byte + * @retval None + */ +void MPU_SetRegionSize(uint32_t u32Num, uint32_t u32Size) +{ + __IO uint32_t *RGD; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_REGION_SIZE(u32Size)); + + RGD = (__IO uint32_t *)MPU_RGD(u32Num); + MODIFY_REG32(*RGD, MPU_RGD_MPURGSIZE, u32Size); +} + +/** + * @brief Enable or disable the write protection of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_RegionWriteProtectCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGWP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + /* Configure the write permission for the region */ + RGWP = (__IO uint32_t *)MPU_RGWP(u32UnitPos); + if (Disable != enNewState) + { + SET_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + else + { + CLEAR_REG32_BIT(*RGWP, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Enable or disable the read protection of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_RegionReadProtectCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGRP; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + /* Configure the read permission for the region */ + RGRP = (__IO uint32_t *)MPU_RGRP(u32UnitPos); + if (Disable != enNewState) + { + SET_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + else + { + CLEAR_REG32_BIT(*RGRP, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Enable or disable the access control of the unit for the region. + * @note 'MPU_REGION_NUM8' to 'MPU_REGION_NUM15' are only valid when the MPU unit is 'MPU_UNIT_DMA1' or 'MPU_UNIT_DMA2'. + * @param [in] u32Num The number of the regsion. + * This parameter can be one of the following values: + * @arg MPU_REGION_NUM0: MPU region number 0 + * @arg MPU_REGION_NUM1: MPU region number 1 + * @arg MPU_REGION_NUM2: MPU region number 2 + * @arg MPU_REGION_NUM3: MPU region number 3 + * @arg MPU_REGION_NUM4: MPU region number 4 + * @arg MPU_REGION_NUM5: MPU region number 5 + * @arg MPU_REGION_NUM6: MPU region number 6 + * @arg MPU_REGION_NUM7: MPU region number 7 + * @arg MPU_REGION_NUM8: MPU region number 8 + * @arg MPU_REGION_NUM9: MPU region number 9 + * @arg MPU_REGION_NUM10: MPU region number 10 + * @arg MPU_REGION_NUM11: MPU region number 11 + * @arg MPU_REGION_NUM12: MPU region number 12 + * @arg MPU_REGION_NUM13: MPU region number 13 + * @arg MPU_REGION_NUM14: MPU region number 14 + * @arg MPU_REGION_NUM15: MPU region number 15 + * @param [in] u32Unit The type of MPU unit. + * This parameter can be one or any combination of the following values: + * @arg MPU_UNIT_DMA1: System DMA_1 MPU + * @arg MPU_UNIT_DMA2: System DMA_2 MPU + * @arg MPU_UNIT_USBFS_DMA: USBFS_DMA MPU + * @arg MPU_UNIT_USBHS_DMA: USBHS_DMA MPU + * @arg MPU_UNIT_ETH_DMA: ETH_DMA MPU + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_RegionCmd(uint32_t u32Num, uint32_t u32Unit, en_functional_state_t enNewState) +{ + __IO uint32_t *RGE; + uint32_t u32UnitPos = 0UL; + uint32_t u32Temp; + + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_REGION(u32Num)); + DDL_ASSERT(IS_MPU_UNIT(u32Unit)); + DDL_ASSERT(IS_MPU_UNIT_REGION(u32Unit, u32Num)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Temp = u32Unit; + while (0UL != u32Temp) + { + if (0UL != (u32Temp & 0x1UL)) + { + RGE = (__IO uint32_t *)MPU_RGE(u32UnitPos); + if (Disable != enNewState) + { + SET_REG32_BIT(*RGE, (0x1UL << u32Num)); + } + else + { + CLEAR_REG32_BIT(*RGE, (0x1UL << u32Num)); + } + } + u32Temp >>= 1UL; + u32UnitPos += 0x10U; + } +} + +/** + * @brief Set the type of exception to access the protected IP. + * @param [in] u32ExceptionType Exception type of MPU IP. + * This parameter can be one of the following values: + * @arg MPU_IP_EXP_TYPE_NONE: Access to the protected IP will be ignored + * @arg MPU_IP_EXP_TYPE_BUS_ERR: Access to the protected IP will trigger a bus error + * @retval None + */ +void MPU_IP_SetExceptionType(uint32_t u32ExceptionType) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_EXP_TYPE(u32ExceptionType)); + + WRITE_REG32(bM4_MPU->IPPR_b.BUSERRE, (u32ExceptionType >> MPU_IPPR_BUSERRE_POS)); +} + +/** + * @brief Enable or disable write protection for the IP. + * @param [in] u32Peripheral The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_FMC: FMC module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_DMPU: DMPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_SYSC: SYSC module + * @arg MPU_IP_MSTP: MSTP module + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_IP_WriteProtectCmd(uint32_t u32Peripheral, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Peripheral)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable != enNewState) + { + SET_REG32_BIT(M4_MPU->IPPR, (u32Peripheral << 1U)); + } + else + { + CLEAR_REG32_BIT(M4_MPU->IPPR, (u32Peripheral << 1U)); + } +} + +/** + * @brief Enable or disable read protection for the IP. + * @param [in] u32Peripheral The peripheral of the chip. + * This parameter can be one or any combination of the following values: + * @arg MPU_IP_AES: AES module + * @arg MPU_IP_HASH: HASH module + * @arg MPU_IP_TRNG: TRNG module + * @arg MPU_IP_CRC: CRC module + * @arg MPU_IP_FMC: FMC module + * @arg MPU_IP_WDT: WDT module + * @arg MPU_IP_SWDT: SWDT module + * @arg MPU_IP_BKSRAM: BKSRAM module + * @arg MPU_IP_RTC: RTC module + * @arg MPU_IP_DMPU: DMPU module + * @arg MPU_IP_SRAMC: SRAMC module + * @arg MPU_IP_INTC: INTC module + * @arg MPU_IP_SYSC: SYSC module + * @arg MPU_IP_MSTP: MSTP module + * @arg MPU_IP_ALL: All of the above + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void MPU_IP_ReadProtectCmd(uint32_t u32Peripheral, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_MPU_UNLOCK()); + DDL_ASSERT(IS_MPU_IP_TYPE(u32Peripheral)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Disable != enNewState) + { + SET_REG32_BIT(M4_MPU->IPPR, u32Peripheral); + } + else + { + CLEAR_REG32_BIT(M4_MPU->IPPR, u32Peripheral); + } +} + +/** + * @} + */ + +#endif /* DDL_MPU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_nfc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_nfc.c new file mode 100644 index 0000000000000000000000000000000000000000..1047f7e99d34da33e4cdf502b4f6f89851a1d635 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_nfc.c @@ -0,0 +1,1978 @@ +/** + ******************************************************************************* + * @file hc32f4a0_nfc.c + * @brief This file provides firmware functions to manage the EXMC NFC + * (External Memory Controller: NAND Flash Controller) driver library. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-14 Hongjh 1. Merge API from EXMC_NFC_Enable/Disable to EXMC_NFC_Cmd + 2. Merge API from EXMC_NFC_Enable/DisableEcc + to EXMC_NFC_EccCmd + 3. Merge API from EXMC_NFC_Enable/DisableWriteProtect + to EXMC_NFC_WriteProtectCmd + 2020-08-25 Hongjh Modify the pointer type cast + 2020-10-12 Hongjh The function EXMC_NFC_ReadId add timeout + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_nfc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_EXMC_NFC EXMC_NFC + * @brief NAND Flash Controller Driver Library + * @{ + */ + +#if (DDL_NFC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Local_Macros NAND Flash Controller Local Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Check_Parameters_Validity EXMC SMC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_NFC_BANK(x) \ +( (EXMC_NFC_BANK_0 == (x)) || \ + (EXMC_NFC_BANK_1 == (x)) || \ + (EXMC_NFC_BANK_2 == (x)) || \ + (EXMC_NFC_BANK_3 == (x)) || \ + (EXMC_NFC_BANK_4 == (x)) || \ + (EXMC_NFC_BANK_5 == (x)) || \ + (EXMC_NFC_BANK_6 == (x)) || \ + (EXMC_NFC_BANK_7 == (x))) + +#define IS_EXMC_NFC_MEM_WIDTH(x) \ +( (EXMC_NFC_MEMORY_WIDTH_8BIT == (x)) || \ + (EXMC_NFC_MEMORY_WIDTH_16BIT == (x))) + +#define IS_EXMC_NFC_BANK_CAPACITY(x) \ +( (EXMC_NFC_BANK_CAPACITY_512MBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_1GBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_2GBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_4GBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_8GBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_16GBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_32GBIT == (x)) || \ + (EXMC_NFC_BANK_CAPACITY_64GBIT == (x))) + +#define IS_EXMC_NFC_PAGE_SIZE(x) \ +( (EXMC_NFC_PAGE_SIZE_2KBYTES == (x)) || \ + (EXMC_NFC_PAGE_SIZE_4KBYTES == (x)) || \ + (EXMC_NFC_PAGE_SIZE_8KBYTES == (x))) + +#define IS_EXMC_NFC_BANK_NUM(x) \ +( (EXMC_NFC_1_BANK == (x)) || \ + (EXMC_NFC_2_BANKS == (x)) || \ + (EXMC_NFC_4_BANKS == (x)) || \ + (EXMC_NFC_8_BANKS == (x))) + +#define IS_EXMC_NFC_WR_PROTECT(x) \ +( (EXMC_NFC_WR_PROTECT_ENABLE == (x)) || \ + (EXMC_NFC_WR_PROTECT_DISABLE == (x))) + +#define IS_EXMC_NFC_ECC_MODE(x) \ +( (EXMC_NFC_ECC_1BIT == (x)) || \ + (EXMC_NFC_ECC_4BITS == (x))) + +#define IS_EXMC_NFC_ROW_ADDRESS_CYCLES(x) \ +( (EXMC_NFC_2_ROW_ADDRESS_CYCLES == (x)) || \ + (EXMC_NFC_3_ROW_ADDRESS_CYCLES == (x))) + +#define IS_EXMC_NFC_SECTION(x) ((x) <= EXMC_NFC_ECC_SECTION15) + +#define IS_EXMC_NFC_INT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~EXMC_NFC_INT_MASK)))) + + +#define IS_EXMC_NFC_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~EXMC_NFC_FLAG_MASK)))) + +#define IS_EXMC_NFC_COLUMN(x) ((x) <= NFC_COLUMN_MAX) + +#define IS_EXMC_NFC_PAGE(page, capacity_index) ((page) <= NFC_PAGE_MAX((capacity_index))) + +#define IS_EXMC_NFC_TIMING_TS(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWP(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRP(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TH(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWH(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRH(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRR(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWB(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TCCS(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TWTR(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TRTW(x) ((x) <= 0xFFUL) + +#define IS_EXMC_NFC_TIMING_TADL(x) ((x) <= 0xFFUL) +/** + * @} + */ + +/** + * @defgroup NFC flag mask + * @{ + */ +#define EXMC_NFC_INT_MASK \ +( EXMC_NFC_INT_RB_BANK0 | \ + EXMC_NFC_INT_RB_BANK1 | \ + EXMC_NFC_INT_RB_BANK2 | \ + EXMC_NFC_INT_RB_BANK3 | \ + EXMC_NFC_INT_RB_BANK4 | \ + EXMC_NFC_INT_RB_BANK5 | \ + EXMC_NFC_INT_RB_BANK6 | \ + EXMC_NFC_INT_RB_BANK7 | \ + EXMC_NFC_INT_ECC_ERROR | \ + EXMC_NFC_INT_ECC_CALC_COMPLETION | \ + EXMC_NFC_INT_ECC_CORRECTABLE_ERROR | \ + EXMC_NFC_INT_ECC_UNCORRECTABLE_ERROR) +/** + * @} + */ + +/** + * @defgroup NFC flag mask + * @{ + */ +#define EXMC_NFC_FLAG_MASK \ +( EXMC_NFC_FLAG_RB_BANK0 | \ + EXMC_NFC_FLAG_RB_BANK1 | \ + EXMC_NFC_FLAG_RB_BANK2 | \ + EXMC_NFC_FLAG_RB_BANK3 | \ + EXMC_NFC_FLAG_RB_BANK4 | \ + EXMC_NFC_FLAG_RB_BANK5 | \ + EXMC_NFC_FLAG_RB_BANK6 | \ + EXMC_NFC_FLAG_RB_BANK7 | \ + EXMC_NFC_FLAG_ECC_ERROR | \ + EXMC_NFC_FLAG_ECC_CALCULATING | \ + EXMC_NFC_FLAG_ECC_CALC_COMPLETION | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR) +/** + * @} + */ + +/** + * @defgroup NFC_Memory_Capacity_Index NFC Memory Capacity Index + * @{ + */ +#define NFC_CAPACITY_INDEX_512MBIT (0UL) +#define NFC_CAPACITY_INDEX_1GBIT (1UL) +#define NFC_CAPACITY_INDEX_2GBIT (2UL) +#define NFC_CAPACITY_INDEX_4GBIT (3UL) +#define NFC_CAPACITY_INDEX_8GBIT (4UL) +#define NFC_CAPACITY_INDEX_16GBIT (5UL) +#define NFC_CAPACITY_INDEX_32GBIT (6UL) +#define NFC_CAPACITY_INDEX_64GBIT (7UL) +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Command_Regster_Value EXMC NFC Command Regster Value + * @{ + */ +/*!< Command value */ +#define NFC_CMD_VALUE(arg, bank, cmd) ((arg) | ((bank) << 8UL) | (cmd)) + +/*!< Command: Read status */ +#define NFC_ADDR_VALUE(bank, addr) (0x40000000UL | ((bank) << 8UL) | (addr)) + +/*!< Command: Read status */ +#define CMD_RESET(bank) (NFC_CMD_VALUE(0UL, (bank), EXMC_NFC_CMD_RESET)) + +/*!< Command: Read status */ +#define CMD_ASYNC_RESET(bank) (NFC_CMD_VALUE(0x82000000UL, (bank), EXMC_NFC_CMD_ASYNCHRONOUS_RESSET)) + +/*!< Command: Read status */ +#define CMD_RESET_LUN(bank) (NFC_CMD_VALUE(0x82000000UL, (bank), EXMC_NFC_CMD_RESET_LUN)) + +/*!< Command: Read status */ +#define CMD_READ_STATUS(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_READ_STATUS)) + +/*!< Command: Read status */ +#define CMD_READ_STATUS_ENHANCED(bank) (NFC_CMD_VALUE(0x80000000UL, (bank), EXMC_NFC_CMD_READ_STATUS_ENHANCED)) + +/*!< Command: Read ID */ +#define CMD_READ_ID(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_READ_ID)) +#define CMD_READ_ID_ADDR(bank, addr) (NFC_ADDR_VALUE((bank), (addr))) + +/*!< Command: Read unique ID */ +#define CMD_READ_UNIQUEID(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_READ_UNIQUE_ID)) +#define CMD_READ_UNIQUEID_ADDR(bank) (NFC_ADDR_VALUE((bank), 0UL)) + +/*!< Command: Erase block */ +#define CMD_ERASE_BLOCK_1ST_CYCLE(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_BLK_ERASE_1ST)) +#define CMD_ERASE_BLOCK_2ND_CYCLE(bank) (NFC_CMD_VALUE(0x81000000UL, (bank), EXMC_NFC_CMD_BLK_ERASE_2ND)) + +/*!< Command: Read parameter page */ +#define CMD_READ_PARAMETER_PAGE(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_READ_PARAMETER_PAGE)) +#define CMD_READ_PARAMETER_PAGE_ADDR(bank) (NFC_ADDR_VALUE((bank), 0UL)) + +/*!< Command: Set feature */ +#define CMD_SET_FEATURE(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_SET_FEATURES)) +#define CMD_SET_FEATURE_ADDR(bank, addr) (NFC_ADDR_VALUE((bank), (addr))) + +/*!< Command: Get feature */ +#define CMD_GET_FEATURE(bank) (NFC_CMD_VALUE(0x83000000UL, (bank), EXMC_NFC_CMD_GET_FEATURES)) +#define CMD_GET_FEATURE_ADDR(bank, addr) (NFC_ADDR_VALUE((bank), (addr))) + +/*!< Command: Address cycle */ +#define CMD_ADDR_1ST_CYCLE(bank, ras) (NFC_ADDR_VALUE((bank), ((ras) & 0xFFUL))) +#define CMD_ADDR_2ND_CYCLE(bank, ras) (NFC_ADDR_VALUE((bank), (((ras) & 0xFF00UL) >> 8UL))) +#define CMD_ADDR_3RD_CYCLE(bank, ras) (NFC_ADDR_VALUE((bank), (((ras) & 0xFF0000UL) >> 16UL))) + +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_IDXR_Bit_Position EXMC NFC IDXR Bit Position + * @{ + */ +#define EXMC_NFC_IDXR_COL_POS (0UL) +#define EXMC_NFC_IDXR_2KPAGE_POS (12UL) +#define EXMC_NFC_IDXR_512MBIT_BANK_POS (27UL) +/** + * @} + */ + +/*!< NFC BACR regsiter: page field value */ +#define NFC_BACR_PAGE_VAL ((READ_REG32_BIT(M4_NFC->BACR, NFC_BACR_PAGE) >> NFC_BACR_PAGE_POS)) + +/*!< NFC Page Size */ +#define NFC_PAGE_SIZE (1024UL << (NFC_BACR_PAGE_VAL & 0x3UL)) + +/*!< NFC Spare Size for user data */ +#define NFC_SPARE_SIZE_FOR_USER_DATA ((READ_REG32_BIT(M4_NFC->BACR, NFC_BACR_SCS) >> NFC_BACR_SCS_POS) << 2UL) + +/*!< IDX register mask for 64bit */ +#define NFC_IDXR_MASK (0x1FFFFFFFFFULL) + +/*!< NFC_ISTR register RBST bit mask */ +#define NFC_FLAG_RB_BANKx_MASK(bank) (EXMC_NFC_FLAG_RB_BANK0 << (EXMC_NFC_BANK_7 & (bank))) + +/*!< IDX register mask for 64bit */ +#define NFC_NFC_ISTR_MASK (0xFF53UL) + +/*!< NFC_DATR for 32bit */ +#define NFC_DATR_REG32(x) (M4_NFC->DATR_BASE) + +/*!< NFC_ID_DATR for 32bit */ +#define NFC_ID_REG32(x) (*((__IO uint32_t *)((uint32_t)(&(M4_NFC->DATR_BASE)) + 0x8010UL + ((x) << 2UL)))) + +/*!< NFC_SYND_REG for 32bit */ +#define NFC_SYND_REG32(sect, reg) (*((__IO uint32_t *)((uint32_t)(&(M4_NFC->ECC_SYND0_0)) + (((uint32_t)(sect)) << 4UL) + (((uint32_t)(reg)) << 2UL)))) + +/*!< NFC_ECCR_REG for 32bit */ +#define NFC_ECCR_REG32(sect) (*((__IO uint32_t *)((uint32_t)(&(M4_NFC->ECCR0)) + (((uint32_t)(sect)) << 2UL)))) + +/*!< NFC_SYND_MAX_Length (Unit: half-word ) */ +#define NFC_SYND_MAX_LEN (8U) + +/** + * @defgroup Parameter_Align Parameter Align + * @{ + */ +#define IS_PARAM_ALIGN_WORD(x) (IS_ADDRESS_ALIGN_WORD((x))) +/** + * @} + */ + +/*!< NFC column max */ +#define NFC_COLUMN_MAX ((1UL << (12UL + ((0x03UL & NFC_BACR_PAGE_VAL) - 1UL))) - 1UL) + +/*!< NFC page max for the specified capacity */ +#define NFC_PAGE_MAX(capacity_index) ((1UL << (14UL + capacity_index - ((0x03UL & NFC_BACR_PAGE_VAL) - 1UL))) - 1UL) + +/** + * @brief Calculate NFC_IDXR register(64bits) value. + * @param [in]bank The specified bank + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in]page The page address + * @param [in]col The column address + * @param [in]capacity_index The number of bank capacity bits + * @arg NFC_CAPACITY_INDEX_512MBIT: NFC device bank size:512M bits + * @arg NFC_CAPACITY_INDEX_1GBIT: NFC device bank size:1G bits + * @arg NFC_CAPACITY_INDEX_2GBIT: NFC device bank size:2G bits + * @arg NFC_CAPACITY_INDEX_4GBIT: NFC device bank size:4G bits + * @arg NFC_CAPACITY_INDEX_8GBIT: NFC device bank size:8G bits + * @arg NFC_CAPACITY_INDEX_16GBIT: NFC device bank size:16G bits + * @arg NFC_CAPACITY_INDEX_32BIT: NFC device bank size:32G bits + * @arg NFC_CAPACITY_INDEX_64BIT: NFC device bank size:64G bits + * @retval NFC Index value + */ +#define NFC_IDXR_VAL(bank, page, col, capacity_index) \ +( (((uint64_t)(col)) << EXMC_NFC_IDXR_COL_POS) | \ + (((uint64_t)(page)) << (EXMC_NFC_IDXR_2KPAGE_POS + ((0x03UL & NFC_BACR_PAGE_VAL) - 1UL))) | \ + (((uint64_t)(bank)) << (EXMC_NFC_IDXR_512MBIT_BANK_POS + (0x07UL & (capacity_index))))) +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/** + * @addtogroup EXMC_NFC_Local_Functions + * @{ + */ + +static en_result_t EXMC_NFC_Read(uint32_t u32Bank, + uint32_t u32Page, + uint32_t u32Col, + uint32_t au32Data[], + uint32_t u32NumWords, + en_functional_state_t enEccState, + uint32_t u32Timeout); +static en_result_t EXMC_NFC_Write(uint32_t u32Bank, + uint32_t u32Page, + uint32_t u32Col, + const uint32_t au32Data[], + uint32_t u32NumWords, + en_functional_state_t enEccState, + uint32_t u32Timeout); +static uint32_t EXMC_NFC_GetCapacityIndex(void); +static en_result_t EXMC_NFC_WaitFlagUntilTo(uint32_t u32Flag, + en_flag_status_t enStatus, + uint32_t u32Timeout); + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EXMC_NFC_Global_Functions NAND Flash Controller Global Functions + * @{ + */ + +/** + * @brief Initialize EXMC NFC function. + * @param [in] pstcInit Pointer to a @ref stc_exmc_nfc_init_t structure (EXMC NFC function configuration structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EXMC_NFC_Init(const stc_exmc_nfc_init_t *pstcInit) +{ + uint32_t u32RegVal; + en_result_t enRet = ErrorInvalidParameter; + + /* Check the pointer pstcInit */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_CAPACITY(pstcInit->stcBaseCfg.u32CapacitySize)); + DDL_ASSERT(IS_EXMC_NFC_MEM_WIDTH(pstcInit->stcBaseCfg.u32MemWidth)); + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(pstcInit->stcBaseCfg.u32BankNum)); + DDL_ASSERT(IS_EXMC_NFC_PAGE_SIZE(pstcInit->stcBaseCfg.u32PageSize)); + DDL_ASSERT(IS_EXMC_NFC_WR_PROTECT(pstcInit->stcBaseCfg.u32WrProtect)); + DDL_ASSERT(IS_EXMC_NFC_ECC_MODE(pstcInit->stcBaseCfg.u32EccMode)); + DDL_ASSERT(IS_EXMC_NFC_ROW_ADDRESS_CYCLES(pstcInit->stcBaseCfg.u32RowAddrCycle)); + + DDL_ASSERT(IS_EXMC_NFC_TIMING_TS(pstcInit->stcTimingReg0.u32TS)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWP(pstcInit->stcTimingReg0.u32TWP)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRP(pstcInit->stcTimingReg0.u32TRP)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TH(pstcInit->stcTimingReg0.u32TH)); + + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWH(pstcInit->stcTimingReg1.u32TWH)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRH(pstcInit->stcTimingReg1.u32TRH)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRR(pstcInit->stcTimingReg1.u32TRR)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWB(pstcInit->stcTimingReg1.u32TWB)); + + DDL_ASSERT(IS_EXMC_NFC_TIMING_TCCS(pstcInit->stcTimingReg2.u32TCCS)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TWTR(pstcInit->stcTimingReg2.u32TWTR)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TRTW(pstcInit->stcTimingReg2.u32TRTW)); + DDL_ASSERT(IS_EXMC_NFC_TIMING_TADL(pstcInit->stcTimingReg2.u32TADL)); + + /* Set NFC open-page.*/ + WRITE_REG32(M4_PERIC->NFC_SYCTLREG, pstcInit->u32OpenPage); + + /* Disable hardware ECC.*/ + WRITE_REG32(M4_NFC->IENR, 0x00000080UL); + + /* Clear flag.*/ + WRITE_REG32(M4_NFC->ISTR, 0x00000000UL); + + /* Set NFC base configure.*/ + u32RegVal = (pstcInit->stcBaseCfg.u32CapacitySize | \ + pstcInit->stcBaseCfg.u32MemWidth | \ + pstcInit->stcBaseCfg.u32BankNum | \ + pstcInit->stcBaseCfg.u32PageSize | \ + pstcInit->stcBaseCfg.u32WrProtect | \ + pstcInit->stcBaseCfg.u32EccMode | \ + pstcInit->stcBaseCfg.u32RowAddrCycle | \ + (((uint32_t)pstcInit->stcBaseCfg.u8SpareSizeForUserData) << NFC_BACR_SCS_POS)); + WRITE_REG32(M4_NFC->BACR, u32RegVal); + + /* Set NFC timing register 0.*/ + u32RegVal = ((pstcInit->stcTimingReg0.u32TS << NFC_TMCR0_TS_POS) | \ + (pstcInit->stcTimingReg0.u32TWP << NFC_TMCR0_TWP_POS) | \ + (pstcInit->stcTimingReg0.u32TRP << NFC_TMCR0_TRP_POS) | \ + (pstcInit->stcTimingReg0.u32TH << NFC_TMCR0_TH_POS)); + WRITE_REG32(M4_NFC->TMCR0, u32RegVal); + + /* Set NFC timing register 1.*/ + u32RegVal = ((pstcInit->stcTimingReg1.u32TWH << NFC_TMCR1_TWH_POS) | \ + (pstcInit->stcTimingReg1.u32TRH << NFC_TMCR1_TRH_POS) | \ + (pstcInit->stcTimingReg1.u32TRR << NFC_TMCR1_TRR_POS) | \ + (pstcInit->stcTimingReg1.u32TWB << NFC_TMCR1_TWB_POS)); + WRITE_REG32(M4_NFC->TMCR1, u32RegVal); + + /* Set NFC timing register 2.*/ + u32RegVal = ((pstcInit->stcTimingReg2.u32TCCS << NFC_TMCR2_TCCS_POS) | \ + (pstcInit->stcTimingReg2.u32TWTR << NFC_TMCR2_TWTR_POS) | \ + (pstcInit->stcTimingReg2.u32TRTW << NFC_TMCR2_TRTW_POS) | \ + (pstcInit->stcTimingReg2.u32TADL << NFC_TMCR2_TADL_POS)); + WRITE_REG32(M4_NFC->TMCR2, u32RegVal); + + /* De-select NFC bank */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_DESELECT_CHIP); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize EXMC NFC function. + * @param None + * @retval None + */ +void EXMC_NFC_DeInit(void) +{ + WRITE_REG32(M4_NFC->BACR, 0x00002187UL); + WRITE_REG32(M4_NFC->IENR, 0x00000080UL); + WRITE_REG32(M4_NFC->ISTR, 0x00000000UL); + WRITE_REG32(M4_NFC->TMCR0, 0x03030202UL); + WRITE_REG32(M4_NFC->TMCR1, 0x28080303UL); + WRITE_REG32(M4_NFC->TMCR2, 0x03050D03UL); +} + +/** + * @brief Set the fields of structure stc_exmc_nfc_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_exmc_nfc_init_t structure (EXMC NFC function configuration structure) + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EXMC_NFC_StructInit(stc_exmc_nfc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + pstcInit->stcBaseCfg.u32CapacitySize = EXMC_NFC_BANK_CAPACITY_8GBIT; + pstcInit->stcBaseCfg.u32MemWidth = EXMC_NFC_MEMORY_WIDTH_8BIT; + pstcInit->stcBaseCfg.u32BankNum = EXMC_NFC_4_BANKS; + pstcInit->stcBaseCfg.u32PageSize = EXMC_NFC_PAGE_SIZE_2KBYTES; + pstcInit->stcBaseCfg.u32WrProtect = EXMC_NFC_WR_PROTECT_ENABLE; + pstcInit->stcBaseCfg.u32EccMode = EXMC_NFC_ECC_1BIT; + pstcInit->stcBaseCfg.u32RowAddrCycle = EXMC_NFC_3_ROW_ADDRESS_CYCLES; + pstcInit->stcBaseCfg.u8SpareSizeForUserData = 0U; + + pstcInit->stcTimingReg0.u32TS = 0x02UL; + pstcInit->stcTimingReg0.u32TWP = 0x02UL; + pstcInit->stcTimingReg0.u32TRP = 0x03UL; + pstcInit->stcTimingReg0.u32TH = 0x03UL; + + pstcInit->stcTimingReg1.u32TWH = 0x03UL; + pstcInit->stcTimingReg1.u32TRH = 0x03UL; + pstcInit->stcTimingReg1.u32TRR = 0x02UL; + pstcInit->stcTimingReg1.u32TWB = 0x28UL; + + pstcInit->stcTimingReg2.u32TCCS = 0x03UL; + pstcInit->stcTimingReg2.u32TWTR = 0x0DUL; + pstcInit->stcTimingReg2.u32TRTW = 0x05UL; + pstcInit->stcTimingReg2.u32TADL = 0x03UL; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable/disable NFC. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void EXMC_NFC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.NFCEN, enNewState); +} + +/** + * @brief Enable/disable NFC ECC function. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void EXMC_NFC_EccCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + CLEAR_REG32_BIT(M4_NFC->IENR, NFC_IENR_ECCDIS); + } + else + { + SET_REG32_BIT(M4_NFC->IENR, NFC_IENR_ECCDIS); + } +} + +/** + * @brief Enable/disable NFC write protection function. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void EXMC_NFC_WriteProtectCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + CLEAR_REG32_BIT(M4_NFC->BACR, NFC_BACR_WP); + } + else + { + SET_REG32_BIT(M4_NFC->BACR, NFC_BACR_WP); + } +} + +/** + * @brief Enable or disable the specified NFC interrupt + * @param [in] u16IntSource The specified interrupt + * This parameter can be any composed value of the following values: + * @arg EXMC_NFC_INT_ECC_UNCORRECTABLE_ERROR: ECC uncorrectable error interrupt + * @arg EXMC_NFC_INT_ECC_CORRECTABLE_ERROR: ECC correctable error interrupt + * @arg EXMC_NFC_INT_ECC_CALC_COMPLETION: Calculating ECC completely interrupt + * @arg EXMC_NFC_INT_ECC_ERROR: ECC error interrupt + * @arg EXMC_NFC_INT_RB_BANK0: NFC bank 0 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK1: NFC bank 1 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK2: NFC bank 2 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK3: NFC bank 3 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_INT_RB_BANK5: NFC bank 5 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK6: NFC bank 6 device ready interrupt + * @arg EXMC_NFC_INT_RB_BANK7: NFC bank 7 device ready interrupt + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void EXMC_NFC_IntCmd(uint16_t u16IntSource, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_EXMC_NFC_INT(u16IntSource)); + + if (Enable == enNewState) + { + SET_REG16_BIT(M4_NFC->IENR, u16IntSource); + } + else + { + CLEAR_REG16_BIT(M4_NFC->IENR, u16IntSource); + } +} + +/** + * @brief Get the flag. + * @param [in] u32Flag The specified flag + * This parameter can be any composed value of the following values: + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR: ECC uncorrectable error + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculate ECC completely + * @arg EXMC_NFC_FLAG_ECC_ERROR: ECC error + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC bank 0 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC bank 1 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC bank 2 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC bank 3 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC bank 5 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC bank 6 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC bank 7 device ready flag + * @arg EXMC_NFC_FLAG_ECC_CALCULATING: Calculating ECC + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t EXMC_NFC_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enStatus1 = Set; + en_flag_status_t enStatus2 = Set; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + if ((u32Flag & NFC_NFC_ISTR_MASK) != 0UL) + { + if (0UL == READ_REG32_BIT(M4_NFC->ISTR, (u32Flag & NFC_NFC_ISTR_MASK))) + { + enStatus1 = Reset; + } + } + + if ((u32Flag & EXMC_NFC_FLAG_ECC_CALCULATING) != 0UL) + { + if (0UL == READ_REG32(bM4_PERIC->NFC_SYSTATREG_b.PECC)) + { + enStatus2 = Reset; + } + } + + return (((Set == enStatus1) && (Set == enStatus2)) ? Set : Reset); +} + +/** + * @brief Get the flag. + * @param [in] u32Flag The specified flag + * This parameter can be any composed value of the following values: + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR: ECC uncorrectable error + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculating ECC completely + * @arg EXMC_NFC_FLAG_ECC_ERROR: ECC error + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC bank 0 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC bank 1 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC bank 2 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC bank 3 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC bank 5 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC bank 6 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC bank 7 device ready flag + * @retval None + */ +void EXMC_NFC_ClearStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + CLEAR_REG32_BIT(M4_NFC->ISTR, u32Flag); +} + +/** + * @brief Get the interrupt result. + * @param [in] u32Flag The specified flag + * This parameter can be any composed value of the following values: + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR: ECC uncorrectable error + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculating ECC completely + * @arg EXMC_NFC_FLAG_ECC_ERROR: ECC error + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC bank 0 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC bank 1 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC bank 2 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC bank 3 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC bank 4 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC bank 5 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC bank 6 device ready flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC bank 7 device ready flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t EXMC_NFC_GetIntResultStatus(uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + return (READ_REG32_BIT(M4_NFC->IRSR, u32Flag) ? Set : Reset); +} + +/** + * @brief Get the 1BIT ECC result of the specified section. + * @param [in] u32Section The specified section + * This parameter can be one of the following values: + * @arg EXMC_NFC_ECC_SECTION0: ECC section 0 + * @arg EXMC_NFC_ECC_SECTION1: ECC section 1 + * @arg EXMC_NFC_ECC_SECTION2: ECC section 2 + * @arg EXMC_NFC_ECC_SECTION3: ECC section 3 + * @arg EXMC_NFC_ECC_SECTION4: ECC section 4 + * @arg EXMC_NFC_ECC_SECTION5: ECC section 5 + * @arg EXMC_NFC_ECC_SECTION6: ECC section 6 + * @arg EXMC_NFC_ECC_SECTION7: ECC section 7 + * @arg EXMC_NFC_ECC_SECTION8: ECC section 8 + * @arg EXMC_NFC_ECC_SECTION9: ECC section 9 + * @arg EXMC_NFC_ECC_SECTION10: ECC section 10 + * @arg EXMC_NFC_ECC_SECTION11: ECC section 11 + * @arg EXMC_NFC_ECC_SECTION12: ECC section 12 + * @arg EXMC_NFC_ECC_SECTION13: ECC section 13 + * @arg EXMC_NFC_ECC_SECTION14: ECC section 14 + * @arg EXMC_NFC_ECC_SECTION15: ECC section 15 + * @retval The register value + */ +uint32_t EXMC_NFC_GetEcc1BitResult(uint32_t u32Section) +{ + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_SECTION(u32Section)); + + return READ_REG32(NFC_ECCR_REG32(u32Section)); +} + +/** + * @brief Set NFC spare area size. + * @param [in] u8SpareSizeForUserData NFC spare area size for user data + * @retval None + */ +void EXMC_NFC_SetSpareAreaSize(uint8_t u8SpareSizeForUserData) +{ + MODIFY_REG32(M4_NFC ->BACR, NFC_BACR_SCS, ((((uint32_t)u8SpareSizeForUserData) << NFC_BACR_SCS_POS) & NFC_BACR_SCS)); +} + +/** + * @brief Set NFC ECC mode. + * @param [in] u32EccMode ECC mode + * This parameter can be one of the following values: + * @arg EXMC_NFC_ECC_1BIT: ECC 1 bit + * @arg EXMC_NFC_ECC_4BITS: ECC 4 bits + * @retval None + */ +void EXMC_NFC_SetEccMode(uint32_t u32EccMode) +{ + DDL_ASSERT(IS_EXMC_NFC_ECC_MODE(u32EccMode)); + + MODIFY_REG32(M4_NFC ->BACR, NFC_BACR_ECCM, u32EccMode); +} + +/** + * @brief Get the 4 bits ECC syndrome register value. + * @param [in] u32Section The syndrome section + * This parameter can be one of the following values: + * @arg EXMC_NFC_SYND0: ECC syndrome section 0 + * @arg EXMC_NFC_SYND1: ECC syndrome section 1 + * @arg EXMC_NFC_SYND2: ECC syndrome section 2 + * @arg EXMC_NFC_SYND3: ECC syndrome section 3 + * @arg EXMC_NFC_SYND4: ECC syndrome section 4 + * @arg EXMC_NFC_SYND5: ECC syndrome section 5 + * @arg EXMC_NFC_SYND6: ECC syndrome section 6 + * @arg EXMC_NFC_SYND7: ECC syndrome section 7 + * @arg EXMC_NFC_SYND8: ECC syndrome section 8 + * @arg EXMC_NFC_SYND9: ECC syndrome section 9 + * @arg EXMC_NFC_SYND10: ECC syndrome section 10 + * @arg EXMC_NFC_SYND11: ECC syndrome section 11 + * @arg EXMC_NFC_SYND12: ECC syndrome section 12 + * @arg EXMC_NFC_SYND13: ECC syndrome section 13 + * @arg EXMC_NFC_SYND14: ECC syndrome section 14 + * @arg EXMC_NFC_SYND15: ECC syndrome section 15 + * @param [out] au16Synd The syndrome value + * @param [in] u8Length The length to be read(unit: half-word) + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: au16Synd = NULL or u8Length is out of range + * @note u8Length value don't be greater than 8 + */ +en_result_t EXMC_NFC_GetSyndrome(uint32_t u32Section, + uint16_t au16Synd[], + uint8_t u8Length) +{ + uint8_t i; + uint32_t u32SyndVal; + uint8_t u8LoopWords; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != au16Synd) && (u8Length <= NFC_SYND_MAX_LEN)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_SECTION(u32Section)); + + u8LoopWords = (u8Length >> 1U); + + for (i = 0U; i < u8LoopWords; i++) + { + u32SyndVal = READ_REG32(NFC_SYND_REG32(u32Section, i)); + RW_MEM16(&au16Synd[i * 2U]) = (uint16_t)(u32SyndVal); + RW_MEM16(&au16Synd[i * 2U + 1U ]) = (uint16_t)(u32SyndVal >> 16UL); + } + + if ((u8Length % 2U) != 0U) + { + u32SyndVal = READ_REG32(NFC_SYND_REG32(u32Section, i)); + RW_MEM16(&au16Synd[i * 2U]) = (uint16_t)(u32SyndVal); + } + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Read NFC device status + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @retval NFC device status + */ +uint32_t EXMC_NFC_ReadStatus(uint32_t u32Bank) +{ + uint32_t u32Status; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Write 0x81000M70 to NFC_CMDR, M = bank number */ + WRITE_REG32(M4_NFC->CMDR, CMD_READ_STATUS(u32Bank)); + + u32Status = READ_REG32(M4_NFC->DATR_BASE); + + EXMC_NFC_DeselectChip(); + + return u32Status; +} + +/** + * @brief Read status enhanced + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32RowAddress The row address + * @retval NFC device status enhanced + */ +uint32_t EXMC_NFC_ReadStatusEnhanced(uint32_t u32Bank, + uint32_t u32RowAddress) +{ + uint32_t u32Status; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Erase block step: + 1. Write 0x81000M78 to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the lowest bytes of Row address + 3. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the middle bytes of Row address + 4. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the highest bytes of Row address + 5. Read Data Register */ + WRITE_REG32(M4_NFC->CMDR, CMD_READ_STATUS_ENHANCED(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_1ST_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_2ND_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_3RD_CYCLE(u32Bank, u32RowAddress)); + + u32Status = READ_REG32(M4_NFC->DATR_BASE); + + EXMC_NFC_DeselectChip(); + + return u32Status; +} + +/** + * @brief Reset NFC device + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Reset timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_Reset(uint32_t u32Bank, uint32_t u32Timeout) +{ + en_result_t enRet; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Reset step: + 1. Write 0x00000MFF to NFC_CMDR, M = bank number + 2. Wait RB signal until high level */ + WRITE_REG32(M4_NFC->CMDR, CMD_RESET(u32Bank)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + + EXMC_NFC_DeselectChip(); + + return enRet; +} + +/** + * @brief Asynchronous reset + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Reset timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_AsyncReset(uint32_t u32Bank, uint32_t u32Timeout) +{ + en_result_t enRet; + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Reset step: + 1. Write 0x00000MFC to NFC_CMDR, M = bank number + 2. Wait RB signal until high level */ + WRITE_REG32(M4_NFC->CMDR, CMD_ASYNC_RESET(u32Bank)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + EXMC_NFC_DeselectChip(); + return enRet; +} + +/** + * @brief Reset lun of NFC device + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32RowAddress The row address + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Reset timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_ResetLun(uint32_t u32Bank, + uint32_t u32RowAddress, + uint32_t u32Timeout) +{ + en_result_t enRet; + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Reset lun step: + 1. Write 0x82000MFA to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the lowest bytes of Row address + 3. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the middle bytes of Row address + 4. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the highest bytes of Row address + 5. Wait RB signal until high level */ + WRITE_REG32(M4_NFC->CMDR, CMD_RESET_LUN(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_1ST_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_2ND_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_3RD_CYCLE(u32Bank, u32RowAddress)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + return enRet; +} + +/** + * @brief Read ID + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32IdAddr The address + * @param [in] au8DevId The id buffer + * @param [in] u32NumBytes The number of bytes to read + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg Error: au8DevId == NULL. + */ +en_result_t EXMC_NFC_ReadId(uint32_t u32Bank, + uint32_t u32IdAddr, + uint8_t au8DevId[], + uint32_t u32NumBytes, + uint32_t u32Timeout) +{ + uint32_t i; + uint64_t u64Val; + const uint32_t u32LoopWords = u32NumBytes/4UL; + const uint32_t u32RemainBytes = u32NumBytes%4UL; + uint32_t u32TmpId; + uint32_t u32CapacityIndex; + en_result_t enRet = Error; + + if ((NULL != au8DevId) && (u32NumBytes > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(u32IdAddr <= 0xFFUL); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank) | \ + EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_CALC_COMPLETION | \ + EXMC_NFC_FLAG_ECC_ERROR); + + u32CapacityIndex = EXMC_NFC_GetCapacityIndex(); + u64Val = (NFC_IDXR_VAL(u32Bank, 0UL, 0UL, u32CapacityIndex) & NFC_IDXR_MASK); + + /* 1. Write 0x00000000 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_READ_1ST); + + /* 2. Write NAND Flash address to NFC_IDXR0/1 */ + WRITE_REG32(M4_NFC->IDXR0, (uint32_t)(u64Val & 0xFFFFFFFFUL)); + WRITE_REG32(M4_NFC->IDXR1, (uint32_t)(u64Val >> 32UL)); + + /* 3. Write 0x000000E0 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_READ_2ND); + + /* 4. Wait RB signal until high level */ + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + if (Ok == enRet) + { + /* Read Id step: + 1. Write 0x81000M90 to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB=ID address + 3. Read NFC_DATR + 4. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + WRITE_REG32(M4_NFC->CMDR, CMD_READ_ID(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_READ_ID_ADDR(u32Bank, u32IdAddr)); + for (i = 0UL; i < u32LoopWords; i++) + { + u32TmpId = NFC_DATR_REG32(i); + (void)memcpy (&au8DevId[i * 4UL], &u32TmpId, 4UL); + } + + if (u32RemainBytes > 0UL) + { + u32TmpId = NFC_DATR_REG32(i); + (void)memcpy (&au8DevId[i * 4UL], &u32TmpId, u32RemainBytes); + } + + enRet = Ok; + } + + EXMC_NFC_DeselectChip(); + } + + return enRet; +} + +/** + * @brief Read Unique ID + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32IdAddr The address + * @param [in] au32UniqueId The id buffer + * @param [in] u8NumWords The number of words to read + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg Error: au8DevId == NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_ReadUniqueId(uint32_t u32Bank, + uint32_t u32IdAddr, + uint32_t au32UniqueId[], + uint8_t u8NumWords, + uint32_t u32Timeout) +{ + uint8_t i; + en_result_t enRet = Error; + + if ((NULL != au32UniqueId) && (u8NumWords > 0U)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Read Id step: + 1. Write 0x81000M90 to NFC_CMDR, M = bank number + 2. Write 0x40000M00 to NFC_CMDR, M = bank number, AB=ID address + 3. Read NFC_DATR + 4. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + WRITE_REG32(M4_NFC->CMDR, CMD_READ_UNIQUEID(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_READ_UNIQUEID_ADDR(u32Bank)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + if (Ok == enRet) + { + for (i = 0U; i < u8NumWords; i++) + { + au32UniqueId[i] = NFC_DATR_REG32(i); + } + } + + EXMC_NFC_DeselectChip(); + } + + return enRet; +} + +/** + * @brief Read parameter page + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] au32Data The data buffer + * @param [in] u16NumWords The number of words to read + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg Error: au8Data == NULL. + * @arg ErrorTimeout: Read timeout + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_ReadParameterPage(uint32_t u32Bank, + uint32_t au32Data[], + uint16_t u16NumWords, + uint32_t u32Timeout) +{ + uint16_t i; + en_result_t enRet = Error; + + if ((NULL != au32Data) && (u16NumWords > 0U)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Read parameter page step: + 1. Write 0x81000MEC to NFC_CMDR, M = bank number + 2. Write 0x40000M00 to NFC_CMDR, M = bank number + 3. Read NFC_DATR + 4. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + WRITE_REG32(M4_NFC->CMDR, CMD_READ_PARAMETER_PAGE(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_READ_PARAMETER_PAGE_ADDR(u32Bank)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + if (Ok == enRet) + { + for (i = 0U; i < u16NumWords; i++) + { + au32Data[i] = NFC_DATR_REG32(i); + } + } + + EXMC_NFC_DeselectChip(); + } + + return enRet; +} + +/** + * @brief Set feature + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u8FeatrueAddr The featrue address + * @param [in] au32Data The data buffer + * @param [in] u8NumWords The number of words to set + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg Error: au8Data == NULL. + * @arg ErrorTimeout: Read timeout + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_SetFeature(uint32_t u32Bank, + uint8_t u8FeatrueAddr, + const uint32_t au32Data[], + uint8_t u8NumWords, + uint32_t u32Timeout) +{ + uint8_t i; + en_result_t enRet = Error; + + if ((NULL != au32Data) && (u8NumWords > 0U)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + WRITE_REG32(M4_NFC->CMDR, CMD_SET_FEATURE(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_SET_FEATURE_ADDR(u32Bank, u8FeatrueAddr)); + + for (i = 0U; i < u8NumWords; i++) + { + NFC_DATR_REG32(i) = au32Data[i]; + } + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + + EXMC_NFC_DeselectChip(); + } + + return enRet; +} + +/** + * @brief Get feature + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u8FeatrueAddr The featrue address + * @param [out] au32Data The data buffer + * @param [in] u8NumWords The number of words to get + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg Error: au8Data == NULL. + * @arg ErrorTimeout: Read timeout + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_GetFeature(uint32_t u32Bank, + uint8_t u8FeatrueAddr, + uint32_t au32Data[], + uint8_t u8NumWords, + uint32_t u32Timeout) +{ + uint8_t i; + en_result_t enRet = Error; + + if ((NULL != au32Data) && (u8NumWords > 0U)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + WRITE_REG32(M4_NFC->CMDR, CMD_GET_FEATURE(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_GET_FEATURE_ADDR(u32Bank, u8FeatrueAddr)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + if (Ok == enRet) + { + for (i = 0U; i < u8NumWords; i++) + { + au32Data[i] = NFC_DATR_REG32(i); + } + } + + EXMC_NFC_DeselectChip(); + } + + return enRet; +} + +/** + * @brief Erase NFC device block + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32RowAddress The row address + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Erase timeout. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_EraseBlock(uint32_t u32Bank, + uint32_t u32RowAddress, + uint32_t u32Timeout) +{ + en_result_t enRet; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + /* Erase block step: + 1. Write 0x81000M60 to NFC_CMDR, M = bank number + 2. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the lowest bytes of Row address + 3. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the middle bytes of Row address + 4. Write 0x40000MAB to NFC_CMDR, M = bank number, AB= the highest bytes of Row address + 5. Write 0x00000MD0 to NFC_CMDR, M = bank number + 6. Wait RB signal until high level */ + WRITE_REG32(M4_NFC->CMDR, CMD_ERASE_BLOCK_1ST_CYCLE(u32Bank)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_1ST_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_2ND_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ADDR_3RD_CYCLE(u32Bank, u32RowAddress)); + WRITE_REG32(M4_NFC->CMDR, CMD_ERASE_BLOCK_2ND_CYCLE(u32Bank)); + + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + return enRet; +} + +/** + * @brief NFC page read + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [out] pu8Data The buffer for reading + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Write timeout. + * @arg ErrorInvalidParameter: The pointer au8Buf value is NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_ReadPageMeta(uint32_t u32Bank, + uint32_t u32Page, + uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDRESS_ALIGN_WORD(pu8Data)); + + enRet = EXMC_NFC_Read(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes/4UL), Disable, u32Timeout); + } + + return enRet; +} + +/** + * @brief NFC page write + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] pu8Data The buffer for writing + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Write timeout. + * @arg ErrorInvalidParameter: The pointer au8Buf value is NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_WritePageMeta(uint32_t u32Bank, + uint32_t u32Page, + const uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDRESS_ALIGN_WORD(pu8Data)); + + enRet = EXMC_NFC_Write(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes/4UL), Disable, u32Timeout); + } + + return enRet; +} + +/** + * @brief NFC page read by hardware ECC + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [out] pu8Data The buffer for reading + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Write timeout. + * @arg ErrorInvalidParameter: The pointer au8Buf value is NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_ReadPageHwEcc(uint32_t u32Bank, + uint32_t u32Page, + uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout) +{ + const uint32_t u32PageSize = NFC_PAGE_SIZE; + const uint32_t u32SpareSizeUserData = NFC_SPARE_SIZE_FOR_USER_DATA; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDRESS_ALIGN_WORD(pu8Data)); + DDL_ASSERT(u32NumBytes <= (u32PageSize + u32SpareSizeUserData)); + + enRet = EXMC_NFC_Read(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes/4UL), Enable, u32Timeout); + } + + return enRet; +} + +/** + * @brief NFC page write by hardware ECC + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] pu8Data The buffer for writing + * @param [in] u32NumBytes The buffer size for bytes + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Write timeout. + * @arg ErrorInvalidParameter: The pointer au8Buf value is NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +en_result_t EXMC_NFC_WritePageHwEcc(uint32_t u32Bank, + uint32_t u32Page, + const uint8_t *pu8Data, + uint32_t u32NumBytes, + uint32_t u32Timeout) +{ + const uint32_t u32PageSize = NFC_PAGE_SIZE; + const uint32_t u32SpareSizeUserData = NFC_SPARE_SIZE_FOR_USER_DATA; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu8Data) && (u32NumBytes > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(IS_PARAM_ALIGN_WORD(u32NumBytes)); + DDL_ASSERT(IS_ADDRESS_ALIGN_WORD((uint32_t)pu8Data)); + DDL_ASSERT(u32NumBytes <= (u32PageSize + u32SpareSizeUserData)); + + enRet = EXMC_NFC_Write(u32Bank, u32Page, 0UL, (uint32_t *)((uint32_t)pu8Data), \ + (u32NumBytes/4UL), Enable, u32Timeout); + } + + return enRet; +} + +/** + * @} + */ + +/** + * @defgroup EXMC_NFC_Local_Functions NAND Flash Controller Local Functions + * @{ + */ + +/** + * @brief NFC read operation + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] u32Col The column address + * @param [out] au32Data The buffer for reading + * @param [in] u32NumWords The buffer size for words + * @param [in] enEccState Disable/enable ECC function + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Write timeout. + * @arg ErrorInvalidParameter: The pointer au8Buf value is NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +static en_result_t EXMC_NFC_Read(uint32_t u32Bank, + uint32_t u32Page, + uint32_t u32Col, + uint32_t au32Data[], + uint32_t u32NumWords, + en_functional_state_t enEccState, + uint32_t u32Timeout) +{ + uint32_t i; + uint64_t u64Val; + en_result_t enRet = ErrorInvalidParameter; + const uint32_t u32CapacityIndex = EXMC_NFC_GetCapacityIndex(); + + if ((NULL != au32Data) && (u32NumWords > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(IS_EXMC_NFC_PAGE(u32Page, u32CapacityIndex)); + DDL_ASSERT(IS_EXMC_NFC_COLUMN(u32Col)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enEccState)); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank) | \ + EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_CALC_COMPLETION | \ + EXMC_NFC_FLAG_ECC_ERROR); + + if (Enable == enEccState) + { + EXMC_NFC_EccCmd(Enable); + } + else + { + EXMC_NFC_EccCmd(Disable); + } + + u64Val = (NFC_IDXR_VAL(u32Bank, u32Page, u32Col, u32CapacityIndex) & NFC_IDXR_MASK); + + /* Read page step: + 1. Write 0x00000000 to NFC_CMDR + 2. Write NAND Flash address to NFC_IDXR0/1 + 3. Write 0x000000E0 to NFC_CMDR + 4. Wait RB signal until high level + 5. Read NFC_DATR + 6. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + + /* 1. Write 0x00000000 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_READ_1ST); + + /* 2. Write NAND Flash address to NFC_IDXR0/1 */ + WRITE_REG32(M4_NFC->IDXR0, (uint32_t)(u64Val & 0xFFFFFFFFUL)); + WRITE_REG32(M4_NFC->IDXR1, (uint32_t)(u64Val >> 32UL)); + + /* 3. Write 0x000000E0 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_READ_2ND); + + /* 4. Wait RB signal until high level */ + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + if (Ok == enRet) + { + /* 5. Read NFC_DATR */ + for (i = 0UL; i < u32NumWords; i++) + { + au32Data[i] = NFC_DATR_REG32(i); + } + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + if (Enable == enEccState) + { + /* Write 0x00000023 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_CALCULATE_ECC); + + /* 4. Wait RB signal until high level */ + enRet = EXMC_NFC_WaitFlagUntilTo(EXMC_NFC_FLAG_ECC_CALCULATING, \ + Reset, \ + u32Timeout); + EXMC_NFC_EccCmd(Disable); + } + } + + /* 6. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + EXMC_NFC_DeselectChip(); + } + + return enRet; +} + +/** + * @brief NFC write operation + * @param [in] u32Bank The specified bank + * This parameter can be one of the following values: + * @arg EXMC_NFC_BANK_0: NFC device bank 0 + * @arg EXMC_NFC_BANK_1: NFC device bank 1 + * @arg EXMC_NFC_BANK_2: NFC device bank 2 + * @arg EXMC_NFC_BANK_3: NFC device bank 3 + * @arg EXMC_NFC_BANK_4: NFC device bank 4 + * @arg EXMC_NFC_BANK_5: NFC device bank 5 + * @arg EXMC_NFC_BANK_6: NFC device bank 6 + * @arg EXMC_NFC_BANK_7: NFC device bank 7 + * @param [in] u32Page The specified page + * @param [in] u32Col The column address + * @param [in] au32Data The buffer for writing + * @param [in] u32NumWords The buffer size for words + * @param [in] enEccState Disable/enable ECC function + * @param [in] u32Timeout The operation timeout value + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Write timeout. + * @arg ErrorInvalidParameter: The pointer au8Buf value is NULL. + * @note Block waiting until operation complete if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +static en_result_t EXMC_NFC_Write(uint32_t u32Bank, + uint32_t u32Page, + uint32_t u32Col, + const uint32_t au32Data[], + uint32_t u32NumWords, + en_functional_state_t enEccState, + uint32_t u32Timeout) +{ + uint32_t i; + uint64_t u64Val; + en_result_t enRet = Error; + const uint32_t u32CapacityIndex = EXMC_NFC_GetCapacityIndex(); + + if ((NULL != au32Data) && (u32NumWords > 0UL)) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_BANK_NUM(u32Bank)); + DDL_ASSERT(IS_EXMC_NFC_PAGE(u32Page, u32CapacityIndex)); + DDL_ASSERT(IS_EXMC_NFC_COLUMN(u32Col)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enEccState)); + + /* Check parameters */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank) | \ + EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR | \ + EXMC_NFC_FLAG_ECC_CALC_COMPLETION | \ + EXMC_NFC_FLAG_ECC_ERROR); + + /* Clear Flag */ + EXMC_NFC_ClearStatus(NFC_FLAG_RB_BANKx_MASK(u32Bank)); + + if (Enable == enEccState) + { + EXMC_NFC_EccCmd(Enable); + } + else + { + EXMC_NFC_EccCmd(Disable); + } + + u64Val = (NFC_IDXR_VAL(u32Bank, u32Page, u32Col, u32CapacityIndex) & NFC_IDXR_MASK); + + /* Write page step: + 1. Write 0x00000080 to NFC_CMDR + 2. Write NAND Flash address to NFC_IDXR0/1 + 3. Write NFC_DATR + 4. Write 0x00000010 to NFC_CMDR + 5. Wait RB signal until high level + 6. Write 0x000000FE to NFC_CMDR, and invalidate CE */ + + /* 1. Write 0x00000080 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_PAGE_PROGRAM_1ST); + + /* 2. Write NAND Flash address to NFC_IDXR0/1 */ + WRITE_REG32(M4_NFC->IDXR0, (uint32_t)(u64Val & 0xFFFFFFFFUL)); + WRITE_REG32(M4_NFC->IDXR1, (uint32_t)(u64Val >> 32UL)); + + /* 3. Write NFC_DATR */ + for (i = 0UL; i < u32NumWords; i++) + { + NFC_DATR_REG32(i) = au32Data[i]; + } + + /* 4. Write 0x00000010 to NFC_CMDR */ + WRITE_REG32(M4_NFC->CMDR, EXMC_NFC_CMD_PAGE_PROGRAM_2ND); + + /* 5. Wait RB signal until high level */ + enRet = EXMC_NFC_WaitFlagUntilTo(NFC_FLAG_RB_BANKx_MASK(u32Bank), \ + Set, \ + u32Timeout); + + /* Write 0x000000FE to NFC_CMDR, and invalidate CE */ + EXMC_NFC_DeselectChip(); + + if (Enable == enEccState) + { + EXMC_NFC_EccCmd(Disable); + } + } + + return enRet; +} + +/** + * @brief Get capacity size. + * @param None + * @retval Capacity index + * @arg NFC_CAPACITY_INDEX_512MBIT: NFC device capacity 512MBit + * @arg NFC_CAPACITY_INDEX_1GBIT: NFC device capacity 1GBit + * @arg NFC_CAPACITY_INDEX_2GBIT: NFC device capacity 2GBit + * @arg NFC_CAPACITY_INDEX_4GBIT: NFC device capacity 4GBit + * @arg NFC_CAPACITY_INDEX_8GBIT: NFC device capacity 8GBit + * @arg NFC_CAPACITY_INDEX_16GBIT: NFC device capacity 16GBit + * @arg NFC_CAPACITY_INDEX_32GBIT: NFC device capacity 32GBit + * @arg NFC_CAPACITY_INDEX_64GBIT: NFC device capacity 64GBit + */ +static uint32_t EXMC_NFC_GetCapacityIndex(void) +{ + uint32_t u32Index; + const uint32_t u32BacrSize = READ_REG32_BIT(M4_NFC->BACR, NFC_BACR_SIZE); + + switch (u32BacrSize) + { + case EXMC_NFC_BANK_CAPACITY_512MBIT: + u32Index = NFC_CAPACITY_INDEX_512MBIT; + break; + case EXMC_NFC_BANK_CAPACITY_1GBIT: + u32Index = NFC_CAPACITY_INDEX_1GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_2GBIT: + u32Index = NFC_CAPACITY_INDEX_2GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_4GBIT: + u32Index = NFC_CAPACITY_INDEX_4GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_8GBIT: + u32Index = NFC_CAPACITY_INDEX_8GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_16GBIT: + u32Index = NFC_CAPACITY_INDEX_16GBIT; + break; + case EXMC_NFC_BANK_CAPACITY_32GBIT: + u32Index = NFC_CAPACITY_INDEX_32GBIT; + break; + default: + u32Index = NFC_CAPACITY_INDEX_64GBIT; + break; + } + + return u32Index; +} + +/** + * @brief Wait the specified flag with timeout. + * @param [in] u32Flag The specified flag + * @arg EXMC_NFC_FLAG_ECC_UNCORRECTABLE_ERROR: ECC uncorrectable error + * @arg EXMC_NFC_FLAG_ECC_CORRECTABLE_ERROR: ECC correctable error + * @arg EXMC_NFC_FLAG_ECC_CALC_COMPLETION: Calculating ECC completely + * @arg EXMC_NFC_FLAG_ECC_ERROR: ECC error + * @arg EXMC_NFC_FLAG_RB_BANK0: NFC device bank 0 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK1: NFC device bank 1 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK2: NFC device bank 2 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK3: NFC device bank 3 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK4: NFC device bank 4 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK5: NFC device bank 5 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK6: NFC device bank 6 busy flag + * @arg EXMC_NFC_FLAG_RB_BANK7: NFC device bank 7 busy flag + * @param enStatus The waiting flag status (SET or RESET). + * @param u32Timeout Timeout duration + * @retval An en_result_t enumeration value: + * @arg Ok: Flag is right + * @arg ErrorTimeout: Wait timeout + * @note Block checking flag if u32Timeout value is EXMC_NFC_MAX_TIMEOUT + */ +static en_result_t EXMC_NFC_WaitFlagUntilTo(uint32_t u32Flag, + en_flag_status_t enStatus, + uint32_t u32Timeout) +{ + en_result_t enRet = Ok; + __IO uint32_t u32To = 0UL; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_NFC_FLAG(u32Flag)); + + while (EXMC_NFC_GetStatus(u32Flag) != enStatus) + { + /* Block checking flag if timeout value is EXMC_NFC_MAX_TIMEOUT */ + if ((u32To++ > u32Timeout) && (u32Timeout < EXMC_NFC_MAX_TIMEOUT)) + { + enRet = ErrorTimeout; + break; + } + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_NFC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_ots.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_ots.c new file mode 100644 index 0000000000000000000000000000000000000000..7158e6f6dd3457b8ec1b020abf773eecbb7457b6 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_ots.c @@ -0,0 +1,445 @@ +/** + ******************************************************************************* + * @file hc32f4a0_ots.c + * @brief This file provides firmware functions to manage the OTS. + @verbatim + Change Logs: + Date Author Notes + 2020-08-11 Wuze First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_ots.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_OTS OTS + * @brief OTS Driver Library + * @{ + */ + +#if (DDL_OTS_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup OTS_Configuration_Bit_Mask OTS Configuration Bit Mask + * @{ + */ +#define OTS_CTL_INIT_MSK (OTS_CTL_OTSCK | OTS_CTL_TSSTP) +#define OTS_COM_TRIG_MSK (OTS_COM_TRIG1 | OTS_COM_TRIG2) +/** + * @} + */ + +/** + * @defgroup OTS_Ext_Reg_Address OTS Extension Register Address + * @{ + */ +#define OTS_PDR1_ADDR (0x40010600UL + 0xE0UL) +#define OTS_PDR2_ADDR (0x40010600UL + 0xF4UL) +#define OTS_PDR3_ADDR (0x40010600UL + 0xF8UL) +#define OTS_CR2_ADDR (0x4004A800UL + 0x10UL) +#define OTS_TMR_ADDR (0x4004A800UL + 0x12UL) +/** + * @} + */ + +/** + * @defgroup OTS_Check_Parameters_Validity OTS check parameters validity + * @{ + */ +#define IS_OTS_CLK(x) \ +( ((x) == OTS_CLK_HRC) || \ + ((x) == OTS_CLK_XTAL)) + +#define IS_OTS_AUTO_OFF_EN(x) \ +( ((x) == OTS_AUTO_OFF_DISABLE) || \ + ((x) == OTS_AUTO_OFF_ENABLE)) + +#define IS_OTS_COM_TRIGGER(x) \ +( ((x) != 0U) && \ + (((x) | OTS_COM_TRIG_MSK) == OTS_COM_TRIG_MSK)) + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +static void OTS_GetDfltPara(const stc_ots_init_t *pstcInit); + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static float32_t m_f32SlopeK = 0.0f; +static float32_t m_f32OffsetM = 0.0f; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup OTS_Global_Functions OTS Global Functions + * @{ + */ + +/** + * @brief Initializes OTS according to the specified parameters in the structure stc_ots_init_t. + * @param [in] pstcInit Pointer to a stc_ots_init_t structure value that + * contains the configuration information for OTS. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t OTS_Init(const stc_ots_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + DDL_ASSERT(IS_OTS_CLK(pstcInit->u16ClkSrc)); + DDL_ASSERT(IS_OTS_AUTO_OFF_EN(pstcInit->u16AutoOffEn)); + + /* Stop OTS sampling. */ + OTS_Stop(); + + MODIFY_REG16(M4_OTS->CTL, OTS_CTL_INIT_MSK, (pstcInit->u16ClkSrc|pstcInit->u16AutoOffEn)); + + if ((pstcInit->f32SlopeK == 0.0f) && (pstcInit->f32OffsetM == 0.0f)) + { + OTS_GetDfltPara(pstcInit); + } + else + { + m_f32SlopeK = pstcInit->f32SlopeK; + m_f32OffsetM = pstcInit->f32OffsetM; + } + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for OTS initialization structure. + * @param [in] pstcInit Pointer to a stc_ots_init_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t OTS_StructInit(stc_ots_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + pstcInit->u16ClkSrc = OTS_CLK_HRC; + pstcInit->f32SlopeK = 0.0f; + pstcInit->f32OffsetM = 0.0f; + pstcInit->u16AutoOffEn = OTS_AUTO_OFF_ENABLE; + + pstcInit->stcParaCond.u16ClkFreq = 8U; + pstcInit->stcParaCond.u8T1 = OTS_COND_T25; + pstcInit->stcParaCond.u8T2 = OTS_COND_T125; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initializes OTS peripheral. Reset the registers of OTS. + * @param None + * @retval None + */ +void OTS_DeInit(void) +{ + /* Stop OTS. */ + OTS_Stop(); + /* Set the value of all registers to the reset value. */ + WRITE_REG16(M4_OTS->CTL, 0U); + WRITE_REG16(M4_OTS->DR1, 0U); + WRITE_REG16(M4_OTS->DR2, 0U); + WRITE_REG16(M4_OTS->ECR, 0U); +} + +/** + * @brief Get temperature via normal mode. + * @param [out] pf32Temp Pointer to a float32_t type address that the temperature value to be stored. + * @param [in] u32Timeout Timeout value. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Works timeout. + * @arg ErrorInvalidParameter: pf32Temp == NULL. + */ +en_result_t OTS_Polling(float32_t *pf32Temp, uint32_t u32Timeout) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pf32Temp != NULL) + { + enRet = ErrorTimeout; + + OTS_Start(); + do + { + if (READ_REG32(bM4_OTS->CTL_b.OTSST) == 0UL) + { + *pf32Temp = OTS_CalculateTemp(); + enRet = Ok; + break; + } + } while (u32Timeout-- != 0UL); + OTS_Stop(); + } + + return enRet; +} + +/** + * @brief Enable or disable the OTS interrutp. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the OTS interrupt. + * @arg Disable: Disable the OTS interrupt. + * @retval None + */ +void OTS_IntCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG32(bM4_OTS->CTL_b.OTSIE, enNewState); +} + +/** + * @brief Specifies the event which is used to trigger OTS start. + * @param [in] enEvent An event of other peripheral. + * This parameter can be a value of @ref en_event_src_t except 'EVT_OTS'. + * @retval None + */ +void OTS_SetTriggerSrc(en_event_src_t enEvent) +{ + MODIFY_REG32(M4_AOS->OTS_TRG, AOS_OTS_TRG_TRGSEL, enEvent); +} + +/** + * @brief Enable or disable common trigger event to start OTS. + * @param [in] u32ComTrig Common trigger event enable bit mask. + * This parameter can be a value of @ref OTS_Common_Trigger_Sel + * @arg OTS_COM_TRIG1: Common trigger 1. + * @arg OTS_COM_TRIG2: Common trigger 2. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified common trigger. + * @arg Disable: Disable the specified common trigger. + * @retval None + */ +void OTS_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_OTS_COM_TRIGGER(u32ComTrig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == Enable) + { + SET_REG32_BIT(M4_AOS->OTS_TRG, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(M4_AOS->OTS_TRG, u32ComTrig); + } +} + +/** + * @brief OTS scaling experiment. Get the value of the data register at the specified temperature to calculate K and M. + * @param [out] pu16Dr1: Pointer to an address to store the value of data register 1. + * @param [out] pu16Dr2: Pointer to an address to store the value of data register 2. + * @param [out] pu16Ecr: Pointer to an address to store the value of register ECR. + * @param [out] pf32A: Pointer to an address to store the parameter A. + * @param [in] u32Timeout: Timeout value. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: Works timeout. + * @arg ErrorInvalidParameter: -pu16Dr1 == NULL. + * -pu16Dr2 == NULL. + * -pu16Ecr == NULL. + * -pf32A == NULL. + */ +en_result_t OTS_ScalingExperiment(uint16_t *pu16Dr1, uint16_t *pu16Dr2, \ + uint16_t *pu16Ecr, float32_t *pf32A, \ + uint32_t u32Timeout) +{ + float32_t f32Dr1; + float32_t f32Dr2; + float32_t f32Ecr; + en_result_t enRet = ErrorInvalidParameter; + + if ((NULL != pu16Dr1) && (NULL != pu16Dr2) && \ + (NULL != pu16Ecr) && (NULL != pf32A)) + { + enRet = ErrorTimeout; + OTS_Start(); + do + { + if (READ_REG32(bM4_OTS->CTL_b.OTSST) == 0UL) + { + enRet = Ok; + break; + } + } while (u32Timeout-- != 0UL); + OTS_Stop(); + + if (enRet == Ok) + { + *pu16Dr1 = READ_REG16(M4_OTS->DR1); + *pu16Dr2 = READ_REG16(M4_OTS->DR2); + + f32Dr1 = (float32_t)(*pu16Dr1); + f32Dr2 = (float32_t)(*pu16Dr2); + + if (READ_REG8_BIT(M4_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_HRC) + { + *pu16Ecr = READ_REG16(M4_OTS->ECR); + f32Ecr = (float32_t)(*pu16Ecr); + } + else + { + *pu16Ecr = 1U; + f32Ecr = 1.0f; + } + + if ((*pu16Dr1 != 0U) && (*pu16Dr2 != 0U) && (*pu16Ecr != 0U)) + { + *pf32A = ((1.7f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr; + } + } + } + + return enRet; +} + +/** + * @brief Calculate the value of temperature. + * @param None + * @retval A float32_t type value of temperature value. + */ +float OTS_CalculateTemp(void) +{ + float32_t f32Ret = 0.0f; + uint16_t u16Dr1 = READ_REG16(M4_OTS->DR1); + uint16_t u16Dr2 = READ_REG16(M4_OTS->DR2); + uint16_t u16Ecr = READ_REG16(M4_OTS->ECR); + float32_t f32Dr1 = (float32_t)u16Dr1; + float32_t f32Dr2 = (float32_t)u16Dr2; + float32_t f32Ecr = (float32_t)u16Ecr; + + if (READ_REG8_BIT(M4_OTS->CTL, OTS_CTL_OTSCK) == OTS_CLK_XTAL) + { + f32Ecr = 1.0f; + } + + if ((u16Dr1 != 0U) && (u16Dr2 != 0U) && (u16Ecr != 0U)) + { + f32Ret = m_f32SlopeK * ((1.7f / f32Dr1) - (1.0f / f32Dr2)) * f32Ecr + m_f32OffsetM; + } + + return f32Ret; +} + +/** + * @} + */ + +/** + * @addtogroup OTS_Local_Functions OTS Local Functions + * @{ + */ + +/** + * @brief Get built-in slope K and offset M. + * @param [in] pstcInit Pointer to a stc_ots_init_t structure value that + * contains the configuration information for OTS. + * @retval None + */ +static void OTS_GetDfltPara(const stc_ots_init_t *pstcInit) +{ +#define OTS_SCAL_T1 (ai16Temp[pstcInit->stcParaCond.u8T1]) +#define OTS_SCAL_T2 (ai16Temp[pstcInit->stcParaCond.u8T2]) +#define OTS_SCAL_A1 (af32A[0U]) +#define OTS_SCAL_A2 (af32A[1U]) + + uint8_t i; + int16_t ai16Temp[] = {-40, 25, 125}; + uint32_t au32PDRAddr[] = {OTS_PDR3_ADDR, OTS_PDR1_ADDR, OTS_PDR2_ADDR}; + uint32_t au32PDR[2U]; + uint32_t u16D1; + uint32_t u16D2; + float32_t f32D1; + float32_t f32D2; + float32_t af32A[2U]; + float32_t f32Ehrc = 1.0f; + float32_t f32ClkFactor = (float32_t)pstcInit->stcParaCond.u16ClkFreq / 8.0f; + + au32PDR[0U] = RW_MEM32(au32PDRAddr[pstcInit->stcParaCond.u8T1]); + au32PDR[1U] = RW_MEM32(au32PDRAddr[pstcInit->stcParaCond.u8T2]); + + if (pstcInit->u16ClkSrc == OTS_CLK_HRC) + { + f32Ehrc = (float32_t)pstcInit->stcParaCond.u16ClkFreq / 0.032768f; + } + + for (i=0U; i<2U; i++) + { + u16D1 = (uint16_t)au32PDR[i]; + u16D2 = (uint16_t)(au32PDR[i] >> 16U); + f32D1 = ((float32_t)u16D1) * f32ClkFactor; + f32D2 = ((float32_t)u16D2) * f32ClkFactor; + af32A[i] = ((1.7f / f32D1) - (1.0f / f32D2)) * f32Ehrc; + } + m_f32SlopeK = ((float32_t)OTS_SCAL_T2 - (float32_t)OTS_SCAL_T1) / (OTS_SCAL_A2 - OTS_SCAL_A1); + m_f32OffsetM = (float32_t)OTS_SCAL_T2 - (m_f32SlopeK * OTS_SCAL_A2); +} + +/** + * @} + */ + +#endif /* DDL_OTS_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_pwc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_pwc.c new file mode 100644 index 0000000000000000000000000000000000000000..15420d6ebc2d2f90f26358f7efed0b5f2aa7a64d --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_pwc.c @@ -0,0 +1,1591 @@ +/** + ******************************************************************************* + * @file hc32f4a0_pwc.c + * @brief This file provides firmware functions to manage the Power Control(PWC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Zhangxl First version + 2020-07-30 Zhangxl Refine power mode switch function + 2020-08-25 Zhangxl Modify for MISRAC2012-10.1 + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_pwc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_PWC PWC + * @brief Power Control Driver Library + * @{ + */ + +#if (DDL_PWC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup PWC_Local_Macros PWC Local Macros + * @{ + */ + +/* Get the backup register address of PWC */ +#define PWC_BKRx(num) ((uint32_t)(&(M4_PWC->BKR0)) + ((uint32_t)(num) << 2U)) + +#define PWC_FCG0_MASK \ + (PWC_FCG0_DCU8 | PWC_FCG0_DCU7 | PWC_FCG0_DCU6 | \ + PWC_FCG0_DCU5 | PWC_FCG0_DCU4 | PWC_FCG0_DCU3 | \ + PWC_FCG0_DCU2 | PWC_FCG0_DCU1 | PWC_FCG0_CRC | \ + PWC_FCG0_TRNG | PWC_FCG0_HASH | PWC_FCG0_AES | \ + PWC_FCG0_CORDIC | PWC_FCG0_CTC | PWC_FCG0_AOS | \ + PWC_FCG0_FCM | PWC_FCG0_DMA2 | PWC_FCG0_DMA1 | \ + PWC_FCG0_KEY | PWC_FCG0_SRAMB| PWC_FCG0_SRAM4 | \ + PWC_FCG0_SRAM3 | PWC_FCG0_SRAM2| PWC_FCG0_SRAM1 | \ + PWC_FCG0_SRAMH) + +#define PWC_FCG1_MASK \ + (PWC_FCG1_CAN1 | PWC_FCG1_CAN2 | PWC_FCG1_ETHER | \ + PWC_FCG1_QSPI | PWC_FCG1_IIC1 | PWC_FCG1_IIC2 | \ + PWC_FCG1_IIC3 | PWC_FCG1_IIC4 | PWC_FCG1_IIC5 | \ + PWC_FCG1_IIC6 | PWC_FCG1_SDIOC1|PWC_FCG1_SDIOC2 | \ + PWC_FCG1_I2S1 | PWC_FCG1_I2S2 | PWC_FCG1_I2S3 | \ + PWC_FCG1_I2S4 | PWC_FCG1_SPI1 | PWC_FCG1_SPI2 | \ + PWC_FCG1_SPI3 | PWC_FCG1_SPI4 | PWC_FCG1_SPI5 | \ + PWC_FCG1_SPI6 | PWC_FCG1_USBFS| PWC_FCG1_USBHS | \ + PWC_FCG1_FMAC1 | PWC_FCG1_FMAC2| PWC_FCG1_FMAC3 | \ + PWC_FCG1_FMAC4) +#define PWC_FCG2_MASK \ + (PWC_FCG2_TMR6_1| PWC_FCG2_TMR6_2 | PWC_FCG2_TMR6_3 | \ + PWC_FCG2_TMR6_4 | PWC_FCG2_TMR6_5 | PWC_FCG2_TMR6_6 | \ + PWC_FCG2_TMR6_7 | PWC_FCG2_TMR6_8 | PWC_FCG2_TMR4_1 | \ + PWC_FCG2_TMR4_2 | PWC_FCG2_TMR4_3 | PWC_FCG2_HRPWM | \ + PWC_FCG2_TMR0_1 | PWC_FCG2_TMR0_2 | PWC_FCG2_EMB | \ + PWC_FCG2_TMR2_1 | PWC_FCG2_TMR2_2 | PWC_FCG2_TMR2_3 | \ + PWC_FCG2_TMR2_4 | PWC_FCG2_TMRA_1 | PWC_FCG2_TMRA_2 | \ + PWC_FCG2_TMRA_3 | PWC_FCG2_TMRA_4 | PWC_FCG2_TMRA_5 | \ + PWC_FCG2_TMRA_6 | PWC_FCG2_TMRA_7 | PWC_FCG2_TMRA_8 | \ + PWC_FCG2_TMRA_9 | PWC_FCG2_TMRA_10| PWC_FCG2_TMRA_11| \ + PWC_FCG2_TMRA_12) +#define PWC_FCG3_MASK \ + (PWC_FCG3_ADC1 | PWC_FCG3_ADC2 | PWC_FCG3_ADC3 | \ + PWC_FCG3_DAC1 | PWC_FCG3_DAC2 | PWC_FCG3_CMP1 | \ + PWC_FCG3_CMP2 | PWC_FCG3_OTS | PWC_FCG3_DVP | \ + PWC_FCG3_SMC | PWC_FCG3_DMC | PWC_FCG3_NFC | \ + PWC_FCG3_USART1 | PWC_FCG3_USART2 | PWC_FCG3_USART3 | \ + PWC_FCG3_USART4 | PWC_FCG3_USART5 | PWC_FCG3_USART6 | \ + PWC_FCG3_USART7 | PWC_FCG3_USART8 | PWC_FCG3_USART9 | \ + PWC_FCG3_USART10| PWC_FCG3_CMBIAS) + +#define PWC_RAM_MASK \ + (PWC_RAMPC0_RAMPDC0 | PWC_RAMPC0_RAMPDC1 | PWC_RAMPC0_RAMPDC2 | \ + PWC_RAMPC0_RAMPDC3 | PWC_RAMPC0_RAMPDC4 | PWC_RAMPC0_RAMPDC5 | \ + PWC_RAMPC0_RAMPDC6 | PWC_RAMPC0_RAMPDC7 | PWC_RAMPC0_RAMPDC8 | \ + PWC_RAMPC0_RAMPDC9 | PWC_RAMPC0_RAMPDC10) + +#define PWC_PRAM_MASK \ + (PWC_PRAMLPC_PRAMPDC0 | PWC_PRAMLPC_PRAMPDC1 | \ + PWC_PRAMLPC_PRAMPDC2 | PWC_PRAMLPC_PRAMPDC3 | \ + PWC_PRAMLPC_PRAMPDC4 | PWC_PRAMLPC_PRAMPDC5 | \ + PWC_PRAMLPC_PRAMPDC6 | PWC_PRAMLPC_PRAMPDC7 | \ + PWC_PRAMLPC_PRAMPDC8 | PWC_PRAMLPC_PRAMPDC9) + +#define PWC_PVD_FLAG_MASK \ + (PWC_PVDDSR_PVD1MON | PWC_PVDDSR_PVD1DETFLG| \ + PWC_PVDDSR_PVD2MON | PWC_PVDDSR_PVD2DETFLG) + +#define PWC_PDWK0_MASK \ + (PWC_PDWKE0_WKE0_0 | PWC_PDWKE0_WKE0_1 | \ + PWC_PDWKE0_WKE0_2 | PWC_PDWKE0_WKE0_3 | \ + PWC_PDWKE0_WKE1_0 | PWC_PDWKE0_WKE1_1 | \ + PWC_PDWKE0_WKE1_2 | PWC_PDWKE0_WKE1_3) + +#define PWC_PDWK1_MASK \ + (PWC_PDWKE1_WKE2_0 | PWC_PDWKE1_WKE2_1 | \ + PWC_PDWKE1_WKE2_2 | PWC_PDWKE1_WKE2_3 | \ + PWC_PDWKE1_WKE3_0 | PWC_PDWKE1_WKE3_1 | \ + PWC_PDWKE1_WKE3_2 | PWC_PDWKE1_WKE3_3) + +#define PWC_PDWK2_MASK \ + (PWC_PDWKE2_VD1WKE | PWC_PDWKE2_VD2WKE | \ + PWC_PDWKE2_RTCPRDWKE| PWC_PDWKE2_RTCALMWKE | \ + PWC_PDWKE2_WKTMWKE | PWC_PDWKE2_XTAL32ERWKE) + +#define PWC_PDWK_FLG0_MASK \ + (PWC_PDWKF0_PTWK0F | PWC_PDWKF0_PTWK1F | \ + PWC_PDWKF0_PTWK2F | PWC_PDWKF0_PTWK3F | \ + PWC_PDWKF0_VD1WKF | PWC_PDWKF0_VD2WKF) + +#define PWC_PDWK_FLG1_MASK \ + (PWC_PDWKF1_RTCPRDWKF | PWC_PDWKF1_RTCALMWKF | \ + PWC_PDWKF1_XTAL32ERWKF | PWC_PDWKF1_WKTMWKF) + +/** + * @defgroup PWC_Check_Parameters_Validity PWC Check Parameters Validity + * @{ + */ +/* Check PWC register lock status. */ +#define IS_PWC_UNLOCKED() ((M4_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1) + +/* Check PWC PVD register lock status. */ +#define IS_PVD_UNLOCKED() ((M4_PWC->FPRC & PWC_FPRC_FPRCB3) == PWC_FPRC_FPRCB3) + +#define IS_PWC_FCG0_UNLOCKED() ((M4_PWC->FCG0PC & PWC_FCG0PC_PRT0) == PWC_FCG0PC_PRT0) + +/*! Parameter validity check for peripheral in fcg0. */ +#define IS_PWC_FCG0_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | PWC_FCG0_MASK) == PWC_FCG0_MASK)) + +/*! Parameter validity check for peripheral in fcg1. */ +#define IS_PWC_FCG1_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | PWC_FCG1_MASK) == PWC_FCG1_MASK)) + +/*! Parameter validity check for peripheral in fcg2. */ +#define IS_PWC_FCG2_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | PWC_FCG2_MASK) == PWC_FCG2_MASK)) + +/*! Parameter validity check for peripheral in fcg3. */ +#define IS_PWC_FCG3_PERIPH(per) \ +( ((per) != 0x00UL) && \ + (((per) | PWC_FCG3_MASK) == PWC_FCG3_MASK)) + +/*! Parameter validity check for internal RAM setting of power mode control */ +#define IS_PWC_RAM_CONTROL(ram) \ +( ((ram) != 0x00UL) && \ + (((ram) | PWC_RAM_MASK) == PWC_RAM_MASK)) + +/*! Parameter validity check for peripheral RAM setting of power mode control */ +#define IS_PWC_PRAM_CONTROL(pram) \ +( ((pram) != 0x00UL) && \ + (((pram) | PWC_PRAM_MASK) == PWC_PRAM_MASK)) + +/*! Parameter validity check for RAM setting of MCU operating mode */ +#define IS_PWC_RAM_MODE(mode) \ +( ((mode) == PWC_RAM_HIGH) || \ + ((mode) == PWC_RAM_LOW)) + +/*! Parameter validity check for PVD channel. */ +#define IS_PWC_PVD_CH(ch) \ +( ((ch) == PWC_PVD_CH1) || \ + ((ch) == PWC_PVD_CH2)) + +/*! Parameter validity check for PVD2 ext. input function setting. */ +#define IS_PWC_PVD2_EXINP(func) \ +( ((func) == PWC_PVD2_EXINP_ON) || \ + ((func) == PWC_PVD2_EXINP_OFF)) + +/*! Parameter validity check for PVD function setting. */ +#define IS_PWC_PVD_EN(func) \ +( ((func) == PWC_PVD_ON) || \ + ((func) == PWC_PVD_OFF)) + +/*! Parameter validity check for PVD interrupt or reset function setting. */ +#define IS_PWC_PVD_IR_EN(func) \ +( ((func) == PWC_PVD_IR_ON) || \ + ((func) == PWC_PVD_IR_OFF)) + +/*! Parameter validity check for PVD interrupt or reset selection. */ +#define IS_PWC_PVD_IR_SEL(sel) \ +( ((sel) == PWC_PVD_RST) || \ + ((sel) == PWC_PVD_INT)) + +/*! Parameter validity check for PVD compare output setting. */ +#define IS_PWC_PVD_CMP_EN(out) \ +( ((out) == PWC_PVD_CMP_ON) || \ + ((out) == PWC_PVD_CMP_OFF)) + +/*! Parameter validity check for PVD digital noise filter function setting. */ +#define IS_PWC_PVD_DFS_EN(func) \ +( ((func) == PWC_PVD_DF_ON) || \ + ((func) == PWC_PVD_DF_OFF)) + +/*! Parameter validity check for PVD digital noise filter clock setting. */ +#define IS_PWC_PVD_DFS_CLK(clk) \ +( ((clk) == PWC_PVD_DFS_DIV1) || \ + ((clk) == PWC_PVD_DFS_DIV2) || \ + ((clk) == PWC_PVD_DFS_DIV4) || \ + ((clk) == PWC_PVD_DFS_MUL2)) + +/*! Parameter validity check for PVD detect voltage setting. */ +#define IS_PWC_PVD_VOLTAGE(vol) \ +( ((vol) == PWC_PVD1_2V0_PVD2_2V1) || \ + ((vol) == PWC_PVD1_2V1_PVD2_2V3) || \ + ((vol) == PWC_PVD1_2V3_PVD2_2V5) || \ + ((vol) == PWC_PVD1_2V5_PVD2_2V6) || \ + ((vol) == PWC_PVD1_2V6_PVD2_2V7) || \ + ((vol) == PWC_PVD1_2V7_PVD2_2V8) || \ + ((vol) == PWC_PVD1_2V8_PVD2_2V9) || \ + ((vol) == PWC_PVD1_2V9_PVD2_1V1)) + +/*! Parameter validity check for PVD NMI function setting. */ +#define IS_PWC_PVD_NMI(func) \ +( ((func) == PWC_PVD_INT_MASK) || \ + ((func) == PWC_PVD_INT_NONMASK)) + +/*! Parameter validity check for PVD trigger setting. */ +#define IS_PWC_PVD_TRIG(trig) \ +( ((trig) == PWC_PVD_TRIGGER_FALLING) || \ + ((trig) == PWC_PVD_TRIGGER_RISING) || \ + ((trig) == PWC_PVD_TRIGGER_BOTH)) + +/*! Parameter validity check for PVD flag. */ +#define IS_PWC_PVD_GET_FLAG(flag) \ +( ((flag) != 0x00U) && \ + (((flag) | PWC_PVD_FLAG_MASK) == PWC_PVD_FLAG_MASK)) + +/*! Parameter validity check for wakeup0 event. */ +#define IS_PWC_WAKEUP0_EVENT(evt) \ +( ((evt) != 0x00U) && \ + (((evt) | PWC_PDWK0_MASK) == PWC_PDWK0_MASK)) + +/*! Parameter validity check for wakeup1 event. */ +#define IS_PWC_WAKEUP1_EVENT(evt) \ +( ((evt) != 0x00U) && \ + (((evt) | PWC_PDWK1_MASK) == PWC_PDWK1_MASK)) + +/*! Parameter validity check for wakeup2 event. */ +#define IS_PWC_WAKEUP2_EVENT(evt) \ +( ((evt) != 0x00U) && \ + (((evt) | PWC_PDWK2_MASK) == PWC_PDWK2_MASK)) + +/*! Parameter validity check for wakeup0 flag. */ +#define IS_PWC_WAKEUP0_FLAG(flag) \ +( ((flag) != 0x00U) && \ + (((flag) | PWC_PDWK_FLG0_MASK) == PWC_PDWK_FLG0_MASK)) + +/*! Parameter validity check for wakeup1 flag. */ +#define IS_PWC_WAKEUP1_FLAG(flag) \ +( ((flag) != 0x00U) && \ + (((flag) | PWC_PDWK_FLG1_MASK) == PWC_PDWK_FLG1_MASK)) + +/*! Parameter validity check for power down mode wakeup event with trigger. */ +#define IS_PWC_WAKEUP_TRIG_EVENT(evt) \ +( ((evt) != 0x00U) && \ + (((evt) | PWC_PD_WKUP_TRIG_MASK) == PWC_PD_WKUP_TRIG_MASK)) + +/*! Parameter validity check for power down mode wakeup trigger edge. */ +#define IS_PWC_WAKEUP_TRIG(edge) \ +( ((edge) == PWC_PD_WKUP_FALLING) || \ + ((edge) == PWC_PD_WKUP_RISING)) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP0_FLAG(flag) \ +( ((flag) != 0x00U) && \ + (((flag) | PWC_PDWK_FLG0_MASK) == PWC_PDWK_FLG0_MASK)) + +/*! Parameter validity check for wake up flag. */ +#define IS_PWC_WKUP1_FLAG(flag) \ +( ((flag) != 0x00U) && \ + (((flag) | PWC_PDWK_FLG1_MASK) == PWC_PDWK_FLG1_MASK)) + +/*! Parameter validity check for stop mode drive capacity. */ +#define IS_PWC_STOP_DRV(drv) \ +( ((drv) == PWC_STOP_DRV_HIGH) || \ + ((drv) == PWC_STOP_DRV_LOW)) + +/*! Parameter validity check for clock setting after wake-up from stop mode. */ +#define IS_PWC_STOP_CLK(clk) \ +( ((clk) == PWC_STOP_CLK_KEEP) || \ + ((clk) == PWC_STOP_CLK_MRC)) + +/*! Parameter validity check for flash wait setting after wake-up from stop mode. */ +#define IS_PWC_STOP_FLASH_WAIT(wait) \ +( ((wait) == PWC_STOP_FLASH_WAIT) || \ + ((wait) == PWC_STOP_FLASH_NOWAIT)) + +/*! Parameter validity check for ex-bus setting in stop mode. */ +#define IS_PWC_STOP_EXBUS(bus) \ +( ((bus) == PWC_STOP_EXBUS_HIZ) || \ + ((bus) == PWC_STOP_EXBUS_HOLD)) + +/*! Parameter validity check for VBAT Reference Voltage. */ +#define IS_PWC_VBAT_REF_VOL(vol) \ +( ((vol) == PWC_VBAT_REF_VOL_2P0V) || \ + ((vol) == PWC_VBAT_REF_VOL_1P8V)) + +/*! Parameter validity check for BACKUP RAM Flag. */ +#define IS_PWC_BACKUP_RAM_FLAG(flag) \ +( 0U != ((flag) & (PWC_BACKUP_RAM_FLAG_RAMPDF | PWC_BACKUP_RAM_FLAG_RAMVALID))) + +/*! Parameter validity check for Backup Register Number. */ +#define IS_PWC_BACKUP_REGISTER_NUMBER(num) ((num) <= 127U) + +/*! Parameter validity check for WKT Clock Source. */ +#define IS_PWC_WKT_CLK_SRC(src) \ +( ((src) == PWC_WKT_CLK_SRC_64HZ) || \ + ((src) == PWC_WKT_CLK_SRC_XTAL32) || \ + ((src) == PWC_WKT_CLK_SRC_RTCLRC)) + +/*! Parameter validity check for WKT Comparision Value. */ +#define IS_PWC_WKT_COMPARISION_VALUE(val) ((val) <= 0x0FFFU) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup PWC_Global_Functions PWC Global Functions + * @{ + */ +/** + * @brief Enter power down mode. + * @param None + * @retval None + */ +void PWC_EnterPowerDownMode(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->STPMCR_b.STOP, 1U); + WRITE_REG32(bM4_PWC->PWRC0_b.PWDN, 1U); + + __WFI(); +} + +/** + * @brief Enter stop mode. + * @param None + * @retval None + */ +void PWC_EnterStopMode(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->STPMCR_b.STOP, 1U); + + __WFI(); +} + +/** + * @brief Enter sleep mode. + * @param None + * @retval None + */ +void PWC_EnterSleepMode(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->STPMCR_b.STOP, 0U); + + __WFI(); +} + +/** + * @brief Enable or disable the FCG0 peripheral clock. + * @param [in] u32Fcg0Periph The peripheral in FCG0. + * @arg PWC_FCG0_SRAMH + * @arg PWC_FCG0_SRAM1 + * @arg PWC_FCG0_SRAM2 + * @arg PWC_FCG0_SRAM3 + * @arg PWC_FCG0_SRAM4 + * @arg PWC_FCG0_SRAMB + * @arg PWC_FCG0_KEY + * @arg PWC_FCG0_DMA1 + * @arg PWC_FCG0_DMA2 + * @arg PWC_FCG0_FCM + * @arg PWC_FCG0_AOS + * @arg PWC_FCG0_CTC + * @arg PWC_FCG0_CORDIC + * @arg PWC_FCG0_AES + * @arg PWC_FCG0_HASH + * @arg PWC_FCG0_TRNG + * @arg PWC_FCG0_CRC + * @arg PWC_FCG0_DCU1 + * @arg PWC_FCG0_DCU2 + * @arg PWC_FCG0_DCU3 + * @arg PWC_FCG0_DCU4 + * @arg PWC_FCG0_DCU5 + * @arg PWC_FCG0_DCU6 + * @arg PWC_FCG0_DCU7 + * @arg PWC_FCG0_DCU8 + * @param [in] enNewState The new state of the clock output. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_Fcg0PeriphClockCmd(uint32_t u32Fcg0Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG0_PERIPH(u32Fcg0Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_FCG0_UNLOCKED()); + + if(Enable == enNewState) + { + CLEAR_REG32_BIT(M4_PWC->FCG0, u32Fcg0Periph); + } + else + { + SET_REG32_BIT(M4_PWC->FCG0, u32Fcg0Periph); + } +} + +/** + * @brief Enable or disable the FCG1 peripheral clock. + * @param [in] u32Fcg1Periph The peripheral in FCG1. + * @arg PWC_FCG1_CAN1 + * @arg PWC_FCG1_CAN2 + * @arg PWC_FCG1_ETHER + * @arg PWC_FCG1_QSPI + * @arg PWC_FCG1_IIC1 + * @arg PWC_FCG1_IIC2 + * @arg PWC_FCG1_IIC3 + * @arg PWC_FCG1_IIC4 + * @arg PWC_FCG1_IIC5 + * @arg PWC_FCG1_IIC6 + * @arg PWC_FCG1_SDIOC1 + * @arg PWC_FCG1_SDIOC2 + * @arg PWC_FCG1_I2S1 + * @arg PWC_FCG1_I2S2 + * @arg PWC_FCG1_I2S3 + * @arg PWC_FCG1_I2S4 + * @arg PWC_FCG1_SPI1 + * @arg PWC_FCG1_SPI2 + * @arg PWC_FCG1_SPI3 + * @arg PWC_FCG1_SPI4 + * @arg PWC_FCG1_SPI5 + * @arg PWC_FCG1_SPI6 + * @arg PWC_FCG1_USBFS + * @arg PWC_FCG1_USBHS + * @arg PWC_FCG1_FMAC1 + * @arg PWC_FCG1_FMAC2 + * @arg PWC_FCG1_FMAC3 + * @arg PWC_FCG1_FMAC4 + * @param [in] enNewState The new state of the clock output. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_Fcg1PeriphClockCmd(uint32_t u32Fcg1Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG1_PERIPH(u32Fcg1Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + CLEAR_REG32_BIT(M4_PWC->FCG1, u32Fcg1Periph); + } + else + { + SET_REG32_BIT(M4_PWC->FCG1, u32Fcg1Periph); + } +} + +/** + * @brief Enable or disable the FCG2 peripheral clock. + * @param [in] u32Fcg2Periph The peripheral in FCG2. + * @arg PWC_FCG2_TMR6_1 + * @arg PWC_FCG2_TMR6_2 + * @arg PWC_FCG2_TMR6_3 + * @arg PWC_FCG2_TMR6_4 + * @arg PWC_FCG2_TMR6_5 + * @arg PWC_FCG2_TMR6_6 + * @arg PWC_FCG2_TMR6_7 + * @arg PWC_FCG2_TMR6_8 + * @arg PWC_FCG2_TMR4_1 + * @arg PWC_FCG2_TMR4_2 + * @arg PWC_FCG2_TMR4_3 + * @arg PWC_FCG2_HRPWM + * @arg PWC_FCG2_TMR0_1 + * @arg PWC_FCG2_TMR0_2 + * @arg PWC_FCG2_EMB + * @arg PWC_FCG2_TMR2_1 + * @arg PWC_FCG2_TMR2_2 + * @arg PWC_FCG2_TMR2_3 + * @arg PWC_FCG2_TMR2_4 + * @arg PWC_FCG2_TMRA_1 + * @arg PWC_FCG2_TMRA_2 + * @arg PWC_FCG2_TMRA_3 + * @arg PWC_FCG2_TMRA_4 + * @arg PWC_FCG2_TMRA_5 + * @arg PWC_FCG2_TMRA_6 + * @arg PWC_FCG2_TMRA_7 + * @arg PWC_FCG2_TMRA_8 + * @arg PWC_FCG2_TMRA_9 + * @arg PWC_FCG2_TMRA_10 + * @arg PWC_FCG2_TMRA_11 + * @arg PWC_FCG2_TMRA_12 + * @param [in] enNewState The new state of the clock output. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_Fcg2PeriphClockCmd(uint32_t u32Fcg2Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG2_PERIPH(u32Fcg2Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + CLEAR_REG32_BIT(M4_PWC->FCG2, u32Fcg2Periph); + } + else + { + SET_REG32_BIT(M4_PWC->FCG2, u32Fcg2Periph); + } +} + +/** + * @brief Enable or disable the FCG3 peripheral clock. + * @param [in] u32Fcg3Periph The peripheral in FCG3. + * @arg PWC_FCG3_ADC1 + * @arg PWC_FCG3_ADC2 + * @arg PWC_FCG3_ADC3 + * @arg PWC_FCG3_CMBIAS + * @arg PWC_FCG3_DAC1 + * @arg PWC_FCG3_DAC2 + * @arg PWC_FCG3_CMP1 + * @arg PWC_FCG3_CMP2 + * @arg PWC_FCG3_OTS + * @arg PWC_FCG3_DVP + * @arg PWC_FCG3_SMC + * @arg PWC_FCG3_DMC + * @arg PWC_FCG3_NFC + * @arg PWC_FCG3_USART1 + * @arg PWC_FCG3_USART2 + * @arg PWC_FCG3_USART3 + * @arg PWC_FCG3_USART4 + * @arg PWC_FCG3_USART5 + * @arg PWC_FCG3_USART6 + * @arg PWC_FCG3_USART7 + * @arg PWC_FCG3_USART8 + * @arg PWC_FCG3_USART9 + * @arg PWC_FCG3_USART10 + * @param [in] enNewState The new state of the clock output. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_Fcg3PeriphClockCmd(uint32_t u32Fcg3Periph, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_FCG3_PERIPH(u32Fcg3Periph)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + CLEAR_REG32_BIT(M4_PWC->FCG3, u32Fcg3Periph); + } + else + { + SET_REG32_BIT(M4_PWC->FCG3, u32Fcg3Periph); + } +} + +/** + * @brief RAM configuration for MCU operating mode and power down control. + * @param [in] pstcRamConfig Pointer to a stc_pwc_ram_config_t structure that + * contains configuration information. + * @arg u32RamCtrl Internal RAM setting for power mode. + * PWC_RAMPC0_RAMPDC0: 0x20000000 ~ 0x2000FFFF + * PWC_RAMPC0_RAMPDC1: 0x20010000 ~ 0x2001FFFF + * PWC_RAMPC0_RAMPDC2: 0x20020000 ~ 0x2002FFFF + * PWC_RAMPC0_RAMPDC3: 0x20030000 ~ 0x2003FFFF + * PWC_RAMPC0_RAMPDC4: 0x20040000 ~ 0x2004FFFF + * PWC_RAMPC0_RAMPDC5: 0x20050000 ~ 0x20057FFF + * PWC_RAMPC0_RAMPDC6: 0x20058000 ~ 0x2005FFFF + * PWC_RAMPC0_RAMPDC7: 0x1FFE0000 ~ 0x1FFE7FFF + * PWC_RAMPC0_RAMPDC8: 0x1FFE8000 ~ 0x1FFEFFFF + * PWC_RAMPC0_RAMPDC9: 0x1FFF0000 ~ 0x1FFF7FFF + * PWC_RAMPC0_RAMPDC10: 0x1FFF8000 ~ 0x1FFFFFFF + * @arg u32PRamCtrl Peripheral RAM setting for power mode. + * PWC_PRAMLPC_PRAMPDC0: CAN1 RAM + * PWC_PRAMLPC_PRAMPDC1: CAN2 RAM + * PWC_PRAMLPC_PRAMPDC2: CACHE RAM + * PWC_PRAMLPC_PRAMPDC3: USBFS RAM + * PWC_PRAMLPC_PRAMPDC4: USBHS RAM + * PWC_PRAMLPC_PRAMPDC5: Ethernet Tx RAM + * PWC_PRAMLPC_PRAMPDC6: Ethernet Rx RAM + * PWC_PRAMLPC_PRAMPDC7: SDIO1 RAM + * PWC_PRAMLPC_PRAMPDC8: SDIO2 RAM + * PWC_PRAMLPC_PRAMPDC9: NFC RAM + * @arg u16RamMode RAM setting for Operating mode. + * PWC_RAM_HIGH MCU operating under high frequency (lower than 240MHz) + * PWC_RAM_LOW MCU operating under low frequency (lower than 8MHz) + * @retval Ok: RAM config successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_RamConfig(const stc_pwc_ram_config_t *pstcRamConfig) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcRamConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_PWC_RAM_CONTROL(pstcRamConfig->u32RamCtrl)); + DDL_ASSERT(IS_PWC_PRAM_CONTROL(pstcRamConfig->u32PRamCtrl)); + DDL_ASSERT(IS_PWC_RAM_MODE(pstcRamConfig->u16RamMode)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(M4_PWC->RAMPC0, pstcRamConfig->u32RamCtrl); + WRITE_REG32(M4_PWC->PRAMLPC, pstcRamConfig->u32PRamCtrl); + WRITE_REG16(M4_PWC->RAMOPM, pstcRamConfig->u16RamMode); + } + return enRet; +} + +/** + * @brief Initialize PVD config structure. Fill each pstcPvdConfig with default value + * @param [in] pstcPvdConfig Pointer to a stc_pwc_pvd_config_t structure that + * contains configuration information. + * @retval Ok: PVD structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_PVD_StructInit(stc_pwc_pvd_config_t *pstcPvdConfig) +{ + en_result_t enRet = Ok; + /* Check if pointer is NULL */ + if (NULL == pstcPvdConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Reset PVD init structure parameters values */ + pstcPvdConfig->u8PvdEn = PWC_PVD_OFF; + pstcPvdConfig->u8Pvd2ExtInEn = PWC_PVD2_EXINP_OFF; + pstcPvdConfig->u8PvdCmpOutEn = PWC_PVD_CMP_OFF; + pstcPvdConfig->u8PvdIntRstSel = PWC_PVD_INT; + pstcPvdConfig->u8PvdIntRstEn = PWC_PVD_IR_OFF; + pstcPvdConfig->u8FilterEn = PWC_PVD_DF_ON; + pstcPvdConfig->u8FilterClk = PWC_PVD_DFS_DIV4; + pstcPvdConfig->u8PvdVoltage = PWC_PVD1_2V0_PVD2_2V1; + pstcPvdConfig->u8PvdNmiEn = PWC_PVD_INT_NONMASK; + pstcPvdConfig->u8PvdTrigger = PWC_PVD_TRIGGER_FALLING; + } + return enRet; +} + +/** + * @brief PVD configuration. + * @param [in] u8Ch PVD channel + * @arg PWC_PVD_CH1 + * @arg PWC_PVD_CH2 + * @param [in] pstcPvdConfig Pointer to a stc_pwc_pvd_config_t structure that + * contains configuration information. + * @retval Ok: PVD initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_PVD_Init(uint8_t u8Ch, const stc_pwc_pvd_config_t *pstcPvdConfig) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcPvdConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_PVD_UNLOCKED()); + DDL_ASSERT(IS_PWC_PVD_CH(u8Ch)); + DDL_ASSERT(IS_PWC_PVD2_EXINP(pstcPvdConfig->u8Pvd2ExtInEn)); + DDL_ASSERT(IS_PWC_PVD_EN(pstcPvdConfig->u8PvdEn)); + DDL_ASSERT(IS_PWC_PVD_IR_EN(pstcPvdConfig->u8PvdIntRstEn)); + DDL_ASSERT(IS_PWC_PVD_IR_SEL(pstcPvdConfig->u8PvdIntRstSel)); + DDL_ASSERT(IS_PWC_PVD_CMP_EN(pstcPvdConfig->u8PvdCmpOutEn)); + DDL_ASSERT(IS_PWC_PVD_DFS_EN(pstcPvdConfig->u8FilterEn)); + DDL_ASSERT(IS_PWC_PVD_DFS_CLK(pstcPvdConfig->u8FilterClk)); + DDL_ASSERT(IS_PWC_PVD_VOLTAGE(pstcPvdConfig->u8PvdVoltage)); + DDL_ASSERT(IS_PWC_PVD_NMI(pstcPvdConfig->u8PvdNmiEn)); + DDL_ASSERT(IS_PWC_PVD_TRIG(pstcPvdConfig->u8PvdTrigger)); + + if (PWC_PVD_CH1 == u8Ch) + { + WRITE_REG32(bM4_PWC->PVDCR0_b.PVD1EN, pstcPvdConfig->u8PvdEn); + } + else + { + WRITE_REG32(bM4_PWC->PVDCR0_b.PVD2EN, pstcPvdConfig->u8PvdEn); + WRITE_REG32(bM4_PWC->PVDCR0_b.EXVCCINEN, pstcPvdConfig->u8Pvd2ExtInEn); + + } + /* config PVDCMPOE before PVDIRE */ + MODIFY_REG8(M4_PWC->PVDCR1, \ + (PWC_PVDCR1_PVD1CMPOE << (uint8_t)(u8Ch * 4U)), \ + (pstcPvdConfig->u8PvdCmpOutEn) << (uint8_t)(u8Ch * 4U)); + + MODIFY_REG8(M4_PWC->PVDCR1, \ + (PWC_PVDCR1_PVD1IRE | PWC_PVDCR1_PVD1IRS) << (uint8_t)(u8Ch * 4U), \ + (pstcPvdConfig->u8PvdIntRstSel | pstcPvdConfig->u8PvdIntRstEn) << (uint8_t)(u8Ch * 4U)); + if (PWC_PVD_DF_ON == pstcPvdConfig->u8FilterEn) + { + /* disable filter function in advance */ + SET_REG8_BIT(M4_PWC->PVDFCR, PWC_PVDFCR_PVD1NFDIS << (uint8_t)(u8Ch * 4U)); + } + MODIFY_REG8(M4_PWC->PVDFCR, \ + (PWC_PVDFCR_PVD1NFDIS | PWC_PVDFCR_PVD1NFCKS) << (uint8_t)(u8Ch * 4U), \ + (pstcPvdConfig->u8FilterEn | pstcPvdConfig->u8FilterClk) << (uint8_t)(u8Ch * 4U)); + + MODIFY_REG8(M4_PWC->PVDLCR, (PWC_PVDLCR_PVD1LVL << (uint8_t)(u8Ch * 4U)), \ + (pstcPvdConfig->u8PvdVoltage) << (uint8_t)(u8Ch * 4U)); + + MODIFY_REG8(M4_PWC->PVDICR, \ + (PWC_PVDICR_PVD1NMIS | PWC_PVDICR_PVD1EDGS) << (uint8_t)(u8Ch * 4U), \ + (pstcPvdConfig->u8PvdNmiEn | pstcPvdConfig->u8PvdTrigger) << (uint8_t)(u8Ch * 4U)); + } + return enRet; +} + +/** + * @brief Get PVD flag. + * @param [in] u8Flag PVD flag to be get + * @arg PWC_PVDDSR_PVD1DETFLG: VCC across VPVD1 + * @arg PWC_PVDDSR_PVD2DETFLG: VCC across VPVD2 + * @arg PWC_PVDDSR_PVD1MON: VCC > VPVD1 + * @arg PWC_PVDDSR_PVD2MON: VCC > VPVD2 + * @retval An en_flag_status_t enumeration value + * @arg Set + * @arg Reset + * @note PVDxDETFLG is avaliable when PVDCR0.PVDxEN and PVDCR1.PVDxCMPOE are set to '1' + */ +en_flag_status_t PWC_PVD_GetStatus(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_PVD_GET_FLAG(u8Flag)); + return READ_REG8_BIT(M4_PWC->PVDDSR, u8Flag) ? Set:Reset; +} + +/** + * @brief Clear PVD1 & PVD2 flag. + * @param None + * @retval None + */ +void PWC_PVD_ClearStatus(void) +{ + DDL_ASSERT(IS_PVD_UNLOCKED()); + WRITE_REG32(bM4_PWC->PVDDSR_b.PVD1DETFLG, 0UL); +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u8Wkup0Evt Wakeup pin group 0 and 1. + * @arg PWC_PDWKE0_WKE0_0 + * @arg PWC_PDWKE0_WKE0_1 + * @arg PWC_PDWKE0_WKE0_2 + * @arg PWC_PDWKE0_WKE0_3 + * @arg PWC_PDWKE0_WKE1_0 + * @arg PWC_PDWKE0_WKE1_1 + * @arg PWC_PDWKE0_WKE1_2 + * @arg PWC_PDWKE0_WKE1_3 + * @param [in] enNewState The new state of the wakeup event. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_PdWakeup0Cmd(uint8_t u8Wkup0Evt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WAKEUP0_EVENT(u8Wkup0Evt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if(Enable == enNewState) + { + SET_REG8_BIT(M4_PWC->PDWKE0, u8Wkup0Evt); + } + else + { + CLEAR_REG8_BIT(M4_PWC->PDWKE0, u8Wkup0Evt); + } +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u8Wkup1Evt Wakeup pin group 0 and 1. + * @arg PWC_PDWKE1_WKE2_0 + * @arg PWC_PDWKE1_WKE2_1 + * @arg PWC_PDWKE1_WKE2_2 + * @arg PWC_PDWKE1_WKE2_3 + * @arg PWC_PDWKE1_WKE3_0 + * @arg PWC_PDWKE1_WKE3_1 + * @arg PWC_PDWKE1_WKE3_2 + * @arg PWC_PDWKE1_WKE3_3 + * @param [in] enNewState The new state of the wakeup event. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_PdWakeup1Cmd(uint8_t u8Wkup1Evt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WAKEUP1_EVENT(u8Wkup1Evt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if(Enable == enNewState) + { + SET_REG8_BIT(M4_PWC->PDWKE1, u8Wkup1Evt); + } + else + { + CLEAR_REG8_BIT(M4_PWC->PDWKE1, u8Wkup1Evt); + } +} + +/** + * @brief Power down mode wake up event config. + * @param [in] u8Wkup2Evt PVD, RTC, XTAL32 and wakeup timer. + * @arg PWC_PDWKE2_VD1WKE + * @arg PWC_PDWKE2_VD2WKE + * @arg PWC_PDWKE2_RTCPRDWKE + * @arg PWC_PDWKE2_RTCALMWKE + * @arg PWC_PDWKE2_XTAL32ERWKE + * @arg PWC_PDWKE2_WKTMWKE + * @param [in] enNewState The new state of the wakeup event. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_PdWakeup2Cmd(uint8_t u8Wkup2Evt, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_WAKEUP2_EVENT(u8Wkup2Evt)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if(Enable == enNewState) + { + SET_REG8_BIT(M4_PWC->PDWKE2, u8Wkup2Evt); + } + else + { + CLEAR_REG8_BIT(M4_PWC->PDWKE2, u8Wkup2Evt); + } +} + +/** + * @brief Power down mode wake up event trigger config. + * @param [in] u8WkupEvt PVD and wakeup pin. + * @arg PWC_PD_WKUP_PVD1 + * @arg PWC_PD_WKUP_PVD2 + * @arg PWC_PD_WKUP_WKP0 + * @arg PWC_PD_WKUP_WKP1 + * @arg PWC_PD_WKUP_WKP2 + * @arg PWC_PD_WKUP_WKP3 + * @param [in] u8TrigEdge The trigger edge. + * @arg PWC_PD_WKUP_FALLING + * @arg PWC_PD_WKUP_RISING + * @retval None + */ +void PWC_PdWakeupTrigConfig(uint8_t u8WkupEvt, uint8_t u8TrigEdge) +{ + DDL_ASSERT(IS_PWC_WAKEUP_TRIG_EVENT(u8WkupEvt)); + DDL_ASSERT(IS_PWC_WAKEUP_TRIG(u8TrigEdge)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (PWC_PD_WKUP_RISING == u8TrigEdge) + { + SET_REG8_BIT(M4_PWC->PDWKES, u8WkupEvt); + } + else + { + CLEAR_REG8_BIT(M4_PWC->PDWKES, u8WkupEvt); + } +} + +/** + * @brief Get wake up event flag. + * @param [in] u8Flag Wake up event. + * @arg PWC_PDWKF0_PTWK0F + * @arg PWC_PDWKF0_PTWK1F + * @arg PWC_PDWKF0_PTWK2F + * @arg PWC_PDWKF0_PTWK3F + * @arg PWC_PDWKF0_VD1WKF + * @arg PWC_PDWKF0_VD2WKF + * @retval en_flag_status_t + */ +en_flag_status_t PWC_GetWakeup0Status(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_WKUP0_FLAG(u8Flag)); + + return (READ_REG8_BIT(M4_PWC->PDWKF0, u8Flag) ? Set : Reset); +} + +/** + * @brief Get wake up event flag. + * @param [in] u8Flag Wake up event. + * @arg PWC_PDWKF1_RTCPRDWKF + * @arg PWC_PDWKF1_RTCALMWKF + * @arg PWC_PDWKF1_XTAL32ERWK + * @arg PWC_PDWKF1_WKTMWKF + * @retval en_flag_status_t + */ +en_flag_status_t PWC_GetWakeup1Status(uint8_t u8Flag) +{ + DDL_ASSERT(IS_PWC_WKUP1_FLAG(u8Flag)); + + return (READ_REG8_BIT(M4_PWC->PDWKF1, u8Flag) ? Set : Reset); +} + +/** + * @brief HRC clock power config. + * @param [in] enNewState The new state of HRC power state. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_HrcPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->PWRC1_b.VHRCSD, enNewState); +} + +/** + * @brief PLLA & PLLH clock power config. + * @param [in] enNewState The new state of PLLA & PLLH power state. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_PllPwrCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (Enable == enNewState) + { + SET_REG8_BIT(M4_PWC->PWRC1, PWC_PWRC1_VPLLSD); + } + else + { + CLEAR_REG8_BIT(M4_PWC->PWRC1, PWC_PWRC1_VPLLSD); + } +} + +/** + * @brief Switch high speed to ultra low speed, set the drive ability. + * @param None + * @retval Ok: Mode switch successful. + * Error: Mode switch failure, check whether EFM was unlocked please. + * @note Before calling this API, please switch system clock to the required + * low speed frequency in advance, and make sure NO any flash program + * or erase operation background. + */ +en_result_t PWC_HighSpeedToLowSpeed(void) +{ + en_result_t enRet = Ok; + uint32_t u32To; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_EFM->FRMC_b.LVM, 0x01UL); + WRITE_REG16(M4_PWC->RAMOPM, PWC_RAM_LOW); + + u32To = 0x1000UL; + while (1UL != READ_REG32(bM4_EFM->FRMC_b.LVM)) + { + if (0UL == u32To--) + { + enRet = Error; + break; + } + } + if (Ok == enRet) + { + u32To = 0x1000UL; + while(PWC_RAM_LOW != READ_REG16(M4_PWC->RAMOPM)) + { + if (0UL == u32To--) + { + enRet = Error; + break; + } + } + } + if (Ok == enRet) + { + MODIFY_REG8(M4_PWC->PWRC2, PWC_PWRC2_DDAS, 0x01UL); + WRITE_REG8(M4_PWC->PWRC3, 0x00UL); + MODIFY_REG8(M4_PWC->PWRC2, PWC_PWRC2_DVS ,PWC_NOR_DRV_LOW); + DDL_DelayMS(1UL); + } + return enRet; +} + +/** + * @brief Switch ultra low speed to high speed, set the drive ability. + * @param None + * @retval Ok: Mode switch successful. + * Error: Mode switch failure, check whether EFM was unlocked please. + * @note After calling this API, the system clock is able to switch high frequency. + */ +en_result_t PWC_LowSpeedToHighSpeed(void) +{ + en_result_t enRet = Ok; + uint32_t u32To; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(M4_PWC->PWRC2, PWC_PWRC2_DDAS, 0x0FUL); + WRITE_REG8(M4_PWC->PWRC3, 0xFFUL); + SET_REG8_BIT(M4_PWC->PWRC2, PWC_NOR_DRV_HIGH); + DDL_DelayMS(1UL); + + WRITE_REG32(bM4_EFM->FRMC_b.LVM, 0x00UL); + WRITE_REG16(M4_PWC->RAMOPM, PWC_RAM_HIGH); + + u32To = 0x1000UL; + while (0UL != READ_REG32(bM4_EFM->FRMC_b.LVM)) + { + if (0UL == u32To--) + { + enRet = Error; + break; + } + } + if (Ok == enRet) + { + u32To = 0x1000UL; + while(PWC_RAM_HIGH != READ_REG16(M4_PWC->RAMOPM)) + { + if (0UL == u32To--) + { + enRet = Error; + break; + } + } + } + return enRet; +} + +/** + * @brief ADC buffer config. + * @param [in] enNewState The new state of ADC buffer. + * @arg Enable + * @arg Disable + * @retval None + */ +void PWC_AdcBufCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->PWRC4_b.ADBUFE, enNewState); +} + +/** + * @brief ADC internal channel sampling selection. + * @param [in] u8AdcInternVol The sampling voltage for ADC internal channel. + * @arg PWC_AD_INTERN_REF + * @arg PWC_AD_VBAT_DIV2 + * @retval None + */ +void PWC_AdcInternVolSel(uint8_t u8AdcInternVol) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->PWRC4_b.ADBUFS, u8AdcInternVol); +} + +/** + * @brief Initialize Power down mode config structure. Fill each pstcPDModeConfig with default value + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval Ok: Power down mode structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_PowerDownStructInit(stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcPDModeConfig->u8IOState = PWC_PD_IO_STATE1; + pstcPDModeConfig->u8PDMode = PWC_PD_MODE1; + pstcPDModeConfig->u8WkUpSpeed = PWC_PD_WKUP_SLOW; + } + return enRet; +} + +/** + * @brief Power down mode config structure. + * @param [in] pstcPDModeConfig Pointer to a stc_pwc_pd_mode_config_t structure that + * contains configuration information. + * @retval Ok: Power down mode config successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_PowerDownConfig(const stc_pwc_pd_mode_config_t *pstcPDModeConfig) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcPDModeConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(M4_PWC->PWRC0, (PWC_PWRC0_IORTN | PWC_PWRC0_PDMDS), \ + (pstcPDModeConfig->u8IOState | pstcPDModeConfig->u8PDMode)); + WRITE_REG32(bM4_PWC->PWRC1_b.PDTS, pstcPDModeConfig->u8WkUpSpeed); + } + return enRet; +} + +/** + * @brief Stop mode config. + * @param [in] pstcStopConfig Chip config before entry stop mode. + * @arg u8StopDrv, MCU from which speed mode entry stop mode. + * @arg u16ClkKeep, System clock setting after wake-up from stop mode. + * @arg u16FlashWait, Whether wait flash stable after wake-up from stop mode. + * @arg u16ExBusHold, ExBus status in stop mode. + * @retval Ok: Stop mode config successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_StopConfig(const stc_pwc_stop_mode_config *pstcStopConfig) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + DDL_ASSERT(IS_PWC_STOP_DRV(pstcStopConfig->u8StopDrv)); + DDL_ASSERT(IS_PWC_STOP_CLK(pstcStopConfig->u16ClkKeep)); + DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(pstcStopConfig->u16FlashWait)); + DDL_ASSERT(IS_PWC_STOP_EXBUS(pstcStopConfig->u16ExBusHold)); + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(M4_PWC->PWRC1, PWC_PWRC1_STPDAS, pstcStopConfig->u8StopDrv); + + MODIFY_REG16(M4_PWC->STPMCR, \ + (PWC_STPMCR_EXBUSOE | PWC_STPMCR_CKSMRC | PWC_STPMCR_FLNWT),\ + (pstcStopConfig->u16ExBusHold | pstcStopConfig->u16ClkKeep |\ + pstcStopConfig->u16FlashWait)); + } + return enRet; +} + +/** + * @brief Initialize stop mode config structure. Fill each pstcStopConfig with default value + * @param [in] pstcStopConfig Pointer to a stc_pwc_stop_mode_config structure that + * contains configuration information. + * @retval Ok: Stop down mode structure initialize successful + * ErrorInvalidParameter: NULL pointer + */ +en_result_t PWC_StopStructInit(stc_pwc_stop_mode_config *pstcStopConfig) +{ + en_result_t enRet = Ok; + + /* Check if pointer is NULL */ + if (NULL == pstcStopConfig) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcStopConfig->u8StopDrv = PWC_STOP_DRV_HIGH; + pstcStopConfig->u16ExBusHold = PWC_STOP_EXBUS_HIZ; + pstcStopConfig->u16ClkKeep = PWC_STOP_CLK_KEEP; + pstcStopConfig->u16FlashWait = PWC_STOP_FLASH_WAIT; + } + return enRet; +} +/** + * @brief Stop mode wake up clock config. + * @param [in] u16ClkKeep System clock setting after wake-up from stop mode. + * @arg PWC_STOP_CLK_KEEP + * @arg PWC_STOP_CLK_MRC + * @retval None + */ +void PWC_StopClockKeepConfig(uint16_t u16ClkKeep) +{ + DDL_ASSERT(IS_PWC_STOP_CLK(u16ClkKeep)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(M4_PWC->STPMCR, PWC_STPMCR_CKSMRC, u16ClkKeep); +} + +/** + * @brief Stop mode wake up flash wait config. + * @param [in] u16FlashWait Whether wait flash stable after wake-up from stop mode. + * @arg PWC_STOP_FLASH_WAIT + * @arg PWC_STOP_FLASH_NOWAIT + * @retval None + */ +void PWC_StopFlashWaitConfig(uint16_t u16FlashWait) +{ + DDL_ASSERT(IS_PWC_STOP_FLASH_WAIT(u16FlashWait)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(M4_PWC->STPMCR, PWC_STPMCR_FLNWT, u16FlashWait); +} + +/** + * @brief Stop mode ex-bus status config. + * @param [in] u16ExBusHold ExBus status in stop mode. + * @arg PWC_STOP_EXBUS_HIZ + * @arg PWC_STOP_EXBUS_HOLD + * @retval None + */ +void PWC_StopExBusHoldConfig(uint16_t u16ExBusHold) +{ + DDL_ASSERT(IS_PWC_STOP_EXBUS(u16ExBusHold)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG16(M4_PWC->STPMCR, PWC_STPMCR_EXBUSOE, u16ExBusHold); +} + +/** + * @brief Stop mode driver capacity config. + * @param [in] u8StopDrv Drive capacity while enter stop mode. + * @arg PWC_STOP_DRV_HIGH + * @arg PWC_STOP_DRV_LOW + * @retval None + */ +void PWC_StopDrvConfig(uint8_t u8StopDrv) +{ + DDL_ASSERT(IS_PWC_STOP_DRV(u8StopDrv)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(M4_PWC->PWRC1, PWC_PWRC1_STPDAS, u8StopDrv); +} + +/** + * @brief VBAT monitor reference voltage selection. + * @param [in] u8RefVol VBAT monitor reference voltage. + * This parameter can be one of the following values: + * @arg PWC_VBAT_REF_VOL_1P8V: Vbat reference voltage is 1.8V + * @arg PWC_VBAT_REF_VOL_2P0V: Vbat reference voltage is 2.0V + * @retval None + */ +void PWC_VBAT_MonitorVolSel(uint8_t u8RefVol) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_VBAT_REF_VOL(u8RefVol)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->PWRC4_b.VBATREFSEL, u8RefVol); +} + +/** + * @brief Enable or Disable VBAT monitor. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void PWC_VBAT_MonitorCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->PWRC4_b.VBATME, enNewState); +} + +/** + * @brief Get VBAT voltage status. + * @param None + * @retval uint8_t VBAT voltage status + */ +uint8_t PWC_VBAT_GetVolStatus(void) +{ + uint8_t u8VolSta; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + u8VolSta = (uint8_t)READ_REG32(bM4_PWC->PWRC4_b.VBATMON); + + return u8VolSta; +} + +/** + * @brief Enable or Disable VBAT measure voltage. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void PWC_VBAT_MeasureVolCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->VBATCR_b.VBATDIVMONE, enNewState); +} + +/** + * @brief Reset the VBAT area. + * @param None + * @retval None + */ +void PWC_VBAT_Reset(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + WRITE_REG8(M4_PWC->VBATRSTR, 0xA5U); +} + +/** + * @brief Enable or Disable VBAT power. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void PWC_VBAT_PwrCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + DDL_ASSERT(IS_PWC_UNLOCKED()); + WRITE_REG32(bM4_PWC->VBATCR_b.CSDIS, enNewState); +} + +/** + * @brief Enable or Disable Backup RAM power. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void PWC_BkRamPwrCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + if (Enable == enNewState) + { + WRITE_REG32(bM4_PWC->VBATCR_b.VBTRSD, 0UL); + } + else + { + WRITE_REG32(bM4_PWC->VBATCR_b.VBTRSD, 1UL); + } +} + +/** + * @brief Get Backup RAM flag. + * @param [in] u8Flag Backup RAM flag. + * This parameter can be one or any combination of the following values: + * @arg PWC_BACKUP_RAM_FLAG_RAMPDF: Backup RAM power down flag + * @arg PWC_BACKUP_RAM_FLAG_RAMVALID: Backup RAM read/write flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t PWC_GetBkRamStatus(uint8_t u8Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_PWC_BACKUP_RAM_FLAG(u8Flag)); + + DDL_ASSERT(IS_PWC_UNLOCKED()); + if (0U != (READ_REG8_BIT(M4_PWC->VBATCR, u8Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Write Backup register. + * @param [in] u8RegNum Backup register number. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 127. + * @param [in] u8RegVal Value written to register + * @retval None + */ +void PWC_WriteBackupReg(uint8_t u8RegNum, uint8_t u8RegVal) +{ + __IO uint8_t *BKR; + + /* Check parameters */ + DDL_ASSERT(IS_PWC_BACKUP_REGISTER_NUMBER(u8RegNum)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + BKR = (__IO uint8_t *)PWC_BKRx(u8RegNum); + WRITE_REG8(*BKR, u8RegVal); +} + +/** + * @brief Read Backup register. + * @param [in] u8RegNum Backup register number. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 127. + * @retval uint8_t Register value + */ +uint8_t PWC_ReadBackupReg(uint8_t u8RegNum) +{ + uint8_t u8RegVal; + + /* Check parameters */ + DDL_ASSERT(IS_PWC_BACKUP_REGISTER_NUMBER(u8RegNum)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + u8RegVal = READ_REG8(*((__IO uint8_t *)PWC_BKRx(u8RegNum))); + + return u8RegVal; +} + +/** + * @brief WKT Timer Initialize. + * @param [in] u8ClkSrc Clock source. + * This parameter can be one of the following values: + * @arg PWC_WKT_CLK_SRC_64HZ: 64Hz Clock + * @arg PWC_WKT_CLK_SRC_XTAL32: XTAL32 Clock + * @arg PWC_WKT_CLK_SRC_RTCLRC: RTCLRC Clock + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_Init(uint8_t u8ClkSrc, uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_CLK_SRC(u8ClkSrc)); + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + MODIFY_REG8(M4_PWC->WKTC2, PWC_WKTC2_WKCKS, u8ClkSrc); + WRITE_REG8(M4_PWC->WKTC0, (uint8_t)(u16CmpVal & 0x00FFU)); + WRITE_REG8(M4_PWC->WKTC1, (uint8_t)((u16CmpVal >> 8U) & 0x000FU)); +} + +/** + * @brief Set WKT Timer compare value. + * @param [in] u16CmpVal Comparison value of the Counter. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0xFFF. + * @retval None + */ +void PWC_WKT_SetCompareValue(uint16_t u16CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_PWC_WKT_COMPARISION_VALUE(u16CmpVal)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG8(M4_PWC->WKTC0, (uint8_t)(u16CmpVal & 0x00FFU)); + WRITE_REG8(M4_PWC->WKTC1, (uint8_t)((u16CmpVal >> 8U) & 0x000FU)); +} + +/** + * @brief Get WKT Timer compare value. + * @param None + * @retval uint16_t WKT Compara value + */ +uint16_t PWC_WKT_GetCompareValue(void) +{ + uint16_t u16CmpVal; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + u16CmpVal = ((uint16_t)READ_REG16_BIT(M4_PWC->WKTC1, PWC_WKTC1_WKTMCMP) << 8U); + u16CmpVal |= READ_REG8(M4_PWC->WKTC0); + + return u16CmpVal; +} + +/** + * @brief Enable or Disable WKT Timer. + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void PWC_WKT_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_PWC_UNLOCKED()); + + WRITE_REG32(bM4_PWC->WKTC2_b.WKTCE, enNewState); +} + +/** + * @brief Get WKT Timer count match flag. + * @param None + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t PWC_WKT_GetStatus(void) +{ + en_flag_status_t enFlagSta; + + DDL_ASSERT(IS_PWC_UNLOCKED()); + + enFlagSta = (en_flag_status_t)READ_REG32(bM4_PWC->WKTC2_b.WKOVF); + + return enFlagSta; +} + +/** + * @brief Clear WKT Timer count match flag. + * @param None + * @retval None + */ +void PWC_WKT_ClearStatus(void) +{ + DDL_ASSERT(IS_PWC_UNLOCKED()); + WRITE_REG32(bM4_PWC->WKTC2_b.WKOVF, 0UL); +} + +/** + * @} + */ + +#endif /* DDL_PWC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ + diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_qspi.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_qspi.c new file mode 100644 index 0000000000000000000000000000000000000000..637b5fe856e03ed2dc617c93b4ec8c4bb3c69848 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_qspi.c @@ -0,0 +1,590 @@ +/** + ******************************************************************************* + * @file hc32f4a0_qspi.c + * @brief This file provides firmware functions to manage the QSPI. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-07-15 Wuze Refined QSPI_WriteData(). + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_qspi.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_QSPI QSPI + * @brief QSPI Driver Library + * @{ + */ + +#if (DDL_QSPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup QSPI_Local_Macros QSPI Local Macros + * @{ + */ + +/** + * @defgroup QSPI_Configuration_Bit_Mask QSPI Configuration Bit Mask + * @{ + */ +#define QSPI_FLAG_CLR_MSK (QSPI_FLAG_ROM_ACCESS_ERR) +/** + * @} + */ + +/** + * @defgroup QSPI_Common_Instruction QSPI Common Instruction + * @{ + */ +#define QSPI_INS_ENTER_4BA (0xB7U) +#define QSPI_INS_EXIT_4BA (0xE9U) +/** + * @} + */ + +/** + * @defgroup QSPI_Check_Parameters_Validity QSPI check parameters validity + * @{ + */ +#define IS_QSPI_CLK_DIV(x) \ +( ((x) >= 2U) && ((x) <= 64U)) + +#define IS_QSPI_CS_SETUP_TIMING(x) \ +( ((x) == QSPI_CS_SETUP_BEFORE_0P5_CYCLE) || \ + ((x) == QSPI_CS_SETUP_BEFORE_1P5_CYCLE)) + +#define IS_QSPI_CS_RELEASE_TIMING(x) \ +( ((x) == QSPI_CS_RELEASE_AFTER_0P5_CYCLE) || \ + ((x) == QSPI_CS_RELEASE_AFTER_1P5_CYCLE)) + +#define IS_QSPI_CS_IDLE_TIME(x) \ +( ((x) >= 1U) && ((x) <= 16U)) + +#define IS_QSPI_CS_EXTEND_TIME(x) \ +( ((x) == QSPI_CS_EXTEND_0CYCLE) || \ + ((x) == QSPI_CS_EXTEND_32CYCLE) || \ + ((x) == QSPI_CS_EXTEND_128CYCLE) || \ + ((x) == QSPI_CS_EXTEND_INFINITE)) + +#define IS_QSPI_SPI_MODE(x) \ +( ((x) == QSPI_SPI_MODE_0) || \ + ((x) == QSPI_SPI_MODE_3)) + +#define IS_QSPI_PREFETCH_STOP_POSITION(x) \ +( ((x) == QSPI_PREFETCH_STOP_BYTE_EDGE) || \ + ((x) == QSPI_PREFETCH_STOP_IMMED)) + +#define IS_QSPI_READ_MODE(x) \ +( ((x) == QSPI_READ_STANDARD_READ) || \ + ((x) == QSPI_READ_FAST_READ) || \ + ((x) == QSPI_READ_FAST_READ_DUAL_OUTPUT) || \ + ((x) == QSPI_READ_FAST_READ_DUAL_IO) || \ + ((x) == QSPI_READ_FAST_READ_QUAD_OUTPUT) || \ + ((x) == QSPI_READ_FAST_READ_QUAD_IO) || \ + ((x) == QSPI_READ_CUSTOM_STANDARD_READ) || \ + ((x) == QSPI_READ_CUSTOM_FAST_READ)) + +#define IS_QSPI_COMM_MODE(x) \ +( ((x) == QSPI_COMM_ROM_ACCESS) || \ + ((x) == QSPI_COMM_DIRECT_COMM)) + +#define IS_QSPI_ADDR_WIDTH(x) \ +( ((x) == QSPI_ADDR_WIDTH_1BYTE) || \ + ((x) == QSPI_ADDR_WIDTH_2BYTE) || \ + ((x) == QSPI_ADDR_WIDTH_3BYTE) || \ + ((x) == QSPI_ADDR_WIDTH_4BYTE)) + +#define IS_QSPI_DUMMY_CYCLES(x) \ +( ((x) >= 3U) && ((x) <= 18U)) + +#define IS_QSPI_INSTR_MODE(x) \ +( ((x) == QSPI_INSTR_1LINE) || \ + ((x) == QSPI_INSTR_2LINE) || \ + ((x) == QSPI_INSTR_4LINE)) + +#define IS_QSPI_ADDR_MODE(x) \ +( ((x) == QSPI_ADDR_1LINE) || \ + ((x) == QSPI_ADDR_2LINE) || \ + ((x) == QSPI_ADDR_4LINE)) + +#define IS_QSPI_DATA_MODE(x) \ +( ((x) == QSPI_DATA_1LINE) || \ + ((x) == QSPI_DATA_2LINE) || \ + ((x) == QSPI_DATA_4LINE)) + +#define IS_QSPI_BLOCK_NUM(x) \ +( (x) <= 62U) + +#define IS_QSPI_PREFETCH_CMD(x) \ +( ((x) == QSPI_PREFETCH_ENABLE) || \ + ((x) == QSPI_PREFETCH_DISABLE)) + +#define IS_QSPI_WP_LEVEL(x) \ +( ((x) == QSPI_WP_LOW) || \ + ((x) == QSPI_WP_HIGH)) + +/** + * @} + */ + +/** + * @defgroup QSPI_Miscellaneous_Macros QSPI Miscellaneous Macros + * @{ + */ +#define QSPI_WORD_TO_BYTE(__word__, __au8__) \ + do { \ + (__au8__)[0U] = (uint8_t)(__word__); \ + (__au8__)[1U] = (uint8_t)((__word__) >> 8U); \ + (__au8__)[2U] = (uint8_t)((__word__) >> 16U); \ + (__au8__)[3U] = (uint8_t)((__word__) >> 24U); \ + } while (0U) + +#define QSPI_ROM_MAP_BASE (0x98000000UL) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup QSPI_Global_Functions QSPI Global Functions + * @{ + */ + +/** + * @brief Initializes QSPI peripheral according to the specified parameters \ + * in the structure stc_qspi_init_t + * @param [in] pstcInit Pointer to a stc_qspi_init_t structure value that \ + * contains the configuration information for QSPI. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t QSPI_Init(const stc_qspi_init_t *pstcInit) +{ + uint32_t u32DutyCorrection = 0U; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + DDL_ASSERT(IS_QSPI_CLK_DIV(pstcInit->u32ClkDiv)); + DDL_ASSERT(IS_QSPI_CS_SETUP_TIMING(pstcInit->u32CSSetupTiming)); + DDL_ASSERT(IS_QSPI_CS_RELEASE_TIMING(pstcInit->u32CSReleaseTiming)); + DDL_ASSERT(IS_QSPI_CS_IDLE_TIME(pstcInit->u32CSIdleTime)); + DDL_ASSERT(IS_QSPI_CS_EXTEND_TIME(pstcInit->u32CSExtendTime)); + DDL_ASSERT(IS_QSPI_SPI_MODE(pstcInit->u32SPIMode)); + DDL_ASSERT(IS_QSPI_PREFETCH_STOP_POSITION(pstcInit->u32PrefetchStopPos)); + DDL_ASSERT(IS_QSPI_PREFETCH_CMD(pstcInit->u32PrefetchCmd)); + DDL_ASSERT(IS_QSPI_WP_LEVEL(pstcInit->u32WPLevel)); + DDL_ASSERT(IS_QSPI_READ_MODE(pstcInit->u32ReadMode)); + DDL_ASSERT(IS_QSPI_COMM_MODE(pstcInit->u32CommMode)); + DDL_ASSERT(IS_QSPI_ADDR_WIDTH(pstcInit->u32AddrWidth)); + DDL_ASSERT(IS_QSPI_DUMMY_CYCLES(pstcInit->u32DummyCycles)); + DDL_ASSERT(IS_QSPI_INSTR_MODE(pstcInit->u32InstrMode)); + DDL_ASSERT(IS_QSPI_ADDR_MODE(pstcInit->u32AddrMode)); + DDL_ASSERT(IS_QSPI_DATA_MODE(pstcInit->u32DataMode)); + + if ((pstcInit->u32ClkDiv & 1UL) != 0UL) + { + u32DutyCorrection = QSPI_FCR_DUTY; + } + + WRITE_REG32(M4_QSPI->CR, (((pstcInit->u32ClkDiv-1UL) << QSPI_CR_DIV_POS) | \ + pstcInit->u32SPIMode | \ + pstcInit->u32PrefetchStopPos | \ + pstcInit->u32PrefetchCmd | \ + pstcInit->u32ReadMode | \ + pstcInit->u32CommMode | \ + pstcInit->u32InstrMode | \ + pstcInit->u32AddrMode | \ + pstcInit->u32DataMode)); + + WRITE_REG32(M4_QSPI->CSCR, (pstcInit->u32CSExtendTime | \ + (pstcInit->u32CSIdleTime-1UL))); + + WRITE_REG32(M4_QSPI->FCR, (pstcInit->u32CSSetupTiming | \ + pstcInit->u32CSReleaseTiming | \ + pstcInit->u32AddrWidth | \ + ((pstcInit->u32DummyCycles-3UL) << QSPI_FCR_DMCYCN_POS) | \ + pstcInit->u32WPLevel | \ + u32DutyCorrection)); + + WRITE_REG32(M4_QSPI->CCMD, pstcInit->u8RomAccessInstr); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initializes QSPI peripheral. Reset the registers of QSPI. + * @param None + * @retval None + */ +void QSPI_DeInit(void) +{ + WRITE_REG32(M4_QSPI->CR, 0x3F0000UL); + WRITE_REG32(M4_QSPI->CSCR, 0xFUL); + WRITE_REG32(M4_QSPI->FCR, 0x80B3UL); + WRITE_REG32(M4_QSPI->SR, 0x8000UL); + WRITE_REG32(M4_QSPI->CCMD, 0x0UL); + WRITE_REG32(M4_QSPI->XCMD, 0xFFUL); + WRITE_REG32(M4_QSPI->SR2, QSPI_FLAG_ROM_ACCESS_ERR); + WRITE_REG32(M4_QSPI->EXAR, 0x0UL); +} + +/** + * @brief Set a default value for QSPI initialization structure. + * @param [in] pstcInit Pointer to a stc_qspi_init_t structure value that \ + * contains the configuration information QSPI. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t QSPI_StructInit(stc_qspi_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + pstcInit->u32ClkDiv = 2UL; + pstcInit->u32CSSetupTiming = QSPI_CS_SETUP_BEFORE_0P5_CYCLE; + pstcInit->u32CSReleaseTiming = QSPI_CS_RELEASE_AFTER_0P5_CYCLE; + pstcInit->u32CSIdleTime = 1UL; + pstcInit->u32CSExtendTime = QSPI_CS_EXTEND_0CYCLE; + pstcInit->u32SPIMode = QSPI_SPI_MODE_0; + pstcInit->u32PrefetchStopPos = QSPI_PREFETCH_STOP_BYTE_EDGE; + pstcInit->u32PrefetchCmd = QSPI_PREFETCH_ENABLE; + pstcInit->u32WPLevel = QSPI_WP_HIGH; + pstcInit->u32CommMode = QSPI_COMM_ROM_ACCESS; + pstcInit->u32AddrWidth = QSPI_ADDR_WIDTH_3BYTE; + pstcInit->u32InstrMode = QSPI_INSTR_1LINE; + pstcInit->u32AddrMode = QSPI_ADDR_1LINE; + pstcInit->u32DataMode = QSPI_DATA_1LINE; + pstcInit->u32ReadMode = QSPI_READ_STANDARD_READ; + pstcInit->u8RomAccessInstr = 0x0U; + pstcInit->u32DummyCycles = 3UL; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief QSPI write data. + * @param [in] u32Instr Instruction. + * @param [in] u32Address Address. + * @param [in] pu8Src Pointer to an array that stores the data to be written. + * @param [in] u32SrcSize Size of the data to be written. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pu8Src == NULL or u32SrcSize == 0U + */ +en_result_t QSPI_WriteData(uint32_t u32Instr, uint32_t u32Address, \ + const uint8_t pu8Src[], uint32_t u32SrcSize) +{ + uint32_t i; + uint8_t au8Address[4U]; + uint32_t u32AddrWidth; + en_result_t enRet = ErrorInvalidParameter; + + if ((pu8Src != NULL) && (u32SrcSize > 0U)) + { + QSPI_WORD_TO_BYTE(u32Address, au8Address); + u32AddrWidth = (READ_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_AWSL) >> QSPI_FCR_AWSL_POS) + 1U; + + /* Enter direct communication mode. */ + QSPI_EnterDirectCommMode(); + /* Send instruction. */ + WRITE_REG32(M4_QSPI->DCOM, u32Instr); + /* Send ROM address. */ + for (i=0U; iDCOM, au8Address[i]); + } + /* Write data at last. */ + for (i=0U; iDCOM, pu8Src[i]); + } + /* Exit direct communication mode. */ + QSPI_ExitDirectCommMode(); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief QSPI write data. + * @param [in] u32Address Address. + * @param [in] pu8Dest Pointer to an array that used to store the read data. + * @param [in] u32DestSize Size of the data to be read. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pu8Dest == NULL or u32DestSize == 0U + */ +en_result_t QSPI_ReadData(uint32_t u32Address, uint8_t pu8Dest[], uint32_t u32DestSize) +{ + uint32_t i = 0U; + en_result_t enRet = ErrorInvalidParameter; + + if ((pu8Dest != NULL) && (u32DestSize > 0U)) + { + u32Address += QSPI_ROM_MAP_BASE; + while (u32DestSize-- != 0U) + { + pu8Dest[i++] = *(uint8_t *)(u32Address++); + } + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Specifies read mode. + * @param [in] u32ReadMode QSPI read mode. + * This parameter can be a value of @ref QSPI_Read_Mode + * @arg QSPI_READ_STANDARD_READ: Standard read mode (no dummy cycles). + * @arg QSPI_READ_FAST_READ: Fast read mode (dummy cycles between address and data). + * @arg QSPI_READ_FAST_READ_DUAL_OUTPUT: Fast read dual output mode (data on 2 lines). + * @arg QSPI_READ_FAST_READ_DUAL_IO: Fast read dual I/O mode (address and data on 2 lines). + * @arg QSPI_READ_FAST_READ_QUAD_OUTPUT: Fast read quad output mode (data on 4 lines). + * @arg QSPI_READ_FAST_READ_QUAD_IO: Fast read quad I/O mode (address and data on 4 lines). + * @arg QSPI_READ_CUSTOM_STANDARD_READ: Custom standard read mode. + * @arg QSPI_READ_CUSTOM_FAST_READ: Custom fast read mode. + * @param [in] u8ReadInstr Read instruction of QSPI flash. Tis instruction must correspond to the read mode that specified by parameter 'u32ReadMode'. + * @param [in] u32DummyCycles The number of dummy cycles for fast read. It must correspond to the QSPI flash read instruction. + * Ignore when u32ReadMode == QSPI_READ_STANDARD_READ. + * This parameter can be a value between 3U and 18U, inclusive. + * @retval None + */ +void QSPI_SetReadMode(uint32_t u32ReadMode, uint8_t u8ReadInstr, uint32_t u32DummyCycles) +{ + DDL_ASSERT(IS_QSPI_READ_MODE(u32ReadMode)); + DDL_ASSERT(IS_QSPI_DUMMY_CYCLES(u32DummyCycles)); + + MODIFY_REG32(M4_QSPI->FCR, QSPI_FCR_DMCYCN, (u32DummyCycles-3UL) << QSPI_FCR_DMCYCN_POS); + MODIFY_REG32(M4_QSPI->CR, QSPI_CR_MDSEL, u32ReadMode); + WRITE_REG32(M4_QSPI->CCMD, u8ReadInstr); +} + +/** + * @brief Enable or disable duty correction. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable duty correction. + * @arg Disable: Disable duty correction. + * @retval None + */ +void QSPI_DutyCorrectCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState == Enable) + { + SET_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_DUTY); + } + else + { + CLEAR_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_DUTY); + } +} + +/** + * @brief Enable or disable prefetch function. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable prefetch function. + * @arg Disable: Disable prefetch function. + * @retval None + */ +void QSPI_PrefetchCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState == Enable) + { + SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_PFE); + } + else + { + CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_PFE); + } +} + +/** + * @brief Enable or disable XIP mode. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable XIP mode. + * @arg Disable: Disable XIP mode. + * @retval None + */ +void QSPI_XIPModeCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState == Enable) + { + SET_REG32_BIT(M4_QSPI->CR, QSPI_CR_XIPE); + } + else + { + CLEAR_REG32_BIT(M4_QSPI->CR, QSPI_CR_XIPE); + } +} + +/** + * @brief Specifies the level of WP. + * @param [in] u32Level The level of WP. + * This parameter can be a value of @ref QSPI_WP_Level + * @arg QSPI_WP_LOW: Set WP output low. + * @arg QSPI_WP_HIGH: Set WP output high. + * @retval None + */ +void QSPI_SetWPPinLevel(uint32_t u32Level) +{ + DDL_ASSERT(IS_QSPI_WP_LEVEL(u32Level)); + MODIFY_REG32(M4_QSPI->FCR, QSPI_FCR_WPOL, u32Level); +} + +/** + * @brief Enable or disable 4-byte address mode. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable 4-byte address mode. + * @arg Disable: Disable 4-byte address mode. + * @retval None + */ +void QSPI_4ByteAddrModeCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState == Enable) + { + SET_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_FOUR_BIC); + } + else + { + CLEAR_REG32_BIT(M4_QSPI->FCR, QSPI_FCR_FOUR_BIC); + } +} + +/** + * @brief Selects the block to access. + * @param [in] u32Block External block. A number between 0U and 62U, inclusive. + * @retval None + */ +void QSPI_SelectBlock(uint32_t u32Block) +{ + DDL_ASSERT(IS_QSPI_BLOCK_NUM(u32Block)); + WRITE_REG32(M4_QSPI->EXAR, ((u32Block << QSPI_EXAR_EXADR_POS) & QSPI_EXAR_EXADR)); +} + +/** + * @brief Get the size of prefetched data. + * @param None + * @retval A number between 0U and 18U, inclusive. + */ +uint32_t QSPI_GetPrefetchedSize(void) +{ + return READ_REG32_BIT(M4_QSPI->SR, QSPI_SR_PFNUM) >> QSPI_SR_PFNUM_POS; +} + +/** + * @brief Get the status of the specified QSPI flags. + * @param [in] u32Flag The status flags of QSPI. + * This parameter can be values of @ref QSPI_Status_Flag + * @arg QSPI_FLAG_DIRECT_COMM_BUSY: Serial transfer being processed. + * @arg QSPI_FLAG_XIP_MODE: XIP mode. + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode. + * @arg QSPI_FLAG_PREFETCH_BUF_FULL: Prefetch buffer is full. + * @arg QSPI_FLAG_PREFETCH_ACTIVE: Prefetch function operating. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified flags is set. + * @arg Reset: None of the specified flags is set. + */ +en_flag_status_t QSPI_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlag = Reset; + + if (READ_REG32_BIT(M4_QSPI->SR, (u32Flag & QSPI_FLAG_ALL)) != 0UL) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief Clear the specified flag. + * @param [in] u32Flag The specified flags to be cleared. + * This parameter can only be the following: + * @arg QSPI_FLAG_ROM_ACCESS_ERR: ROM access detection status in direct communication mode. + * @retval None + */ +void QSPI_ClrStatus(uint32_t u32Flag) +{ + SET_REG32_BIT(M4_QSPI->SR2, (u32Flag & QSPI_FLAG_CLR_MSK)); +} + +/** + * @} + */ + +#endif /* DDL_QSPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rmu.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rmu.c new file mode 100644 index 0000000000000000000000000000000000000000..900893f7da48e616cb876f04fb327a486ad0d1f1 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rmu.c @@ -0,0 +1,171 @@ +/** + ******************************************************************************* + * @file hc32f4a0_rmu.c + * @brief This file provides firmware functions to manage the Reset Manage Unit + * (RMU). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + 2020-07-21 Heqb Add write protect check for RMU_ClrStatus function + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_rmu.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_RMU RMU + * @brief RMU Driver Library + * @{ + */ + +#if (DDL_RMU_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RMU_Local_Macros RMU Local Macros + * @{ + */ +#define RMU_STATUS_MASK (0x40007FFFUL) + +/** + * @defgroup RMU_Check_Parameters_Validity RMU Check Parameters Validity + * @{ + */ + +/*! Parameter validity check for RMU reset cause. */ +#define IS_VALID_RMU_RESET_STATUS(x) \ +( ((x) != 0U) || \ + ((x) | RMU_STATUS_MASK) == RMU_STATUS_MASK) + +/** + * @} + */ + +/** + * @} + */ +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RMU_Global_Functions RMU Global Functions + * @{ + */ + +/** + * @brief Get the reset cause. + * @param [in] u32RmuResetCause Reset flags that need to be queried + * @arg RMU_RST_POWER_ON: Power on reset + * @arg RMU_RST_RESET_PIN: Reset pin reset + * @arg RMU_RST_BROWN_OUT: Brown-out reset + * @arg RMU_RST_PVD1: Program voltage Detection 1 reset + * @arg RMU_RST_PVD2: Program voltage Detection 2 reset + * @arg RMU_RST_WDT: Watchdog timer reset + * @arg RMU_RST_SWDT: Special watchdog timer reset + * @arg RMU_RST_POWER_DOWN: Power down reset + * @arg RMU_RST_SOFTWARE: Software reset + * @arg RMU_RST_MPU_ERR: Mpu error reset + * @arg RMU_RST_RAM_PARITY_ERR: Ram parity error reset + * @arg RMU_RST_RAM_ECC: Ram ECC reset + * @arg RMU_RST_CLK_ERR: Clk frequence error reset + * @arg RMU_RST_XTAL_ERR: Xtal error reset + * @arg RMU_RST_LOCKUP: M4 Lockup reset + * @arg RMU_RST_MULTI: Multiply reset cause + * @retval Set: Flag is Set. + * Reset: Flag is Reset + */ +en_flag_status_t RMU_GetStatus(uint32_t u32RmuResetCause) +{ + en_flag_status_t enRet; + DDL_ASSERT(IS_VALID_RMU_RESET_STATUS(u32RmuResetCause)); + + enRet = ((0UL == READ_REG32_BIT(M4_RMU->RSTF0, u32RmuResetCause)) ? Reset :Set); + return enRet; +} + +/** + * @brief Clear reset Status. + * @param None + * @retval NOne + * @note Clear reset flag should be done after read RMU_RSTF0 register. + * Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_RSTF0 register first. + */ +void RMU_ClrStatus(void) +{ + DDL_ASSERT((M4_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + + SET_REG32_BIT(M4_RMU->RSTF0, RMU_RSTF0_CLRF); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); + __NOP(); +} + +/** + * @brief Enable or disable LOCKUP reset. + * @param [in] enNewState Enable or disable LOCKUP reset. + * @retval None + * @note Call PWC_Unlock(PWC_UNLOCK_CODE_1) unlock RMU_PRSTCR0 register first. + */ +void RMU_CPULockUpCmd(en_functional_state_t enNewState) +{ + DDL_ASSERT((M4_PWC->FPRC & PWC_FPRC_FPRCB1) == PWC_FPRC_FPRCB1); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + WRITE_REG8(bM4_RMU->PRSTCR0_b.LKUPREN, enNewState); +} + +/** + * @} + */ + +#endif /* DDL_RMU_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rtc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..e08aa40a15a31ad0475d90f5541e0258499eb0a4 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rtc.c @@ -0,0 +1,1240 @@ +/** + ******************************************************************************* + * @file hc32f4a0_rtc.c + * @brief This file provides firmware functions to manage the Real-Time + * Clock(RTC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-09-04 Yangjp Optimize timeout handling in functions + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_rtc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_RTC RTC + * @brief Real-Time Clock Driver Library + * @{ + */ + +#if (DDL_RTC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup RTC_Local_Macros RTC Local Macros + * @{ + */ + +/* RTC TPCR register Mask */ +#define RTC_TPCR_CLEAR_MASK (RTC_TPCR0_TPCT0 | RTC_TPCR0_TPNF0 | \ + RTC_TPCR0_TPRSTE0 | RTC_TPCR0_TSTPE0) + +/* Get the specified register address of the RTC Intrusion Control */ +#define RTC_TPCRx(__CH__) ((uint32_t)(&(M4_RTC->TPCR0)) + (uint32_t)(__CH__)) + +/* RTC software reset timeout(ms) */ +#define RTC_SOFTWARE_RESET_TIMEOUT (100UL) + +/* RTC mode switch timeout(ms) */ +#define RTC_MODE_SWITCH_TIMEOUT (100UL) + +/** + * @defgroup RTC_Check_Parameters_Validity RTC Check Parameters Validity + * @{ + */ +#define IS_RTC_DATA_FORMAT(x) \ +( ((x) == RTC_DATA_FORMAT_DEC) || \ + ((x) == RTC_DATA_FORMAT_BCD)) + +#define IS_RTC_CLOCK_SOURCE(x) \ +( ((x) == RTC_CLOCK_SOURCE_XTAL32) || \ + ((x) == RTC_CLOCK_SOURCE_RTCLRC)) + +#define IS_RTC_HOUR_FORMAT(x) \ +( ((x) == RTC_HOUR_FORMAT_12) || \ + ((x) == RTC_HOUR_FORMAT_24)) + +#define IS_RTC_PERIOD_INTERRUPT(x) \ +( ((x) == RTC_PERIOD_INT_INVALID) || \ + ((x) == RTC_PERIOD_INT_HALF_SECOND) || \ + ((x) == RTC_PERIOD_INT_ONE_SECOND) || \ + ((x) == RTC_PERIOD_INT_ONE_MINUTE) || \ + ((x) == RTC_PERIOD_INT_ONE_HOUR) || \ + ((x) == RTC_PERIOD_INT_ONE_DAY) || \ + ((x) == RTC_PERIOD_INT_ONE_MONTH)) + +#define IS_RTC_CLOCK_COMPEN(x) \ +( ((x) == RTC_CLOCK_COMPEN_DISABLE) || \ + ((x) == RTC_CLOCK_COMPEN_ENABLE)) + +#define IS_RTC_OUTPUT_COMPEN_MODE(x) \ +( ((x) == RTC_OUTPUT_COMPEN_MODE_DISTRIBUTED) || \ + ((x) == RTC_OUTPUT_COMPEN_MODE_UNIFORM)) + +#define IS_RTC_HOUR12_AM_PM(x) \ +( ((x) == RTC_HOUR12_AM_HOUR24) || \ + ((x) == RTC_HOUR12_PM)) + +#define IS_RTC_INTRUSION_CHANNEL(x) \ +( ((x) == RTC_INTRU_CH0) || \ + ((x) == RTC_INTRU_CH1)) + +#define IS_RTC_INTRUSION_TIMESTAMP(x) \ +( ((x) == RTC_INTRU_TIMESTAMP_DISABLE) || \ + ((x) == RTC_INTRU_TIMESTAMP_ENABLE)) + +#define IS_RTC_RESET_BACKUP_REGISTER(x) \ +( ((x) == RTC_RESET_BACKUP_REG_DISABLE) || \ + ((x) == RTC_RESET_BACKUP_REG_ENABLE)) + +#define IS_RTC_INTRUSION_FILTER(x) \ +( ((x) == RTC_INTRU_FILTER_INVALID) || \ + ((x) == RTC_INTRU_FILTER_THREE_TIME) || \ + ((x) == RTC_INTRU_FILTER_THREE_TIME_CLK_DIV32)) + +#define IS_RTC_INTRUSION_DETECT_EDGE(x) \ +( ((x) == RTC_DETECT_EDGE_NONE) || \ + ((x) == RTC_DETECT_EDGE_RISING) || \ + ((x) == RTC_DETECT_EDGE_FALLING) || \ + ((x) == RTC_DETECT_EDGE_RISING_FALLING)) + +#define IS_RTC_GET_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(RTC_FLAG_PRDF | \ + RTC_FLAG_ALMF | \ + RTC_FLAG_RWEN | \ + RTC_FLAG_TPOVF | \ + RTC_FLAG_TPF0 | \ + RTC_FLAG_TPF1)))))) + +#define IS_RTC_CLEAR_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(RTC_FLAG_PRDF | \ + RTC_FLAG_ALMF | \ + RTC_FLAG_TPOVF | \ + RTC_FLAG_TPF0 | \ + RTC_FLAG_TPF1)))))) + +#define IS_RTC_INTERRUPT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(RTC_INT_PRDIE | \ + RTC_INT_ALMIE | \ + RTC_INT_TPIE0 | \ + RTC_INT_TPIE1)))))) + +#define IS_RTC_YEAR(x) ((x) <= 99U) + +#define IS_RTC_MONTH(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_DAY(x) (((x) >= 1U) && ((x) <= 31U)) + +#define IS_RTC_HOUR12(x) (((x) >= 1U) && ((x) <= 12U)) + +#define IS_RTC_HOUR24(x) ((x) <= 23U) + +#define IS_RTC_MINUTE(x) ((x) <= 59U) + +#define IS_RTC_SECOND(x) ((x) <= 59U) + +#define IS_RTC_WEEKDAY(x) ((x) <= 6U) + +#define IS_RTC_ALARM_WEEKDAY(x) (((x) >= 0x01U) && ((x) <= 0x7FU)) + +#define IS_RTC_COMPENSATION_VALUE(x) ((x) <= 0x1FFU) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup RTC_Global_Functions RTC Global Functions + * @{ + */ + +/** + * @brief De-Initialize RTC. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: De-Initialize success + * - ErrorTimeout: De-Initialize timeout + */ +en_result_t RTC_DeInit(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + WRITE_REG32(bM4_RTC->CR0_b.RESET, Reset); + /* Waiting for normal count status or end of RTC software reset */ + u32Count = RTC_SOFTWARE_RESET_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_RTC->CR0_b.RESET)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (Ok == enRet) + { + /* Reset all RTC registers */ + WRITE_REG32(bM4_RTC->CR0_b.RESET, Set); + /* Waiting for RTC software reset to complete */ + u32Count = RTC_SOFTWARE_RESET_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_RTC->CR0_b.RESET)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + } + + return enRet; +} + +/** + * @brief Initialize RTC. + * @param [in] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_Init(const stc_rtc_init_t *pstcRtcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLOCK_SOURCE(pstcRtcInit->u8ClockSource)); + DDL_ASSERT(IS_RTC_HOUR_FORMAT(pstcRtcInit->u8HourFormat)); + DDL_ASSERT(IS_RTC_PERIOD_INTERRUPT(pstcRtcInit->u8PeriodInterrupt)); + DDL_ASSERT(IS_RTC_CLOCK_COMPEN(pstcRtcInit->u8ClkCompenEn)); + DDL_ASSERT(IS_RTC_COMPENSATION_VALUE(pstcRtcInit->u16ClkCompenValue)); + DDL_ASSERT(IS_RTC_OUTPUT_COMPEN_MODE(pstcRtcInit->u8CompenMode)); + + /* RTC CR3 Configuration */ + MODIFY_REG8(M4_RTC->CR3, (RTC_CR3_LRCEN | RTC_CR3_RCKSEL), pstcRtcInit->u8ClockSource); + /* RTC CR1 Configuration */ + MODIFY_REG8(M4_RTC->CR1, (RTC_CR1_PRDS | RTC_CR1_AMPM | RTC_CR1_ONEHZSEL), + (pstcRtcInit->u8PeriodInterrupt | pstcRtcInit->u8HourFormat | pstcRtcInit->u8CompenMode)); + /* RTC Compensation Configuration */ + MODIFY_REG8(M4_RTC->ERRCRH, (RTC_ERRCRH_COMPEN | RTC_ERRCRH_COMP8), + (pstcRtcInit->u8ClkCompenEn | (uint8_t)((pstcRtcInit->u16ClkCompenValue >> 8U) & 0x01U))); + WRITE_REG8(M4_RTC->ERRCRL, (uint8_t)(pstcRtcInit->u16ClkCompenValue & 0xFFU)); + } + + return enRet; +} + +/** + * @brief Fills each stc_rtc_init_t member with default value. + * @param [out] pstcRtcInit Pointer to a @ref stc_rtc_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: stc_rtc_init_t member initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_StructInit(stc_rtc_init_t *pstcRtcInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcRtcInit->u8ClockSource = RTC_CLOCK_SOURCE_RTCLRC; + pstcRtcInit->u8HourFormat = RTC_HOUR_FORMAT_24; + pstcRtcInit->u8PeriodInterrupt = RTC_PERIOD_INT_INVALID; + pstcRtcInit->u8ClkCompenEn = RTC_CLOCK_COMPEN_DISABLE; + pstcRtcInit->u16ClkCompenValue = 0U; + pstcRtcInit->u8CompenMode = RTC_OUTPUT_COMPEN_MODE_DISTRIBUTED; + } + + return enRet; +} + +/** + * @brief Enter RTC read/write mode. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Enter mode success + * - ErrorTimeout: Enter mode timeout + */ +en_result_t RTC_EnterRwMode(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bM4_RTC->CR1_b.START)) + { + if (1UL != READ_REG32(bM4_RTC->CR2_b.RWEN)) + { + WRITE_REG32(bM4_RTC->CR2_b.RWREQ, Set); + /* Waiting for RWEN bit set */ + u32Count = RTC_MODE_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bM4_RTC->CR2_b.RWEN)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + } + } + + return enRet; +} + +/** + * @brief Exit RTC read/write mode. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Exit mode success + * - ErrorTimeout: Exit mode timeout + */ +en_result_t RTC_ExitRwMode(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + /* Mode switch when RTC is running */ + if (0UL != READ_REG32(bM4_RTC->CR1_b.START)) + { + if (0UL != READ_REG32(bM4_RTC->CR2_b.RWEN)) + { + WRITE_REG32(bM4_RTC->CR2_b.RWREQ, Reset); + /* Waiting for RWEN bit reset */ + u32Count = RTC_MODE_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_RTC->CR2_b.RWEN)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + } + } + + return enRet; +} + +/** + * @brief RTC period interrupt config. + * @param [in] u8IntCond Specifies the period interrupt type + * This parameter can be one of the following values: + * @arg RTC_PERIOD_INT_INVALID: Period interrupt invalid + * @arg RTC_PERIOD_INT_HALF_SECOND: 0.5 second period interrupt + * @arg RTC_PERIOD_INT_ONE_SECOND: 1 second period interrupt + * @arg RTC_PERIOD_INT_ONE_MINUTE: 1 minute period interrupt + * @arg RTC_PERIOD_INT_ONE_HOUR: 1 hour period interrupt + * @arg RTC_PERIOD_INT_ONE_DAY: 1 day period interrupt + * @arg RTC_PERIOD_INT_ONE_MONTH: 1 month period interrupt + * @retval None + */ +void RTC_PeriodIntConfig(uint8_t u8IntCond) +{ + uint32_t u32RtcSta; + uint32_t u32IntSta; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_PERIOD_INTERRUPT(u8IntCond)); + + u32RtcSta = READ_REG32(bM4_RTC->CR1_b.START); + u32IntSta = READ_REG32(bM4_RTC->CR2_b.PRDIE); + /* Disable period interrupt when START=1 and clear period flag after write */ + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) + { + WRITE_REG32(bM4_RTC->CR2_b.PRDIE, Reset); + } + + /* RTC CR1 Configuration */ + MODIFY_REG8(M4_RTC->CR1, RTC_CR1_PRDS, u8IntCond); + WRITE_REG32(bM4_RTC->CR2_b.PRDF, Reset); + + if ((0UL != u32IntSta) && (0UL != u32RtcSta)) + { + WRITE_REG32(bM4_RTC->CR2_b.PRDIE, Set); + } +} + +/** + * @brief RTC enter low power condition check. + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Can enter low power mode + * - ErrorTimeout: Can't enter low power mode + */ +en_result_t RTC_LowPowerCheck(void) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + /* Check RTC work status */ + if (0UL != READ_REG32(bM4_RTC->CR1_b.START)) + { + WRITE_REG32(bM4_RTC->CR2_b.RWREQ, Set); + /* Waiting for RTC RWEN bit set */ + u32Count = RTC_MODE_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (1UL != READ_REG32(bM4_RTC->CR2_b.RWEN)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (Ok == enRet) + { + WRITE_REG32(bM4_RTC->CR2_b.RWREQ, Reset); + /* Waiting for RTC RWEN bit reset */ + u32Count = RTC_MODE_SWITCH_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32(bM4_RTC->CR2_b.RWEN)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + } + } + + return enRet; +} + +/** + * @brief Set RTC clock compensation value. + * @param [in] u16CompenVal Specifies the clock compensation value of RTC. + * @arg This parameter can be a number between Min_Data = 0 and Max_Data = 0x1FF. + * @retval None + */ +void RTC_SetClkCompenValue(uint16_t u16CompenVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_COMPENSATION_VALUE(u16CompenVal)); + + WRITE_REG32(bM4_RTC->ERRCRH_b.COMP8, ((uint32_t)u16CompenVal >> 8U) & 0x01U); + WRITE_REG8(M4_RTC->ERRCRL, (uint8_t)(u16CompenVal & 0x00FFU)); +} + +/** + * @brief Enable or disable RTC count. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_Cmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_RTC->CR1_b.START, enNewSta); +} + +/** + * @brief Enable or disable RTC LRC function. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_LrcCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_RTC->CR3_b.LRCEN, enNewSta); +} + +/** + * @brief Get RTC counter status. + * @param None + * @retval An en_result_t enumeration value: + * - Enable: RTC counter started + * - Disable: RTC counter stopped + */ +en_functional_state_t RTC_GetCounterState(void) +{ + en_functional_state_t enState; + + if (0UL != READ_REG32(bM4_RTC->CR1_b.START)) + { + enState = Enable; + } + else + { + enState = Disable; + } + + return enState; +} + +/** + * @brief Enable or disable RTC 1HZ output. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_OneHzOutputCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_RTC->CR1_b.ONEHZOE, enNewSta); +} + +/** + * @brief Enable or disable clock compensation. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_ClkCompenCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_RTC->ERRCRH_b.COMPEN, enNewSta); +} + +/** + * @brief Set RTC current date. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [in] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval An en_result_t enumeration value: + * - Ok: Set date success + * - Error: Set date failed + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_SetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcDate) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + if (RTC_DATA_FORMAT_DEC != u8Format) + { + DDL_ASSERT(IS_RTC_YEAR(BCD2DEC(pstcRtcDate->u8Year))); + DDL_ASSERT(IS_RTC_MONTH(BCD2DEC(pstcRtcDate->u8Month))); + DDL_ASSERT(IS_RTC_DAY(BCD2DEC(pstcRtcDate->u8Day))); + } + else + { + DDL_ASSERT(IS_RTC_YEAR(pstcRtcDate->u8Year)); + DDL_ASSERT(IS_RTC_MONTH(pstcRtcDate->u8Month)); + DDL_ASSERT(IS_RTC_DAY(pstcRtcDate->u8Day)); + } + DDL_ASSERT(IS_RTC_WEEKDAY(pstcRtcDate->u8Weekday)); + + /* Enter read/write mode */ + if (Ok != RTC_EnterRwMode()) + { + enRet = Error; + } + else + { + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcRtcDate->u8Year = DEC2BCD(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = DEC2BCD(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = DEC2BCD(pstcRtcDate->u8Day); + } + + WRITE_REG8(M4_RTC->YEAR, pstcRtcDate->u8Year); + WRITE_REG8(M4_RTC->MON, pstcRtcDate->u8Month); + WRITE_REG8(M4_RTC->DAY, pstcRtcDate->u8Day); + WRITE_REG8(M4_RTC->WEEK, pstcRtcDate->u8Weekday); + + /* Exit read/write mode */ + if (Ok != RTC_ExitRwMode()) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + * @brief Get RTC current date. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [out] pstcRtcDate Pointer to a @ref stc_rtc_date_t structure + * @retval An en_result_t enumeration value: + * - Ok: Get date success + * - Error: Get date failed + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_GetDate(uint8_t u8Format, stc_rtc_date_t *pstcRtcDate) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcDate) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + /* Enter read/write mode */ + if (Ok != RTC_EnterRwMode()) + { + enRet = Error; + } + else + { + /* Get RTC date registers */ + pstcRtcDate->u8Year = READ_REG8(M4_RTC->YEAR); + pstcRtcDate->u8Month = READ_REG8(M4_RTC->MON); + pstcRtcDate->u8Day = READ_REG8(M4_RTC->DAY); + pstcRtcDate->u8Weekday = READ_REG8(M4_RTC->WEEK); + + /* Check decimal format*/ + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcRtcDate->u8Year = BCD2DEC(pstcRtcDate->u8Year); + pstcRtcDate->u8Month = BCD2DEC(pstcRtcDate->u8Month); + pstcRtcDate->u8Day = BCD2DEC(pstcRtcDate->u8Day); + } + + /* exit read/write mode */ + if (Ok != RTC_ExitRwMode()) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + * @brief Set RTC current time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [in] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval An en_result_t enumeration value: + * - Ok: Set time success + * - Error: Set time failed + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_SetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcTime) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + if (RTC_DATA_FORMAT_DEC != u8Format) + { + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + DDL_ASSERT(IS_RTC_HOUR12(BCD2DEC(pstcRtcTime->u8Hour))); + DDL_ASSERT(IS_RTC_HOUR12_AM_PM(pstcRtcTime->u8AmPm)); + } + else + { + DDL_ASSERT(IS_RTC_HOUR24(BCD2DEC(pstcRtcTime->u8Hour))); + } + DDL_ASSERT(IS_RTC_MINUTE(BCD2DEC(pstcRtcTime->u8Minute))); + DDL_ASSERT(IS_RTC_SECOND(BCD2DEC(pstcRtcTime->u8Second))); + } + else + { + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + DDL_ASSERT(IS_RTC_HOUR12(pstcRtcTime->u8Hour)); + DDL_ASSERT(IS_RTC_HOUR12_AM_PM(pstcRtcTime->u8AmPm)); + } + else + { + DDL_ASSERT(IS_RTC_HOUR24(pstcRtcTime->u8Hour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcTime->u8Minute)); + DDL_ASSERT(IS_RTC_SECOND(pstcRtcTime->u8Second)); + } + + /* Enter read/write mode */ + if (Ok != RTC_EnterRwMode()) + { + enRet = Error; + } + else + { + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcRtcTime->u8Hour = DEC2BCD(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = DEC2BCD(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = DEC2BCD(pstcRtcTime->u8Second); + } + if ((RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) && + (RTC_HOUR12_PM == pstcRtcTime->u8AmPm)) + { + pstcRtcTime->u8Hour |= RTC_HOUR12_PM; + } + + WRITE_REG8(M4_RTC->HOUR, pstcRtcTime->u8Hour); + WRITE_REG8(M4_RTC->MIN, pstcRtcTime->u8Minute); + WRITE_REG8(M4_RTC->SEC, pstcRtcTime->u8Second); + + /* Exit read/write mode */ + if (Ok != RTC_ExitRwMode()) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + * @brief Get RTC current time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [out] pstcRtcTime Pointer to a @ref stc_rtc_time_t structure + * @retval An en_result_t enumeration value: + * - Ok: Get time success + * - Error: Get time failed + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_GetTime(uint8_t u8Format, stc_rtc_time_t *pstcRtcTime) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcTime) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + /* Enter read/write mode */ + if (Ok != RTC_EnterRwMode()) + { + enRet = Error; + } + else + { + /* Get RTC time registers */ + pstcRtcTime->u8Hour = READ_REG8(M4_RTC->HOUR); + pstcRtcTime->u8Minute = READ_REG8(M4_RTC->MIN); + pstcRtcTime->u8Second = READ_REG8(M4_RTC->SEC); + + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + if (RTC_HOUR12_PM == (pstcRtcTime->u8Hour & RTC_HOUR12_PM)) + { + pstcRtcTime->u8Hour &= (uint8_t)(~RTC_HOUR12_PM); + pstcRtcTime->u8AmPm = RTC_HOUR12_PM; + } + else + { + pstcRtcTime->u8AmPm = RTC_HOUR12_AM_HOUR24; + } + } + else + { + pstcRtcTime->u8AmPm = RTC_HOUR12_AM_HOUR24; + } + + /* Check decimal format*/ + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcRtcTime->u8Hour = BCD2DEC(pstcRtcTime->u8Hour); + pstcRtcTime->u8Minute = BCD2DEC(pstcRtcTime->u8Minute); + pstcRtcTime->u8Second = BCD2DEC(pstcRtcTime->u8Second); + } + + /* exit read/write mode */ + if (Ok != RTC_ExitRwMode()) + { + enRet = Error; + } + } + } + + return enRet; +} + +/** + * @brief Set RTC alarm time. + * @param [in] u8Format Specifies the format of the entered parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [in] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval An en_result_t enumeration value: + * - Ok: Set RTC alarm time success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_SetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcAlarm) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + if (RTC_DATA_FORMAT_DEC != u8Format) + { + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + DDL_ASSERT(IS_RTC_HOUR12(BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + DDL_ASSERT(IS_RTC_HOUR12_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } + else + { + DDL_ASSERT(IS_RTC_HOUR24(BCD2DEC(pstcRtcAlarm->u8AlarmHour))); + } + DDL_ASSERT(IS_RTC_MINUTE(BCD2DEC(pstcRtcAlarm->u8AlarmMinute))); + } + else + { + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + DDL_ASSERT(IS_RTC_HOUR12(pstcRtcAlarm->u8AlarmHour)); + DDL_ASSERT(IS_RTC_HOUR12_AM_PM(pstcRtcAlarm->u8AlarmAmPm)); + } + else + { + DDL_ASSERT(IS_RTC_HOUR24(pstcRtcAlarm->u8AlarmHour)); + } + DDL_ASSERT(IS_RTC_MINUTE(pstcRtcAlarm->u8AlarmMinute)); + } + DDL_ASSERT(IS_RTC_ALARM_WEEKDAY(pstcRtcAlarm->u8AlarmWeekday)); + + /* Configure alarm registers */ + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcRtcAlarm->u8AlarmHour = DEC2BCD(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = DEC2BCD(pstcRtcAlarm->u8AlarmMinute); + } + if ((RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) && + (RTC_HOUR12_PM == pstcRtcAlarm->u8AlarmAmPm)) + { + pstcRtcAlarm->u8AlarmHour |= RTC_HOUR12_PM; + } + + WRITE_REG8(M4_RTC->ALMHOUR, pstcRtcAlarm->u8AlarmHour); + WRITE_REG8(M4_RTC->ALMMIN, pstcRtcAlarm->u8AlarmMinute); + WRITE_REG8(M4_RTC->ALMWEEK, pstcRtcAlarm->u8AlarmWeekday); + } + + return enRet; +} + +/** + * @brief Get RTC alarm time. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [out] pstcRtcAlarm Pointer to a @ref stc_rtc_alarm_t structure + * @retval An en_result_t enumeration value: + * - Ok: Get RTC alarm time success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_GetAlarm(uint8_t u8Format, stc_rtc_alarm_t *pstcRtcAlarm) +{ + en_result_t enRet = Ok; + + if (NULL == pstcRtcAlarm) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + + /* Get RTC date and time register */ + pstcRtcAlarm->u8AlarmWeekday = READ_REG8(M4_RTC->ALMWEEK); + pstcRtcAlarm->u8AlarmMinute = READ_REG8(M4_RTC->ALMMIN); + pstcRtcAlarm->u8AlarmHour = READ_REG8(M4_RTC->ALMHOUR); + + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + if (RTC_HOUR12_PM == (pstcRtcAlarm->u8AlarmHour & RTC_HOUR12_PM)) + { + pstcRtcAlarm->u8AlarmHour &= (uint8_t)(~RTC_HOUR12_PM); + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR12_PM; + } + else + { + pstcRtcAlarm->u8AlarmAmPm = RTC_HOUR12_AM_HOUR24; + } + } + + /* Check decimal format*/ + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcRtcAlarm->u8AlarmHour = BCD2DEC(pstcRtcAlarm->u8AlarmHour); + pstcRtcAlarm->u8AlarmMinute = BCD2DEC(pstcRtcAlarm->u8AlarmMinute); + } + } + + return enRet; +} + +/** + * @brief Enable or disable RTC alarm. + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_AlarmCmd(en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + WRITE_REG32(bM4_RTC->CR2_b.ALME, enNewSta); +} + +/** + * @brief Configure RTC intrusion function. + * @param [in] u8Ch Specifies the RTC intrusion channel. + * This parameter can be one of the following values: + * @arg RTC_INTRU_CH0: Intrusion channel 0 + * @arg RTC_INTRU_CH1: Intrusion channel 1 + * @param [in] pstcIntru Pointer to a @ref stc_rtc_intrusion_t structure + * @retval An en_result_t enumeration value: + * - Ok: Configure RTC intrusion function success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_IntrusionConfig(uint8_t u8Ch, const stc_rtc_intrusion_t *pstcIntru) +{ + en_result_t enRet = Ok; + __IO uint8_t *TPCR; + + if (NULL == pstcIntru) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_INTRUSION_CHANNEL(u8Ch)); + DDL_ASSERT(IS_RTC_INTRUSION_TIMESTAMP(pstcIntru->u8TimeStampEn)); + DDL_ASSERT(IS_RTC_RESET_BACKUP_REGISTER(pstcIntru->u8ResetBackupRegEn)); + DDL_ASSERT(IS_RTC_INTRUSION_FILTER(pstcIntru->u8Filter)); + DDL_ASSERT(IS_RTC_INTRUSION_DETECT_EDGE(pstcIntru->u8TrigEdge)); + + TPCR = (__IO uint8_t *)RTC_TPCRx(u8Ch); + /* RTC Intrusion control Configuration */ + MODIFY_REG8(*TPCR, RTC_TPCR_CLEAR_MASK, + (pstcIntru->u8TimeStampEn | pstcIntru->u8ResetBackupRegEn | + pstcIntru->u8Filter | pstcIntru->u8TrigEdge)); + } + + return enRet; +} + +/** + * @brief Get RTC intrusion timestamp. + * @param [in] u8Format Specifies the format of the returned parameters. + * This parameter can be one of the following values: + * @arg RTC_DATA_FORMAT_DEC: Decimal data format + * @arg RTC_DATA_FORMAT_BCD: BCD data format + * @param [out] pstcTimestamp Pointer to a @ref stc_rtc_timestamp_t structure + * @retval An en_result_t enumeration value: + * - Ok: Get RTC intrusion timestamp success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t RTC_GetIntrusionTimestamp(uint8_t u8Format, stc_rtc_timestamp_t *pstcTimestamp) +{ + en_result_t enRet = Ok; + + if (NULL == pstcTimestamp) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_RTC_DATA_FORMAT(u8Format)); + + /* Get RTC Timestamp registers */ + pstcTimestamp->stcTSTime.u8Hour = READ_REG8(M4_RTC->HOURTP); + pstcTimestamp->stcTSTime.u8Minute = READ_REG8(M4_RTC->MINTP); + pstcTimestamp->stcTSTime.u8Second = READ_REG8(M4_RTC->SECTP); + pstcTimestamp->u8TSMonth = READ_REG8(M4_RTC->MONTP); + pstcTimestamp->u8TSDay = READ_REG8(M4_RTC->DAYTP); + + if (RTC_HOUR_FORMAT_12 == READ_REG32(bM4_RTC->CR1_b.AMPM)) + { + if (RTC_HOUR12_PM == (pstcTimestamp->stcTSTime.u8Hour & RTC_HOUR12_PM)) + { + pstcTimestamp->stcTSTime.u8Hour &= (uint8_t)(~RTC_HOUR12_PM); + pstcTimestamp->stcTSTime.u8AmPm = RTC_HOUR12_PM; + } + else + { + pstcTimestamp->stcTSTime.u8AmPm = RTC_HOUR12_AM_HOUR24; + } + } + else + { + pstcTimestamp->stcTSTime.u8AmPm = RTC_HOUR12_AM_HOUR24; + } + + /* Check decimal format*/ + if (RTC_DATA_FORMAT_DEC == u8Format) + { + pstcTimestamp->stcTSTime.u8Hour = BCD2DEC(pstcTimestamp->stcTSTime.u8Hour); + pstcTimestamp->stcTSTime.u8Minute = BCD2DEC(pstcTimestamp->stcTSTime.u8Minute); + pstcTimestamp->stcTSTime.u8Second = BCD2DEC(pstcTimestamp->stcTSTime.u8Second); + pstcTimestamp->u8TSMonth = BCD2DEC(pstcTimestamp->u8TSMonth); + pstcTimestamp->u8TSDay = BCD2DEC(pstcTimestamp->u8TSDay); + } + } + + return enRet; +} + +/** + * @brief Enable or disable RTC intrusion. + * @param [in] u8Ch Specifies the RTC intrusion channel. + * This parameter can be one of the following values: + * @arg RTC_INTRU_CH0: Intrusion channel 0 + * @arg RTC_INTRU_CH1: Intrusion channel 1 + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_IntrusionCmd(uint8_t u8Ch, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_INTRUSION_CHANNEL(u8Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (RTC_INTRU_CH0 != u8Ch) + { + WRITE_REG32(bM4_RTC->TPCR1_b.TPEN1, enNewSta); + } + else + { + WRITE_REG32(bM4_RTC->TPCR0_b.TPEN0, enNewSta); + } +} + +/** + * @brief Enable or disable specified RTC interrupt. + * @param [in] u32IntSrc Specifies the RTC interrupt source. + * This parameter can be one or any combination of the following values: + * @arg RTC_INT_PRDIE: Period interrupt + * @arg RTC_INT_ALMIE: Alarm interrupt + * @arg RTC_INT_TPIE0: RTCIC0 intrusion interrupt + * @arg RTC_INT_TPIE1: RTCIC1 intrusion interrupt + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void RTC_IntCmd(uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_RTC_INTERRUPT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (0UL != (u32IntSrc & 0x0000FFUL)) + { + if (Disable != enNewSta) + { + SET_REG8_BIT(M4_RTC->CR2, (u32IntSrc & 0x0000FFUL)); + } + else + { + CLEAR_REG8_BIT(M4_RTC->CR2, (u32IntSrc & 0x0000FFUL)); + } + } + + if (0UL != (u32IntSrc & 0x00FF00UL)) + { + WRITE_REG32(bM4_RTC->TPCR0_b.TPIE0, enNewSta); + } + + if (0UL != (u32IntSrc & 0xFF0000UL)) + { + WRITE_REG32(bM4_RTC->TPCR1_b.TPIE1, enNewSta); + } +} + +/** + * @brief Get RTC flag status. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg RTC_FLAG_PRDF: Period flag + * @arg RTC_FLAG_ALMF: Alarm flag + * @arg RTC_FLAG_RWEN: Read and write permission flag + * @arg RTC_FLAG_TPOVF: Intrusion overflow flag + * @arg RTC_FLAG_TPF0: RTCIC0 intrusion flag + * @arg RTC_FLAG_TPF1: RTCIC1 intrusion flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t RTC_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + uint8_t u8NormalFlag; + uint8_t u8IntruFlag; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_GET_FLAG(u32Flag)); + + u8NormalFlag = (uint8_t)(u32Flag & 0xFFU); + u8IntruFlag = (uint8_t)((u32Flag >> 16U) & 0xFFU); + if (0U != u8NormalFlag) + { + if (0U != (READ_REG8_BIT(M4_RTC->CR2, u8NormalFlag))) + { + enFlagSta = Set; + } + } + if ((0U != u8IntruFlag) && (Set != enFlagSta)) + { + if (0U != (READ_REG8_BIT(M4_RTC->TPSR, u8IntruFlag))) + { + enFlagSta = Set; + } + } + + return enFlagSta; +} + +/** + * @brief Clear RTC flag. + * @param [in] u32Flag Specifies the RTC flag type. + * This parameter can be one or any combination of the following values: + * @arg RTC_FLAG_PRDF: Period flag + * @arg RTC_FLAG_ALMF: Alarm flag + * @arg RTC_FLAG_TPOVF: Intrusion overflow flag + * @arg RTC_FLAG_TPF0: RTCIC0 intrusion flag + * @arg RTC_FLAG_TPF1: RTCIC1 intrusion flag + * @retval None + */ +void RTC_ClearStatus(uint32_t u32Flag) +{ + uint8_t u8NormalFlag; + uint8_t u8IntruFlag; + + /* Check parameters */ + DDL_ASSERT(IS_RTC_CLEAR_FLAG(u32Flag)); + + u8NormalFlag = (uint8_t)(u32Flag & 0xFFU); + u8IntruFlag = (uint8_t)((u32Flag >> 16U) & 0xFFU); + if (0U != u8NormalFlag) + { + CLEAR_REG8_BIT(M4_RTC->CR2, u8NormalFlag); + } + if (0U != u8IntruFlag) + { + CLEAR_REG8_BIT(M4_RTC->TPSR, u8IntruFlag); + } +} + +/** + * @} + */ + +#endif /* DDL_RTC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sdioc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sdioc.c new file mode 100644 index 0000000000000000000000000000000000000000..b0642bcb0da1709b4c76bec7cca588d5d7a69932 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sdioc.c @@ -0,0 +1,3050 @@ +/** + ******************************************************************************* + * @file hc32f4a0_sdioc.c + * @brief This file provides firmware functions to manage the Secure Digital + * Input and Output Controller(SDIOC). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-08-11 Yangjp Fix a known potential risk in SDIOC_VerifyClockDiv function + 2020-09-04 Yangjp Optimize timeout handling in functions + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_sdioc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_SDIOC SDIOC + * @brief SDIOC Driver Library + * @{ + */ + +#if (DDL_SDIOC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SDIOC_Local_Macros SDIOC Local Macros + * @{ + */ + +/* Masks for R6 Response */ +#define SDMMC_R6_GENERAL_UNKNOWN_ERROR (0x00002000UL) +#define SDMMC_R6_ILLEGAL_CMD (0x00004000UL) +#define SDMMC_R6_COM_CRC_FAILED (0x00008000UL) + +/* SDMMC command parameters */ +#define SDMMC_CMD8_CHECK_PATTERN (0x000001AAUL) +/* 3.2V-3.3V */ +#define SDMMC_ACMD41_VOLTAGE_WINDOW (0x80100000UL) + +/* Command send and response timeout(ms) */ +#define SDMMC_CMD_TIMEOUT (5000UL) +/* Max erase Timeout 60s */ +#define SDMMC_MAX_ERASE_TIMEOUT (60000UL) + +/* SDIOC software reset timeout(ms) */ +#define SDIOC_SW_RESET_TIMEOUT (50UL) + +/* SDIOC NORINTSGEN register Mask */ +#define SDIOC_NORINTSGEN_CLEAR_MASK (0x01F7U) +/* SDIOC ERRINTSGEN register Mask */ +#define SDIOC_ERRINTSGEN_CLEAR_MASK (0x017FU) + +/*!< Get the specified register address of the specified SDIOC unit */ +#define SDIOC_ARG(__UNIT__) ((uint32_t)(&((__UNIT__)->ARG0))) +#define SDIOC_BUF(__UNIT__) ((uint32_t)(&((__UNIT__)->BUF0))) +#define SDIOC_RESPx(__UNIT__, RESP_REG) ((uint32_t)(&((__UNIT__)->RESP0)) + (uint32_t)(RESP_REG)) + +/** + * @defgroup SDIOC_Check_Parameters_Validity SDIOC Check Parameters Validity + * @{ + */ +#define IS_SDIOC_UNIT(x) \ +( ((x) == M4_SDIOC1) || \ + ((x) == M4_SDIOC2)) + +#define IS_SDIOC_MODE(x) \ +( ((x) == SDIOC_MODE_SD) || \ + ((x) == SDIOC_MODE_MMC)) + +#define IS_SDIOC_CARD_DETECT_SELECT(x) \ +( ((x) == SDIOC_CARD_DETECT_CD_PIN_LEVEL) || \ + ((x) == SDIOC_CARD_DETECT_TEST_SIGNAL)) + +#define IS_SDIOC_CARD_DETECT_TEST_LEVEL(x) \ +( ((x) == SDIOC_CARD_DETECT_TEST_LEVEL_LOW) || \ + ((x) == SDIOC_CARD_DETECT_TEST_LEVEL_HIGH)) + +#define IS_SDIOC_SPEED_MODE(x) \ +( ((x) == SDIOC_SPEED_MODE_NORMAL) || \ + ((x) == SDIOC_SPEED_MODE_HIGH)) + +#define IS_SDIOC_BUS_WIDTH(x) \ +( ((x) == SDIOC_BUS_WIDTH_1BIT) || \ + ((x) == SDIOC_BUS_WIDTH_4BIT) || \ + ((x) == SDIOC_BUS_WIDTH_8BIT)) + +#define IS_SDIOC_CLOCK_DIV(x) \ +( ((x) == SDIOC_CLOCK_DIV_1) || \ + ((x) == SDIOC_CLOCK_DIV_2) || \ + ((x) == SDIOC_CLOCK_DIV_4) || \ + ((x) == SDIOC_CLOCK_DIV_8) || \ + ((x) == SDIOC_CLOCK_DIV_16) || \ + ((x) == SDIOC_CLOCK_DIV_32) || \ + ((x) == SDIOC_CLOCK_DIV_64) || \ + ((x) == SDIOC_CLOCK_DIV_128) || \ + ((x) == SDIOC_CLOCK_DIV_256)) + +#define IS_SDIOC_CMD_TYPE(x) \ +( ((x) == SDIOC_CMD_TYPE_NORMAL) || \ + ((x) == SDIOC_CMD_TYPE_SUSPEND) || \ + ((x) == SDIOC_CMD_TYPE_RESUME) || \ + ((x) == SDIOC_CMD_TYPE_ABORT)) + +#define IS_SDIOC_DATA_LINE(x) \ +( ((x) == SDIOC_DATA_LINE_DISABLE) || \ + ((x) == SDIOC_DATA_LINE_ENABLE)) + +#define IS_SDIOC_TRANSFER_DIR(x) \ +( ((x) == SDIOC_TRANSFER_DIR_TO_CARD) || \ + ((x) == SDIOC_TRANSFER_DIR_TO_HOST)) + +#define IS_SDIOC_AUTO_SEND_CMD12(x) \ +( ((x) == SDIOC_AUTO_SEND_CMD12_DISABLE) || \ + ((x) == SDIOC_AUTO_SEND_CMD12_ENABLE)) + +#define IS_SDIOC_TRANSFER_MODE(x) \ +( ((x) == SDIOC_TRANSFER_MODE_SINGLE) || \ + ((x) == SDIOC_TRANSFER_MODE_INFINITE) || \ + ((x) == SDIOC_TRANSFER_MODE_MULTIPLE) || \ + ((x) == SDIOC_TRANSFER_MODE_STOP_MULTIPLE)) + +#define IS_SDIOC_DATA_TIMEOUT_TIME(x) \ +( ((x) == SDIOC_DATA_TIMEOUT_CLK_2_13) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_14) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_15) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_16) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_17) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_18) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_19) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_20) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_21) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_22) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_23) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_24) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_25) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_26) || \ + ((x) == SDIOC_DATA_TIMEOUT_CLK_2_27)) + +#define IS_SDIOC_RESPONSE_REG(x) \ +( ((x) == SDIOC_RESPONSE_REG_BIT0_31) || \ + ((x) == SDIOC_RESPONSE_REG_BIT32_63) || \ + ((x) == SDIOC_RESPONSE_REG_BIT64_95) || \ + ((x) == SDIOC_RESPONSE_REG_BIT96_127)) + +#define IS_SDIOC_SW_RESET_TYPE(x) \ +( ((x) == SDIOC_SW_RESET_DATA_LINE) || \ + ((x) == SDIOC_SW_RESET_CMD_LINE) || \ + ((x) == SDIOC_SW_RESET_ALL)) + +#define IS_SDIOC_OUTPUT_CLK_FREQ(x) \ +( ((x) == SDIOC_OUTPUT_CLK_FREQ_400K) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_25M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_26M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_50M) || \ + ((x) == SDIOC_OUTPUT_CLK_FREQ_52M)) + +#define IS_SDIOC_GET_HOST_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(SDIOC_HOST_FLAG_CMDL | \ + SDIOC_HOST_FLAG_DATL | \ + SDIOC_HOST_FLAG_DATL_D0 | \ + SDIOC_HOST_FLAG_DATL_D1 | \ + SDIOC_HOST_FLAG_DATL_D2 | \ + SDIOC_HOST_FLAG_DATL_D3 | \ + SDIOC_HOST_FLAG_WPL | \ + SDIOC_HOST_FLAG_CDL | \ + SDIOC_HOST_FLAG_CSS | \ + SDIOC_HOST_FLAG_CIN | \ + SDIOC_HOST_FLAG_BRE | \ + SDIOC_HOST_FLAG_BWE | \ + SDIOC_HOST_FLAG_RTA | \ + SDIOC_HOST_FLAG_WTA | \ + SDIOC_HOST_FLAG_DA | \ + SDIOC_HOST_FLAG_CID | \ + SDIOC_HOST_FLAG_CIC)))))) + +#define IS_SDIOC_GET_NORMAL_ERROR_INT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(SDIOC_NORMAL_INT_FLAG_EI | \ + SDIOC_NORMAL_INT_FLAG_CINT | \ + SDIOC_NORMAL_INT_FLAG_CRM | \ + SDIOC_NORMAL_INT_FLAG_CIST | \ + SDIOC_NORMAL_INT_FLAG_BRR | \ + SDIOC_NORMAL_INT_FLAG_BWR | \ + SDIOC_NORMAL_INT_FLAG_BGE | \ + SDIOC_NORMAL_INT_FLAG_TC | \ + SDIOC_NORMAL_INT_FLAG_CC | \ + SDIOC_ERROR_INT_FLAG_ACE | \ + SDIOC_ERROR_INT_FLAG_DEBE | \ + SDIOC_ERROR_INT_FLAG_DCE | \ + SDIOC_ERROR_INT_FLAG_DTOE | \ + SDIOC_ERROR_INT_FLAG_CIE | \ + SDIOC_ERROR_INT_FLAG_CEBE | \ + SDIOC_ERROR_INT_FLAG_CCE | \ + SDIOC_ERROR_INT_FLAG_CTOE)))))) + +#define IS_SDIOC_CLEAR_NORMAL_ERROR_INT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(SDIOC_NORMAL_INT_FLAG_CRM | \ + SDIOC_NORMAL_INT_FLAG_CIST | \ + SDIOC_NORMAL_INT_FLAG_BRR | \ + SDIOC_NORMAL_INT_FLAG_BWR | \ + SDIOC_NORMAL_INT_FLAG_BGE | \ + SDIOC_NORMAL_INT_FLAG_TC | \ + SDIOC_NORMAL_INT_FLAG_CC | \ + SDIOC_ERROR_INT_FLAG_ACE | \ + SDIOC_ERROR_INT_FLAG_DEBE | \ + SDIOC_ERROR_INT_FLAG_DCE | \ + SDIOC_ERROR_INT_FLAG_DTOE | \ + SDIOC_ERROR_INT_FLAG_CIE | \ + SDIOC_ERROR_INT_FLAG_CEBE | \ + SDIOC_ERROR_INT_FLAG_CCE | \ + SDIOC_ERROR_INT_FLAG_CTOE)))))) + +#define IS_SDIOC_NORMAL_ERROR_INT(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(SDIOC_NORMAL_INT_CINTSEN | \ + SDIOC_NORMAL_INT_CRMSEN | \ + SDIOC_NORMAL_INT_CISTSEN | \ + SDIOC_NORMAL_INT_BRRSEN | \ + SDIOC_NORMAL_INT_BWRSEN | \ + SDIOC_NORMAL_INT_BGESEN | \ + SDIOC_NORMAL_INT_TCSEN | \ + SDIOC_NORMAL_INT_CCSEN | \ + SDIOC_ERROR_INT_ACESEN | \ + SDIOC_ERROR_INT_DEBESEN | \ + SDIOC_ERROR_INT_DCESEN | \ + SDIOC_ERROR_INT_DTOESEN | \ + SDIOC_ERROR_INT_CIESEN | \ + SDIOC_ERROR_INT_CEBESEN | \ + SDIOC_ERROR_INT_CCESEN | \ + SDIOC_ERROR_INT_CTOESEN)))))) + +#define IS_SDIOC_AUTO_CMD_ERROR_FLAG(x) \ +( (0U != (x)) && \ + (0U == ((x) & ((uint16_t)(~(uint16_t)(SDIOC_AUTO_CMD_ERROR_FLAG_CMDE | \ + SDIOC_AUTO_CMD_ERROR_FLAG_IE | \ + SDIOC_AUTO_CMD_ERROR_FLAG_EBE | \ + SDIOC_AUTO_CMD_ERROR_FLAG_CE | \ + SDIOC_AUTO_CMD_ERROR_FLAG_TOE | \ + SDIOC_AUTO_CMD_ERROR_FLAG_NE)))))) + +#define IS_SDIOC_FORCE_AUTO_CMD_FLAG(x) \ +( (0U != (x)) && \ + (0U == ((x) & ((uint16_t)(~(uint16_t)(SDIOC_FORCE_AUTO_CMD_ERROR_FCMDE | \ + SDIOC_FORCE_AUTO_CMD_ERROR_FIE | \ + SDIOC_FORCE_AUTO_CMD_ERROR_FEBE | \ + SDIOC_FORCE_AUTO_CMD_ERROR_FCE | \ + SDIOC_FORCE_AUTO_CMD_ERROR_FTOE | \ + SDIOC_FORCE_AUTO_CMD_ERROR_FNE)))))) + +#define IS_SDIOC_FORCE_ERROR_INT_FLAG(x) \ +( (0U != (x)) && \ + (0U == ((x) & ((uint16_t)(~(uint16_t)(SDIOC_FORCE_ERROR_INT_FACE | \ + SDIOC_FORCE_ERROR_INT_FDEBE | \ + SDIOC_FORCE_ERROR_INT_FDCE | \ + SDIOC_FORCE_ERROR_INT_FDTOE | \ + SDIOC_FORCE_ERROR_INT_FCIE | \ + SDIOC_FORCE_ERROR_INT_FCEBE | \ + SDIOC_FORCE_ERROR_INT_FCCE | \ + SDIOC_FORCE_ERROR_INT_FCTOE)))))) + +#define IS_SDIOC_RESOPNE_TYPE(x) \ +( ((x) == SDIOC_RESOPNE_TYPE_NO) || \ + ((x) == SDIOC_RESOPNE_TYPE_R2) || \ + ((x) == SDIOC_RESOPNE_TYPE_R3_R4) || \ + ((x) == SDIOC_RESOPNE_TYPE_R1_R5_R6_R7) || \ + ((x) == SDIOC_RESOPNE_TYPE_R1B_R5B)) + +#define IS_SDIOC_CMD_INDEX(x) ((x) < 0x40U) + +#define IS_SDIOC_BLOCK_SIZE(x) (((x) >= 1U) && ((x) <= 512U)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +static en_result_t SDMMC_WaitResponse(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32CheckFlag, uint32_t u32Timeout, uint32_t *pu32ErrSta); +static en_result_t SDMMC_GetCmdError(M4_SDIOC_TypeDef *SDIOCx); +static en_result_t SDMMC_GetCmdResp1(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrSta); +static en_result_t SDMMC_GetCmdResp1Busy(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrSta); +static en_result_t SDMMC_GetCmdResp2(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +static en_result_t SDMMC_GetCmdResp3(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); +static en_result_t SDMMC_GetCmdResp6(M4_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrSta); +static en_result_t SDMMC_GetCmdResp7(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta); + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SDIOC_Global_Functions SDIOC Global Functions + * @{ + */ +/** + * @brief De-Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @retval An en_result_t enumeration value: + * - Ok: SDIOC De-Initialize success + * - ErrorTimeout: Software reset timeout + */ +en_result_t SDIOC_DeInit(M4_SDIOC_TypeDef *SDIOCx) +{ + return SDIOC_SoftwareReset(SDIOCx, SDIOC_SW_RESET_ALL); +} + +/** + * @brief Initialize SDIOC. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: SDIOC Initialize success + * - ErrorInvalidParameter: pstcSdiocInit == NULL + */ +en_result_t SDIOC_Init(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_init_t *pstcSdiocInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcSdiocInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_MODE(pstcSdiocInit->u32Mode)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_SELECT(pstcSdiocInit->u8CardDetectSelect)); + DDL_ASSERT(IS_SDIOC_SPEED_MODE(pstcSdiocInit->u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(pstcSdiocInit->u8BusWidth)); + DDL_ASSERT(IS_SDIOC_CLOCK_DIV(pstcSdiocInit->u16ClockDiv)); + + /* Set the SDIOC mode */ + if (M4_SDIOC1 == SDIOCx) + { + WRITE_REG32(bM4_PERIC->SDIOC_SYCTLREG_b.SELMMC1, pstcSdiocInit->u32Mode); + } + else + { + WRITE_REG32(bM4_PERIC->SDIOC_SYCTLREG_b.SELMMC2, pstcSdiocInit->u32Mode); + } + + /* Set the SDIOC clock control value */ + WRITE_REG16(SDIOCx->CLKCON, (pstcSdiocInit->u16ClockDiv | SDIOC_CLKCON_ICE | SDIOC_CLKCON_CE)); + /* Set the SDIOC host control value */ + WRITE_REG8(SDIOCx->HOSTCON, (pstcSdiocInit->u8CardDetectSelect | + pstcSdiocInit->u8BusWidth | pstcSdiocInit->u8SpeedMode)); + /* Enable normal interrupt status */ + WRITE_REG16(SDIOCx->NORINTSTEN, SDIOC_NORINTSGEN_CLEAR_MASK); + /* Enable error interrupt status */ + WRITE_REG16(SDIOCx->ERRINTSTEN, SDIOC_ERRINTSGEN_CLEAR_MASK); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_sdioc_init_t to default values. + * @param [out] pstcSdiocInit Pointer to a @ref stc_sdioc_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcSdiocInit == NULL + */ +en_result_t SDIOC_StructInit(stc_sdioc_init_t *pstcSdiocInit) +{ + en_result_t enRet = Ok; + + if (NULL == pstcSdiocInit) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcSdiocInit->u32Mode = SDIOC_MODE_SD; + pstcSdiocInit->u8CardDetectSelect = SDIOC_CARD_DETECT_CD_PIN_LEVEL; + pstcSdiocInit->u8SpeedMode = SDIOC_SPEED_MODE_NORMAL; + pstcSdiocInit->u8BusWidth = SDIOC_BUS_WIDTH_1BIT; + pstcSdiocInit->u16ClockDiv = SDIOC_CLOCK_DIV_1; + } + + return enRet; +} + +/** + * @brief Set software reset. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u8ResetType Software reset type + * This parameter can be one of the following values: + * @arg SDIOC_SW_RESET_DATA_LINE: Only part of data circuit is reset + * @arg SDIOC_SW_RESET_CMD_LINE: Only part of command circuit is reset + * @arg SDIOC_SW_RESET_ALL: Reset the entire Host Controller except for the card detection circuit + * @retval An en_result_t enumeration value: + * - Ok: Software reset success + * - ErrorTimeout: Software reset timeout + */ +en_result_t SDIOC_SoftwareReset(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8ResetType) +{ + en_result_t enRet = Ok; + __IO uint32_t u32Count; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SW_RESET_TYPE(u8ResetType)); + + WRITE_REG8(SDIOCx->SFTRST, u8ResetType); + /* Wait for reset finish */ + u32Count = SDIOC_SW_RESET_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0U != READ_REG8_BIT(SDIOCx->SFTRST, u8ResetType)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @brief Enable or disable power. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_PowerCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } + else + { + CLEAR_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON); + } +} + +/** + * @brief Get power state. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @retval An en_result_t enumeration value: + * - Disable: Power off or SDIOCx == NULL + * - Enable: Power on + */ +en_functional_state_t SDIOC_GetPowerState(const M4_SDIOC_TypeDef *SDIOCx) +{ + en_functional_state_t enPowerSta = Disable; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0U != (READ_REG8_BIT(SDIOCx->PWRCON, SDIOC_PWRCON_PWON))) + { + enPowerSta = Enable; + } + + return enPowerSta; +} + +/** + * @brief Get SDIOC work mode. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @retval uint32_t value: + * - SDIOC_MODE_SD: SDIOCx selects SD mode + * - SDIOC_MODE_MMC: SDIOCx selects MMC mode + */ +uint32_t SDIOC_GetMode(const M4_SDIOC_TypeDef *SDIOCx) +{ + uint32_t u32SdMode; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + u32SdMode = READ_REG32_BIT(M4_PERIC->SDIOC_SYCTLREG, ((M4_SDIOC1 == SDIOCx) ? + PERIC_SDIOC_SYCTLREG_SELMMC1 : PERIC_SDIOC_SYCTLREG_SELMMC2)); + if (0UL != u32SdMode) /* MMC mode */ + { + u32SdMode = SDIOC_MODE_MMC; + } + + return u32SdMode; +} + +/** + * @brief Enable or disable clock output. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_ClockCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } + else + { + CLEAR_REG8_BIT(SDIOCx->CLKCON, SDIOC_CLKCON_CE); + } +} + +/** + * @brief Set clock division. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u16ClkDiv Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLOCK_DIV_1: PCLK1/1 + * @arg SDIOC_CLOCK_DIV_2: PCLK1/2 + * @arg SDIOC_CLOCK_DIV_4: PCLK1/4 + * @arg SDIOC_CLOCK_DIV_8: PCLK1/8 + * @arg SDIOC_CLOCK_DIV_16: PCLK1/16 + * @arg SDIOC_CLOCK_DIV_32: PCLK1/32 + * @arg SDIOC_CLOCK_DIV_64: PCLK1/64 + * @arg SDIOC_CLOCK_DIV_128: PCLK1/128 + * @arg SDIOC_CLOCK_DIV_256: PCLK1/256 + * @retval None + */ +void SDIOC_SetClockDiv(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16ClkDiv) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLOCK_DIV(u16ClkDiv)); + + MODIFY_REG16(SDIOCx->CLKCON, SDIOC_CLKCON_FS, u16ClkDiv); +} + +/** + * @brief Find the most suitable clock division for the set clock frequency. + * @note More clock values can be set as needed, but the maximum cannot exceed 50MHz. + * @param [in] u32ClkFreq SDIOCx_CK clock frequency + * This parameter can be one of the following values: + * @arg SDIOC_OUTPUT_CLK_FREQ_400K: SDIOC clock: 400KHz + * @arg SDIOC_OUTPUT_CLK_FREQ_25M: SDIOC clock: 25MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_26M: SDIOC clock: 26MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_50M: SDIOC clock: 50MHz + * @arg SDIOC_OUTPUT_CLK_FREQ_52M: SDIOC clock: 52MHz + * @arg Any other value + * @param [out] pu16ClkDiv Pointer to a value of clock division + * @retval An en_result_t enumeration value: + * - Ok: SDIOC Initialize success + * - Error: The Bus clock frequency is too high + * - ErrorInvalidParameter: pu16ClkDiv == NULL or 0UL == u32ClkFreq + */ +en_result_t SDIOC_GetOptimumClockDiv(uint32_t u32ClkFreq, uint16_t *pu16ClkDiv) +{ + en_result_t enRet = Ok; + uint32_t u32BusClk; + uint32_t u32ClkDiv; + uint32_t u32Temp; + + if ((NULL == pu16ClkDiv) || (0UL == u32ClkFreq)) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Get PCLK1 frequency */ + u32BusClk = SystemCoreClock / (0x01UL << (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + u32ClkDiv = u32BusClk / u32ClkFreq; + if (0UL != (u32BusClk % u32ClkFreq)) + { + u32ClkDiv++; + } + + /* Check the effectiveness of clock division */ + if (u32ClkDiv > 256U) /* Maximum division is 256 */ + { + enRet = Error; + } + else + { + if (1U == u32ClkDiv) + { + *pu16ClkDiv = SDIOC_CLOCK_DIV_1; + } + else + { + for (u32Temp=SDIOC_CLOCK_DIV_2; u32Temp<=SDIOC_CLOCK_DIV_256; u32Temp<<=1U) + { + if (u32ClkDiv <= (u32Temp >> (SDIOC_CLKCON_FS_POS - 1U))) + { + break; + } + } + *pu16ClkDiv = (uint16_t)u32Temp; + } + } + } + + return enRet; +} + +/** + * @brief Verify the validity of the clock division. + * @param [in] u32Mode SDIOC work mode + * This parameter can be one of the following values: + * @arg SDIOC_MODE_SD: SDIOCx selects SD mode + * @arg SDIOC_MODE_MMC: SDIOCx selects MMC mode + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MODE_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MODE_HIGH: High speed mode + * @param [in] u16ClkDiv Clock division + * This parameter can be one of the following values: + * @arg SDIOC_CLOCK_DIV_1: PCLK1/1 + * @arg SDIOC_CLOCK_DIV_2: PCLK1/2 + * @arg SDIOC_CLOCK_DIV_4: PCLK1/4 + * @arg SDIOC_CLOCK_DIV_8: PCLK1/8 + * @arg SDIOC_CLOCK_DIV_16: PCLK1/16 + * @arg SDIOC_CLOCK_DIV_32: PCLK1/32 + * @arg SDIOC_CLOCK_DIV_64: PCLK1/64 + * @arg SDIOC_CLOCK_DIV_128: PCLK1/128 + * @arg SDIOC_CLOCK_DIV_256: PCLK1/256 + * @retval An en_result_t enumeration value: + * - Ok: The clock division is valid + * - Error: The Bus clock frequency is too high + */ +en_result_t SDIOC_VerifyClockDiv(uint32_t u32Mode, uint8_t u8SpeedMode, uint16_t u16ClkDiv) +{ + en_result_t enRet = Ok; + uint32_t u32BusClk; + uint32_t u32ClkFreq; + uint32_t u32MaxFreq; + uint32_t u32DivValue; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_MODE(u32Mode)); + DDL_ASSERT(IS_SDIOC_SPEED_MODE(u8SpeedMode)); + DDL_ASSERT(IS_SDIOC_CLOCK_DIV(u16ClkDiv)); + + /* Get PCLK1 frequency */ + u32BusClk = SystemCoreClock / (0x01UL << (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)); + u32DivValue = ((uint32_t)u16ClkDiv >> (SDIOC_CLKCON_FS_POS - 1U)); + if (0UL == u32DivValue) + { + u32ClkFreq = u32BusClk; + } + else + { + u32ClkFreq = u32BusClk / u32DivValue; + } + + if (SDIOC_SPEED_MODE_NORMAL == u8SpeedMode) + { + if (SDIOC_MODE_SD != u32Mode) /* MMC mode */ + { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_26M; + } + else + { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_25M; + } + } + else + { + if (SDIOC_MODE_SD != u32Mode) /* MMC mode */ + { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_52M; + } + else + { + u32MaxFreq = SDIOC_OUTPUT_CLK_FREQ_50M; + } + } + + if (u32ClkFreq > u32MaxFreq) + { + enRet = Error; + } + + return enRet; +} + +/** + * @brief Get device insert state. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @retval An en_result_t enumeration value: + * - Disable: No device inserted + * - Enable: The device inserted + */ +en_functional_state_t SDIOC_GetDeviceInsertState(const M4_SDIOC_TypeDef *SDIOCx) +{ + en_functional_state_t enInsertSta = Disable; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CSS))) + { + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, SDIOC_PSTAT_CIN))) + { + enInsertSta = Enable; + } + } + + return enInsertSta; +} + +/** + * @brief Set speed mode. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u8SpeedMode Speed mode + * This parameter can be one of the following values: + * @arg SDIOC_SPEED_MODE_NORMAL: Normal speed mode + * @arg SDIOC_SPEED_MODE_HIGH: High speed mode + * @retval None + */ +void SDIOC_SetSpeedMode(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8SpeedMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_SPEED_MODE(u8SpeedMode)); + + if (SDIOC_SPEED_MODE_NORMAL != u8SpeedMode) + { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } + else + { + CLEAR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_HSEN); + } +} + +/** + * @brief Set bus width. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u8BusWidth Bus width + * This parameter can be one of the following values: + * @arg SDIOC_BUS_WIDTH_1BIT: The Bus width is 1 bit + * @arg SDIOC_BUS_WIDTH_4BIT: The Bus width is 4 bit + * @arg SDIOC_BUS_WIDTH_8BIT: The Bus width is 8 bit + * @retval None + */ +void SDIOC_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8BusWidth) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BUS_WIDTH(u8BusWidth)); + + MODIFY_REG8(SDIOCx->HOSTCON, (SDIOC_HOSTCON_DW | SDIOC_HOSTCON_EXDW), u8BusWidth); +} + +/** + * @brief Set card detect line select. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u8Src Card detect source + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_CD_PIN_LEVEL: SDIOCx_CD(x=1~2) line is selected (for normal use) + * @arg SDIOC_CARD_DETECT_TEST_SIGNAL: The Card Detect Test Level is selected(for test purpose) + * @retval None + */ +void SDIOC_SetCardDetectSource(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8Src) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_SELECT(u8Src)); + + if (SDIOC_CARD_DETECT_CD_PIN_LEVEL != u8Src) + { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } + else + { + CLEAR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDSS); + } +} + +/** + * @brief Set card detect test level. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u8Level Card test level + * This parameter can be one of the following values: + * @arg SDIOC_CARD_DETECT_TEST_LEVEL_LOW: Card identification test signal is low level (with device insertion) + * @arg SDIOC_CARD_DETECT_TEST_LEVEL_HIGH: Card identification test signal is high level (no device insertion) + * @retval None + */ +void SDIOC_SetCardDetectTestLevel(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8Level) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CARD_DETECT_TEST_LEVEL(u8Level)); + + if (SDIOC_CARD_DETECT_TEST_LEVEL_LOW != u8Level) + { + SET_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } + else + { + CLEAR_REG8_BIT(SDIOCx->HOSTCON, SDIOC_HOSTCON_CDTL); + } +} + +/** + * @brief Configure the SDIOCx command parameters. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] pstcCmd Pointer to a @ref stc_sdioc_cmd_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Configure SDIOCx command parameters success + * - ErrorInvalidParameter: pstcCmd == NULL + */ +en_result_t SDIOC_SendCommand(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_cmd_init_t *pstcCmd) +{ + en_result_t enRet = Ok; + __IO uint32_t *pu32Temp; + + if (NULL == pstcCmd) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CMD_INDEX(pstcCmd->u16CmdIndex)); + DDL_ASSERT(IS_SDIOC_CMD_TYPE(pstcCmd->u16CmdType)); + DDL_ASSERT(IS_SDIOC_DATA_LINE(pstcCmd->u16DataLineEn)); + DDL_ASSERT(IS_SDIOC_RESOPNE_TYPE(pstcCmd->u16RespType)); + + /* Set the SDIOC Command parameters value */ + pu32Temp = (__IO uint32_t *)SDIOC_ARG(SDIOCx); + WRITE_REG32(*pu32Temp, pstcCmd->u32Argument); + /* Set the SDIOC Command controller value */ + WRITE_REG16(SDIOCx->CMD, ((uint16_t)(pstcCmd->u16CmdIndex << SDIOC_CMD_IDX_POS) | + pstcCmd->u16CmdType | pstcCmd->u16DataLineEn | pstcCmd->u16RespType)); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_sdioc_cmd_init_t to default values. + * @param [out] pstcCmd Pointer to a @ref stc_sdioc_cmd_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcData == NULL + */ +en_result_t SDIOC_CmdStructInit(stc_sdioc_cmd_init_t *pstcCmd) +{ + en_result_t enRet = Ok; + + if (NULL == pstcCmd) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcCmd->u32Argument = 0U; + pstcCmd->u16CmdIndex = 0U; + pstcCmd->u16CmdType = SDIOC_CMD_TYPE_NORMAL; + pstcCmd->u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + pstcCmd->u16RespType = SDIOC_RESOPNE_TYPE_NO; + } + + return enRet; +} + +/** + * @brief Get the response received from the card for the last command + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u8RespReg SDIOC response register + * This parameter can be one of the following values: + * @arg SDIOC_RESPONSE_REG_BIT0_31: Command Response Register 0-31bit + * @arg SDIOC_RESPONSE_REG_BIT32_63: Command Response Register 32-63bit + * @arg SDIOC_RESPONSE_REG_BIT64_95: Command Response Register 64-95bit + * @arg SDIOC_RESPONSE_REG_BIT96_127: Command Response Register 96-127bit + * @param [out] pu32RespVal Pointer to a Response value + * @retval An en_result_t enumeration value: + * - Ok: Get response success + * - ErrorInvalidParameter: pu32RespVal == NULL + */ +en_result_t SDIOC_GetResponse(M4_SDIOC_TypeDef *SDIOCx, uint8_t u8RespReg, uint32_t *pu32RespVal) +{ + en_result_t enRet = Ok; + + if (NULL == pu32RespVal) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_RESPONSE_REG(u8RespReg)); + + *pu32RespVal = READ_REG32(*(__IO uint32_t *)SDIOC_RESPx(SDIOCx, u8RespReg)); + } + + return enRet; +} + +/** + * @brief Configure the SDIOCx data parameters. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] pstcData Pointer to a @ref stc_sdioc_data_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Configure SDIOCx data parameters success + * - ErrorInvalidParameter: pstcData == NULL + */ +en_result_t SDIOC_ConfigData(M4_SDIOC_TypeDef *SDIOCx, const stc_sdioc_data_init_t *pstcData) +{ + en_result_t enRet = Ok; + uint16_t u16BlkCnt; + + if (NULL == pstcData) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_BLOCK_SIZE(pstcData->u16BlockSize)); + DDL_ASSERT(IS_SDIOC_TRANSFER_DIR(pstcData->u16TransferDir)); + DDL_ASSERT(IS_SDIOC_AUTO_SEND_CMD12(pstcData->u16AutoCMD12En)); + DDL_ASSERT(IS_SDIOC_TRANSFER_MODE(pstcData->u16TransferMode)); + DDL_ASSERT(IS_SDIOC_DATA_TIMEOUT_TIME(pstcData->u16DataTimeout)); + + if (SDIOC_TRANSFER_MODE_STOP_MULTIPLE == pstcData->u16TransferMode) + { + u16BlkCnt = 0U; + } + else + { + u16BlkCnt = pstcData->u16BlockCount; + } + + /* Set the SDIOC Data Transfer Timeout value */ + WRITE_REG8(SDIOCx->TOUTCON, pstcData->u16DataTimeout); + /* Set the SDIOC Block Count value */ + WRITE_REG16(SDIOCx->BLKSIZE, pstcData->u16BlockSize); + /* Set the SDIOC Block Size value */ + WRITE_REG16(SDIOCx->BLKCNT,u16BlkCnt); + /* Set the SDIOC Data Transfer Mode */ + WRITE_REG16(SDIOCx->TRANSMODE, ((pstcData->u16TransferDir | + pstcData->u16AutoCMD12En | pstcData->u16TransferMode) & 0x00FFU)); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_sdioc_data_init_t to default values. + * @param [out] pstcData Pointer to a @ref stc_sdioc_data_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Structure Initialize success + * - ErrorInvalidParameter: pstcData == NULL + */ +en_result_t SDIOC_DataStructInit(stc_sdioc_data_init_t *pstcData) +{ + en_result_t enRet = Ok; + + if (NULL == pstcData) + { + enRet = ErrorInvalidParameter; + } + else + { + pstcData->u16BlockSize = 512U; + pstcData->u16BlockCount = 0U; + pstcData->u16TransferDir = SDIOC_TRANSFER_DIR_TO_CARD; + pstcData->u16AutoCMD12En = SDIOC_AUTO_SEND_CMD12_DISABLE; + pstcData->u16TransferMode = SDIOC_TRANSFER_MODE_SINGLE; + pstcData->u16DataTimeout = SDIOC_DATA_TIMEOUT_CLK_2_13; + } + + return enRet; +} + +/** + * @brief Read data from SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval An en_result_t enumeration value: + * - Ok: Read data success + * - ErrorInvalidParameter: NULL == au8Data or (u32Len % 4U) != 0 + */ +en_result_t SDIOC_ReadBuffer(M4_SDIOC_TypeDef *SDIOCx, uint8_t au8Data[], uint32_t u32Len) +{ + en_result_t enRet = Ok; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = (__IO uint32_t *)SDIOC_BUF(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) + { + u32Temp = READ_REG32(*BUF_REG); + au8Data[i] = (uint8_t)(u32Temp & 0x000000FFUL); + au8Data[i+1U] = (uint8_t)((u32Temp >> 8U) & 0x000000FFUL); + au8Data[i+2U] = (uint8_t)((u32Temp >> 16U) & 0x000000FFUL); + au8Data[i+3U] = (uint8_t)((u32Temp >> 24U) & 0x000000FFUL); + } + } + + return enRet; +} + +/** + * @brief Write data to SDIOC FIFO. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] au8Data Pointer to the buffer + * @param [in] u32Len Data length + * @retval An en_result_t enumeration value: + * - Ok: Write data success + * - ErrorInvalidParameter: NULL == au8Data or (u32Len % 4U) != 0 + */ +en_result_t SDIOC_WriteBuffer(M4_SDIOC_TypeDef *SDIOCx, const uint8_t au8Data[], uint32_t u32Len) +{ + en_result_t enRet = Ok; + uint32_t i; + uint32_t u32Temp; + __IO uint32_t *BUF_REG; + + if ((NULL == au8Data) || (0U != (u32Len % 4U))) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + BUF_REG = (__IO uint32_t *)SDIOC_BUF(SDIOCx); + for (i = 0U; i < u32Len; i += 4U) + { + u32Temp = (uint32_t)au8Data[i] | ((uint32_t)au8Data[i+1U] << 8U) | + ((uint32_t)au8Data[i+2U] << 16U) | ((uint32_t)au8Data[i+3U] << 24U); + WRITE_REG32(*BUF_REG, u32Temp); + } + } + + return enRet; +} + +/** + * @brief Enable or disable block gap stop. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_BlockGapStopCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } + else + { + CLEAR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_SABGR); + } +} + +/** + * @brief Restart data transfer. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @retval None + */ +void SDIOC_RestartTransfer(M4_SDIOC_TypeDef *SDIOCx) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_CR); +} + +/** + * @brief Enable or disable read wait. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_ReadWaitCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } + else + { + CLEAR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_RWC); + } +} + +/** + * @brief Enable or disable data block gap interrupt. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_BlockGapInterruptCmd(M4_SDIOC_TypeDef *SDIOCx, en_functional_state_t enNewSta) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + if (Disable != enNewSta) + { + SET_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } + else + { + CLEAR_REG8_BIT(SDIOCx->BLKGPCON, SDIOC_BLKGPCON_IABG); + } +} + +/** + * @brief Enable or disable interrupt. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32IntSrc Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_NORMAL_INT_CINTSEN: Card Interrupt + * @arg SDIOC_NORMAL_INT_CRMSEN: Card Removal Interrupt + * @arg SDIOC_NORMAL_INT_CISTSEN: Card Insertion Interrupt + * @arg SDIOC_NORMAL_INT_BRRSEN: Buffer Read Ready Interrupt + * @arg SDIOC_NORMAL_INT_BWRSEN: Buffer Write Ready Interrupt + * @arg SDIOC_NORMAL_INT_BGESEN: Block Gap Event Interrupt + * @arg SDIOC_NORMAL_INT_TCSEN: Transfer Complete Interrupt + * @arg SDIOC_NORMAL_INT_CCSEN: Command Complete Interrupt + * @arg SDIOC_ERROR_INT_ACESEN: Auto CMD12 Error Interrupt + * @arg SDIOC_ERROR_INT_DEBESEN: Data End Bit Error Interrupt + * @arg SDIOC_ERROR_INT_DCESEN: Data CRC Error Interrupt + * @arg SDIOC_ERROR_INT_DTOESEN: Data Timeout Error Interrupt + * @arg SDIOC_ERROR_INT_CIESEN: Command Index Error Interrupt + * @arg SDIOC_ERROR_INT_CEBESEN: Command End Bit Error Interrupt + * @arg SDIOC_ERROR_INT_CCESEN: Command CRC Error Interrupt + * @arg SDIOC_ERROR_INT_CTOESEN: Command Timeout Error Interrupt + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_IntCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_NORMAL_ERROR_INT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u16NormalInt = (uint16_t)(u32IntSrc & 0xFFFFU); + u16ErrorInt = (uint16_t)((u32IntSrc >> 16U) & 0xFFFFU); + + if (Disable != enNewSta) + { + if (0U != u16NormalInt) + { + SET_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) + { + SET_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } + else + { + if (0U != u16NormalInt) + { + CLEAR_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt); + } + if (0U != u16ErrorInt) + { + CLEAR_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt); + } + } +} + +/** + * @brief Get interrupt enable state. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32IntSrc Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_NORMAL_INT_CINTSEN: Card Interrupt + * @arg SDIOC_NORMAL_INT_CRMSEN: Card Removal Interrupt + * @arg SDIOC_NORMAL_INT_CISTSEN: Card Insertion Interrupt + * @arg SDIOC_NORMAL_INT_BRRSEN: Buffer Read Ready Interrupt + * @arg SDIOC_NORMAL_INT_BWRSEN: Buffer Write Ready Interrupt + * @arg SDIOC_NORMAL_INT_BGESEN: Block Gap Event Interrupt + * @arg SDIOC_NORMAL_INT_TCSEN: Transfer Complete Interrupt + * @arg SDIOC_NORMAL_INT_CCSEN: Command Complete Interrupt + * @arg SDIOC_ERROR_INT_ACESEN: Auto CMD12 Error Interrupt + * @arg SDIOC_ERROR_INT_DEBESEN: Data End Bit Error Interrupt + * @arg SDIOC_ERROR_INT_DCESEN: Data CRC Error Interrupt + * @arg SDIOC_ERROR_INT_DTOESEN: Data Timeout Error Interrupt + * @arg SDIOC_ERROR_INT_CIESEN: Command Index Error Interrupt + * @arg SDIOC_ERROR_INT_CEBESEN: Command End Bit Error Interrupt + * @arg SDIOC_ERROR_INT_CCESEN: Command CRC Error Interrupt + * @arg SDIOC_ERROR_INT_CTOESEN: Command Timeout Error Interrupt + * @retval An en_functional_state_t enumeration value: + * - Enable: The interrupt is enable + * - Disable: The interrupt is disable + */ +en_functional_state_t SDIOC_GetIntEnableState(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + en_functional_state_t enIntSta = Disable; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_NORMAL_ERROR_INT(u32IntSrc)); + + u16NormalInt = (uint16_t)(u32IntSrc & 0xFFFFU); + u16ErrorInt = (uint16_t)((u32IntSrc >> 16U) & 0xFFFFU); + + if (0U != u16NormalInt) + { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTSGEN, u16NormalInt))) + { + enIntSta = Enable; + } + } + if (0U != u16ErrorInt) + { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTSGEN, u16ErrorInt))) + { + enIntSta = Enable; + } + } + + return enIntSta; +} + +/** + * @brief Get interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_NORMAL_INT_FLAG_EI: Error Interrupt Status + * @arg SDIOC_NORMAL_INT_FLAG_CINT: Card Interrupt status + * @arg SDIOC_NORMAL_INT_FLAG_CRM: Card Removal status + * @arg SDIOC_NORMAL_INT_FLAG_CIST: Card Insertion status + * @arg SDIOC_NORMAL_INT_FLAG_BRR: Buffer Read Ready status + * @arg SDIOC_NORMAL_INT_FLAG_BWR: Buffer Write Ready status + * @arg SDIOC_NORMAL_INT_FLAG_BGE: Block Gap Event status + * @arg SDIOC_NORMAL_INT_FLAG_TC: Transfer Complete status + * @arg SDIOC_NORMAL_INT_FLAG_CC: Command Complete status + * @arg SDIOC_ERROR_INT_FLAG_ACE: Auto CMD12 Error Status + * @arg SDIOC_ERROR_INT_FLAG_DEBE: Data End Bit Error status + * @arg SDIOC_ERROR_INT_FLAG_DCE: Data CRC Error status + * @arg SDIOC_ERROR_INT_FLAG_DTOE: Data Timeout Error status + * @arg SDIOC_ERROR_INT_FLAG_CIE: Command Index Error status + * @arg SDIOC_ERROR_INT_FLAG_CEBE: Command End Bit Error status + * @arg SDIOC_ERROR_INT_FLAG_CCE: Command CRC Error status + * @arg SDIOC_ERROR_INT_FLAG_CTOE: Command Timeout Error status + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t SDIOC_GetIntStatus(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_NORMAL_ERROR_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)((u32Flag >> 16U) & 0xFFFFU); + + if (0U != u16NormalFlag) + { + if (0U != (READ_REG16_BIT(SDIOCx->NORINTST, u16NormalFlag))) + { + enFlagSta = Set; + } + } + if (0U != u16ErrorFlag) + { + if (0U != (READ_REG16_BIT(SDIOCx->ERRINTST, u16ErrorFlag))) + { + enFlagSta = Set; + } + } + + return enFlagSta; +} + +/** + * @brief Clear interrupt flag status. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Flag Normal and error interrupts flag + * This parameter can be one or any combination of the following values: + * @arg SDIOC_NORMAL_INT_FLAG_CRM: Card Removal status + * @arg SDIOC_NORMAL_INT_FLAG_CIST: Card Insertion status + * @arg SDIOC_NORMAL_INT_FLAG_BRR: Buffer Read Ready status + * @arg SDIOC_NORMAL_INT_FLAG_BWR: Buffer Write Ready status + * @arg SDIOC_NORMAL_INT_FLAG_BGE: Block Gap Event status + * @arg SDIOC_NORMAL_INT_FLAG_TC: Transfer Complete status + * @arg SDIOC_NORMAL_INT_FLAG_CC: Command Complete status + * @arg SDIOC_ERROR_INT_FLAG_ACE: Auto CMD12 Error Status + * @arg SDIOC_ERROR_INT_FLAG_DEBE: Data End Bit Error status + * @arg SDIOC_ERROR_INT_FLAG_DCE: Data CRC Error status + * @arg SDIOC_ERROR_INT_FLAG_DTOE: Data Timeout Error status + * @arg SDIOC_ERROR_INT_FLAG_CIE: Command Index Error status + * @arg SDIOC_ERROR_INT_FLAG_CEBE: Command End Bit Error status + * @arg SDIOC_ERROR_INT_FLAG_CCE: Command CRC Error status + * @arg SDIOC_ERROR_INT_FLAG_CTOE: Command Timeout Error status + * @retval None + */ +void SDIOC_ClearIntStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + uint16_t u16NormalFlag; + uint16_t u16ErrorFlag; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_CLEAR_NORMAL_ERROR_INT_FLAG(u32Flag)); + + u16NormalFlag = (uint16_t)(u32Flag & 0xFFFFU); + u16ErrorFlag = (uint16_t)((u32Flag >> 16U) & 0xFFFFU); + if (0U != u16NormalFlag) + { + WRITE_REG16(SDIOCx->NORINTST, u16NormalFlag); + } + if (0U != u16ErrorFlag) + { + WRITE_REG16(SDIOCx->ERRINTST, u16ErrorFlag); + } +} + +/** + * @brief Enable or disable interrupt status. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32IntSrc Normal and error interrupts source + * This parameter can be one or any combination of the following values: + * @arg SDIOC_NORMAL_INT_CINTSEN: Card Interrupt + * @arg SDIOC_NORMAL_INT_CRMSEN: Card Removal Interrupt + * @arg SDIOC_NORMAL_INT_CISTSEN: Card Insertion Interrupt + * @arg SDIOC_NORMAL_INT_BRRSEN: Buffer Read Ready Interrupt + * @arg SDIOC_NORMAL_INT_BWRSEN: Buffer Write Ready Interrupt + * @arg SDIOC_NORMAL_INT_BGESEN: Block Gap Event Interrupt + * @arg SDIOC_NORMAL_INT_TCSEN: Transfer Complete Interrupt + * @arg SDIOC_NORMAL_INT_CCSEN: Command Complete Interrupt + * @arg SDIOC_ERROR_INT_ACESEN: Auto CMD12 Error Interrupt + * @arg SDIOC_ERROR_INT_DEBESEN: Data End Bit Error Interrupt + * @arg SDIOC_ERROR_INT_DCESEN: Data CRC Error Interrupt + * @arg SDIOC_ERROR_INT_DTOESEN: Data Timeout Error Interrupt + * @arg SDIOC_ERROR_INT_CIESEN: Command Index Error Interrupt + * @arg SDIOC_ERROR_INT_CEBESEN: Command End Bit Error Interrupt + * @arg SDIOC_ERROR_INT_CCESEN: Command CRC Error Interrupt + * @arg SDIOC_ERROR_INT_CTOESEN: Command Timeout Error Interrupt + * @param [in] enNewSta The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void SDIOC_IntStatusCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32IntSrc, en_functional_state_t enNewSta) +{ + uint16_t u16NormalInt; + uint16_t u16ErrorInt; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_NORMAL_ERROR_INT(u32IntSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewSta)); + + u16NormalInt = (uint16_t)(u32IntSrc & 0xFFFFU); + u16ErrorInt = (uint16_t)((u32IntSrc >> 16U) & 0xFFFFU); + + if (Disable != enNewSta) + { + if (0U != u16NormalInt) + { + SET_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) + { + SET_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } + else + { + if (0U != u16NormalInt) + { + CLEAR_REG16_BIT(SDIOCx->NORINTSTEN, u16NormalInt); + } + if (0U != u16ErrorInt) + { + CLEAR_REG16_BIT(SDIOCx->ERRINTSTEN, u16ErrorInt); + } + } +} + +/** + * @brief Get Host status. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Flag Host flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_HOST_FLAG_CMDL: CMD Line Level status + * @arg SDIOC_HOST_FLAG_DATL: DAT[3:0] Line Level status + * @arg SDIOC_HOST_FLAG_DATL_D0: DAT[0] Line Level status + * @arg SDIOC_HOST_FLAG_DATL_D1: DAT[1] Line Level status + * @arg SDIOC_HOST_FLAG_DATL_D2: DAT[2] Line Level status + * @arg SDIOC_HOST_FLAG_DATL_D3: DAT[3] Line Level status + * @arg SDIOC_HOST_FLAG_WPL: Write Protect Line Level status + * @arg SDIOC_HOST_FLAG_CDL: Card Detect Line Level status + * @arg SDIOC_HOST_FLAG_CSS: Device Stable Status + * @arg SDIOC_HOST_FLAG_CIN: Device Inserted status + * @arg SDIOC_HOST_FLAG_BRE: Data buffer full status + * @arg SDIOC_HOST_FLAG_BWE: Data buffer empty status + * @arg SDIOC_HOST_FLAG_RTA: Read operation status + * @arg SDIOC_HOST_FLAG_WTA: Write operation status + * @arg SDIOC_HOST_FLAG_DA: DAT Line transfer status + * @arg SDIOC_HOST_FLAG_CID: Command Inhibit with data status + * @arg SDIOC_HOST_FLAG_CIC: Command Inhibit status + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t SDIOC_GetHostStatus(const M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_GET_HOST_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(SDIOCx->PSTAT, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Get auto CMD12 error status. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u16Flag Auto CMD12 error flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_AUTO_CMD_ERROR_FLAG_CMDE: Command Not Issued By Auto CMD12 Error Status + * @arg SDIOC_AUTO_CMD_ERROR_FLAG_IE: Auto CMD12 Index Error status + * @arg SDIOC_AUTO_CMD_ERROR_FLAG_EBE: Auto CMD12 End Bit Error status + * @arg SDIOC_AUTO_CMD_ERROR_FLAG_CE: Auto CMD12 CRC Error status + * @arg SDIOC_AUTO_CMD_ERROR_FLAG_TOE: Auto CMD12 Timeout Error status + * @arg SDIOC_AUTO_CMD_ERROR_FLAG_NE: Auto CMD12 Not Executed status + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t SDIOC_GetAutoCmdErrorStatus(const M4_SDIOC_TypeDef *SDIOCx, uint16_t u16Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_AUTO_CMD_ERROR_FLAG(u16Flag)); + + if (0U != (READ_REG16_BIT(SDIOCx->ATCERRST, u16Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Force the specified auto CMD12 error event flag. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u16CmdFlag Auto CMD12 error flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_AUTO_CMD_ERROR_FCMDE: Force Event for Command Not Issued By Auto CMD12 Error + * @arg SDIOC_FORCE_AUTO_CMD_ERROR_FIE: Force Event for Auto CMD12 Index Error + * @arg SDIOC_FORCE_AUTO_CMD_ERROR_FEBE: Force Event for Auto CMD12 End Bit Error + * @arg SDIOC_FORCE_AUTO_CMD_ERROR_FCE: Force Event for Auto CMD12 CRC Error + * @arg SDIOC_FORCE_AUTO_CMD_ERROR_FTOE: Force Event for Auto CMD12 Timeout Error + * @arg SDIOC_FORCE_AUTO_CMD_ERROR_FNE: Force Event for Auto CMD12 Not Executed + * @retval None + */ +void SDIOC_ForceAutoCmdErrorEvent(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16CmdFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_AUTO_CMD_FLAG(u16CmdFlag)); + + WRITE_REG16(SDIOCx->FEA, u16CmdFlag); +} + +/** + * @brief Force the specified error interrupt event flag. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u16IntFlag Error interrupt flag + * This parameter can be one or any combination the following values: + * @arg SDIOC_FORCE_ERROR_INT_FACE: Force Event for Auto CMD12 Error + * @arg SDIOC_FORCE_ERROR_INT_FDEBE: Force Event for Data End Bit Error + * @arg SDIOC_FORCE_ERROR_INT_FDCE: Force Event for Data CRC Error + * @arg SDIOC_FORCE_ERROR_INT_FDTOE: Force Event for Data Timeout Error + * @arg SDIOC_FORCE_ERROR_INT_FCIE: Force Event for Command Index Error + * @arg SDIOC_FORCE_ERROR_INT_FCEBE: Force Event for Command End Bit Error + * @arg SDIOC_FORCE_ERROR_INT_FCCE: Force Event for Command CRC Error + * @arg SDIOC_FORCE_ERROR_INT_FCTOE: Force Event for Command Timeout Error + * @retval None + */ +void SDIOC_ForceErrorInterruptEvent(M4_SDIOC_TypeDef *SDIOCx, uint16_t u16IntFlag) +{ + /* Check parameters */ + DDL_ASSERT(IS_SDIOC_UNIT(SDIOCx)); + DDL_ASSERT(IS_SDIOC_FORCE_ERROR_INT_FLAG(u16IntFlag)); + + WRITE_REG16(SDIOCx->FEE, u16IntFlag); +} + +/** + * @brief Send the Go Idle State command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD0_GoIdleState(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + *pu32ErrSta = SDMMC_ERROR_NONE; + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_CMD0_GO_IDLE_STATE; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_NO; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdError(SDIOCx); + } + } + + return enRet; +} + +/** + * @brief Send the Send CID command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD2_AllSendCID(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_CMD2_ALL_SEND_CID; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R2; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp2(SDIOCx, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the command for asking the card to publish a new relative address(RCA). + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu16RCA Pointer to the new RCA value + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu16RCA == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD3_SendRelativeAddr(M4_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if ((NULL == pu16RCA) || (NULL == pu32ErrSta)) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_CMD3_SEND_RELATIVE_ADDR; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp6(SDIOCx, pu16RCA, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Checks switchable function and switch card function. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD6_SwitchFunc(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + uint32_t u32SdMode; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32Argument; + stcCmdInit.u16CmdIndex = SDIOC_CMD6_SWITCH_FUNC; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MODE_SD != u32SdMode) /* MMC mode */ + { + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1B_R5B; + } + else + { + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + } + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + if (SDIOC_MODE_SD != u32SdMode) /* MMC mode */ + { + enRet = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + else + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + } + + return enRet; +} + +/** + * @brief Send the Select Deselect command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD7_SelectDeselectCard(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32RCA; + stcCmdInit.u16CmdIndex = SDIOC_CMD7_SELECT_DESELECT_CARD; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1B_R5B; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Interface Condition command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD8_SendInterfaceCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + uint32_t u32SdMode; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Argument: - [31:12]: Reserved (shall be set to '0') + - [11:8]: Supply Voltage (VHS) 0x1 (Range: 2.7-3.6 V) + - [7:0]: Check Pattern (recommended 0xAA) */ + stcCmdInit.u32Argument = SDMMC_CMD8_CHECK_PATTERN; + stcCmdInit.u16CmdIndex = SDIOC_CMD8_SEND_IF_COND; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + u32SdMode = SDIOC_GetMode(SDIOCx); + if (SDIOC_MODE_SD != u32SdMode) /* MMC mode */ + { + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + } + else + { + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + } + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + if (SDIOC_MODE_SD != u32SdMode) /* MMC mode */ + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + else + { + enRet = SDMMC_GetCmdResp7(SDIOCx, pu32ErrSta); + } + } + } + + return enRet; +} + +/** + * @brief Send the Send CSD command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD9_SendCSD(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32RCA; + stcCmdInit.u16CmdIndex = SDIOC_CMD9_SEND_CSD; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R2; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp2(SDIOCx, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Stop Transfer command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD12_StopTransmission(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_CMD12_STOP_TRANSMISSION; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1B_R5B; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_CMD_TIMEOUT * 1000UL, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Status command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32RCA Relative Card Address(RCA) + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32RCA, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32RCA; + stcCmdInit.u16CmdIndex = SDIOC_CMD13_SEND_STATUS; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Data Block Lenght command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32BlockLen Block length + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD16_SetBlockLength(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BlockLen, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32BlockLen; + stcCmdInit.u16CmdIndex = SDIOC_CMD16_SET_BLOCKLEN; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Read Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD17_ReadSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32ReadAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD17_READ_SINGLE_BLOCK; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Read Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32ReadAddr Data address + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD18_ReadMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32ReadAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32ReadAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD18_READ_MULTIPLE_BLOCK; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Write Single Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD24_WriteSingleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32WriteAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD24_WRITE_SINGLE_BLOCK; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Write Multi Block command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32WriteAddr Data address + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD25_WriteMultipleBlock(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32WriteAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32WriteAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD25_WRITE_MULTIPLE_BLOCK; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Start Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD32_EraseBlockStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32StartAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD32_ERASE_WR_BLK_START; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the End Address Erase command for SD and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD33_EraseBlockEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32EndAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD33_ERASE_WR_BLK_END; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Erase command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD38_Erase(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_CMD38_ERASE; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1B_R5B; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1Busy(SDIOCx, SDMMC_MAX_ERASE_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Application command to verify that that the next command + * is an application specific command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD55_AppCmd(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32Argument; + stcCmdInit.u16CmdIndex = SDIOC_CMD55_APP_CMD; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Bus Width command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32BusWidth The data bus width + * This parameter can be one of the following values: + * @arg SDMMC_SCR_BUS_WIDTH_1BIT: 1 bit bus + * @arg SDMMC_SCR_BUS_WIDTH_4BIT: 4 bits bus + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_ACMD6_SetBusWidth(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32BusWidth, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32BusWidth; + stcCmdInit.u16CmdIndex = SDIOC_ACMD6_SET_BUS_WIDTH; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Status register command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_ACMD13_SendStatus(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_ACMD13_SD_STATUS; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the command asking the accessed card to send its operating condition register(OCR). + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_ACMD41_SendOperatCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32Argument | SDMMC_ACMD41_VOLTAGE_WINDOW; + stcCmdInit.u16CmdIndex = SDIOC_ACMD41_SD_APP_OP_COND; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R3_R4; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp3(SDIOCx, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Send SCR command and check the response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_ACMD51_SendSCR(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = 0UL; + stcCmdInit.u16CmdIndex = SDIOC_ACMD51_SEND_SCR; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_ENABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Sends host capacity support information command. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Argument Argument used for the command. + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD1_SendOperatCond(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Argument, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32Argument; + stcCmdInit.u16CmdIndex = SDIOC_CMD1_SEND_OP_COND; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R3_R4; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp3(SDIOCx, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the Start Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32StartAddr The start address will be erased + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD35_EraseGroupStartAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32StartAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32StartAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD35_ERASE_GRP_START; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Send the End Address Erase command and check the response + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32EndAddr The end address will be erased + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorInvalidParameter: SDIOCx == NULL or pu32ErrSta == NULL + * - ErrorTimeout: Wait timeout + */ +en_result_t SDMMC_CMD36_EraseGroupEndAddr(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32EndAddr, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + stc_sdioc_cmd_init_t stcCmdInit; + + if (NULL == pu32ErrSta) + { + enRet = ErrorInvalidParameter; + } + else + { + stcCmdInit.u32Argument = u32EndAddr; + stcCmdInit.u16CmdIndex = SDIOC_CMD36_ERASE_GRP_END; + stcCmdInit.u16CmdType = SDIOC_CMD_TYPE_NORMAL; + stcCmdInit.u16DataLineEn = SDIOC_DATA_LINE_DISABLE; + stcCmdInit.u16RespType = SDIOC_RESOPNE_TYPE_R1_R5_R6_R7; + enRet = SDIOC_SendCommand(SDIOCx, &stcCmdInit); + /* Check for error conditions */ + if (Ok == enRet) + { + enRet = SDMMC_GetCmdResp1(SDIOCx, SDMMC_CMD_TIMEOUT, pu32ErrSta); + } + } + + return enRet; +} + +/** + * @brief Wait for command response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32CheckFlag Check flags + * This parameter can be one or any combination the following values: + * @arg SDIOC_NORMAL_INT_FLAG_CC: Command Complete status + * @arg SDIOC_ERROR_INT_FLAG_CIE: Command Index Error status + * @arg SDIOC_ERROR_INT_FLAG_CEBE: Command End Bit Error status + * @arg SDIOC_ERROR_INT_FLAG_CCE: Command CRC Error status + * @arg SDIOC_ERROR_INT_FLAG_CTOE: Command Timeout Error status + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_WaitResponse(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32CheckFlag, uint32_t u32Timeout, uint32_t *pu32ErrSta) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + uint32_t u32Temp; + + *pu32ErrSta = 0UL; + /* The u32Timeout is expressed in ms */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (Reset == SDIOC_GetIntStatus(SDIOCx, u32CheckFlag)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (Ok == enRet) + { + enRet = Error; + u32Temp = CLEAR_REG32_BIT(u32CheckFlag, SDIOC_NORMAL_INT_FLAG_CC); + if (Reset == SDIOC_GetIntStatus(SDIOCx, u32Temp)) + { + /* No error flag set */ + *pu32ErrSta = SDMMC_ERROR_NONE; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_ERROR_INT_STATIC_FLAGS); + enRet = Ok; + } + else if ((Reset != SDIOC_GetIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CIE)) && + (SDIOC_ERROR_INT_FLAG_CIE == (u32CheckFlag & SDIOC_ERROR_INT_FLAG_CIE))) + { + *pu32ErrSta = SDMMC_ERROR_CMD_INDEX; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CIE); + } + else if ((Reset != SDIOC_GetIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CEBE)) && + (SDIOC_ERROR_INT_FLAG_CEBE == (u32CheckFlag & SDIOC_ERROR_INT_FLAG_CEBE))) + { + *pu32ErrSta = SDMMC_ERROR_CMD_STOP_BIT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CEBE); + } + else if ((Reset != SDIOC_GetIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CCE)) && + (SDIOC_ERROR_INT_FLAG_CCE == (u32CheckFlag & SDIOC_ERROR_INT_FLAG_CCE))) + { + *pu32ErrSta = SDMMC_ERROR_CMD_CRC_FAIL; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CCE); + } + else + { + *pu32ErrSta = SDMMC_ERROR_CMD_TIMEOUT; + SDIOC_ClearIntStatus(SDIOCx, SDIOC_ERROR_INT_FLAG_CTOE); + } + } + + return enRet; +} + +/** + * @brief Checks for error conditions for no response command. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @retval An en_result_t enumeration value: + * - Ok: Command send completed + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdError(M4_SDIOC_TypeDef *SDIOCx) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + /* The SDMMC_CMD_TIMEOUT is expressed in ms */ + u32Count = SDMMC_CMD_TIMEOUT * (HCLK_VALUE / 20000UL); + while (Reset == SDIOC_GetIntStatus(SDIOCx, SDIOC_NORMAL_INT_FLAG_CC)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + if (Ok == enRet) + { + SDIOC_ClearIntStatus(SDIOCx, SDIOC_ERROR_INT_STATIC_FLAGS); + } + + return enRet; +} + +/** + * @brief Checks for error conditions for R1 response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdResp1(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + uint32_t u32RespVal; + + enRet = SDMMC_WaitResponse(SDIOCx, + (SDIOC_NORMAL_INT_FLAG_CC | SDIOC_ERROR_INT_FLAG_CIE | SDIOC_ERROR_INT_FLAG_CEBE | + SDIOC_ERROR_INT_FLAG_CCE | SDIOC_ERROR_INT_FLAG_CTOE), u32Timeout, pu32ErrSta); + + if (Ok == enRet) + { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESPONSE_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_CARD_ERROR_BITS_MASK)) + { + *pu32ErrSta = u32RespVal & SDMMC_CARD_ERROR_BITS_MASK; + enRet = Error; + } + } + + return enRet; +} + +/** + * @brief Checks for error conditions for R1 response with busy. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [in] u32Timeout Timeout time(ms) for waiting SDIOC + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdResp1Busy(M4_SDIOC_TypeDef *SDIOCx, uint32_t u32Timeout, uint32_t *pu32ErrSta) +{ + __IO uint32_t u32Count; + en_result_t enRet; + uint32_t u32RespVal; + + enRet = SDMMC_WaitResponse(SDIOCx, + (SDIOC_NORMAL_INT_FLAG_CC | SDIOC_ERROR_INT_FLAG_CIE | SDIOC_ERROR_INT_FLAG_CEBE | + SDIOC_ERROR_INT_FLAG_CCE | SDIOC_ERROR_INT_FLAG_CTOE), u32Timeout, pu32ErrSta); + + if (Ok == enRet) + { + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESPONSE_REG_BIT0_31, &u32RespVal); + if (0UL != (u32RespVal & SDMMC_CARD_ERROR_BITS_MASK)) + { + *pu32ErrSta = u32RespVal & SDMMC_CARD_ERROR_BITS_MASK; + enRet = Error; + } + else + { + /* Wait for busy status to release */ + u32Count = u32Timeout * (HCLK_VALUE / 20000UL); + while (Reset == SDIOC_GetHostStatus(SDIOCx, SDIOC_HOST_FLAG_DATL_D0)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + } + } + + return enRet; +} + +/** + * @brief Checks for error conditions for R2(CID or CSD) response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdResp2(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + return SDMMC_WaitResponse(SDIOCx, + (SDIOC_NORMAL_INT_FLAG_CC | SDIOC_ERROR_INT_FLAG_CEBE | SDIOC_ERROR_INT_FLAG_CCE | + SDIOC_ERROR_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrSta); +} + +/** + * @brief Checks for error conditions for R3(OCR) response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdResp3(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + return SDMMC_WaitResponse(SDIOCx, + (SDIOC_NORMAL_INT_FLAG_CC | SDIOC_ERROR_INT_FLAG_CEBE | SDIOC_ERROR_INT_FLAG_CTOE), + SDMMC_CMD_TIMEOUT, pu32ErrSta); +} + +/** + * @brief Checks for error conditions for R6(RCA) response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu16RCA Pointer to a value of device RCA + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdResp6(M4_SDIOC_TypeDef *SDIOCx, uint16_t *pu16RCA, uint32_t *pu32ErrSta) +{ + en_result_t enRet; + uint32_t u32RespVal; + + enRet = SDMMC_WaitResponse(SDIOCx, + (SDIOC_NORMAL_INT_FLAG_CC | SDIOC_ERROR_INT_FLAG_CIE | SDIOC_ERROR_INT_FLAG_CEBE | + SDIOC_ERROR_INT_FLAG_CCE | SDIOC_ERROR_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrSta); + + if (Ok == enRet) + { + enRet = Error; + /* Fetch has received a response. */ + (void)SDIOC_GetResponse(SDIOCx, SDIOC_RESPONSE_REG_BIT0_31, &u32RespVal); + if (0UL == (u32RespVal & (SDMMC_R6_GENERAL_UNKNOWN_ERROR | SDMMC_R6_ILLEGAL_CMD | SDMMC_R6_COM_CRC_FAILED))) + { + enRet = Ok; + *pu16RCA = (uint16_t)((u32RespVal >> 16U) & 0xFFFFUL); + } + else if (SDMMC_R6_GENERAL_UNKNOWN_ERROR == (u32RespVal & SDMMC_R6_GENERAL_UNKNOWN_ERROR)) + { + *pu32ErrSta = SDMMC_ERROR_GENERAL_UNKNOWN_ERR; + } + else if (SDMMC_R6_ILLEGAL_CMD == (u32RespVal & SDMMC_R6_ILLEGAL_CMD)) + { + *pu32ErrSta = SDMMC_ERROR_ILLEGAL_CMD; + } + else + { + *pu32ErrSta = SDMMC_ERROR_COM_CRC_FAILED; + } + } + + return enRet; +} + +/** + * @brief Checks for error conditions for R7 response. + * @param [in] SDIOCx Pointer to SDIOC instance register base + * This parameter can be one of the following values: + * @arg M4_SDIOC1: SDIOC unit 1 instance register base + * @arg M4_SDIOC2: SDIOC unit 2 instance register base + * @param [out] pu32ErrSta Pointer to the error state value + * @retval An en_result_t enumeration value: + * - Ok: The response is normal received + * - Error: Refer to pu32ErrSta for the reason of error + * - ErrorTimeout: Wait timeout + */ +static en_result_t SDMMC_GetCmdResp7(M4_SDIOC_TypeDef *SDIOCx, uint32_t *pu32ErrSta) +{ + return SDMMC_WaitResponse(SDIOCx, + (SDIOC_NORMAL_INT_FLAG_CC | SDIOC_ERROR_INT_FLAG_CIE | SDIOC_ERROR_INT_FLAG_CEBE | + SDIOC_ERROR_INT_FLAG_CCE | SDIOC_ERROR_INT_FLAG_CTOE), SDMMC_CMD_TIMEOUT, pu32ErrSta); +} + +/** + * @} + */ + +#endif /* DDL_SDIOC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_smc.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_smc.c new file mode 100644 index 0000000000000000000000000000000000000000..89cf8e7c42480bd370510513e59c79bf98308582 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_smc.c @@ -0,0 +1,557 @@ +/** + ******************************************************************************* + * @file hc32f4a0_smc.c + * @brief This file provides firmware functions to manage the EXMC SMC + * (External Memory Controller: Static Memory Controller). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-14 Hongjh Merge API from EXMC_SMC_Enable/Disable to EXMC_SMC_Cmd + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_smc.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_EXMC_SMC EXMC_SMC + * @brief Static Memory Controller Driver Library + * @{ + */ + +#if (DDL_SMC_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Local_Macros Static Memory Controller Local Macros + * @{ + */ + +/** + * @defgroup EXMC_SMC_Check_Parameters_Validity EXMC SMC Check Parameters Validity + * @{ + */ + +#define IS_EXMC_SMC_MEM_WIDTH(x) \ +( (EXMC_SMC_MEMORY_WIDTH_16BIT == (x)) || \ + (EXMC_SMC_MEMORY_WIDTH_32BIT == (x))) + +#define IS_EXMC_SMC_MEM_READ_MODE(x) \ +( (EXMC_SMC_MEM_READ_SYNC == (x)) || \ + (EXMC_SMC_MEM_READ_ASYNC == (x))) + +#define IS_EXMC_SMC_MEM_WRITE_MODE(x) \ +( (EXMC_SMC_MEM_WRITE_SYNC == (x)) || \ + (EXMC_SMC_MEM_WRITE_ASYNC == (x))) + +#define IS_EXMC_SMC_CHIP(x) \ +( (EXMC_SMC_CHIP_0 == (x)) || \ + (EXMC_SMC_CHIP_1 == (x)) || \ + (EXMC_SMC_CHIP_2 == (x)) || \ + (EXMC_SMC_CHIP_3 == (x))) + +#define IS_EXMC_SMC_MEM_READ_BURST(x) \ +( (EXMC_SMC_MEM_READ_BURST_1 == (x)) || \ + (EXMC_SMC_MEM_READ_BURST_4 == (x)) || \ + (EXMC_SMC_MEM_READ_BURST_8 == (x)) || \ + (EXMC_SMC_MEM_READ_BURST_16 == (x)) || \ + (EXMC_SMC_MEM_READ_BURST_32 == (x)) || \ + (EXMC_SMC_MEM_READ_BURST_CONTINUOUS == (x))) + +#define IS_EXMC_SMC_MEM_WRITE_BURST(x) \ +( (EXMC_SMC_MEM_WRITE_BURST_1 == (x)) || \ + (EXMC_SMC_MEM_WRITE_BURST_4 == (x)) || \ + (EXMC_SMC_MEM_WRITE_BURST_8 == (x)) || \ + (EXMC_SMC_MEM_WRITE_BURST_16 == (x)) || \ + (EXMC_SMC_MEM_WRITE_BURST_32 == (x)) || \ + (EXMC_SMC_MEM_WRITE_BURST_CONTINUOUS == (x))) + +#define IS_EXMC_SMC_BLS_SYNC(x) \ +( (EXMC_SMC_BLS_SYNC_CS == (x)) || \ + (EXMC_SMC_BLS_SYNC_WE == (x))) + +#define IS_EXMC_SMC_BAA_PORT(x) \ +( (EXMC_SMC_BAA_PORT_DISABLE == (x)) || \ + (EXMC_SMC_BAA_PORT_ENABLE == (x))) + +#define IS_EXMC_SMC_ADV_PORT(x) \ +( (EXMC_SMC_ADV_PORT_DISABLE == (x)) || \ + (EXMC_SMC_ADV_PORT_ENABLE == (x))) + +#define IS_EXMC_SMC_CMD(x) \ +( (EXMC_SMC_CMD_MDREGCONFIG == (x)) || \ + (EXMC_SMC_CMD_UPDATEREGS == (x)) || \ + (EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS == (x))) + +#define IS_EXMC_SMC_CRE_POLARITY(x) \ +( (EXMC_SMC_CRE_POLARITY_LOW == (x)) || \ + (EXMC_SMC_CRE_POLARITY_HIGH == (x))) + +#define IS_EXMC_SMC_ADDRESS(match, mask) ((~(((mask) ^ (match)) << 24UL)) <= 0x7FFFFFFFUL) + +#define IS_EXMC_SMC_CS_ADDRESS_MASK(x) (((x) >= 0xE0UL) && ((x) <= 0XFFUL)) + +#define IS_EXMC_SMC_CS_ADDRESS_MATCH(x) (((x) >= 0x60UL) && ((x) <= 0x7FUL)) + +#define IS_EXMC_SMC_REFRESH_PERIOD(x) ((x) <= SMC_RFTR_REFPRD) + +#define IS_EXMC_SMC_CMDADD(x) ((x) <= 0xFFFFFUL) + +#define IS_EXMC_SMC_TIMING_RC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_SMC_TIMING_WC_CYCLE(x) ((x) <= 0x0FUL) + +#define IS_EXMC_SMC_TIMING_CEOE_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_WP_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_PC_CYCLE(x) ((x) <= 7UL) + +#define IS_EXMC_SMC_TIMING_TR_CYCLE(x) ((x) <= 7UL) + +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Register EXMC sMC Register + * @{ + */ +#define EXMC_SMC_CPSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&M4_SMC->CPSR0)) + (0x20UL * (__CHIPx__)))) +#define EXMC_SMC_TMSRx(__CHIPx__) ((__IO uint32_t *)(((uint32_t)(&M4_SMC->TMSR0)) + (0x20UL * (__CHIPx__)))) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_Register_Bit_Mask EXMC SMC Register Bit Mask + * @{ + */ +#define SMC_CSCR0_ADDMSKx_POS(__CHIPx__) ((__CHIPx__) << 3UL) +#define SMC_CSCR0_ADDMSKx(__CHIPx__) (SMC_CSCR0_ADDMSK0 << SMC_CSCR0_ADDMSKx_POS((__CHIPx__))) + +#define SMC_CSCR1_ADDMATx_POS(__CHIPx__) ((__CHIPx__) << 3UL) +#define SMC_CSCR1_ADDMATx(__CHIPx__) (SMC_CSCR1_ADDMAT0 << SMC_CSCR1_ADDMATx_POS((__CHIPx__))) +/** + * @} + */ + +/** + * @defgroup EXMC_SMC_MUX_Selection EXMC SMC MUX Selection + * @{ + */ +#define EXMC_SMC_MUX_DISABLE (0x00000300UL) +#define EXMC_SMC_MUX_ENABLE (0x00000300UL | SMC_BACR_MUXMD) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup EXMC_SMC_Global_Functions Static Memory Controller Global Functions + * @{ + */ + +/** + * @brief Initialize EXMC SMC function. + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CHIP_0: Chip 0 + * @arg EXMC_SMC_CHIP_1: Chip 1 + * @arg EXMC_SMC_CHIP_2: Chip 2 + * @arg EXMC_SMC_CHIP_3: Chip 3 + * @param [in] pstcInit Pointer to a @ref stc_exmc_smc_init_t structure (EXMC SMC function configuration structure). + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EXMC_SMC_Init(uint32_t u32Chip, const stc_exmc_smc_init_t *pstcInit) +{ + uint32_t u32RegVal; + en_result_t enRet = ErrorInvalidParameter; + + /* Check the pointer pstcInit */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + DDL_ASSERT(IS_EXMC_SMC_MEM_READ_MODE(pstcInit->stcChipCfg.u32ReadMode)); + DDL_ASSERT(IS_EXMC_SMC_MEM_WRITE_MODE(pstcInit->stcChipCfg.u32WriteMode)); + DDL_ASSERT(IS_EXMC_SMC_MEM_READ_BURST(pstcInit->stcChipCfg.u32ReadBurstLen)); + DDL_ASSERT(IS_EXMC_SMC_MEM_WRITE_BURST(pstcInit->stcChipCfg.u32WriteBurstLen)); + DDL_ASSERT(IS_EXMC_SMC_MEM_WIDTH(pstcInit->stcChipCfg.u32SmcMemWidth)); + DDL_ASSERT(IS_EXMC_SMC_BAA_PORT(pstcInit->stcChipCfg.u32BAA)); + DDL_ASSERT(IS_EXMC_SMC_ADV_PORT(pstcInit->stcChipCfg.u32ADV)); + DDL_ASSERT(IS_EXMC_SMC_BLS_SYNC(pstcInit->stcChipCfg.u32BLS)); + DDL_ASSERT(IS_EXMC_SMC_CS_ADDRESS_MATCH(pstcInit->stcChipCfg.u32AddressMatch)); + DDL_ASSERT(IS_EXMC_SMC_CS_ADDRESS_MASK(pstcInit->stcChipCfg.u32AddressMask)); + DDL_ASSERT(IS_EXMC_SMC_ADDRESS(pstcInit->stcChipCfg.u32AddressMatch, pstcInit->stcChipCfg.u32AddressMask)); + + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcInit->stcTimingCfg.u32RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WC_CYCLE(pstcInit->stcTimingCfg.u32WC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_CEOE_CYCLE(pstcInit->stcTimingCfg.u32CEOE)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WP_CYCLE(pstcInit->stcTimingCfg.u32WP)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcInit->stcTimingCfg.u32RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_TR_CYCLE(pstcInit->stcTimingCfg.u32TR)); + + /* Set SMC timing.*/ + u32RegVal = ((pstcInit->stcTimingCfg.u32RC << SMC_TMCR_T_RC_POS) | \ + (pstcInit->stcTimingCfg.u32WC << SMC_TMCR_T_WC_POS) | \ + (pstcInit->stcTimingCfg.u32CEOE << SMC_TMCR_T_CEOE_POS) | \ + (pstcInit->stcTimingCfg.u32WP << SMC_TMCR_T_WP_POS) | \ + (pstcInit->stcTimingCfg.u32PC << SMC_TMCR_T_PC_POS) | \ + (pstcInit->stcTimingCfg.u32TR << SMC_TMCR_T_TR_POS) | \ + 0xFF000000UL); + WRITE_REG32(M4_SMC->TMCR, u32RegVal); + + /* Set SMC chip configuration.*/ + u32RegVal = (pstcInit->stcChipCfg.u32ReadMode | \ + pstcInit->stcChipCfg.u32ReadBurstLen | \ + pstcInit->stcChipCfg.u32WriteMode | \ + pstcInit->stcChipCfg.u32WriteBurstLen | \ + pstcInit->stcChipCfg.u32SmcMemWidth | \ + pstcInit->stcChipCfg.u32BAA | \ + pstcInit->stcChipCfg.u32ADV | \ + pstcInit->stcChipCfg.u32BLS | \ + 0xFFFF0000UL); + WRITE_REG32(M4_SMC->CPCR, u32RegVal); + + /* Set chip selection address match/mask spacefor SMC.*/ + MODIFY_REG32(M4_SMC->CSCR0, \ + SMC_CSCR0_ADDMSKx(u32Chip), \ + (pstcInit->stcChipCfg.u32AddressMask << SMC_CSCR0_ADDMSKx_POS(u32Chip))); + MODIFY_REG32(M4_SMC->CSCR1, \ + SMC_CSCR0_ADDMSKx(u32Chip), \ + (pstcInit->stcChipCfg.u32AddressMatch << SMC_CSCR1_ADDMATx_POS(u32Chip))); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize EXMC SMC function. + * @param None + * @retval None + */ +void EXMC_SMC_DeInit(void) +{ + /* Disable SMC */ + WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.SMCEN, 0UL); + + /* Set SMC timing.*/ + WRITE_REG32(M4_SMC->TMCR, 0UL); + + /* Set SMC chip configuration.*/ + WRITE_REG32(M4_SMC->CPCR, 0UL); +} + +/** + * @brief Set the fields of structure @ref stc_exmc_smc_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_exmc_smc_init_t structure (EXMC SMC function configuration structure) + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t EXMC_SMC_StructInit(stc_exmc_smc_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + pstcInit->stcChipCfg.u32ReadMode = EXMC_SMC_MEM_READ_ASYNC; + pstcInit->stcChipCfg.u32ReadBurstLen = EXMC_SMC_MEM_READ_BURST_1; + pstcInit->stcChipCfg.u32WriteMode = EXMC_SMC_MEM_WRITE_ASYNC; + pstcInit->stcChipCfg.u32WriteBurstLen = EXMC_SMC_MEM_WRITE_BURST_1; + pstcInit->stcChipCfg.u32SmcMemWidth = EXMC_SMC_MEMORY_WIDTH_16BIT; + pstcInit->stcChipCfg.u32BAA = EXMC_SMC_BAA_PORT_DISABLE; + pstcInit->stcChipCfg.u32ADV = EXMC_SMC_ADV_PORT_DISABLE; + pstcInit->stcChipCfg.u32BLS = EXMC_SMC_BLS_SYNC_CS; + pstcInit->stcChipCfg.u32AddressMask = 0xF8UL; /* Address space 128M: 0x60000000 ~ 0X67FFFFFF */ + pstcInit->stcChipCfg.u32AddressMatch = 0X60UL; + + pstcInit->stcTimingCfg.u32RC = 7UL; + pstcInit->stcTimingCfg.u32WC = 7UL; + pstcInit->stcTimingCfg.u32CEOE = 1UL; + pstcInit->stcTimingCfg.u32WP = 5UL; + pstcInit->stcTimingCfg.u32PC = 0UL; + pstcInit->stcTimingCfg.u32TR = 0UL; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable/Disable SMC. + * @param [in] enNewState An en_functional_state_t enumeration value. + * This parameter can be one of the following values: + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void EXMC_SMC_Cmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(bM4_PERIC->EXMC_ENAR_b.SMCEN, enNewState); +} + +/** + * @brief Set EXMC SMC command. + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CHIP_0: Chip 0 + * @arg EXMC_SMC_CHIP_1: Chip 1 + * @arg EXMC_SMC_CHIP_2: Chip 2 + * @arg EXMC_SMC_CHIP_3: Chip 3 + * @param [in] u32Cmd The command. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CMD_MDREGCONFIG: Configure mode register + * @arg EXMC_SMC_CMD_UPDATEREGS: Update mode register + * @arg EXMC_SMC_CMD_MDREGCONFIG_AND_UPDATEREGS: Configure mode register and update + * @param [in] u32CrePolarity The command. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CRE_POLARITY_LOW: CRE is LOW + * @arg EXMC_SMC_CRE_POLARITY_HIGH: CRE is HIGH when ModeReg write occurs + * @param [in] u32Address The address parameter is valid when CMD type is + * MdRegConfig or MdRegConfig and UpdateRegs only. + * @retval None + */ +void EXMC_SMC_SetCommand(uint32_t u32Chip, + uint32_t u32Cmd, + uint32_t u32CrePolarity, + uint32_t u32Address) +{ + uint32_t u32SmcCmdr; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_CMD(u32Cmd)); + DDL_ASSERT(IS_EXMC_SMC_CRE_POLARITY(u32CrePolarity)); + DDL_ASSERT(IS_EXMC_SMC_CMDADD(u32Address)); + + /* Set SMC_CMDR register for SMC.*/ + u32SmcCmdr = (u32Address | u32CrePolarity | u32Cmd | (u32Chip << SMC_CMDR_CMDCHIP_POS)); + WRITE_REG32(M4_SMC->CMDR, u32SmcCmdr); +} + +/** + * @brief Get the start address of the specified SMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CHIP_0: Chip 0 + * @arg EXMC_SMC_CHIP_1: Chip 1 + * @arg EXMC_SMC_CHIP_2: Chip 2 + * @arg EXMC_SMC_CHIP_3: Chip 3 + * @retval The start address of the specified SMC chip. + */ +uint32_t EXMC_SMC_ChipStartAddress(uint32_t u32Chip) +{ + uint32_t u32StartAddress; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + u32StartAddress = (READ_REG32_BIT(M4_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) << (24UL - SMC_CSCR1_ADDMATx_POS(u32Chip))); + return u32StartAddress; +} + +/** + * @brief Get the end address of the specified SMC chip. + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CHIP_0: Chip 0 + * @arg EXMC_SMC_CHIP_1: Chip 1 + * @arg EXMC_SMC_CHIP_2: Chip 2 + * @arg EXMC_SMC_CHIP_3: Chip 3 + * @retval The end address of the specified SMC chip + */ +uint32_t EXMC_SMC_ChipEndAddress(uint32_t u32Chip) +{ + uint32_t u32Mask; + uint32_t u32Match; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + + u32Mask = (READ_REG32_BIT(M4_SMC->CSCR0, SMC_CSCR0_ADDMSKx(u32Chip)) >> SMC_CSCR0_ADDMSKx_POS(u32Chip)); + u32Match = (READ_REG32_BIT(M4_SMC->CSCR1, SMC_CSCR1_ADDMATx(u32Chip)) >> SMC_CSCR1_ADDMATx_POS(u32Chip)); + + return (~((u32Match ^ u32Mask) << 24UL)); +} + +/** + * @brief Check SMC chip status register value + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CHIP_0: Chip 0 + * @arg EXMC_SMC_CHIP_1: Chip 1 + * @arg EXMC_SMC_CHIP_2: Chip 2 + * @arg EXMC_SMC_CHIP_3: Chip 3 + * @param [in] pstcChipCfg Pointer to a @ref stc_exmc_smc_chip_cfg_t structure + * @retval An en_result_t enumeration value: + * - Ok: Status is right + * - Error: Status is error + */ +en_result_t EXMC_SMC_CheckChipStatus(uint32_t u32Chip, + const stc_exmc_smc_chip_cfg_t *pstcChipCfg) +{ + uint32_t u32ChipCfg; + __IO uint32_t *SMC_CPSRx; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_MEM_READ_MODE(pstcChipCfg->u32ReadMode)); + DDL_ASSERT(IS_EXMC_SMC_MEM_WRITE_MODE(pstcChipCfg->u32WriteMode)); + DDL_ASSERT(IS_EXMC_SMC_MEM_READ_BURST(pstcChipCfg->u32ReadBurstLen)); + DDL_ASSERT(IS_EXMC_SMC_MEM_WRITE_BURST(pstcChipCfg->u32WriteBurstLen)); + DDL_ASSERT(IS_EXMC_SMC_MEM_WIDTH(pstcChipCfg->u32SmcMemWidth)); + DDL_ASSERT(IS_EXMC_SMC_BAA_PORT(pstcChipCfg->u32BAA)); + DDL_ASSERT(IS_EXMC_SMC_ADV_PORT(pstcChipCfg->u32ADV)); + DDL_ASSERT(IS_EXMC_SMC_BLS_SYNC(pstcChipCfg->u32BLS)); + DDL_ASSERT(IS_EXMC_SMC_CS_ADDRESS_MATCH(pstcChipCfg->u32AddressMatch)); + DDL_ASSERT(IS_EXMC_SMC_CS_ADDRESS_MASK(pstcChipCfg->u32AddressMask)); + + u32ChipCfg = (pstcChipCfg->u32ReadMode | \ + pstcChipCfg->u32WriteMode | \ + pstcChipCfg->u32ReadBurstLen | \ + pstcChipCfg->u32WriteBurstLen | \ + pstcChipCfg->u32SmcMemWidth | \ + pstcChipCfg->u32BAA | \ + pstcChipCfg->u32ADV | \ + pstcChipCfg->u32BLS | \ + (pstcChipCfg->u32AddressMask << SMC_CPSR_ADDMSK_POS) | \ + (pstcChipCfg->u32AddressMatch << SMC_CPSR_ADDMAT_POS)); + SMC_CPSRx = EXMC_SMC_CPSRx(u32Chip); + return (u32ChipCfg == READ_REG32(*SMC_CPSRx)) ? Ok : Error; +} + +/** + * @brief Check SMC timing status register value + * @param [in] u32Chip The chip number. + * This parameter can be one of the following values: + * @arg EXMC_SMC_CHIP_0: Chip 0 + * @arg EXMC_SMC_CHIP_1: Chip 1 + * @arg EXMC_SMC_CHIP_2: Chip 2 + * @arg EXMC_SMC_CHIP_3: Chip 3 + * @param [in] pstcTimingCfg Pointer to a @ref stc_exmc_smc_timing_cfg_t structure + * @retval An en_result_t enumeration value: + * - Ok: Status is right + * - Error: Status is error + */ +en_result_t EXMC_SMC_CheckTimingStatus(uint32_t u32Chip, + const stc_exmc_smc_timing_cfg_t *pstcTimingCfg) +{ + uint32_t u32TimingCfg; + __IO uint32_t *SMC_TMSRx; + + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_CHIP(u32Chip)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcTimingCfg->u32RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WC_CYCLE(pstcTimingCfg->u32WC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_CEOE_CYCLE(pstcTimingCfg->u32CEOE)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_WP_CYCLE(pstcTimingCfg->u32WP)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_RC_CYCLE(pstcTimingCfg->u32RC)); + DDL_ASSERT(IS_EXMC_SMC_TIMING_TR_CYCLE(pstcTimingCfg->u32TR)); + + u32TimingCfg = ((pstcTimingCfg->u32RC << SMC_TMCR_T_RC_POS) | \ + (pstcTimingCfg->u32WC << SMC_TMCR_T_WC_POS) | \ + (pstcTimingCfg->u32CEOE << SMC_TMCR_T_CEOE_POS) | \ + (pstcTimingCfg->u32WP << SMC_TMCR_T_WP_POS) | \ + (pstcTimingCfg->u32PC << SMC_TMCR_T_PC_POS) | \ + (pstcTimingCfg->u32TR << SMC_TMCR_T_TR_POS)); + SMC_TMSRx = EXMC_SMC_TMSRx(u32Chip); + return (u32TimingCfg == READ_REG32(*SMC_TMSRx)) ? Ok : Error; +} + +/** + * @brief Enable SMC MUX. + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void EXMC_SMC_PinMuxCmd(en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + WRITE_REG32(M4_SMC->BACR, (Enable == enNewState) ? EXMC_SMC_MUX_ENABLE: EXMC_SMC_MUX_DISABLE); +} + +/** + * @brief Set SMC refresh period value + * @param [in] u32PeriodVal The SMC refresh period value + * @arg number of 16bit + * @retval None + */ +void EXMC_SMC_SetRefreshPeriod(uint32_t u32PeriodVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_EXMC_SMC_REFRESH_PERIOD(u32PeriodVal)); + + WRITE_REG16(M4_SMC->RFTR, u32PeriodVal); +} + +/** + * @} + */ + +#endif /* DDL_SMC_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_spi.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..1dbf6acc00fc3dd77ee437bece6bb050f77d798b --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_spi.c @@ -0,0 +1,1095 @@ +/** + ******************************************************************************* + * @file hc32f4a0_spi.c + * @brief This file provides firmware functions to manage the Serial Peripheral + * Interface(SPI). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-08-31 Wangmin Modify for MISRAC2012 + 2020-10-13 Wangmin Define variable for count as __IO type + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_spi.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_SPI SPI + * @brief Serial Peripheral Interface Driver Library + * @{ + */ + +#if (DDL_SPI_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Macros SPI Local Macros + * @{ + */ + +#define SPI_CFG1_DEFAULT (0x00000010UL) +#define SPI_CFG2_DEFAULT (0x00000F1DUL) +#define SPI_SR_DEFAULT (0x00000020UL) + +#define SPI_IRQ_MASK ( SPI_INT_ERROR | \ + SPI_INT_TX_BUFFER_EMPTY | \ + SPI_INT_RX_BUFFER_FULL | \ + SPI_INT_IDLE ) +#define SPI_GET_STD_MASK ( SPI_FLAG_OVERLOAD | \ + SPI_FLAG_IDLE | \ + SPI_FLAG_MODE_FAULT | \ + SPI_FLAG_PARITY_ERROR | \ + SPI_FLAG_UNDERLOAD | \ + SPI_FLAG_TX_BUFFER_EMPTY | \ + SPI_FLAG_RX_BUFFER_FULL ) +#define SPI_CLR_STD_MASK ( SPI_FLAG_OVERLOAD | \ + SPI_FLAG_MODE_FAULT | \ + SPI_FLAG_PARITY_ERROR | \ + SPI_FLAG_UNDERLOAD ) + +#define SPI_SS0_VALID_CFG (0UL) +#define SPI_SS1_VALID_CFG (SPI_CFG2_SSA_0) +#define SPI_SS2_VALID_CFG (SPI_CFG2_SSA_1) +#define SPI_SS3_VALID_CFG (SPI_CFG2_SSA_0 | SPI_CFG2_SSA_1) + +/** + * @defgroup SPI_Check_Parameters_Validity SPI check parameters validity + * @{ + */ + +/*! Parameter valid check for SPI peripheral */ +#define IS_VALID_SPI_UNIT(x) \ +( (M4_SPI1 == (x)) || \ + (M4_SPI2 == (x)) || \ + (M4_SPI3 == (x)) || \ + (M4_SPI4 == (x)) || \ + (M4_SPI5 == (x)) || \ + (M4_SPI6 == (x))) + +/*! Parameter valid check for SPI wire mode */ +#define IS_SPI_WIRE_MODE(x) \ +( ((x) == SPI_WIRE_4) || \ + ((x) == SPI_WIRE_3)) + +/*! Parameter valid check for SPI transfer mode */ +#define IS_SPI_TRANS_MODE(x) \ +( ((x) == SPI_FULL_DUPLEX) || \ + ((x) == SPI_SEND_ONLY)) + +/*! Parameter valid check for SPI master slave mode */ +#define IS_SPI_MASTER_SLAVE(x) \ +( ((x) == SPI_SLAVE) || \ + ((x) == SPI_MASTER)) + +/*! Parameter valid check for SPI loopback mode */ +#define IS_SPI_SPLPBK(x) \ +( ((x) == SPI_SPLPBK_INVALID) || \ + ((x) == SPI_SPLPBK_MOSI_INVERT) || \ + ((x) == SPI_SPLPBK_MOSI)) + +/*! Parameter valid check for SPI communication suspend function status */ +#define IS_SPI_SUSP_MODE_STD(x) \ +( ((x) == SPI_COM_SUSP_FUNC_OFF) || \ + ((x) == SPI_COM_SUSP_FUNC_ON)) + +/*! Parameter valid check for SPI fault dectet function status */ +#define IS_SPI_MODFE_CMD(x) \ +( ((x) == SPI_MODFE_DISABLE) || \ + ((x) == SPI_MODFE_ENABLE)) + +/*! Parameter valid check for SPI parity check mode */ +#define IS_SPI_PARITY_CHECK(x) \ +( ((x) == SPI_PARITY_INVALID) || \ + ((x) == SPI_PARITY_EVEN) || \ + ((x) == SPI_PARITY_ODD)) + +/*! Parameter valid check for SPI interval time delay */ +#define IS_SPI_INTERVAL_DELAY(x) \ +( ((x) == SPI_INTERVAL_TIME_1SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_2SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_3SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_4SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_5SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_6SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_7SCK_2PCLK1) || \ + ((x) == SPI_INTERVAL_TIME_8SCK_2PCLK1)) + +/*! Parameter valid check for SPI release time delay */ +#define IS_SPI_RELEASE_DELAY(x) \ +( ((x) == SPI_RELEASE_TIME_1SCK) || \ + ((x) == SPI_RELEASE_TIME_2SCK) || \ + ((x) == SPI_RELEASE_TIME_3SCK) || \ + ((x) == SPI_RELEASE_TIME_4SCK) || \ + ((x) == SPI_RELEASE_TIME_5SCK) || \ + ((x) == SPI_RELEASE_TIME_6SCK) || \ + ((x) == SPI_RELEASE_TIME_7SCK) || \ + ((x) == SPI_RELEASE_TIME_8SCK)) + +/*! Parameter valid check for SPI Setup time delay delay */ +#define IS_SPI_SETUP_DELAY(x) \ +( ((x) == SPI_SETUP_TIME_1SCK) || \ + ((x) == SPI_SETUP_TIME_2SCK) || \ + ((x) == SPI_SETUP_TIME_3SCK) || \ + ((x) == SPI_SETUP_TIME_4SCK) || \ + ((x) == SPI_SETUP_TIME_5SCK) || \ + ((x) == SPI_SETUP_TIME_6SCK) || \ + ((x) == SPI_SETUP_TIME_7SCK) || \ + ((x) == SPI_SETUP_TIME_8SCK)) + +/*! Parameter valid check for SPI SS active level */ +#define IS_SPI_SS_ACTIVE_LEVEL(x) \ +( ((x) == SPI_SS_ACTIVE_LOW) || \ + ((x) == SPI_SS_ACTIVE_HIGH)) + +/*! Parameter valid check for SPI read data register target buffer */ +#define IS_SPI_RD_TARGET_BUFF(x) \ +( ((x) == SPI_RD_TARGET_RD_BUF) || \ + ((x) == SPI_RD_TARGET_WR_BUF)) + +/*! Parameter valid check for SPI mode */ +#define IS_SPI_SPI_MODE(x) \ +( ((x) == SPI_MODE_0) || \ + ((x) == SPI_MODE_1) || \ + ((x) == SPI_MODE_2) || \ + ((x) == SPI_MODE_3)) + +/*! Parameter valid check for SPI SS signal */ +#define IS_SPI_SS_PIN(x) \ +( ((x) == SPI_PIN_SS0) || \ + ((x) == SPI_PIN_SS1) || \ + ((x) == SPI_PIN_SS2) || \ + ((x) == SPI_PIN_SS3)) + +/*! Parameter valid check for SPI baudrate prescaler */ +#define IS_SPI_BIT_RATE_DIV(x) \ +( ((x) == SPI_BR_PCLK1_DIV2) || \ + ((x) == SPI_BR_PCLK1_DIV4) || \ + ((x) == SPI_BR_PCLK1_DIV8) || \ + ((x) == SPI_BR_PCLK1_DIV16) || \ + ((x) == SPI_BR_PCLK1_DIV32) || \ + ((x) == SPI_BR_PCLK1_DIV64) || \ + ((x) == SPI_BR_PCLK1_DIV128) || \ + ((x) == SPI_BR_PCLK1_DIV256)) + +/*! Parameter valid check for SPI data bits */ +#define IS_SPI_DATA_SIZE(x) \ +( ((x) == SPI_DATA_SIZE_4BIT) || \ + ((x) == SPI_DATA_SIZE_5BIT) || \ + ((x) == SPI_DATA_SIZE_6BIT) || \ + ((x) == SPI_DATA_SIZE_7BIT) || \ + ((x) == SPI_DATA_SIZE_8BIT) || \ + ((x) == SPI_DATA_SIZE_9BIT) || \ + ((x) == SPI_DATA_SIZE_10BIT) || \ + ((x) == SPI_DATA_SIZE_11BIT) || \ + ((x) == SPI_DATA_SIZE_12BIT) || \ + ((x) == SPI_DATA_SIZE_13BIT) || \ + ((x) == SPI_DATA_SIZE_14BIT) || \ + ((x) == SPI_DATA_SIZE_15BIT) || \ + ((x) == SPI_DATA_SIZE_16BIT) || \ + ((x) == SPI_DATA_SIZE_20BIT) || \ + ((x) == SPI_DATA_SIZE_24BIT) || \ + ((x) == SPI_DATA_SIZE_32BIT)) + +/*! Parameter valid check for SPI data frame level */ +#define IS_SPI_DATA_FRAME(x) \ +( ((x) == SPI_FRAME_1) || \ + ((x) == SPI_FRAME_2) || \ + ((x) == SPI_FRAME_3) || \ + ((x) == SPI_FRAME_4)) + +/*! Parameter valid check for SPI LSB MSB mode */ +#define IS_SPI_FIRST_BIT(x) \ +( ((x) == SPI_FIRST_MSB) || \ + ((x) == SPI_FIRST_LSB)) + +/*! Parameter valid check for interrupt flag */ +#define IS_SPI_IRQ_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_IRQ_MASK) == SPI_IRQ_MASK)) + +/*! Parameter valid check for SPI status flag */ +#define IS_SPI_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_GET_STD_MASK) == SPI_GET_STD_MASK)) + +/*! Parameter valid check for SPI status flag for clear */ +#define IS_SPI_CLR_STD_FLAG(x) \ +( ((x) != 0UL) && \ + (((x) | SPI_CLR_STD_MASK) == SPI_CLR_STD_MASK)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Local_Functions SPI Local Functions + * @{ + */ + +static en_result_t SPI_TxRx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length); +static en_result_t SPI_Tx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Length); + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SPI_Global_Functions SPI Global Functions + * @{ + */ + +/** + * @brief Initializes the SPI peripheral according to the specified parameters + * in the structure stc_spi_init. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pstcInit Pointer to a stc_spi_init_t structure that contains + * the configuration information for the SPI. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorInvalidParameter: pstcInit == NULL or configuration parameter error. + */ +en_result_t SPI_Init(M4_SPI_TypeDef *SPIx, const stc_spi_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcInit) + { + DDL_ASSERT(IS_SPI_WIRE_MODE(pstcInit->u32WireMode)); + DDL_ASSERT(IS_SPI_TRANS_MODE(pstcInit->u32TransMode)); + DDL_ASSERT(IS_SPI_MASTER_SLAVE(pstcInit->u32MasterSlave)); + DDL_ASSERT(IS_SPI_SUSP_MODE_STD(pstcInit->u32SuspMode)); + DDL_ASSERT(IS_SPI_MODFE_CMD(pstcInit->u32Modfe)); + DDL_ASSERT(IS_SPI_PARITY_CHECK(pstcInit->u32Parity)); + DDL_ASSERT(IS_SPI_SPI_MODE(pstcInit->u32SpiMode)); + DDL_ASSERT(IS_SPI_BIT_RATE_DIV(pstcInit->u32BaudRatePrescaler)); + DDL_ASSERT(IS_SPI_DATA_SIZE(pstcInit->u32DataBits)); + DDL_ASSERT(IS_SPI_FIRST_BIT(pstcInit->u32FirstBit)); + DDL_ASSERT(IS_SPI_DATA_FRAME(pstcInit->u32FrameLevel)); + + /* Configuration parameter check */ + if((SPI_MASTER == pstcInit->u32MasterSlave)&&(SPI_MODFE_ENABLE == pstcInit->u32Modfe)) + { + /* pstcInit->u32Modfe can not be SPI_MODFE_ENABLE in master mode */ + } + else if((SPI_WIRE_3 == pstcInit->u32WireMode) + && (SPI_SLAVE == pstcInit->u32MasterSlave) + &&((SPI_MODE_0 == pstcInit->u32SpiMode)||(SPI_MODE_2 == pstcInit->u32SpiMode))) + { + /* SPI_WIRE_3 can not support SPI_MODE_0 and SPI_MODE_2 */ + } + else + { + WRITE_REG32(SPIx->CR1, pstcInit->u32WireMode + | pstcInit->u32TransMode + | pstcInit->u32MasterSlave + | pstcInit->u32SuspMode + | pstcInit->u32Modfe + | pstcInit->u32Parity ); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_FTHLV, pstcInit->u32FrameLevel); + + WRITE_REG32(SPIx->CFG2, pstcInit->u32SpiMode + | pstcInit->u32BaudRatePrescaler + | pstcInit->u32DataBits + | pstcInit->u32FirstBit); + + enRet = Ok; + } + } + return enRet; +} + +/** + * @brief De-initializes the SPI peripheral. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @retval None + */ +void SPI_DeInit(M4_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + SPI_FunctionCmd(SPIx, Disable); + + WRITE_REG32(SPIx->CR1, 0x00000000UL); + WRITE_REG32(SPIx->CFG1, SPI_CFG1_DEFAULT); + WRITE_REG32(SPIx->CFG2, SPI_CFG2_DEFAULT); + WRITE_REG32(SPIx->SR, SPI_SR_DEFAULT); +} + +/** + * @brief Set a default value for the SPI initialization structure. + * @param [in] pstcInit Pointer to a stc_spi_init_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t SPI_StructInit(stc_spi_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcInit) + { + pstcInit->u32WireMode = SPI_WIRE_4; + pstcInit->u32TransMode = SPI_FULL_DUPLEX; + pstcInit->u32MasterSlave = SPI_MASTER; + pstcInit->u32SuspMode = SPI_COM_SUSP_FUNC_OFF; + pstcInit->u32Modfe = SPI_MODFE_DISABLE; + pstcInit->u32Parity = SPI_PARITY_INVALID; + pstcInit->u32SpiMode = SPI_MODE_0; + pstcInit->u32BaudRatePrescaler = SPI_BR_PCLK1_DIV8; + pstcInit->u32DataBits = SPI_DATA_SIZE_8BIT; + pstcInit->u32FirstBit = SPI_FIRST_MSB; + pstcInit->u32FrameLevel = SPI_FRAME_1; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Enable or disable SPI interrupt. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32IntType SPI interrupt type. Can be one or any + * combination of the parameter @ref SPI_Interrupt_Type_Define + * @arg SPI_INT_ERROR + * @arg SPI_INT_TX_BUFFER_EMPTY + * @arg SPI_INT_RX_BUFFER_FULL + * @arg SPI_INT_IDLE + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable the specified interrupt of SPI. + * @arg Disable: Disable the specified interrupt of SPI. + * @retval None + */ +void SPI_IntCmd(M4_SPI_TypeDef *SPIx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_SPI_IRQ_FLAG(u32IntType)); + + if (enNewState == Enable) + { + SET_REG32_BIT(SPIx->CR1, u32IntType); + } + else + { + CLEAR_REG32_BIT(SPIx->CR1, u32IntType); + } +} + +/** + * @brief SPI function enable or disable. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable SPI function. + * @arg Disable: Disable SPI function. + * @retval None + */ +void SPI_FunctionCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } + else + { + CLEAR_REG32_BIT(SPIx->CR1, SPI_CR1_SPE); + } +} + +/** + * @brief Write SPI data register. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Data The data will be written to the data register. + * @retval None. + */ +void SPI_WriteDataReg(M4_SPI_TypeDef *SPIx, uint32_t u32Data) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + WRITE_REG32(SPIx->DR, u32Data); +} + +/** + * @brief Read SPI data register. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @retval A 32-bit data of SPI data register. + */ +uint32_t SPI_ReadDataReg(const M4_SPI_TypeDef *SPIx) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + return READ_REG32(SPIx->DR); +} + + +/** + * @brief SPI get status flag. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Flag SPI state flag. Can be one or any + * combination of the parameter of @ref SPI_State_Flag_Define + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_IDLE + * @arg SPI_FLAG_MODE_FAULT + * @arg SPI_FLAG_PARITY_ERROR + * @arg SPI_FLAG_UNDERLOAD + * @arg SPI_FLAG_TX_BUFFER_EMPTY + * @arg SPI_FLAG_RX_BUFFER_FULL + * @retval An en_flag_status_t enumeration. + * @arg Set: The specified flag has set. + * @arg Reset: The specified flag has not set. + */ +en_flag_status_t SPI_GetStatus(const M4_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + en_flag_status_t enFlag = Reset; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_STD_FLAG(u32Flag)); + + if(0U != READ_REG32_BIT(SPIx->SR, u32Flag)) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief SPI clear state flag. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Flag SPI state flag. + * Can be one or any combination of the parameter below + * @arg SPI_FLAG_OVERLOAD + * @arg SPI_FLAG_MODE_FAULT + * @arg SPI_FLAG_PARITY_ERROR + * @arg SPI_FLAG_UNDERLOAD + * @retval None + */ +void SPI_ClearFlag(M4_SPI_TypeDef *SPIx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_CLR_STD_FLAG(u32Flag)); + + CLEAR_REG32_BIT(SPIx->SR, u32Flag); +} + +/** + * @brief SPI loopback function configuration. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32Mode Loopback mode. + * Can be one parameter @ref SPI_Loopback_Selection_Define + * @arg SPI_SPLPBK_INVALID + * @arg SPI_SPLPBK_MOSI_INVERT + * @arg SPI_SPLPBK_MOSI + * @retval None + */ +void SPI_LoopbackModeCfg(M4_SPI_TypeDef *SPIx, uint32_t u32Mode) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SPLPBK(u32Mode)); + + MODIFY_REG32(SPIx->CR1, SPI_CR1_SPLPBK | SPI_CR1_SPLPBK2, u32Mode); +} + +/** + * @brief SPI parity check error self diagnosis function enable or disable. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: Enable function. + * @arg Disable: Disable function. + * @retval None + */ +void SPI_PateCmd(M4_SPI_TypeDef *SPIx, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } + else + { + CLEAR_REG32_BIT(SPIx->CR1, SPI_CR1_PATE); + } +} + +/** + * @brief SPI signals delay time configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pstcDelayCfg Pointer to a stc_spi_delay_t structure that contains + * the configuration information for the SPI delay time. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorInvalidParameter: pstcDelayCfg == NULL + */ +en_result_t SPI_DelayTimeCfg(M4_SPI_TypeDef *SPIx, const stc_spi_delay_t *pstcDelayCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + + if (NULL != pstcDelayCfg) + { + DDL_ASSERT(IS_SPI_INTERVAL_DELAY(pstcDelayCfg->u32IntervalDelay)); + DDL_ASSERT(IS_SPI_RELEASE_DELAY(pstcDelayCfg->u32ReleaseDelay)); + DDL_ASSERT(IS_SPI_SETUP_DELAY(pstcDelayCfg->u32SetupDelay)); + + /* Interval delay */ + if(SPI_INTERVAL_TIME_1SCK_2PCLK1 == pstcDelayCfg->u32IntervalDelay) + { + CLEAR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + CLEAR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MIDI); + } + else + { + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MIDI, pstcDelayCfg->u32IntervalDelay); + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MIDIE); + } + + /* SCK release delay */ + if(SPI_RELEASE_TIME_1SCK == pstcDelayCfg->u32ReleaseDelay) + { + CLEAR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + CLEAR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSDL); + } + else + { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSDLE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSDL, pstcDelayCfg->u32ReleaseDelay); + } + + /* Setup delay */ + if(SPI_SETUP_TIME_1SCK == pstcDelayCfg->u32SetupDelay) + { + CLEAR_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + CLEAR_REG32_BIT(SPIx->CFG1, SPI_CFG1_MSSI); + } + else + { + SET_REG32_BIT(SPIx->CFG2, SPI_CFG2_MSSIE); + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_MSSI, pstcDelayCfg->u32SetupDelay); + } + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set a default value for the SPI delay time configuration structure. + * @param [in] pstcDelayCfg Pointer to a stc_spi_delay_t structure that + * contains configuration information. + * @retval An en_result_t enumeration value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcDelayCfg == NULL. + */ +en_result_t SPI_DelayStructInit(stc_spi_delay_t *pstcDelayCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (NULL != pstcDelayCfg) + { + pstcDelayCfg->u32IntervalDelay = SPI_INTERVAL_TIME_1SCK_2PCLK1; + pstcDelayCfg->u32ReleaseDelay = SPI_RELEASE_TIME_1SCK; + pstcDelayCfg->u32SetupDelay = SPI_SETUP_TIME_1SCK; + enRet = Ok; + } + return enRet; +} + +/** + * @brief SPI SS signal valid level configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @param [in] enNewState An en_functional_state_t enumeration value. + * @arg Enable: SS pin high level valid. + * @arg Disable: SS pin low level valid. + * @retval None + */ +void SPI_SSValidLevelCfg(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(SPIx->CFG1, u32SSPin); + } + else + { + CLEAR_REG32_BIT(SPIx->CFG1, u32SSPin); + } +} + +/** + * @brief SPI valid SS signal configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32SSPin Specify the SS pin @ref SPI_SS_Pin_Define + * @retval None + */ +void SPI_SSPinSel(M4_SPI_TypeDef *SPIx, uint32_t u32SSPin) +{ + uint32_t u32RegCfg; + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_SS_PIN(u32SSPin)); + + switch (u32SSPin) + { + case SPI_PIN_SS0: + u32RegCfg = SPI_SS0_VALID_CFG; + break; + case SPI_PIN_SS1: + u32RegCfg = SPI_SS1_VALID_CFG; + break; + case SPI_PIN_SS2: + u32RegCfg = SPI_SS2_VALID_CFG; + break; + case SPI_PIN_SS3: + u32RegCfg = SPI_SS3_VALID_CFG; + break; + + default: + u32RegCfg = SPI_SS0_VALID_CFG; + break; + } + MODIFY_REG32(SPIx->CFG2, SPI_CFG2_SSA, u32RegCfg); +} + +/** + * @brief SPI read buffer configuration + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] u32ReadBuf Target buffer for read operation @ref SPI_Read_Target_Buffer_Define + * @retval None + */ +void SPI_ReadBufCfg(M4_SPI_TypeDef *SPIx, uint32_t u32ReadBuf) +{ + DDL_ASSERT(IS_VALID_SPI_UNIT(SPIx)); + DDL_ASSERT(IS_SPI_RD_TARGET_BUFF(u32ReadBuf)); + + MODIFY_REG32(SPIx->CFG1, SPI_CFG1_SPRDTD, u32ReadBuf); +} + +/** + * @brief SPI transmit data. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32TxLength The length of the data to be sent. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI transmit timeout. + * @arg ErrorInvalidParameter: pvTxBuf == NULL or u32TxLength == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function supports full duplex mode and send only mode. + */ +en_result_t SPI_Transmit(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32TxLength) +{ + uint32_t u32Flags; + en_result_t enRet = ErrorInvalidParameter; + + if ((pvTxBuf != NULL) && (u32TxLength != 0U)) + { + u32Flags = READ_REG32_BIT(SPIx->CR1, SPI_CR1_TXMDS); + if (u32Flags == SPI_SEND_ONLY) + { + /* Transmit data in send only mode. */ + enRet = SPI_Tx(SPIx, pvTxBuf, u32TxLength); + } + else + { + /* Transmit data in full duplex mode. */ + enRet = SPI_TxRx(SPIx, pvTxBuf, NULL, u32TxLength); + } + } + return enRet; +} + +/** + * @brief SPI receive data. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvRxBuf The pointer to the buffer which the received data to be stored. + * @param [in] u32RxLength The length of the data to be received. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI receive timeout. + * @arg ErrorInvalidParameter: pvRxBuf == NULL or u32RxLength == 0U + * @note -No SS pin active and inactive operation in 3-wire mode. Add operations of SS pin depending on your application. + * -This function only works in full duplex master mode. + */ +en_result_t SPI_Receive(M4_SPI_TypeDef *SPIx, void *pvRxBuf, uint32_t u32RxLength) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((pvRxBuf != NULL) && (u32RxLength != 0U)) + { + /* Receives data in full duplex master mode. */ + enRet = SPI_TxRx(SPIx, NULL, pvRxBuf, u32RxLength); + } + return enRet; +} + +/** + * @brief SPI transmit and receive data. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * If this pointer is NULL and the pvRxBuf is NOT NULL, the MOSI output high + * and the the received data will be stored in the buffer pointed by pvRxBuf. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * This for full duplex transfer. + * @param [in] u32Length The length of the data(in byte or half word) to be sent and received. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI transmit and receive timeout. + * @arg ErrorInvalidParameter: pvRxBuf == NULL or pvRxBuf == NULL or u32Length == 0U + * @note SPI receives data while sending data. Only works in full duplex master mode. + */ +en_result_t SPI_TransmitReceive(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length) +{ + en_result_t enRet = ErrorInvalidParameter; + + if ((pvTxBuf != NULL) && (pvRxBuf != NULL) && (u32Length != 0U)) + { + /* Transmit and receive data in full duplex master mode. */ + enRet = SPI_TxRx(SPIx, pvTxBuf, pvRxBuf, u32Length); + } + return enRet; +} +/** + * @} + */ + +/** + * @addtogroup SPI_Local_Functions SPI Local Functions + * @{ + */ +/** + * @brief SPI transmit and receive data in full duplex mode. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [out] pvRxBuf The pointer to the buffer which the received data will be stored. + * @param [in] u32Length The length of the data in byte or half word. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred + * @arg ErrorTimeout: SPI transmit and receive timeout. + */ +static en_result_t SPI_TxRx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, void *pvRxBuf, uint32_t u32Length) +{ + uint32_t u32BitSize; + __IO uint32_t u32Timecount; + __IO uint32_t u32Count = 0U; + en_result_t enRet = Ok; + uint32_t u32Tmp; + __UNUSED __IO uint32_t u32Read; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Length) + { + if (pvTxBuf != NULL) + { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) + { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } + else if(u32BitSize <= SPI_DATA_SIZE_16BIT) + { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } + else + { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + } + else + { + WRITE_REG32(SPIx->DR, 0xFFFFFFFFUL); + } + + /* Delay about 10ms */ + u32Timecount = HCLK_VALUE/100UL; + do + { + if(0UL != READ_REG32_BIT(SPIx->SR, SPI_FLAG_RX_BUFFER_FULL)) + { + break; + } + u32Timecount--; + } while (u32Timecount != 0U); + + if (u32Timecount == 0U) + { + enRet = ErrorTimeout; + break; + } + + u32Tmp = READ_REG32(SPIx->DR); + if (pvRxBuf != NULL) + { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) + { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + ((uint8_t *)pvRxBuf)[u32Count] = (uint8_t)u32Tmp; + } + else if(u32BitSize <= SPI_DATA_SIZE_16BIT) + { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + ((uint16_t *)pvRxBuf)[u32Count] = (uint16_t)u32Tmp; + } + else + { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + ((uint32_t *)pvRxBuf)[u32Count] = (uint32_t)u32Tmp; + } + } + else + { + /* Dummy read */ + u32Read = READ_REG32(SPIx->DR); + } + + u32Count++; + } + return enRet; +} + +/** + * @brief SPI send data only. + * @param [in] SPIx SPI unit + * @arg M4_SPI1 + * @arg M4_SPI2 + * @arg M4_SPI3 + * @arg M4_SPI4 + * @arg M4_SPI5 + * @arg M4_SPI6 + * @param [in] pvTxBuf The pointer to the buffer which contains the data to be sent. + * @param [in] u32Length The length of the data in byte or half word or word. + * @retval An en_result_t enumeration value: + * @arg Ok: No errors occurred. + * @arg ErrorTimeout: SPI transmit timeout. + */ +static en_result_t SPI_Tx(M4_SPI_TypeDef *SPIx, const void *pvTxBuf, uint32_t u32Length) +{ + __IO uint32_t u32Count = 0U; + __IO uint32_t u32Timecount; + uint32_t u32BitSize; + en_result_t enRet = Ok; + + /* Get data bit size, SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_32BIT */ + u32BitSize = READ_REG32_BIT(SPIx->CFG2, SPI_CFG2_DSIZE); + + while (u32Count < u32Length) + { + if (u32BitSize <= SPI_DATA_SIZE_8BIT) + { + /* SPI_DATA_SIZE_4BIT ~ SPI_DATA_SIZE_8BIT */ + WRITE_REG32(SPIx->DR, ((const uint8_t *)pvTxBuf)[u32Count]); + } + else if(u32BitSize <= SPI_DATA_SIZE_16BIT) + { + /* SPI_DATA_SIZE_9BIT ~ SPI_DATA_SIZE_16BIT */ + WRITE_REG32(SPIx->DR, ((const uint16_t *)pvTxBuf)[u32Count]); + } + else + { + /* SPI_DATA_SIZE_20BIT ~ SPI_DATA_SIZE_32BIT */ + WRITE_REG32(SPIx->DR, ((const uint32_t *)pvTxBuf)[u32Count]); + } + + /* Delay about 10ms */ + u32Timecount = HCLK_VALUE/100UL; + do + { + if(0UL != READ_REG32_BIT(SPIx->SR, SPI_FLAG_TX_BUFFER_EMPTY)) + { + break; + } + u32Timecount--; + } while (u32Timecount != 0U); + + if (u32Timecount == 0U) + { + enRet = ErrorTimeout; + } + + u32Count++; + } + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_SPI_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sram.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sram.c new file mode 100644 index 0000000000000000000000000000000000000000..19459921b9314faa17fe648fd425be075b23bcd5 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sram.c @@ -0,0 +1,332 @@ +/** + ******************************************************************************* + * @file hc32f4a0_sram.c + * @brief This file provides firmware functions to manage the SRAM. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_sram.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_SRAM SRAM + * @brief SRAM Driver Library + * @{ + */ + +#if (DDL_SRAM_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SRAM_Local_Macros SRAM Local Macros + * @{ + */ + +/** + * @defgroup SRAM_Configuration_Bits_Mask SRAM Configuration Bits Mask + * @{ + */ +#define SRAM_ECC_MODE_MSK (SRAMC_CKCR_ECCMOD) +#define SRAM_CYCLE_MSK (SRAMC_WTCR_SRAM123RWT) +/** + * @} + */ + +/** + * @defgroup SRAM_Check_Parameters_Validity SRAM check parameters validity + * @{ + */ +#define IS_SRAM_ERR_OP(x) \ +( ((x) == SRAM_ERR_OP_NMI) || \ + ((x) == SRAM_ERR_OP_RESET)) + +#define IS_SRAM_CYCLE(x) \ +( ((x) <= SRAM_WAIT_CYCLE_7)) + +#define IS_SRAM_ECC_MODE(x) \ +( ((x) == SRAM_ECC_MODE_INVALID) || \ + ((x) == SRAM_ECC_MODE_1) || \ + ((x) == SRAM_ECC_MODE_2) || \ + ((x) == SRAM_ECC_MODE_3)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SRAM_Global_Functions SRAM Global Functions + * @{ + */ + +/** + * @brief Initializes SRAM. + * @param None + * @retval None + */ +void SRAM_Init(void) +{ + SET_REG32_BIT(M4_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief De-initializes SRAM. Reset the registers of SRAM. + * @param None + * @retval None + * @note Call SRAM_WTCR_Unlock to unlock register WTCR and SRAM_CKCR_Unlock to unlock register CKCR first. + */ +void SRAM_DeInit(void) +{ + /* Call SRAM_WTCR_Unlock to unlock register WTCR. */ + DDL_ASSERT(M4_SRAMC->WTPR == SRAM_UNLOCK_CMD); + /* Call SRAM_CKCR_Unlock to unlock register CKCR. */ + DDL_ASSERT(M4_SRAMC->CKPR == SRAM_UNLOCK_CMD); + + WRITE_REG32(M4_SRAMC->WTCR, 0U); + WRITE_REG32(M4_SRAMC->CKCR, 0U); + SET_REG32_BIT(M4_SRAMC->CKSR, SRAM_FLAG_ALL); +} + +/** + * @brief Set access wait cycle for SRAM(s). + * @param [in] u32SramIndex The SRAM(s) index bit mask. + * This parameter can be values of @ref SRAM_Index_Bit_Mask + * @arg SRAM_SRAMH: SRAMH. + * @arg SRAM_SRAM123: SRAM1, SRAM2 and SRAM3. When the CPU clock frequency is higher + * than 200MHz, access wait cycle is needed. + * @arg SRAM_SRAM4: SRAM4. When the CPU clock frequency is higher than 200MHz, + * access wait cycle is needed. + * @arg SRAM_SRAMB: SRAMB. When the CPU clock frequency is higher than 120MHz, + * access wait cycle is needed. + * @param [in] u32WriteCycle The write access wait cycle for the specified SRAM(s) + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * @arg SRAM_WAIT_CYCLE_0: Wait 0 CPU cycle. + * @arg SRAM_WAIT_CYCLE_1: Wait 1 CPU cycle. + * @arg SRAM_WAIT_CYCLE_2: Wait 2 CPU cycles. + * @arg SRAM_WAIT_CYCLE_3: Wait 3 CPU cycles. + * @arg SRAM_WAIT_CYCLE_4: Wait 4 CPU cycles. + * @arg SRAM_WAIT_CYCLE_5: Wait 5 CPU cycles. + * @arg SRAM_WAIT_CYCLE_6: Wait 6 CPU cycles. + * @arg SRAM_WAIT_CYCLE_7: Wait 7 CPU cycles. + * @param [in] u32ReadCycle The read access wait cycle for the specified SRAM(s) + * This parameter can be a value of @ref SRAM_Access_Wait_Cycle + * The arguments are same as u32WriteCycle. + * @retval None + * @note Call SRAM_WTCR_Unlock to unlock register WTCR first. + */ +void SRAM_SetWaitCycle(uint32_t u32SramIndex, uint32_t u32WriteCycle, uint32_t u32ReadCycle) +{ + uint8_t i; + uint8_t u8OfsWt; + uint8_t u8OfsRd; + uint32_t au32SramList[4U] = {SRAM_SRAM123, SRAM_SRAM4, SRAM_SRAMH, SRAM_SRAMB}; + + DDL_ASSERT(IS_SRAM_CYCLE(u32WriteCycle)); + DDL_ASSERT(IS_SRAM_CYCLE(u32ReadCycle)); + DDL_ASSERT(M4_SRAMC->WTPR == SRAM_UNLOCK_CMD); + + for (i=0U; i<4U; i++) + { + if ((u32SramIndex & au32SramList[i]) != 0U) + { + u8OfsWt = i << 3U; + u8OfsRd = u8OfsWt + 4U; + MODIFY_REG32(M4_SRAMC->WTCR, + ((SRAM_CYCLE_MSK << u8OfsWt) | (SRAM_CYCLE_MSK << u8OfsRd)), + ((u32WriteCycle << u8OfsWt) | (u32ReadCycle << u8OfsRd))); + } + } +} + +/** + * @brief Set ECC mode for SRAM4 and SRAMB. + * @param [in] u32SramIndex The SRAM(s) index bit mask.This function is used to set the + * ECC mode of SRAM4 and SRAMB, so u32SramIndex must contain + * SRAM_SRAM4 or SRAM_SRAMB or both, from @ref SRAM_Index_Bit_Mask + * @param [in] u32EccMode The ECC mode of SRAM4 and SRAMB. + * This parameter can be a value of @ref SRAM_ECC_Mode + * @arg SRAM_ECC_MODE_INVALID: The ECC mode is invalid. + * @arg SRAM_ECC_MODE_1: When 1-bit error occurred: + * ECC error corrects. + * No 1-bit-error status flag setting, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MODE_2: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets, no interrupt or reset. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @arg SRAM_ECC_MODE_3: When 1-bit error occurred: + * ECC error corrects. + * 1-bit-error status flag sets and interrupt or reset occurred. + * When 2-bit error occurred: + * ECC error detects. + * 2-bit-error status flag sets and interrupt or reset occurred. + * @retval None + * @note Call SRAM_CKCR_Unlock to unlock register CKCR first. + */ +void SRAM_SetEccMode(uint32_t u32SramIndex, uint32_t u32EccMode) +{ + DDL_ASSERT(IS_SRAM_ECC_MODE(u32EccMode)); + DDL_ASSERT(M4_SRAMC->CKPR == SRAM_UNLOCK_CMD); + + if ((u32SramIndex & SRAM_SRAM4) != 0U) + { + MODIFY_REG32(M4_SRAMC->CKCR, SRAM_ECC_MODE_MSK, u32EccMode); + } + + if ((u32SramIndex & SRAM_SRAMB) != 0U) + { + MODIFY_REG32(M4_SRAMC->CKCR, SRAM_ECC_MODE_MSK<<2U, u32EccMode); + } +} + +/** + * @brief Set the operation which is operated after check error occurred. + * @param [in] u32SramIndex The SRAM(s) index bit mask. + * This parameter can be values of @ref SRAM_Index_Bit_Mask + * @arg SRAM_SRAMH: SRAMH. + * @arg SRAM_SRAM123: SRAM1, SRAM2 and SRAM3. + * @arg SRAM_SRAM4: SRAM4. + * @arg SRAM_SRAMB: SRAMB. + * @param [out] u32OpAfterError The operation after check error occurred. + * This parameter can be a value of @ref SRAM_Operation_After_Check_Error + * @arg SRAM_ERR_OP_NMI: Check error generates NMI(non-maskable interrupt). + * @arg SRAM_ERR_OP_RESET: Check error generates system reset. + * @retval None + * @note Call SRAM_CKCR_Unlock to unlock register CKCR first. + */ +void SRAM_SetErrOperation(uint32_t u32SramIndex, uint32_t u32OpAfterError) +{ + DDL_ASSERT(IS_SRAM_ERR_OP(u32OpAfterError)); + DDL_ASSERT(M4_SRAMC->CKPR == SRAM_UNLOCK_CMD); + + if ((u32SramIndex & (SRAM_SRAM123 | SRAM_SRAMH)) != 0U) + { + WRITE_REG32(bM4_SRAMC->CKCR_b.PYOAD, u32OpAfterError); + } + + if ((u32SramIndex & SRAM_SRAM4) != 0U) + { + WRITE_REG32(bM4_SRAMC->CKCR_b.ECCOAD, u32OpAfterError); + } + + if ((u32SramIndex & SRAM_SRAMB) != 0U) + { + WRITE_REG32(bM4_SRAMC->CKCR_b.BECCOAD, u32OpAfterError); + } +} + +/** + * @brief Get the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be a value of @ref SRAM_Check_Status_Flag + * @arg SRAM_FLAG_SRAM1_PYERR: SRAM1 parity error. + * @arg SRAM_FLAG_SRAM2_PYERR: SRAM2 parity error. + * @arg SRAM_FLAG_SRAM3_PYERR: SRAM3 parity error. + * @arg SRAM_FLAG_SRAMH_PYERR: SRAMH parity error. + * @arg SRAM_FLAG_SRAM4_1ERR: SRAM4 ECC 1-bit error. + * @arg SRAM_FLAG_SRAM4_2ERR: SRAM4 ECC 2-bit error. + * @arg SRAM_FLAG_SRAMB_1ERR: SRAMB ECC 1-bit error. + * @arg SRAM_FLAG_SRAMB_2ERR: SRAMB ECC 2-bit error. + * @arg SRAM_FLAG_CACHE_PYERR: Cache RAM parity error. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: The specified flag is set. + * @arg Reset: The specified flag is not set. + */ +en_flag_status_t SRAM_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlag = Reset; + + if (READ_REG32_BIT(M4_SRAMC->CKSR, (u32Flag & SRAM_FLAG_ALL)) != 0U) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief Clear the status of the specified flag of SRAM. + * @param [in] u32Flag The flag of SRAM. + * This parameter can be a value(s) of @ref SRAM_Check_Status_Flag + * @arg SRAM_FLAG_SRAM1_PYERR: SRAM1 parity error. + * @arg SRAM_FLAG_SRAM2_PYERR: SRAM2 parity error. + * @arg SRAM_FLAG_SRAM3_PYERR: SRAM3 parity error. + * @arg SRAM_FLAG_SRAMH_PYERR: SRAMH parity error. + * @arg SRAM_FLAG_SRAM4_1ERR: SRAM4 ECC 1-bit error. + * @arg SRAM_FLAG_SRAM4_2ERR: SRAM4 ECC 2-bit error. + * @arg SRAM_FLAG_SRAMB_1ERR: SRAMB ECC 1-bit error. + * @arg SRAM_FLAG_SRAMB_2ERR: SRAMB ECC 2-bit error. + * @arg SRAM_FLAG_CACHE_PYERR: Cache RAM parity error. + * @retval None + */ +void SRAM_ClrStatus(uint32_t u32Flag) +{ + SET_REG32_BIT(M4_SRAMC->CKSR, (u32Flag & SRAM_FLAG_ALL)); +} + +/** + * @} + */ + +#endif /* DDL_SRAM_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_swdt.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_swdt.c new file mode 100644 index 0000000000000000000000000000000000000000..944b5521a8fda65dd6b1a36ab512c15134b2a890 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_swdt.c @@ -0,0 +1,262 @@ +/** + ******************************************************************************* + * @file hc32f4a0_swdt.c + * @brief This file provides firmware functions to manage the Special Watch Dog + * Timer(SWDT). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-09-04 Yangjp Optimize timeout handling in functions + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_swdt.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_SWDT SWDT + * @brief Special Watch Dog Timer + * @{ + */ + +#if (DDL_SWDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup SWDT_Local_Macros SWDT Local Macros + * @{ + */ + +/* SWDT Registers Clear Mask */ +#define SWDT_CR_CLEAR_MASK (SWDT_CR_PERI | SWDT_CR_CKS | SWDT_CR_WDPT | \ + SWDT_CR_SLPOFF | SWDT_CR_ITS) + +/* SWDT Refresh Key */ +#define SWDT_REFRESH_KEY_START (0x0123UL) +#define SWDT_REFRESH_KEY_END (0x3210UL) + +/* SWDT clear flag timeout(ms) */ +#define SWDT_CLEAR_FLAG_TIMEOUT (5UL) + +/** + * @defgroup SWDT_Check_Parameters_Validity SWDT Check Parameters Validity + * @{ + */ +#define IS_SWDT_COUNTER_CYCLE(x) \ +( ((x) == SWDT_COUNTER_CYCLE_256) || \ + ((x) == SWDT_COUNTER_CYCLE_4096) || \ + ((x) == SWDT_COUNTER_CYCLE_16384) || \ + ((x) == SWDT_COUNTER_CYCLE_65536)) + +#define IS_SWDT_CLOCK_DIVISION(x) \ +( ((x) == SWDT_CLOCK_DIV1) || \ + ((x) == SWDT_CLOCK_DIV16) || \ + ((x) == SWDT_CLOCK_DIV32) || \ + ((x) == SWDT_CLOCK_DIV64) || \ + ((x) == SWDT_CLOCK_DIV128) || \ + ((x) == SWDT_CLOCK_DIV256) || \ + ((x) == SWDT_CLOCK_DIV2048)) + +#define IS_SWDT_ALLOW_REFRESH_RANGE(x) \ +( ((x) == SWDT_RANGE_0TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT) || \ + ((x) == SWDT_RANGE_25TO50PCT) || \ + ((x) == SWDT_RANGE_0TO50PCT) || \ + ((x) == SWDT_RANGE_50TO75PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == SWDT_RANGE_25TO75PCT) || \ + ((x) == SWDT_RANGE_0TO75PCT) || \ + ((x) == SWDT_RANGE_75TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == SWDT_RANGE_50TO100PCT) || \ + ((x) == SWDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == SWDT_RANGE_25TO100PCT)) + +#define IS_SWDT_LPM_COUNT(x) \ +( ((x) == SWDT_LPM_COUNT_CONTINUE) || \ + ((x) == SWDT_LPM_COUNT_STOP)) + +#define IS_SWDT_REQUEST_TYPE(x) \ +( ((x) == SWDT_TRIG_EVENT_INT) || \ + ((x) == SWDT_TRIG_EVENT_RESET)) + +#define IS_SWDT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(SWDT_FLAG_UDF | SWDT_FLAG_REF)))))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup SWDT_Global_Functions SWDT Global Functions + * @{ + */ + +/** + * @brief Initialize SWDT. + * @param [in] pstcSwdtInit Pointer to a @ref stc_swdt_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t SWDT_Init(const stc_swdt_init_t *pstcSwdtInit) +{ + en_result_t enRet = Ok; + + if(NULL == pstcSwdtInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_SWDT_COUNTER_CYCLE(pstcSwdtInit->u32CountCycle)); + DDL_ASSERT(IS_SWDT_CLOCK_DIVISION(pstcSwdtInit->u32ClockDivision)); + DDL_ASSERT(IS_SWDT_ALLOW_REFRESH_RANGE(pstcSwdtInit->u32RefreshRange)); + DDL_ASSERT(IS_SWDT_LPM_COUNT(pstcSwdtInit->u32LPModeCountEn)); + DDL_ASSERT(IS_SWDT_REQUEST_TYPE(pstcSwdtInit->u32TrigType)); + + /* SWDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(M4_SWDT->CR, SWDT_CR_CLEAR_MASK, + (pstcSwdtInit->u32CountCycle | pstcSwdtInit->u32ClockDivision | + pstcSwdtInit->u32RefreshRange | pstcSwdtInit->u32LPModeCountEn | + pstcSwdtInit->u32TrigType)); + } + + return enRet; +} + +/** + * @brief SWDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void SWDT_Feed(void) +{ + WRITE_REG32(M4_SWDT->RR, SWDT_REFRESH_KEY_START); + WRITE_REG32(M4_SWDT->RR, SWDT_REFRESH_KEY_END); +} + +/** + * @brief Get SWDT flag status. + * @param [in] u32Flag Specifies the SWDT flag type. + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count Underflow flag + * @arg SWDT_FLAG_REF: Refresh Error flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t SWDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_SWDT->SR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Clear SWDT flag status. + * @param [in] u32Flag Specifies the SWDT flag type. + * This parameter can be one or any combination of the following values: + * @arg SWDT_FLAG_UDF: Count Underflow flag + * @arg SWDT_FLAG_REF: Refresh Error flag + * @retval An en_result_t enumeration value: + * - Ok: Clear flag success + * - ErrorTimeout: Clear flag timeout + */ +en_result_t SWDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_SWDT_FLAG(u32Flag)); + + CLEAR_REG32_BIT(M4_SWDT->SR, u32Flag); + /* Waiting for FLAG bit clear */ + u32Count = SWDT_CLEAR_FLAG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(M4_SWDT->SR, u32Flag)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_SWDT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr0.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr0.c new file mode 100644 index 0000000000000000000000000000000000000000..ae2b9a4e722ee18d8fc8ebfdafcacd7e143298bf --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr0.c @@ -0,0 +1,592 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmr0.c + * @brief This file provides firmware functions to manage the TMR0 + * (TMR0). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_tmr0.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_TMR0 TMR0 + * @brief TMR0 Driver Library + * @{ + */ + +#if (DDL_TMR0_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR0_Local_Macros TMR0 Local Macros + * @{ + */ +#define TMR0_BCONR_INIT_MSK (TMR0_BCONR_CAPMDA | TMR0_BCONR_CKDIVA | \ + TMR0_BCONR_HICPA | TMR0_BCONR_HSTAA | \ + TMR0_BCONR_HSTPA | TMR0_BCONR_HCLEA) + +#define TMR0_CHA_CLKSRC_MSK (TMR0_BCONR_SYNSA | \ + TMR0_BCONR_SYNCLKA | \ + TMR0_BCONR_ASYNCLKA) +#define TMR0_CHB_CLKSRC_MSK (TMR0_BCONR_SYNSB | \ + TMR0_BCONR_SYNCLKB | \ + TMR0_BCONR_ASYNCLKB) + +#define TMR0_CHB_POS (16U) +#define TMR0_OFFEST(ch) ((ch) * TMR0_CHB_POS) +/** + * @defgroup TMR0_Check_Parameters_Validity TMR0 Check Parameters Validity + * @{ + */ +#define IS_VALID_UNIT(x) \ +( ((x) == M4_TMR0_1) || \ + ((x) == M4_TMR0_2)) + +#define IS_VALID_CHANNEL(x) \ +( ((x) == TMR0_CH_A) || \ + ((x) == TMR0_CH_B)) + +#define IS_VALID_CLK_DIVISION(x) \ +( ((x) == TMR0_CLK_DIV1) || \ + ((x) == TMR0_CLK_DIV2) || \ + ((x) == TMR0_CLK_DIV4) || \ + ((x) == TMR0_CLK_DIV8) || \ + ((x) == TMR0_CLK_DIV16) || \ + ((x) == TMR0_CLK_DIV32) || \ + ((x) == TMR0_CLK_DIV64) || \ + ((x) == TMR0_CLK_DIV128) || \ + ((x) == TMR0_CLK_DIV256) || \ + ((x) == TMR0_CLK_DIV512) || \ + ((x) == TMR0_CLK_DIV1024)) + +#define IS_VALID_CLK_SRC(x) \ +( ((x) == TMR0_CLK_SRC_PCLK1) || \ + ((x) == TMR0_CLK_SRC_INTHWTRIG) || \ + ((x) == TMR0_CLK_SRC_XTAL32) || \ + ((x) == TMR0_CLK_SRC_LRC)) + +#define IS_VALID_HWTRG_FUNC(x) \ +( ((x) | TMR0_BT_HETRG_FUNC_MASK) == TMR0_BT_HETRG_FUNC_MASK) + +#define IS_VALID_TMR0_FUNC(x) \ +( ((x) == TMR0_FUNC_CMP) || \ + ((x) == TMR0_FUNC_CAP)) + +#define IS_VALID_TMR0_COM_TRIG(x) \ +( ((x) != 0x0UL) && \ + (((x) | TMR0_COM_TRIG_MASk) == TMR0_COM_TRIG_MASk)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR0_Global_Functions TMR0 Global Functions + * @{ + */ + +/** + * @brief Set a default value for TMR0 configuration structure. + * @param [in] pstcInitStruct Tmr0 function structure + * See the structure definition for @ref stc_tmr0_init_t + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + */ +en_result_t TMR0_StructInit(stc_tmr0_init_t* pstcInitStruct) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInitStruct != NULL) + { + pstcInitStruct->u32ClockDivision = TMR0_CLK_DIV1; + pstcInitStruct->u32ClockSource = TMR0_CLK_SRC_PCLK1; + pstcInitStruct->u32Tmr0Func = TMR0_FUNC_CMP; + pstcInitStruct->u16CmpValue = 0xFFFFU; + pstcInitStruct->u16CntValue = 0x0000U; + pstcInitStruct->u32HwTrigFunc = TMR0_BT_HWTRG_FUNC_NONE; + enRet = Ok; + } + return enRet; +} + +/** + * @brief Tmr0 peripheral function initialize + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_CH_A or TMR0_CH_B + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] pstcTmr0Init TMR0 function base parameter structure + * @arg See the structure definition for @ref stc_tmr0_init_t + * @retval Ok: Success + * ErrorInvalidParameter: Parameter error + * @note In capture mode, don't need configure member u32HwTrigFunc and u16CmpValue. + * In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + */ +en_result_t TMR0_Init(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, \ + const stc_tmr0_init_t* pstcTmr0Init) +{ + uint32_t u32Temp; + uint32_t u32CMPRAddr; + uint32_t u32CNTRAddr; + en_result_t enRet = ErrorInvalidParameter; + if (pstcTmr0Init != NULL) + { + enRet = Ok; + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + DDL_ASSERT(IS_VALID_CLK_DIVISION(pstcTmr0Init->u32ClockDivision)); + DDL_ASSERT(IS_VALID_CLK_SRC(pstcTmr0Init->u32ClockSource)); + DDL_ASSERT(IS_VALID_TMR0_FUNC(pstcTmr0Init->u32Tmr0Func)); + DDL_ASSERT(IS_VALID_HWTRG_FUNC(pstcTmr0Init->u32HwTrigFunc)); + + u32Temp = (uint32_t)u8Channel * 4UL; + u32CNTRAddr = (uint32_t)(&TMR0x->CNTAR) + u32Temp; + u32CMPRAddr = (uint32_t)(&TMR0x->CMPAR) + u32Temp; + RW_MEM32(u32CNTRAddr) = pstcTmr0Init->u16CntValue; + RW_MEM32(u32CMPRAddr) = pstcTmr0Init->u16CmpValue; + + u32Temp = pstcTmr0Init->u32ClockDivision | \ + pstcTmr0Init->u32HwTrigFunc | \ + pstcTmr0Init->u32Tmr0Func; + + u8Channel *= TMR0_CHB_POS; + /* Config mode, clock source */ + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_INIT_MSK << u8Channel), (u32Temp << u8Channel)); + /* Config clock mode */ + MODIFY_REG32(TMR0x->BCONR, (TMR0_CHA_CLKSRC_MSK << u8Channel), (pstcTmr0Init->u32ClockSource << u8Channel)); + } + return enRet; +} + +/** + * @brief Set clock source. + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_ChannelA or TMR0_ChannelB + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] u32ClkSrc Specifies the clock source + * This parameter can be a value of the following: + * @arg TMR0_CLK_SRC_PCLK1: Synchronous clock source: PCLK1. + * @arg TMR0_CLK_SRC_INTHWTRIG: Synchronous clock source: Hardware Trigger Event. + * @arg TMR0_CLK_SRC_XTAL32: Asynchronous clock source: XTAl32 + * @arg TMR0_CLK_SRC_LRC: Asynchronous clock source: LRC + * @retval None. + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + */ +void TMR0_SetClkSrc(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, uint32_t u32ClkSrc) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + DDL_ASSERT(IS_VALID_CLK_SRC(u32ClkSrc)); + + u8Channel = TMR0_OFFEST(u8Channel); + MODIFY_REG32(TMR0x->BCONR, (TMR0_CHA_CLKSRC_MSK << u8Channel), (u32ClkSrc << u8Channel)); +} + +/** + * @brief Set the division of the clock source. + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_ChannelA or TMR0_ChannelB + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] u32ClkDiv Specifies the clock source division + * This parameter can be a value of the following: + * @arg TMR0_CLK_DIV1: Clock source. + * @arg TMR0_CLK_DIV2: Clock source / 2. + * @arg TMR0_CLK_DIV4: Clock source / 4. + * @arg TMR0_CLK_DIV8: Clock source / 8. + * @arg TMR0_CLK_DIV16: Clock source / 16. + * @arg TMR0_CLK_DIV32: Clock source / 32. + * @arg TMR0_CLK_DIV64: Clock source / 64. + * @arg TMR0_CLK_DIV128: Clock source / 128. + * @arg TMR0_CLK_DIV256: Clock source / 256. + * @arg TMR0_CLK_DIV512: Clock source / 512. + * @arg TMR0_CLK_DIV1024: Clock source / 1024. + * @retval None. + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + */ +void TMR0_SetClkDiv(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, uint32_t u32ClkDiv) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + DDL_ASSERT(IS_VALID_CLK_DIVISION(u32ClkDiv)); + + u8Channel = TMR0_OFFEST(u8Channel); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CKDIVA << u8Channel), (u32ClkDiv << u8Channel)); +} + +/** + * @brief Set Tmr0 HardWare Trigger Function + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_ChannelA or TMR0_ChannelB + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] u32HWFunc Select TMR0 hardware trigger function + * This parameter can be a value of @ref TMR0_HardwareTrigger_Func_define + * @param [in] enNewState Disable or Enable the function + * @retval None + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + */ +void TMR0_HWTrigCmd(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, \ + uint32_t u32HWFunc, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + DDL_ASSERT(IS_VALID_HWTRG_FUNC(u32HWFunc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8Channel = TMR0_OFFEST(u8Channel); + if(enNewState == Enable) + { + MODIFY_REG32(TMR0x->BCONR, (u32HWFunc << u8Channel), (u32HWFunc << u8Channel)); + } + else + { + CLEAR_REG32_BIT(TMR0x->BCONR, (u32HWFunc << u8Channel)); + } +} + +/** + * @brief Set Tmr0 Function + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_CH_A or TMR0_CH_B + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] u32Func Select TMR0 function + * @arg TMR0_FUNC_CMP: Select the Compare function for TMR0 + * @arg TMR0_FUNC_CAP: Select the Capture function for TMR0 + * @retval None + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + */ +void TMR0_SetFunc(M4_TMR0_TypeDef *TMR0x, uint8_t u8Channel, uint32_t u32Func) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + DDL_ASSERT(IS_VALID_TMR0_FUNC(u32Func)); + + u8Channel = TMR0_OFFEST(u8Channel); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CAPMDA << u8Channel), (u32Func << u8Channel)); +} + +/** + * @brief Get Tmr0 status (STFLR) + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_CH_A or TMR0_CH_B + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @retval Set: Flag is set + * Reset: Flag is reset + */ +en_flag_status_t TMR0_GetStatus(const M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel) +{ + en_flag_status_t enRet = Reset; + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + + u8Channel = TMR0_OFFEST(u8Channel); + if (READ_REG32_BIT(TMR0x->STFLR, (TMR0_STFLR_CMFA << u8Channel)) != 0U) + { + enRet = Set; + } + return enRet; +} + +/** + * @brief Clear Tmr0 status (STFLR) + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_CH_A or TMR0_CH_B + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @retval None + * @note In asynchronous clock, continuous operation of the STFLR register requires waiting for 3 asynchronous clocks. + */ +void TMR0_ClearStatus(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + + u8Channel = TMR0_OFFEST(u8Channel); + /*Clear the Flag*/ + CLEAR_REG32_BIT(TMR0x->STFLR, (TMR0_STFLR_CMFA << u8Channel)); +} + +/** + * @brief Command the tmr0 function + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_CH_A or TMR0_CH_B + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] enNewState Disable or Enable the function + * @retval None + * @note In asynchronous clock, continuous operation of the BCONR register requires waiting for 3 asynchronous clocks. + */ +void TMR0_Cmd(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8Channel = TMR0_OFFEST(u8Channel); + MODIFY_REG32(TMR0x->BCONR, (TMR0_BCONR_CSTA <BCONR, (TMR0_BCONR_INTENA << u8Channel), ((uint32_t)enNewState << TMR0_BCONR_INTENA_POS) << u8Channel); +} + +/** + * @brief Get Tmr0 counter value + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_ChannelA or TMR0_ChannelB + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @retval In asynchronous clock, Get the value requires stop timer0 + * + */ +uint16_t TMR0_GetCntVal(const M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel) +{ + uint16_t u16CntVal; + uint32_t u32CNTRAddr; + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + + u32CNTRAddr = (uint32_t)&TMR0x->CNTAR + (uint32_t)u8Channel * 4UL; + u16CntVal = (uint16_t)RW_MEM32(u32CNTRAddr); + return u16CntVal; +} + +/** + * @brief Set Tmr0 counter value + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_CH_A or TMR0_CH_B + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] u16Value The data to write to the counter register + * @retval None + * @note Setting the count requires stop timer0 + */ +void TMR0_SetCntVal(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, uint16_t u16Value) +{ + uint32_t u32CNTRAddr; + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + + u32CNTRAddr = (uint32_t)&TMR0x->CNTAR + (uint32_t)u8Channel * 4UL; + RW_MEM32(u32CNTRAddr) = (uint32_t)u16Value; +} + +/** + * @brief Get Tmr0 base compare value + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_ChannelA or TMR0_ChannelB + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @retval In asynchronous clock, Get the value requires stop timer0 + */ +uint16_t TMR0_GetCmpVal(const M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel) +{ + uint16_t u16CmpVal; + uint32_t u32CMPRAddr; + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + + u32CMPRAddr = (uint32_t)&TMR0x->CMPAR + (uint32_t)u8Channel * 4UL; + u16CmpVal = (uint16_t)RW_MEM32(u32CMPRAddr); + return u16CmpVal; +} + +/** + * @brief Set Tmr0 compare value + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @param [in] u8Channel TMR0_ChannelA or TMR0_ChannelB + * @arg TMR0_CH_A. + * @arg TMR0_CH_B. + * @param [in] u16Value The data to write to the compare register + * @retval Setting the count requires stop timer0 + */ +void TMR0_SetCmpVal(M4_TMR0_TypeDef* TMR0x, uint8_t u8Channel, uint16_t u16Value) +{ + uint32_t u32CMPRAddr; + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + DDL_ASSERT(IS_VALID_CHANNEL(u8Channel)); + + u32CMPRAddr = (uint32_t)&TMR0x->CMPAR + (uint32_t)u8Channel * 4UL; + RW_MEM32(u32CMPRAddr) = (uint32_t)u16Value; +} + +/** + * @brief De-Initialize TMR0 function + * @param [in] TMR0x Pointer to TMR0 instance register base. + * This parameter can be value of the following: + * @arg M4_TMR0_1: TMR0 unit 1 instance register base + * @arg M4_TMR0_2: TMR0 unit 2 instance register base + * @retval None + */ +void TMR0_DeInit(M4_TMR0_TypeDef* TMR0x) +{ + DDL_ASSERT(IS_VALID_UNIT(TMR0x)); + + WRITE_REG32(TMR0x->CMPAR, 0x0000FFFFUL); + WRITE_REG32(TMR0x->CMPBR, 0x0000FFFFUL); + WRITE_REG32(TMR0x->CNTAR, 0UL); + WRITE_REG32(TMR0x->CNTBR, 0UL); + WRITE_REG32(TMR0x->STFLR, 0UL); + WRITE_REG32(TMR0x->BCONR, 0UL); +} + +/** + * @brief Enable or Disable common trigger source for Tmr0 + * @param [in] u32ComTrig Common trigger event enable bit mask. + * This parameter can be value of @ref TMR0_Common_Trigger_Sel + * @arg TMR0_COM_TRIG1: Common trigger source 1. + * @arg TMR0_COM_TRIG2: Common trigger source 2. + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR0_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_TMR0_COM_TRIG(u32ComTrig)); + + if (enNewState == Enable) + { + SET_REG32_BIT(M4_AOS->TMR0_HTSSR, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(M4_AOS->TMR0_HTSSR, u32ComTrig); + } +} + +/** + * @brief Set trigger source for Tmr0 + * @param [in] enEvent External event source, @ref en_event_src_t + * @retval None + */ +void TMR0_SetTriggerSrc(en_event_src_t enEvent) +{ + MODIFY_REG32(M4_AOS->TMR0_HTSSR, AOS_TMR0_HTSSR_TRGSEL, (uint32_t)enEvent); +} + +/** + * @} +*/ + +#endif /* DDL_TMR0_ENABLE */ + +/** + * @} +*/ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr2.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr2.c new file mode 100644 index 0000000000000000000000000000000000000000..c241c5854028448c3a487731d3ebd3a0b628edb6 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr2.c @@ -0,0 +1,1129 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmr2.c + * @brief This file provides firmware functions to manage the TMR2(Timer2). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_tmr2.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_TMR2 TMR2 + * @brief TMR2 Driver Library + * @{ + */ +#if (DDL_TMR2_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR2_Local_Macros TMR2 Local Macros + * @{ + */ + +/** + * @defgroup TMR2_Configuration_Bit_Mask TMR2 Configuration Bit Mask + * @{ + */ +#define TMR2_BCONR_INIT_MSK (TMR2_BCONR_CAPMDA | TMR2_BCONR_SYNSA | TMR2_BCONR_SYNCLKA | TMR2_BCONR_ASYNCLKA | \ + TMR2_BCONR_CKDIVA | TMR2_BCONR_SYNCLKAT_0 | TMR2_BCONR_SYNCLKAT_1) +#define TMR2_FUNC_MODE_MSK (TMR2_BCONR_CAPMDA) +#define TMR2_CLK_SRC_MSK (TMR2_BCONR_SYNSA |TMR2_BCONR_SYNCLKA |TMR2_BCONR_ASYNCLKA | TMR2_BCONR_SYNCLKAT_0 | \ + TMR2_BCONR_SYNCLKAT_1) +#define TMR2_CLK_DIV_MSK (TMR2_BCONR_CKDIVA) +#define TMR2_PWM_START_POLARITY_MSK (TMR2_PCONR_STACA) +#define TMR2_PWM_STOP_POLARITY_MSK (TMR2_PCONR_STPCA) +#define TMR2_PWM_CMP_POLARITY_MSK (TMR2_PCONR_CMPCA) +#define TMR2_PWM_POLARITY_MSK (TMR2_PCONR_STACA | TMR2_PCONR_STPCA | TMR2_PCONR_CMPCA) +#define TMR2_FILTER_CLK_DIV_MSK (TMR2_PCONR_NOFICKA) +#define TMR2_START_COND_MSK (TMR2_HCONR_HSTAA0 | TMR2_HCONR_HSTAA1 | TMR2_HCONR_HSTAA2) +#define TMR2_STOP_COND_MSK (TMR2_HCONR_HSTPA0 | TMR2_HCONR_HSTPA1 | TMR2_HCONR_HSTPA2) +#define TMR2_CLR_COND_MSK (TMR2_HCONR_HCLEA0 | TMR2_HCONR_HCLEA1 | TMR2_HCONR_HCLEA2) +#define TMR2_CAPT_COND_MSK (TMR2_HCONR_HICPA0 | TMR2_HCONR_HICPA1 | TMR2_HCONR_HICPA2) +#define TMR2_TRIG_COND_MSK (TMR2_START_COND_MSK | TMR2_STOP_COND_MSK | TMR2_CLR_COND_MSK | TMR2_CAPT_COND_MSK) +#define TMR2_INT_TYPE_MSK (TMR2_ICONR_CMENA | TMR2_ICONR_OVENA) +#define TMR2_COM_TRIG_MSK (TMR2_COM_TRIG1 | TMR2_COM_TRIG2) +#define TMR2_TRIG_EVENT_MSK (AOS_TMR2_HTSSR_TRGSEL) +/** + * @} + */ + +/** + * @defgroup TMR2_Channel_Cfg_Bit_Field_Offset TMR2 Channel Configuration Bit Field Offset + * @{ + */ +#define TMR2_BCONR_OFFSET (TMR2_BCONR_CSTB_POS) +#define TMR2_ICONR_OFFSET (TMR2_ICONR_CMENB_POS) +#define TMR2_PCONR_OFFSET (TMR2_PCONR_STACB_POS) +#define TMR2_HCONR_OFFSET (TMR2_HCONR_HSTAB0_POS) +/** + * @} + */ + +/** + * @defgroup TMR2_Register_Bit_Band TMR2 Register Bit Band + * @{ + */ +#define __BIT_BAND_BASE (0x42000000UL) +#define __PERIP_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIP_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __BIT_BAND_BASE) +#define BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup TMR2_Check_Parameters_Validity TMR2 check parameters validity + * @{ + */ +#define IS_TMR2_UNIT(x) \ +( ((x) == M4_TMR2_1) || \ + ((x) == M4_TMR2_2) || \ + ((x) == M4_TMR2_3) || \ + ((x) == M4_TMR2_4)) + +#define IS_TMR2_CH(x) \ +( ((x) <= TMR2_CH_B)) + +#define IS_TMR2_FUNC_MODE(x) \ +( ((x) == TMR2_FUNC_COMPARE) || \ + ((x) == TMR2_FUNC_CAPTURE)) + +#define IS_TMR2_CLK_SRC(x) \ +( ((x) == TMR2_CLK_SYNC_PCLK1) || \ + ((x) == TMR2_CLK_SYNC_TRIGR) || \ + ((x) == TMR2_CLK_SYNC_TRIGF) || \ + ((x) == TMR2_CLK_SYNC_EVENT) || \ + ((x) == TMR2_CLK_SYNC_TIMER6_OVF) || \ + ((x) == TMR2_CLK_SYNC_TIMER6_UDF) || \ + ((x) == TMR2_CLK_ASYNC_LRC) || \ + ((x) == TMR2_CLK_ASYNC_XTAL32) || \ + ((x) == TMR2_CLK_ASYNC_PIN_CLK)) + +#define IS_TMR2_STATUS_FLAG(x) \ +( ((x) == TMR2_FLAG_CMP) || \ + ((x) == TMR2_FLAG_OVF)) + +#define IS_TMR2_CLK_DIV(x) \ +( ((x) == TMR2_CLK_DIV1) || \ + ((x) == TMR2_CLK_DIV2) || \ + ((x) == TMR2_CLK_DIV4) || \ + ((x) == TMR2_CLK_DIV8) || \ + ((x) == TMR2_CLK_DIV16) || \ + ((x) == TMR2_CLK_DIV32) || \ + ((x) == TMR2_CLK_DIV64) || \ + ((x) == TMR2_CLK_DIV128) || \ + ((x) == TMR2_CLK_DIV256) || \ + ((x) == TMR2_CLK_DIV512) || \ + ((x) == TMR2_CLK_DIV1024)) + +#define IS_TMR2_FILTER_CLK_DIV(x) \ +( ((x) == TMR2_FILTER_CLK_DIV1) || \ + ((x) == TMR2_FILTER_CLK_DIV4) || \ + ((x) == TMR2_FILTER_CLK_DIV16) || \ + ((x) == TMR2_FILTER_CLK_DIV64)) + +#define IS_TMR2_PWM_START_POLARITY(x) \ +( ((x) == TMR2_PWM_START_LOW) || \ + ((x) == TMR2_PWM_START_HIGH) || \ + ((x) == TMR2_PWM_START_KEEP)) + +#define IS_TMR2_PWM_STOP_POLARITY(x) \ +( ((x) == TMR2_PWM_STOP_LOW) || \ + ((x) == TMR2_PWM_STOP_HIGH) || \ + ((x) == TMR2_PWM_STOP_KEEP)) + +#define IS_TMR2_PWM_CMP_POLARITY(x) \ +( ((x) == TMR2_PWM_CMP_LOW) || \ + ((x) == TMR2_PWM_CMP_HIGH) || \ + ((x) == TMR2_PWM_CMP_KEEP) || \ + ((x) == TMR2_PWM_CMP_REVERSE)) + +#define IS_TMR2_COM_TRIGGER(x) \ +( ((x) != 0U) && \ + (((x) | TMR2_COM_TRIG_MSK) == TMR2_COM_TRIG_MSK)) + +#define IS_TMR2_VALID_VAL(x) \ +( (x) <= 0xFFFFUL) + +/** + * @} + */ + +/** + * @defgroup TMR2_Miscellaneous_Macros TMR2 Miscellaneous Macros + * @{ + */ +#define TMR2_CH_COUNT (2U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMR2_Global_Functions TMR2 Global Functions + * @{ + */ + +/** + * @brief Initializes the specified TMR2 channel according to the specified parameters \ + * in the structure stc_tmr2_init_t + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] pstcInit Pointer to a stc_tmr2_init_t structure value that \ + * contains the configuration information for the TMR2 channel. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t TMR2_Init(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_init_t *pstcInit) +{ + uint32_t u32Temp; + uint32_t u32CMPRAddr; + uint32_t u32CNTRAddr; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_FUNC_MODE(pstcInit->u32FuncMode)); + DDL_ASSERT(IS_TMR2_CLK_SRC(pstcInit->u32ClkSrc)); + DDL_ASSERT(IS_TMR2_CLK_DIV(pstcInit->u32ClkDiv)); + DDL_ASSERT(IS_TMR2_VALID_VAL(pstcInit->u32CmpVal)); + DDL_ASSERT(IS_TMR2_VALID_VAL(pstcInit->u32CntVal)); + + u32Temp = (uint32_t)u8Tmr2Ch * 4U; + u32CMPRAddr = (uint32_t)&TMR2x->CMPAR + u32Temp; + u32CNTRAddr = (uint32_t)&TMR2x->CNTAR + u32Temp; + RW_MEM32(u32CMPRAddr) = pstcInit->u32CmpVal; + RW_MEM32(u32CNTRAddr) = pstcInit->u32CntVal; + + u32Temp = pstcInit->u32FuncMode | \ + pstcInit->u32ClkSrc | \ + pstcInit->u32ClkDiv; + + /* Channel bit filed offset. */ + u8Tmr2Ch *= TMR2_BCONR_OFFSET; + MODIFY_REG32(TMR2x->BCONR, (TMR2_BCONR_INIT_MSK << u8Tmr2Ch), (u32Temp << u8Tmr2Ch)); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for TMR2 initialization structure. + * @param [in] pstcInit Pointer to a stc_tmr2_init_t structure that + * contains configuration information. + * @retval An en_result_t enumeration type value. + * @arg Ok: No errors occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t TMR2_StructInit(stc_tmr2_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + pstcInit->u32FuncMode = TMR2_FUNC_COMPARE; + pstcInit->u32ClkSrc = TMR2_CLK_SYNC_PCLK1; + pstcInit->u32ClkDiv = TMR2_CLK_DIV1; + pstcInit->u32CmpVal = 0xFFFFUL; + pstcInit->u32CntVal = 0U; + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initializes the specified TMR2 unit. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @retval None + */ +void TMR2_DeInit(M4_TMR2_TypeDef *TMR2x) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + + TMR2_Stop(TMR2x, TMR2_CH_A); + TMR2_Stop(TMR2x, TMR2_CH_B); + + CLEAR_REG32(TMR2x->CNTAR); + CLEAR_REG32(TMR2x->CNTBR); + CLEAR_REG32(TMR2x->BCONR); + CLEAR_REG32(TMR2x->ICONR); + CLEAR_REG32(TMR2x->PCONR); + CLEAR_REG32(TMR2x->HCONR); + CLEAR_REG32(TMR2x->STFLR); + + WRITE_REG32(TMR2x->CMPAR, 0xFFFFU); + WRITE_REG32(TMR2x->CMPBR, 0xFFFFU); +} + +/** + * @brief Configures the specified channel's PWM output polarity according to the specified \ + * parameters in the structure stc_tmr2_pwm_cfg_t + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] pstcCfg Pointer to a stc_tmr2_pwm_cfg_t structure value that contains \ + * the configuration information for the PWM output polarity. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t TMR2_PWM_Config(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_pwm_cfg_t *pstcCfg) +{ + uint32_t u32Cfg; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_PWM_START_POLARITY(pstcCfg->u32StartPolarity)); + DDL_ASSERT(IS_TMR2_PWM_STOP_POLARITY(pstcCfg->u32StopPolarity)); + DDL_ASSERT(IS_TMR2_PWM_CMP_POLARITY(pstcCfg->u32CmpPolarity)); + + u32Cfg = pstcCfg->u32StartPolarity | \ + pstcCfg->u32StopPolarity | \ + pstcCfg->u32CmpPolarity; + u8Tmr2Ch *= TMR2_PCONR_OFFSET; + MODIFY_REG32(TMR2x->PCONR, (TMR2_PWM_POLARITY_MSK << u8Tmr2Ch), (u32Cfg << u8Tmr2Ch)); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for TMR2 PWM configuration structure. + * @param [in] pstcCfg Pointer to a stc_tmr2_pwm_cfg_t structure value that contains \ + * the configuration information for the PWM output polarity. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t TMR2_PWM_StructInit(stc_tmr2_pwm_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + pstcCfg->u32StartPolarity = TMR2_PWM_START_HIGH; + pstcCfg->u32StopPolarity = TMR2_PWM_STOP_LOW; + pstcCfg->u32CmpPolarity = TMR2_PWM_CMP_REVERSE; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable PWM output of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] enNewState An @ref en_functional_state_t value. + * @arg Enable: Enable PWM output of the specified TMR2's channel. + * @arg Disable: Disable PWM output of the specified TMR2's channel. + * @retval None + */ +void TMR2_PWM_Cmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + uint8_t au8EnPos[] = {TMR2_PCONR_OUTENA_POS, TMR2_PCONR_OUTENB_POS}; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMR2x->PCONR; + BIT_BAND(u32Addr, au8EnPos[u8Tmr2Ch]) = (uint32_t)enNewState; +} + +/** + * @brief Specify the channel's hardware trigger condition according to the specified \ + * parameters in the structure stc_tmr2_trig_cond_t + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] pstcCond Pointer to a stc_tmr2_trig_cond_t structure value that contains \ + * the configuration information for the hardware condition. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCond == NULL. + */ +en_result_t TMR2_SetTrigCond(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, const stc_tmr2_trig_cond_t *pstcCond) +{ + uint32_t u32Cfg; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCond != NULL) + { + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + + u32Cfg = (pstcCond->u32StartCond | \ + pstcCond->u32StopCond | \ + pstcCond->u32ClrCond | \ + pstcCond->u32CaptCond) & TMR2_TRIG_COND_MSK; + u8Tmr2Ch *= TMR2_HCONR_OFFSET; + MODIFY_REG32(TMR2x->HCONR, (TMR2_TRIG_COND_MSK << u8Tmr2Ch), (u32Cfg << u8Tmr2Ch)); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for TMR2 hardware trigger condition structure. + * @param [in] pstcCond Pointer to a stc_tmr2_trig_cond_t structure value that contains \ + * the configuration information for the hardware condition. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCond == NULL. + */ +en_result_t TMR2_TrigCondStructInit(stc_tmr2_trig_cond_t *pstcCond) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCond != NULL) + { + pstcCond->u32StartCond = TMR2_START_COND_INVALID; + pstcCond->u32StopCond = TMR2_STOP_COND_INVALID; + pstcCond->u32ClrCond = TMR2_CLR_COND_INVALID; + pstcCond->u32CaptCond = TMR2_CAPT_COND_INVALID; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set trigger source for TMR2. + * @param [in] enEvent An en_event_src_t enumeration type value. + * @retval None + */ +void TMR2_SetTriggerSrc(en_event_src_t enEvent) +{ + MODIFY_REG32(M4_AOS->TMR2_HTSSR, TMR2_TRIG_EVENT_MSK, enEvent); +} + +/** + * @brief Enable or disable common trigger event for the specified usage. + * @param [in] u32ComTrig Common trigger event enable bit mask. + * This parameter can be a value of @ref TMR2_Common_Trigger_Sel + * @arg TMR2_COM_TRIG1: Common trigger 1. + * @arg TMR2_COM_TRIG2: Common trigger 2. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified common trigger. + * @arg Disable: Disable the specified common trigger. + * @retval None + */ +void TMR2_ComTriggerCmd(uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_COM_TRIGGER(u32ComTrig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (enNewState == Enable) + { + SET_REG32_BIT(M4_AOS->TMR2_HTSSR, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(M4_AOS->TMR2_HTSSR, u32ComTrig); + } +} + +/** + * @brief Set clock divider for the filter of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32ClkDiv Clock divider for the specified TMR2 unit channel filter. + * This parameter can be a value of @ref TMR2_Filter_Clock_Divider + * @arg TMR2_FILTER_CLK_DIV1: Clock source. + * @arg TMR2_FILTER_CLK_DIV4: Clock source / 4. + * @arg TMR2_FILTER_CLK_DIV16: Clock source / 16. + * @arg TMR2_FILTER_CLK_DIV64: Clock source / 64. + * @retval None + */ +void TMR2_FilterConfig(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkDiv) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_FILTER_CLK_DIV(u32ClkDiv)); + + u8Tmr2Ch *= TMR2_PCONR_OFFSET; + MODIFY_REG32(TMR2x->PCONR, \ + (TMR2_FILTER_CLK_DIV_MSK << u8Tmr2Ch), \ + (u32ClkDiv << u8Tmr2Ch)); +} + +/** + * @brief Enable or disable the filter of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] enNewState An @ref en_functional_state_t value. + * @arg Enable: Enable the filter of the specified channel. + * @arg Disable: Disable the filter of the specified channel. + * @retval None + */ +void TMR2_FilterCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + uint8_t au8EnPos[] = {TMR2_PCONR_NOFIENA_POS, TMR2_PCONR_NOFIENB_POS}; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMR2x->PCONR; + BIT_BAND(u32Addr, au8EnPos[u8Tmr2Ch]) = (uint32_t)enNewState; +} + +/** + * @brief Enable or disable the interrupt of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32IntType The interrupt type. + * This parameter can be a value(s) of @ref TMR2_Interrupt_Type + * @arg TMR2_INT_CMP: TMR2 count match interrupt. + * @arg TMR2_INT_OVF: TMR2 count overflow interrupt. + * @param [in] enNewState An @ref en_functional_state_t value. + * @arg Enable: Enable the specified interrupt. + * @arg Disable: Disable the specified interrupt. + * @retval None + */ +void TMR2_IntCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, \ + uint32_t u32IntType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8Tmr2Ch *= TMR2_ICONR_OFFSET; + u32IntType &= TMR2_INT_TYPE_MSK; + u32IntType <<= u8Tmr2Ch; + + if (enNewState == Enable) + { + SET_REG32_BIT(TMR2x->ICONR, u32IntType); + } + else + { + CLEAR_REG32_BIT(TMR2x->ICONR, u32IntType); + } +} + +/** + * @brief Start the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @retval None + */ +void TMR2_Start(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch) +{ + uint32_t au32Cfg[] = {TMR2_BCONR_CSTA, TMR2_BCONR_CSTB}; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + SET_REG32_BIT(TMR2x->BCONR, au32Cfg[u8Tmr2Ch]); +} + +/** + * @brief Stop the specified channel of the specified TMR2 unit. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @retval None + */ +void TMR2_Stop(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch) +{ + uint32_t au32Cfg[] = {TMR2_BCONR_CSTA, TMR2_BCONR_CSTB}; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + CLEAR_REG32_BIT(TMR2x->BCONR, au32Cfg[u8Tmr2Ch]); +} + +/** + * @brief Get the specified flag's status of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Flag TMR2 state flag. + * This parameter can be values of @ref TMR2_State_Flag + * @arg TMR2_FLAG_CMP: Counting match flag. + * @arg TMR2_FLAG_OVF: Counting overflow flag. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified flags is set. + * @arg Reset: None of the specified flags is set. + */ +en_flag_status_t TMR2_GetStatus(const M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Flag) +{ + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_STATUS_FLAG(u32Flag)); + + u32Flag &= TMR2_FLAG_ALL; + u32Flag <<= ((uint32_t)u8Tmr2Ch * TMR2_ICONR_OFFSET); + if (READ_REG32_BIT(TMR2x->STFLR, u32Flag) != 0U) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief Clear the specified flag state of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Flag TMR2 state flag. + * This parameter can be values of @ref TMR2_State_Flag + * @arg TMR2_FLAG_CMP: Counter match flag of channel A/B. + * @arg TMR2_FLAG_OVF: Counter overflow flag of channel A/B. + * @retval None + */ +void TMR2_ClrStatus(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + + /* Bit filed offset. */ + u8Tmr2Ch *= TMR2_ICONR_OFFSET; + u32Flag &= TMR2_FLAG_ALL; + u32Flag <<= u8Tmr2Ch; + CLEAR_REG32_BIT(TMR2x->STFLR, u32Flag); +} + +/** + * @brief Set compare value for the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Val The compare reference value for the specified TMR2's channel. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMR2_SetCmpVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Val) +{ + uint32_t u32CMPRAddr; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_VALID_VAL(u32Val)); + u32CMPRAddr = (uint32_t)&TMR2x->CMPAR + (uint32_t)u8Tmr2Ch * 4U; + RW_MEM32(u32CMPRAddr) = u32Val; +} + +/** + * @brief Get compare value of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @retval The compare value of the specified TMR2's channel. A number between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMR2_GetCmpVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch) +{ + uint32_t u32CMPRAddr; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + + u32CMPRAddr = (uint32_t)&TMR2x->CMPAR + (uint32_t)u8Tmr2Ch * 4U; + return RW_MEM32(u32CMPRAddr); +} + +/** + * @brief Set counter value for the specified channel of the specified TMR2 unit. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel of the specified TMR2 unit. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Val The counter value for the specified TMR2's channel. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMR2_SetCntVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Val) +{ + uint32_t u32CNTRAddr; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_VALID_VAL(u32Val)); + + u32CNTRAddr = (uint32_t)&TMR2x->CNTAR + (uint32_t)u8Tmr2Ch * 4U; + RW_MEM32(u32CNTRAddr) = u32Val; +} + +/** + * @brief Get counter value of the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @retval The counter value of the specified TMR2's channel. A number between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMR2_GetCntVal(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch) +{ + uint32_t u32CNTRAddr; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + u32CNTRAddr = (uint32_t)&TMR2x->CNTAR + (uint32_t)u8Tmr2Ch * 4U; + + return RW_MEM32(u32CNTRAddr); +} + +/** + * @brief Set function mode for the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32FuncMode Specifies the function for the specified TMR2's channel. + * This parameter can be a value of @ref TMR2_Function_Mode + * @arg TMR2_FUNC_COMPARE: Set the function of the specified channel of TMR2 unit as compare output. + * @arg TMR2_FUNC_CAPTURE: Set the function of the specified channel of TMR2 unit as capturing input. + * @retval None + */ +void TMR2_SetFuncMode(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32FuncMode) +{ + uint32_t u32Msk; + uint32_t u32Cfg; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_FUNC_MODE(u32FuncMode)); + + /* Bit filed offset. */ + u8Tmr2Ch *= TMR2_BCONR_OFFSET; + u32Msk = TMR2_FUNC_MODE_MSK << u8Tmr2Ch; + u32Cfg = u32FuncMode << u8Tmr2Ch; + MODIFY_REG32(TMR2x->BCONR, u32Msk, u32Cfg); +} + +/** + * @brief Specify the clock source for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32ClkSrc Specifies the clock source for the specified TMR2's channel. + * This parameter can be a value of @ref TMR2_Clock_Source + * @arg TMR2_SYNC_CLK_PCLK1: Synchronous clock source, PCLK1. + * @arg TMR2_SYNC_CLK_TRIG_RISE: Synchronous clock source, rising edge of TIM2_x_TRIGA/B. + * @arg TMR2_SYNC_CLK_TRIG_FALL: Synchronous clock source, falling edge of TIM2_x_TRIGA/B. + * @arg TMR2_SYNC_CLK_EVENT: Synchronous clock source, peripheral event. + * @arg TMR2_CLK_SYNC_TIMER6_OVF: Synchronous clock source, the event of counting overflow of TIMER6. \ + * It is NOT need to set register TMR2_HTSSR. + * @arg TMR2_CLK_SYNC_TIMER6_UDF: Synchronous clock source, the event of counting underflow of TIMER6. \ + * It is NOT need to set register TMR2_HTSSR. + * @arg TMR2_ASYNC_CLK_LRC: Asynchronous clock source, LRC. + * @arg TMR2_ASYNC_CLK_XTAL32: Asynchronous clock source, XTAL32. + * @arg TMR2_ASYNC_CLK_PIN_CLK: Asynchronous clock source, from pin TIM2_x_CLKA/B. + * @retval None + */ +void TMR2_SetClkSrc(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkSrc) +{ + uint32_t u32Msk; + uint32_t u32Cfg; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_CLK_SRC(u32ClkSrc)); + + /* Bit filed offset. */ + u8Tmr2Ch *= TMR2_BCONR_OFFSET; + u32Msk = TMR2_CLK_SRC_MSK << u8Tmr2Ch; + u32Cfg = u32ClkSrc << u8Tmr2Ch; + MODIFY_REG32(TMR2x->BCONR, u32Msk, u32Cfg); +} + +/** + * @brief Specify the division of the clock source for the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32ClkDiv Specifies the clock source division for the specified TMR2's channel. + * This parameter can be a value of @ref TMR2_Clock_Divider + * @arg TMR2_CLK_DIV1: Clock source. + * @arg TMR2_CLK_DIV2: Clock source / 2. + * @arg TMR2_CLK_DIV4: Clock source / 4. + * @arg TMR2_CLK_DIV8: Clock source / 8. + * @arg TMR2_CLK_DIV16: Clock source / 16. + * @arg TMR2_CLK_DIV32: Clock source / 32. + * @arg TMR2_CLK_DIV64: Clock source / 64. + * @arg TMR2_CLK_DIV128: Clock source / 128. + * @arg TMR2_CLK_DIV256: Clock source / 256. + * @arg TMR2_CLK_DIV512: Clock source / 512. + * @arg TMR2_CLK_DIV1024: Clock source / 1024. + * @retval None + */ +void TMR2_SetClkDiv(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32ClkDiv) +{ + uint32_t u32Msk; + uint32_t u32Cfg; + + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_CLK_DIV(u32ClkDiv)); + + /* Bit filed offset. */ + u8Tmr2Ch *= TMR2_BCONR_OFFSET; + u32Msk = TMR2_CLK_DIV_MSK << u8Tmr2Ch; + u32Cfg = u32ClkDiv << u8Tmr2Ch; + MODIFY_REG32(TMR2x->BCONR, u32Msk, u32Cfg); +} + +/** + * @brief Enable or disable the specified trigger conditions of the specified TMR2 channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Cond The specified conditions. + * This parameter can be a value of + * @ref TMR2_Hardware_Start_Condition \ + * @ref TMR2_Hardware_Stop_Condition \ + * @ref TMR2_Hardware_Clear_Condition \ + * @ref TMR2_Hardware_Capture_Condition + * @arg TMR2_START_COND_TRIG_RISE: The condition of start is the rising edge of TIM2_x_TRIGA/B. + * @arg TMR2_START_COND_TRIG_FALL: The condition of start is the falling edge of TIM2_x_TRIGA/B. + * @arg TMR2_START_COND_EVENT: The condition of start is the specified event occurred. + * @arg TMR2_STOP_COND_TRIG_RISE: The condition of stop is the rising edge of TIM2_x_TRIGA/B. + * @arg TMR2_STOP_COND_TRIG_FALL: The condition of stop is the falling edge of TIM2_x_TRIGA/B. + * @arg TMR2_STOP_COND_EVENT: The condition of stop is the specified event occurred. + * @arg TMR2_CLR_COND_TRIG_RISE: The condition of clear(clear CNTAR/CNTBR) is the rising edge of TIM2_x_TRIGA/B. + * @arg TMR2_CLR_COND_TRIG_FALL: The condition of clear(clear CNTAR/CNTBR) is the falling edge of TIM2_x_TRIGA/B. + * @arg TMR2_CLR_COND_EVENT: The condition of clear(clear CNTAR/CNTBR) is the specified event occurred. + * @arg TMR2_CAPT_COND_TRIG_RISE: The condition for capturing is the rising edge of TIM2_x_TRIGA/B. + * @arg TMR2_CAPT_COND_TRIG_FALL: The condition for capturing is the falling edge of TIM2_x_TRIGA/B. + * @arg TMR2_CAPT_COND_EVENT: The condition for capturing is the specified event occurred. + * @param [in] enNewState An @ref en_functional_state_t value. + * @arg Enable: Enable the sepcified trigger conditions. + * @arg Disable: Disable the sepcified trigger conditions. + * @retval None + */ +void TMR2_TrigCondCmd(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Cond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Cond &= TMR2_TRIG_COND_MSK; + u8Tmr2Ch *= TMR2_HCONR_OFFSET; + u32Cond <<= u8Tmr2Ch; + if (enNewState == Enable) + { + SET_REG32_BIT(TMR2x->HCONR, u32Cond); + } + else + { + CLEAR_REG32_BIT(TMR2x->HCONR, u32Cond); + } +} + +/** + * @brief Set PWM polarity when counting start for the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Polarity Specifies the PWM start polarity for the specified TMR2's channel. + * This parameter can be a value of @ref TMR2_PWM_Start_Polarity + * @arg TMR2_PWM_START_LOW: PWM output low when counting start. + * @arg TMR2_PWM_START_HIGH: PWM output high when counting start. + * @arg TMR2_PWM_START_KEEP: PWM output keeps the current polarity when counting start. + * @retval None + */ +void TMR2_PWM_SetStartPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_PWM_START_POLARITY(u32Polarity)); + + u8Tmr2Ch *= TMR2_PCONR_OFFSET; + MODIFY_REG32(TMR2x->PCONR, \ + (TMR2_PWM_START_POLARITY_MSK << u8Tmr2Ch), \ + (u32Polarity << u8Tmr2Ch)); +} + +/** + * @brief Set PWM polarity when counting stop for the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Polarity Specifies the PWM stop polarity for the specified TMR2's channel. + * This parameter can be a value of @ref TMR2_PWM_Stop_Polarity + * @arg TMR2_PWM_STOP_LOW: PWM output low when counting stop. + * @arg TMR2_PWM_STOP_HIGH: PWM output high when counting stop. + * @arg TMR2_PWM_STOP_KEEP: PWM output keeps the current polarity when counting stop. + * @retval None + */ +void TMR2_PWM_SetStopPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_PWM_STOP_POLARITY(u32Polarity)); + + u8Tmr2Ch *= TMR2_PCONR_OFFSET; + MODIFY_REG32(TMR2x->PCONR, \ + (TMR2_PWM_STOP_POLARITY_MSK << u8Tmr2Ch), \ + (u32Polarity << u8Tmr2Ch)); +} + +/** + * @brief Set PWM polarity when counting compare match for the specified TMR2's channel. + * @param [in] TMR2x Pointer to TMR2 instance register base. + * This parameter can be a value of the following: + * @arg M4_TMR2_1: TMR2 unit 1 instance register base. + * @arg M4_TMR2_2: TMR2 unit 2 instance register base. + * @arg M4_TMR2_3: TMR2 unit 3 instance register base. + * @arg M4_TMR2_4: TMR2 unit 4 instance register base. + * @param [in] u8Tmr2Ch The channel number of TMR2. + * This parameter can be a value of @ref TMR2_Channel_Number + * @arg TMR2_CH_A: Channel A of TMR2. + * @arg TMR2_CH_B: Channel B of TMR2. + * @param [in] u32Polarity Specifies the PWM count match polarity for the specified TMR2's channel. + * This parameter can be a value of @ref TMR2_PWM_Cmp_Polarity + * @arg TMR2_PWM_CMP_LOW: PWM output low when counting compare match. + * @arg TMR2_PWM_CMP_HIGH: PWM output high when counting compare match. + * @arg TMR2_PWM_CMP_KEEP: PWM output keeps the current polarity when counting compare match. + * @arg TMR2_PWM_CMP_REVERSE: PWM output reverses the current polarity when counting compare match. + * @retval None + */ +void TMR2_PWM_SetCmpPolarity(M4_TMR2_TypeDef *TMR2x, uint8_t u8Tmr2Ch, uint32_t u32Polarity) +{ + DDL_ASSERT(IS_TMR2_UNIT(TMR2x)); + DDL_ASSERT(IS_TMR2_CH(u8Tmr2Ch)); + DDL_ASSERT(IS_TMR2_PWM_CMP_POLARITY(u32Polarity)); + + u8Tmr2Ch *= TMR2_PCONR_OFFSET; + MODIFY_REG32(TMR2x->PCONR, \ + (TMR2_PWM_CMP_POLARITY_MSK << u8Tmr2Ch), \ + (u32Polarity << u8Tmr2Ch)); +} + +/** + * @} + */ + +#endif /* DDL_TMR2_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr4.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr4.c new file mode 100644 index 0000000000000000000000000000000000000000..ca65d042cf74e5f9c8a8a21020ce9c4af91f6696 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr4.c @@ -0,0 +1,3256 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmr4.c + * @brief This file provides firmware functions to manage the TMR4(Timer4) + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-15 Hongjh Modify error parameter assert condition for + the function TMR4_PWM_SetPclkDiv. + 2020-07-25 Hongjh Modify TMR4_OCO_SetLowChCompareMode function + comment:from TMR4_OCO_UH/VH/WH to TMR4_OCO_UL/VL/WL + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_tmr4.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_TMR4 TMR4 + * @brief TMR4 Driver Library + * @{ + */ + +#if (DDL_TMR4_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR4_Local_Macros TMR4 Local Macros + * @{ + */ + +/** + * @defgroup TMR4_Check_Parameters_Validity TMR4 Check Parameters Validity + * @{ + */ + +#define IS_VALID_TMR4_INSTANCE(x) \ +( (M4_TMR4_1 == (x)) || \ + (M4_TMR4_2 == (x)) || \ + (M4_TMR4_3 == (x))) + +#define IS_VALID_TMR4_CNT_PCLK_DIV(x) \ +( (TMR4_CNT_PCLK_DIV1 == (x)) || \ + (TMR4_CNT_PCLK_DIV2 == (x)) || \ + (TMR4_CNT_PCLK_DIV4 == (x)) || \ + (TMR4_CNT_PCLK_DIV8 == (x)) || \ + (TMR4_CNT_PCLK_DIV16 == (x)) || \ + (TMR4_CNT_PCLK_DIV32 == (x)) || \ + (TMR4_CNT_PCLK_DIV64 == (x)) || \ + (TMR4_CNT_PCLK_DIV128 == (x)) || \ + (TMR4_CNT_PCLK_DIV256 == (x)) || \ + (TMR4_CNT_PCLK_DIV512 == (x)) || \ + (TMR4_CNT_PCLK_DIV1024 == (x))) + +#define IS_VALID_TMR4_CNT_MODE(x) \ +( (TMR4_CNT_MODE_SAWTOOTH_WAVE == (x)) || \ + (TMR4_CNT_MODE_TRIANGLE_WAVE == (x))) + +#define IS_VALID_TMR4_CNT_BUF_STATE(x) \ +( (TMR4_CNT_BUFFER_ENABLE == (x)) || \ + (TMR4_CNT_BUFFER_DISABLE == (x))) + +#define IS_VALID_TMR4_CNT_CLK_SRC(x) \ +( (TMR4_CNT_PCLK == (x)) || \ + (TMR4_CNT_EXTCLK == (x))) + +#define IS_VALID_TMR4_CNT_INT_MASKTIMES(x) \ +( (TMR4_CNT_INT_MASK_0 == (x)) || \ + (TMR4_CNT_INT_MASK_1 == (x)) || \ + (TMR4_CNT_INT_MASK_2 == (x)) || \ + (TMR4_CNT_INT_MASK_3 == (x)) || \ + (TMR4_CNT_INT_MASK_4 == (x)) || \ + (TMR4_CNT_INT_MASK_5 == (x)) || \ + (TMR4_CNT_INT_MASK_6 == (x)) || \ + (TMR4_CNT_INT_MASK_7 == (x)) || \ + (TMR4_CNT_INT_MASK_8 == (x)) || \ + (TMR4_CNT_INT_MASK_9 == (x)) || \ + (TMR4_CNT_INT_MASK_10 == (x)) || \ + (TMR4_CNT_INT_MASK_11 == (x)) || \ + (TMR4_CNT_INT_MASK_12 == (x)) || \ + (TMR4_CNT_INT_MASK_13 == (x)) || \ + (TMR4_CNT_INT_MASK_14 == (x)) || \ + (TMR4_CNT_INT_MASK_15 == (x))) + +#define IS_VALID_TMR4_CNT_INT(x) \ +( (0UL != (x)) && \ + (TMR4_CNT_INT_MASK == ((x) | TMR4_CNT_INT_MASK))) + +#define IS_VALID_TMR4_CNT_FLAG(x) \ +( (0UL != (x)) && \ + (TMR4_CNT_FLAG_MASK == ((x) | TMR4_CNT_FLAG_MASK))) + +#define IS_VALID_TMR4_OCO_CH(x) \ +( (TMR4_OCO_UH == (x)) || \ + (TMR4_OCO_UL == (x)) || \ + (TMR4_OCO_VH == (x)) || \ + (TMR4_OCO_VL == (x)) || \ + (TMR4_OCO_WH == (x)) || \ + (TMR4_OCO_WL == (x))) + +#define IS_VALID_TMR4_OCO_HIGH_CH(x) \ +( (TMR4_OCO_UH == (x)) || \ + (TMR4_OCO_VH == (x)) || \ + (TMR4_OCO_WH == (x))) + +#define IS_VALID_TMR4_OCO_LOW_CH(x) \ +( (TMR4_OCO_UL == (x)) || \ + (TMR4_OCO_VL == (x)) || \ + (TMR4_OCO_WL == (x))) + +#define IS_VALID_TMR4_OCO_STATE(x) \ +( (TMR4_OCO_DISABLE == (x)) || \ + (TMR4_OCO_ENABLE == (x))) + +#define IS_VALID_TMR4_OCO_EXTEND_MATCH(x) \ +( (TMR4_OCO_EXTEND_MATCH_DISABLE == (x)) || \ + (TMR4_OCO_EXTEND_MATCH_ENABLE == (x))) + +#define IS_VALID_TMR4_OCO_OCCR_LINK_TRANSFER(x) \ +( (TMR4_OCO_OCCR_LINK_TRANSFER_DISABLE == (x)) || \ + (TMR4_OCO_OCCR_LINK_TRANSFER_ENABLE == (x))) + +#define IS_VALID_TMR4_OCO_OCCR_BUF_MODE(x) \ +( (TMR4_OCO_OCCR_BUF_DISABLE == (x)) || \ + (TMR4_OCO_OCCR_BUF_CNT_ZERO == (x)) || \ + (TMR4_OCO_OCCR_BUF_CNT_PEAK == (x)) || \ + (TMR4_OCO_OCCR_BUF_CNT_ZERO_OR_PEAK == (x))) + +#define IS_VALID_TMR4_OCO_OCMR_LINK_TRANSFER(x) \ +( (TMR4_OCO_OCMR_LINK_TRANSFER_DISABLE == (x)) || \ + (TMR4_OCO_OCMR_LINK_TRANSFER_ENABLE == (x))) + +#define IS_VALID_TMR4_OCO_OCMR_BUF_MODE(x) \ +( (TMR4_OCO_OCMR_BUF_DISABLE == (x)) || \ + (TMR4_OCO_OCMR_BUF_CNT_ZERO == (x)) || \ + (TMR4_OCO_OCMR_BUF_CNT_PEAK == (x)) || \ + (TMR4_OCO_OCMR_BUF_CNT_ZERO_OR_PEAK == (x))) + +#define IS_VALID_TMR4_OCO_PORT_INVALID_OP(x) \ +( (TMR4_OCO_INVAILD_OP_LOW == (x)) || \ + (TMR4_OCO_INVAILD_OP_HIGH == (x))) + +#define IS_VALID_TMR4_OCO_OCF_STATE(x) \ +( (TMR4_OCO_OCF_HOLD == (x)) || \ + (TMR4_OCO_OCF_SET == (x))) + +#define IS_VALID_TMR4_OCO_OUTPUT_POLARITY(x) \ +( (TMR4_OCO_OP_HOLD == (x)) || \ + (TMR4_OCO_OP_HIGH == (x)) || \ + (TMR4_OCO_OP_LOW == (x)) || \ + (TMR4_OCO_OP_INVERT == (x))) + +#define IS_VALID_TMR4_PWM_CH(x) \ +( (TMR4_PWM_U == (x)) || \ + (TMR4_PWM_V == (x)) || \ + (TMR4_PWM_W == (x))) + +#define IS_VALID_TMR4_PWM_PORT(x) \ +( (TMR4_PWM_PORT_OUH == (x)) || \ + (TMR4_PWM_PORT_OUL == (x)) || \ + (TMR4_PWM_PORT_OVH == (x)) || \ + (TMR4_PWM_PORT_OVL == (x)) || \ + (TMR4_PWM_PORT_OWH == (x)) || \ + (TMR4_PWM_PORT_OWL == (x))) + +#define IS_VALID_TMR4_PWM_MODE(x) \ +( (TMR4_PWM_THROUGH_MODE == (x)) || \ + (TMR4_PWM_DEAD_TIMER_MODE == (x)) || \ + (TMR4_PWM_DEAD_TIMER_FILTER_MODE == (x))) + +#define IS_VALID_TMR4_PWM_TRANSFORM_OCO_POLARITY(x) \ +( (TMR4_PWM_OP_OXH_HOLD_OXL_HOLD == (x)) || \ + (TMR4_PWM_OP_OXH_INVERT_OXL_HOLD == (x)) || \ + (TMR4_PWM_OP_OXH_HOLD_OXL_INVERT == (x)) || \ + (TMR4_PWM_OP_OXH_INVERT_OXL_INVERT == (x))) + +#define IS_VALID_TMR4_PWM_PCLK_DIV(x) \ +( (TMR4_PWM_PCLK_DIV1 == (x)) || \ + (TMR4_PWM_PCLK_DIV2 == (x)) || \ + (TMR4_PWM_PCLK_DIV4 == (x)) || \ + (TMR4_PWM_PCLK_DIV8 == (x)) || \ + (TMR4_PWM_PCLK_DIV16 == (x)) || \ + (TMR4_PWM_PCLK_DIV32 == (x)) || \ + (TMR4_PWM_PCLK_DIV64 == (x)) || \ + (TMR4_PWM_PCLK_DIV128 == (x))) + +#define IS_VALID_TMR4_PWM_EMB_PORT_OUTPUT_STATE(x) \ +( (TMR4_PWM_EMB_PORT_OUTPUT_NORMAL == (x)) || \ + (TMR4_PWM_EMB_PORT_OUTPUT_HIZ == (x)) || \ + (TMR4_PWM_EMB_PORT_OUTPUT_LOW == (x)) || \ + (TMR4_PWM_EMB_PORT_OUTPUT_HIGH == (x))) + +#define IS_VALID_TMR4_PWM_PORT_ENBIT_EFFECT(x) \ +( (TMR4_PWM_PORT_ENBIT_EFFECT_IMMEDIATE == (x)) || \ + (TMR4_PWM_PORT_ENBIT_EFFECT_CNTUVF == (x)) || \ + (TMR4_PWM_PORT_ENBIT_EFFECT_CNTOVF == (x))) + +#define IS_VALID_TMR4_PWM_PORT_MODE(x) \ +( (TMR4_PWM_PORT_OUTPUT_OSxy == (x)) || \ + (TMR4_PWM_PORT_OUTPUT_NORMAL == (x))) + +#define IS_VALID_TMR4_SEVT_CH(x) \ +( (TMR4_SEVT_UH == (x)) || \ + (TMR4_SEVT_UL == (x)) || \ + (TMR4_SEVT_VH == (x)) || \ + (TMR4_SEVT_VL == (x)) || \ + (TMR4_SEVT_WH == (x)) || \ + (TMR4_SEVT_WL == (x))) + +#define IS_VALID_TMR4_SEVT_LINK_TRANSFER(x) \ +( (TMR4_SEVT_LINK_TRANSFER_DISABLE == (x)) || \ + (TMR4_SEVT_LINK_TRANSFER_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_DOWN_SEL(x) \ +( (TMR4_SEVT_DOWN_DISABLE == (x)) || \ + (TMR4_SEVT_DOWN_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_UP_SEL(x) \ +( (TMR4_SEVT_UP_DISABLE == (x)) || \ + (TMR4_SEVT_UP_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_PEAK_SEL(x) \ +( (TMR4_SEVT_PEAK_DISABLE == (x)) || \ + (TMR4_SEVT_PEAK_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_ZERO_SEL(x) \ +( (TMR4_SEVT_ZERO_DISABLE == (x)) || \ + (TMR4_SEVT_ZERO_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_ZERO_MATCH_MASK_SEL(x) \ +( (TMR4_SEVT_ZERO_MATCH_MASK_DISABLE == (x)) || \ + (TMR4_SEVT_ZERO_MATCH_MASK_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_PEAK_MATCH_MASK_SEL(x) \ +( (TMR4_SEVT_PEAK_MATCH_MASK_DISABLE == (x)) || \ + (TMR4_SEVT_PEAK_MATCH_MASK_ENABLE == (x))) + +#define IS_VALID_TMR4_SEVT_OBJECT(x) \ +( (TMR4_SEVT_DELAY_OCCRXH == (x)) || \ + (TMR4_SEVT_DELAY_OCCRXL == (x))) + +#define IS_VALID_TMR4_SEVT_MODE(x) \ +( (TMR4_SEVT_MODE_DELAY_TRIGGER == (x)) || \ + (TMR4_SEVT_MODE_COMPARE_TRIGGER == (x))) + +#define IS_VALID_TMR4_SEVT_MASK(x) \ +( (TMR4_SEVT_MASK_0 == (x)) || \ + (TMR4_SEVT_MASK_1 == (x)) || \ + (TMR4_SEVT_MASK_2 == (x)) || \ + (TMR4_SEVT_MASK_3 == (x)) || \ + (TMR4_SEVT_MASK_4 == (x)) || \ + (TMR4_SEVT_MASK_5 == (x)) || \ + (TMR4_SEVT_MASK_6 == (x)) || \ + (TMR4_SEVT_MASK_7 == (x)) || \ + (TMR4_SEVT_MASK_8 == (x)) || \ + (TMR4_SEVT_MASK_9 == (x)) || \ + (TMR4_SEVT_MASK_10 == (x)) || \ + (TMR4_SEVT_MASK_11 == (x)) || \ + (TMR4_SEVT_MASK_12 == (x)) || \ + (TMR4_SEVT_MASK_13 == (x)) || \ + (TMR4_SEVT_MASK_14 == (x)) || \ + (TMR4_SEVT_MASK_15 == (x))) + +#define IS_VALID_TMR4_SEVT_OUTPUT_EVENT(x) \ +( (TMR4_SEVT_OUTPUT_EVENT0 == (x)) || \ + (TMR4_SEVT_OUTPUT_EVENT1 == (x)) || \ + (TMR4_SEVT_OUTPUT_EVENT2 == (x)) || \ + (TMR4_SEVT_OUTPUT_EVENT3 == (x)) || \ + (TMR4_SEVT_OUTPUT_EVENT4 == (x)) || \ + (TMR4_SEVT_OUTPUT_EVENT5 == (x))) + +#define IS_VALID_TMR4_SEVT_BUF_MODE(x) \ +( (TMR4_SEVT_BUF_DISABLE == (x)) || \ + (TMR4_SEVT_BUF_CNT_ZERO == (x)) || \ + (TMR4_SEVT_BUF_CNT_PEAK == (x)) || \ + (TMR4_SEVT_BUF_CNT_ZERO_OR_PEAK == (x))) + +#define IS_VALID_TMR4_SEVT_PORT_OUTPUT_SIGNAL(x) \ +( (TMR4_SEVT_PORT_OUTPUT_NONE == (x)) || \ + (TMR4_SEVT_PORT_OUTPUT_EVENT0_SIGNAL == (x)) || \ + (TMR4_SEVT_PORT_OUTPUT_EVENT1_SIGNAL == (x)) || \ + (TMR4_SEVT_PORT_OUTPUT_EVENT2_SIGNAL == (x)) || \ + (TMR4_SEVT_PORT_OUTPUT_EVENT3_SIGNAL == (x)) || \ + (TMR4_SEVT_PORT_OUTPUT_EVENT4_SIGNAL == (x)) || \ + (TMR4_SEVT_PORT_OUTPUT_EVENT5_SIGNAL == (x))) +/** + * @} + */ + +/** + * @defgroup TMR4_Register_Address Get TMR4 register address + * @{ + */ +#define REG_ADDR(__REG__) ((uint32_t)(&(__REG__))) +/** + * @} + */ + +/** + * @defgroup TMR4_Register_Shift_Bits Get register value shift bit + * @{ + */ +#define SHIFT_1BIT(__CH__) ((uint16_t)((__CH__) % 2UL)) +#define SHIFT_2BIT(__CH__) ((uint16_t)(((__CH__) % 2UL) << 1UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_OCO_Register TMR4 OCO Register + * @brief Get the specified OCO register address of the specified TMR4 unit + * @note __CH__ value is TMR4_OCO_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCCRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->OCCRUH) + (((uint32_t)(__CH__)) << 2UL))) +#define TMR4_OCMRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->OCMRHUH) + (((uint32_t)(__CH__)) << 2UL))) +#define TMR4_OCERx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->OCERU) + ((((uint32_t)(__CH__)) & 0x06UL) << 1UL))) +#define TMR4_OCSRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->OCSRU) + ((((uint32_t)(__CH__)) & 0x06UL) << 1UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit_Mask TMR4_OCSR Bit Mask + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OCO channel + * @note __CH__ value is TMR4_OCO_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCSR_OCEx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCSR_OCEH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_OCPx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCSR_OCPH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_OCIEx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCSR_OCIEH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_OCFx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCSR_OCFH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_MASK(__CH__) \ +( (uint16_t)((uint16_t)(TMR4_OCSR_OCEH | TMR4_OCSR_OCPH | TMR4_OCSR_OCIEH | TMR4_OCSR_OCFH)) << SHIFT_1BIT(__CH__)) +/** + * @} + */ + +/** + * @defgroup TMR4_OCSR_Bit TMR4_OCSR Bit + * @brief Get the specified TMR4_OCSR register bis value of the specified TMR4 OCO channel + * @note __CH__ value is TMR4_OCO_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCSR_OCEx(__CH__,__OCEx__) ((uint16_t)(((uint16_t)__OCEx__) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_OCPx(__CH__,__OCPx__) ((uint16_t)(((uint16_t)__OCPx__) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_OCIEx(__CH__,__OCIEx__) ((uint16_t)(((uint16_t)__OCIEx__) << SHIFT_1BIT(__CH__))) +#define TMR4_OCSR_OCFx(__CH__,__OCFx__) ((uint16_t)(((uint16_t)__OCFx__) << SHIFT_1BIT(__CH__))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit_Mask TMR4_OCER Bit Mask + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OCO channel + * @note __CH__ value is TMR4_OCO_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCER_CxBUFEN_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCER_CHBUFEN) << SHIFT_2BIT(__CH__))) +#define TMR4_OCER_MxBUFEN_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCER_MHBUFEN) << SHIFT_2BIT(__CH__))) +#define TMR4_OCER_LMCx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCER_LMCH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCER_LMMx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCER_LMMH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCER_MCECx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_OCER_MCECH) << SHIFT_1BIT(__CH__))) +#define TMR4_OCER_MASK(__CH__) \ +( (uint16_t)(((uint16_t)(TMR4_OCER_CHBUFEN | TMR4_OCER_MHBUFEN)) << SHIFT_2BIT(__CH__)) | \ + (uint16_t)(((uint16_t)(TMR4_OCER_LMCH | TMR4_OCER_LMMH | TMR4_OCER_MCECH)) << SHIFT_2BIT(__CH__))) +/** + * @} + */ + +/** + * @defgroup TMR4_OCER_Bit TMR4_OCER Bit + * @brief Get the specified TMR4_OCER register bis value of the specified TMR4 OCO channel + * @note __CH__ value is TMR4_OCO_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_OCER_CxBUFEN(__CH__,__CxBUFEN__) ((uint16_t)((__CxBUFEN__) << SHIFT_2BIT(__CH__))) +#define TMR4_OCER_MxBUFEN(__CH__,__MxBUFEN__) ((uint16_t)((__MxBUFEN__) << SHIFT_2BIT(__CH__))) +#define TMR4_OCER_LMCx(__CH__,__LMCx__) ((uint16_t)((__LMCx__) << SHIFT_1BIT(__CH__))) +#define TMR4_OCER_LMMx(__CH__,__LMMx__) ((uint16_t)((__LMMx__) << SHIFT_1BIT(__CH__))) +#define TMR4_OCER_MCECx(__CH__,__MCECx__) ((uint16_t)((__MCECx__) << SHIFT_1BIT(__CH__))) +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Register TMR4 PWM Register + * @brief Get the specified PWM register address of the specified TMR4 unit + * @note __CH__ value is TMR4_PWM_x (x=U/V/W) + * @{ + */ +#define TMR4_RCSRx(__TMR4x__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->RCSR))) +#define TMR4_POCRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->POCRU) + (((uint32_t)(__CH__)) << 2UL))) +#define TMR4_PDARx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->PDARU) + (((uint32_t)(__CH__)) << 3UL))) +#define TMR4_PDBRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->PDBRU) + (((uint32_t)(__CH__)) << 3UL))) +#define TMR4_PFSRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->PFSRU) + (((uint32_t)(__CH__)) << 3UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_RCSR_Bit_Mask TMR4_RCSR Bit Mask + * @brief Get the specified TMR4_RCSR register bis value of the specified TMR4 PWM channel + * @note __CH__ value is TMR4_PWM_x (x=U/V/W) + * @{ + */ +#define TMR4_RCSR_RTIDx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_RCSR_RTIDU) << (__CH__))) +#define TMR4_RCSR_RTIFx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_RCSR_RTIFU) << ((__CH__) << 2UL))) +#define TMR4_RCSR_RTICx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_RCSR_RTICU) << ((__CH__) << 2UL))) +#define TMR4_RCSR_RTEx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_RCSR_RTEU) << ((__CH__) << 2UL))) +#define TMR4_RCSR_RTSx_MASK(__CH__) ((uint16_t)(((uint16_t)TMR4_RCSR_RTSU) << ((__CH__) << 2UL))) +/** + * @} + */ + +/** + * @defgroup TMR4_PSCR_Bit_Mask TMR4_PSCR Bit Mask + * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel + * @note __PORT__ value is TMR4_PWM_PORT_Oxy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_PSCR_OExy_MASK(__PORT__) (TMR4_PSCR_OEUH << (__PORT__)) +#define TMR4_PSCR_OSxy_MASK(__PORT__) (TMR4_PSCR_OSUH << ((__PORT__) * 2UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_PSCR_Bit TMR4_PSCR Bit + * @brief Get the specified TMR4_PSCR register bis value of the specified TMR4 PWM port channel + * @note __PORT__ value is TMR4_PWM_PORT_Oxy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_PSCR_OExy(__PORT__, __OExy__) ((__OExy__) << (__PORT__)) +#define TMR4_PSCR_OSxy(__PORT__, __OSxy__) ((__OSxy__) << ((__PORT__) * 2UL)) +/** + * @} + */ + +/** + * @defgroup TMR4_SEVT_Register TMR4 SEVT Register + * @brief Get the specified SEVT register address of the specified TMR4 unit + * @note __CH__ value is TMR4_SEVT_xy (x=U/V/W, y=H/L) + * @{ + */ +#define TMR4_SCCRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->SCCRUH) + ((__CH__) << 2UL))) +#define TMR4_SCSRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->SCSRUH) + ((__CH__) << 2UL))) +#define TMR4_SCMRx(__TMR4x__, __CH__) ((__IO uint16_t *)(REG_ADDR((__TMR4x__)->SCMRUH) + ((__CH__) << 2UL))) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR4_Global_Functions TMR4 Global Functions + * @{ + */ + +/** + * @defgroup TMR4_CNT_Global_Functions TMR4 Counter Global Functions + * @{ + */ + +/** + * @brief Initialize TMR4 counter. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] pstcInit Pointer to a @ref stc_tmr4_cnt_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t TMR4_CNT_Init(M4_TMR4_TypeDef *TMR4x, + const stc_tmr4_cnt_init_t *pstcInit) +{ + uint16_t u16Val; + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_BUF_STATE(pstcInit->u16BufState)); + DDL_ASSERT(IS_VALID_TMR4_CNT_MODE(pstcInit->u16CntMode)); + DDL_ASSERT(IS_VALID_TMR4_CNT_PCLK_DIV(pstcInit->u16PclkDiv)); + DDL_ASSERT(IS_VALID_TMR4_CNT_CLK_SRC(pstcInit->u16ClkSrc)); + DDL_ASSERT(IS_VALID_TMR4_CNT_INT_MASKTIMES(pstcInit->u16ZeroIntMask)); + DDL_ASSERT(IS_VALID_TMR4_CNT_INT_MASKTIMES(pstcInit->u16PeakIntMask)); + + /* Set default value */ + WRITE_REG16(TMR4x->CCSR, 0x0050U); + WRITE_REG16(TMR4x->CVPR, 0x0000U); + + /* Set count clock div && cnt mode && buffer enable bit && + external clock enable bit && interrupt enable bit */ + u16Val = (pstcInit->u16PclkDiv | \ + pstcInit->u16ClkSrc | \ + pstcInit->u16CntMode | \ + TMR4_CCSR_STOP | \ + pstcInit->u16BufState); + WRITE_REG16(TMR4x->CCSR, u16Val); + + /* set interrupt mask times */ + u16Val = (((uint16_t)(pstcInit->u16ZeroIntMask << TMR4_CVPR_ZIM_POS)) | \ + ((uint16_t)(pstcInit->u16PeakIntMask << TMR4_CVPR_PIM_POS))); + WRITE_REG16(TMR4x->CVPR, u16Val); + + /* Set TMR4 cycle */ + WRITE_REG16(TMR4x->CPSR, pstcInit->u16CycleVal); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr4_cnt_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr4_cnt_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t TMR4_CNT_StructInit(stc_tmr4_cnt_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u16CycleVal = 0xFFFFU; + pstcInit->u16CntMode = TMR4_CNT_MODE_SAWTOOTH_WAVE; + pstcInit->u16ClkSrc = TMR4_CNT_PCLK; + pstcInit->u16PclkDiv = TMR4_CNT_PCLK_DIV1; + pstcInit->u16ZeroIntMask = TMR4_CNT_INT_MASK_0; + pstcInit->u16PeakIntMask = TMR4_CNT_INT_MASK_0; + pstcInit->u16BufState = TMR4_CNT_BUFFER_DISABLE; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize TMR4 counter function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval None + */ +void TMR4_CNT_DeInit(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + /* Configures the registers to reset value. */ + WRITE_REG16(TMR4x->CCSR, 0x0050U); + WRITE_REG16(TMR4x->CPSR, 0xFFFFU); + WRITE_REG16(TMR4x->CVPR, 0x0000U); +} + +/** + * @brief Set TMR4 counter clock source + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16ClkSrc TMR4 CNT clock source + * This parameter can be one of the following values: + * @arg TMR4_CNT_PCLK: Uses the internal clock (PCLK) as counter's count clock + * @arg TMR4_CNT_EXTCLK: Uses an external input clock (EXCK) as counter's count clock + * @retval None + * @note The PCLK division function is valid when clock source is PCLK + */ +void TMR4_CNT_SetClock(M4_TMR4_TypeDef *TMR4x, uint16_t u16ClkSrc) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_CLK_SRC(u16ClkSrc)); + + /* Set external clock enable bit */ + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_ECKEN, u16ClkSrc); +} + +/** + * @brief Get TMR4 counter clock source + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval Returned value can be one of the following values: + * @arg TMR4_CNT_PCLK: Uses the internal clock (PCLK) as counter's count clock + * @arg TMR4_CNT_EXTCLK: Uses an external input clock (EXCK) as counter's count clock + */ +uint16_t TMR4_CNT_GetClock(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + /* Get external clock enable bit */ + return READ_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_ECKEN); +} + +/** + * @brief Set TMR4 counter clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16Div TMR4 clock division + * This parameter can be one of the following values: + * @arg TMR4_CNT_PCLK_DIV1: PCLK + * @arg TMR4_CNT_PCLK_DIV2: PCLK/2 + * @arg TMR4_CNT_PCLK_DIV4: PCLK/4 + * @arg TMR4_CNT_PCLK_DIV8: PCLK/8 + * @arg TMR4_CNT_PCLK_DIV16: PCLK/16 + * @arg TMR4_CNT_PCLK_DIV32: PCLK/32 + * @arg TMR4_CNT_PCLK_DIV64: PCLK/64 + * @arg TMR4_CNT_PCLK_DIV128: PCLK/128 + * @arg TMR4_CNT_PCLK_DIV256: PCLK/256 + * @arg TMR4_CNT_PCLK_DIV512: PCLK/512 + * @arg TMR4_CNT_PCLK_DIV1024: PCLK/1024 + * @retval None + * @note The PCLK division function is valid when clock source is PCLK + */ +void TMR4_CNT_SetPclkDiv(M4_TMR4_TypeDef *TMR4x, uint16_t u16Div) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_PCLK_DIV(u16Div)); + + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_CKDIV, u16Div); +} + +/** + * @brief Get TMR4 counter clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval Returned value can be one of the following values: + * @arg TMR4_CNT_PCLK_DIV1: PCLK + * @arg TMR4_CNT_PCLK_DIV2: PCLK/2 + * @arg TMR4_CNT_PCLK_DIV4: PCLK/4 + * @arg TMR4_CNT_PCLK_DIV8: PCLK/8 + * @arg TMR4_CNT_PCLK_DIV16: PCLK/16 + * @arg TMR4_CNT_PCLK_DIV32: PCLK/32 + * @arg TMR4_CNT_PCLK_DIV64: PCLK/64 + * @arg TMR4_CNT_PCLK_DIV128: PCLK/128 + * @arg TMR4_CNT_PCLK_DIV256: PCLK/256 + * @arg TMR4_CNT_PCLK_DIV512: PCLK/512 + * @arg TMR4_CNT_PCLK_DIV1024: PCLK/1024 + * @note The PCLK division function is valid when clock source is PCLK + */ +uint16_t TMR4_CNT_GetPclkDiv(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + return READ_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CKDIV); +} + +/** + * @brief Set TMR4 counter mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16Mode TMR4 counter mode + * This parameter can be one of the following values: + * @arg TMR4_CNT_MODE_SAWTOOTH_WAVE: TMR4 count mode:sawtooth wave + * @arg TMR4_CNT_MODE_TRIANGLE_WAVE: TMR4 count mode:triangular wave + * @retval None + */ +void TMR4_CNT_SetMode(M4_TMR4_TypeDef *TMR4x, uint16_t u16Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_MODE(u16Mode)); + + /* Set external clock enable bit */ + MODIFY_REG16(TMR4x->CCSR, TMR4_CCSR_MODE, u16Mode); +} + +/** + * @brief Get TMR4 counter mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval Returned value can be one of the following values: + * @arg TMR4_CNT_MODE_SAWTOOTH_WAVE: TMR4 count mode:sawtooth wave + * @arg TMR4_CNT_MODE_TRIANGLE_WAVE: TMR4 count mode:triangular wave + */ +uint16_t TMR4_CNT_GetMode(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + /* Get external clock enable bit */ + return READ_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_MODE); +} + +/** + * @brief Get TMR4 counter flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16Flag TMR4 flag + * This parameter can be any composed value of the following values: + * @arg TMR4_CNT_FLAG_PEAK: Overflow interrupt + * @arg TMR4_CNT_FLAG_ZERO: Underflow interrupt + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t TMR4_CNT_GetStatus(const M4_TMR4_TypeDef *TMR4x, + uint16_t u16Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_FLAG(u16Flag)); + + return (READ_REG16_BIT(TMR4x->CCSR, u16Flag) != 0U) ? Set : Reset; +} + +/** + * @brief Clear TMR4 counter flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16Flag TMR4 counter flag + * This parameter can be any composed value of the following values: + * @arg TMR4_CNT_FLAG_PEAK: Overflow interrupt + * @arg TMR4_CNT_FLAG_ZERO: Underflow interrupt + * @retval None + */ +void TMR4_CNT_ClearStatus(M4_TMR4_TypeDef *TMR4x, uint16_t u16Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_FLAG(u16Flag)); + + CLEAR_REG16_BIT(TMR4x->CCSR, u16Flag); +} + +/** + * @brief Enable or disable specified TMR4 counter interrupt + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16IntSource TMR4 interrupt source + * This parameter can be any composed value of the following values: + * @arg TMR4_CNT_INT_PEAK: Overflow interrupt + * @arg TMR4_CNT_INT_ZERO: Underflow interrupt + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR4_CNT_IntCmd(M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_VALID_TMR4_CNT_INT(u16IntSource)); + + if (Enable == enNewState) + { + SET_REG16_BIT(TMR4x->CCSR, u16IntSource); + } + else + { + CLEAR_REG16_BIT(TMR4x->CCSR, u16IntSource); + } +} + +/** + * @brief Start TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval None + */ +void TMR4_CNT_Start(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + CLEAR_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Stop TMR4 counter + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval None + */ +void TMR4_CNT_Stop(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_STOP); +} + +/** + * @brief Set TMR4 counter cycle value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16CycleVal The TMR4 counter cycle value + * @arg number of 16bit + * @retval None + */ +void TMR4_CNT_SetCycleVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16CycleVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + WRITE_REG16(TMR4x->CPSR, u16CycleVal); +} + +/** + * @brief Get TMR4 counter cycle value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval The cycle value of the TMR4 counter + */ +uint16_t TMR4_CNT_GetCycleVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + return READ_REG16(TMR4x->CPSR); +} + +/** + * @brief Clear TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval None + */ +void TMR4_CNT_ClearCountVal(M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + SET_REG16_BIT(TMR4x->CCSR, TMR4_CCSR_CLEAR); +} + +/** + * @brief Set TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16CountVal The TMR4 counter count value + * @arg number of 16bit + * @retval None + */ +void TMR4_CNT_SetCountVal(M4_TMR4_TypeDef *TMR4x, uint16_t u16CountVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + WRITE_REG16(TMR4x->CNTR, u16CountVal); +} + +/** + * @brief Get TMR4 counter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval The count value of the TMR4 counter + */ +uint16_t TMR4_CNT_GetCountVal(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + return READ_REG16(TMR4x->CNTR); +} + +/** + * @brief Set TMR4 counter interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16IntSource TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_CNT_INT_PEAK: Overflow interrupt + * @arg TMR4_CNT_INT_ZERO: Underflow interrupt + * @param [in] u16MaskTimes TMR4 counter interrupt mask times + * This parameter can be one of the following values: + * @arg TMR4_CNT_INT_MASK_0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * @arg TMR4_CNT_INT_MASK_1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skiping 1 count) + * @arg TMR4_CNT_INT_MASK_2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skiping 2 count) + * @arg TMR4_CNT_INT_MASK_3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skiping 3 count) + * @arg TMR4_CNT_INT_MASK_4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skiping 4 count) + * @arg TMR4_CNT_INT_MASK_5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skiping 5 count) + * @arg TMR4_CNT_INT_MASK_6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skiping 6 count) + * @arg TMR4_CNT_INT_MASK_7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skiping 7 count) + * @arg TMR4_CNT_INT_MASK_8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skiping 8 count) + * @arg TMR4_CNT_INT_MASK_9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skiping 9 count) + * @arg TMR4_CNT_INT_MASK_10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skiping 10 count) + * @arg TMR4_CNT_INT_MASK_11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skiping 11 count) + * @arg TMR4_CNT_INT_MASK_12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skiping 12 count) + * @arg TMR4_CNT_INT_MASK_13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skiping 13 count) + * @arg TMR4_CNT_INT_MASK_14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skiping 14 count) + * @arg TMR4_CNT_INT_MASK_15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skiping 15 count) + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: u16IntSource value is invalid + */ +en_result_t TMR4_CNT_SetIntMaskTimes(M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + uint16_t u16MaskTimes) +{ + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_CNT_INT_MASKTIMES(u16MaskTimes)); + + switch (u16IntSource) + { + case TMR4_CNT_INT_ZERO: + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_ZIM, (uint16_t)(u16MaskTimes << TMR4_CVPR_ZIM_POS)); + break; + case TMR4_CNT_INT_PEAK: + MODIFY_REG16(TMR4x->CVPR, TMR4_CVPR_PIM, (uint16_t)(u16MaskTimes << TMR4_CVPR_PIM_POS)); + break; + default: + DDL_ASSERT(NULL); + enRet = ErrorInvalidParameter; + break; + } + + return enRet; +} + +/** + * @brief Get TMR4 CNT interrupt mask times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16IntSource TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_CNT_INT_PEAK: Overflow interrupt + * @arg TMR4_CNT_INT_ZERO: Underflow interrupt + * @param [out] pu16MaskTimes The pointer for mask times + * This parameter can be one of the following values: + * @arg TMR4_CNT_INT_MASK_0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * @arg TMR4_CNT_INT_MASK_1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skiping 1 count) + * @arg TMR4_CNT_INT_MASK_2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skiping 2 count) + * @arg TMR4_CNT_INT_MASK_3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skiping 3 count) + * @arg TMR4_CNT_INT_MASK_4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skiping 4 count) + * @arg TMR4_CNT_INT_MASK_5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skiping 5 count) + * @arg TMR4_CNT_INT_MASK_6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skiping 6 count) + * @arg TMR4_CNT_INT_MASK_7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skiping 7 count) + * @arg TMR4_CNT_INT_MASK_8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skiping 8 count) + * @arg TMR4_CNT_INT_MASK_9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skiping 9 count) + * @arg TMR4_CNT_INT_MASK_10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skiping 10 count) + * @arg TMR4_CNT_INT_MASK_11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skiping 11 count) + * @arg TMR4_CNT_INT_MASK_12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skiping 12 count) + * @arg TMR4_CNT_INT_MASK_13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skiping 13 count) + * @arg TMR4_CNT_INT_MASK_14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skiping 14 count) + * @arg TMR4_CNT_INT_MASK_15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skiping 15 count) + @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: pu16MaskTimes = NULL or u16IntSource value is invalid + */ +en_result_t TMR4_CNT_GetIntMaskTimes(const M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + uint16_t *pu16MaskTimes) +{ + en_result_t enRet = Ok; + + if (NULL == pu16MaskTimes) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + switch (u16IntSource) + { + case TMR4_CNT_INT_ZERO: + *pu16MaskTimes = (uint16_t)(READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIM) >> TMR4_CVPR_ZIM_POS); + break; + case TMR4_CNT_INT_PEAK: + *pu16MaskTimes = (uint16_t)(READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIM) >> TMR4_CVPR_PIM_POS); + break; + default: + DDL_ASSERT(NULL); + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + * @brief Get TMR4 CNT interrupt mask current times + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16IntSource TMR4 interrupt source + * This parameter can be one of the following values: + * @arg TMR4_CNT_INT_PEAK: Overflow interrupt + * @arg TMR4_CNT_INT_ZERO: Underflow interrupt + * @param [out] pu16MaskTimes The pointer for mask times + * This parameter can be one of the following values: + * @arg TMR4_CNT_INT_MASK_0: Counter interrupt flag is always set(not masked) for every counter count at "0x0000" or peak + * @arg TMR4_CNT_INT_MASK_1: Counter interrupt flag is set once for 2 every counter counts at "0x0000" or peak (skiping 1 count) + * @arg TMR4_CNT_INT_MASK_2: Counter interrupt flag is set once for 3 every counter counts at "0x0000" or peak (skiping 2 count) + * @arg TMR4_CNT_INT_MASK_3: Counter interrupt flag is set once for 4 every counter counts at "0x0000" or peak (skiping 3 count) + * @arg TMR4_CNT_INT_MASK_4: Counter interrupt flag is set once for 5 every counter counts at "0x0000" or peak (skiping 4 count) + * @arg TMR4_CNT_INT_MASK_5: Counter interrupt flag is set once for 6 every counter counts at "0x0000" or peak (skiping 5 count) + * @arg TMR4_CNT_INT_MASK_6: Counter interrupt flag is set once for 7 every counter counts at "0x0000" or peak (skiping 6 count) + * @arg TMR4_CNT_INT_MASK_7: Counter interrupt flag is set once for 8 every counter counts at "0x0000" or peak (skiping 7 count) + * @arg TMR4_CNT_INT_MASK_8: Counter interrupt flag is set once for 9 every counter counts at "0x0000" or peak (skiping 8 count) + * @arg TMR4_CNT_INT_MASK_9: Counter interrupt flag is set once for 10 every counter counts at "0x0000" or peak (skiping 9 count) + * @arg TMR4_CNT_INT_MASK_10: Counter interrupt flag is set once for 11 every counter counts at "0x0000" or peak (skiping 10 count) + * @arg TMR4_CNT_INT_MASK_11: Counter interrupt flag is set once for 12 every counter counts at "0x0000" or peak (skiping 11 count) + * @arg TMR4_CNT_INT_MASK_12: Counter interrupt flag is set once for 13 every counter counts at "0x0000" or peak (skiping 12 count) + * @arg TMR4_CNT_INT_MASK_13: Counter interrupt flag is set once for 14 every counter counts at "0x0000" or peak (skiping 13 count) + * @arg TMR4_CNT_INT_MASK_14: Counter interrupt flag is set once for 15 every counter counts at "0x0000" or peak (skiping 14 count) + * @arg TMR4_CNT_INT_MASK_15: Counter interrupt flag is set once for 16 every counter counts at "0x0000" or peak (skiping 15 count) + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: pu16MaskTimes = NULL or u16IntSource value is invalid + */ +en_result_t TMR4_CNT_GetIntMaskCurrentTimes(const M4_TMR4_TypeDef *TMR4x, + uint16_t u16IntSource, + uint16_t *pu16MaskTimes) +{ + en_result_t enRet = Ok; + + if (NULL == pu16MaskTimes) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + switch (u16IntSource) + { + case TMR4_CNT_INT_ZERO: + *pu16MaskTimes = (uint16_t)(READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_ZIC) >> TMR4_CVPR_ZIC_POS); + break; + case TMR4_CNT_INT_PEAK: + *pu16MaskTimes = (uint16_t)(READ_REG16_BIT(TMR4x->CVPR, TMR4_CVPR_PIC) >> TMR4_CVPR_PIC_POS); + break; + default: + DDL_ASSERT(NULL); + enRet = ErrorInvalidParameter; + break; + } + } + + return enRet; +} + +/** + * @brief Set TMR4 count direction signal output to port + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR4_CNT_PortOutputDirSigCmd(M4_TMR4_TypeDef *TMR4x, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS); + } + else + { + CLEAR_REG16_BIT(TMR4x->SCER, TMR4_SCER_PCTS); + } +} + +/** + * @} + */ + +/** + * @defgroup TMR4_OCO_Global_Functions TMR4 OCO Global Functions + * @{ + */ + +/** + * @brief Initialize TMR4 OCO + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] pstcInit Pointer to a @ref stc_tmr4_oco_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: u32Ch is invalid or pstcInit = NULL + */ +en_result_t TMR4_OCO_Init(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_tmr4_oco_init_t *pstcInit) +{ + uint16_t u16Val; + __IO uint16_t *TMR4_OCER; + __IO uint16_t *TMR4_OCSR; + __IO uint16_t *TMR4_OCCR; + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_STATE(pstcInit->u16OcoCmd)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCCR_LINK_TRANSFER(pstcInit->u16OccrLinkTransfer)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCMR_LINK_TRANSFER(pstcInit->u16OcmrLinkTransfer)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCCR_BUF_MODE(pstcInit->u16OccrBufMode)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCMR_BUF_MODE(pstcInit->u16OcmrBufMode)); + DDL_ASSERT(IS_VALID_TMR4_OCO_PORT_INVALID_OP(pstcInit->u16OcoInvalidOp)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + TMR4_OCCR = TMR4_OCCRx(TMR4x, u32Ch); + + /* Set port output valid && OP level && interrupt */ + u16Val = ((uint16_t)(pstcInit->u16OcoCmd << SHIFT_1BIT(u32Ch)) | \ + (uint16_t)(pstcInit->u16OcoInvalidOp << SHIFT_1BIT(u32Ch))); + MODIFY_REG16(*TMR4_OCSR, TMR4_OCSR_MASK(u32Ch), u16Val); + + /* Set OCMR&&OCCR buffer */ + u16Val = (TMR4_OCER_CxBUFEN(u32Ch, pstcInit->u16OccrBufMode) | \ + TMR4_OCER_MxBUFEN(u32Ch, pstcInit->u16OcmrBufMode) | \ + TMR4_OCER_LMCx(u32Ch, pstcInit->u16OccrLinkTransfer) | \ + TMR4_OCER_LMMx(u32Ch, pstcInit->u16OcmrLinkTransfer)); + MODIFY_REG16(*TMR4_OCER, TMR4_OCER_MASK(u32Ch), u16Val); + + /* Set OCO compare match value */ + WRITE_REG16(*TMR4_OCCR, pstcInit->u16CompareVal); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr4_oco_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr4_oco_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t TMR4_OCO_StructInit(stc_tmr4_oco_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u16OcoCmd = TMR4_OCO_ENABLE; + pstcInit->u16OccrLinkTransfer = TMR4_OCO_OCCR_LINK_TRANSFER_DISABLE; + pstcInit->u16OcmrLinkTransfer = TMR4_OCO_OCMR_LINK_TRANSFER_DISABLE; + pstcInit->u16OccrBufMode = TMR4_OCO_OCCR_BUF_DISABLE; + pstcInit->u16OcmrBufMode = TMR4_OCO_OCMR_BUF_DISABLE; + pstcInit->u16OcoInvalidOp = TMR4_OCO_INVAILD_OP_LOW; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initialize TMR4 OCO + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval None + */ +void TMR4_OCO_DeInit(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *TMR4_OCER; + __IO uint16_t *TMR4_OCSR; + __IO uint16_t *TMR4_OCCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + TMR4_OCCR = TMR4_OCCRx(TMR4x, u32Ch); + + /* Clear bits: port output valid && OP level && interrupt */ + CLEAR_REG16_BIT(*TMR4_OCSR, TMR4_OCSR_MASK(u32Ch)); + + /* Clear bits: OCMR&&OCCR buffer */ + CLEAR_REG16_BIT(*TMR4_OCER, TMR4_OCER_MASK(u32Ch)); + + /* Set OCO compare match value */ + WRITE_REG16(*TMR4_OCCR, 0x0000U); +} + +/** + * @brief Set TMR4 OCO OCCR buffer mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16OccrBufMode TMR4 OCO OCCR buffer mode + * This parameter can be one of the following values: + * @arg TMR4_OCO_OCCR_BUF_DISABLE: Disable the register OCCR buffer function + * @arg TMR4_OCO_OCCR_BUF_CNT_ZERO: Register OCCR buffer transfer when counter value is 0x0000 + * @arg TMR4_OCO_OCCR_BUF_CNT_PEAK: Register OCCR buffer transfer when counter value is CPSR + * @arg TMR4_OCO_OCCR_BUF_CNT_ZERO_OR_PEAK: Register OCCR buffer transfer when the value is both 0 and CPSR + * @retval None + */ +void TMR4_OCO_SetOccrBufMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OccrBufMode) +{ + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCCR_BUF_MODE(u16OccrBufMode)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Set OCER register: OCCR buffer mode */ + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_CxBUFEN_MASK(u32Ch), \ + TMR4_OCER_CxBUFEN(u32Ch, u16OccrBufMode)); +} + +/** + * @brief Get TMR4 OCO OCCR buffer mode + * This parameter can be one of the following values: + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval Returned value can be one of the following values: + * @arg TMR4_OCO_OCCR_BUF_DISABLE: Disable the register OCCR buffer function + * @arg TMR4_OCO_OCCR_BUF_CNT_ZERO: Register OCCR buffer transfer when counter value is 0x0000 + * @arg TMR4_OCO_OCCR_BUF_CNT_PEAK: Register OCCR buffer transfer when counter value is CPSR + * @arg TMR4_OCO_OCCR_BUF_CNT_ZERO_OR_PEAK: Register OCCR buffer transfer when the value is both 0 and CPSR + */ +uint16_t TMR4_OCO_GetOccrBufMode(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + uint16_t OccrBufMode; + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Get OCCR buffer mode */ + OccrBufMode = READ_REG16_BIT(*TMR4_OCER, TMR4_OCER_CxBUFEN_MASK(u32Ch)); + + return (uint16_t)(OccrBufMode >> SHIFT_2BIT(u32Ch)); +} + +/** + * @brief Set TMR4 OCO OCCR buffer link transfer function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16TransferState The OCO OCCR buffer link transfer state + * @arg TMR4_OCO_OCCR_LINK_TRANSFER_DISABLE: Disable the register OCCR buffer link transfer function + * @arg TMR4_OCO_OCCR_LINK_TRANSFER_ENABLE: Register OCCR buffer transfer when the value is both 0 and CPSR and ZIC/PIC is 0 + * @retval None + */ +void TMR4_OCO_SetOccrLinkTransfer(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16TransferState) +{ + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCCR_LINK_TRANSFER(u16TransferState)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Set OCER register: OCCR link transfer function */ + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_LMCx_MASK(u32Ch), \ + TMR4_OCER_LMCx(u32Ch, u16TransferState)); +} + +/** + * @brief Set TMR4 OCO OCMR buffer mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16OcmrBufMode TMR4 OCO OCCR buffer mode + * This parameter can be one of the following values: + * @arg TMR4_OCO_OCMR_BUF_DISABLE: Disable the register OCMR buffer function + * @arg TMR4_OCO_OCMR_BUF_CNT_ZERO: Register OCMR buffer transfer when counter value is 0x0000 + * @arg TMR4_OCO_OCMR_BUF_CNT_PEAK: Register OCMR buffer transfer when counter value is CPSR + * @arg TMR4_OCO_OCMR_BUF_CNT_ZERO_OR_PEAK: Register OCMR buffer transfer when the value is both 0 and CPSR + * @retval None + */ +void TMR4_OCO_SetOcmrBufMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OcmrBufMode) +{ + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCMR_BUF_MODE(u16OcmrBufMode)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Set OCER register: OCMR buffer mode */ + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_MxBUFEN_MASK(u32Ch), \ + TMR4_OCER_MxBUFEN(u32Ch, u16OcmrBufMode)); +} + +/** + * @brief Get TMR4 OCO OCMR buffer mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval Returned value can be one of the following values: + * This parameter can be one of the following values: + * @arg TMR4_OCO_OCMR_BUF_DISABLE: Disable the register OCMR buffer function + * @arg TMR4_OCO_OCMR_BUF_CNT_ZERO: Register OCMR buffer transfer when counter value is 0x0000 + * @arg TMR4_OCO_OCMR_BUF_CNT_PEAK: Register OCMR buffer transfer when counter value is CPSR + * @arg TMR4_OCO_OCMR_BUF_CNT_ZERO_OR_PEAK: Register OCMR buffer transfer when the value is both 0 and CPSR + */ +uint16_t TMR4_OCO_GetOcmrBufMode(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + uint16_t u16OcmrBufMode; + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Get OCCR buffer mode */ + u16OcmrBufMode = READ_REG16_BIT(*TMR4_OCER, TMR4_OCER_MxBUFEN_MASK(u32Ch)); + + return (uint16_t)(u16OcmrBufMode >> SHIFT_2BIT(u32Ch)); +} + +/** + * @brief Set TMR4 OCO OCMR buffer link transfer function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16TransferState The OCO OCCR buffer link transfer state + * @arg TMR4_OCO_OCCR_LINK_TRANSFER_DISABLE: Disable the register OCCR buffer link transfer function + * @arg TMR4_OCO_OCCR_LINK_TRANSFER_ENABLE: Register OCCR buffer transfer when the value is both 0 and CPSR and ZIC/PIC is 0 + * @retval None + */ +void TMR4_OCO_SetOcmrLinkTransfer(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16TransferState) +{ + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_OCMR_LINK_TRANSFER(u16TransferState)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Set OCER register: OCMR link transfer function */ + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_LMMx_MASK(u32Ch), \ + TMR4_OCER_LMMx(u32Ch, u16TransferState)); +} + +/** + * @brief Extend the matching conditions of TMR4 OCO channel + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16ExtMatch TMR4 OCO extend match function selection + * @arg TMR4_OCO_EXTEND_MATCH_DISABLE: Disable TMR4 OCO extend match function + * @arg TMR4_OCO_EXTEND_MATCH_ENABLE: Enable TMR4 OCO extend match function + * @retval None + */ +void TMR4_OCO_SetExtMatchCond(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16ExtMatch) +{ + __IO uint16_t *TMR4_OCER; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_EXTEND_MATCH(u16ExtMatch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + + /* Set OCER register: Extend match function */ + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_MCECx_MASK(u32Ch), \ + TMR4_OCER_MCECx(u32Ch, u16ExtMatch)); +} + +/** + * @brief Set the TMR4 OCO high channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel. + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @param [in] pstcMode Pointer to a @ref stc_oco_high_ch_compare_mode_t structure of the TMR4 OCO high channel mode + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: pstcMode = NULL + */ +en_result_t TMR4_OCO_SetHighChCompareMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_oco_high_ch_compare_mode_t *pstcMode) +{ + __IO uint16_t *TMR4_OCER; + __IO uint16_t *TMR4_OCMRxH; + en_result_t enRet = ErrorInvalidParameter; + + /* Check pointer */ + if (NULL != pstcMode) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_HIGH_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_EXTEND_MATCH(pstcMode->u16ExtendMatch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + TMR4_OCMRxH = TMR4_OCMRx(TMR4x, u32Ch); + + WRITE_REG16(*TMR4_OCMRxH, pstcMode->OCMRx); + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_MCECx_MASK(u32Ch), \ + TMR4_OCER_MCECx(u32Ch, pstcMode->u16ExtendMatch)); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the TMR4 OCO low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel. + * This parameter can be one of the following values: + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] pstcMode Pointer to a @ref stc_oco_low_ch_compare_mode_t structure of the TMR4 OCO low channel mode + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: pstcMode = NULL + */ +en_result_t TMR4_OCO_SetLowChCompareMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_oco_low_ch_compare_mode_t *pstcMode) +{ + __IO uint16_t *TMR4_OCER; + __IO uint32_t *TMR4_OCMRxL; + en_result_t enRet = ErrorInvalidParameter; + + /* Check pointer */ + if (NULL != pstcMode) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_LOW_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_EXTEND_MATCH(pstcMode->u16ExtendMatch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCER = TMR4_OCERx(TMR4x, u32Ch); + TMR4_OCMRxL = (__IO uint32_t*)((uint32_t)TMR4_OCMRx(TMR4x, u32Ch)); + + WRITE_REG32(*TMR4_OCMRxL, pstcMode->OCMRx); + MODIFY_REG16(*TMR4_OCER, \ + TMR4_OCER_MCECx_MASK(u32Ch), \ + TMR4_OCER_MCECx(u32Ch, pstcMode->u16ExtendMatch)); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the TMR4 OCO low channel mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16OcoCmd The function new state + * @arg TMR4_OCO_DISABLE: Disable TMR4 OCO function + * @arg TMR4_OCO_ENABLE: Enable TMR4 OCO function + * @retval None + */ +void TMR4_OCO_SetOutputCompare(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OcoCmd) +{ + __IO uint16_t *TMR4_OCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_STATE(u16OcoCmd)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + + /* Set OCSR port output compare */ + MODIFY_REG16(*TMR4_OCSR, \ + TMR4_OCSR_OCEx_MASK(u32Ch), \ + TMR4_OCSR_OCEx(u32Ch, u16OcoCmd)); +} + +/** + * @brief Set the TMR4 OCO interrupt function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR4_OCO_IntCmd(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + en_functional_state_t enNewState) +{ + __IO uint16_t *TMR4_OCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + + if (Enable == enNewState) + { + SET_REG16_BIT(*TMR4_OCSR, TMR4_OCSR_OCIEx(u32Ch, TMR4_OCSR_OCIEH)); + } + else + { + CLEAR_REG16_BIT(*TMR4_OCSR, TMR4_OCSR_OCIEx(u32Ch, TMR4_OCSR_OCIEH)); + } +} + +/** + * @brief Set the TMR4 OCO interrupt flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval An en_flag_status_t enumeration value: + * - Reset: None interrupt request flag is set on TMR4 OCO + * - Set: Detection interrupt request on TMR4 OCO + */ +en_flag_status_t TMR4_OCO_GetStatus(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_OCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + + return (READ_REG16_BIT(*TMR4_OCSR, TMR4_OCSR_OCFx(u32Ch, TMR4_OCSR_OCFH)) ? Set : Reset); +} + +/** + * @brief Clear the TMR4 OCO interrupt function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval None + */ +void TMR4_OCO_ClearStatus(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *TMR4_OCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + + /* Clear OCSR count compare flag */ + CLEAR_REG16_BIT(*TMR4_OCSR, TMR4_OCSR_OCFx(u32Ch, TMR4_OCSR_OCFH)); +} + +/** + * @brief Set TMR4 OCO invalid output polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16OutputPolarity TMR4 OCO invalid output polarity. + * This parameter can be one of the following values: + * @arg TMR4_OCO_INVAILD_OP_LOW: TMR4 OCO output low level when OCO is invalid + * @arg TMR4_OCO_INVAILD_OP_HIGH: TMR4 OCO output high level when OCO is invalid + * @retval None + */ +void TMR4_OCO_SetOcoInvalidOp(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OutputPolarity) +{ + __IO uint16_t *TMR4_OCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_OCO_PORT_INVALID_OP(u16OutputPolarity)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + + /* Set OCSR register: OCO invalid output polarity */ + MODIFY_REG16(*TMR4_OCSR, \ + TMR4_OCSR_OCPx_MASK(u32Ch), \ + TMR4_OCSR_OCPx(u32Ch, u16OutputPolarity)); +} + +/** + * @brief Get TMR4 OCO output polarity + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval Returned value can be one of the following values: + * @arg TMR4_OCO_INVAILD_OP_LOW: TMR4 OCO output low level when OCO is invalid + * @arg TMR4_OCO_INVAILD_OP_HIGH: TMR4 OCO output high level when OCO is invalid + */ +uint16_t TMR4_OCO_GetOutputPolarity(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + uint16_t u16OutputPolarity; + __IO uint16_t *TMR4_OCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCSR = TMR4_OCSRx(TMR4x, u32Ch); + + /* Get OCSR register: OCO output polarity */ + u16OutputPolarity = READ_REG16_BIT(*TMR4_OCSR, TMR4_OCSR_OCPx_MASK(u32Ch)); + + return (u16OutputPolarity >> SHIFT_1BIT(u32Ch)); +} + +/** + * @brief Set TMR4 OCO compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @param [in] u16CompareVal The TMR4 OCO OCCR register value + * @arg number of 16bit + * @retval None + */ +void TMR4_OCO_SetCompareVal(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16CompareVal) +{ + __IO uint16_t *TMR4_OCCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCCR = TMR4_OCCRx(TMR4x, u32Ch); + + WRITE_REG16(*TMR4_OCCR, u16CompareVal); +} + +/** + * @brief Get TMR4 OCO OCCR compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 OCO channel + * This parameter can be one of the following values: + * @arg TMR4_OCO_UH: TMR4 OCO channel - UH + * @arg TMR4_OCO_UL: TMR4 OCO channel - UL + * @arg TMR4_OCO_VH: TMR4 OCO channel - VH + * @arg TMR4_OCO_VL: TMR4 OCO channel - VL + * @arg TMR4_OCO_WH: TMR4 OCO channel - WH + * @arg TMR4_OCO_WL: TMR4 OCO channel - WL + * @retval The OCCR register value of the TMR4 OCO + */ +uint16_t TMR4_OCO_GetCompareVal(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_OCCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_OCO_CH(u32Ch)); + + /* Get pointer of current channel OCO register address */ + TMR4_OCCR = TMR4_OCCRx(TMR4x, u32Ch); + + return READ_REG16(*TMR4_OCCR); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_PWM_Global_Functions TMR4 PWM Global Functions + * @{ + */ + +/** + * @brief Initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [in] pstcInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: u32Ch is invalid or pstcInit = NULL + */ +en_result_t TMR4_PWM_Init(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_tmr4_pwm_init_t *pstcInit) +{ + __IO uint16_t *TMR4_POCR; + __IO uint16_t *TMR4_RCSR; + en_result_t enRet = ErrorInvalidParameter; + + /* Check channel && structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_PWM_MODE(pstcInit->u16Mode)); + DDL_ASSERT(IS_VALID_TMR4_PWM_PCLK_DIV(pstcInit->u16PclkDiv)); + DDL_ASSERT(IS_VALID_TMR4_PWM_TRANSFORM_OCO_POLARITY(pstcInit->u16TransformOcoPol)); + DDL_ASSERT(IS_VALID_TMR4_PWM_EMB_PORT_OUTPUT_STATE(pstcInit->u32EmbOxHPortState)); + DDL_ASSERT(IS_VALID_TMR4_PWM_EMB_PORT_OUTPUT_STATE(pstcInit->u32EmbOxLPortState)); + + /* Get pointer of current channel PWM register address */ + TMR4_POCR = TMR4_POCRx(TMR4x, u32Ch); + TMR4_RCSR = TMR4_RCSRx(TMR4x); + + /* Set POCR register */ + WRITE_REG16(*TMR4_POCR, (pstcInit->u16PclkDiv | pstcInit->u16Mode | pstcInit->u16TransformOcoPol)); + + /* Set RCSR register */ + MODIFY_REG16(*TMR4_RCSR, + TMR4_RCSR_RTEx_MASK(u32Ch), \ + (TMR4_RCSR_RTIDx_MASK(u32Ch) | TMR4_RCSR_RTSx_MASK(u32Ch) | TMR4_RCSR_RTICx_MASK(u32Ch))); + + /* Set PSCR register: PWM port state */ + MODIFY_REG32(TMR4x->PSCR, \ + ((TMR4_PSCR_OEUH | TMR4_PSCR_OEUL) << (u32Ch * 2UL) | \ + (TMR4_PSCR_OSUH | TMR4_PSCR_OSUL) << (u32Ch * 4UL)), \ + ((pstcInit->u32OxHPortOutMode << (u32Ch * 2UL)) | \ + (pstcInit->u32OxLPortOutMode << (u32Ch * 2UL + 1UL)) | \ + (pstcInit->u32EmbOxHPortState << (u32Ch * 4UL)) | \ + (pstcInit->u32EmbOxLPortState << (u32Ch * 4UL + 2UL)))); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t TMR4_PWM_StructInit(stc_tmr4_pwm_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u16Mode = TMR4_PWM_THROUGH_MODE; + pstcInit->u16PclkDiv = TMR4_PWM_PCLK_DIV1; + pstcInit->u16TransformOcoPol = TMR4_PWM_OP_OXH_HOLD_OXL_HOLD; + pstcInit->u32OxHPortOutMode = TMR4_PWM_PORT_OUTPUT_OSxy; + pstcInit->u32EmbOxHPortState = TMR4_PWM_EMB_PORT_OUTPUT_NORMAL; + pstcInit->u32OxLPortOutMode = TMR4_PWM_PORT_OUTPUT_OSxy; + pstcInit->u32EmbOxLPortState = TMR4_PWM_EMB_PORT_OUTPUT_NORMAL; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval None + */ +void TMR4_PWM_DeInit(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *TMR4_POCR; + __IO uint16_t *TMR4_RCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_POCR = TMR4_POCRx(TMR4x, u32Ch); + TMR4_RCSR = TMR4_RCSRx(TMR4x); + + /* Set POCR register */ + WRITE_REG16(*TMR4_POCR, (TMR4_PWM_PCLK_DIV1 | \ + TMR4_PWM_THROUGH_MODE | \ + TMR4_PWM_OP_OXH_HOLD_OXL_HOLD)); + + /* Set RCSR register */ + MODIFY_REG16(*TMR4_RCSR, + TMR4_RCSR_RTEx_MASK(u32Ch), \ + (TMR4_RCSR_RTIDx_MASK(u32Ch) | \ + TMR4_RCSR_RTSx_MASK(u32Ch) | \ + TMR4_RCSR_RTICx_MASK(u32Ch))); +} + +/** + * @brief Set TMR4 PWM PCLK clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [in] u16Div TMR4 PWM PCLK clock division + * This parameter can be one of the following values: + * @arg TMR4_PWM_PCLK_DIV1: PCLK + * @arg TMR4_PWM_PCLK_DIV2: PCLK/2 + * @arg TMR4_PWM_PCLK_DIV4: PCLK/4 + * @arg TMR4_PWM_PCLK_DIV8: PCLK/8 + * @arg TMR4_PWM_PCLK_DIV16: PCLK/16 + * @arg TMR4_PWM_PCLK_DIV32: PCLK/32 + * @arg TMR4_PWM_PCLK_DIV64: PCLK/64 + * @arg TMR4_PWM_PCLK_DIV128: PCLK/128 + * @retval None + * @note The PCLK division function is valid when clock source is PCLK + */ +void TMR4_PWM_SetPclkDiv(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16Div) +{ + __IO uint16_t *TMR4_POCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_PWM_PCLK_DIV(u16Div)); + + /* Get pointer of current channel PWM register address */ + TMR4_POCR = TMR4_POCRx(TMR4x, u32Ch); + MODIFY_REG16(*TMR4_POCR, TMR4_POCR_DIVCK, u16Div); +} + +/** + * @brief Get TMR4 PWM PCLK clock division + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval Returned value can be one of the following values: + * @arg TMR4_PWM_PCLK_DIV1: PCLK + * @arg TMR4_PWM_PCLK_DIV2: PCLK/2 + * @arg TMR4_PWM_PCLK_DIV4: PCLK/4 + * @arg TMR4_PWM_PCLK_DIV8: PCLK/8 + * @arg TMR4_PWM_PCLK_DIV16: PCLK/16 + * @arg TMR4_PWM_PCLK_DIV32: PCLK/32 + * @arg TMR4_PWM_PCLK_DIV64: PCLK/64 + * @arg TMR4_PWM_PCLK_DIV128: PCLK/128 + * @note The PCLK division function is valid when clock source is PCLK + */ +uint16_t TMR4_PWM_GetPclkDiv(const M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *TMR4_POCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_POCR = TMR4_POCRx(TMR4x, u32Ch); + return READ_REG16_BIT(*TMR4_POCR, TMR4_POCR_DIVCK); +} + +/** + * @brief Set TMR4 PWM output polarity transform + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [in] u16OcoPolTransform TMR4 PWM transform OCO polarity + * This parameter can be one of the following values: + * @arg TMR4_PWM_OP_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level + * @arg TMR4_PWM_OP_OXH_INVERT_OXL_INVERT: Output both PWML and PWMH signals reversed + * @arg TMR4_PWM_OP_OXH_INVERT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level + * @arg TMR4_PWM_OP_OXH_HOLD_OXL_INVERT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed + * @retval None + */ +void TMR4_PWM_SetOcoPolarityTransform(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16OcoPolTransform) +{ + __IO uint16_t *TMR4_POCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_PWM_TRANSFORM_OCO_POLARITY(u16OcoPolTransform)); + + /* Get pointer of current channel PWM register address */ + TMR4_POCR = TMR4_POCRx(TMR4x, u32Ch); + + MODIFY_REG16(*TMR4_POCR, TMR4_POCR_LVLS, u16OcoPolTransform); +} + +/** + * @brief Get TMR4 PWM output polarity transform + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval Returned value can be one of the following values: + * @arg TMR4_PWM_OP_OXH_HOLD_OXL_HOLD: Output PWML and PWMH signals without changing the level + * @arg TMR4_PWM_OP_OXH_INVERT_OXL_INVERT: Output both PWML and PWMH signals reversed + * @arg TMR4_PWM_OP_OXH_INVERT_OXL_HOLD: Output the PWMH signal reversed, outputs the PWML signal without changing the level + * @arg TMR4_PWM_OP_OXH_HOLD_OXL_INVERT: Output the PWMH signal without changing the level, Outputs the PWML signal reversed + */ +uint16_t TMR4_PWM_GetOcoPolarityTransform(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_POCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_POCR = TMR4_POCRx(TMR4x, u32Ch); + + return READ_REG16_BIT(*TMR4_POCR, TMR4_POCR_LVLS); +} + +/** + * @brief Start TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval None + */ +void TMR4_PWM_StartReloadTimer(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTEx_MASK(u32Ch)); +} + +/** + * @brief Stop TMR4 PWM reload-timer + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval None + */ +void TMR4_PWM_StopReloadTimer(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTSx_MASK(u32Ch)); +} + +/** + * @brief Set the TMR4 PWM interrupt function + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR4_PWM_IntCmd(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + CLEAR_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTIDx_MASK(u32Ch)); + } + else + { + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTIDx_MASK(u32Ch)); + } +} + +/** + * @brief Get PWM reload-timer interrupt flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval An en_flag_status_t enumeration value: + * - Reset None interrupt request on PWM reload-timer + * - Set Detection interrupt request on PWM reload-timer + */ +en_flag_status_t TMR4_PWM_GetStatus(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_RCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_RCSR = TMR4_RCSRx(TMR4x); + + return (READ_REG16_BIT(*TMR4_RCSR, TMR4_RCSR_RTIFx_MASK(u32Ch)) ? Set : Reset); +} + +/** + * @brief Clear PWM reload-timer interrupt flag + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @retval None + */ +void TMR4_PWM_ClearStatus(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + SET_REG16_BIT(TMR4x->RCSR, TMR4_RCSR_RTICx_MASK(u32Ch)); +} + +/** + * @brief Set TMR4 PWM dead region count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [in] u16PDAR PDAR value + * @arg number of 16bit + * @param [in] u16PDBR PDBR value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetDeadRegionValue(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16PDAR, + uint16_t u16PDBR) +{ + __IO uint16_t *TMR4_PDAR; + __IO uint16_t *TMR4_PDBR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_PDAR = TMR4_PDARx(TMR4x, u32Ch); + TMR4_PDBR = TMR4_PDBRx(TMR4x, u32Ch); + + WRITE_REG16(*TMR4_PDAR, u16PDAR); + WRITE_REG16(*TMR4_PDBR, u16PDBR); +} + +/** + * @brief Get TMR4 PWM dead region count + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [out] pu16PDAR Pointer of 16bit data + * @arg pointer of 16bit + * @param [out] pu16PDBR Pointer of 16bit data + * @arg pointer of 16bit + * @retval None + */ +void TMR4_PWM_GetDeadRegionValue(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t *pu16PDAR, + uint16_t *pu16PDBR) +{ + __IO uint16_t *TMR4_PDAR; + __IO uint16_t *TMR4_PDBR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_PDAR = TMR4_PDARx(TMR4x, u32Ch); + TMR4_PDBR = TMR4_PDBRx(TMR4x, u32Ch); + + *pu16PDAR = READ_REG16(*TMR4_PDAR); + *pu16PDBR = READ_REG16(*TMR4_PDBR); +} + +/** + * @brief Set TMR4 PWM filter count value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_U: TMR4 PWM couple channel - U + * @arg TMR4_PWM_V: TMR4 PWM couple channel - V + * @arg TMR4_PWM_W: TMR4 PWM couple channel - W + * @param [in] u16Count TMR4 PWM filter count value + * @arg number of 16bit + * @retval None + */ +void TMR4_PWM_SetFilterCountValue(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16Count) +{ + __IO uint16_t *TMR4_PFSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_CH(u32Ch)); + + /* Get pointer of current channel PWM register address */ + TMR4_PFSR = TMR4_PFSRx(TMR4x, u32Ch); + + WRITE_REG16(*TMR4_PFSR, u16Count); +} + +/** + * @brief Enable TMR4 PWM master output + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR4_PWM_AutoOutputCmd(M4_TMR4_TypeDef *TMR4x, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE); + } + else + { + CLEAR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_AOE); + } +} + +/** + * @brief Enable TMR4 PWM master output + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR4_PWM_MasterOutputCmd(M4_TMR4_TypeDef *TMR4x, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE); + } + else + { + CLEAR_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_MOE); + } +} + +/** + * @brief Set TMR4 PWM port output mode + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32PwmPort TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_PORT_OUH: TMR4 PWM port - TIM4__OUH + * @arg TMR4_PWM_PORT_OUL: TMR4 PWM port - TIM4__OUL + * @arg TMR4_PWM_PORT_OVH: TMR4 PWM port - TIM4__OVH + * @arg TMR4_PWM_PORT_OVL: TMR4 PWM port - TIM4__OVL + * @arg TMR4_PWM_PORT_OWH: TMR4 PWM port - TIM4__OWH + * @arg TMR4_PWM_PORT_OWL: TMR4 PWM port - TIM4__OWL + * @param [in] u32Mode The PWM port output mode + * This parameter can be one of the following values: + * @arg TMR4_PWM_PORT_OUTPUT_OSxy: TIM4__Oxy output polarity by specified OSxy + * @arg TMR4_PWM_PORT_OUTPUT_NORMAL: TIM4__Oxy output normal PWM + * @retval None + */ +void TMR4_PWM_PortOutputMode(M4_TMR4_TypeDef *TMR4x, + uint32_t u32PwmPort, + uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_PORT(u32PwmPort)); + DDL_ASSERT(IS_VALID_TMR4_PWM_PORT_MODE(u32Mode)); + + MODIFY_REG32(TMR4x->PSCR, \ + TMR4_PSCR_OExy_MASK(u32PwmPort), \ + TMR4_PSCR_OExy(u32PwmPort, u32Mode)); +} + +/** + * @brief Set TMR4 PWM port enable bit effective time + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32EffectTime Effective time + * This parameter can be one of the following values: + * @arg TMR4_PWM_PORT_ENBIT_EFFECT_IMMEDIATE:Effective time - Immediate + * @arg TMR4_PWM_PORT_ENBIT_EFFECT_CNTUVF: Effective time - TMR4 counter underflow + * @arg TMR4_PWM_PORT_ENBIT_EFFECT_CNTOVF: Effective time - TMR4 counter overflow + * @retval None + */ +void TMR4_PWM_SetPortEnBitEffectTime(M4_TMR4_TypeDef *TMR4x, + uint32_t u32EffectTime) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_PORT_ENBIT_EFFECT(u32EffectTime)); + + MODIFY_REG32(TMR4x->PSCR, TMR4_PSCR_ODT, u32EffectTime); +} + +/** + * @brief Get TMR4 PWM port state + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval Returned value can be one of the following values: + * @arg TMR4_PWM_PORT_ENBIT_EFFECT_IMMEDIATE:TMR4 PWM port enable bit effective Time - Immediate + * @arg TMR4_PWM_PORT_ENBIT_EFFECT_CNTUVF: TMR4 PWM port enable bit effective Time - TMR4 counter underflow + * @arg TMR4_PWM_PORT_ENBIT_EFFECT_CNTOVF: TMR4 PWM port enable bit effective Time - TMR4 counter overflow + */ +uint32_t TMR4_PWM_GetPortEnBitEffectTime(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + return READ_REG32_BIT(TMR4x->PSCR, TMR4_PSCR_ODT); +} + +/** + * @brief TMR4 PWM port output when emb event occur + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32PwmPort TMR4 PWM channel + * This parameter can be one of the following values: + * @arg TMR4_PWM_PORT_OUH: TMR4 PWM port - TIM4__OUH + * @arg TMR4_PWM_PORT_OUL: TMR4 PWM port - TIM4__OUL + * @arg TMR4_PWM_PORT_OVH: TMR4 PWM port - TIM4__OVH + * @arg TMR4_PWM_PORT_OVL: TMR4 PWM port - TIM4__OVL + * @arg TMR4_PWM_PORT_OWH: TMR4 PWM port - TIM4__OWH + * @arg TMR4_PWM_PORT_OWL: TMR4 PWM port - TIM4__OWL + * @param [in] u32State The port new state + * This parameter can be one of the following values: + * @arg TMR4_PWM_EMB_PORT_OUTPUT_NORMAL:TIM4__Oxy output normal + * @arg TMR4_PWM_EMB_PORT_OUTPUT_HIZ: TIM4__Oxy output Hi-z + * @arg TMR4_PWM_EMB_PORT_OUTPUT_LOW: TIM4__Oxy output low level + * @arg TMR4_PWM_EMB_PORT_OUTPUT_HIGH: TIM4__Oxy output high level + * @retval None + */ +void TMR4_PWM_EmbPwmPortOutputState(M4_TMR4_TypeDef *TMR4x, + uint32_t u32PwmPort, + uint32_t u32State) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_PWM_PORT(u32PwmPort)); + DDL_ASSERT(IS_VALID_TMR4_PWM_EMB_PORT_OUTPUT_STATE(u32State)); + + MODIFY_REG32(TMR4x->PSCR, \ + TMR4_PSCR_OSxy_MASK(u32PwmPort), \ + TMR4_PSCR_OSxy(u32PwmPort, u32State)); +} + +/** + * @} + */ + +/** + * @defgroup TMR4_SEVT_Global_Functions TMR4 SEVT Global Functions + * @{ + */ + +/** + * @brief Initialize TMR4 SEVT + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @param [in] pstcInit Pointer to a @ref stc_tmr4_sevt_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: u32Ch is invalid or pstcInit = NULL + */ +en_result_t TMR4_SEVT_Init(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + const stc_tmr4_sevt_init_t *pstcInit) +{ + __IO uint16_t *TMR4_SCCR; + __IO uint16_t *TMR4_SCSR; + __IO uint16_t *TMR4_SCMR; + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_MODE(pstcInit->u16Mode)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_LINK_TRANSFER(pstcInit->u16LinkTransfer)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_OUTPUT_EVENT(pstcInit->u16OutpuEvent)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_BUF_MODE(pstcInit->u16BufMode)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_UP_SEL(pstcInit->u16UpMatchCmd)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_DOWN_SEL(pstcInit->u16DownMatchCmd)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_PEAK_SEL(pstcInit->u16PeakMatchCmd)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_ZERO_SEL(pstcInit->u16ZeroMatchCmd)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_ZERO_MATCH_MASK_SEL(pstcInit->u16ZeroMatchMaskCmd)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_PEAK_MATCH_MASK_SEL(pstcInit->u16PeakMatchMaskCmd)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_MASK(pstcInit->u16MaskTimes)); + + /* Get actual address of register list of current channel */ + TMR4_SCCR = TMR4_SCCRx(TMR4x, u32Ch); + TMR4_SCSR = TMR4_SCSRx(TMR4x, u32Ch); + TMR4_SCMR = TMR4_SCMRx(TMR4x, u32Ch); + + /* Configure default parameter */ + WRITE_REG16(*TMR4_SCSR, 0x0000U); + WRITE_REG16(*TMR4_SCMR, 0xFF00U); + + /* Set SCSR register */ + WRITE_REG16(*TMR4_SCSR, \ + (pstcInit->u16Mode | \ + pstcInit->u16OutpuEvent | \ + pstcInit->u16BufMode | \ + pstcInit->u16LinkTransfer | \ + pstcInit->u16DownMatchCmd | \ + pstcInit->u16PeakMatchCmd | \ + pstcInit->u16UpMatchCmd | \ + pstcInit->u16ZeroMatchCmd)); + + /* Set SCMR register */ + WRITE_REG16(*TMR4_SCMR, \ + (pstcInit->u16MaskTimes | \ + pstcInit->u16ZeroMatchMaskCmd | \ + pstcInit->u16PeakMatchMaskCmd)); + + WRITE_REG16(*TMR4_SCCR, pstcInit->u16CompareVal); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr4_pwm_init_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr4_pwm_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: pstcInit = NULL + */ +en_result_t TMR4_SEVT_StructInit(stc_tmr4_sevt_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u16CompareVal = 0U; + pstcInit->u16Mode = TMR4_SEVT_MODE_COMPARE_TRIGGER; + pstcInit->u16OutpuEvent = TMR4_SEVT_OUTPUT_EVENT0; + pstcInit->u16BufMode = TMR4_SEVT_BUF_DISABLE; + pstcInit->u16LinkTransfer = TMR4_SEVT_LINK_TRANSFER_DISABLE; + pstcInit->u16DownMatchCmd = TMR4_SEVT_DOWN_DISABLE; + pstcInit->u16PeakMatchCmd = TMR4_SEVT_PEAK_DISABLE; + pstcInit->u16UpMatchCmd = TMR4_SEVT_UP_DISABLE; + pstcInit->u16ZeroMatchCmd = TMR4_SEVT_ZERO_DISABLE; + pstcInit->u16ZeroMatchMaskCmd = TMR4_SEVT_ZERO_MATCH_MASK_DISABLE; + pstcInit->u16PeakMatchMaskCmd = TMR4_SEVT_PEAK_MATCH_MASK_DISABLE; + pstcInit->u16MaskTimes = TMR4_SEVT_MASK_0; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initialize TMR4 PWM + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @retval None + */ +void TMR4_SEVT_DeInit(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *TMR4_SCCR; + __IO uint16_t *TMR4_SCSR; + __IO uint16_t *TMR4_SCMR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + TMR4_SCCR = TMR4_SCCRx(TMR4x, u32Ch); + TMR4_SCSR = TMR4_SCSRx(TMR4x, u32Ch); + TMR4_SCMR = TMR4_SCMRx(TMR4x, u32Ch); + + /* Configure default parameter */ + WRITE_REG16(*TMR4_SCCR, 0x0U); + WRITE_REG16(*TMR4_SCSR, 0x0000U); + WRITE_REG16(*TMR4_SCMR, 0xFF00U); +} + +/** + * @brief Set TMR4 SEVT trigger event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @param [in] u16Event TMR4 SEVT trigger event + * This parameter can be one of the following values: + * @arg TMR4_SEVT_OUTPUT_EVENT0: TMR4 SEVT output special event 0 + * @arg TMR4_SEVT_OUTPUT_EVENT1: TMR4 SEVT output special event 1 + * @arg TMR4_SEVT_OUTPUT_EVENT2: TMR4 SEVT output special event 2 + * @arg TMR4_SEVT_OUTPUT_EVENT3: TMR4 SEVT output special event 3 + * @arg TMR4_SEVT_OUTPUT_EVENT4: TMR4 SEVT output special event 4 + * @arg TMR4_SEVT_OUTPUT_EVENT5: TMR4 SEVT output special event 5 + * @retval None + */ +void TMR4_SEVT_SetOutpuEvent(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16Event) +{ + __IO uint16_t *TMR4_SCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_OUTPUT_EVENT(u16Event)); + + /* Get actual address of register list of current channel */ + TMR4_SCSR = TMR4_SCSRx(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*TMR4_SCSR, TMR4_SCSR_EVTOS, u16Event); +} + +/** + * @brief Get TMR4 SEVT trigger event + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @retval Returned value can be one of the following values: + * @arg TMR4_SEVT_OUTPUT_EVENT0: TMR4 SEVT output special event 0 + * @arg TMR4_SEVT_OUTPUT_EVENT1: TMR4 SEVT output special event 1 + * @arg TMR4_SEVT_OUTPUT_EVENT2: TMR4 SEVT output special event 2 + * @arg TMR4_SEVT_OUTPUT_EVENT3: TMR4 SEVT output special event 3 + * @arg TMR4_SEVT_OUTPUT_EVENT4: TMR4 SEVT output special event 4 + * @arg TMR4_SEVT_OUTPUT_EVENT5: TMR4 SEVT output special event 5 + */ +uint16_t TMR4_SEVT_GetOutpuEvent(M4_TMR4_TypeDef *TMR4x, uint32_t u32Ch) +{ + __IO uint16_t *TMR4_SCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + TMR4_SCSR = TMR4_SCSRx(TMR4x, u32Ch); + return READ_REG16_BIT(*TMR4_SCSR, TMR4_SCSR_EVTOS); +} + +/** + * @brief Set TMR4 SEVT delay object + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @param [in] u16DelayObject TMR4 SEVT delay object + * This parameter can be one of the following values: + * @arg TMR4_SEVT_DELAY_OCCRXH: TMR4 SEVT delay object - OCCRxh + * @arg TMR4_SEVT_DELAY_OCCRXL: TMR4 SEVT delay object - OCCRxl + * @retval None + */ +void TMR4_SEVT_SetDelayObject(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16DelayObject) +{ + __IO uint16_t *TMR4_SCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_OBJECT(u16DelayObject)); + + /* Get actual address of register list of current channel */ + TMR4_SCSR = TMR4_SCSRx(TMR4x, u32Ch); + + /* Set SCSR register */ + MODIFY_REG16(*TMR4_SCSR, TMR4_SCSR_EVTDS, u16DelayObject); +} + +/** + * @brief Get TMR4 SEVT SCCR register value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @retval Returned value can be one of the following values: + * @arg TMR4_SEVT_DELAY_OCCRXH: TMR4 SEVT delay object - OCCRxh + * @arg TMR4_SEVT_DELAY_OCCRXL: TMR4 SEVT delay object - OCCRxl + */ +uint16_t TMR4_SEVT_GetDelayObject(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_SCSR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + TMR4_SCSR = TMR4_SCSRx(TMR4x, u32Ch); + + return READ_REG16_BIT(*TMR4_SCSR, TMR4_SCSR_EVTDS); +} + +/** + * @brief Set TMR4 SEVT compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @param [in] u16CompareVal SCCR register value + * @arg number of 16bit + * @retval None + */ +void TMR4_SEVT_SetCompareVal(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16CompareVal) +{ + __IO uint16_t *TMR4_SCCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + TMR4_SCCR = TMR4_SCCRx(TMR4x, u32Ch); + + /* Set SCCR register */ + WRITE_REG16(*TMR4_SCCR, u16CompareVal); +} + +/** + * @brief Get TMR4 SEVT compare value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @retval SCCR register value + */ +uint16_t TMR4_SEVT_GetCompareVal(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_SCCR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + TMR4_SCCR = TMR4_SCCRx(TMR4x, u32Ch); + + return READ_REG16(*TMR4_SCCR); +} + +/** + * @brief Set TMR4 SEVT trigger event. + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @param [in] u16MaskTimes Mask times + * @arg TMR4_SEVT_MASK_0: Mask 0 times + * @arg TMR4_SEVT_MASK_1: Mask 1 times + * @arg TMR4_SEVT_MASK_2: Mask 2 times + * @arg TMR4_SEVT_MASK_3: Mask 3 times + * @arg TMR4_SEVT_MASK_4: Mask 4 times + * @arg TMR4_SEVT_MASK_5: Mask 5 times + * @arg TMR4_SEVT_MASK_6: Mask 6 times + * @arg TMR4_SEVT_MASK_7: Mask 7 times + * @arg TMR4_SEVT_MASK_8: Mask 8 times + * @arg TMR4_SEVT_MASK_9: Mask 9 times + * @arg TMR4_SEVT_MASK_10: Mask 10 times + * @arg TMR4_SEVT_MASK_11: Mask 11 times + * @arg TMR4_SEVT_MASK_12: Mask 12 times + * @arg TMR4_SEVT_MASK_13: Mask 13 times + * @arg TMR4_SEVT_MASK_14: Mask 14 times + * @arg TMR4_SEVT_MASK_15: Mask 15 times + * @retval None + */ +void TMR4_SEVT_SetMaskTimes(M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch, + uint16_t u16MaskTimes) +{ + __IO uint16_t *TMR4_SCMR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_MASK(u16MaskTimes)); + + /* Get actual address of register list of current channel */ + TMR4_SCMR = TMR4_SCMRx(TMR4x, u32Ch); + + /* Set SCMR register */ + MODIFY_REG16(*TMR4_SCMR, TMR4_SCMR_AMC, u16MaskTimes); +} + +/** + * @brief Get TMR4 SEVT SCCR register value + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u32Ch TMR4 SEVT channel + * This parameter can be one of the following values: + * @arg TMR4_SEVT_UH: TMR4 SEVT channel - UH + * @arg TMR4_SEVT_UL: TMR4 SEVT channel - UL + * @arg TMR4_SEVT_VH: TMR4 SEVT channel - VH + * @arg TMR4_SEVT_VL: TMR4 SEVT channel - VL + * @arg TMR4_SEVT_WH: TMR4 SEVT channel - WH + * @arg TMR4_SEVT_WL: TMR4 SEVT channel - WL + * @retval Returned value can be one of the following values: + * @arg TMR4_SEVT_MASK_0: Mask 0 times + * @arg TMR4_SEVT_MASK_1: Mask 1 times + * @arg TMR4_SEVT_MASK_2: Mask 2 times + * @arg TMR4_SEVT_MASK_3: Mask 3 times + * @arg TMR4_SEVT_MASK_4: Mask 4 times + * @arg TMR4_SEVT_MASK_5: Mask 5 times + * @arg TMR4_SEVT_MASK_6: Mask 6 times + * @arg TMR4_SEVT_MASK_7: Mask 7 times + * @arg TMR4_SEVT_MASK_8: Mask 8 times + * @arg TMR4_SEVT_MASK_9: Mask 9 times + * @arg TMR4_SEVT_MASK_10: Mask 10 times + * @arg TMR4_SEVT_MASK_11: Mask 11 times + * @arg TMR4_SEVT_MASK_12: Mask 12 times + * @arg TMR4_SEVT_MASK_13: Mask 13 times + * @arg TMR4_SEVT_MASK_14: Mask 14 times + * @arg TMR4_SEVT_MASK_15: Mask 15 times + */ +uint16_t TMR4_SEVT_GetMaskTimes(const M4_TMR4_TypeDef *TMR4x, + uint32_t u32Ch) +{ + __IO uint16_t *TMR4_SCMR; + + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_CH(u32Ch)); + + /* Get actual address of register list of current channel */ + TMR4_SCMR = TMR4_SCMRx(TMR4x, u32Ch); + + return READ_REG16_BIT(*TMR4_SCMR, TMR4_SCMR_AMC); +} + +/** + * @brief Set TMR4 SEVT event signal output to port + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @param [in] u16EvtSignal TMR4 SEVT event signal selection + * This parameter can be one of the following values: + * @arg TMR4_SEVT_PORT_OUTPUT_NONE: Disable output event signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT0_SIGNAL: Output the specified event 0 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT1_SIGNAL: Output the specified event 1 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT2_SIGNAL: Output the specified event 2 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT3_SIGNAL: Output the specified event 3 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT4_SIGNAL: Output the specified event 4 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT5_SIGNAL: Output the specified event 5 signal of TMR4 Special-EVT + * @retval None + */ +void TMR4_SEVT_SetPortOutputEventSig(M4_TMR4_TypeDef *TMR4x, + uint16_t u16EvtSignal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + DDL_ASSERT(IS_VALID_TMR4_SEVT_PORT_OUTPUT_SIGNAL(u16EvtSignal)); + + MODIFY_REG16(TMR4x->SCER, TMR4_SCER_EVTRS, u16EvtSignal); +} + +/** + * @brief Get TMR4 SEVT event signal output to port + * @param [in] TMR4x Pointer to TMR4 instance register base + * This parameter can be one of the following values: + * @arg M4_TMR4_1: TMR4 unit 1 instance register base + * @arg M4_TMR4_2: TMR4 unit 2 instance register base + * @arg M4_TMR4_3: TMR4 unit 3 instance register base + * @retval Returned value can be one of the following values: + * @arg TMR4_SEVT_PORT_OUTPUT_NONE: Disable output event signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT0_SIGNAL: Output the specified event 0 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT1_SIGNAL: Output the specified event 1 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT2_SIGNAL: Output the specified event 2 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT3_SIGNAL: Output the specified event 3 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT4_SIGNAL: Output the specified event 4 signal of TMR4 Special-EVT + * @arg TMR4_SEVT_PORT_OUTPUT_EVENT5_SIGNAL: Output the specified event 5 signal of TMR4 Special-EVT + */ +uint16_t TMR4_SEVT_GetPortOutputEventSig(const M4_TMR4_TypeDef *TMR4x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR4_INSTANCE(TMR4x)); + + return READ_REG16_BIT(TMR4x->SCER, TMR4_SCER_EVTRS); +} + +/** + * @} + */ + +/** + * @} + */ + +#endif /* DDL_TMR4_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr6.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr6.c new file mode 100644 index 0000000000000000000000000000000000000000..0d1a83d4851ae2698b488b4a8b2b7408dd23f119 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr6.c @@ -0,0 +1,2325 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmr6.c + * @brief This file provides firmware functions to manage the TMR6 (TMR6). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wangmin First version + 2020-07-15 Wangmin Refine macro define + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_tmr6.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_TMR6 TMR6 + * @brief TMR6 Driver Library + * @{ + */ + +#if (DDL_TMR6_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMR6_Local_Macros TMR6 Local Macros + * @{ + */ + +/* Timer6 registers reset value */ +#define TMR6_REG_REFERENCE_RESET_VALUE_U32 (0xFFFFFFFFUL) +#define TMR6_REG_REFERENCE_RESET_VALUE_U16 (0xFFFFU) +#define TMR6_REG_GCONR_RESET_VALUE (0x00000100UL) + +/* Define for BCONR register configuration */ +#define BCONR_REG_CFG_MSK (0x0000000FUL) +#define BCONR_GEN_BUF_CHA_OFFSET (0x00UL) +#define BCONR_GEN_BUF_CHB_OFFSET (0x04UL) +#define BCONR_PERIOD_BUF_OFFSET (0x08UL) +#define BCONR_SPECIAL_BUF_CHA_OFFSET (0x10UL) +#define BCONR_SPECIAL_BUF_CHB_OFFSET (0x14UL) + +/* Define mask value for port output configuration for PCNAR/PCNBR register */ +#define PCNA_BR_REG_OUTPUT_CFG_MASK (0x9003FFFFUL) +#define PCNA_BR_REG_EMB_CFG_MASK (TMR6_PCNAR_EMBSA | TMR6_PCNAR_EMBRA | TMR6_PCNAR_EMBCA) +/* Define mask value for GCONR register */ +#define TMR6_INITIAL_MASK (TMR6_GCONR_DIR | TMR6_GCONR_MODE | TMR6_GCONR_CKDIV | TMR6_GCONR_OVSTP) +#define TMR6_ZMASK_CFG_MASK (TMR6_GCONR_ZMSKVAL | TMR6_GCONR_ZMSKPOS | TMR6_GCONR_ZMSKREV) + +#define TMR6_HW_CTRL_EVENT_MASK (TMR6_HW_CTRL_PWMA_RISING | \ + TMR6_HW_CTRL_PWMA_FAILLING | \ + TMR6_HW_CTRL_PWMB_RISING | \ + TMR6_HW_CTRL_PWMB_FAILLING | \ + TMR6_HW_CTRL_INTER_EVENT0 | \ + TMR6_HW_CTRL_INTER_EVENT1 | \ + TMR6_HW_CTRL_INTER_EVENT2 | \ + TMR6_HW_CTRL_INTER_EVENT3 | \ + TMR6_HW_CTRL_TRIGEA_RISING | \ + TMR6_HW_CTRL_TRIGEA_FAILLING | \ + TMR6_HW_CTRL_TRIGEB_RISING | \ + TMR6_HW_CTRL_TRIGEB_FAILLING | \ + TMR6_HW_CTRL_TRIGEC_RISING | \ + TMR6_HW_CTRL_TRIGEC_FAILLING | \ + TMR6_HW_CTRL_TRIGED_RISING | \ + TMR6_HW_CTRL_TRIGED_FAILLING) + +#define TMR6_HW_CNT_EVENT_MASK (TMR6_HW_CNT_PWMAL_PWMBRISING | \ + TMR6_HW_CNT_PWMAL_PWMBFAILLING | \ + TMR6_HW_CNT_PWMAH_PWMBRISING | \ + TMR6_HW_CNT_PWMAH_PWMBFAILLING | \ + TMR6_HW_CNT_PWMBL_PWMARISING | \ + TMR6_HW_CNT_PWMBL_PWMAFAILLING | \ + TMR6_HW_CNT_PWMBH_PWMARISING | \ + TMR6_HW_CNT_PWMBH_PWMAFAILLING | \ + TMR6_HW_CNT_INTER_EVENT0 | \ + TMR6_HW_CNT_INTER_EVENT1 | \ + TMR6_HW_CNT_INTER_EVENT2 | \ + TMR6_HW_CNT_INTER_EVENT3 | \ + TMR6_HW_CNT_TRIGEA_RISING | \ + TMR6_HW_CNT_TRIGEA_FAILLING | \ + TMR6_HW_CNT_TRIGEB_RISING | \ + TMR6_HW_CNT_TRIGEB_FAILLING | \ + TMR6_HW_CNT_TRIGEC_RISING | \ + TMR6_HW_CNT_TRIGEC_FAILLING | \ + TMR6_HW_CNT_TRIGED_RISING | \ + TMR6_HW_CNT_TRIGED_FAILLING) + +#define TMR6_IRQ_EN_MASK (TMR6_IRQ_EN_CNT_MATCH_A | \ + TMR6_IRQ_EN_CNT_MATCH_B | \ + TMR6_IRQ_EN_CNT_MATCH_C | \ + TMR6_IRQ_EN_CNT_MATCH_D | \ + TMR6_IRQ_EN_CNT_MATCH_E | \ + TMR6_IRQ_EN_CNT_MATCH_F | \ + TMR6_IRQ_EN_OVERFLOW | \ + TMR6_IRQ_EN_UNDERFLOW | \ + TMR6_IRQ_EN_DEAD_TIME_ERR | \ + TMR6_IRQ_EN_UPCNT_SP_MATCH_A | \ + TMR6_IRQ_EN_DOWNCNT_SP_MATCH_A | \ + TMR6_IRQ_EN_UPCNT_SP_MATCH_B | \ + TMR6_IRQ_EN_DOWNCNT_SP_MATCH_B) + +#define TMR6_STAT_FLAG_MASK (TMR6_STAT_CNT_MATCH_A | \ + TMR6_STAT_CNT_MATCH_B | \ + TMR6_STAT_CNT_MATCH_C | \ + TMR6_STAT_CNT_MATCH_D | \ + TMR6_STAT_CNT_MATCH_E | \ + TMR6_STAT_CNT_MATCH_F | \ + TMR6_STAT_OVERFLOW | \ + TMR6_STAT_UNDERFLOW | \ + TMR6_STAT_DEAD_TIME_ERR | \ + TMR6_STAT_UPCNT_SP_MATCH_A | \ + TMR6_STAT_DOWNCNT_SP_MATCH_A | \ + TMR6_STAT_UPCNT_SP_MATCH_B | \ + TMR6_STAT_DOWNCNT_SP_MATCH_B | \ + TMR6_STAT_CNT_DIR) + +#define TMR6_SW_CTRL_REG_MASK (TMR6_SSTAR_SSTA1 | \ + TMR6_SSTAR_SSTA2 | \ + TMR6_SSTAR_SSTA3 | \ + TMR6_SSTAR_SSTA4 | \ + TMR6_SSTAR_SSTA5 | \ + TMR6_SSTAR_SSTA6 | \ + TMR6_SSTAR_SSTA7 | \ + TMR6_SSTAR_SSTA8) + + + + +/** + * @defgroup TMR6_Check_Parameters_Validity TMR6 Check Parameters Validity + * @{ + */ + +/*! Parameter valid check for normal timer6 unit */ +#define IS_VALID_TMR6_UNIT(__TMR6x__) \ +( (M4_TMR6_1 == (__TMR6x__)) || \ + (M4_TMR6_2 == (__TMR6x__)) || \ + (M4_TMR6_3 == (__TMR6x__)) || \ + (M4_TMR6_4 == (__TMR6x__)) || \ + (M4_TMR6_5 == (__TMR6x__)) || \ + (M4_TMR6_6 == (__TMR6x__)) || \ + (M4_TMR6_7 == (__TMR6x__)) || \ + (M4_TMR6_8 == (__TMR6x__))) + +/*! Parameter valid check for interrupt source configuration */ +#define IS_VALID_IRQ_SOURCE_CONFIG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_IRQ_EN_MASK) == TMR6_IRQ_EN_MASK)) + +/*! Parameter valid check for status bit read */ +#define IS_VALID_STABIT_GET(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_STAT_FLAG_MASK) == TMR6_STAT_FLAG_MASK)) + +/*! Parameter valid check for period register */ +#define IS_VALID_PERIOD_REG(x) \ +( (TMR6_PERIOD_REG_A == (x)) || \ + (TMR6_PERIOD_REG_B == (x)) || \ + (TMR6_PERIOD_REG_C == (x))) + +/*! Parameter valid check for general compare register */ +#define IS_VALID_CMP_REG(x) \ +( (TMR6_CMP_REG_A == (x)) || \ + (TMR6_CMP_REG_B == (x)) || \ + (TMR6_CMP_REG_C == (x)) || \ + (TMR6_CMP_REG_D == (x)) || \ + (TMR6_CMP_REG_E == (x)) || \ + (TMR6_CMP_REG_F == (x))) + +/*! Parameter valid check for general/special compare channel */ +#define IS_VALID_CMP_CH(x) \ +( (TMR6_CH_A == (x)) || \ + (TMR6_CH_B == (x))) + +/*! Parameter valid check for buffer function status */ +#define IS_VALID_BUF_STAT(x) \ +( (TMR6_BUF_FUNC_OFF == (x)) || \ + (TMR6_BUF_FUNC_ON == (x))) + +/*! Parameter valid check for buffer function number */ +#define IS_VALID_BUF_FUN_NUM(x) \ +( (TMR6_BUF_FUNC_SINGLE == (x)) || \ + (TMR6_BUF_FUNC_DOUBLE == (x))) + +/*! Parameter valid check for buffer transfer timer configuration */ +#define IS_VALID_BUF_TRANS_TIM(x) \ +( (TMR6_BUF_TRANS_TIM_NONE == (x)) || \ + (TMR6_BUF_TRANS_TIM_OVERFLOW == (x)) || \ + (TMR6_BUF_TRANS_TIM_UNDERFLOW == (x))|| \ + (TMR6_BUF_TRANS_TIM_BOTH == (x))) + +/*! Parameter valid check for valid period function status for channel A */ +#define IS_VALID_VALID_PERIOD_STAT_CHA(x) \ +( (TMR6_VALID_PERIOD_FUNC_CHA_OFF == (x)) || \ + (TMR6_VALID_PERIOD_FUNC_CHA_ON == (x))) + +/*! Parameter valid check for valid period function status for channel B */ +#define IS_VALID_VALID_PERIOD_STAT_CHB(x) \ +( (TMR6_VALID_PERIOD_FUNC_CHB_OFF == (x)) || \ + (TMR6_VALID_PERIOD_FUNC_CHB_ON == (x))) + +/*! Parameter valid check for count condition for valid period function */ +#define IS_VALID_PERIOD_CNT_COND(x) \ +( (TMR6_VALID_PERIOD_FUNC_OFF == (x)) || \ + (TMR6_VALID_PERIOD_CNT_COND_UNDERFLOW == (x)) || \ + (TMR6_VALID_PERIOD_CNT_COND_OVERFLOW == (x)) || \ + (TMR6_VALID_PERIOD_CNT_COND_BOTH == (x))) + +/*! Parameter valid check for count condition for valid period count */ +#define IS_VALID_PERIOD_CNT(x) \ +( (TMR6_VALID_PERIOD_CNT_INVALID == (x)) || \ + (TMR6_VALID_PERIOD_CNT_1 == (x)) || \ + (TMR6_VALID_PERIOD_CNT_2 == (x)) || \ + (TMR6_VALID_PERIOD_CNT_3 == (x)) || \ + (TMR6_VALID_PERIOD_CNT_4 == (x)) || \ + (TMR6_VALID_PERIOD_CNT_5 == (x)) || \ + (TMR6_VALID_PERIOD_CNT_6 == (x)) || \ + (TMR6_VALID_PERIOD_CNT_7 == (x))) + +/*! Parameter valid check for count register data range */ +#define IS_VALID_REG_RANGE_U16(x) ((x) <= 0xFFFFUL) + +/*! Parameter valid check for dead time register */ +#define IS_VALID_DEADTIME_REG(x) \ +( (TMR6_DEADTIME_REG_UP_A == (x)) || \ + (TMR6_DEADTIME_REG_DOWN_A == (x)) || \ + (TMR6_DEADTIME_REG_UP_B == (x)) || \ + (TMR6_DEADTIME_REG_DOWN_B == (x))) + +/*! Parameter valid check for input port */ +#define IS_VALID_INPUT_PORT(x) \ +( (TMR6_IO_PWMA == (x)) || \ + (TMR6_IO_PWMB == (x)) || \ + (TMR6_INPUT_TRIGA == (x)) || \ + (TMR6_INPUT_TRIGB == (x)) || \ + (TMR6_INPUT_TRIGC == (x)) || \ + (TMR6_INPUT_TRIGD == (x))) + +/*! Parameter valid check for output port */ +#define IS_VALID_OUTPUT_PORT(x) \ +( (TMR6_IO_PWMA == (x)) || \ + (TMR6_IO_PWMB == (x))) + +/*! Parameter valid check for input port filter clock */ +#define IS_VALID_INPUT_FILTER_CLK(x) \ +( (TMR6_INPUT_FILTER_PCLK0_DIV1 == (x)) || \ + (TMR6_INPUT_FILTER_PCLK0_DIV4 == (x)) || \ + (TMR6_INPUT_FILTER_PCLK0_DIV16 == (x)) || \ + (TMR6_INPUT_FILTER_PCLK0_DIV64 == (x))) + +/*! Parameter valid check for port function mode*/ +#define IS_VALID_PORT_MODE_FUNC(x) \ +( (TMR6_PORT_COMPARE_OUTPUT == (x)) || \ + (TMR6_PORT_CAPTURE_INPUT == (x))) + +/*! Parameter valid check for port input filter function status */ +#define IS_VALID_PORT_INPUT_FILTER_STA(x) \ +( (TMR6_PORT_INPUT_FILTER_OFF == (x)) || \ + (TMR6_PORT_INPUT_FILTER_ON == (x))) + +/*! Parameter valid check for output port status for count result */ +#define IS_VALID_OUTPUT_STA_RESULT(x) \ +( (TMR6_PORT_OUTPUT_STA_LOW == (x)) || \ + (TMR6_PORT_OUTPUT_STA_HIGH == (x)) || \ + (TMR6_PORT_OUTPUT_STA_HOLD == (x)) || \ + (TMR6_PORT_OUTPUT_STA_REVERSE == (x))) + +/*! Parameter valid check for force output port status for count result */ +#define IS_VALID_FORCE_OUTPUT_STA_RESULT(x) \ +( (TMR6_FORCE_PORT_OUTPUT_INVALID == (x)) || \ + (TMR6_FORCE_PORT_OUTPUT_STA_LOW == (x)) || \ + (TMR6_FORCE_PORT_OUTPUT_STA_HIGH == (x))) + +/*! Parameter valid check for output port status for count status */ +#define IS_VALID_OUTPUT_STA_STA(x) \ +( (TMR6_PORT_OUTPUT_STA_LOW == (x)) || \ + (TMR6_PORT_OUTPUT_STA_HIGH == (x)) || \ + (TMR6_PORT_OUTPUT_STA_HOLD == (x))) + +/*! Parameter valid check for EMB event valid channel */ +#define IS_VALID_EMB_CH(x) \ +( (TMR6_EMB_EVENT_VALID_CH0 == (x)) || \ + (TMR6_EMB_EVENT_VALID_CH1 == (x)) || \ + (TMR6_EMB_EVENT_VALID_CH2 == (x)) || \ + (TMR6_EMB_EVENT_VALID_CH3 == (x))) + +/*! Parameter valid check for EMB release mode when EMB event invalid */ +#define IS_VALID_EMB_RELEASE_MODE(x) \ +( (TMR6_EMB_RELEASE_IMMEDIATE == (x)) || \ + (TMR6_EMB_RELEASE_OVERFLOW == (x)) || \ + (TMR6_EMB_RELEASE_UNDERFLOW == (x)) || \ + (TMR6_EMB_RELEASE_OVERFLOW_UNDERFLOW == (x))) + +/*! Parameter valid check for port output status when EMB event valid */ +#define IS_VALID_EMB_VALID_PORT_STA(x) \ +( (TMR6_EMB_PORTSTA_NORMAL == (x)) || \ + (TMR6_EMB_PORTSTA_HIZ == (x)) || \ + (TMR6_EMB_PORTSTA_LOW == (x)) || \ + (TMR6_EMB_PORTSTA_HIGH == (x))) + +/*! Parameter valid check for dead time buffer function for DTUAR and DTUBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(x) \ +( (TMR6_DEADTIME_CNT_UP_BUF_OFF == (x)) || \ + (TMR6_DEADTIME_CNT_UP_BUF_ON == (x))) + +/*! Parameter valid check for dead time buffer function for DTDAR and DTDBR register */ +#define IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(x) \ +( (TMR6_DEADTIME_CNT_DOWN_BUF_OFF == (x)) || \ + (TMR6_DEADTIME_CNT_DOWN_BUF_ON == (x))) + +/*! Parameter valid check for dead time buffer transfer condition */ +#define IS_VALID_DEADTIME_BUF_TRANS_COND_REG(x) \ +( (TMR6_DEADTIME_TRANS_COND_NONE == (x)) || \ + (TMR6_DEADTIME_TRANS_COND_OVERFLOW == (x)) || \ + (TMR6_DEADTIME_TRANS_COND_UNDERFLOW == (x)) || \ + (TMR6_DEADTIME_TRANS_COND_BOTH == (x))) + +/*! Parameter valid check for dead time equal function for DTUAR and DTDAR register */ +#define IS_VALID_DEADTIME_EQUAL_FUNC_REG(x) \ +( (TMR6_DEADTIME_EQUAL_OFF == (x)) || \ + (TMR6_DEADTIME_EQUAL_ON == (x))) + +/*! Parameter valid check for hardware control events */ +#define IS_VALID_HW_CTRL_EVENTS(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_HW_CTRL_EVENT_MASK) == TMR6_HW_CTRL_EVENT_MASK)) + +/*! Parameter valid check for hardware count events */ +#define IS_VALID_HW_CNT_EVENTS(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_HW_CNT_EVENT_MASK) == TMR6_HW_CNT_EVENT_MASK)) + +/*! Parameter valid check for count Mode */ +#define IS_VALID_CNT_MODE(x) \ +( (TMR6_MODE_SAWTOOTH == (x)) || \ + (TMR6_MODE_TRIANGLE == (x))) + +/*! Parameter valid check for count direction */ +#define IS_VALID_CNT_DIRECTION(x) \ +( (TMR6_CNT_INCREASE == (x)) || \ + (TMR6_CNT_DECREASE == (x))) + +/*! Parameter valid check for count clock source */ +#define IS_VALID_CNT_CLK_SRC(x) \ +( (TMR6_CLK_PCLK0_DIV1 == (x)) || \ + (TMR6_CLK_PCLK0_DIV2 == (x)) || \ + (TMR6_CLK_PCLK0_DIV4 == (x)) || \ + (TMR6_CLK_PCLK0_DIV8 == (x)) || \ + (TMR6_CLK_PCLK0_DIV16 == (x)) || \ + (TMR6_CLK_PCLK0_DIV32 == (x)) || \ + (TMR6_CLK_PCLK0_DIV64 == (x)) || \ + (TMR6_CLK_PCLK0_DIV128 == (x)) || \ + (TMR6_CLK_PCLK0_DIV256 == (x)) || \ + (TMR6_CLK_PCLK0_DIV512 == (x)) || \ + (TMR6_CLK_PCLK0_DIV1024 == (x))) + +/*! Parameter valid check for stop when overflow mode */ +#define IS_VALID_STOP_AFTER_OVF_MODE(x) \ +( (TMR6_CNT_CONTINUOUS == (x)) || \ + (TMR6_STOP_AFTER_OVF == (x))) + +/*! Parameter valid check for Z Mask input function mask cycles number */ +#define IS_VALID_ZMASK_CYCLES(x) \ +( (TMR6_ZMASK_CYCLE_FUNC_INVALID == (x)) || \ + (TMR6_ZMASK_CYCLE_4 == (x)) || \ + (TMR6_ZMASK_CYCLE_8 == (x)) || \ + (TMR6_ZMASK_CYCLE_16 == (x))) + +/*! Parameter valid check for Z Mask function of timer6 position unit */ +#define IS_VALID_POS_UNIT_ZMASK_FUNC(x) \ +( (TMR6_POS_CLR_ZMASK_FUNC_INVALID == (x)) || \ + (TMR6_POS_CLR_ZMASK_FUNC_VALID == (x))) + +/*! Parameter valid check for Z Mask function of timer6 revolution unit */ +#define IS_VALID_REVO_UNIT_ZMASK_FUNC(x) \ +( (TMR6_REVO_CNT_ZMASK_FUNC_INVALID == (x)) || \ + (TMR6_REVO_CNT_ZMASK_FUNC_VALID == (x))) + +/*! Parameter valid check for hardware trigger index */ +#define IS_VALID_HW_TRIGGER_INDEX(x) \ +( (TMR6_HW_TRIG_0 == (x)) || \ + (TMR6_HW_TRIG_1 == (x)) || \ + (TMR6_HW_TRIG_2 == (x)) || \ + (TMR6_HW_TRIG_3 == (x))) + +/*! Parameter valid check for software sync control unit configuration */ +#define IS_VALID_SW_CTRL_CFG(x) \ +( ((x) != 0UL) && \ + (((x) | TMR6_SW_CTRL_REG_MASK) == TMR6_SW_CTRL_REG_MASK)) + +/*! Parameter valid check for common trigger configuration. */ +#define IS_VALID_TMR6_COM_TRIG(x) \ +( ((x) != 0x00UL) && \ + (((x) | TMR6_COM_TRIG_MASK) == TMR6_COM_TRIG_MASK)) + +/* Unit check for TMR6 which data width is 32 bit */ +#define IS_TMR6_32BIT_UINT(x) \ +( (M4_TMR6_1 == (x)) || \ + (M4_TMR6_2 == (x)) || \ + (M4_TMR6_3 == (x)) || \ + (M4_TMR6_4 == (x))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + * @defgroup TMR6_Global_Functions TMR6 Global Functions + * @{ + */ + +/** + * @brief Timer6 interrupt request enable or disable + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32Tmr6Irq Irq source, Can be one or any combination of + * the values from @ref TMR6_Interrupt_Enable_Bit_Define + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR6_IntCmd(M4_TMR6_TypeDef *TMR6x, uint32_t u32Tmr6Irq, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_IRQ_SOURCE_CONFIG(u32Tmr6Irq)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(TMR6x->ICONR, u32Tmr6Irq); + } + else + { + CLEAR_REG32_BIT(TMR6x->ICONR, u32Tmr6Irq); + } +} + +/** + * @brief Get Timer6 status flag + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32StaBit Status bit to be read, Can be one or any combination of + * the values from @ref TMR6_Sta_Bit_Get_Define + * @retval An en_flag_status_t enumeration value. + * @arg Set: Status bit is set + * @arg Reset: Status bit is reset + */ +en_flag_status_t TMR6_GetSta(const M4_TMR6_TypeDef *TMR6x, uint32_t u32StaBit) +{ + en_flag_status_t enRet = Reset; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_STABIT_GET(u32StaBit)); + + if(0UL != READ_REG32_BIT(TMR6x->STFLR, u32StaBit)) + { + enRet = Set; + } + return enRet; +} + +/** + * @brief Get Timer6 period number when valid period function enable + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval A uint32_t data for periods number + */ +uint32_t TMR6_GetPeriodNum(const M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return (READ_REG32_BIT(TMR6x->STFLR, TMR6_STFLR_VPERNUM) >> TMR6_STFLR_VPERNUM_POS); +} + +/** + * @brief De-initialize the timer6 unit + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_DeInit(M4_TMR6_TypeDef *TMR6x) +{ + uint32_t u32RefRegRstValue; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + u32RefRegRstValue = TMR6_REG_REFERENCE_RESET_VALUE_U32; + } + else + { + u32RefRegRstValue = TMR6_REG_REFERENCE_RESET_VALUE_U16; + } + + WRITE_REG32(TMR6x->GCONR, TMR6_REG_GCONR_RESET_VALUE); + WRITE_REG32(TMR6x->CNTER, 0x00000000UL); + WRITE_REG32(TMR6x->UPDAR, 0x00000000UL); + WRITE_REG32(TMR6x->PERAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->PERBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->PERCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMDR, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMER, u32RefRegRstValue); + WRITE_REG32(TMR6x->GCMFR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMCR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMDR, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMER, u32RefRegRstValue); + WRITE_REG32(TMR6x->SCMFR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTUAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTDAR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTUBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->DTDBR, u32RefRegRstValue); + WRITE_REG32(TMR6x->ICONR, 0x00000000UL); + WRITE_REG32(TMR6x->BCONR, 0x00000000UL); + WRITE_REG32(TMR6x->DCONR, 0x00000000UL); + WRITE_REG32(TMR6x->PCNAR, 0x00000000UL); + WRITE_REG32(TMR6x->PCNBR, 0x00000000UL); + WRITE_REG32(TMR6x->FCNGR, 0x00000000UL); + WRITE_REG32(TMR6x->VPERR, 0x00000000UL); + WRITE_REG32(TMR6x->STFLR, 0x00000000UL); + WRITE_REG32(TMR6x->HSTAR, 0x00000000UL); + WRITE_REG32(TMR6x->HSTPR, 0x00000000UL); + WRITE_REG32(TMR6x->HCLRR, 0x00000000UL); + WRITE_REG32(TMR6x->HUPDR, 0x00000000UL); + WRITE_REG32(TMR6x->HCPAR, 0x00000000UL); + WRITE_REG32(TMR6x->HCPBR, 0x00000000UL); + WRITE_REG32(TMR6x->HCUPR, 0x00000000UL); + WRITE_REG32(TMR6x->HCDOR, 0x00000000UL); +} + +/** + * @brief Initialize the timer6 unit + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] pstcTmr6BaseCntCfg Pointer of configuration structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_Init(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_basecnt_cfg_t* pstcTmr6BaseCntCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if(NULL != pstcTmr6BaseCntCfg) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_CNT_MODE(pstcTmr6BaseCntCfg->u32CntMode)); + DDL_ASSERT(IS_VALID_CNT_DIRECTION(pstcTmr6BaseCntCfg->u32CntDir)); + DDL_ASSERT(IS_VALID_CNT_CLK_SRC(pstcTmr6BaseCntCfg->u32CntClkDiv)); + DDL_ASSERT(IS_VALID_STOP_AFTER_OVF_MODE(pstcTmr6BaseCntCfg->u32CntStpAftOvf)); + + MODIFY_REG32(TMR6x->GCONR, + TMR6_INITIAL_MASK, + (pstcTmr6BaseCntCfg->u32CntMode \ + | pstcTmr6BaseCntCfg->u32CntDir \ + | pstcTmr6BaseCntCfg->u32CntClkDiv \ + | pstcTmr6BaseCntCfg->u32CntStpAftOvf)); + enRet = Ok; + } + return enRet; +} + +/** + * @brief Timer6 unit Z phase input mask config + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] pstcTmr6ZMaskCfg Pointer of configuration structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_ZMaskCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_zmask_cfg_t* pstcTmr6ZMaskCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if(NULL != pstcTmr6ZMaskCfg) + { + DDL_ASSERT(IS_VALID_ZMASK_CYCLES(pstcTmr6ZMaskCfg->u32ZMaskCycle)); + DDL_ASSERT(IS_VALID_POS_UNIT_ZMASK_FUNC(pstcTmr6ZMaskCfg->u32PosCntMaskEn)); + DDL_ASSERT(IS_VALID_REVO_UNIT_ZMASK_FUNC(pstcTmr6ZMaskCfg->u32RevCntMaskEn)); + + MODIFY_REG32(TMR6x->GCONR, + TMR6_ZMASK_CFG_MASK, + pstcTmr6ZMaskCfg->u32ZMaskCycle | pstcTmr6ZMaskCfg->u32PosCntMaskEn | pstcTmr6ZMaskCfg->u32RevCntMaskEn); + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Timer6 counter function command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR6_CountCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); + } + else + { + CLEAR_REG32_BIT(TMR6x->GCONR, TMR6_GCONR_START); + } +} + +/** + * @brief Timer6 counter register set + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetCntReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + WRITE_REG32(TMR6x->CNTER, u32Value); + } + else + { + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(TMR6x->CNTER, u32Value); + } + +} + +/** + * @brief Timer6 update register set + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32Value Counter value + * @retval None + */ +void TMR6_SetUpdateReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32Value) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + WRITE_REG32(TMR6x->UPDAR, u32Value); + } + else + { + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32Value)); + WRITE_REG16(TMR6x->UPDAR, u32Value); + } +} + +/** + * @brief Timer6 get counter register value + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval A uint32_t data for the count register value + */ +uint32_t TMR6_GetCntReg(const M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->CNTER); +} + +/** + * @brief Timer6 get update register value + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval A uint32_t data for register value + */ +uint32_t TMR6_GetUpdateReg(const M4_TMR6_TypeDef *TMR6x) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + return READ_REG32(TMR6x->UPDAR); +} + +/** + * @brief Timer6 set period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32PeriodReg Period register to be write, @ref TMR6_Period_Register_Index_Define + * @param [in] u32PeriodVal Period value for write + * @retval None + */ +void TMR6_SetPeriodReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32PeriodReg, uint32_t u32PeriodVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32PeriodReg)); + __IO uint32_t *TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32PeriodReg); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + /* 32bit */ + WRITE_REG32(*TMR6_PERxR, u32PeriodVal); + } + else + { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32PeriodVal)); + WRITE_REG16(*TMR6_PERxR, u32PeriodVal); + } +} + +/** + * @brief Timer6 set general compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32GenCmpReg General compare register to be write, @ref TMR6_Compare_Register_Index_Define + * @param [in] u32CmpVal Value for write + * @retval None + */ +void TMR6_SetGenCmpReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32GenCmpReg, uint32_t u32CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32GenCmpReg)); + __IO uint32_t *TMR6_GCMxR = (__IO uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32GenCmpReg); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + /* 32bit */ + WRITE_REG32(*TMR6_GCMxR ,u32CmpVal); + } + else + { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32CmpVal)); + WRITE_REG16(*TMR6_GCMxR ,u32CmpVal); + } +} + +/** + * @brief Timer6 set special compare register(A~F) + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32SpecialCmpReg Special compare register to be write, @ref TMR6_Compare_Register_Index_Define + * @param [in] u32CmpVal Value for write + * @retval None + */ +void TMR6_SetSpecialCmpReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32SpecialCmpReg, uint32_t u32CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32SpecialCmpReg)); + __IO uint32_t *TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32SpecialCmpReg); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + /* 32bit */ + WRITE_REG32(*TMR6_SCMxR, u32CmpVal); + } + else + { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32CmpVal)); + WRITE_REG16(*TMR6_SCMxR, u32CmpVal); + } +} + +/** + * @brief Timer6 set dead time registerr + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32DeadTimeReg Special compare register to be write, @ref TMR6_DeadTime_Reg_Define + * @param [in] u32CmpVal Value for write + * @retval None + */ +void TMR6_SetDeadTimeReg(M4_TMR6_TypeDef *TMR6x, uint32_t u32DeadTimeReg, uint32_t u32CmpVal) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32DeadTimeReg)); + __IO uint32_t *TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32DeadTimeReg); + + if(IS_TMR6_32BIT_UINT(TMR6x)) + { + /* 32bit */ + WRITE_REG32(*TMR6_DTxyR, u32CmpVal); + } + else + { + /* 16bit */ + DDL_ASSERT(IS_VALID_REG_RANGE_U16(u32CmpVal)); + WRITE_REG16(*TMR6_DTxyR, u32CmpVal); + } +} + +/** + * @brief Timer6 get general compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32GenCmpReg General compare register to be read, @ref TMR6_Compare_Register_Index_Define + * @retval A uint32_t data for value of the register + */ +uint32_t TMR6_GetGenCmpReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32GenCmpReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32GenCmpReg)); + __IO uint32_t *TMR6_GCMxR = (uint32_t *)((uint32_t)&TMR6x->GCMAR + 4UL * u32GenCmpReg); + + return READ_REG32(*TMR6_GCMxR); +} + +/** + * @brief Timer6 get special compare registers value(A~F) + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32SpecialCmpReg Special compare register to be read, @ref TMR6_Compare_Register_Index_Define + * @retval A uint32_t data for value of the register + */ +uint32_t TMR6_GetSpecialCmpReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32SpecialCmpReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_REG(u32SpecialCmpReg)); + __IO uint32_t *TMR6_SCMxR = (uint32_t *)((uint32_t)&TMR6x->SCMAR + 4UL * u32SpecialCmpReg); + + return READ_REG32(*TMR6_SCMxR); +} + +/** + * @brief Timer6 Get period register(A~C) + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32PeriodReg Period register to be write, @ref TMR6_Period_Register_Index_Define + * @retval A uint32_t data for value of the register + */ +uint32_t TMR6_GetPeriodReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32PeriodReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_PERIOD_REG(u32PeriodReg)); + __IO uint32_t *TMR6_PERxR = (uint32_t *)((uint32_t)&TMR6x->PERAR + 4UL * u32PeriodReg); + + return READ_REG32(*TMR6_PERxR); +} + +/** + * @brief Timer6 get dead time register + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32DeadTimeReg Dead time register to be write, @ref TMR6_DeadTime_Reg_Define + * @retval A uint32_t data for value of the register + */ +uint32_t TMR6_GetDeadTimeReg(const M4_TMR6_TypeDef *TMR6x, uint32_t u32DeadTimeReg) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_DEADTIME_REG(u32DeadTimeReg)); + __IO uint32_t *TMR6_DTxyR = (uint32_t *)((uint32_t)&TMR6x->DTUAR + 4UL * u32DeadTimeReg); + + return READ_REG32(*TMR6_DTxyR); +} + +/** + * @brief Timer6 general compare buffer function configuration + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CmpChIdx General compare buffer chose, @ref TMR6_Compare_channel_Define + * @param [in] pstcGenBufCfg Pointer of configuration structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_GenCmpBufCfg(M4_TMR6_TypeDef *TMR6x, uint32_t u32CmpChIdx, const stc_tmr6_buf_func_cfg_t* pstcGenBufCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + if(NULL != pstcGenBufCfg) + { + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_CMP_CH(u32CmpChIdx)); + DDL_ASSERT(IS_VALID_BUF_STAT(pstcGenBufCfg->u32BufFunCmd)); + DDL_ASSERT(IS_VALID_BUF_FUN_NUM(pstcGenBufCfg->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TIM(pstcGenBufCfg->u32BufTransTim)); + + if(TMR6_CH_A == u32CmpChIdx) + { + MODIFY_REG32(TMR6x->BCONR, + BCONR_REG_CFG_MSK<u32BufFunCmd | pstcGenBufCfg->u32BufNum | pstcGenBufCfg->u32BufTransTim)<BCONR, + BCONR_REG_CFG_MSK<u32BufFunCmd | pstcGenBufCfg->u32BufNum | pstcGenBufCfg->u32BufTransTim)<u32BufFunCmd)); + DDL_ASSERT(IS_VALID_BUF_FUN_NUM(pstcSpecialBufCfg->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TIM(pstcSpecialBufCfg->u32BufTransTim)); + + if(TMR6_CH_A == u32CmpChIdx) + { + MODIFY_REG32(TMR6x->BCONR, + BCONR_REG_CFG_MSK<u32BufFunCmd | pstcSpecialBufCfg->u32BufNum | pstcSpecialBufCfg->u32BufTransTim)<BCONR, + BCONR_REG_CFG_MSK<u32BufFunCmd | pstcSpecialBufCfg->u32BufNum | pstcSpecialBufCfg->u32BufTransTim)<u32BufFunCmd)); + DDL_ASSERT(IS_VALID_BUF_FUN_NUM(pstcPeriodBufCfg->u32BufNum)); + DDL_ASSERT(IS_VALID_BUF_TRANS_TIM(pstcPeriodBufCfg->u32BufTransTim)); + + MODIFY_REG32(TMR6x->BCONR, + BCONR_REG_CFG_MSK<u32BufFunCmd | pstcPeriodBufCfg->u32BufNum | pstcPeriodBufCfg->u32BufTransTim)<u32StatChA)); + DDL_ASSERT(IS_VALID_VALID_PERIOD_STAT_CHB(pstcValidPeriodCfg->u32StatChB)); + DDL_ASSERT(IS_VALID_PERIOD_CNT_COND(pstcValidPeriodCfg->u32CntCond)); + DDL_ASSERT(IS_VALID_PERIOD_CNT(pstcValidPeriodCfg->u32PeriodInterval)); + + WRITE_REG32(TMR6x->VPERR, pstcValidPeriodCfg->u32StatChA | + pstcValidPeriodCfg->u32StatChB | + pstcValidPeriodCfg->u32CntCond | + pstcValidPeriodCfg->u32PeriodInterval); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Port input configuration(Trig) + * @param [in] TMR6x Timer6 unit + * @param [in] u32PortSel Input port to be configured + * @arg TMR6_IO_PWMA + * @arg TMR6_IO_PWMB + * @arg TMR6_INPUT_TRIGA + * @arg TMR6_INPUT_TRIGB + * @arg TMR6_INPUT_TRIGC + * @arg TMR6_INPUT_TRIGD + * @param [in] pstcTmr6PortInputCfg Point Input Config Pointer + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_PortInputConfig(M4_TMR6_TypeDef *TMR6x, + uint32_t u32PortSel, + const stc_tmr6_port_input_cfg_t* pstcTmr6PortInputCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6PortInputCfg) + { + DDL_ASSERT(IS_VALID_INPUT_PORT(u32PortSel)); + DDL_ASSERT(IS_VALID_PORT_MODE_FUNC(pstcTmr6PortInputCfg->u32PortMode)); + DDL_ASSERT(IS_VALID_PORT_INPUT_FILTER_STA(pstcTmr6PortInputCfg->u32FilterSta)); + DDL_ASSERT(IS_VALID_INPUT_FILTER_CLK(pstcTmr6PortInputCfg->u32FltClk)); + + enRet = Ok; + switch (u32PortSel) + { + case TMR6_IO_PWMA: + MODIFY_REG32(TMR6x->PCNAR, + TMR6_PCNAR_CAPMDA, + pstcTmr6PortInputCfg->u32PortMode); + MODIFY_REG32(TMR6x->FCNGR, + TMR6_FCNGR_NOFIENGA | TMR6_FCNGR_NOFICKGA, + pstcTmr6PortInputCfg->u32FilterSta<u32FltClk<PCNBR, + TMR6_PCNBR_CAPMDB, + pstcTmr6PortInputCfg->u32PortMode); + MODIFY_REG32(TMR6x->FCNGR, + TMR6_FCNGR_NOFIENGB | TMR6_FCNGR_NOFICKGB, + pstcTmr6PortInputCfg->u32FilterSta<u32FltClk<FCNTR, + TMR6_FCNTR_NOFIENTA | TMR6_FCNTR_NOFICKTA, + pstcTmr6PortInputCfg->u32FilterSta<u32FltClk<FCNTR, + TMR6_FCNTR_NOFIENTB | TMR6_FCNTR_NOFICKTB, + pstcTmr6PortInputCfg->u32FilterSta<u32FltClk<FCNTR, + TMR6_FCNTR_NOFIENTC | TMR6_FCNTR_NOFICKTC, + pstcTmr6PortInputCfg->u32FilterSta<u32FltClk<FCNTR, + TMR6_FCNTR_NOFIENTD | TMR6_FCNTR_NOFICKTD, + pstcTmr6PortInputCfg->u32FilterSta<u32FltClk<u32PortMode)); + DDL_ASSERT(IS_VALID_FORCE_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32NextPeriodForceSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32DownCntMatchAnotherCmpRegSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32UpCntMatchAnotherCmpRegSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32DownCntMatchCmpRegSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32UpCntMatchCmpRegSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32UnderflowSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_RESULT(pstcTmr6PortOutputCfg->u32OverflowSta)); + + DDL_ASSERT(IS_VALID_OUTPUT_STA_STA(pstcTmr6PortOutputCfg->u32StopSta)); + DDL_ASSERT(IS_VALID_OUTPUT_STA_STA(pstcTmr6PortOutputCfg->u32StartSta)); + + if(TMR6_IO_PWMA == u32PortSel) + { + MODIFY_REG32(TMR6x->PCNAR, + PCNA_BR_REG_OUTPUT_CFG_MASK, + pstcTmr6PortOutputCfg->u32PortMode | TMR6_PCNAR_OUTENA + | pstcTmr6PortOutputCfg->u32NextPeriodForceSta << TMR6_PCNAR_FORCA_POS + | pstcTmr6PortOutputCfg->u32DownCntMatchAnotherCmpRegSta << TMR6_PCNAR_CMBDCA_POS + | pstcTmr6PortOutputCfg->u32UpCntMatchAnotherCmpRegSta << TMR6_PCNAR_CMBUCA_POS + | pstcTmr6PortOutputCfg->u32DownCntMatchCmpRegSta << TMR6_PCNAR_CMADCA_POS + | pstcTmr6PortOutputCfg->u32UpCntMatchCmpRegSta << TMR6_PCNAR_CMAUCA_POS + | pstcTmr6PortOutputCfg->u32UnderflowSta << TMR6_PCNAR_UDFCA_POS + | pstcTmr6PortOutputCfg->u32OverflowSta << TMR6_PCNAR_OVFCA_POS + | pstcTmr6PortOutputCfg->u32StopSta << TMR6_PCNAR_STPCA_POS + | pstcTmr6PortOutputCfg->u32StartSta << TMR6_PCNAR_STACA_POS); + } + else + { + MODIFY_REG32(TMR6x->PCNBR, + PCNA_BR_REG_OUTPUT_CFG_MASK, + pstcTmr6PortOutputCfg->u32PortMode | TMR6_PCNBR_OUTENB + | pstcTmr6PortOutputCfg->u32NextPeriodForceSta << TMR6_PCNBR_FORCB_POS + | pstcTmr6PortOutputCfg->u32DownCntMatchAnotherCmpRegSta << TMR6_PCNBR_CMADCB_POS + | pstcTmr6PortOutputCfg->u32UpCntMatchAnotherCmpRegSta << TMR6_PCNBR_CMAUCB_POS + | pstcTmr6PortOutputCfg->u32DownCntMatchCmpRegSta << TMR6_PCNBR_CMBDCB_POS + | pstcTmr6PortOutputCfg->u32UpCntMatchCmpRegSta << TMR6_PCNBR_CMBUCB_POS + | pstcTmr6PortOutputCfg->u32UnderflowSta << TMR6_PCNBR_UDFCB_POS + | pstcTmr6PortOutputCfg->u32OverflowSta << TMR6_PCNBR_OVFCB_POS + | pstcTmr6PortOutputCfg->u32StopSta << TMR6_PCNBR_STPCB_POS + | pstcTmr6PortOutputCfg->u32StartSta << TMR6_PCNBR_STACB_POS); + } + enRet = Ok; + } + return enRet; +} + +/** + * @brief EMB function configuration + * @param [in] TMR6x Timer6 unit + * @param [in] u32PortSel Output port to be configured + * @arg TMR6_IO_PWMA + * @arg TMR6_IO_PWMB + * @param [in] pstcTmr6EmbCfg Point EMB function Config Pointer + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_EMBConfig(M4_TMR6_TypeDef *TMR6x, + uint32_t u32PortSel, + const stc_tmr6_emb_cfg_t* pstcTmr6EmbCfg) +{ + __IO uint32_t *PCNXR; + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6EmbCfg) + { + DDL_ASSERT(IS_VALID_OUTPUT_PORT(u32PortSel)); + DDL_ASSERT(IS_VALID_EMB_CH(pstcTmr6EmbCfg->u32ValidCh)); + DDL_ASSERT(IS_VALID_EMB_RELEASE_MODE(pstcTmr6EmbCfg->u32ReleaseMode)); + DDL_ASSERT(IS_VALID_EMB_VALID_PORT_STA(pstcTmr6EmbCfg->u32PortSta)); + + if(TMR6_IO_PWMA == u32PortSel) + { + PCNXR = (__IO uint32_t*)&TMR6x->PCNAR; + } + else + { + PCNXR = (__IO uint32_t*)&TMR6x->PCNBR; + } + + MODIFY_REG32(*PCNXR, + PCNA_BR_REG_EMB_CFG_MASK, + pstcTmr6EmbCfg->u32ValidCh + | pstcTmr6EmbCfg->u32ReleaseMode + | pstcTmr6EmbCfg->u32PortSta ); + + enRet = Ok; + } + return enRet; + +} + +/** + * @brief Timer6 dead time function command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR6_DeadTimeFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if(Enable == enNewState) + { + SET_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } + else + { + CLEAR_REG32_BIT(TMR6x->DCONR, TMR6_DCONR_DTCEN); + } +} + +/** + * @brief DeadTime function configuration + * @param [in] TMR6x Timer6 unit + * @param [in] pstcTmr6DTCfg Timer6 dead time config pointer + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_DeadTimeCfg(M4_TMR6_TypeDef *TMR6x, const stc_tmr6_deadtime_cfg_t* pstcTmr6DTCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + if (NULL != pstcTmr6DTCfg) + { + DDL_ASSERT(IS_VALID_DEADTIME_EQUAL_FUNC_REG(pstcTmr6DTCfg->u32DtEqualUpDwn)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTUAR_REG(pstcTmr6DTCfg->u32EnDtBufUp)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_FUNC_DTDAR_REG(pstcTmr6DTCfg->u32EnDtBufDwn)); + DDL_ASSERT(IS_VALID_DEADTIME_BUF_TRANS_COND_REG(pstcTmr6DTCfg->u32DtUpdCond)); + + WRITE_REG32(TMR6x->DCONR, pstcTmr6DTCfg->u32DtEqualUpDwn + | pstcTmr6DTCfg->u32EnDtBufUp + | pstcTmr6DTCfg->u32EnDtBufDwn + | pstcTmr6DTCfg->u32DtUpdCond); + enRet = Ok; + } + return enRet; +} + +/** + * @brief Software Sync Start + * @param [in] u32UnitCombine Software Sync units, This parameter can + * be one or any combination of the parameter + * @ref TMR6_Soft_Sync_Ctrl_Unit_Number_define + * @retval None + */ +void TMR6_SwSyncStart(uint32_t u32UnitCombine) +{ + DDL_ASSERT(IS_VALID_SW_CTRL_CFG(u32UnitCombine)); + WRITE_REG32(M4_TMR6_1->SSTAR, u32UnitCombine); +} + +/** + * @brief Software Sync Stop + * @param [in] u32UnitCombine Software Sync units, This parameter can + * be one or any combination of the parameter + * @ref TMR6_Soft_Sync_Ctrl_Unit_Number_define + * @retval None + */ +void TMR6_SwSyncStop(uint32_t u32UnitCombine) +{ + DDL_ASSERT(IS_VALID_SW_CTRL_CFG(u32UnitCombine)); + WRITE_REG32(M4_TMR6_1->SSTPR, u32UnitCombine); +} + +/** + * @brief Software Sync clear + * @param [in] u32UnitCombine Software Sync units, This parameter can + * be one or any combination of the parameter + * @ref TMR6_Soft_Sync_Ctrl_Unit_Number_define + * @retval None + */ +void TMR6_SwSyncClr(uint32_t u32UnitCombine) +{ + DDL_ASSERT(IS_VALID_SW_CTRL_CFG(u32UnitCombine)); + WRITE_REG32(M4_TMR6_1->SCLRR, u32UnitCombine); +} + +/** + * @brief Software Sync update + * @param [in] u32UnitCombine Software Sync units, This parameter can + * be one or any combination of the parameter + * @ref TMR6_Soft_Sync_Ctrl_Unit_Number_define + * @retval None + */ +void TMR6_SwSyncUpdate(uint32_t u32UnitCombine) +{ + DDL_ASSERT(IS_VALID_SW_CTRL_CFG(u32UnitCombine)); + WRITE_REG32(M4_TMR6_1->SUPDR, u32UnitCombine); +} + +/** + * @brief Hardware start function command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR6_HwStartFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTAR, TMR6_HSTAR_STAS, (uint32_t)enNewState << TMR6_HSTAR_STAS_POS); +} + +/** + * @brief Hardware stop function command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR6_HwStopFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HSTPR, TMR6_HSTPR_STPS, (uint32_t)enNewState << TMR6_HSTPR_STPS_POS); +} + +/** + * @brief Hardware clear function command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] enNewState Disable or Enable the function + * @retval None + */ +void TMR6_HwClrFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HCLRR, TMR6_HCLRR_CLES, (uint32_t)enNewState << TMR6_HCLRR_CLES_POS); +} + +/** + * @brief Hardware update function command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] enNewState Disable or Enable the function + * + * @retval None + */ +void TMR6_HwUpdateFuncCmd(M4_TMR6_TypeDef *TMR6x, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + MODIFY_REG32(TMR6x->HUPDR, TMR6_HUPDR_UPDS, (uint32_t)enNewState << TMR6_HUPDR_UPDS_POS); +} + +/** + * @brief Hardware start condtion command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware start, maybe one or any combination of the parameter + * @ref TMR6_hardware_control_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwStartCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CTRL_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HSTAR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HSTAR, u32CondSrc); + } +} + +/** + * @brief Hardware start condition clear + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwStartCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HSTAR, 0UL); +} + +/** + * @brief Hardware stop condtion command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware stop, maybe one or any combination of the parameter + * @ref TMR6_hardware_control_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwStopCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CTRL_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HSTPR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HSTPR, u32CondSrc); + } +} + +/** + * @brief Hardware stop condtion clear + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwStopCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HSTPR, 0UL); +} + +/** + * @brief Hardware clear condtion command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware clear, maybe one or any combination of the parameter + * @ref TMR6_hardware_control_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwClrCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CTRL_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HCLRR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HCLRR, u32CondSrc); + } +} + +/** + * @brief Hardware clear condtion clear + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwClrCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HCLRR, 0UL); +} + +/** + * @brief Hardware update condtion command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware update, maybe one or any combination of the parameter + * @ref TMR6_hardware_control_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwUpdCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CTRL_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HUPDR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HUPDR, u32CondSrc); + } +} + +/** + * @brief Hardware update conditon clear + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwUpdCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HUPDR, 0UL); +} + +/** + * @brief Hardware capture condtion command for channel A + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware capture, maybe one or any combination of the parameter + * @ref TMR6_hardware_control_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwCaptureChACondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CTRL_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HCPAR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HCPAR, u32CondSrc); + } +} + +/** + * @brief Hardware capture condition clear for channel A + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwCaptureChACondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HCPAR, 0UL); +} + +/** + * @brief Hardware capture condtion command for channel B + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware capture, maybe one or any combination of the parameter + * @ref TMR6_hardware_control_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwCaptureChBCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CTRL_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HCPBR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HCPBR, u32CondSrc); + } +} + +/** + * @brief Hardware capture condition clear for channel B + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwCaptureChBCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HCPBR, 0UL); +} + +/** + * @brief Hardware increase conditon command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_hardware_count_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwIncreaseCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CNT_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HCUPR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HCUPR, u32CondSrc); + } +} + +/** + * @brief Hardware increase condition clear + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3s + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwIncreaseCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HCUPR, 0UL); +} + +/** + * @brief Hardware decrease condition command + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @param [in] u32CondSrc Events source for hardware count, maybe one or any combination of the parameter + * @ref TMR6_hardware_count_event_define + * @param [in] enNewState The function new state + * @arg This parameter can be: Enable or Disable + * @retval None + */ +void TMR6_HwDecreaseCondCmd(M4_TMR6_TypeDef *TMR6x, + uint32_t u32CondSrc, + en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + DDL_ASSERT(IS_VALID_HW_CNT_EVENTS(u32CondSrc)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(TMR6x->HCDOR, u32CondSrc); + } + else + { + CLEAR_REG32_BIT(TMR6x->HCDOR, u32CondSrc); + } +} + +/** + * @brief Hardware decrease condtion clear + * @param [in] TMR6x Timer6 unit + * @arg M4_TMR6_1 + * @arg M4_TMR6_2 + * @arg M4_TMR6_3 + * @arg M4_TMR6_4 + * @arg M4_TMR6_5 + * @arg M4_TMR6_6 + * @arg M4_TMR6_7 + * @arg M4_TMR6_8 + * @retval None + */ +void TMR6_HwDecreaseCondClr(M4_TMR6_TypeDef *TMR6x) +{ + DDL_ASSERT(IS_VALID_TMR6_UNIT(TMR6x)); + + WRITE_REG32(TMR6x->HCDOR, 0UL); +} + +/** + * @brief Timer6 Hardware trigger event configuration for(trigger0~trigger3) + * @param [in] u32TrigIndex Timer6 Hardware trigger index + * @ref TMR6_Hardware_Trigger_Index_define + * @param [in] enEvent Event configuration for timer6 hardware trigger + * @retval None + */ +void TMR6_SetTriggerSrc(uint32_t u32TrigIndex, en_event_src_t enEvent) +{ + DDL_ASSERT(IS_VALID_HW_TRIGGER_INDEX(u32TrigIndex)); + + __IO uint32_t *TMR6_HTSSRx = (__IO uint32_t *)((uint32_t)&M4_AOS->TMR6_HTSSR1 + 4UL * u32TrigIndex); + MODIFY_REG32(*TMR6_HTSSRx, AOS_TMR6_HTSSR_TRGSEL, enEvent); +} + +/** + * @brief Timer6 Hardware trigger common event function command for(trigger0~trigger3) + * @param [in] u32TrigIndex Timer6 Hardware trigger index + * @ref TMR6_Hardware_Trigger_Index_define + * @param [in] u32ComTrig Common trigger event enable. + * This parameter can be one of the following values: + * @arg TMR6_COM_TRIG1: Common trigger event 1. + * @arg TMR6_COM_TRIG2: Common trigger event 2. + * @param [in] enNewState New state of common trigger function. + * @retval none + */ +void TMR6_ComTriggerCmd(uint32_t u32TrigIndex, uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_VALID_HW_TRIGGER_INDEX(u32TrigIndex)); + DDL_ASSERT(IS_VALID_TMR6_COM_TRIG(u32ComTrig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + __IO uint32_t *TMR6_HTSSRx = (__IO uint32_t *)((uint32_t)&M4_AOS->TMR6_HTSSR1 + 4UL * u32TrigIndex); + + if (Enable == enNewState) + { + SET_REG32_BIT(*TMR6_HTSSRx, u32ComTrig); + } + else + { + CLEAR_REG32_BIT(*TMR6_HTSSRx, u32ComTrig); + } +} + +/** + * @brief Set the fields of structure stc_tmr6_basecnt_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_basecnt_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_BaseCntStructInit(stc_tmr6_basecnt_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32CntMode = TMR6_MODE_SAWTOOTH; + pstcInit->u32CntDir = TMR6_CNT_INCREASE; + pstcInit->u32CntClkDiv = TMR6_CLK_PCLK0_DIV1; + pstcInit->u32CntStpAftOvf = TMR6_CNT_CONTINUOUS; + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_buf_func_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_buf_func_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_BufFuncStructInit(stc_tmr6_buf_func_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32BufFunCmd = TMR6_BUF_FUNC_OFF; + pstcInit->u32BufNum = TMR6_BUF_FUNC_SINGLE; + pstcInit->u32BufTransTim = TMR6_BUF_TRANS_TIM_NONE; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_valid_period_func_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_valid_period_func_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_ValidPeriodStructInit(stc_tmr6_valid_period_func_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32StatChA = TMR6_VALID_PERIOD_FUNC_CHA_OFF; + pstcInit->u32StatChB = TMR6_VALID_PERIOD_FUNC_CHB_OFF; + pstcInit->u32CntCond = TMR6_VALID_PERIOD_FUNC_OFF; + pstcInit->u32PeriodInterval = TMR6_VALID_PERIOD_CNT_INVALID; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_port_input_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_port_input_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_PortInputStructInit(stc_tmr6_port_input_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32PortMode = TMR6_PORT_CAPTURE_INPUT; + pstcInit->u32FilterSta = TMR6_PORT_INPUT_FILTER_OFF; + pstcInit->u32FltClk = TMR6_INPUT_FILTER_PCLK0_DIV1; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_port_output_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_port_output_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_PortOutputStructInit(stc_tmr6_port_output_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32PortMode = TMR6_PORT_COMPARE_OUTPUT; + pstcInit->u32NextPeriodForceSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32DownCntMatchAnotherCmpRegSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32UpCntMatchAnotherCmpRegSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32DownCntMatchCmpRegSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32UpCntMatchCmpRegSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32UnderflowSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32OverflowSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32StopSta = TMR6_PORT_OUTPUT_STA_LOW; + pstcInit->u32StartSta = TMR6_PORT_OUTPUT_STA_LOW; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_emb_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_emb_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_EMBCfgStructInit(stc_tmr6_emb_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32ValidCh = TMR6_EMB_EVENT_VALID_CH0; + pstcInit->u32ReleaseMode = TMR6_EMB_RELEASE_IMMEDIATE; + pstcInit->u32PortSta = TMR6_EMB_PORTSTA_NORMAL; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_deadtime_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_deadtime_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_DeadTimeCfgStructInit(stc_tmr6_deadtime_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32DtEqualUpDwn = TMR6_DEADTIME_EQUAL_OFF; + pstcInit->u32EnDtBufUp = TMR6_DEADTIME_CNT_UP_BUF_OFF; + pstcInit->u32EnDtBufDwn = TMR6_DEADTIME_CNT_DOWN_BUF_OFF; + + enRet = Ok; + } + return enRet; +} + +/** + * @brief Set the fields of structure stc_tmr6_zmask_cfg_t to default values + * @param [out] pstcInit Pointer to a @ref stc_tmr6_zmask_cfg_t structure + * @retval An en_result_t enumeration value. + * @arg Ok: Successfully done + * @arg ErrorInvalidParameter: Parameter error + */ +en_result_t TMR6_ZMaskCfgStructInit(stc_tmr6_zmask_cfg_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32ZMaskCycle = TMR6_ZMASK_CYCLE_FUNC_INVALID; + pstcInit->u32PosCntMaskEn = TMR6_POS_CLR_ZMASK_FUNC_INVALID; + pstcInit->u32RevCntMaskEn = TMR6_REVO_CNT_ZMASK_FUNC_INVALID; + + enRet = Ok; + } + return enRet; +} +/** + * @} + */ + +#endif /* DDL_TMR6_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmra.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmra.c new file mode 100644 index 0000000000000000000000000000000000000000..42a73b173d64be669587b16ebd9bdd0664210090 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmra.c @@ -0,0 +1,1561 @@ +/** + ******************************************************************************* + * @file hc32f4a0_tmra.c + * @brief This file provides firmware functions to manage the TMRA(TimerA). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Wuze First version + 2020-07-02 Wuze API TMRA_SyncStartCmd() refine. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_tmra.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_TMRA TMRA + * @brief TMRA Driver Library + * @{ + */ + +#if (DDL_TMRA_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TMRA_Local_Macros TMRA Local Macros + * @{ + */ + +/** + * @defgroup TMRA_Configuration_Bit_Mask TMRA Configuration Bit Mask + * @{ + */ +#define TMRA_BCSTR_INIT_MSK (0x01F6UL) +#define TMRA_BCSTR_INT_MSK (0x00003000UL) +#define TMRA_BCSTR_FLAG_MSK (0x0000C000UL) +#define TMRA_FCONR_FILTER_CLK_MSK (0x3UL) +#define TMRA_CCONR_FILTER_CLK_MSK (TMRA_CCONR_NOFICKCP) +#define TMRA_PWM_POLARITY_MSK (0x03FFUL) +#define TMRA_TRIG_COND_MSK (TMRA_START_COND_ALL | TMRA_STOP_COND_ALL | TMRA_CLR_COND_ALL) +#define TMRA_CACHE_COND_MSK (TMRA_BCONR_BSE0 | TMRA_BCONR_BSE1) +#define TMRA_COM_TRIG_MSK (TMRA_COM_TRIG1 | TMRA_COM_TRIG2) +#define TMRA_TRIG_EVENT_MSK (AOS_TMRA_HTSSR_TRGSEL) +/** + * @} + */ + +/** + * @defgroup TMRA_Unit_Index TMRA Unit Index + * @{ + */ +#define __TMRA_BASE (0x4003A000UL) +#define __TMRA_UNIT_SIZE (0x400UL) +#define TMRA_IDX(__TMRAx__) (((uint32_t)&(__TMRAx__)->CNTER - __TMRA_BASE) / __TMRA_UNIT_SIZE) +/** + * @} + */ + +/** + * @defgroup TMRA_Register_Bit_Band TMRA Register Bit Band + * @{ + */ +#define __BIT_BAND_BASE (0x42000000UL) +#define __PERIP_BASE (0x40000000UL) +#define __REG_OFS(regAddr) ((regAddr) - __PERIP_BASE) +#define __BIT_BAND_ADDR(regAddr, pos) ((__REG_OFS(regAddr) << 5U) + ((uint32_t)(pos) << 2U) + __BIT_BAND_BASE) +#define BIT_BAND(regAddr, pos) (*(__IO uint32_t *)__BIT_BAND_ADDR((regAddr), (pos))) +/** + * @} + */ + +/** + * @defgroup TMRA_HTSSR_Address TMRA HTSSR Address + * @{ + */ +#define TMRA_HTSSR0_ADDR (0x40010880UL) +#define TMRA_HTSSR1_ADDR (0x40010884UL) +#define TMRA_HTSSR2_ADDR (0x40010888UL) +#define TMRA_HTSSR3_ADDR (0x4001088CUL) +/** + * @} + */ + +/** + * @defgroup TMRA_Check_Parameters_Validity TMRA check parameters validity + * @{ + */ +#define IS_TMRA_UNIT(x) \ +( ((x) == M4_TMRA_1) || \ + ((x) == M4_TMRA_2) || \ + ((x) == M4_TMRA_3) || \ + ((x) == M4_TMRA_4) || \ + ((x) == M4_TMRA_5) || \ + ((x) == M4_TMRA_6) || \ + ((x) == M4_TMRA_7) || \ + ((x) == M4_TMRA_8) || \ + ((x) == M4_TMRA_9) || \ + ((x) == M4_TMRA_10) || \ + ((x) == M4_TMRA_11) || \ + ((x) == M4_TMRA_12)) + +#define IS_TMRA_EVEN_UNIT(x) \ +( ((x) == M4_TMRA_2) || \ + ((x) == M4_TMRA_4) || \ + ((x) == M4_TMRA_6) || \ + ((x) == M4_TMRA_8) || \ + ((x) == M4_TMRA_10) || \ + ((x) == M4_TMRA_12)) + +#define IS_TMRA_CH(x) \ +( ((x) <= TMRA_CH_4)) + +#define IS_TMRA_FUNC_MODE(x) \ +( ((x) == TMRA_FUNC_COMPARE) || \ + ((x) == TMRA_FUNC_CAPTURE)) + +#define IS_TMRA_PCLK_DIV(x) \ +( ((x) == TMRA_PCLK_DIV1) || \ + ((x) == TMRA_PCLK_DIV2) || \ + ((x) == TMRA_PCLK_DIV4) || \ + ((x) == TMRA_PCLK_DIV8) || \ + ((x) == TMRA_PCLK_DIV16) || \ + ((x) == TMRA_PCLK_DIV32) || \ + ((x) == TMRA_PCLK_DIV64) || \ + ((x) == TMRA_PCLK_DIV128) || \ + ((x) == TMRA_PCLK_DIV256) || \ + ((x) == TMRA_PCLK_DIV512) || \ + ((x) == TMRA_PCLK_DIV1024)) + +#define IS_TMRA_CNT_DIR(x) \ +( ((x) == TMRA_DIR_DOWN) || \ + ((x) == TMRA_DIR_UP)) + +#define IS_TMRA_CNT_MODE(x) \ +( ((x) == TMRA_MODE_SAWTOOTH) || \ + ((x) == TMRA_MODE_TRIANGLE)) + +#define IS_TMRA_OVF_OPERATION(x) \ +( ((x) == TMRA_OVF_CNT_CONTINUE) || \ + ((x) == TMRA_OVF_CNT_STOP)) + +#define IS_TMRA_FILTER_CLK_DIV(x) \ +( ((x) <= TMRA_FILTER_CLK_DIV64)) + +#define IS_TMRA_CACHE_COND(x) \ +( ((x) == TMRA_CACHE_COND_OVF_CLR) || \ + ((x) == TMRA_CACHE_COND_TW_VALLEY) || \ + ((x) == TMRA_CACHE_COND_TW_PEAK)) + +#define IS_TMRA_PWM_START_POLARITY(x) \ +( ((x) == TMRA_PWM_START_LOW) || \ + ((x) == TMRA_PWM_START_HIGH) || \ + ((x) == TMRA_PWM_START_KEEP)) + +#define IS_TMRA_PWM_STOP_POLARITY(x) \ +( ((x) == TMRA_PWM_STOP_LOW) || \ + ((x) == TMRA_PWM_STOP_HIGH) || \ + ((x) == TMRA_PWM_STOP_KEEP)) + +#define IS_TMRA_PWM_CMP_POLARITY(x) \ +( ((x) == TMRA_PWM_CMP_LOW) || \ + ((x) == TMRA_PWM_CMP_HIGH) || \ + ((x) == TMRA_PWM_CMP_KEEP) || \ + ((x) == TMRA_PWM_CMP_REVERSE)) + +#define IS_TMRA_PWM_PERIOD_POLARITY(x) \ +( ((x) == TMRA_PWM_PERIOD_LOW) || \ + ((x) == TMRA_PWM_PERIOD_HIGH) || \ + ((x) == TMRA_PWM_PERIOD_KEEP) || \ + ((x) == TMRA_PWM_PERIOD_REVERSE)) + +#define IS_TMRA_PWM_FORCE_POLARITY(x) \ +( ((x) == TMRA_PWM_FORCE_INVALID) || \ + ((x) == TMRA_PWM_FORCE_LOW) || \ + ((x) == TMRA_PWM_FORCE_HIGH)) + +#define IS_TMRA_EVT_USAGE(x) \ +( ((x) == TMRA_EVENT_USAGE_CNT) || \ + ((x) == TMRA_EVENT_USAGE_CAPT)) + +#define IS_TMRA_COM_TRIGGER(x) \ +( ((x) != 0U) && \ + (((x) | TMRA_COM_TRIG_MSK) == TMRA_COM_TRIG_MSK)) + +#define IS_TMRA_VALID_VAL(x) \ +( (x) <= 0xFFFFUL) + +/** + * @} + */ + +/** + * @defgroup TMRA_Miscellaneous_Macros TMRA Miscellaneous Macros + * @{ + */ +#define TMRA_CH_COUNT (4U) +#define TMRA_PIN_PWM_OFFSET (3U) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TMRA_Global_Functions TMRA Global Functions + * @{ + */ + +/** + * @brief Initializes the specified TMRA peripheral according to the specified parameters \ + * in the structure stc_tmra_init_t + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] pstcInit Pointer to a stc_tmra_init_t structure value that \ + * contains the configuration information for the TMRA. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t TMRA_Init(M4_TMRA_TypeDef *TMRAx, const stc_tmra_init_t *pstcInit) +{ + uint32_t u32Cfg = 0U; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_DIR(pstcInit->u32CntDir)); + DDL_ASSERT(IS_TMRA_CNT_MODE(pstcInit->u32CntMode)); + DDL_ASSERT(IS_TMRA_OVF_OPERATION(pstcInit->u32CntOvfOp)); + DDL_ASSERT(IS_TMRA_VALID_VAL(pstcInit->u32PeriodVal)); + DDL_ASSERT(IS_TMRA_VALID_VAL(pstcInit->u32CntVal)); + + if (pstcInit->u32ClkSrc == TMRA_CLK_PCLK) + { + DDL_ASSERT(IS_TMRA_PCLK_DIV(pstcInit->u32PCLKDiv)); + u32Cfg = pstcInit->u32PCLKDiv | pstcInit->u32CntDir | pstcInit->u32CntMode; + } + else + { + WRITE_REG32(TMRAx->HCUPR, (pstcInit->u32ClkSrc & TMRA_CLK_HW_UP_ALL)); + WRITE_REG32(TMRAx->HCDOR, ((pstcInit->u32ClkSrc & TMRA_CLK_HW_DOWN_ALL) >> 16U)); + } + + u32Cfg |= pstcInit->u32CntOvfOp; + + MODIFY_REG32(TMRAx->BCSTR, TMRA_BCSTR_INIT_MSK, u32Cfg); + WRITE_REG32(TMRAx->PERAR, pstcInit->u32PeriodVal); + WRITE_REG32(TMRAx->CNTER, pstcInit->u32CntVal); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for the TMRA initialization structure. + * @param [in] pstcInit Pointer to a stc_tmra_init_t structure value that \ + * contains the configuration information for the TMRA. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcInit == NULL. + */ +en_result_t TMRA_StructInit(stc_tmra_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcInit != NULL) + { + pstcInit->u32ClkSrc = TMRA_CLK_PCLK; + pstcInit->u32PCLKDiv = TMRA_PCLK_DIV1; + pstcInit->u32CntDir = TMRA_DIR_UP; + pstcInit->u32CntMode = TMRA_MODE_SAWTOOTH; + pstcInit->u32CntOvfOp = TMRA_OVF_CNT_CONTINUE; + pstcInit->u32PeriodVal = 0xFFFFUL; + pstcInit->u32CntVal = 0UL; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-initializes the TMRA peripheral. Reset all registers of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @retval None + */ +void TMRA_DeInit(M4_TMRA_TypeDef *TMRAx) +{ + uint32_t i; + uint32_t u32AddrOffset; + uint32_t u32CMPARAddr; + uint32_t u32CCONRAddr; + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32CMPARAddr = TMRAx->CMPAR1; + u32CCONRAddr = TMRAx->CCONR1; + u32PCONRAddr = TMRAx->PCONR1; + + for (i=0U; iCNTER, 0x0U); + WRITE_REG32(TMRAx->PERAR, 0xFFFFU); + WRITE_REG32(TMRAx->BCSTR, 0x2U); + WRITE_REG32(TMRAx->ICONR, 0x0U); + WRITE_REG32(TMRAx->ECONR, 0x0U); + WRITE_REG32(TMRAx->FCONR, 0x0U); + WRITE_REG32(TMRAx->STFLR, 0x0U); + WRITE_REG32(TMRAx->BCONR1, 0x0U); + WRITE_REG32(TMRAx->BCONR2, 0x0U); + WRITE_REG32(TMRAx->HCONR, 0x0U); + WRITE_REG32(TMRAx->HCUPR, 0x0U); + WRITE_REG32(TMRAx->HCDOR, 0x0U); +} + +/** + * @brief Set general count value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32Val The general count value to be set. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMRA_SetCntVal(M4_TMRA_TypeDef *TMRAx, uint32_t u32Val) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_VALID_VAL(u32Val)); + WRITE_REG32(TMRAx->CNTER, u32Val); +} + +/** + * @brief Get general count value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @retval An uint32_t type type value of general count value between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMRA_GetCntVal(const M4_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->CNTER); +} + +/** + * @brief Set period reference value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32Val The period reference value to be set. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMRA_SetPeriodVal(M4_TMRA_TypeDef *TMRAx, uint32_t u32Val) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_VALID_VAL(u32Val)); + WRITE_REG32(TMRAx->PERAR, u32Val); +} + +/** + * @brief Get period reference value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @retval An uint32_t type type value of period reference value between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMRA_GetPeriodVal(const M4_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return (TMRAx->PERAR); +} + +/** + * @brief Specifies the function mode of the specified TMRA channle. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32FuncMode Function mode of TMRA. + * This parameter can be a value of @ref TMRA_Function_Mode + * @arg TMRA_FUNC_COMPARE: The function mode of TMRA is comparison ouput. + * @arg TMRA_FUNC_CAPTURE: The function mode of TMRA is capture the input. + * @retval None + */ +void TMRA_SetFuncMode(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32FuncMode) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_FUNC_MODE(u32FuncMode)); + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (uint32_t)u8TmrCh * 4U; + BIT_BAND(u32CCONRAddr, TMRA_CCONR_CAPMD_POS) = u32FuncMode; +} + +/** + * @brief Set compare reference value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Val The comparison reference value to be set. + * This parameter can be a number between 0U and 0xFFFFU, inclusive. + * @retval None + */ +void TMRA_SetCmpVal(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Val) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_VALID_VAL(u32Val)); + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + (uint32_t)u8TmrCh * 4U; + RW_MEM32(u32CMPARAddr) = u32Val; +} + +/** + * @brief Get compare reference value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @retval An uint32_t type type value of comparison reference value between 0U and 0xFFFFU, inclusive. + */ +uint32_t TMRA_GetCmpVal(const M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh) +{ + uint32_t u32CMPARAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + + u32CMPARAddr = (uint32_t)&TMRAx->CMPAR1 + (uint32_t)u8TmrCh * 4U; + return RW_MEM32(u32CMPARAddr); +} + +/** + * @brief Configures the specified channel's PWM of TMRA according to the specified parameters + * in the structure stc_tmra_pwm_cfg_t. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] pstcCfg Pointer to a stc_tmra_pwm_cfg_t structure value that + * contains the configuration information for the PWM. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t TMRA_PWM_Config(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, const stc_tmra_pwm_cfg_t *pstcCfg) +{ + uint32_t u32Cfg; + uint32_t u32PCONRAddr; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(pstcCfg->u32StartPolarity)); + DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(pstcCfg->u32StopPolarity)); + DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(pstcCfg->u32CmpPolarity)); + DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(pstcCfg->u32PeriodPolarity)); + DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(pstcCfg->u32ForcePolarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + u32Cfg = pstcCfg->u32StartPolarity | \ + pstcCfg->u32StopPolarity | \ + pstcCfg->u32CmpPolarity | \ + pstcCfg->u32PeriodPolarity | \ + pstcCfg->u32ForcePolarity; + MODIFY_REG32(RW_MEM32(u32PCONRAddr), TMRA_PWM_POLARITY_MSK, u32Cfg); + + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for the PWM configuration structure. + * @param [in] pstcCfg Pointer to a stc_tmra_pwm_cfg_t structure value that + * contains the configuration information for the PWM. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t TMRA_PWM_StructInit(stc_tmra_pwm_cfg_t *pstcCfg) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCfg != NULL) + { + pstcCfg->u32StartPolarity = TMRA_PWM_START_HIGH; + pstcCfg->u32StopPolarity = TMRA_PWM_STOP_LOW; + pstcCfg->u32CmpPolarity = TMRA_PWM_CMP_REVERSE; + pstcCfg->u32PeriodPolarity = TMRA_PWM_PERIOD_REVERSE; + pstcCfg->u32ForcePolarity = TMRA_PWM_FORCE_INVALID; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Enable or disable the specified channel's PWM output. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified channel's PWM output. + * @arg Disable: Disable the specified channel's PWM output. + * @retval None + */ +void TMRA_PWM_Cmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, en_functional_state_t enNewState) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + BIT_BAND(u32PCONRAddr, TMRA_PCONR_OUTEN_POS) = (uint32_t)enNewState; +} + +/** + * @brief Specifies the divider of filter's clock source for the specified TMRA input pin. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8InputPin The input pin of TMRA. + * This parameter can be values of @ref TMRA_Input_Pin + * @arg TMRA_PIN_TRIG: Pin TIMA__TRIG. + * @arg TMRA_PIN_CLKA: Pin TIMA__CLKA. + * @arg TMRA_PIN_CLKB: Pin TIMA__CLKB. + * @arg TMRA_PIN_PWM1: Pin TIMA__PWM1. + * @arg TMRA_PIN_PWM2: Pin TIMA__PWM2. + * @arg TMRA_PIN_PWM3: Pin TIMA__PWM3. + * @arg TMRA_PIN_PWM4: Pin TIMA__PWM4. + * @param [in] u32ClkDiv The clock source divider of the filter. + * This parameter can be a value of @ref TMRA_Filter_Clock_Divider + * @arg TMRA_FILTER_CLK_DIV1: The filter clock is PCLK / 1. + * @arg TMRA_FILTER_CLK_DIV4: The filter clock is PCLK / 4. + * @arg TMRA_FILTER_CLK_DIV16: The filter clock is PCLK / 16. + * @arg TMRA_FILTER_CLK_DIV64: The filter clock is PCLK / 64. + * @retval None + */ +void TMRA_FilterConfig(M4_TMRA_TypeDef *TMRAx, uint8_t u8InputPin, uint32_t u32ClkDiv) +{ + uint8_t u8PinIdx = 0U; + uint8_t u8TmrCh; + uint32_t u32CfgMsk; + uint32_t u32CCONRAddr; + uint8_t au8Offset[] = {TMRA_FCONR_NOFICKTG_POS, TMRA_FCONR_NOFICKCA_POS, TMRA_FCONR_NOFICKCB_POS, \ + TMRA_CCONR_NOFICKCP_POS, TMRA_CCONR_NOFICKCP_POS, TMRA_CCONR_NOFICKCP_POS, \ + TMRA_CCONR_NOFICKCP_POS}; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_FILTER_CLK_DIV(u32ClkDiv)); + + u8InputPin &= (uint8_t)TMRA_PIN_ALL; + while (u8InputPin != 0U) + { + if ((u8InputPin & 0x1U) != 0U) + { + if (u8PinIdx < TMRA_PIN_PWM_OFFSET) + { + u32CfgMsk = (uint32_t)(TMRA_FCONR_FILTER_CLK_MSK << au8Offset[u8PinIdx]); + MODIFY_REG32(TMRAx->FCONR, u32CfgMsk, (u32ClkDiv << au8Offset[u8PinIdx])); + } + else + { + u8TmrCh = u8PinIdx - TMRA_PIN_PWM_OFFSET; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32CCONRAddr), \ + TMRA_CCONR_FILTER_CLK_MSK, \ + (u32ClkDiv << au8Offset[u8PinIdx])); + } + } + u8InputPin >>= 1U; + u8PinIdx++; + } +} + +/** + * @brief Enable or disable the filter function of the specified TMRA input pin. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8InputPin The input pin of TMRA. + * This parameter can be values of @ref TMRA_Input_Pin + * @arg TMRA_PIN_TRIG: Pin TIMA__TRIG. + * @arg TMRA_PIN_CLKA: Pin TIMA__CLKA. + * @arg TMRA_PIN_CLKB: Pin TIMA__CLKB. + * @arg TMRA_PIN_PWM1: Pin TIMA__PWM1. + * @arg TMRA_PIN_PWM2: Pin TIMA__PWM2. + * @arg TMRA_PIN_PWM3: Pin TIMA__PWM3. + * @arg TMRA_PIN_PWM4: Pin TIMA__PWM4. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified pin's filter. + * @arg Disable: Disable the specified pin's filter. + * @retval None + */ +void TMRA_FilterCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8InputPin, en_functional_state_t enNewState) +{ + uint8_t u8PinIdx = 0U; + uint8_t u8TmrCh; + uint32_t u32CCONRAddr; + uint8_t au8Offset[] = {TMRA_FCONR_NOFIENTG_POS, TMRA_FCONR_NOFIENCA_POS, TMRA_FCONR_NOFIENCB_POS, \ + TMRA_CCONR_NOFIENCP_POS, TMRA_CCONR_NOFIENCP_POS, TMRA_CCONR_NOFIENCP_POS, \ + TMRA_CCONR_NOFIENCP_POS}; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u8InputPin &= (uint8_t)TMRA_PIN_ALL; + while (u8InputPin != 0U) + { + if ((u8InputPin & 0x1U) != 0U) + { + if (u8PinIdx < TMRA_PIN_PWM_OFFSET) + { + u32CCONRAddr = (uint32_t)&TMRAx->FCONR; + } + else + { + u8TmrCh = u8PinIdx - TMRA_PIN_PWM_OFFSET; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (uint32_t)u8TmrCh * 4U; + } + BIT_BAND(u32CCONRAddr, au8Offset[u8PinIdx]) = (uint32_t)enNewState; + } + u8InputPin >>= 1U; + u8PinIdx++; + } +} + +/** + * @brief Specifies the capture condition for the specified channel. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Cond The capture condition. Set this parameter to 0xFFFF to select all the conditions of capturing start. + * This parameter can be values of @ref TMRA_Channel_Capture_Condition + * @arg TMRA_CAPT_COND_INVALID: The condition of capture is INVALID. + * @arg TMRA_CAPT_COND_PWMR: The condition of capture is a rising edge is sampled on PWM(pin). + * @arg TMRA_CAPT_COND_PWMF: The condition of capture is a falling edge is sampled on PWM(pin). + * @arg TMRA_CAPT_COND_EVENT: The condition of capture is the specified event occurred. + * @arg TMRA_CAPT_COND_TRIGR: The condition of capture is a rising edge is sampled on TRIG. + * @arg TMRA_CAPT_COND_TRIGF: The condition of capture is a falling edge is sampled on TRIG. + * @retval None + */ +void TMRA_SetCaptCond(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Cond) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32CCONRAddr), TMRA_CAPT_COND_ALL, u32Cond); +} + +/** + * @brief Specifies the hardware trigger condition of TMRA according to the specified parameters + * in the structure stc_tmra_trig_cond_t. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] pstcCond Pointer to a stc_tmra_trig_cond_t structure value that contains \ + * the configuration information of hardware trigger condition. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCond == NULL. + */ +en_result_t TMRA_SetTrigCond(M4_TMRA_TypeDef *TMRAx, const stc_tmra_trig_cond_t *pstcCond) +{ + uint32_t u32StartCond; + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCond != NULL) + { + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32StartCond = (pstcCond->u32StartCond | pstcCond->u32StopCond | pstcCond->u32ClrCond) & TMRA_TRIG_COND_MSK; + WRITE_REG32(TMRAx->HCONR, u32StartCond); + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Set a default value for the hardware trigger condition configuration structure. + * @param [in] pstcCond Pointer to a stc_tmra_trig_cond_t structure value that contains \ + * the configuration information of hardware trigger condition. + * @retval An en_result_t enumeration type value. + * @arg Ok: No error occurred. + * @arg ErrorInvalidParameter: pstcCfg == NULL. + */ +en_result_t TMRA_TrigCondStructInit(stc_tmra_trig_cond_t *pstcCond) +{ + en_result_t enRet = ErrorInvalidParameter; + + if (pstcCond != NULL) + { + pstcCond->u32StartCond = TMRA_START_COND_INVALID; + pstcCond->u32StopCond = TMRA_STOP_COND_INVALID; + pstcCond->u32ClrCond = TMRA_CLR_COND_INVALID; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Specifies the event for specified usage. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8EvtUsage Usage of the event. + * This parameter can be a value of @ref TMRA_Event_Usage + * @arg TMRA_EVENT_USAGE_CNT: The specified event is used for counting. + * @arg TMRA_EVENT_USAGE_CAPT: The specified event is used for capturing. + * @param [in] enEvent An en_event_src_t enumeration type value. + * @retval None + * @note Correspondence of TMRA instances and the event setting registers is as follows: + * TMRA unit USAGE_CNT USAGE_CAPT + * ---------------------------------------------------------- + * TMRA uint1 | TMRA_HTSSR0 | TMRA_HTSSR1 + * TMRA uint2 | TMRA_HTSSR1 | TMRA_HTSSR0 + * TMRA uint3 | TMRA_HTSSR2 | TMRA_HTSSR3 + * TMRA uint4 | TMRA_HTSSR3 | TMRA_HTSSR2 + * TMRA uint5 | TMRA_HTSSR0 | TMRA_HTSSR1 + * TMRA uint6 | TMRA_HTSSR1 | TMRA_HTSSR0 + * TMRA uint7 | TMRA_HTSSR2 | TMRA_HTSSR3 + * TMRA uint8 | TMRA_HTSSR3 | TMRA_HTSSR2 + * TMRA uint9 | TMRA_HTSSR0 | TMRA_HTSSR1 + * TMRA uint10 | TMRA_HTSSR1 | TMRA_HTSSR0 + * TMRA uint11 | TMRA_HTSSR2 | TMRA_HTSSR3 + * TMRA uint12 | TMRA_HTSSR3 | TMRA_HTSSR2 + */ +void TMRA_SetTriggerSrc(M4_TMRA_TypeDef *TMRAx, uint8_t u8EvtUsage, en_event_src_t enEvent) +{ + uint32_t u32Idx; + uint32_t u32HTSSRAddr; + uint32_t au32CaptEventAddr[] = {TMRA_HTSSR1_ADDR, TMRA_HTSSR0_ADDR, \ + TMRA_HTSSR3_ADDR, TMRA_HTSSR2_ADDR}; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_EVT_USAGE(u8EvtUsage)); + + u32Idx = TMRA_IDX(TMRAx) % TMRA_CH_COUNT; + if (u8EvtUsage == TMRA_EVENT_USAGE_CNT) + { + u32HTSSRAddr = (uint32_t)&M4_AOS->TMRA_HTSSR0 + u32Idx * 4U; + } + else + { + u32HTSSRAddr = au32CaptEventAddr[u32Idx]; + } + + MODIFY_REG32(RW_MEM32(u32HTSSRAddr), TMRA_TRIG_EVENT_MSK, enEvent); +} + +/** + * @brief Enable or disable common trigger event for the specified usage. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8EvtUsage Usage of the event. + * This parameter can be a value of @ref TMRA_Event_Usage + * @arg TMRA_EVENT_USAGE_CNT: The specified event is used for counting. + * @arg TMRA_EVENT_USAGE_CAPT: The specified event is used for capturing. + * @param [in] u32ComTrig Common trigger event enable bit mask. + * This parameter can be values of @ref TMRA_Common_Trigger_Sel + * @arg TMRA_COM_TRIG1: Common trigger 1. + * @arg TMRA_COM_TRIG2: Common trigger 2. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified common trigger. + * @arg Disable: Disable the specified common trigger. + * @retval None + */ +void TMRA_ComTriggerCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8EvtUsage, \ + uint32_t u32ComTrig, en_functional_state_t enNewState) +{ + uint32_t u32Idx; + uint32_t u32HTSSRAddr; + uint32_t au32CaptEventAddr[] = {TMRA_HTSSR1_ADDR, TMRA_HTSSR0_ADDR, \ + TMRA_HTSSR3_ADDR, TMRA_HTSSR2_ADDR}; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_EVT_USAGE(u8EvtUsage)); + DDL_ASSERT(IS_TMRA_COM_TRIGGER(u32ComTrig)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Idx = TMRA_IDX(TMRAx) % TMRA_CH_COUNT; + if (u8EvtUsage == TMRA_EVENT_USAGE_CNT) + { + u32HTSSRAddr = (uint32_t)&M4_AOS->TMRA_HTSSR0 + u32Idx * 4U; + } + else + { + u32HTSSRAddr = au32CaptEventAddr[u32Idx]; + } + + if (enNewState == Enable) + { + SET_REG32_BIT(RW_MEM32(u32HTSSRAddr), u32ComTrig); + } + else + { + CLEAR_REG32_BIT(RW_MEM32(u32HTSSRAddr), u32ComTrig); + } +} + +/** + * @brief Configures cache function. Specifies the cache condition of compare value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be one of the following values of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @param [in] u32CacheCond Cache condition of the specified TMRA unit. + * This parameter can be a value of @ref TMRA_Cmp_Value_Cache_Condition + * @arg TIEMRA_CACHE_POS_OVF_CLR: This configuration value applies to non-triangular wave counting mode. \ + * When counting overflow or underflow or counting register was cleared, \ + * transfer CMPARm(m=2,4) to CMPARn(n=1,3). + * @arg TMRA_CACHE_POS_TW_PEAK: In triangle wave count mode, when count reached peak, \ + * transfer CMMARm(m=2,4) to CMMARn(n=1,3). + * @arg TMRA_CACHE_POS_TW_VALLEY: In triangle wave count mode, when count reached valley, \ + * transfer CMMARm(m=2,4) to CMMARn(n=1,3). + * @retval None + */ +void TMRA_CmpValCacheConfig(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32CacheCond) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT((u8TmrCh == TMRA_CH_1) || (u8TmrCh == TMRA_CH_3)); + DDL_ASSERT(IS_TMRA_CACHE_COND(u32CacheCond)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32BCONRAddr), TMRA_CACHE_COND_MSK, u32CacheCond); +} + +/** + * @brief Enable or disable the compare value function.. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be one of the following values of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the comparison reference value function. + * @arg Disable: Disable the comparison reference value function. + * @retval None + */ +void TMRA_CmpValCacheCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, en_functional_state_t enNewState) +{ + uint32_t u32BCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT((u8TmrCh == TMRA_CH_1) || (u8TmrCh == TMRA_CH_3)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32BCONRAddr = (uint32_t)&TMRAx->BCONR1 + (uint32_t)u8TmrCh * 4U; + BIT_BAND(u32BCONRAddr, TMRA_BCONR_BEN_POS) = (uint32_t)enNewState; +} + +/** + * @brief Specifies the operation when counting overflow/underflow. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32OvfOp The operation when count overflow/underflow. + * @arg TMRA_OVF_CNT_CONTINUE: When counting overflow(or underflow), counting continue. + * @arg TMRA_OVF_CNT_STOP: When count overflow(or underflow), counting stop. + * @retval None + */ +void TMRA_SetOvfOperation(M4_TMRA_TypeDef *TMRAx, uint32_t u32OvfOp) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_OVF_OPERATION(u32OvfOp)); + MODIFY_REG32(TMRAx->BCSTR, TMRA_BCSTR_OVSTP, u32OvfOp); +} + +/** + * @brief Enable or disable synchronous-start. When an even unit enables synchronous-start function, \ + * start the symmetric odd unit can start the even unit at the same time. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_2: TMRA unit 2 instance register base. + * @arg M4_TMRA_4: TMRA unit 4 instance register base. + * @arg M4_TMRA_6: TMRA unit 6 instance register base. + * @arg M4_TMRA_8: TMRA unit 8 instance register base. + * @arg M4_TMRA_10: TMRA unit 10 instance register base. + * @arg M4_TMRA_12: TMRA unit 12 instance register base. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the synchronous start. + * @arg Disable: Disable the synchronous start. + * @retval None + * @note Only even units can be enabled/disabled synchronous-start function. + * @note Symmetric units: uint 1 and 2; uint 3 and 4; ...; uint 11 and 12. + */ +void TMRA_SyncStartCmd(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_TMRA_EVEN_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32Addr = (uint32_t)&TMRAx->BCSTR; + BIT_BAND(u32Addr, TMRA_BCSTR_SYNST_POS) = (uint32_t)enNewState; +} + +/** + * @brief Enable of disable the specified interrupts of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32IntType The interrupt type of TMRA. Set this parameter to 0xFFFFFFFF to select all interrupts. + * This parameter can be values of @ref TMRA_Interrupt_Type + * @arg TMRA_INT_OVF: Count overflow interrupt. + * @arg TMRA_INT_UNF: Count underflow interrupt. + * @arg TMRA_INT_CMP_CH1: Compare-match interrupt of channel 1. + * @arg TMRA_INT_CMP_CH2: Compare-match interrupt of channel 2. + * @arg TMRA_INT_CMP_CH3: Compare-match interrupt of channel 3. + * @arg TMRA_INT_CMP_CH4: Compare-match interrupt of channel 4. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified interrupts. + * @arg Disable: Disable the specified interrupts. + * @retval None + */ +void TMRA_IntCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32IntType, en_functional_state_t enNewState) +{ + uint32_t u32BCSTR; + uint32_t u32ICONR; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32IntType &= TMRA_INT_ALL; + u32BCSTR = u32IntType & TMRA_BCSTR_INT_MSK; + u32ICONR = u32IntType >> 16U; + if (enNewState == Enable) + { + SET_REG32_BIT(TMRAx->BCSTR, u32BCSTR); + SET_REG32_BIT(TMRAx->ICONR, u32ICONR); + } + else + { + CLEAR_REG32_BIT(TMRAx->BCSTR, u32BCSTR); + CLEAR_REG32_BIT(TMRAx->ICONR, u32ICONR); + } +} + +/** + * @brief Enable of disable the specified event of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32EvtType The event type of TMRA. Set this parameter to 0xFFFF to select all events. + * This parameter can be values of @ref TMRA_Event_Type + * @arg TMRA_EVENT_CMP_CH1: Compare-match event of channel 1. + * @arg TMRA_EVENT_CMP_CH2: Compare-match event of channel 2. + * @arg TMRA_EVENT_CMP_CH3: Compare-match event of channel 3. + * @arg TMRA_EVENT_CMP_CH4: Compare-match event of channel 4. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified event. + * @arg Disable: Disable the specified event. + * @retval None + */ +void TMRA_EventCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32EvtType, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32EvtType &= TMRA_EVENT_ALL; + if (enNewState == Enable) + { + SET_REG32_BIT(TMRAx->ECONR, u32EvtType); + } + else + { + CLEAR_REG32_BIT(TMRAx->ECONR, u32EvtType); + } +} + +/** + * @brief Get the specified flag's status. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32Flag The status flags of TMRA. + * This parameter can be values of @ref TMRA_Status_Flag + * @arg TMRA_FLAG_OVF: Count overflow flag. + * @arg TMRA_FLAG_UNF: Count underflow flag. + * @arg TMRA_FLAG_CMP_CH1: Compare-match flag of channel 1. + * @arg TMRA_FLAG_CMP_CH2: Compare-match flag of channel 2. + * @arg TMRA_FLAG_CMP_CH3: Compare-match flag of channel 3. + * @arg TMRA_FLAG_CMP_CH4: Compare-match flag of channel 4. + * @retval An en_flag_status_t enumeration type value. + * @arg Set: At least one of the specified flags is set. + * @arg Reset: None of the specified flags is set. + */ +en_flag_status_t TMRA_GetStatus(const M4_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + uint32_t u32BCSTR; + uint32_t u32STFLR; + en_flag_status_t enFlag = Reset; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32Flag &= TMRA_FLAG_ALL; + u32BCSTR = READ_REG32_BIT(TMRAx->BCSTR, (u32Flag & TMRA_BCSTR_FLAG_MSK)); + u32STFLR = READ_REG32_BIT(TMRAx->STFLR, (u32Flag >> 16U)); + + if ((u32BCSTR != 0U) || (u32STFLR != 0U)) + { + enFlag = Set; + } + + return enFlag; +} + +/** + * @brief Clear the specified flags' status. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32Flag The status flags of TMRA. Set this parameter to 0xFFFFFFFF to select all status flags. + * This parameter can be values of @ref TMRA_Status_Flag + * @arg TMRA_FLAG_OVF: Count overflow flag. + * @arg TMRA_FLAG_UNF: Count underflow flag. + * @arg TMRA_FLAG_CMP_CH1: Count match flag of channel 1. + * @arg TMRA_FLAG_CMP_CH2: Count match flag of channel 2. + * @arg TMRA_FLAG_CMP_CH3: Count match flag of channel 3. + * @arg TMRA_FLAG_CMP_CH4: Count match flag of channel 4. + * @retval None + */ +void TMRA_ClrStatus(M4_TMRA_TypeDef *TMRAx, uint32_t u32Flag) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + + u32Flag &= TMRA_FLAG_ALL; + TMRAx->BCSTR &= (uint32_t)(~(u32Flag & TMRA_BCSTR_FLAG_MSK)); + TMRAx->STFLR &= (uint32_t)(~(u32Flag >> 16U)); +} + +/** + * @brief Start the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @retval None + */ +void TMRA_Start(M4_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + SET_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_START); +} + +/** + * @brief Stop the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @retval None + */ +void TMRA_Stop(M4_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + CLEAR_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_START); +} + +/** + * @brief Specifies the counting direction for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32CntDir Count direction. + * This parameter can be a value of @ref TMRA_Count_Direction + * @arg TMRA_DIR_DOWN: TMRA count down. + * @arg TMRA_DIR_UP: TMRA count up. + * @retval None + */ +void TMRA_SetCntDir(M4_TMRA_TypeDef *TMRAx, uint32_t u32CntDir) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_DIR(u32CntDir)); + MODIFY_REG32(TMRAx->BCSTR, TMRA_BCSTR_DIR, u32CntDir); +} + +/** + * @brief Specifies the counting mode for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32CntMode Count mode. + * This parameter can be a value of @ref TMRA_Count_Mode + * @arg TMRA_MODE_SAWTOOTH: Count mode is sawtooth wave. + * @arg TMRA_MODE_TRIANGLE: Count mode is triangle wave. + * @retval None + */ +void TMRA_SetCntMode(M4_TMRA_TypeDef *TMRAx, uint32_t u32CntMode) +{ + uint32_t u32Addr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CNT_MODE(u32CntMode)); + + u32Addr = (uint32_t)&TMRAx->BCSTR; + BIT_BAND(u32Addr, TMRA_BCSTR_SYNST_POS) = (uint32_t)u32CntMode; +} + +/** + * @brief Specifies the divider of PCLK when the clock source is PCLK. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32ClkDiv The clock source division. + * This parameter can be a value of @ref TMRA_PCLK_Divider + * @arg TMRA_PCLK_DIV1: The clock source of TMRA is PCLK. + * @arg TMRA_PCLK_DIV2: The clock source of TMRA is PCLK / 2. + * @arg TMRA_PCLK_DIV4: The clock source of TMRA is PCLK / 4. + * @arg TMRA_PCLK_DIV8: The clock source of TMRA is PCLK / 8. + * @arg TMRA_PCLK_DIV16: The clock source of TMRA is PCLK / 16. + * @arg TMRA_PCLK_DIV32: The clock source of TMRA is PCLK / 32. + * @arg TMRA_PCLK_DIV64: The clock source of TMRA is PCLK / 64. + * @arg TMRA_PCLK_DIV128: The clock source of TMRA is PCLK / 128. + * @arg TMRA_PCLK_DIV256: The clock source of TMRA is PCLK / 256. + * @arg TMRA_PCLK_DIV512: The clock source of TMRA is PCLK / 512. + * @arg TMRA_PCLK_DIV1024: The clock source of TMRA is PCLK / 1024. + * @retval None + */ +void TMRA_SetPCLKDiv(M4_TMRA_TypeDef *TMRAx, uint32_t u32ClkDiv) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_PCLK_DIV(u32ClkDiv)); + MODIFY_REG32(TMRAx->BCSTR, TMRA_BCSTR_CKDIV, u32ClkDiv); +} + +/** + * @brief Get the counting direction of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA1 ~ M4_TMRA12: TMRA unit 1 ~ 12 instance register base. + * @retval An uint32_t type value of counting direction. + * @arg TMRA_DIR_DOWN: TMRA count goes down. + * @arg TMRA_DIR_UP: TMRA count goes up. + */ +uint32_t TMRA_GetCntDir(const M4_TMRA_TypeDef *TMRAx) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + return READ_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_DIR); +} + +/** + * @brief Specifies the clock source for the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA1 ~ M4_TMRA12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32ClkSrc The clock source of TMRA. + * This parameter can be values of @ref TMRA_Clock_Source + * @retval None + */ +void TMRA_SetClkSrc(M4_TMRA_TypeDef *TMRAx, uint32_t u32ClkSrc) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + WRITE_REG32(TMRAx->HCUPR, (u32ClkSrc & TMRA_CLK_HW_UP_ALL)); + WRITE_REG32(TMRAx->HCDOR, ((u32ClkSrc & TMRA_CLK_HW_DOWN_ALL) >> 16U)); +} + +/** + * @brief Enable or disable the specified hardware clock source of the specified TMRA unit. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA1 ~ M4_TMRA12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u32HwClkSrc The hardware clock source of TMRA. + * This parameter can be values of @ref TMRA_Clock_Source except TMRA_CLK_PCLK + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified hardware clock source. + * @arg Disable: Disable the specified hardware clock source. + * @retval None + */ +void TMRA_HwClkSrcCmd(M4_TMRA_TypeDef *TMRAx, uint32_t u32HwClkSrc, en_functional_state_t enNewState) +{ + const uint32_t u32HwCntUpClk = u32HwClkSrc & TMRA_CLK_HW_UP_ALL; + const uint32_t u32HwCntDownClk = (u32HwClkSrc & TMRA_CLK_HW_DOWN_ALL) >> 16U; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + if (enNewState == Enable) + { + SET_REG32_BIT(TMRAx->HCUPR, u32HwCntUpClk); + SET_REG32_BIT(TMRAx->HCDOR, u32HwCntDownClk); + } + else + { + CLEAR_REG32_BIT(TMRAx->HCUPR, u32HwCntUpClk); + CLEAR_REG32_BIT(TMRAx->HCDOR, u32HwCntDownClk); + } +} + +/** + * @brief Specifies the PWM polarity when counting start. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Polarity Polarity of PWM output. + * This parameter can be a value of @ref TMRA_PWM_Start_Polarity + * @arg TMRA_PWM_START_LOW: The polarity of PWM output is low. + * @arg TMRA_PWM_START_HIGH: The polarity of PWM output is high. + * @arg TMRA_PWM_START_KEEP: The polarity of PWM output keeps the current polarity. + * @retval None + */ +void TMRA_PWM_SetStartPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_PWM_START_POLARITY(u32Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32PCONRAddr), TMRA_PCONR_STAC, u32Polarity); +} + +/** + * @brief Specifies the PWM polarity when counting stop. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Polarity Polarity of PWM output. + * This parameter can be a value of @ref TMRA_PWM_Stop_Polarity + * @arg TMRA_PWM_STOP_LOW: The polarity of PWM output is low. + * @arg TMRA_PWM_STOP_HIGH: The polarity of PWM output is high. + * @arg TMRA_PWM_STOP_KEEP: The polarity of PWM output keeps the current polarity. + * @retval None + */ +void TMRA_PWM_SetStopPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_PWM_STOP_POLARITY(u32Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32PCONRAddr), TMRA_PCONR_STPC, u32Polarity); +} + +/** + * @brief Specifies the PWM polarity when counting matches the compare reference value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Polarity Polarity of PWM output. + * This parameter can be a value of @ref TMRA_PWM_Match_Cmp_Polarity + * @arg TMRA_PWM_CMP_LOW: The polarity of PWM output is low. + * @arg TMRA_PWM_CMP_HIGH: The polarity of PWM output is high. + * @arg TMRA_PWM_CMP_KEEP: The polarity of PWM output keeps the current polarity. + * @arg TMRA_PWM_CMP_REVERSE: PWM output reverses the current polarity. + * @retval None + */ +void TMRA_PWM_SetMatchCmpPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_PWM_CMP_POLARITY(u32Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32PCONRAddr), TMRA_PCONR_CMPC, u32Polarity); +} + +/** + * @brief Specifies the PWM polarity when counting matches the period reference value. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Polarity Polarity of PWM output. + * This parameter can be a value of @ref TMRA_PWM_Match_Period_Polarity + * @arg TMRA_PWM_PERIOD_LOW: The polarity of PWM output is low. + * @arg TMRA_PWM_PERIOD_HIGH: The polarity of PWM output is high. + * @arg TMRA_PWM_PERIOD_KEEP: The polarity of PWM output keeps the current polarity. + * @arg TMRA_PWM_PERIOD_REVERSE: PWM output reverses the current polarity. + * @retval None + */ +void TMRA_PWM_SetMatchPeriodPolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_PWM_PERIOD_POLARITY(u32Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32PCONRAddr), TMRA_PCONR_PERC, u32Polarity); +} + +/** + * @brief Specifies the PWM polarity when next cycle start. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32Polarity Polarity of PWM output. + * This parameter can be a value of @ref TMRA_PWM_Force_Polarity + * @arg TMRA_PWM_FORCE_INVALID: Force polarity is invalid. + * @arg TMRA_PWM_FORCE_LOW: Force the PWM output low at the beginning of the next cycle. \ + * The beginning of the next cycle: overflow position or underflow position \ + * of sawtooth wave; valley position of triangle wave. + * @arg TMRA_PWM_FORCE_HIGH: Force the PWM output high at the beginning of the next cycle. \ + * The beginning of the next cycle: overflow position or underflow position \ + * of sawtooth wave; valley position of triangle wave. + * @retval None + */ +void TMRA_PWM_SetForcePolarity(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32Polarity) +{ + uint32_t u32PCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_TMRA_PWM_FORCE_POLARITY(u32Polarity)); + + u32PCONRAddr = (uint32_t)&TMRAx->PCONR1 + (uint32_t)u8TmrCh * 4U; + MODIFY_REG32(RW_MEM32(u32PCONRAddr), TMRA_PCONR_FORC, u32Polarity); +} + +/** + * @brief Specifies the capture condition for the specified channel. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32CaptCond The capture condition. Set this parameter to 0xFFFF to select all the conditions of capturing start. + * This parameter can be values of @ref TMRA_Channel_Capture_Condition + * @arg TMRA_CAPT_COND_PWMR: The condition of capture is a rising edge is sampled on PWM(pin). + * @arg TMRA_CAPT_COND_PWMF: The condition of capture is a falling edge is sampled on PWM(pin). + * @arg TMRA_CAPT_COND_EVENT: The condition of capture is the specified event occurred. + * @arg TMRA_CAPT_COND_TRIGR: The condition of capture is a rising edge is sampled on TRIG. + * @arg TMRA_CAPT_COND_TRIGF: The condition of capture is a falling edge is sampled on TRIG. + * @param [in] enNewState An @ref en_functional_state_t value. + * @arg Enable: Enable the sepcified capture conditions. + * @arg Disable: Disable the sepcified capture conditions. + * @retval None + */ +void TMRA_CaptCondCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32CaptCond, en_functional_state_t enNewState) +{ + uint32_t u32CCONRAddr; + + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_TMRA_CH(u8TmrCh)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32CaptCond &= TMRA_CAPT_COND_ALL; + u32CCONRAddr = (uint32_t)&TMRAx->CCONR1 + (uint32_t)u8TmrCh * 4U; + if (enNewState == Enable) + { + SET_REG32_BIT(RW_MEM32(u32CCONRAddr), u32CaptCond); + } + else + { + CLEAR_REG32_BIT(RW_MEM32(u32CCONRAddr), u32CaptCond); + } +} + +/** + * @brief Enable or disable the specified hardware start condition. + * @param [in] TMRAx Pointer to TMRA instance register base. + * This parameter can be a value of the following: + * @arg M4_TMRA_1 ~ M4_TMRA_12: TMRA unit 1 ~ 12 instance register base. + * @param [in] u8TmrCh TMRA channel number. + * This parameter can be a value of @ref TMRA_Channel + * @arg TMRA_CH_1: Channel 1 of TMRA. + * @arg TMRA_CH_2: Channel 2 of TMRA. + * @arg TMRA_CH_3: Channel 3 of TMRA. + * @arg TMRA_CH_4: Channel 4 of TMRA. + * @param [in] u32TrigCond The trigger condition. + * This parameter can be a value of: + * @ref TMRA_Hardware_Start_Condition + * @ref TMRA_Hardware_Stop_Condition + * @ref TMRA_Hardware_Clear_Condition + * @arg TMRA_START_COND_TRIGR: 1. Sync start is invalid: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. \ + * 2. Sync start is valid: The condition is that a rising edge is sampled on TRIG of the symmetric TMRA unit. + * @arg TMRA_START_COND_TRIGF: 1. Sync start is invalid: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. \ + * 2. Sync start is valid: The condition is that a falling edge is sampled on TRIG of the symmetric TMRA unit. + * @arg TMRA_START_COND_EVENT: The condition is that the event which is set in register TMRA_HTSSR0 has occurred. + * @arg TMRA_STOP_COND_TRIGR: The condition is that a rising edge is sampled on pin TRIG of the current TMRA unit. + * @arg TMRA_STOP_COND_TRIGF: The condition is that a falling edge is sampled on pin TRIG of the current TMRA unit. + * @arg TMRA_STOP_COND_EVENT: The condition is that the event which is set in register TMRA_HTSSR0 has occurred. + * @arg TMRA_CLR_COND_TRIGR: The condition is that a rising edge is sampled on TRIG of the current TMRA unit. + * @arg TMRA_CLR_COND_TRIGF: The condition is that a falling edge is sampled on TRIG of the current TMRA unit. + * @arg TMRA_CLR_COND_EVENT: The condition is that the event which is set in register TMRA_HTSSR0 has occurred. + * @arg TMRA_CLR_COND_SYM_TRIGR: The condition is that a rising edge is sampled on TRIG of the symmetric unit. + * @arg TMRA_CLR_COND_SYM_TRIGF: The condition is that a falling edge is sampled on TRIG of the symmetric unit. + * @arg TMRA_CLR_COND_PWM3R: The condition is that a rising edge is sampled on PWM3 of the current TMRA unit. + * @arg TMRA_CLR_COND_PWM3F: The condition is that a falling edge is sampled on PWM3 of the current TMRA unit. + * @param [in] enNewState An en_functional_state_t enumeration type value. + * @arg Enable: Enable the specified hardware start condition. + * @arg Disable: Disable the specified hardware start condition. + * @retval None + */ +void TMRA_TrigCondCmd(M4_TMRA_TypeDef *TMRAx, uint8_t u8TmrCh, uint32_t u32TrigCond, en_functional_state_t enNewState) +{ + DDL_ASSERT(IS_TMRA_UNIT(TMRAx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + u32TrigCond &= TMRA_TRIG_COND_MSK; + if (enNewState == Enable) + { + SET_REG32_BIT(TMRAx->HCONR, u32TrigCond); + } + else + { + CLEAR_REG32_BIT(TMRAx->HCONR, u32TrigCond); + } +} + +/** + * @} + */ + +#endif /* DDL_TMRA_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_trng.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_trng.c new file mode 100644 index 0000000000000000000000000000000000000000..d75374fd7f6957c0e1277dae2ad16d31ad46c9c2 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_trng.c @@ -0,0 +1,182 @@ +/** + ******************************************************************************* + * @file hc32f4a0_trng.c + * @brief This file provides firmware functions to manage the True Random + * Number Generator(TRNG). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Heqb First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_trng.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_TRNG TRNG + * @brief TRNG Driver Library + * @{ + */ + +#if (DDL_TRNG_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup TRNG_Local_Macros TRNG Local Macros + * @{ + */ +#define TRNG_TIMEOUT (20000UL) + +/** + * @defgroup TRNG_Check_Parameters_Validity TRNG Check Parameters Validity + * @{ + */ +#define IS_VALID_SHIFT_CNT(x) \ +( ((x) == TRNG_SHIFT_COUNT_32) || \ + ((x) == TRNG_SHIFT_COUNT_64) || \ + ((x) == TRNG_SHIFT_COUNT_128) || \ + ((x) == TRNG_SHIFT_COUNT_256)) + +#define IS_VALID_RELOAD(x) \ +( ((x) == TRNG_RELOAD_ENABLE) || \ + ((x) == TRNG_RELOAD_DISABLE)) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup TRNG_Global_Functions TRNG Global Functions + * @{ + */ + +/** + * @brief Set shift times + * @param [in] u32ShiftCount Config the shift times. + * This parameter can be a value of the following: + * @arg TRNG_SHIFT_COUNT_32 Shift 32 times + * @arg TRNG_SHIFT_COUNT_64 Shift 64 times + * @arg TRNG_SHIFT_COUNT_128 Shift 128 times + * @arg TRNG_SHIFT_COUNT_256 Shift 256 times + * @retval None + */ +void TRNG_SetShiftCnt(uint32_t u32ShiftCount) +{ + DDL_ASSERT(IS_VALID_SHIFT_CNT(u32ShiftCount)); + MODIFY_REG32(M4_TRNG->MR, TRNG_MR_CNT, u32ShiftCount); +} + +/** + * @brief Enable or disable load new value + * @param [in] u32ReloadCmd Enable or disable load new value. + * This parameter can be a value of the following: + * @arg TRNG_RELOAD_ENABLE Enable the function + * @arg TRNG_RELOAD_DISABLE Disable the function + * @retval None + */ +void TRNG_ReloadCmd(uint32_t u32ReloadCmd) +{ + DDL_ASSERT(IS_VALID_RELOAD(u32ReloadCmd)); + MODIFY_REG32(M4_TRNG->MR, TRNG_MR_LOAD, u32ReloadCmd); +} + +/** + * @brief Start TRNG and get random number + * @param [in] au32Random The destination address where the random number will be stored. + * @retval Ok: Success + * ErrorTimeout: Process timeout + * ErrorInvalidParameter: Parameter error + * @note Please pass in an array of 64 bits or more + */ +en_result_t TRNG_Generate(uint32_t au32Random[]) +{ + en_result_t enRet = ErrorInvalidParameter; + uint32_t u32TimeCount = 0U; + if(au32Random != NULL) + { + enRet = Ok; + /* Enable TRNG circuit. */ + SET_REG32_BIT(M4_TRNG->CR, TRNG_CR_EN); + /* Start TRNG */ + SET_REG32_BIT(M4_TRNG->CR, TRNG_CR_RUN); + /* Wait for the TRNG to stop */ + while(READ_REG32_BIT(M4_TRNG->CR, TRNG_CR_RUN) == 1U) + { + if(u32TimeCount++ > TRNG_TIMEOUT) + { + enRet = ErrorTimeout; + break; + } + } + if(enRet == Ok) + { + /* Get the random number. */ + au32Random[0U] = READ_REG32(M4_TRNG->DR0); + au32Random[1U] = READ_REG32(M4_TRNG->DR1); + /* Disable TRNG circuit. */ + CLEAR_REG32_BIT(M4_TRNG->CR, TRNG_CR_EN); + } + } + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_TRNG_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_usart.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..0b443423600756698650d44f3c1ec7b8224c35c8 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_usart.c @@ -0,0 +1,2710 @@ +/** + ******************************************************************************* + * @file hc32f4a0_usart.c + * @brief This file provides firmware functions to manage the USART(Universal + * Synchronous/Asynchronous Receiver Transmitter). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Hongjh First version + 2020-07-03 Hongjh Add doxygen group:USART_Local_Functions. + 2020-08-25 Hongjh The variable f32Err un-initializes an + unnecessary assignment. + 2020-10-19 Hongjh Modify USART initialization function. + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_usart.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_USART USART + * @brief USART Driver Library + * @{ + */ + +#if (DDL_USART_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup USART_Local_Macros USART Local Macros + * @{ + */ + +/** + * @defgroup USART_Check_Parameters_Validity USART Check Parameters Validity + * @{ + */ + +#define IS_USART_INSTANCE(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x)) || \ + (M4_USART5 == (x)) || \ + (M4_USART6 == (x)) || \ + (M4_USART7 == (x)) || \ + (M4_USART8 == (x)) || \ + (M4_USART9 == (x)) || \ + (M4_USART10 == (x))) + +#define IS_USART_SMARTCARD_INSTANCE(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x)) || \ + (M4_USART6 == (x)) || \ + (M4_USART7 == (x)) || \ + (M4_USART8 == (x)) || \ + (M4_USART9 == (x))) + +#define IS_USART_LIN_INSTANCE(x) \ +( (M4_USART5 == (x)) || \ + (M4_USART10 == (x))) + +#define IS_USART_STOPMODE_INSTANCE(x) (M4_USART1 == (x)) + +#define IS_USART_TIMEOUT_INSTANCE(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART5 == (x)) || \ + (M4_USART6 == (x))) + +#define IS_USART_FRACTION_INSTANCE(x) \ +( (M4_USART1 == (x)) || \ + (M4_USART2 == (x)) || \ + (M4_USART3 == (x)) || \ + (M4_USART4 == (x)) || \ + (M4_USART6 == (x)) || \ + (M4_USART7 == (x)) || \ + (M4_USART8 == (x)) || \ + (M4_USART9 == (x))) + +#define IS_USART_FUNCTION(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~USART_FUNCTION_MASK)))) + +#define IS_USART_LIN_FUNCTION(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~USART_LIN_FUNCTION_MASK)))) + +#define IS_USART_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~USART_FLAG_MASK)))) + +#define IS_USART_CLEAR_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & (~USART_CLEAR_FLAG_MASK)))) + +#define IS_USART_TRANSMISSION_TYPE(x) \ +( (USART_TRANSMISSION_ID == (x)) || \ + (USART_TRANSMISSION_DATA == (x))) + +#define IS_USART_PARITY_CONTROL(x) \ +( (USART_PARITY_ODD == (x)) || \ + (USART_PARITY_EVEN == (x)) || \ + (USART_PARITY_NONE == (x))) + +#define IS_USART_DATA_WIDTH(x) \ +( (USART_DATA_LENGTH_8BIT == (x)) || \ + (USART_DATA_LENGTH_9BIT == (x))) + +#define IS_USART_NOISE_FILTER(x) \ +( (USART_NOISE_FILTER_ENABLE == (x)) || \ + (USART_NOISE_FILTER_DISABLE == (x))) + +#define IS_USART_OVERSAMPLING_BITS(x) \ +( (USART_OVERSAMPLING_8BIT == (x)) || \ + (USART_OVERSAMPLING_16BIT == (x))) + +#define IS_USART_SIGNIFICANT_BIT(x) \ +( (USART_MSB == (x)) || \ + (USART_LSB == (x))) + +#define IS_USART_SB_DETECT_POLARITY(x) \ +( (USART_SB_DETECT_LOW == (x)) || \ + (USART_SB_DETECT_FALLING == (x))) + +#define IS_USART_CLOCK_MODE(x) \ +( (USART_EXTCLK == (x)) || \ + (USART_INTERNCLK_OUTPUT == (x)) || \ + (USART_INTERNCLK_NONE_OUTPUT == (x))) + +#define IS_USART_SMARTCARD_CLOCK_MODE(x) \ +( (USART_INTERNCLK_OUTPUT == (x)) || \ + (USART_INTERNCLK_NONE_OUTPUT == (x))) + +#define IS_USART_CLKSYNC_CLOCK_MODE(x) \ +( (USART_EXTCLK == (x)) || \ + (USART_INTERNCLK_OUTPUT == (x))) + +#define IS_USART_STOP_BITS(x) \ +( (USART_STOPBIT_1BIT == (x)) || \ + (USART_STOPBIT_2BIT == (x))) + +#define IS_UART_DUPLEX_MODE(x) \ +( (USART_HALFDUPLEX_MODE == (x)) || \ + (USART_FULLDUPLEX_MODE == (x))) + +#define IS_USART_HWFLOWCTRL(x) \ +( (USART_HWFLOWCTRL_NONE == (x)) || \ + (USART_HWFLOWCTRL_CTS == (x)) || \ + (USART_HWFLOWCTRL_RTS == (x)) || \ + (USART_HWFLOWCTRL_RTS_CTS == (x))) + +#define IS_USART_PCLK_DIV(x) \ +( (USART_PCLK_DIV1 == (x)) || \ + (USART_PCLK_DIV4 == (x)) || \ + (USART_PCLK_DIV16 == (x)) || \ + (USART_PCLK_DIV64 == (x))) + +#define IS_USART_LIN_BMC_PCLK_DIV(x) \ +( (USART_LIN_BMC_PCLK_DIV1 == (x)) || \ + (USART_LIN_BMC_PCLK_DIV2 == (x)) || \ + (USART_LIN_BMC_PCLK_DIV4 == (x)) || \ + (USART_LIN_BMC_PCLK_DIV8 == (x))) + +#define IS_USART_STOPMODE_FILTER(x) \ +( (USART_STOP_MODE_FILTER_NONE == (x)) || \ + (USART_STOP_MODE_FILTER_WIDTH_LEVEL_1 == (x)) || \ + (USART_STOP_MODE_FILTER_WIDTH_LEVEL_2 == (x)) || \ + (USART_STOP_MODE_FILTER_WIDTH_LEVEL_3 == (x)) || \ + (USART_STOP_MODE_FILTER_WIDTH_LEVEL_4 == (x))) + +#define IS_USART_SMARTCARD_ETU_CLK(x) \ +( (USART_SC_ETU_CLK_32 == (x)) || \ + (USART_SC_ETU_CLK_64 == (x)) || \ + (USART_SC_ETU_CLK_128 == (x)) || \ + (USART_SC_ETU_CLK_256 == (x)) || \ + (USART_SC_ETU_CLK_372 == (x))) + +#define IS_USART_LIN_SEND_BREAK_MODE(x) \ +( (USART_LIN_SEND_BREAK_MODE_SBK == (x)) || \ + (USART_LIN_SEND_BREAK_MODE_TDR == (x))) + +#define IS_USART_LIN_DETECT_BREAK_LEN(x) \ +( (USART_LIN_DETECT_BREAK_10BIT == (x)) || \ + (USART_LIN_DETECT_BREAK_11BIT == (x))) + +#define IS_USART_LIN_SEND_BREAK_LEN(x) \ +( (USART_LIN_SEND_BREAK_10BIT == (x)) || \ + (USART_LIN_SEND_BREAK_11BIT == (x)) || \ + (USART_LIN_SEND_BREAK_13BIT == (x)) || \ + (USART_LIN_SEND_BREAK_14BIT == (x))) + +/** + * @} + */ + +/** + * @defgroup USART_Flag_Mask USART flag mask definition + * @{ + */ +#define USART_FLAG_MASK (USART_FLAG_PE | \ + USART_FLAG_FE | \ + USART_FLAG_ORE | \ + USART_FLAG_BE | \ + USART_FLAG_RXNE | \ + USART_FLAG_TC | \ + USART_FLAG_TXE | \ + USART_FLAG_RTOF | \ + USART_FLAG_LBD | \ + USART_FLAG_WKUP | \ + USART_FLAG_MPB) +/** + * @} + */ + +/** + * @defgroup USART_Clear_Flag_Mask USART clear flag mask definition + * @{ + */ +#define USART_CLEAR_FLAG_MASK (USART_CLEAR_FLAG_PE | \ + USART_CLEAR_FLAG_FE | \ + USART_CLEAR_FLAG_ORE | \ + USART_CLEAR_FLAG_RTOF | \ + USART_CLEAR_FLAG_BE | \ + USART_CLEAR_FLAG_WKUP | \ + USART_CLEAR_FLAG_LBD) +/** + * @} + */ + +/** + * @defgroup USART_function_Mask USART function mask definition + * @{ + */ +#define USART_FUNCTION_MASK (USART_RX | \ + USART_TX | \ + USART_RTO | \ + USART_INT_RX | \ + USART_INT_TC | \ + USART_INT_TXE | \ + USART_INT_RTO) +/** + * @} + */ + +/** + * @defgroup USART_LIN_function_Mask USART LIN function mask definition + * @{ + */ +#define USART_LIN_FUNCTION_MASK (USART_LIN | \ + USART_LIN_WKUP | \ + USART_LIN_BUSERR | \ + USART_LIN_INT_WKUP | \ + USART_LIN_INT_BREAK | \ + USART_LIN_INT_BUSERR) +/** + * @} + */ + +/** + * @defgroup USART_CR1_Clear_Flag_Mask USART register clear flag bits mask definition + * @{ + */ +#define USART_CR1_CLR_FLAG_MASK (USART_CR1_CPE | \ + USART_CR1_CORE | \ + USART_CR1_CFE | \ + USART_CR1_CRTOF | \ + USART_CR1_CBE | \ + USART_CR1_CWKUP | \ + USART_CR1_CLBD) +/** + * @} + */ + +/** + * @defgroup USART_CR2_Reserved_Bit USART CR2 register reserved bit 9/10 definition + * @{ + */ +#define USART_CR2_BIT9 (0x00000200UL) +#define USART_CR2_BIT10 (0x00000400UL) +/** + * @} + */ + +/** + * @defgroup USART_Clk_Frequency USART Clk Frequency + * @{ + */ +#define USART_DIV(INSTANCE) \ +( 1UL << (READ_REG32_BIT((INSTANCE)->PR, USART_PR_PSC) * 2UL)) + +#define USART_BMC_DIV(INSTANCE) \ +( 1UL << (READ_REG32_BIT((INSTANCE)->PR, USART_PR_LBMPSC) >> USART_PR_LBMPSC_POS)) + +#define PCLK_FREQ \ +( SystemCoreClock >> (READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS)) +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +/** + * @addtogroup USART_Local_Functions + * @{ + */ + +static en_result_t CalcUartBaudrate(const M4_USART_TypeDef *USARTx, + uint32_t u32UartClk, + uint32_t u32Baudrate, + uint32_t *pu32BrrVal, + uint32_t *pu32FractEn, + float32_t *pf32Err); +static en_result_t CalcClkSyncBaudrate(const M4_USART_TypeDef *USARTx, + uint32_t u32UsartClk, + uint32_t u32Baudrate, + uint32_t *pu32BrrVal, + uint32_t *pu32FractEn, + float32_t *pf32Err); +static en_result_t CalcSmartcardBaudrate(const M4_USART_TypeDef *USARTx, + uint32_t u32UartClk, + uint32_t u32Baudrate, + uint32_t *pu32BrrVal, + uint32_t *pu32FractEn, + float32_t *pf32Err); + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup USART_Global_Functions USART Global Functions + * @{ + */ + +/** + * @brief Initialize UART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] pstcInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL or baudrate set unsuccessfully + */ +en_result_t USART_UartInit(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_CLOCK_MODE(pstcInit->u32ClkMode)); + DDL_ASSERT(IS_USART_PARITY_CONTROL(pstcInit->u32Parity)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOP_BITS(pstcInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVERSAMPLING_BITS(pstcInit->u32OversamplingBits)); + DDL_ASSERT(IS_USART_SIGNIFICANT_BIT(pstcInit->u32BitDirection)); + DDL_ASSERT(IS_USART_NOISE_FILTER(pstcInit->u32NoiseFilterState)); + DDL_ASSERT(IS_USART_SB_DETECT_POLARITY(pstcInit->u32SbDetectPolarity)); + DDL_ASSERT(IS_USART_HWFLOWCTRL(pstcInit->u32HwFlowCtrl)); + + /* Disbale TX/RX && clear flag */ + WRITE_REG32(USARTx->CR1, USART_CR1_CLR_FLAG_MASK); + + /* Set CR2 */ + WRITE_REG32(USARTx->CR2, (USART_CR2_BIT9 | \ + USART_CR2_BIT10 | \ + pstcInit->u32ClkMode | + pstcInit->u32StopBit)); + + /* Set CR3 */ + WRITE_REG32(USARTx->CR3, pstcInit->u32HwFlowCtrl); + + /* Set CR1 */ + WRITE_REG32(USARTx->CR1, (pstcInit->u32Parity | \ + pstcInit->u32DataWidth | \ + pstcInit->u32OversamplingBits | \ + pstcInit->u32BitDirection | \ + pstcInit->u32NoiseFilterState | \ + pstcInit->u32SbDetectPolarity)); + + /* Set LBMC */ + WRITE_REG32(USARTx->LBMC, 0UL); + + if (USART_EXTCLK != pstcInit->u32ClkMode) + { + DDL_ASSERT(IS_USART_PCLK_DIV(pstcInit->u32PclkDiv)); + + /* Set PR */ + WRITE_REG32(USARTx->PR, pstcInit->u32PclkDiv); + + /* Set baudrate */ + enRet = USART_SetBaudrate(USARTx, pstcInit->u32Baudrate, NULL); + } + else + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Initialize UART half duplex function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] pstcInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL or baudrate set unsuccessfully + */ +en_result_t USART_HalfduplexInit(M4_USART_TypeDef *USARTx, + const stc_usart_uart_init_t *pstcInit) +{ + en_result_t enRet; + + enRet = USART_UartInit(USARTx, pstcInit); + if (Ok == enRet) + { + /* Set CR3: UART half duplex */ + SET_REG32_BIT(USARTx->CR3, USART_CR3_HDSEL); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_usart_uart_init_t to default values. + * @param [out] pstcInit Pointer to a @ref stc_usart_uart_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL + */ +en_result_t USART_UartStructInit(stc_usart_uart_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Baudrate = 9600UL; + pstcInit->u32ClkMode = USART_INTERNCLK_NONE_OUTPUT; + pstcInit->u32PclkDiv = USART_PCLK_DIV1; + pstcInit->u32Parity = USART_PARITY_NONE; + pstcInit->u32DataWidth = USART_DATA_LENGTH_8BIT; + pstcInit->u32StopBit = USART_STOPBIT_1BIT; + pstcInit->u32OversamplingBits = USART_OVERSAMPLING_16BIT; + pstcInit->u32BitDirection = USART_LSB; + pstcInit->u32NoiseFilterState = USART_NOISE_FILTER_DISABLE; + pstcInit->u32SbDetectPolarity = USART_SB_DETECT_FALLING; + pstcInit->u32HwFlowCtrl = USART_HWFLOWCTRL_NONE; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Initialize UART multiple processor function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] pstcInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL or baudrate set unsuccessfully + */ +en_result_t USART_MultiProcessorInit(M4_USART_TypeDef *USARTx, + const stc_usart_multiprocessor_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_CLOCK_MODE(pstcInit->u32ClkMode)); + DDL_ASSERT(IS_USART_DATA_WIDTH(pstcInit->u32DataWidth)); + DDL_ASSERT(IS_USART_STOP_BITS(pstcInit->u32StopBit)); + DDL_ASSERT(IS_USART_OVERSAMPLING_BITS(pstcInit->u32OversamplingBits)); + DDL_ASSERT(IS_USART_SIGNIFICANT_BIT(pstcInit->u32BitDirection)); + DDL_ASSERT(IS_USART_NOISE_FILTER(pstcInit->u32NoiseFilterState)); + DDL_ASSERT(IS_USART_SB_DETECT_POLARITY(pstcInit->u32SbDetectPolarity)); + DDL_ASSERT(IS_USART_HWFLOWCTRL(pstcInit->u32HwFlowCtrl)); + + /* Disbale TX/RX && clear flag */ + WRITE_REG32(USARTx->CR1, USART_CR1_CLR_FLAG_MASK); + + /* Set CR2 */ + WRITE_REG32(USARTx->CR2, (USART_CR2_MPE | \ + USART_CR2_BIT9 | \ + USART_CR2_BIT10 | \ + pstcInit->u32ClkMode | \ + pstcInit->u32StopBit)); + + /* Set CR3 */ + WRITE_REG32(USARTx->CR3, pstcInit->u32HwFlowCtrl); + + /* Set CR1 */ + WRITE_REG32(USARTx->CR1, (pstcInit->u32DataWidth | \ + pstcInit->u32OversamplingBits | \ + pstcInit->u32BitDirection | \ + pstcInit->u32NoiseFilterState | \ + pstcInit->u32SbDetectPolarity)); + + /* Set LBMC */ + WRITE_REG32(USARTx->LBMC, 0UL); + + if (USART_EXTCLK != pstcInit->u32ClkMode) + { + DDL_ASSERT(IS_USART_PCLK_DIV(pstcInit->u32PclkDiv)); + + /* Set PR */ + WRITE_REG32(USARTx->PR, pstcInit->u32PclkDiv); + + /* Set baudrate */ + enRet = USART_SetBaudrate(USARTx, pstcInit->u32Baudrate, NULL); + } + else + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_usart_multiprocessor_init_t to default values. + * @param [out] pstcInit Pointer to a @ref stc_usart_multiprocessor_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: the pointer pstcInit is NULL + */ +en_result_t USART_MultiProcessorStructInit(stc_usart_multiprocessor_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Baudrate = 9600UL; + pstcInit->u32ClkMode = USART_INTERNCLK_NONE_OUTPUT; + pstcInit->u32PclkDiv = USART_PCLK_DIV1; + pstcInit->u32DataWidth = USART_DATA_LENGTH_8BIT; + pstcInit->u32StopBit = USART_STOPBIT_1BIT; + pstcInit->u32OversamplingBits = USART_OVERSAMPLING_16BIT; + pstcInit->u32BitDirection = USART_LSB; + pstcInit->u32NoiseFilterState = USART_NOISE_FILTER_DISABLE; + pstcInit->u32SbDetectPolarity = USART_SB_DETECT_FALLING; + pstcInit->u32HwFlowCtrl = USART_HWFLOWCTRL_NONE; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Initialize LIN function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] pstcInit Pointer to a @ref stc_usart_lin_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: the pointer pstcInit is NULL or baudrate set unsuccessfully + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +en_result_t USART_LinInit(M4_USART_TypeDef *USARTx, + const stc_usart_lin_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_CLOCK_MODE(pstcInit->u32ClkMode)); + DDL_ASSERT(IS_USART_OVERSAMPLING_BITS(pstcInit->u32OversamplingBits)); + DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(pstcInit->u32DetectBreakLen)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(pstcInit->u32SendBreakLen)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MODE(pstcInit->u32SendBreakMode)); + + /* Disbale TX/RX && clear flag */ + WRITE_REG32(USARTx->CR1, USART_CR1_CLR_FLAG_MASK); + + /* Set CR2 */ + WRITE_REG32(USARTx->CR2, (USART_CR2_BIT9 | \ + USART_CR2_BIT10 | \ + pstcInit->u32ClkMode | \ + USART_CR2_LINEN | \ + pstcInit->u32DetectBreakLen | \ + pstcInit->u32SendBreakLen | \ + pstcInit->u32SendBreakMode)); + + /* Set CR3 */ + WRITE_REG32(USARTx->CR3, 0UL); + + /* Set CR1 */ + WRITE_REG32(USARTx->CR1, (pstcInit->u32OversamplingBits | \ + USART_CR1_SBS)); + + /* Set LBMC */ + WRITE_REG32(USARTx->LBMC, 0UL); + + if (USART_EXTCLK != pstcInit->u32ClkMode) + { + DDL_ASSERT(IS_USART_PCLK_DIV(pstcInit->u32PclkDiv)); + DDL_ASSERT(IS_USART_LIN_BMC_PCLK_DIV(pstcInit->u32BmcPclkDiv)); + + /* Set PR */ + WRITE_REG32(USARTx->PR, (pstcInit->u32PclkDiv | \ + pstcInit->u32BmcPclkDiv)); + + /* Set baudrate */ + enRet = USART_SetBaudrate(USARTx, pstcInit->u32Baudrate, NULL); + } + else + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_usart_lin_init_t to default values. + * @param [out] pstcInit Pointer to a @ref stc_usart_lin_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: the pointer pstcInit is NULL + */ +en_result_t USART_LinStructInit(stc_usart_lin_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Baudrate = 9600UL; + pstcInit->u32ClkMode = USART_INTERNCLK_NONE_OUTPUT; + pstcInit->u32PclkDiv = USART_PCLK_DIV1; + pstcInit->u32BmcPclkDiv = USART_LIN_BMC_PCLK_DIV1; + pstcInit->u32OversamplingBits = USART_OVERSAMPLING_16BIT; + pstcInit->u32DetectBreakLen = USART_LIN_DETECT_BREAK_10BIT; + pstcInit->u32SendBreakLen = USART_LIN_SEND_BREAK_10BIT; + pstcInit->u32SendBreakMode = USART_LIN_SEND_BREAK_MODE_SBK; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Initialize smartcard function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @param [in] pstcInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL or baudrate set unsuccessfully + * @note Smartcard feature is unsupported by M4_USART5/M4_USART10 + */ +en_result_t USART_SmartcardInit(M4_USART_TypeDef *USARTx, + const stc_usart_smartcard_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_USART_SMARTCARD_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_SMARTCARD_CLOCK_MODE(pstcInit->u32ClkMode)); + DDL_ASSERT(IS_USART_PCLK_DIV(pstcInit->u32PclkDiv)); + DDL_ASSERT(IS_USART_SIGNIFICANT_BIT(pstcInit->u32BitDirection)); + + /* Disbale TX/RX && clear flag */ + WRITE_REG32(USARTx->CR1, USART_CR1_CLR_FLAG_MASK); + + /* Set CR2 */ + WRITE_REG32(USARTx->CR2, (USART_CR2_BIT9 | \ + USART_CR2_BIT10 | \ + pstcInit->u32ClkMode | \ + pstcInit->u32StopBit)); + + /* Set CR3 */ + WRITE_REG32(USARTx->CR3, USART_CR3_SCEN | USART_SC_ETU_CLK_372); + + /* Set CR1 */ + WRITE_REG32(USARTx->CR1, (USART_CR1_PCE | \ + pstcInit->u32BitDirection | \ + USART_CR1_SBS)); + + /* Set PR */ + WRITE_REG32(USARTx->PR, pstcInit->u32PclkDiv); + + /* Set LBMC */ + WRITE_REG32(USARTx->LBMC, 0UL); + + /* Set baudrate */ + enRet = USART_SetBaudrate(USARTx, pstcInit->u32Baudrate, NULL); + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_usart_smartcard_init_t to default values. + * @param [out] pstcInit Pointer to a @ref stc_usart_smartcard_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: the pointer pstcInit is NULL + */ +en_result_t USART_SmartcardStructInit(stc_usart_smartcard_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Baudrate = 9600UL; + pstcInit->u32ClkMode = USART_INTERNCLK_NONE_OUTPUT; + pstcInit->u32PclkDiv = USART_PCLK_DIV1; + pstcInit->u32BitDirection = USART_LSB; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief Initialize clock synchronization function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] pstcInit Pointer to a @ref stc_usart_clksync_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL or baudrate set unsuccessfully + */ +en_result_t USART_ClkSyncInit(M4_USART_TypeDef *USARTx, + const stc_usart_clksync_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_CLKSYNC_CLOCK_MODE(pstcInit->u32ClkMode)); + DDL_ASSERT(IS_USART_SIGNIFICANT_BIT(pstcInit->u32BitDirection)); + DDL_ASSERT(IS_USART_HWFLOWCTRL(pstcInit->u32HwFlowCtrl)); + + /* Disbale TX/RX && clear flag */ + WRITE_REG32(USARTx->CR1, USART_CR1_CLR_FLAG_MASK); + + /* Set CR2 */ + WRITE_REG32(USARTx->CR2, (USART_CR2_BIT9 | \ + USART_CR2_BIT10 | \ + pstcInit->u32ClkMode)); + + /* Set CR3 */ + WRITE_REG32(USARTx->CR3, pstcInit->u32HwFlowCtrl); + + /* Set CR1 */ + WRITE_REG32(USARTx->CR1, (USART_CR1_MS | \ + pstcInit->u32BitDirection | \ + USART_CR1_SBS)); + + /* Set LBMC */ + WRITE_REG32(USARTx->LBMC, 0UL); + + if (USART_EXTCLK != pstcInit->u32ClkMode) + { + DDL_ASSERT(IS_USART_PCLK_DIV(pstcInit->u32PclkDiv)); + + /* Set PR */ + WRITE_REG32(USARTx->PR, pstcInit->u32PclkDiv); + + /* Set baudrate */ + enRet = USART_SetBaudrate(USARTx, pstcInit->u32Baudrate, NULL); + } + else + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief Set the fields of structure stc_usart_clksync_init_t to default values. + * @param [out] pstcInit Pointer to a @ref stc_usart_clksync_init_t structure. + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - ErrorInvalidParameter: the pointer pstcInit is NULL + */ +en_result_t USART_ClkSyncStructInit(stc_usart_clksync_init_t *pstcInit) +{ + en_result_t enRet = ErrorInvalidParameter; + + /* Check structure pointer */ + if (NULL != pstcInit) + { + pstcInit->u32Baudrate = 9600UL; + pstcInit->u32ClkMode = USART_INTERNCLK_NONE_OUTPUT; + pstcInit->u32PclkDiv = USART_PCLK_DIV1; + pstcInit->u32BitDirection = USART_LSB; + pstcInit->u32HwFlowCtrl = USART_HWFLOWCTRL_NONE; + enRet = Ok; + } + + return enRet; +} + +/** + * @brief De-Initialize USART function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval None + */ +void USART_DeInit(M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + /* Configures the registers to reset value. */ + WRITE_REG32(USARTx->CR1, USART_CR1_CLR_FLAG_MASK); + WRITE_REG32(USARTx->PR, 0x00000000UL); + WRITE_REG32(USARTx->BRR, 0x0000FF00UL); + WRITE_REG32(USARTx->CR1, 0x80000000UL); + WRITE_REG32(USARTx->CR2, 0x00000600UL); + WRITE_REG32(USARTx->CR3, 0x00000000UL); + WRITE_REG32(USARTx->LBMC, 0x00000000UL); +} + +/** + * @brief Enable/disable USART Transmit/Receive Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the following values: + * @arg USART_RX: USART RX function + * @arg USART_TX: USART TX function + * @arg USART_RTO: USART RX timerout function + * @arg USART_INT_RX: USART receive data register not empty && receive error interrupt + * @arg USART_INT_TE: USART transmit data register empty interrupt + * @arg USART_INT_TC: USART transmission complete interrupt + * @arg USART_INT_RTO: USART RX timerout interrupt + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note USART RX timeout feature is supported by M4_USART1/M4_USART2/M4_USART5/M4_USART6 + */ +void USART_FuncCmd(M4_USART_TypeDef *USARTx, + uint32_t u32Func, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_TIMEOUT_INSTANCE(USARTx) || \ + ((!IS_USART_TIMEOUT_INSTANCE(USARTx)) && (0UL == (u32Func & (USART_RTO | USART_INT_RTO))))); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_USART_FUNCTION(u32Func)); + + (Enable == enNewState) ? SET_REG32_BIT(USARTx->CR1, u32Func) : CLEAR_REG32_BIT(USARTx->CR1, u32Func); +} + +/** + * @brief Get USART function state. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Func USART function type + * This parameter can be one of the following values: + * @arg USART_RX: USART RX function + * @arg USART_TX: USART TX function + * @arg USART_RTO: USART RX timerout function + * @arg USART_INT_RX: USART RX interrupt function + * @arg USART_INT_TXE: Transmit data register empty interrupt + * @arg USART_INT_TC: USART transmission complete interrupt + * @arg USART_INT_RTO: USART RX timerout interrupt + * @retval An en_functional_state_t enumeration value: + * - Enable: Enable function + * - Disable: Disable function + */ +en_functional_state_t USART_GetFuncState(const M4_USART_TypeDef *USARTx, + uint32_t u32Func) +{ + /* Check parameters */ + DDL_ASSERT (IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_FUNCTION(u32Func)); + + return (READ_REG32_BIT(USARTx->CR1, u32Func) ? Enable : Disable); +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the following values: + * @arg USART_FLAG_PE: Parity error flag + * @arg USART_FLAG_FE: Framing error flag + * @arg USART_FLAG_ORE: Overrun error flag + * @arg USART_FLAG_BE: LIN bus error flag + * @arg USART_FLAG_RXNE: Receive data register not empty flag + * @arg USART_FLAG_TC: Transmission complete flag + * @arg USART_FLAG_TXE: Transmit data register empty flag + * @arg USART_FLAG_MPB: Receive processor ID flag + * @arg USART_FLAG_RTOF: Receive timeout flag + * @arg USART_FLAG_LBD: LIN break signal detection flag + * @arg USART_FLAG_WKUP: LIN wakeup signal detection flag + * @arg USART_FLAG_MPB: Receive processor ID flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t USART_GetStatus(const M4_USART_TypeDef *USARTx, + uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_FLAG(u32Flag)); + + return (READ_REG32_BIT(USARTx->SR, u32Flag) ? Set : Reset); +} + +/** + * @brief Get USART flag. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Flag USART flag type + * This parameter can be any composed value of the following values: + * @arg USART_CLEAR_FLAG_PE: Clear Parity error flag + * @arg USART_CLEAR_FLAG_FE: Clear Framing error flag + * @arg USART_CLEAR_FLAG_ORE: Clear Overrun error flag + * @arg USART_CLEAR_FLAG_RTOF:Clear RX timeout flag + * @arg USART_CLEAR_FLAG_BE: Clear LIN bus error flag + * @arg USART_CLEAR_FLAG_WKUP:Clear LIN wakeup signal flag + * @arg USART_CLEAR_FLAG_LBD: Clear Clear LIN break detection flag + * @retval None + */ +void USART_ClearStatus(M4_USART_TypeDef *USARTx, uint32_t u32Flag) +{ + /* Check parameters */ + DDL_ASSERT (IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_CLEAR_FLAG(u32Flag)); + + SET_REG32_BIT(USARTx->CR1, u32Flag); +} + +/** + * @brief Set USART transmission type. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Type USART transmission content type + * This parameter can be one of the following values: + * @arg USART_TRANSMISSION_ID USART transmission content type is processor ID + * @arg USART_TRANSMISSION_DATA USART transmission content type is frame data + * @retval None + */ +void USART_SetTransmissionType(M4_USART_TypeDef *USARTx, uint32_t u32Type) +{ + /* Check parameters */ + DDL_ASSERT (IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_TRANSMISSION_TYPE(u32Type)); + + MODIFY_REG32(USARTx->DR, USART_DR_MPID, u32Type); +} + +/** + * @brief Get USART transmission type. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_TRANSMISSION_ID USART transmission content type is processor ID + * @arg USART_TRANSMISSION_DATA USART transmission content type is frame data + */ +uint32_t USART_GetTransmissionType(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->DR, USART_DR_MPID); +} + +/** + * @brief Set USART parity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Parity USART parity + * This parameter can be one of the following values: + * @arg USART_PARITY_NONE: Parity control disabled + * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected + * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected + * @retval None + */ +void USART_SetParity(M4_USART_TypeDef *USARTx, uint32_t u32Parity) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_PARITY_CONTROL(u32Parity)); + + MODIFY_REG32(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE), u32Parity); +} + +/** + * @brief Get USART parity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_PARITY_NONE: Parity control disabled + * @arg USART_PARITY_ODD: Parity control enabled and Odd Parity is selected + * @arg USART_PARITY_EVEN: Parity control enabled and Even Parity is selected + */ +uint32_t USART_GetParity(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR1, (USART_CR1_PS | USART_CR1_PCE)); +} + +/** + * @brief Set USART data width. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32DataWidth USART data width + * This parameter can be one of the following values: + * @arg USART_DATA_LENGTH_8BIT: 8 bits word length + * @arg USART_DATA_LENGTH_9BIT: 9 bits word length + * @retval None + */ +void USART_SetDataWidth(M4_USART_TypeDef *USARTx, uint32_t u32DataWidth) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_DATA_WIDTH(u32DataWidth)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_M, u32DataWidth); +} + +/** + * @brief Get USART data width. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_DATA_LENGTH_8BIT: 8 bits word length + * @arg USART_DATA_LENGTH_9BIT: 9 bits word length + */ +uint32_t USART_GetDataWidth(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR1, USART_CR1_M); +} + +/** + * @brief Set USART oversampling bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32OversamplingBits USART oversampling bits + * This parameter can be one of the following values: + * @arg USART_OVERSAMPLING_8BIT: Oversampling by 8 bits + * @arg USART_OVERSAMPLING_16BIT: Oversampling by 16 bits + * @retval None + */ +void USART_SetOversmaplingBits(M4_USART_TypeDef *USARTx, + uint32_t u32OversamplingBits) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_OVERSAMPLING_BITS(u32OversamplingBits)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_OVER8, u32OversamplingBits); +} + +/** + * @brief Get USART oversampling bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_OVERSAMPLING_8BIT: Oversampling by 8 bits + * @arg USART_OVERSAMPLING_16BIT: Oversampling by 16 bits + */ +uint32_t USART_GetOversmaplingBits(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8); +} + +/** + * @brief Set USART bit direction. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32BitDir USART bit direction + * This parameter can be one of the following values: + * @arg USART_MSB: MSB(Most Significant Bit) + * @arg USART_LSB: LSB(Least Significant Bit) + * @retval None + */ +void USART_SetBitDirection(M4_USART_TypeDef *USARTx, uint32_t u32BitDir) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_SIGNIFICANT_BIT(u32BitDir)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_ML, u32BitDir); +} + +/** + * @brief Get USART bit direction. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_MSB: MSB(Most Significant Bit) + * @arg USART_LSB: LSB(Least Significant Bit) + */ +uint32_t USART_GetBitDirection(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR1, USART_CR1_ML); +} + +/** + * @brief Set USART start bit detect polarity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Polarity USART start bit detect polarity + * This parameter can be one of the following values: + * @arg USART_SB_DETECT_LOW: Detect RX pin low level + * @arg USART_SB_DETECT_FALLING: Detect RX pin falling edge + * @retval None + */ +void USART_SetSbDetectPolarity(M4_USART_TypeDef *USARTx, + uint32_t u32Polarity) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_SB_DETECT_POLARITY(u32Polarity)); + + MODIFY_REG32(USARTx->CR1, USART_CR1_SBS, u32Polarity); +} + +/** + * @brief Get USART start bit detect polarity. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_SB_DETECT_LOW: Detect RX pin low level + * @arg USART_SB_DETECT_FALLING: Detect RX pin falling edge + */ +uint32_t USART_GetSbDetectPolarity(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR1, USART_CR1_SBS); +} + +/** + * @brief Set USART clock mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32ClkMode USART clock mode + * This parameter can be one of the following values: + * @arg USART_EXTCLK: Select external clock source. + * @arg USART_INTERNCLK_OUTPUT: Select internal clock source and output clock. + * @arg USART_INTERNCLK_NONE_OUTPUT: Select internal clock source and don't output clock + * @retval None + */ +void USART_SetClockMode(M4_USART_TypeDef *USARTx, uint32_t u32ClkMode) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_CLOCK_MODE(u32ClkMode)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_CLKC, u32ClkMode); +} + +/** + * @brief Get USART clock mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_EXTCLK: Select external clock source. + * @arg USART_INTERNCLK_OUTPUT: Select internal clock source and output clock. + * @arg USART_INTERNCLK_NONE_OUTPUT: Select internal clock source and don't output clock + */ +uint32_t USART_GetClockMode(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_CLKC); +} + +/** + * @brief Set USART stop bits. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32StopBits USART stop bits + * This parameter can be one of the following values: + * @arg USART_STOPBIT_1BIT: 1 stop bit + * @arg USART_STOPBIT_2BIT: 2 stop bits + * @retval None + */ +void USART_SetStopBits(M4_USART_TypeDef *USARTx, uint32_t u32StopBits) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_STOP_BITS(u32StopBits)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_STOP, u32StopBits); +} + +/** + * @brief Get USART clock mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_STOPBIT_1BIT: 1 stop bit + * @arg USART_STOPBIT_2BIT: 2 stop bits + */ +uint32_t USART_GetStopBits(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_STOP); +} + +/** + * @brief USART receive data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Receive data + */ +uint16_t USART_RecData(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return (uint16_t)(READ_REG32(USARTx->DR) >> USART_DR_RDR_POS); +} + +/** + * @brief USART send data. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + ** \param [in] u16Data Transmit data + * @retval None + */ +void USART_SendData(M4_USART_TypeDef *USARTx, uint16_t u16Data) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + WRITE_REG32(USARTx->DR, ((uint32_t)u16Data & 0x01FFUL)); +} + +/** + * @brief USART send processor ID. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + ** \param [in] u16ID Processor ID + * @retval None + */ +void USART_SendId(M4_USART_TypeDef *USARTx, uint16_t u16ID) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + WRITE_REG32(USARTx->DR, (USART_DR_MPID | ((uint32_t)u16ID & 0x01FFUL))); +} + +/** + * @brief Enable or disable USART silence. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + */ +void USART_SilenceCmd(M4_USART_TypeDef *USARTx, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } + else + { + CLEAR_REG32_BIT(USARTx->CR1, USART_CR1_SLME); + } +} + +/** + * @brief Enable or disable USART loop function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +void USART_LinLoopCmd(M4_USART_TypeDef *USARTx, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + + if (Enable == enNewState) + { + SET_REG32_BIT(USARTx->CR3, USART_CR3_LOOP); + } + else + { + CLEAR_REG32_BIT(USARTx->CR3, USART_CR3_LOOP); + } +} + +/** + * @brief LIN Request break sending + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +void USART_LinRequestBreakSending(M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + SET_REG32_BIT(USARTx->CR2, USART_CR2_SBK); +} + +/** + * @brief Get request break sending status + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval An en_flag_status_t enumeration value: + * - Set: Sending break + * - Reset: Send break completely + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +en_flag_status_t USART_GetLinRequestBreakStatus(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_SBK) ? Set : Reset; +} + +/** + * @brief Set send break mode for USART LIN. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Mode USART send break mode + * This parameter can be one of the following values: + * @arg USART_LIN_SEND_BREAK_MODE_SBK: Start send break after USART_CR2 SBK bit set 1 value + * @arg USART_LIN_SEND_BREAK_MODE_TDR: Start send break after USART_DR TDR write 0x00 value + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +void USART_SetLinBreakMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_MODE(u32Mode)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_SBKM, u32Mode); +} + +/** + * @brief Get send break mode for USART LIN. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_LIN_SEND_BREAK_MODE_SBK: Start send break after USART_CR2 SBK bit set 1 value + * @arg USART_LIN_SEND_BREAK_MODE_TDR: Start send break after USART_DR TDR write 0x00 value + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetLinBreakMode(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_SBKM); +} + +/** + * @brief Set UART half/full duplex selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Mode USART half/full duplex selection + * This parameter can be one of the following values: + * @arg USART_HALFDUPLEX_MODE:USART half-duplex mode + * @arg USART_FULLDUPLEX_MODE:USART full-duplex mode + * @retval None + */ +void USART_SetDuplexMode(M4_USART_TypeDef *USARTx, uint32_t u32Mode) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_UART_DUPLEX_MODE(u32Mode)); + + MODIFY_REG32(USARTx->CR3, USART_CR3_HDSEL, u32Mode); +} + +/** + * @brief Get USART half/full duplex. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_HALFDUPLEX_MODE:USART half-duplex mode + * @arg USART_FULLDUPLEX_MODE:USART full-duplex mode + */ +uint32_t USART_GetDuplexMode(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR3, USART_CR3_HDSEL); +} + +/** + * @brief Set UART hardware flow control CTS/RTS selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32HwFlowCtrl USART hardware flow control CTS/RTS selection + * This parameter can be one of the following values: + * @arg USART_HWFLOWCTRL_NONE Disable USART hardware flow control + * @arg USART_HWFLOWCTRL_CTS: UART hardware flow control CTS mode + * @arg USART_HWFLOWCTRL_RTS: UART hardware flow control RTS mode + * @arg USART_HWFLOWCTRL_RTS_CTS: UART hardware flow control RTS and CTS mode + * @retval None + */ +void USART_SetHwFlowCtrl(M4_USART_TypeDef *USARTx, uint32_t u32HwFlowCtrl) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_HWFLOWCTRL(u32HwFlowCtrl)); + + MODIFY_REG32(USARTx->CR3, (USART_CR3_RTSE | USART_CR3_CTSE), u32HwFlowCtrl); +} + +/** + * @brief Get USART hardware flow control CTS/RTS selection. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_HWFLOWCTRL_NONE: Disable USART hardware flow control + * @arg USART_HWFLOWCTRL_CTS: UART hardware flow control CTS mode + * @arg USART_HWFLOWCTRL_RTS: UART hardware flow control RTS mode + * @arg USART_HWFLOWCTRL_RTS_CTS: UART hardware flow control RTS and CTS mode + */ +uint32_t USART_GetHwFlowCtrl(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR3, (USART_CR3_RTSE | USART_CR3_CTSE)); +} + +/** + * @brief Set USART Smartcard ETU Clock. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @param [in] u32EtuClk USART Smartcard ETU Clock. + * This parameter can be one of the following values: + * @arg USART_SC_ETU_CLK_32: 1 etu = 32/f + * @arg USART_SC_ETU_CLK_64: 1 etu = 64/f + * @arg USART_SC_ETU_CLK_128: 1 etu = 128/f + * @arg USART_SC_ETU_CLK_256: 1 etu = 256/f + * @arg USART_SC_ETU_CLK_372: 1 etu = 372/f + * @retval None + * @note Smartcard feature is unsupported by M4_USART5/M4_USART10 + */ +void USART_SetSmartcardEtuClk(M4_USART_TypeDef *USARTx, + uint32_t u32EtuClk) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_SMARTCARD_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(u32EtuClk)); + + MODIFY_REG32(USARTx->CR3, USART_CR3_BCN, u32EtuClk); +} + +/** + * @brief Get USART Smartcard ETU Clock. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_SC_ETU_CLK_32: 1 etu = 32/f + * @arg USART_SC_ETU_CLK_64: 1 etu = 64/f + * @arg USART_SC_ETU_CLK_128: 1 etu = 128/f + * @arg USART_SC_ETU_CLK_256: 1 etu = 256/f + * @arg USART_SC_ETU_CLK_372: 1 etu = 372/f + * @note Smartcard feature is unsupported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetSmartcardEtuClk(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_SMARTCARD_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); +} + +/** + * @brief Set USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32PclkDiv USART clock prescaler division. + * This parameter can be one of the following values: + * @arg USART_PCLK_DIV1: PCLK + * @arg USART_PCLK_DIV4: PCLK/4 + * @arg USART_PCLK_DIV16: PCLK/16 + * @arg USART_PCLK_DIV64: PCLK/64 + * @retval None + * @note The PCLK division function is valid when clock source is PCLK + */ +void USART_SetPclkDiv(M4_USART_TypeDef *USARTx, + uint32_t u32PclkDiv) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_PCLK_DIV(u32PclkDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_PSC, u32PclkDiv); +} + +/** + * @brief Get USART clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_PCLK_DIV1: PCLK + * @arg USART_PCLK_DIV4: PCLK/4 + * @arg USART_PCLK_DIV16: PCLK/16 + * @arg USART_PCLK_DIV64: PCLK/64 + * @note The PCLK division function is valid when clock source is PCLK + */ +uint32_t USART_GetPclkDiv(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->PR, USART_PR_PSC); +} + +/** + * @brief Set USART LIN counter clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32PclkDiv USART USART LIN counter clock prescaler division. + * This parameter can be one of the following values: + * @arg USART_LIN_BMC_PCLK_DIV1: PCLK + * @arg USART_LIN_BMC_PCLK_DIV2: PCLK/2 + * @arg USART_LIN_BMC_PCLK_DIV4: PCLK/4 + * @arg USART_LIN_BMC_PCLK_DIV8: PCLK/8 + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + * @note The PCLK division function is valid when clock source is PCLK + */ +void USART_SetLinBmcPclkDiv(M4_USART_TypeDef *USARTx, + uint32_t u32PclkDiv) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_LIN_BMC_PCLK_DIV(u32PclkDiv)); + + MODIFY_REG32(USARTx->PR, USART_PR_LBMPSC, u32PclkDiv); +} + +/** + * @brief Get USART LIN counter clock prescaler division. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_LIN_BMC_PCLK_DIV1: PCLK + * @arg USART_LIN_BMC_PCLK_DIV2: PCLK/2 + * @arg USART_LIN_BMC_PCLK_DIV4: PCLK/4 + * @arg USART_LIN_BMC_PCLK_DIV8: PCLK/8 + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetLinBmcPclkDiv(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->PR, USART_PR_LBMPSC); +} + +/** + * @brief Set stop mode noise filter. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @param [in] u32Filter The noise filter value + * This parameter can be one of the following values: + * @arg USART_STOP_MODE_FILTER_NONE: Disable noise filter + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_1: Filter width level 1 + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_2: Filter width level 2 + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_3: Filter width level 3 + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_4: Filter width level 4 + * @retval None + * @note The stop mode noise filter is supported by M4_USART1 + */ +void USART_SetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx, + uint32_t u32Filter) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_STOPMODE_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_STOPMODE_FILTER(u32Filter)); + + WRITE_REG32(M4_PERIC->USART1_NFC, u32Filter); +} + +/** + * @brief Disable UART multiple processor function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_STOP_MODE_FILTER_NONE: Disable noise filter + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_1: Filter width level 1 + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_2: Filter width level 2 + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_3: Filter width level 3 + * @arg USART_STOP_MODE_FILTER_WIDTH_LEVEL_4: Filter width level 4 + * @note The stop mode noise filter is supported by M4_USART1 + */ +uint32_t USART_GetStopModeNoiseFilter(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_STOPMODE_INSTANCE(USARTx)); + + return READ_REG32_BIT(M4_PERIC->USART1_NFC, (PERIC_USART1_NFC_NFE | PERIC_USART1_NFC_NFS)); +} + +/** + * @brief Enable/disable USART LIN Function. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Func USART function type + * This parameter can be any composed value of the following values: + * @arg USART_LIN: USART LIN function + * @arg USART_LIN_WKUP: USART LIN wakeup signal detect function + * @arg USART_LIN_INT_WKUP: USART LIN wakeup signal detect interrupt function + * @arg USART_LIN_BUSERR: USART LIN bus error detect function + * @arg USART_LIN_INT_BUSERR: USART LIN bus error detect interrupt function + * @arg USART_LIN_INT_BREAK: USART LIN break field detect interrupt function + * @param [in] enNewState The function new state. + * @arg This parameter can be: Enable or Disable. + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +void USART_LinFuncCmd(M4_USART_TypeDef *USARTx, + uint32_t u32Func, + en_functional_state_t enNewState) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_FUNCTIONAL_STATE(enNewState)); + DDL_ASSERT(IS_USART_LIN_FUNCTION(u32Func)); + + (Enable == enNewState) ? SET_REG32_BIT(USARTx->CR2, u32Func) : CLEAR_REG32_BIT(USARTx->CR2, u32Func); +} + +/** + * @brief Get USART LIN function state. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Func USART function type + * This parameter can be one of the following values: + * @arg USART_LIN: USART LIN function + * @arg USART_LIN_WKUP: USART LIN wakeup signal detect function + * @arg USART_LIN_INT_WKUP: USART LIN wakeup signal detect interrupt function + * @arg USART_LIN_BUSERR: USART LIN bus error detect function + * @arg USART_LIN_INT_BUSERR: USART LIN bus error detect interrupt function + * @arg USART_LIN_INT_BREAK: USART LIN break field detect interrupt function + * @retval An en_functional_state_t enumeration value: + * - Enable: Enable function + * - Disable: Disable function + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +en_functional_state_t USART_GetLinFuncState(const M4_USART_TypeDef *USARTx, + uint32_t u32Func) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_FUNCTION(u32Func)); + + return (READ_REG32_BIT(USARTx->CR2, u32Func) ? Enable : Disable); +} + +/** + * @brief Get USART LIN baudrate measure count. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval LIN baudrate measure count value + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetLinMeasureCnt(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC); +} + +/** + * @brief Get USART LIN baudrate measure count. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @retval LIN baudrate measure count value + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetLinMeasureBaudrate(const M4_USART_TypeDef *USARTx) +{ + uint32_t u32BmClk; + uint32_t u32BmDiv; + uint32_t u32LBMC; + + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + u32BmDiv = USART_BMC_DIV(USARTx); + u32BmClk = PCLK_FREQ / u32BmDiv; + u32LBMC = READ_REG32_BIT(USARTx->LBMC, USART_LBMC_LBMC); + + return (u32LBMC > 0UL) ? (u32BmClk / u32LBMC) : 0UL; +} + +/** + * @brief Set USART LIN break detection length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 1 instance register base + * @arg M4_USART10: USART unit 2 instance register base + * @param [in] u32Len USART clock prescaler division. + * This parameter can be one of the following values: + * @arg USART_LIN_DETECT_BREAK_10BIT: 10-bit break detection + * @arg USART_LIN_DETECT_BREAK_11BIT: 11-bit break detection + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +void USART_SetLinDetectBreakLen(M4_USART_TypeDef *USARTx, + uint32_t u32Len) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_LIN_DETECT_BREAK_LEN(u32Len)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_LBDL, u32Len); +} + +/** + * @brief Get USART LIN break detection length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 1 instance register base + * @arg M4_USART10: USART unit 2 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_LIN_DETECT_BREAK_10BIT: 10-bit break detection + * @arg USART_LIN_DETECT_BREAK_11BIT: 11-bit break detection + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetLinDetectBreakLen(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_LBDL); +} + +/** + * @brief Set USART LIN break sending length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 1 instance register base + * @arg M4_USART10: USART unit 2 instance register base + * @param [in] u32Len USART clock prescaler division. + * This parameter can be one of the following values: + * @arg USART_LIN_SEND_BREAK_10BIT: Send break 10-bit + * @arg USART_LIN_SEND_BREAK_11BIT: Send break 11-bit + * @arg USART_LIN_SEND_BREAK_13BIT: Send break 13-bit + * @arg USART_LIN_SEND_BREAK_14BIT: Send break 14-bit + * @retval None + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +void USART_SetLinSendBreakLen(M4_USART_TypeDef *USARTx, uint32_t u32Len) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + DDL_ASSERT(IS_USART_LIN_SEND_BREAK_LEN(u32Len)); + + MODIFY_REG32(USARTx->CR2, USART_CR2_SBKL, u32Len); +} + +/** + * @brief Get USART LIN break detection length. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART5: USART unit 1 instance register base + * @arg M4_USART10: USART unit 2 instance register base + * @retval Returned value can be one of the following values: + * @arg USART_LIN_SEND_BREAK_10BIT: Send break 10-bit + * @arg USART_LIN_SEND_BREAK_11BIT: Send break 11-bit + * @arg USART_LIN_SEND_BREAK_13BIT: Send break 13-bit + * @arg USART_LIN_SEND_BREAK_14BIT: Send break 14-bit + * @note LIN feature is supported by M4_USART5/M4_USART10 + */ +uint32_t USART_GetLinSendBreakLen(const M4_USART_TypeDef *USARTx) +{ + /* Check parameters */ + DDL_ASSERT(IS_USART_LIN_INSTANCE(USARTx)); + + return READ_REG32_BIT(USARTx->CR2, USART_CR2_SBKL); +} + +/** + * @brief Set USART baudrate. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Baudrate UART baudrate + * @param [out] pf32Err E(%) baudrate error rate + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: set unsuccessfully + */ +en_result_t USART_SetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate, + float32_t *pf32Err) +{ + uint32_t u32Mode; + uint32_t u32BrrVal = 0UL; + uint32_t u32FractEn = 0UL; + uint32_t u32UsartClk; + uint32_t u32UsartDiv; + en_result_t enRet; + + /* Check parameter */ + DDL_ASSERT(u32Baudrate > 0UL); + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + /* Get USART clock frequency */ + u32UsartDiv = USART_DIV(USARTx); + u32UsartClk = PCLK_FREQ / u32UsartDiv; + + u32Mode = READ_REG32_BIT(USARTx->CR3, USART_CR3_SCEN); + if (u32Mode > 0UL) + { + /* Smart card */ + enRet = CalcSmartcardBaudrate(USARTx, u32UsartClk, u32Baudrate, &u32BrrVal, &u32FractEn, pf32Err); + } + else + { + u32Mode = READ_REG32_BIT(USARTx->CR1, USART_CR1_MS); + if (u32Mode > 0UL) + { + /* Clock synchronization */ + enRet = CalcClkSyncBaudrate(USARTx, u32UsartClk, u32Baudrate, &u32BrrVal, &u32FractEn, pf32Err); + } + else + { + /* UART */ + enRet = CalcUartBaudrate(USARTx, u32UsartClk, u32Baudrate, &u32BrrVal, &u32FractEn, pf32Err); + } + } + + if (Ok == enRet) + { + if ((!IS_USART_FRACTION_INSTANCE(USARTx)) && (u32FractEn > 0UL)) + { + enRet = Error; + } + else + { + /* Set baudrate */ + MODIFY_REG32(USARTx->CR1, USART_CR1_FBME, u32FractEn); + WRITE_REG32(USARTx->BRR, u32BrrVal); + } + } + + return enRet; +} + +/** + * @} + */ + +/** + * @defgroup USART_Local_Functions USART Local Functions + * @{ + */ + +/** + * @brief Calculate baudrate for UART mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32BrrVal Pointer to BRR register value + * @param [out] pu32FractEn Pointer to CR1 FBME bit value + * @param [out] pf32Err E(%) baudrate error rate + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: set unsuccessfully + * @note Baudrate fraction feature is unsupported by M4_USART5/M4_USART10 + */ +static en_result_t CalcUartBaudrate(const M4_USART_TypeDef *USARTx, + uint32_t u32UsartClk, + uint32_t u32Baudrate, + uint32_t *pu32BrrVal, + uint32_t *pu32FractEn, + float32_t *pf32Err) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t DIV; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction = 0UL; + float32_t f32Err; + en_result_t enRet = Ok; + + /* Check parameter */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((C > 0UL) && (B > 0UL)) + { + OVER8 = READ_REG32_BIT(USARTx->CR1, USART_CR1_OVER8) ? 1UL : 0UL; + + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0F * (2.0F - (float)OVER8))) - 1.0F; + DIV_Integer = (uint32_t)(DIV); + DDL_ASSERT((DIV > 0.0F) && (DIV_Integer <= 0xFFUL)); + + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + + if (IS_USART_FRACTION_INSTANCE(USARTx)) + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001F) + { + /* UART mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */ + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + if (DIV_Fraction > 0x7FUL) + { + enRet = ErrorInvalidParameter; + } + } + } + + if (Ok == enRet) + { + *pu32FractEn = (DIV_Fraction > 0UL) ? USART_CR1_FBME : 0UL; + *pu32BrrVal = DIV_Fraction + (uint32_t)(DIV_Integer << USART_BRR_DIV_INTEGER_POS); + + if (NULL != pf32Err) + { + if (0UL == DIV_Fraction) + { + /* E(%) = C / (8 * (2 - OVER8) * (DIV_Integer + 1) * B) - 1 */ + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + } + else + { + /* E(%) = C * (128 + DIV_Fraction) / (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B)) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + } + + *pf32Err = f32Err; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + * @brief Calculate baudrate for clock synchronization mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32BrrVal Pointer to BRR register value + * @param [out] pu32FractEn Pointer to CR1 FBME bit value + * @param [out] pf32Err E(%) baudrate error rate + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: set unsuccessfully + */ +static en_result_t CalcClkSyncBaudrate(const M4_USART_TypeDef *USARTx, + uint32_t u32UsartClk, + uint32_t u32Baudrate, + uint32_t *pu32BrrVal, + uint32_t *pu32FractEn, + float32_t *pf32Err) +{ + uint32_t C; + uint32_t B; + float32_t DIV; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction = 0UL; + float32_t f32Err; + en_result_t enRet = Ok; + + /* Check parameter */ + DDL_ASSERT(IS_USART_INSTANCE(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((C > 0UL) && (B > 0UL)) + { + /* Clock sync mode baudrate integer calculation formula: */ + /* B = C / (4 * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 4)) - 1 */ + DIV = ((float)C / ((float)B * 4.0F)) - 1.0F; + DIV_Integer = (uint32_t)DIV; + DDL_ASSERT((DIV > 0.0F) && (DIV_Integer <= 0xFFUL)); + + u64Temp = (uint64_t)((uint64_t)4U * ((uint64_t)DIV_Integer + (uint64_t)1UL) * (uint64_t)B); + + if (IS_USART_FRACTION_INSTANCE(USARTx)) + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001F) + { + /* Clock sync mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = 256 * (4 * (DIV_Integer + 1) * B / C - 128 */ + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + if (DIV_Fraction > 0x7FUL) + { + enRet = ErrorInvalidParameter; + } + } + } + + if (Ok == enRet) + { + *pu32FractEn = (DIV_Fraction > 0UL) ? USART_CR1_FBME : 0UL; + *pu32BrrVal = DIV_Fraction + (uint32_t)(DIV_Integer << USART_BRR_DIV_INTEGER_POS); + + if (NULL != pf32Err) + { + if (0UL == DIV_Fraction) + { + /* E(%) = C / (4 * (DIV_Integer + 1) * B) - 1 */ + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + } + else + { + /* E(%) = C * (128 + DIV_Fraction) / (4 * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)(u64Dividend) / (float64_t)(u64Temp)) - 1.0F; + } + + *pf32Err = f32Err; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + * @brief Calculate baudrate for smart-card mode. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @param [in] u32UsartClk USART clock + * @param [in] u32Baudrate UART baudrate + * @param [out] pu32BrrVal Pointer to BRR register value + * @param [out] pu32FractEn Pointer to CR1 FBME bit value + * @param [out] pf32Err E(%) baudrate error rate + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - ErrorInvalidParameter: set unsuccessfully + * @note Smartcard feature is unsupported by M4_USART5/M4_USART10 + */ +static en_result_t CalcSmartcardBaudrate(const M4_USART_TypeDef *USARTx, + uint32_t u32UsartClk, + uint32_t u32Baudrate, + uint32_t *pu32BrrVal, + uint32_t *pu32FractEn, + float32_t *pf32Err) +{ + uint32_t B; + uint32_t C; + uint32_t BCN; + float32_t DIV; + uint64_t u64Temp; + uint64_t u64Dividend; + uint32_t DIV_Integer; + uint32_t DIV_Fraction = 0UL; + const uint16_t au16EtuClkCnts[] = {32U, 64U, 93U, 128U, 186U, 256U, 372U, 512U}; + float32_t f32Err; + en_result_t enRet = Ok; + + /* Check parameter */ + DDL_ASSERT(IS_USART_SMARTCARD_INSTANCE(USARTx)); + + C = u32UsartClk; + B = u32Baudrate; + + if ((C > 0UL) && (B > 0UL)) + { + BCN = READ_REG32_BIT(USARTx->CR3, USART_CR3_BCN); + DDL_ASSERT(IS_USART_SMARTCARD_ETU_CLK(BCN)); + BCN = au16EtuClkCnts[BCN >> USART_CR3_BCN_POS]; + + /* Smartcard mode baudrate integer calculation formula: */ + /* B = C / (2 * BCN * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 2 * BCN)) - 1 */ + DIV = ((float)C / ((float)B * (float)BCN * 2.0F)) - 1.0F; + DIV_Integer = (uint32_t)DIV; + + DDL_ASSERT((DIV > 0.0F) && (DIV_Integer <= 0xFFUL)); + + u64Temp = (uint64_t)((uint64_t)2UL * BCN * ((uint64_t)DIV_Integer + (uint64_t)1UL) * B); + + if (IS_USART_FRACTION_INSTANCE(USARTx)) + { + if ((DIV - (float32_t)DIV_Integer) > 0.00001F) + { + /* Smartcard mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / ((2 * BCN) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (2 * BCN * (DIV_Integer + 1) * B) / C) - 128 */ + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + if (DIV_Fraction > 0x7FUL) + { + enRet = ErrorInvalidParameter; + } + } + } + + if (Ok == enRet) + { + *pu32FractEn = (DIV_Fraction > 0UL )? USART_CR1_FBME : 0UL; + *pu32BrrVal = DIV_Fraction + (uint32_t)(DIV_Integer << USART_BRR_DIV_INTEGER_POS); + + if (NULL != pf32Err) + { + if (0UL == DIV_Fraction) + { + /* E(%) = C / (2 * BCN * (DIV_Integer + 1) * B) - 1 */ + f32Err = (float32_t)((float64_t)C / (float64_t)u64Temp) - 1.0F; + } + else + { + /* E(%) = C * (128 + DIV_Fraction) / (2 * BCN * (DIV_Integer + 1) * B * 256) - 1 */ + u64Temp *= (uint64_t)256UL; + u64Dividend = (uint64_t)C * ((uint64_t)128UL + (uint64_t)DIV_Fraction); + f32Err = (float32_t)((float64_t)u64Dividend / (float64_t)(u64Temp)) - 1.0F; + } + + *pf32Err = f32Err; + } + } + } + else + { + enRet = ErrorInvalidParameter; + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_USART_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_utility.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_utility.c new file mode 100644 index 0000000000000000000000000000000000000000..9b8b53baa166dd0c9e481ff893dc5fccf38c5e35 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_utility.c @@ -0,0 +1,541 @@ +/** + ******************************************************************************* + * @file hc32f4a0_utility.c + * @brief This file provides utility functions for DDL. + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-12-03 Yangjp Fixed SysTick_Delay function overflow handling + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_UTILITY UTILITY + * @brief DDL Utility Driver + * @{ + */ + +#if (DDL_UTILITY_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup UTILITY_Local_Macros UTILITY Local Macros + * @{ + */ + +#if (DDL_PRINT_ENABLE == DDL_ON) +/** + * @defgroup DDL UART channel/fcg/pin/baudrate definition + * @{ + */ +#define DDL_UART_CH (M4_USART1) +#define DDL_UART_PWC_FCG (PWC_FCG3_USART1) +#define DDL_UART_GPIO_TX_PFSR (M4_GPIO->PFSRH15) /* PH15: USART1_TX */ +#define DDL_UART_GPIO_TX_FUNC (32U) /* GPIO function: USART1_TX */ +#define DDL_UART_BAUDRATE (115200UL) +/** + * @} + */ +#endif + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/** + * @addtogroup UTILITY_Local_Functions UTILITY Local Functions + * @{ + */ + +#if (DDL_PRINT_ENABLE == DDL_ON) + +static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData); +static en_result_t UartSetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate); +#endif + +/** + * @} + */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +/** + * @defgroup UTILITY_Local_Variables UTILITY Local Variables + * @{ + */ + +static uint32_t m_u32TickStep = 0UL; +static __IO uint32_t m_u32TickCount = 0UL; + +/** + * @} + */ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup UTILITY_Global_Functions UTILITY Global Functions + * @{ + */ + +/** + * @brief Delay function, delay ms approximately + * @param [in] u32Cnt ms + * @retval None + */ +void DDL_DelayMS(uint32_t u32Cnt) +{ + __IO uint32_t i; + const uint32_t u32Cyc = HCLK_VALUE / 10000UL; + + while (u32Cnt-- > 0UL) + { + i = u32Cyc; + while (i-- > 0UL) + { + ; + } + } +} + +/** + * @brief Delay function, delay us approximately + * @param [in] u32Cnt us + * @retval None + */ +void DDL_DelayUS(uint32_t u32Cnt) +{ + __IO uint32_t i; + const uint32_t u32Cyc = HCLK_VALUE / 10000000UL; + + while (u32Cnt-- > 0UL) + { + i = u32Cyc; + while (i-- > 0UL) + { + ; + } + } +} + +/** + * @brief This function Initializes the interrupt frequency of the SysTick. + * @param [in] u32Freq SysTick interrupt frequency (1 to 1000). + * @retval An en_result_t enumeration value: + * - Ok: SysTick Initializes succeed + * - Error: SysTick Initializes failed + */ +__WEAKDEF en_result_t SysTick_Init(uint32_t u32Freq) +{ + en_result_t enRet = Error; + + if ((0UL != u32Freq) && (u32Freq <= 1000UL)) + { + m_u32TickStep = 1000UL / u32Freq; + /* Configure the SysTick interrupt */ + if (0UL == SysTick_Config(HCLK_VALUE / u32Freq)) + { + enRet = Ok; + } + } + + return enRet; +} + +/** + * @brief This function provides minimum delay (in milliseconds). + * @param [in] u32Delay Delay specifies the delay time. + * @retval None + */ +__WEAKDEF void SysTick_Delay(uint32_t u32Delay) +{ + const uint32_t tickStart = SysTick_GetTick(); + uint32_t tickEnd; + uint32_t tickMax; + + if (m_u32TickStep != 0UL) + { + tickMax = 0xFFFFFFFFUL / m_u32TickStep * m_u32TickStep; + /* Add a freq to guarantee minimum wait */ + if ((u32Delay >= tickMax) || ((tickMax - u32Delay) < m_u32TickStep)) + { + tickEnd = tickMax; + } + else + { + tickEnd = u32Delay + m_u32TickStep; + } + + while ((SysTick_GetTick() - tickStart) < tickEnd) + { + } + } +} + +/** + * @brief This function is called to increment a global variable "u32TickCount". + * @note This variable is incremented in SysTick ISR. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_IncTick(void) +{ + m_u32TickCount += m_u32TickStep; +} + +/** + * @brief Provides a tick value in millisecond. + * @param None + * @retval Tick value + */ +__WEAKDEF uint32_t SysTick_GetTick(void) +{ + return m_u32TickCount; +} + +/** + * @brief Suspend SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Suspend(void) +{ + /* Disable SysTick Interrupt */ + SysTick->CTRL &= ~SysTick_CTRL_TICKINT_Msk; +} + +/** + * @brief Resume SysTick increment. + * @param None + * @retval None + */ +__WEAKDEF void SysTick_Resume(void) +{ + /* Enable SysTick Interrupt */ + SysTick->CTRL |= SysTick_CTRL_TICKINT_Msk; +} + +#ifdef __DEBUG +/** + * @brief DDL assert error handle function + * @param [in] file Point to the current assert the wrong file. + * @param [in] line Point line assert the wrong file in the current. + * @retval None + */ +__WEAKDEF void DDL_AssertHandler(const char *file, int line) +{ + /* Users can re-implement this function to print information */ +#if (DDL_PRINT_ENABLE == DDL_ON) + (void)printf("Wrong parameters value: file %s on line %d\r\n", file, line); +#endif + + for (;;) + { + ; + } +} +#endif /* __DEBUG */ + +#if (DDL_PRINT_ENABLE == DDL_ON) + +#if defined ( __GNUC__ ) && !defined (__CC_ARM) +/** + * @brief Re-target _write function. + * @param [in] fd + * @param [in] data + * @param [in] size + * @retval int32_t + */ +int32_t _write(int fd, char data[], int32_t size) +{ + int32_t i = -1; + + if (NULL != data) + { + (void)fd; /* Prevent unused argument compilation warning */ + + for (i = 0; i < size; i++) + { + if (Ok != UartPutChar(DDL_UART_CH, data[i])) + { + break; + } + } + } + + return i ? i : -1; +} + +#else +/** + * @brief Re-target fputc function. + * @param [in] ch + * @param [in] f + * @retval int32_t + */ +int32_t fputc(int32_t ch, FILE *f) +{ + (void)f; /* Prevent unused argument compilation warning */ + + return (Ok == UartPutChar(DDL_UART_CH, (char)ch)) ? ch: -1; +} +#endif + +/** + * @brief Initialize UART for debug printf function + * @param None + * @retval An en_result_t enumeration value: + * - Ok: Initialize successfully + * - Error: Don't permit write the GPIO configuration register or set baudrate unsuccessfully + */ +en_result_t DDL_PrintfInit(void) +{ + en_result_t enRet = Error; + + /* Check whether permit write GPIO register */ + if (READ_REG16_BIT(M4_GPIO->PWPR, GPIO_PWPR_WE)) + { + /* Configure USART TX pin. */ + MODIFY_REG16(DDL_UART_GPIO_TX_PFSR, GPIO_PFSR_FSEL, DDL_UART_GPIO_TX_FUNC); + + /* Enable USART function clock gate */ + CLEAR_REG32_BIT(M4_PWC->FCG3, DDL_UART_PWC_FCG); + + /*********************************************************************** + * Configure UART + *********************************************************************** + * Baud rate: 115200 + * Bit direction: LSB + * Data bits: 8 + * Stop bits: 1 + * Parity: None + * Sampling bits: 8 + **********************************************************************/ + /* Disbale TX/RX && clear flag */ + WRITE_REG32(DDL_UART_CH->CR1, (USART_CR1_CPE | USART_CR1_CORE | \ + USART_CR1_CFE | USART_CR1_CRTOF | \ + USART_CR1_CBE | USART_CR1_CWKUP | \ + USART_CR1_CLBD)); + + /* Set CR1 */ + WRITE_REG32(DDL_UART_CH->CR1, (USART_CR1_NFE | USART_CR1_SBS)); + + /* Set CR2: reset value */ + WRITE_REG32(DDL_UART_CH->CR2, 0x00000600UL); + + /* Set CR3: reset value */ + WRITE_REG32(DDL_UART_CH->CR3, 0x00UL); + + /* Set LBMC: reset value */ + WRITE_REG32(DDL_UART_CH->LBMC, 0x00UL); + + /* Set baudrate */ + enRet = UartSetBaudrate(DDL_UART_CH, DDL_UART_BAUDRATE); + if (Ok == enRet) + { + /* Enable TX function */ + SET_REG32_BIT(DDL_UART_CH->CR1, USART_CR1_TE); + } + } + + return enRet; +} +#endif /* DDL_PRINT_ENABLE */ + +/** + * @} + */ + +/** + * @defgroup UTILITY_Local_Functions UTILITY Local Functions + * @{ + */ +#if (DDL_PRINT_ENABLE == DDL_ON) + +/** + * @brief UART transmit. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] cData The data for transmitting + * @retval An en_result_t enumeration value: + * - Ok: Send successfully + * - ErrorTimeout: Send timeout + */ +static en_result_t UartPutChar(M4_USART_TypeDef *USARTx, char cData) +{ + uint32_t u32TxEmpty; + en_result_t enRet = Ok; + __IO uint32_t u32Timeout = (HCLK_VALUE / DDL_UART_BAUDRATE); + + /* Wait TX data register empty */ + do + { + u32Timeout--; + u32TxEmpty = READ_REG32_BIT(USARTx->SR, USART_SR_TXE); + } while ((u32Timeout > 0UL) && (0UL == u32TxEmpty)); + + if (0UL != u32TxEmpty) + { + WRITE_REG32(USARTx->DR, (uint32_t)cData); + } + else + { + enRet = ErrorTimeout; + } + + return enRet; +} + +/** + * @brief Set UART baudrate. + * @param [in] USARTx Pointer to USART instance register base + * This parameter can be one of the following values: + * @arg M4_USART1: USART unit 1 instance register base + * @arg M4_USART2: USART unit 2 instance register base + * @arg M4_USART3: USART unit 3 instance register base + * @arg M4_USART4: USART unit 4 instance register base + * @arg M4_USART5: USART unit 5 instance register base + * @arg M4_USART6: USART unit 6 instance register base + * @arg M4_USART7: USART unit 7 instance register base + * @arg M4_USART8: USART unit 8 instance register base + * @arg M4_USART9: USART unit 9 instance register base + * @arg M4_USART10: USART unit 10 instance register base + * @param [in] u32Baudrate UART baudrate + * @retval An en_result_t enumeration value: + * - Ok: Set successfully + * - Error: Baudrate set unsuccessfully + */ +static en_result_t UartSetBaudrate(M4_USART_TypeDef *USARTx, + uint32_t u32Baudrate) +{ + uint32_t B; + uint32_t C; + uint32_t OVER8; + float32_t DIV; + uint32_t DIV_Integer; + uint32_t u32Prescaler; + uint32_t u32Pclk; + uint64_t u64Temp; + en_result_t enRet = Error; + uint32_t DIV_Fraction = 0UL; + + if (u32Baudrate > 0UL) + { + B = u32Baudrate; + OVER8 = (0UL != (READ_REG32(USARTx->CR1) & USART_CR1_OVER8)) ? 1UL : 0UL; + u32Pclk = (SystemCoreClock >> ((uint32_t)(READ_REG32_BIT(M4_CMU->SCFGR, CMU_SCFGR_PCLK1S) >> CMU_SCFGR_PCLK1S_POS))); + + for (u32Prescaler = 0UL; u32Prescaler <= USART_PR_PSC; u32Prescaler++) + { + C = (u32Pclk / (1UL << (u32Prescaler * 2UL))); + + if (C > 0UL) + { + /* UART mode baudrate integer calculation formula: */ + /* B = C / (8 * (2 - OVER8) * (DIV_Integer + 1)) */ + /* DIV_Integer = (C / (B * 8 * (2 - OVER8))) - 1 */ + DIV = ((float)C / ((float)B * 8.0F * (2.0F - (float)OVER8))) - 1.0F; + DIV_Integer = (uint32_t)(DIV); + + if ((DIV > 0.0F) && (DIV_Integer < 0xFFUL)) + { + enRet = Ok; + if ((DIV - (float32_t)DIV_Integer) > 0.00001F) + { + /* UART mode baudrate fraction calculation formula: */ + /* B = C * (128 + DIV_Fraction) / (8 * (2 - OVER8) * (DIV_Integer + 1) * 256) */ + /* DIV_Fraction = (256 * (8 * (2 - OVER8) * (DIV_Integer + 1) * B) / C) - 128 */ + u64Temp = (uint64_t)((uint64_t)8UL * ((uint64_t)2UL - (uint64_t)OVER8) * ((uint64_t)DIV_Integer + 1UL) * (uint64_t)B); + DIV_Fraction = (uint32_t)(256UL * u64Temp / C - 128UL); + if (DIV_Fraction > 0x7FUL) + { + enRet = Error; + } + } + + if (Ok == enRet) + { + /* Set clock prescaler */ + WRITE_REG32(USARTx->PR, u32Prescaler); + + /* Enable or disable baudrate fraction function */ + MODIFY_REG32(USARTx->CR1, USART_CR1_FBME, (0UL != DIV_Fraction) ? USART_CR1_FBME : 0UL); + + /* Set USART_BRR register */ + WRITE_REG32(USARTx->BRR, ((DIV_Integer << USART_BRR_DIV_INTEGER_POS) + DIV_Fraction)); + break; + } + } + } + } + } + + return enRet; +} + +#endif /* DDL_PRINT_ENABLE */ + +/** + * @} + */ + +#endif /* DDL_UTILITY_ENABLE */ + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_wdt.c b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_wdt.c new file mode 100644 index 0000000000000000000000000000000000000000..093fc41d9dff5bd60e55c209bbb704a918903082 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/HC32F4A0_StdPeriph_Driver/src/hc32f4a0_wdt.c @@ -0,0 +1,263 @@ +/** + ******************************************************************************* + * @file hc32f4a0_wdt.c + * @brief This file provides firmware functions to manage the General Watch Dog + * Timer(WDT). + @verbatim + Change Logs: + Date Author Notes + 2020-06-12 Yangjp First version + 2020-09-04 Yangjp Optimize timeout handling in functions + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32f4a0_wdt.h" +#include "hc32f4a0_utility.h" + +/** + * @addtogroup HC32F4A0_DDL_Driver + * @{ + */ + +/** + * @defgroup DDL_WDT WDT + * @brief General Watch Dog Timer + * @{ + */ + +#if (DDL_WDT_ENABLE == DDL_ON) + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/** + * @defgroup WDT_Local_Macros WDT Local Macros + * @{ + */ + +/* WDT Registers Clear Mask */ +#define WDT_CR_CLEAR_MASK (WDT_CR_PERI | WDT_CR_CKS | WDT_CR_WDPT | \ + WDT_CR_SLPOFF | WDT_CR_ITS) + +/* WDT Refresh Key */ +#define WDT_REFRESH_KEY_START (0x0123UL) +#define WDT_REFRESH_KEY_END (0x3210UL) + +/* WDT clear flag timeout(ms) */ +#define WDT_CLEAR_FLAG_TIMEOUT (5UL) + +/** + * @defgroup WDT_Check_Parameters_Validity WDT Check Parameters Validity + * @{ + */ +#define IS_WDT_COUNTER_CYCLE(x) \ +( ((x) == WDT_COUNTER_CYCLE_256) || \ + ((x) == WDT_COUNTER_CYCLE_4096) || \ + ((x) == WDT_COUNTER_CYCLE_16384) || \ + ((x) == WDT_COUNTER_CYCLE_65536)) + +#define IS_WDT_CLOCK_DIVISION(x) \ +( ((x) == WDT_CLOCK_DIV4) || \ + ((x) == WDT_CLOCK_DIV64) || \ + ((x) == WDT_CLOCK_DIV128) || \ + ((x) == WDT_CLOCK_DIV256) || \ + ((x) == WDT_CLOCK_DIV512) || \ + ((x) == WDT_CLOCK_DIV1024) || \ + ((x) == WDT_CLOCK_DIV2048) || \ + ((x) == WDT_CLOCK_DIV8192)) + +#define IS_WDT_ALLOW_REFRESH_RANGE(x) \ +( ((x) == WDT_RANGE_0TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT) || \ + ((x) == WDT_RANGE_25TO50PCT) || \ + ((x) == WDT_RANGE_0TO50PCT) || \ + ((x) == WDT_RANGE_50TO75PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO75PCT) || \ + ((x) == WDT_RANGE_25TO75PCT) || \ + ((x) == WDT_RANGE_0TO75PCT) || \ + ((x) == WDT_RANGE_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_25TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_0TO50PCT_75TO100PCT) || \ + ((x) == WDT_RANGE_50TO100PCT) || \ + ((x) == WDT_RANGE_0TO25PCT_50TO100PCT) || \ + ((x) == WDT_RANGE_25TO100PCT)) + +#define IS_WDT_LPM_COUNT(x) \ +( ((x) == WDT_LPM_COUNT_CONTINUE) || \ + ((x) == WDT_LPM_COUNT_STOP)) + +#define IS_WDT_REQUEST_TYPE(x) \ +( ((x) == WDT_TRIG_EVENT_INT) || \ + ((x) == WDT_TRIG_EVENT_RESET)) + +#define IS_WDT_FLAG(x) \ +( (0UL != (x)) && \ + (0UL == ((x) & ((uint32_t)(~(WDT_FLAG_UDF | WDT_FLAG_REF)))))) + +/** + * @} + */ + +/** + * @} + */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * @defgroup WDT_Global_Functions WDT Global Functions + * @{ + */ + +/** + * @brief Initialize WDT. + * @param [in] pstcWdtInit Pointer to a @ref stc_wdt_init_t structure + * @retval An en_result_t enumeration value: + * - Ok: Initialize success + * - ErrorInvalidParameter: Invalid parameter + */ +en_result_t WDT_Init(const stc_wdt_init_t *pstcWdtInit) +{ + en_result_t enRet = Ok; + + if(NULL == pstcWdtInit) + { + enRet = ErrorInvalidParameter; + } + else + { + /* Check parameters */ + DDL_ASSERT(IS_WDT_COUNTER_CYCLE(pstcWdtInit->u32CountCycle)); + DDL_ASSERT(IS_WDT_CLOCK_DIVISION(pstcWdtInit->u32ClockDivision)); + DDL_ASSERT(IS_WDT_ALLOW_REFRESH_RANGE(pstcWdtInit->u32RefreshRange)); + DDL_ASSERT(IS_WDT_LPM_COUNT(pstcWdtInit->u32LPModeCountEn)); + DDL_ASSERT(IS_WDT_REQUEST_TYPE(pstcWdtInit->u32TrigType)); + + /* WDT CR Configuration(Software Start Mode) */ + MODIFY_REG32(M4_WDT->CR, WDT_CR_CLEAR_MASK, + (pstcWdtInit->u32CountCycle | pstcWdtInit->u32ClockDivision | + pstcWdtInit->u32RefreshRange | pstcWdtInit->u32LPModeCountEn | + pstcWdtInit->u32TrigType)); + } + + return enRet; +} + +/** + * @brief WDT feed dog. + * @note In software startup mode, Start counter when refreshing for the first time. + * @param None + * @retval None + */ +void WDT_Feed(void) +{ + WRITE_REG32(M4_WDT->RR, WDT_REFRESH_KEY_START); + WRITE_REG32(M4_WDT->RR, WDT_REFRESH_KEY_END); +} + +/** + * @brief Get WDT flag status. + * @param [in] u32Flag Specifies the WDT flag type. + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count Underflow flag + * @arg WDT_FLAG_REF: Refresh Error flag + * @retval An en_flag_status_t enumeration value: + * - Set: Flag is set + * - Reset: Flag is reset + */ +en_flag_status_t WDT_GetStatus(uint32_t u32Flag) +{ + en_flag_status_t enFlagSta = Reset; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + if (0UL != (READ_REG32_BIT(M4_WDT->SR, u32Flag))) + { + enFlagSta = Set; + } + + return enFlagSta; +} + +/** + * @brief Clear WDT flag status. + * @param [in] u32Flag Specifies the WDT flag type. + * This parameter can be one or any combination of the following values: + * @arg WDT_FLAG_UDF: Count Underflow flag + * @arg WDT_FLAG_REF: Refresh Error flag + * @retval An en_result_t enumeration value: + * - Ok: Clear flag success + * - ErrorTimeout: Clear flag timeout + */ +en_result_t WDT_ClearStatus(uint32_t u32Flag) +{ + __IO uint32_t u32Count; + en_result_t enRet = Ok; + + /* Check parameters */ + DDL_ASSERT(IS_WDT_FLAG(u32Flag)); + + CLEAR_REG32_BIT(M4_WDT->SR, u32Flag); + /* Waiting for FLAG bit clear */ + u32Count = WDT_CLEAR_FLAG_TIMEOUT * (HCLK_VALUE / 20000UL); + while (0UL != READ_REG32_BIT(M4_WDT->SR, u32Flag)) + { + if (0UL == u32Count) + { + enRet = ErrorTimeout; + break; + } + u32Count--; + } + + return enRet; +} + +/** + * @} + */ + +#endif /* DDL_WDT_ENABLE */ + +/** + * @} + */ + +/** +* @} +*/ + +/****************************************************************************** + * EOF (not truncated) + *****************************************************************************/ diff --git a/bsp/hc32f4a0/Libraries/LICENSE b/bsp/hc32f4a0/Libraries/LICENSE new file mode 100644 index 0000000000000000000000000000000000000000..72823826b8a523f9aa409f11a9daa817f6a2ae2e --- /dev/null +++ b/bsp/hc32f4a0/Libraries/LICENSE @@ -0,0 +1,29 @@ +BSD 3-Clause License + +Copyright (c) 2020, Huada Semiconductor Co., Ltd ("HDSC") +All rights reserved. + +Redistribution and use in source and binary forms, with or without +modification, are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. + +* Redistributions in binary form must reproduce the above copyright notice, + this list of conditions and the following disclaimer in the documentation + and/or other materials provided with the distribution. + +* Neither the name of the copyright holder nor the names of its + contributors may be used to endorse or promote products derived from + this software without specific prior written permission. + +THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. diff --git a/bsp/hc32f4a0/Libraries/SConscript b/bsp/hc32f4a0/Libraries/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..c5cb672a38b929ecd11251beef0566dabd13ba99 --- /dev/null +++ b/bsp/hc32f4a0/Libraries/SConscript @@ -0,0 +1,70 @@ +# RT-Thread building script for bridge + +import rtconfig +Import('RTT_ROOT') +from building import * + +# get current directory +cwd = GetCurrentDir() + +# The set of source files associated with this SConscript file. +src = Split(""" +CMSIS/Device/HDSC/HC32F4A0/Source/system_hc32f4a0.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_clk.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_dma.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_efm.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_gpio.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_icg.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_interrupts.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_pwc.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_sram.c +HC32F4A0_StdPeriph_Driver/src/hc32f4a0_utility.c +""") + +#src += Glob('HC32F4A0_StdPeriph_Driver/src/*.c') + +if GetDepend(['RT_USING_SERIAL']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_usart.c'] + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmr0.c'] + +if GetDepend(['RT_USING_I2C']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_spi.c'] + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_qspi.c'] + +if GetDepend(['RT_USING_CAN']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_can.c'] + +if GetDepend(['RT_USING_ADC']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_adc.c'] + +if GetDepend(['RT_USING_RTC']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_rtc.c'] + +if GetDepend(['RT_USING_WDT']): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_wdt.c'] + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_swdt.c'] + +if GetDepend(['RT_USING_HWTIMER']) or GetDepend(['RT_USING_PWM'] or GetDepend(['RT_USING_PULSE_ENCODER'])): + src += ['HC32F4A0_StdPeriph_Driver/src/hc32f4a0_tmra.c'] + +#add for startup script +if rtconfig.CROSS_TOOL == 'gcc': + src = src + ['CMSIS/Device/HDSC/HC32F4A0/Source/GCC/startup_hc32f4a0.S'] +elif rtconfig.CROSS_TOOL == 'keil': + src = src + ['CMSIS/Device/HDSC/HC32F4A0/Source/ARM/startup_hc32f4a0.s'] +elif rtconfig.CROSS_TOOL == 'iar': + src = src + ['CMSIS/Device/HDSC/HC32F4A0/Source/IAR/startup_hc32f4a0.s'] + +#add headfile script +path = [cwd + '/CMSIS/Include', + cwd + '/CMSIS/Device/HDSC/HC32F4A0/Include', + cwd + '/HC32F4A0_StdPeriph_Driver/inc'] + +CPPDEFINES = ['USE_DDL_DRIVER', rtconfig.MCU_TYPE, '__DEBUG'] + +group = DefineGroup('HC32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES) + +Return('group') diff --git a/bsp/hc32f4a0/README.md b/bsp/hc32f4a0/README.md new file mode 100644 index 0000000000000000000000000000000000000000..3fc1c5ad40d074fe84265b2c847374267313e58f --- /dev/null +++ b/bsp/hc32f4a0/README.md @@ -0,0 +1,117 @@ +# HDSC EV_F4A0_LQ176 开发板 BSP 说明 + +## 简介 + +本文档为华大半导体为 EV_F4A0_LQ176 开发板提供的 BSP (板级支持包) 说明。 + +主要内容如下： + +- 开发板资源介绍 +- BSP 快速上手 +- 进阶使用方法 + +通过阅读快速上手章节开发者可以快速地上手该 BSP，将 RT-Thread 运行在开发板上。在进阶使用指南章节，将会介绍更多高级功能，帮助开发者利用 RT-Thread 驱动更多板载资源。 + +## 开发板介绍 + +EV_F4A0_LQ176 是 HDSC 官方推出的开发板，搭载 HC32F4A0SITB 芯片，基于 ARM Cortex-M4 内核，最高主频 240 MHz，具有丰富的板载资源，可以充分发挥 HC32F4A0SITB 的芯片性能。 + +开发板外观如下图所示： + +![board](figures/board.jpg) + +EV_F4A0_LQ176 开发板常用 **板载资源** 如下： + +- MCU：HC32F4A0SITB，主频 240MHz，2048KB FLASH ，512KB RAM +- 外部 RAM：IS62WV51216(SRAM,512KB) IS42S16400J(SDRAM,1MB) +- 外部 FLASH: MT29F2G08AB(Nand,256MB) W25Q64(SPI,64M) +- 常用外设 + - LED：11 个，DAP LED (D82), USB LED (D26,D19,D4), Power LED (D39,D83), JTAG LED(D80), MCU LED(D81), user LED(LED0,LED1,LED2)。 + - 按键：11 个，SW0~SW9(矩阵键盘)、WAKEUP(SW10)、RESET。 +- 常用接口：USB 转串口、SD 卡接口、以太网接口、LCD 接口、USB HS、USB FS、USB 3300、DVP接口、3.5mm 耳机接口、Line in 接口、喇叭接口 +- 调试接口：板载DAP调试器、标准 JTAG/SWD。 + +开发板更多详细信息请参考华大半导体半导体[EV_F4A0_LQ176](https://www.hdsc.com.cn) + +## 外设支持 + +本 BSP 目前对外设的支持情况如下： + +| **板载外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| USB 转串口 | 支持 | 使用 UART1 | +| SPI Flash | 支持 | 使用 SPI1 | +| LED | 支持 | LED | +| **片上外设** | **支持情况** | **备注** | +| :------------ | :-----------: | :-----------------------------------: | +| GPIO | 支持 | PA0, PA1... PI15 ---> PIN: 0, 1...144 | +| UART | 支持 | UART1~10 | +| SPI | 支持 | SPI1~6 | +| I2C | 支持 | 软件 I2C | +| RTC | 支持 | 支持外部晶振和内部低速时钟 | +| PWM | 支持 | | +| HWTIMER | 支持 | | +| LED | 支持 | LED2 | + + +## 使用说明 + +使用说明分为如下两个章节： + +- 快速上手 + + 本章节是为刚接触 RT-Thread 的新手准备的使用说明，遵循简单的步骤即可将 RT-Thread 操作系统运行在该开发板上，看到实验效果 。 + +- 进阶使用 + + 本章节是为需要在 RT-Thread 操作系统上使用更多开发板资源的开发者准备的。通过使用 ENV 工具对 BSP 进行配置，可以开启更多板载资源，实现更多高级功能。 + + +### 快速上手 + +本 BSP 为开发者提供 MDK4、MDK5 和 IAR 工程，并且支持 GCC 开发环境。下面以 MDK5 开发环境为例，介绍如何将系统运行起来。 + +#### 硬件连接 + +使用 Type-A to Mini-B 线连接开发板和 PC 供电，D81,D82,D39 会点亮。 + +#### 编译下载 + +双击 project.uvprojx 文件，打开 MDK5 工程，编译并下载程序到开发板。 + +> 工程默认配置使用 J-LINK 下载程序，点击下载按钮即可下载程序到开发板。 + +#### 运行结果 + +下载程序成功之后，系统会自动运行，观察开发板上 LED 的运行效果，绿色D81,D82,D39 常亮、绿色 D26 会周期性闪烁。 + +USB 虚拟 COM 端口默认连接串口 1，在终端工具里打开相应的串口，复位设备后，可以看到 RT-Thread 的输出信息: + +``` + \ | / +- RT - Thread Operating System + / | \ 4.0.3 build Dec 22 2020 + 2006 - 2020 Copyright by rt-thread team +Os is Start!!! +msh > +``` + +### 进阶使用 + +此 BSP 默认只开启了 GPIO 和 串口 1 的功能，更多高级功能需要利用 env 工具对 BSP 进行配置，步骤如下： + +1. 在 bsp 下打开 env 工具。 + +2. 输入`menuconfig`命令配置工程，配置好之后保存退出。 + +3. 输入`pkgs --update`命令更新软件包。 + +4. 输入`scons --target=mdk4/mdk5/iar` 命令重新生成工程。 + +## 注意事项 + +## 联系人信息 + +维护人: + +- [华大半导体CDT](http://www.hdsc.com.cn/mcu.htm), 邮箱： \ No newline at end of file diff --git a/bsp/hc32f4a0/SConscript b/bsp/hc32f4a0/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..24bb4646ab77bd26114d2c871e4862dc33ea1a5f --- /dev/null +++ b/bsp/hc32f4a0/SConscript @@ -0,0 +1,15 @@ +# for module compiling +import os +Import('RTT_ROOT') +from building import * + +cwd = GetCurrentDir() +objs = [] +list = os.listdir(cwd) + +for d in list: + path = os.path.join(cwd, d) + if os.path.isfile(os.path.join(path, 'SConscript')): + objs = objs + SConscript(os.path.join(d, 'SConscript')) + +Return('objs') diff --git a/bsp/hc32f4a0/SConstruct b/bsp/hc32f4a0/SConstruct new file mode 100644 index 0000000000000000000000000000000000000000..b358e0d0458cb9e2f82c9d0e3d3ea6ec647e18fd --- /dev/null +++ b/bsp/hc32f4a0/SConstruct @@ -0,0 +1,45 @@ +import os +import sys +import rtconfig + +print "############sconstruct##############" +if os.getenv('RTT_ROOT'): + RTT_ROOT = os.getenv('RTT_ROOT') +else: + RTT_ROOT = os.path.normpath(os.getcwd() + '/../..') + +print "RTT_ROOT: " + RTT_ROOT + +sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')] +try: + from building import * +except: + print('Cannot found RT-Thread root directory, please check RTT_ROOT') + print(RTT_ROOT) + exit(-1) + +TARGET = 'hc32f4A0.' + rtconfig.TARGET_EXT + +DefaultEnvironment(tools=[]) +env = Environment(tools = ['mingw'], + AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS, + CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS, + AR = rtconfig.AR, ARFLAGS = '-rc', + LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS) +env.PrependENVPath('PATH', rtconfig.EXEC_PATH) + +if rtconfig.PLATFORM == 'iar': + env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES']) + env.Replace(ARFLAGS = ['']) + env.Replace(LINKCOM = env["LINKCOM"] + ' --map project.map') + +Export('RTT_ROOT') +Export('rtconfig') + +# prepare building environment +print "######################env:" +print env +objs = PrepareBuilding(env, RTT_ROOT, has_libcpu=False) + +# make a building +DoBuilding(TARGET, objs) diff --git a/bsp/hc32f4a0/applications/SConscript b/bsp/hc32f4a0/applications/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..6f66f7ab7360b02f3561ec14d3f28841190e7e83 --- /dev/null +++ b/bsp/hc32f4a0/applications/SConscript @@ -0,0 +1,12 @@ +import rtconfig +from building import * + +cwd = GetCurrentDir() +CPPPATH = [cwd, str(Dir('#'))] +src = Split(""" +main.c +""") + +group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f4a0/applications/main.c b/bsp/hc32f4a0/applications/main.c new file mode 100644 index 0000000000000000000000000000000000000000..8235b147ecea23ac6cf0401da8d973d92e39668a --- /dev/null +++ b/bsp/hc32f4a0/applications/main.c @@ -0,0 +1,75 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "hc32_ddl.h" +#include "board.h" + +#include +#include + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/* defined the LED pin: PC9 */ +#define LED_PIN (41) + +#define DELAY_MS (RT_TICK_PER_SECOND) /* 1s */ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +/** + ******************************************************************************* + ** \brief Main function of GPIO output + ** + ** \param None + ** + ** \retval int32_t Return value, if needed + ** + ******************************************************************************/ +int32_t main(void) +{ + rt_kprintf("Os is Start!!! \n"); + + while(1) + { + rt_pin_mode(LED_PIN, PIN_MODE_OUTPUT); + rt_pin_write(LED_PIN, PIN_HIGH); + rt_thread_delay(DELAY_MS); + rt_pin_write(LED_PIN, PIN_LOW); + rt_thread_delay(DELAY_MS); + }; +} + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/board/Kconfig b/bsp/hc32f4a0/board/Kconfig new file mode 100644 index 0000000000000000000000000000000000000000..c33c82d89e04ce84f6771e40dbf5ceaba65162be --- /dev/null +++ b/bsp/hc32f4a0/board/Kconfig @@ -0,0 +1,336 @@ +menu "Hardware Drivers Config" + +config MCU_HC32F4A0 + bool + select ARCH_ARM_CORTEX_M4 + select RT_USING_COMPONENTS_INIT + select RT_USING_USER_MAIN + default y + +menu "Onboard Peripheral Drivers" + +endmenu + +menu "On-chip Peripheral Drivers" + config BSP_USING_GPIO + bool "Enable GPIO" + select RT_USING_PIN + default y + + menuconfig BSP_USING_UART + bool "Enable UART" + default y + select RT_USING_SERIAL + if BSP_USING_UART + config BSP_USING_UART1 + bool "Enable UART1" + default y + + config BSP_UART1_RX_USING_DMA + bool "Enable UART1 RX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_UART1_TX_USING_DMA + bool "Enable UART1 TX DMA" + depends on BSP_USING_UART1 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART2 + bool "Enable UART2" + default n + + config BSP_UART2_RX_USING_DMA + bool "Enable UART2 RX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_UART2_TX_USING_DMA + bool "Enable UART2 TX DMA" + depends on BSP_USING_UART2 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART3 + bool "Enable UART3" + default n + + config BSP_USING_UART4 + bool "Enable UART4" + default n + + config BSP_USING_UART5 + bool "Enable UART5" + default n + + config BSP_USING_UART6 + bool "Enable UART6" + default n + + config BSP_UART6_RX_USING_DMA + bool "Enable UART6 RX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_UART6_TX_USING_DMA + bool "Enable UART6 TX DMA" + depends on BSP_USING_UART6 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART7 + bool "Enable UART7" + default n + + config BSP_UART7_RX_USING_DMA + bool "Enable UART7 RX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_UART7_TX_USING_DMA + bool "Enable UART7 TX DMA" + depends on BSP_USING_UART7 && RT_SERIAL_USING_DMA + default n + + config BSP_USING_UART8 + bool "Enable UART8" + default n + + config BSP_USING_UART9 + bool "Enable UART9" + default n + + config BSP_USING_UART10 + bool "Enable UART10" + default n + endif + + menuconfig BSP_USING_I2C1 + bool "Enable I2C1 BUS (software simulation)" + default y + select RT_USING_I2C + select RT_USING_I2C_BITOPS + select RT_USING_PIN + if BSP_USING_I2C1 + config BSP_I2C1_SCL_PIN + int "i2c1 scl pin number" + range 1 176 + default 51 + config BSP_I2C1_SDA_PIN + int "I2C1 sda pin number" + range 1 176 + default 90 + endif + + menuconfig BSP_USING_SPI + bool "Enable SPI BUS" + default n + select RT_USING_SPI + if BSP_USING_SPI + config BSP_USING_SPI1 + bool "Enable SPI1 BUS" + default n + + config BSP_SPI1_TX_USING_DMA + bool "Enable SPI1 TX DMA" + depends on BSP_USING_SPI1 + default n + + config BSP_SPI1_RX_USING_DMA + bool "Enable SPI1 RX DMA" + depends on BSP_USING_SPI1 + select BSP_SPI1_TX_USING_DMA + default n + + config BSP_USING_SPI2 + bool "Enable SPI2 BUS" + default n + + config BSP_SPI2_TX_USING_DMA + bool "Enable SPI2 TX DMA" + depends on BSP_USING_SPI2 + default n + + config BSP_SPI2_RX_USING_DMA + bool "Enable SPI2 RX DMA" + depends on BSP_USING_SPI2 + select BSP_SPI2_TX_USING_DMA + default n + + config BSP_USING_SPI3 + bool "Enable SPI3 BUS" + default n + + config BSP_SPI3_TX_USING_DMA + bool "Enable SPI3 TX DMA" + depends on BSP_USING_SPI3 + default n + + config BSP_SPI3_RX_USING_DMA + bool "Enable SPI3 RX DMA" + depends on BSP_USING_SPI3 + select BSP_SPI3_TX_USING_DMA + default n + + config BSP_USING_SPI4 + bool "Enable SPI4 BUS" + default n + + config BSP_SPI4_TX_USING_DMA + bool "Enable SPI4 TX DMA" + depends on BSP_USING_SPI4 + default n + + config BSP_SPI4_RX_USING_DMA + bool "Enable SPI4 RX DMA" + depends on BSP_USING_SPI4 + select BSP_SPI4_TX_USING_DMA + default n + + config BSP_USING_SPI5 + bool "Enable SPI5 BUS" + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 TX DMA" + depends on BSP_USING_SPI5 + default n + + config BSP_SPI5_RX_USING_DMA + bool "Enable SPI5 RX DMA" + depends on BSP_USING_SPI5 + select BSP_SPI5_TX_USING_DMA + default n + + config BSP_USING_SPI6 + bool "Enable SPI6 BUS" + default n + + config BSP_SPI6_TX_USING_DMA + bool "Enable SPI6 TX DMA" + depends on BSP_USING_SPI6 + default n + + config BSP_SPI6_RX_USING_DMA + bool "Enable SPI6 RX DMA" + depends on BSP_USING_SPI6 + select BSP_SPI6_TX_USING_DMA + default n + endif + + menuconfig BSP_USING_RTC + bool "Enable RTC" + select RT_USING_RTC + select RT_USING_LIBC + default n + + if BSP_USING_RTC + choice + prompt "Select clock source" + default BSP_RTC_USING_LRC + + config BSP_RTC_USING_XTAL32 + bool "RTC USING XTAL32" + + config BSP_RTC_USING_LRC + bool "RTC USING LRC" + endchoice + endif + + menuconfig BSP_USING_PWM + bool "Enable PWM" + default n + select RT_USING_PWM + if BSP_USING_PWM + menuconfig BSP_USING_PWM1 + bool "Enable timer1 output pwm" + default n + if BSP_USING_PWM1 + config BSP_USING_PWM1_CH1 + bool "Enable PWM1 channel1" + default n + + config BSP_USING_PWM1_CH2 + bool "Enable PWM1 channel2" + default n + + config BSP_USING_PWM1_CH3 + bool "Enable PWM1 channel3" + default n + + config BSP_USING_PWM1_CH4 + bool "Enable PWM1 channel4" + default n + endif + + menuconfig BSP_USING_PWM2 + bool "Enable timer2 output pwm" + default n + if BSP_USING_PWM2 + config BSP_USING_PWM2_CH1 + bool "Enable PWM2 channel1" + default n + + config BSP_USING_PWM2_CH2 + bool "Enable PWM2 channel2" + default n + + config BSP_USING_PWM2_CH3 + bool "Enable PWM2 channel3" + default n + + config BSP_USING_PWM2_CH4 + bool "Enable PWM2 channel4" + default n + endif + endif + + menuconfig BSP_USING_TIMER + bool "Enable TIMER" + default n + select RT_USING_HWTIMER + if BSP_USING_TIMER + config BSP_USING_TIMER5 + bool "Enable TIMER5" + default n + + config BSP_USING_TIMER6 + bool "Enable TIMER6" + default n + + config BSP_USING_TIMER7 + bool "Enable TIMER7" + default n + + config BSP_USING_TIMER8 + bool "Enable TIMER8" + default n + endif + + menuconfig BSP_USING_PULSE_ENCODER + bool "Enable Pulse Encoder" + default n + select RT_USING_PULSE_ENCODER + if BSP_USING_PULSE_ENCODER + config BSP_USING_PULSE_ENCODER9 + bool "Enable Pulse Encoder9" + default n + + config BSP_USING_PULSE_ENCODER10 + bool "Enable Pulse Encoder10" + default n + + config BSP_USING_PULSE_ENCODER11 + bool "Enable Pulse Encoder11" + default n + + config BSP_USING_PULSE_ENCODER12 + bool "Enable Pulse Encoder12" + default n + endif + +endmenu + +menu "Board extended module Drivers" + +endmenu + +endmenu diff --git a/bsp/hc32f4a0/board/SConscript b/bsp/hc32f4a0/board/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..e06723028ffbbfbebac4cda1544df0e813b57ef9 --- /dev/null +++ b/bsp/hc32f4a0/board/SConscript @@ -0,0 +1,15 @@ +from building import * + +cwd = GetCurrentDir() + +CPPPATH = [cwd] + +# add general drivers +src = Split(''' +board.c +board_config.c +''') + +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f4a0/board/board.c b/bsp/hc32f4a0/board/board.c new file mode 100644 index 0000000000000000000000000000000000000000..de249f4b7c1f08854e235540ad1d0dcc7bad9b49 --- /dev/null +++ b/bsp/hc32f4a0/board/board.c @@ -0,0 +1,190 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + + +#include +#include + +#include "board.h" + +/** + * @addtogroup HC32 + */ + +/*@{*/ + +/******************************************************************************* +* Function Name : Peripheral_WE +* Description : MCU Peripheral registers write unprotected. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Peripheral_WE(void) +{ + /* Unlock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_Unlock(); + /* Unlock PWC register: FCG0 */ + PWC_FCG0_Unlock(); + /* Unlock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_Unlock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1); + /* Unlock SRAM register: WTCR */ + SRAM_WTCR_Unlock(); + /* Unlock SRAM register: CKCR */ + // SRAM_CKCR_Unlock(); + /* Unlock all EFM registers */ + EFM_Unlock(); + /* Unlock EFM register: FWMC */ + // EFM_FWMC_Unlock(); + /* Unlock EFM OTP write protect registers */ + // EFM_OTP_WP_Unlock(); +} + +/******************************************************************************* +* Function Name : Peripheral_WP +* Description : MCU Peripheral registers write protected. +* Input : None +* Output : None +* Return : None +*******************************************************************************/ +void Peripheral_WP(void) +{ + /* Lock GPIO register: PSPCR, PCCR, PINAER, PCRxy, PFSRxy */ + GPIO_Lock(); + /* Lock PWC register: FCG0 */ + // PWC_FCG0_Lock(); + /* Lock PWC, CLK, PVD registers, @ref PWC_REG_Write_Unlock_Code for details */ + PWC_Lock(PWC_UNLOCK_CODE_0 | PWC_UNLOCK_CODE_1); + /* Lock SRAM register: WTCR */ + // SRAM_WTCR_Lock(); + /* Lock SRAM register: CKCR */ + // SRAM_CKCR_Lock(); + /* Lock all EFM registers */ + // EFM_Lock(); + /* Lock EFM OTP write protect registers */ + // EFM_OTP_WP_Lock(); + /* Lock EFM register: FWMC */ + // EFM_FWMC_Lock(); +} + +/** + * @brief BSP clock initialize. + * Set board system clock to PLLH@240MHz + * @param None + * @retval None + */ +void rt_hw_board_clock_init(void) +{ + stc_clk_pllh_init_t stcPLLHInit; + + CLK_ClkDiv(CLK_CATE_ALL, \ + (CLK_PCLK0_DIV1 | CLK_PCLK1_DIV2 | CLK_PCLK2_DIV4 | \ + CLK_PCLK3_DIV4 | CLK_PCLK4_DIV2 | CLK_EXCLK_DIV2 | \ + CLK_HCLK_DIV1)); + + (void)CLK_PLLHStrucInit(&stcPLLHInit); + /* VCO = (8/1)*120 = 960MHz*/ + stcPLLHInit.u8PLLState = CLK_PLLH_ON; + stcPLLHInit.PLLCFGR = 0UL; + stcPLLHInit.PLLCFGR_f.PLLM = 1UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLN = 120UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLP = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLQ = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLR = 4UL - 1UL; + stcPLLHInit.PLLCFGR_f.PLLSRC = CLK_PLLSRC_XTAL; + (void)CLK_PLLHInit(&stcPLLHInit); + + /* Highspeed SRAM set to 1 Read/Write wait cycle */ + SRAM_SetWaitCycle(SRAM_SRAMH, SRAM_WAIT_CYCLE_1, SRAM_WAIT_CYCLE_1); + /* SRAM1_2_3_4_backup set to 2 Read/Write wait cycle */ + SRAM_SetWaitCycle((SRAM_SRAM123 | SRAM_SRAM4 | SRAM_SRAMB), SRAM_WAIT_CYCLE_2, SRAM_WAIT_CYCLE_2); + /* 0-wait @ 40MHz */ + EFM_SetWaitCycle(EFM_WAIT_CYCLE_5); + /* 4 cycles for 200 ~ 250MHz */ + GPIO_SetReadWaitCycle(GPIO_READ_WAIT_4); + CLK_SetSysClkSrc(CLK_SYSCLKSOURCE_PLLH); +} + +/******************************************************************************* + * Function Name : SysTick_Configuration + * Description : Configures the SysTick for OS tick. + * Input : None + * Output : None + * Return : None + *******************************************************************************/ +void SysTick_Configuration(void) +{ + stc_clk_freq_t stcClkFreq; + rt_uint32_t cnts; + + CLK_GetClockFreq(&stcClkFreq); + + cnts = (rt_uint32_t)stcClkFreq.hclkFreq / RT_TICK_PER_SECOND; + + SysTick_Config(cnts); +} + +/** + * This is the timer interrupt service routine. + * + */ +void SysTick_Handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + rt_tick_increase(); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +/** + * This function will initialize HC32 board. + */ +void rt_hw_board_init() +{ + /* Unlock the protected registers. */ + Peripheral_WE(); + + /* Configure the System clock */ + rt_hw_board_clock_init(); + + /* Configure the SysTick */ + SysTick_Configuration(); + +#ifdef RT_USING_HEAP + rt_system_heap_init((void *)HEAP_BEGIN, (void *)HEAP_END); +#endif + +#ifdef RT_USING_COMPONENTS_INIT + rt_components_board_init(); +#endif + +#ifdef RT_USING_CONSOLE + rt_console_set_device(RT_CONSOLE_DEVICE_NAME); +#endif +} + +void rt_hw_us_delay(rt_uint32_t us) +{ + uint32_t start, now, delta, reload, us_tick; + start = SysTick->VAL; + reload = SysTick->LOAD; + us_tick = SystemCoreClock / 1000000UL; + + do{ + now = SysTick->VAL; + delta = start > now ? start - now : reload + start - now; + } + while(delta < us_tick * us); +} +/*@}*/ diff --git a/bsp/hc32f4a0/board/board.h b/bsp/hc32f4a0/board/board.h new file mode 100644 index 0000000000000000000000000000000000000000..927f7d78f29555b5068910f342030e08fe33171e --- /dev/null +++ b/bsp/hc32f4a0/board/board.h @@ -0,0 +1,51 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __BOARD_H__ +#define __BOARD_H__ + +#include +#include "hc32_ddl.h" +#include "drv_gpio.h" + +/* board configuration */ +#define SRAM_BASE 0x1FFE0000 +#define SRAM_SIZE 0x20000 +#define SRAM_END (SRAM_BASE + SRAM_SIZE) + +/* High speed sram. */ +#ifdef __CC_ARM +extern int Image$$RW_IRAM1$$ZI$$Limit; +#define HEAP_BEGIN (&Image$$RW_IRAM1$$ZI$$Limit) +#elif __ICCARM__ +#pragma section="HEAP" +#define HEAP_BEGIN (__segment_end("HEAP")) +#else +extern int __bss_end; +#define HEAP_BEGIN (&__bss_end) +#endif + +#ifdef __ICCARM__ +// Use *.icf ram symbal, to avoid hardcode. +extern char __ICFEDIT_region_RAM_end__; +#define HEAP_END (&__ICFEDIT_region_RAM_end__) +#else +#define HEAP_END SRAM_END +#endif + +void Peripheral_WE(void); +void Peripheral_WP(void); +void rt_hw_board_init(void); +void rt_hw_us_delay(rt_uint32_t us); + +#endif + +// <<< Use Configuration Wizard in Context Menu >>> diff --git a/bsp/hc32f4a0/board/board_config.c b/bsp/hc32f4a0/board/board_config.c new file mode 100644 index 0000000000000000000000000000000000000000..292b67de37fd7b18a4ecdf408a8a26f43ba60422 --- /dev/null +++ b/bsp/hc32f4a0/board/board_config.c @@ -0,0 +1,146 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ +#include +#include "board_config.h" + +/** + * The below functions will initialize HC32 board. + */ + +#if defined RT_USING_SERIAL +rt_err_t rt_hw_board_uart_init(M4_USART_TypeDef *USARTx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)USARTx) + { +#if defined(BSP_USING_UART1) + case (rt_uint32_t)M4_USART1: + /* Configure USART RX/TX pin. */ + GPIO_SetFunc(USART1_RX_PORT, USART1_RX_PIN, GPIO_FUNC_33_USART1_RX, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(USART1_TX_PORT, USART1_TX_PIN, GPIO_FUNC_32_USART1_TX, PIN_SUBFUNC_DISABLE); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined(RT_USING_PWM) +rt_err_t rt_hw_board_pwm_init(M4_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PWM1) + case (rt_uint32_t)M4_TMRA_1: +#if defined(BSP_USING_PWM1_CH1) + GPIO_SetFunc(PWM1_CH1_PORT, PWM1_CH1_PIN, PWM1_CH1_FUNC, PIN_SUBFUNC_DISABLE); +#endif +#if defined(BSP_USING_PWM1_CH2) + GPIO_SetFunc(PWM1_CH2_PORT, PWM1_CH2_PIN, PWM1_CH2_FUNC, PIN_SUBFUNC_DISABLE); +#endif + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif + +#if defined (RT_USING_SPI) +void hc32_board_spi_init(M4_SPI_TypeDef *M4_SPIx, rt_uint8_t mode) +{ +#if defined (BSP_USING_SPI1) + stc_gpio_init_t stcGpioCfg; + + GPIO_StructInit(&stcGpioCfg); + + /* Port configurate, High driving capacity for output pin. + CMOS input for input pin */ + if(mode & RT_SPI_3WIRE) + { + /* code */ + } + else + { + if(mode & RT_SPI_SLAVE) + { + stcGpioCfg.u16PinIType = PIN_ITYPE_CMOS; + } + else + { + stcGpioCfg.u16PinDrv = PIN_DRV_HIGH; + } + GPIO_Init(SPI1_NSS_PORT, SPI1_NSS_PIN, &stcGpioCfg); + GPIO_SetFunc(SPI1_NSS_PORT, SPI1_NSS_PIN, SPI1_NSS_GPIO_FUNC, PIN_SUBFUNC_DISABLE); + } + if(mode & RT_SPI_SLAVE) + { + stcGpioCfg.u16PinIType = PIN_ITYPE_CMOS; + GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioCfg); + GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioCfg); + stcGpioCfg.u16PinDrv = PIN_DRV_HIGH; + GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioCfg); + } + else + { + stcGpioCfg.u16PinDrv = PIN_DRV_HIGH; + GPIO_Init(SPI1_SCK_PORT, SPI1_SCK_PIN, &stcGpioCfg); + GPIO_Init(SPI1_MOSI_PORT, SPI1_MOSI_PIN, &stcGpioCfg); + stcGpioCfg.u16PinIType = PIN_ITYPE_CMOS; + GPIO_Init(SPI1_MISO_PORT, SPI1_MISO_PIN, &stcGpioCfg); + } + + GPIO_SetFunc(SPI1_SCK_PORT, SPI1_SCK_PIN, SPI1_SCK_GPIO_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(SPI1_MOSI_PORT, SPI1_MOSI_PIN, SPI1_MOSI_GPIO_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(SPI1_MISO_PORT, SPI1_MISO_PIN, SPI1_MISO_GPIO_FUNC, PIN_SUBFUNC_DISABLE); +#endif + +#if defined (BSP_USING_SPI2) + /* Config SPI2 relevant port according to SPI1 */ +#endif + +#if defined (BSP_USING_SPI3) + /* Config SPI3 relevant port according to SPI1 */ +#endif + +} +#endif + +#if defined(RT_USING_PULSE_ENCODER) +rt_err_t rt_hw_board_pulse_encoder_init(M4_TMRA_TypeDef *TMRAx) +{ + rt_err_t result = RT_EOK; + + switch ((rt_uint32_t)TMRAx) + { +#if defined(BSP_USING_PULSE_ENCODER9) + case (rt_uint32_t)M4_TMRA_9: + GPIO_SetFunc(PULSE_ENCODER9_CLKA_PORT, PULSE_ENCODER9_CLKA_PIN, PULSE_ENCODER9_CLKA_FUNC, PIN_SUBFUNC_DISABLE); + GPIO_SetFunc(PULSE_ENCODER9_CLKB_PORT, PULSE_ENCODER9_CLKB_PIN, PULSE_ENCODER9_CLKB_FUNC, PIN_SUBFUNC_DISABLE); + break; +#endif + default: + result = -RT_ERROR; + break; + } + + return result; +} +#endif diff --git a/bsp/hc32f4a0/board/board_config.h b/bsp/hc32f4a0/board/board_config.h new file mode 100644 index 0000000000000000000000000000000000000000..c029ee022330abf1d360137c4c9293e055328328 --- /dev/null +++ b/bsp/hc32f4a0/board/board_config.h @@ -0,0 +1,198 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __BOARD_CONFIG_H__ +#define __BOARD_CONFIG_H__ + +#include +#include "hc32_ddl.h" + +/*********** Port configure *********/ +#if defined(BSP_USING_UART1) +#define USART1_RX_PORT (GPIO_PORT_H) +#define USART1_RX_PIN (GPIO_PIN_13) + +#define USART1_TX_PORT (GPIO_PORT_H) +#define USART1_TX_PIN (GPIO_PIN_15) +#endif + +#if defined(BSP_USING_SPI1) +#define SPI1_NSS_PORT (GPIO_PORT_C) +#define SPI1_NSS_PIN (GPIO_PIN_07) +#define SPI1_NSS_GPIO_FUNC (GPIO_FUNC_0_GPO) + +#define SPI1_SCK_PORT (GPIO_PORT_C) +#define SPI1_SCK_PIN (GPIO_PIN_06) +#define SPI1_SCK_GPIO_FUNC (GPIO_FUNC_40_SPI1_SCK) + +#define SPI1_MOSI_PORT (GPIO_PORT_B) +#define SPI1_MOSI_PIN (GPIO_PIN_13) +#define SPI1_MOSI_GPIO_FUNC (GPIO_FUNC_41_SPI1_MOSI) + +#define SPI1_MISO_PORT (GPIO_PORT_B) +#define SPI1_MISO_PIN (GPIO_PIN_12) +#define SPI1_MISO_GPIO_FUNC (GPIO_FUNC_42_SPI1_MISO) +#endif + +#if defined(BSP_USING_PWM1) + +#if defined(BSP_USING_PWM1_CH1) +#define PWM1_CH1_PORT (GPIO_PORT_A) +#define PWM1_CH1_PIN (GPIO_PIN_08) +#define PWM1_CH1_FUNC (GPIO_FUNC_4_TIMA1_PWM1) +#endif + +#if defined(BSP_USING_PWM1_CH2) +#define PWM1_CH2_PORT (GPIO_PORT_A) +#define PWM1_CH2_PIN (GPIO_PIN_09) +#define PWM1_CH2_FUNC (GPIO_FUNC_4_TIMA1_PWM2) +#endif + +#endif + +#if defined(BSP_USING_PULSE_ENCODER9) +#define PULSE_ENCODER9_CLKA_PORT (GPIO_PORT_G) +#define PULSE_ENCODER9_CLKA_PIN (GPIO_PIN_04) +#define PULSE_ENCODER9_CLKA_FUNC (GPIO_FUNC_4_TIMA9_PWM1) + +#define PULSE_ENCODER9_CLKB_PORT (GPIO_PORT_G) +#define PULSE_ENCODER9_CLKB_PIN (GPIO_PIN_05) +#define PULSE_ENCODER9_CLKB_FUNC (GPIO_FUNC_4_TIMA9_PWM2) +#endif + +/*********** USART configure *********/ +#if defined(BSP_USING_UART1) + +#define USART1_RXERR_INT_IRQn (Int001_IRQn) +#define USART1_RXERR_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define USART1_RX_INT_IRQn (Int002_IRQn) +#define USART1_RX_INT_PRIO (DDL_IRQ_PRIORITY_00) + +#define USART1_TX_INT_IRQn (Int003_IRQn) +#define USART1_TX_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#if defined(RT_SERIAL_USING_DMA) +#if defined(BSP_UART1_RX_USING_DMA) +#define USART1_RXTO_TMR0_UNIT (M4_TMR0_1) +#define USART1_RXTO_TMR0_CH (TMR0_CH_A) +#define USART1_RXTO_INT_IRQn (Int004_IRQn) +#define USART1_RXTO_INT_PRIO (DDL_IRQ_PRIORITY_01) + +#define USART1_RX_DMA_UNIT (M4_DMA1) +#define USART1_RX_DMA_CH (DMA_CH0) +#define USART1_RX_DMA_INT_IRQn (Int005_IRQn) +#define USART1_RX_DMA_INT_SRC (INT_DMA1_TC0) +#define USART1_RX_DMA_INT_PRIO (DDL_IRQ_PRIORITY_01) +#endif + +#if defined(BSP_UART1_TX_USING_DMA) +#define USART1_TX_DMA_UNIT (M4_DMA2) +#define USART1_TX_DMA_CH (DMA_CH0) + +#define USART1_TC_INT_IRQn (Int006_IRQn) +#define USART1_TC_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) +#endif +#endif + +#endif + +/*********** Timer configure *********/ +#if defined(BSP_USING_TIMER5) +#define TIMER5_CNT_INT_IRQn (Int092_IRQn) +#define TIMER5_CNT_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) +#endif + +#if defined(BSP_USING_TIMER6) +#define TIMER6_CNT_INT_IRQn (Int093_IRQn) +#define TIMER6_CNT_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) +#endif + +/****** Pulse Encoder configure ******/ +#if defined(BSP_USING_PULSE_ENCODER9) +#define PULSE_ENCODER9_OVF_INT_IRQn (Int098_IRQn) +#define PULSE_ENCODER9_OVF_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define PULSE_ENCODER9_UNF_INT_IRQn (Int099_IRQn) +#define PULSE_ENCODER9_UNF_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) +#endif + +/*********** SPI configure *********/ +#if defined(BSP_SPI1_TX_USING_DMA) +#define SPI1_TX_DMA_INSTANCE (M4_DMA1) +#define SPI1_TX_DMA_CHANNEL (DMA_CH1) +#define SPI1_TX_DMA_IRQn (Int010_IRQn) +#define SPI1_TX_DMA_INT_SRC (INT_DMA1_TC1) +#define SPI1_TX_DMA_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) +#endif + +#if defined(BSP_SPI1_RX_USING_DMA) +#define SPI1_RX_DMA_INSTANCE (M4_DMA1) +#define SPI1_RX_DMA_CHANNEL (DMA_CH2) +#define SPI1_RX_DMA_IRQn (Int011_IRQn) +#define SPI1_RX_DMA_INT_SRC (INT_DMA1_TC2) +#define SPI1_RX_DMA_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) +#endif + +/*********** Pin configure *********/ +#if defined(RT_USING_PIN) + +#define EXINT0_INT_IRQn (Int016_IRQn) +#define EXINT0_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT1_INT_IRQn (Int017_IRQn) +#define EXINT1_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT2_INT_IRQn (Int018_IRQn) +#define EXINT2_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT3_INT_IRQn (Int019_IRQn) +#define EXINT3_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT4_INT_IRQn (Int020_IRQn) +#define EXINT4_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT5_INT_IRQn (Int021_IRQn) +#define EXINT5_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT6_INT_IRQn (Int022_IRQn) +#define EXINT6_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT7_INT_IRQn (Int023_IRQn) +#define EXINT7_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT8_INT_IRQn (Int024_IRQn) +#define EXINT8_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT9_INT_IRQn (Int025_IRQn) +#define EXINT9_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT10_INT_IRQn (Int026_IRQn) +#define EXINT10_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT11_INT_IRQn (Int027_IRQn) +#define EXINT11_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT12_INT_IRQn (Int028_IRQn) +#define EXINT12_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT13_INT_IRQn (Int029_IRQn) +#define EXINT13_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT14_INT_IRQn (Int030_IRQn) +#define EXINT14_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#define EXINT15_INT_IRQn (Int031_IRQn) +#define EXINT15_INT_PRIO (DDL_IRQ_PRIORITY_DEFAULT) + +#endif + +#endif diff --git a/bsp/hc32f4a0/board/linker_scripts/link.icf b/bsp/hc32f4a0/board/linker_scripts/link.icf new file mode 100644 index 0000000000000000000000000000000000000000..3a80cf803bfe898866f520431e200b3bc53c446b --- /dev/null +++ b/bsp/hc32f4a0/board/linker_scripts/link.icf @@ -0,0 +1,65 @@ +/*###ICF### Section handled by ICF editor, don't touch! ****/ +/*-Editor annotation file-*/ +/* IcfEditorFile="$TOOLKIT_DIR$\config\ide\IcfEditor\cortex_v1_4.xml" */ +/*-Specials-*/ +define symbol __ICFEDIT_intvec_start__ = 0x00000000; +/*-Memory Regions-*/ +define symbol __ICFEDIT_region_IROM1_start__ = 0x00000000; +define symbol __ICFEDIT_region_IROM1_end__ = 0x001FFFFF; +define symbol __ICFEDIT_region_IROM2_start__ = 0x03000000; +define symbol __ICFEDIT_region_IROM2_end__ = 0x030017FF; +define symbol __ICFEDIT_region_EROM1_start__ = 0x0; +define symbol __ICFEDIT_region_EROM1_end__ = 0x0; +define symbol __ICFEDIT_region_EROM2_start__ = 0x0; +define symbol __ICFEDIT_region_EROM2_end__ = 0x0; +define symbol __ICFEDIT_region_EROM3_start__ = 0x0; +define symbol __ICFEDIT_region_EROM3_end__ = 0x0; +define symbol __ICFEDIT_region_IRAM1_start__ = 0x1FFE0000; +define symbol __ICFEDIT_region_IRAM1_end__ = 0x1FFFFFFF; +define symbol __ICFEDIT_region_IRAM2_start__ = 0x20000000; +define symbol __ICFEDIT_region_IRAM2_end__ = 0x2001FFFF; +define symbol __ICFEDIT_region_IRAM3_start__ = 0x20020000; +define symbol __ICFEDIT_region_IRAM3_end__ = 0x2003FFFF; +define symbol __ICFEDIT_region_IRAM4_start__ = 0x20040000; +define symbol __ICFEDIT_region_IRAM4_end__ = 0x20057FFF; +define symbol __ICFEDIT_region_IRAM5_start__ = 0x20058000; +define symbol __ICFEDIT_region_IRAM5_end__ = 0x2005FFFF; +define symbol __ICFEDIT_region_IRAM6_start__ = 0x200F0000; +define symbol __ICFEDIT_region_IRAM6_end__ = 0x200F0FFF; +define symbol __ICFEDIT_region_ERAM1_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM1_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM2_end__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_start__ = 0x0; +define symbol __ICFEDIT_region_ERAM3_end__ = 0x0; + +define symbol __ICFEDIT_region_RAM_end__ = __ICFEDIT_region_IRAM6_end__; +export symbol __ICFEDIT_region_RAM_end__; + + +/*-Sizes-*/ +define symbol __ICFEDIT_size_cstack__ = 0x2100; +define symbol __ICFEDIT_size_proc_stack__ = 0x0; +define symbol __ICFEDIT_size_heap__ = 0x2000; +/**** End of ICF editor section. ###ICF###*/ + +define memory mem with size = 4G; +define region ROM_region = mem:[from __ICFEDIT_region_IROM1_start__ to __ICFEDIT_region_IROM1_end__] + | mem:[from __ICFEDIT_region_IROM2_start__ to __ICFEDIT_region_IROM2_end__]; +define region RAM_region = mem:[from __ICFEDIT_region_IRAM1_start__ to __ICFEDIT_region_IRAM1_end__] + | mem:[from __ICFEDIT_region_IRAM2_start__ to __ICFEDIT_region_IRAM2_end__] + | mem:[from __ICFEDIT_region_IRAM3_start__ to __ICFEDIT_region_IRAM3_end__] + | mem:[from __ICFEDIT_region_IRAM4_start__ to __ICFEDIT_region_IRAM4_end__] + | mem:[from __ICFEDIT_region_IRAM5_start__ to __ICFEDIT_region_IRAM5_end__] + | mem:[from __ICFEDIT_region_IRAM6_start__ to __ICFEDIT_region_IRAM6_end__]; + +define block CSTACK with alignment = 8, size = __ICFEDIT_size_cstack__ { }; +define block HEAP with alignment = 8, size = __ICFEDIT_size_heap__ { }; + +initialize by copy { readwrite }; +do not initialize { section .noinit }; + +place at address mem:__ICFEDIT_intvec_start__ { readonly section .intvec }; + +place in ROM_region { readonly }; +place in RAM_region { readwrite, last block CSTACK, block HEAP }; \ No newline at end of file diff --git a/bsp/hc32f4a0/board/linker_scripts/link.lds b/bsp/hc32f4a0/board/linker_scripts/link.lds new file mode 100644 index 0000000000000000000000000000000000000000..af109a6da6a06aee6a86790e572fc886b5069460 --- /dev/null +++ b/bsp/hc32f4a0/board/linker_scripts/link.lds @@ -0,0 +1,203 @@ + /** + ******************************************************************************* + * @file hc32f4a0_flash.lds + * @brief Linker script for HC32F4A0 Device with 2MByte FLASH, 512KByte RAM. + @verbatim + Change Logs: + Date Author Notes + 2020-09-15 Chengy First version + @endverbatim + ******************************************************************************* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. All rights reserved. + * + * This software component is licensed by HDSC under BSD 3-Clause license + * (the "License"); You may not use this file except in compliance with the + * License. You may obtain a copy of the License at: + * opensource.org/licenses/BSD-3-Clause + * + ******************************************************************************* + */ + +/* Use contiguous memory regions for simple. */ +MEMORY +{ + FLASH (rx): ORIGIN = 0x00000000, LENGTH = 2M + OTP (rx): ORIGIN = 0x03000000, LENGTH = 6876 + RAM (rwx): ORIGIN = 0x1FFE0000, LENGTH = 512K + RAMB (rwx): ORIGIN = 0x200F0000, LENGTH = 4K +} + +ENTRY(Reset_Handler) + +SECTIONS +{ + .vectors : + { + . = ALIGN(4); + KEEP(*(.vectors)) + . = ALIGN(4); + } >FLASH + + .icg_sec 0x00000400 : + { + KEEP(*(.icg_sec)) + } >FLASH + + .text : + { + . = ALIGN(4); + *(.text) + *(.text*) + *(.glue_7) + *(.glue_7t) + *(.eh_frame) + + KEEP(*(.init)) + KEEP(*(.fini)) + . = ALIGN(4); + } >FLASH + + .rodata : + { + . = ALIGN(4); + *(.rodata) + *(.rodata*) + . = ALIGN(4); + } >FLASH + + .ARM.extab : + { + *(.ARM.extab* .gnu.linkonce.armextab.*) + } >FLASH + + __exidx_start = .; + .ARM.exidx : + { + *(.ARM.exidx* .gnu.linkonce.armexidx.*) + } >FLASH + __exidx_end = .; + + .preinit_array : + { + . = ALIGN(4); + /* preinit data */ + PROVIDE_HIDDEN (__preinit_array_start = .); + KEEP(*(.preinit_array)) + PROVIDE_HIDDEN (__preinit_array_end = .); + . = ALIGN(4); + } >FLASH + + .init_array : + { + . = ALIGN(4); + /* init data */ + PROVIDE_HIDDEN (__init_array_start = .); + KEEP(*(SORT(.init_array.*))) + KEEP(*(.init_array)) + PROVIDE_HIDDEN (__init_array_end = .); + . = ALIGN(4); + } >FLASH + + .fini_array : + { + . = ALIGN(4); + /* finit data */ + PROVIDE_HIDDEN (__fini_array_start = .); + KEEP(*(SORT(.fini_array.*))) + KEEP(*(.fini_array)) + PROVIDE_HIDDEN (__fini_array_end = .); + . = ALIGN(4); + } >FLASH + + __etext = ALIGN(4); + + .otp_sec : + { + KEEP(*(.otp_sec)) + } >OTP + + .otp_lock_sec 0x03001800 : + { + KEEP(*(.otp_lock_sec)) + } >OTP + + .data : AT (__etext) + { + . = ALIGN(4); + __data_start__ = .; + *(vtable) + *(.data) + *(.data*) + . = ALIGN(4); + *(.ramfunc) + *(.ramfunc*) + . = ALIGN(4); + __data_end__ = .; + } >RAM + + __etext_ramb = __etext + ALIGN (SIZEOF(.data), 4); + .ramb_data : AT (__etext_ramb) + { + . = ALIGN(4); + __data_start_ramb__ = .; + *(.ramb_data) + *(.ramb_data*) + . = ALIGN(4); + __data_end_ramb__ = .; + } >RAMB + + .bss : + { + . = ALIGN(4); + _sbss = .; + __bss_start__ = _sbss; + *(.bss) + *(.bss*) + *(COMMON) + . = ALIGN(4); + _ebss = .; + __bss_end__ = _ebss; + } >RAM + + .ramb_bss : + { + . = ALIGN(4); + __bss_start_ramb__ = .; + *(.ramb_bss) + *(.ramb_bss*) + . = ALIGN(4); + __bss_end_ramb__ = .; + } >RAMB + + .heap_stack (COPY) : + { + . = ALIGN(8); + __end__ = .; + PROVIDE(end = .); + PROVIDE(_end = .); + *(.heap*) + . = ALIGN(8); + __HeapLimit = .; + + __StackLimit = .; + *(.stack*) + . = ALIGN(8); + __StackTop = .; + } >RAM + + /DISCARD/ : + { + libc.a (*) + libm.a (*) + libgcc.a (*) + } + + .ARM.attributes 0 : { *(.ARM.attributes) } + + PROVIDE(_stack = __StackTop); + PROVIDE(_Min_Heap_Size = __HeapLimit - __HeapBase); + PROVIDE(_Min_Stack_Size = __StackTop - __StackLimit); + + __RamEnd = ORIGIN(RAM) + LENGTH(RAM); + ASSERT(__StackTop <= __RamEnd, "region RAM overflowed with stack") +} diff --git a/bsp/hc32f4a0/board/linker_scripts/link.sct b/bsp/hc32f4a0/board/linker_scripts/link.sct new file mode 100644 index 0000000000000000000000000000000000000000..68e731802a6e5d951a2e97fd25ef7701bd97deb8 --- /dev/null +++ b/bsp/hc32f4a0/board/linker_scripts/link.sct @@ -0,0 +1,15 @@ +; ************************************************************* +; *** Scatter-Loading Description File generated by uVision *** +; ************************************************************* + +LR_IROM1 0x00000000 0x00200000 { ; load region size_region + ER_IROM1 0x00000000 0x00200000 { ; load address = execution address + *.o (RESET, +First) + *(InRoot$$Sections) + .ANY (+RO) + } + RW_IRAM1 0x1FFE0000 0x80000 { ; RW data + .ANY (+RW +ZI) + } +} + diff --git a/bsp/hc32f4a0/drivers/SConscript b/bsp/hc32f4a0/drivers/SConscript new file mode 100644 index 0000000000000000000000000000000000000000..f9e0d18b7fdfa10ac44338208e1f0db223761035 --- /dev/null +++ b/bsp/hc32f4a0/drivers/SConscript @@ -0,0 +1,40 @@ +from building import * + +cwd = GetCurrentDir() + +# add the general drivers. +src = Split(""" +drv_irq.c +""") + +if GetDepend(['RT_USING_PIN']): + src += ['drv_gpio.c'] + +if GetDepend(['RT_USING_SERIAL']): + src += ['drv_usart.c'] + +if GetDepend(['RT_USING_I2C', 'RT_USING_I2C_BITOPS']): + src += ['drv_soft_i2c.c'] + +if GetDepend(['RT_USING_SPI']): + src += ['drv_spi.c'] + +if GetDepend(['RT_USING_QSPI']): + src += ['drv_qspi.c'] + +if GetDepend('BSP_USING_RTC'): + src += ['drv_rtc.c'] + +if GetDepend('RT_USING_HWTIMER'): + src += ['drv_hwtimer.c'] + +if GetDepend('RT_USING_PWM'): + src += ['drv_pwm.c'] + +if GetDepend('RT_USING_PULSE_ENCODER'): + src += ['drv_pulse_encoder.c'] + +CPPPATH = [cwd] +group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) + +Return('group') diff --git a/bsp/hc32f4a0/drivers/drv_dma.h b/bsp/hc32f4a0/drivers/drv_dma.h new file mode 100644 index 0000000000000000000000000000000000000000..a54c69470ad868e8542abe34c7243f7ebe28c88e --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_dma.h @@ -0,0 +1,39 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_DMA_H__ +#define __DRV_DMA_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "hc32_ddl.h" +#include "drv_irq.h" + +#ifdef __cplusplus +extern "C" { +#endif + +struct dma_config { + M4_DMA_TypeDef *Instance; + rt_uint32_t channel; + + en_event_src_t trigger_evt_src; + + struct hc32_irq_config irq_config; +}; + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_DMA_H__ */ + diff --git a/bsp/hc32f4a0/drivers/drv_gpio.c b/bsp/hc32f4a0/drivers/drv_gpio.c new file mode 100644 index 0000000000000000000000000000000000000000..16846f4e2cad0e6d5f0db456293e0a17226055e0 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_gpio.c @@ -0,0 +1,481 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#include +#include "rthw.h" + +#ifdef RT_USING_PIN +#include "drv_gpio.h" +#include "drv_irq.h" + +#define GPIO_PIN_INDEX(pin) ((uint8_t)((pin) & 0x0F)) +#define GPIO_PORT(pin) ((uint8_t)(((pin) >> 4) & 0x0F)) +#define GPIO_PIN(pin) ((uint16_t)(0x01U << GPIO_PIN_INDEX(pin))) + +#define PIN_NUM(port, pin) (((((port) & 0x0F) << 4) | ((pin) & 0x0F))) +#define PIN_MAX_NUM ((GPIO_PORT_I * 16) + (__CLZ(__RBIT(GPIO_PIN_13))) + 1) + +#define ITEM_NUM(items) sizeof(items) / sizeof(items[0]) + +static void exint0_irq_handler(void); +static void exint1_irq_handler(void); +static void exint2_irq_handler(void); +static void exint3_irq_handler(void); +static void exint4_irq_handler(void); +static void exint5_irq_handler(void); +static void exint6_irq_handler(void); +static void exint7_irq_handler(void); +static void exint8_irq_handler(void); +static void exint9_irq_handler(void); +static void exint10_irq_handler(void); +static void exint11_irq_handler(void); +static void exint12_irq_handler(void); +static void exint13_irq_handler(void); +static void exint14_irq_handler(void); +static void exint15_irq_handler(void); + +struct hc32_pin_irq_map +{ + rt_uint16_t pinbit; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; +}; + +#ifndef HC32_PIN_CONFIG +#define HC32_PIN_CONFIG(pin, irq, src, irq_info) \ + { \ + .pinbit = pin, \ + .irq_callback = irq, \ + .irq_config = irq_info, \ + .irq_config.int_src = src, \ + } +#endif /* HC32_PIN_CONFIG */ + +static struct hc32_pin_irq_map pin_irq_map[] = +{ + HC32_PIN_CONFIG(GPIO_PIN_00, exint0_irq_handler, INT_PORT_EIRQ0, EXINT0_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_01, exint1_irq_handler, INT_PORT_EIRQ1, EXINT1_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_02, exint2_irq_handler, INT_PORT_EIRQ2, EXINT2_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_03, exint3_irq_handler, INT_PORT_EIRQ3, EXINT3_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_04, exint4_irq_handler, INT_PORT_EIRQ4, EXINT4_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_05, exint5_irq_handler, INT_PORT_EIRQ5, EXINT5_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_06, exint6_irq_handler, INT_PORT_EIRQ6, EXINT6_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_07, exint7_irq_handler, INT_PORT_EIRQ7, EXINT7_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_08, exint8_irq_handler, INT_PORT_EIRQ8, EXINT8_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_09, exint9_irq_handler, INT_PORT_EIRQ9, EXINT9_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_10, exint10_irq_handler, INT_PORT_EIRQ10, EXINT10_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_11, exint11_irq_handler, INT_PORT_EIRQ11, EXINT11_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_12, exint12_irq_handler, INT_PORT_EIRQ12, EXINT12_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_13, exint13_irq_handler, INT_PORT_EIRQ13, EXINT13_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_14, exint14_irq_handler, INT_PORT_EIRQ14, EXINT14_IRQ_CONFIG), + HC32_PIN_CONFIG(GPIO_PIN_15, exint15_irq_handler, INT_PORT_EIRQ15, EXINT15_IRQ_CONFIG), +}; + +struct rt_pin_irq_hdr pin_irq_hdr_tab[] = +{ + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, + {-1, 0, RT_NULL, RT_NULL}, +}; + +static void pin_irq_handler(rt_uint16_t pinbit) +{ + rt_int32_t irqindex = -1; + + if (Set == EXINT_GetExIntSrc(pinbit)) + { + EXINT_ClrExIntSrc(pinbit); + irqindex = __CLZ(__RBIT(pinbit)); + if (pin_irq_hdr_tab[irqindex].hdr) + { + pin_irq_hdr_tab[irqindex].hdr(pin_irq_hdr_tab[irqindex].args); + } + } +} + +static void exint0_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[0].pinbit); + rt_interrupt_leave(); +} + +static void exint1_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[1].pinbit); + rt_interrupt_leave(); +} + +static void exint2_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[2].pinbit); + rt_interrupt_leave(); +} + +static void exint3_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[3].pinbit); + rt_interrupt_leave(); +} + +static void exint4_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[4].pinbit); + rt_interrupt_leave(); +} + +static void exint5_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[5].pinbit); + rt_interrupt_leave(); +} + +static void exint6_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[6].pinbit); + rt_interrupt_leave(); +} + +static void exint7_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[7].pinbit); + rt_interrupt_leave(); +} + +static void exint8_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[8].pinbit); + rt_interrupt_leave(); +} + +static void exint9_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[9].pinbit); + rt_interrupt_leave(); +} + +static void exint10_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[10].pinbit); + rt_interrupt_leave(); +} + +static void exint11_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[11].pinbit); + rt_interrupt_leave(); +} + +static void exint12_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[12].pinbit); + rt_interrupt_leave(); +} + +static void exint13_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[13].pinbit); + rt_interrupt_leave(); +} + +static void exint14_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[14].pinbit); + rt_interrupt_leave(); +} + +static void exint15_irq_handler(void) +{ + rt_interrupt_enter(); + pin_irq_handler(pin_irq_map[15].pinbit); + rt_interrupt_leave(); +} + +static void hc32_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (PIN_LOW == value) + { + GPIO_ResetPins(gpio_port, gpio_pin); + } + else + { + GPIO_SetPins(gpio_port, gpio_pin); + } + } +} + +static int hc32_pin_read(rt_device_t dev, rt_base_t pin) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + int value = PIN_LOW; + + if (pin < PIN_MAX_NUM) + { + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + if (Pin_Reset == GPIO_ReadInputPins(gpio_port, gpio_pin)) + { + value = PIN_LOW; + } + else + { + value = PIN_HIGH; + } + } + + return value; +} + +static void hc32_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) +{ + uint8_t gpio_port; + uint16_t gpio_pin; + stc_gpio_init_t stcGpioInit; + + if (pin >= PIN_MAX_NUM) + { + return; + } + + GPIO_StructInit(&stcGpioInit); + switch (mode) + { + case PIN_MODE_OUTPUT: + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinOType = PIN_OTYPE_CMOS; + break; + case PIN_MODE_INPUT: + stcGpioInit.u16PinDir = PIN_DIR_IN; + break; + case PIN_MODE_INPUT_PULLUP: + stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PullUp = PIN_PU_ON; + break; + case PIN_MODE_INPUT_PULLDOWN: + stcGpioInit.u16PinDir = PIN_DIR_IN; + stcGpioInit.u16PullUp = PIN_PU_OFF; + break; + case PIN_MODE_OUTPUT_OD: + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PinOType = PIN_OTYPE_NMOS; + break; + default: + break; + } + + gpio_port = GPIO_PORT(pin); + gpio_pin = GPIO_PIN(pin); + GPIO_Init(gpio_port, gpio_pin, &stcGpioInit); +} + +static void gpio_irq_config(uint8_t u8Port, uint16_t u16Pin, uint16_t u16ExInt) +{ + __IO uint16_t *PCRx; + uint16_t pin_num; + + pin_num = __CLZ(__RBIT(u16Pin)); + PCRx = (__IO uint16_t *)((uint32_t)(&M4_GPIO->PCRA0) + ((uint32_t)u8Port * 0x40UL) + (pin_num * 4UL)); + MODIFY_REG16(*PCRx, GPIO_PCR_INTE, u16ExInt); +} + +static rt_err_t hc32_pin_attach_irq(struct rt_device *device, rt_int32_t pin, + rt_uint32_t mode, void (*hdr)(void *args), void *args) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == pin && + pin_irq_hdr_tab[irqindex].hdr == hdr && + pin_irq_hdr_tab[irqindex].mode == mode && + pin_irq_hdr_tab[irqindex].args == args) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + if (pin_irq_hdr_tab[irqindex].pin != -1) + { + rt_hw_interrupt_enable(level); + return RT_EBUSY; + } + pin_irq_hdr_tab[irqindex].pin = pin; + pin_irq_hdr_tab[irqindex].hdr = hdr; + pin_irq_hdr_tab[irqindex].mode = mode; + pin_irq_hdr_tab[irqindex].args = args; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_detach_irq(struct rt_device *device, rt_int32_t pin) +{ + rt_base_t level; + rt_int32_t irqindex = -1; + + if (pin >= PIN_MAX_NUM) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_EOK; + } + pin_irq_hdr_tab[irqindex].pin = -1; + pin_irq_hdr_tab[irqindex].hdr = RT_NULL; + pin_irq_hdr_tab[irqindex].mode = 0; + pin_irq_hdr_tab[irqindex].args = RT_NULL; + rt_hw_interrupt_enable(level); + + return RT_EOK; +} + +static rt_err_t hc32_pin_irq_enable(struct rt_device *device, rt_base_t pin, rt_uint32_t enabled) + +{ + struct hc32_pin_irq_map *irq_map; + rt_base_t level; + rt_int32_t irqindex = -1; + uint16_t gpio_pin; + stc_exint_init_t stcExintInit; + + if ((pin >= PIN_MAX_NUM) || ((PIN_IRQ_ENABLE != enabled) && (PIN_IRQ_DISABLE != enabled))) + { + return -RT_ENOSYS; + } + + irqindex = GPIO_PIN_INDEX(pin); + if (irqindex >= ITEM_NUM(pin_irq_map)) + { + return RT_ENOSYS; + } + + irq_map = &pin_irq_map[irqindex]; + gpio_pin = GPIO_PIN(pin); + if (enabled == PIN_IRQ_ENABLE) + { + level = rt_hw_interrupt_disable(); + if (pin_irq_hdr_tab[irqindex].pin == -1) + { + rt_hw_interrupt_enable(level); + return RT_ENOSYS; + } + + /* Exint config */ + EXINT_StructInit(&stcExintInit); + switch (pin_irq_hdr_tab[irqindex].mode) + { + case PIN_IRQ_MODE_RISING: + stcExintInit.u32ExIntLvl = EXINT_TRIGGER_RISING; + break; + case PIN_IRQ_MODE_FALLING: + stcExintInit.u32ExIntLvl = EXINT_TRIGGER_FALLING; + break; + case PIN_IRQ_MODE_RISING_FALLING: + stcExintInit.u32ExIntLvl = EXINT_TRIGGER_BOTH; + break; + case PIN_IRQ_MODE_LOW_LEVEL: + stcExintInit.u32ExIntLvl = EXINT_TRIGGER_LOW; + break; + } + stcExintInit.u32ExIntCh = gpio_pin; + stcExintInit.u32ExIntFAE = EXINT_FILTER_A_ON; + stcExintInit.u32ExIntFAClk = EXINT_FACLK_HCLK_DIV8; + EXINT_Init(&stcExintInit); + /* IRQ sign-in */ + hc32_install_irq_handler(&irq_map->irq_config, irq_map->irq_callback, RT_FALSE); + NVIC_EnableIRQ(irq_map->irq_config.irq); + gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_ON); + + rt_hw_interrupt_enable(level); + } + else + { + level = rt_hw_interrupt_disable(); + gpio_irq_config(GPIO_PORT(pin), gpio_pin, PIN_EXINT_OFF); + NVIC_DisableIRQ(irq_map->irq_config.irq); + + rt_hw_interrupt_enable(level); + } + + return RT_EOK; +} + +static const struct rt_pin_ops pin_ops = +{ + hc32_pin_mode, + hc32_pin_write, + hc32_pin_read, + hc32_pin_attach_irq, + hc32_pin_detach_irq, + hc32_pin_irq_enable, +}; + +int rt_hw_pin_init(void) +{ + return rt_device_pin_register("pin", &pin_ops, RT_NULL); +} +INIT_BOARD_EXPORT(rt_hw_pin_init); + +#endif /* RT_USING_PIN */ diff --git a/bsp/hc32f4a0/drivers/drv_gpio.h b/bsp/hc32f4a0/drivers/drv_gpio.h new file mode 100644 index 0000000000000000000000000000000000000000..359e8f77659a24052d15e8a5124aff4823af398d --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_gpio.h @@ -0,0 +1,152 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_GPIO_H__ +#define __DRV_GPIO_H__ + +#include +#include "board_config.h" + +#ifdef RT_USING_PIN + +#define __HC_PORT(port) GPIO_PORT_##port +#define GET_PIN(PORT, PIN) (((rt_uint16_t)__HC_PORT(PORT) * 16) + PIN) + +#ifndef EXINT0_IRQ_CONFIG +#define EXINT0_IRQ_CONFIG \ + { \ + .irq = EXINT0_INT_IRQn, \ + .irq_prio = EXINT0_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT1_IRQ_CONFIG +#define EXINT1_IRQ_CONFIG \ + { \ + .irq = EXINT1_INT_IRQn, \ + .irq_prio = EXINT1_INT_PRIO, \ + } +#endif /* EXINT1_IRQ_CONFIG */ + +#ifndef EXINT2_IRQ_CONFIG +#define EXINT2_IRQ_CONFIG \ + { \ + .irq = EXINT2_INT_IRQn, \ + .irq_prio = EXINT2_INT_PRIO, \ + } +#endif /* EXINT2_IRQ_CONFIG */ + +#ifndef EXINT3_IRQ_CONFIG +#define EXINT3_IRQ_CONFIG \ + { \ + .irq = EXINT3_INT_IRQn, \ + .irq_prio = EXINT3_INT_PRIO, \ + } +#endif /* EXINT3_IRQ_CONFIG */ + +#ifndef EXINT4_IRQ_CONFIG +#define EXINT4_IRQ_CONFIG \ + { \ + .irq = EXINT4_INT_IRQn, \ + .irq_prio = EXINT4_INT_PRIO, \ + } +#endif /* EXINT4_IRQ_CONFIG */ + +#ifndef EXINT5_IRQ_CONFIG +#define EXINT5_IRQ_CONFIG \ + { \ + .irq = EXINT5_INT_IRQn, \ + .irq_prio = EXINT5_INT_PRIO, \ + } +#endif /* EXINT5_IRQ_CONFIG */ + +#ifndef EXINT6_IRQ_CONFIG +#define EXINT6_IRQ_CONFIG \ + { \ + .irq = EXINT6_INT_IRQn, \ + .irq_prio = EXINT6_INT_PRIO, \ + } +#endif /* EXINT6_IRQ_CONFIG */ + +#ifndef EXINT7_IRQ_CONFIG +#define EXINT7_IRQ_CONFIG \ + { \ + .irq = EXINT7_INT_IRQn, \ + .irq_prio = EXINT7_INT_PRIO, \ + } +#endif /* EXINT7_IRQ_CONFIG */ + +#ifndef EXINT8_IRQ_CONFIG +#define EXINT8_IRQ_CONFIG \ + { \ + .irq = EXINT8_INT_IRQn, \ + .irq_prio = EXINT8_INT_PRIO, \ + } +#endif /* EXINT8_IRQ_CONFIG */ + +#ifndef EXINT9_IRQ_CONFIG +#define EXINT9_IRQ_CONFIG \ + { \ + .irq = EXINT9_INT_IRQn, \ + .irq_prio = EXINT9_INT_PRIO, \ + } +#endif /* EXINT9_IRQ_CONFIG */ + +#ifndef EXINT10_IRQ_CONFIG +#define EXINT10_IRQ_CONFIG \ + { \ + .irq = EXINT10_INT_IRQn, \ + .irq_prio = EXINT10_INT_PRIO, \ + } +#endif /* EXINT10_IRQ_CONFIG */ + +#ifndef EXINT11_IRQ_CONFIG +#define EXINT11_IRQ_CONFIG \ + { \ + .irq = EXINT11_INT_IRQn, \ + .irq_prio = EXINT11_INT_PRIO, \ + } +#endif /* EXINT11_IRQ_CONFIG */ + +#ifndef EXINT12_IRQ_CONFIG +#define EXINT12_IRQ_CONFIG \ + { \ + .irq = EXINT12_INT_IRQn, \ + .irq_prio = EXINT12_INT_PRIO, \ + } +#endif /* EXINT12_IRQ_CONFIG */ + +#ifndef EXINT13_IRQ_CONFIG +#define EXINT13_IRQ_CONFIG \ + { \ + .irq = EXINT13_INT_IRQn, \ + .irq_prio = EXINT13_INT_PRIO, \ + } +#endif /* EXINT13_IRQ_CONFIG */ + +#ifndef EXINT14_IRQ_CONFIG +#define EXINT14_IRQ_CONFIG \ + { \ + .irq = EXINT14_INT_IRQn, \ + .irq_prio = EXINT14_INT_PRIO, \ + } +#endif /* EXINT14_IRQ_CONFIG */ + +#ifndef EXINT15_IRQ_CONFIG +#define EXINT15_IRQ_CONFIG \ + { \ + .irq = EXINT15_INT_IRQn, \ + .irq_prio = EXINT15_INT_PRIO, \ + } +#endif /* EXINT15_IRQ_CONFIG */ + +#endif + +#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/hc32f4a0/drivers/drv_hwtimer.c b/bsp/hc32f4a0/drivers/drv_hwtimer.c new file mode 100644 index 0000000000000000000000000000000000000000..cc6a1ba945a2aba3ec4c96ac5928fb94ed30f11a --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_hwtimer.c @@ -0,0 +1,551 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#include +#include + +#ifdef RT_USING_HWTIMER + +#if !defined(BSP_USING_TIMER1) && !defined(BSP_USING_TIMER2) && !defined(BSP_USING_TIMER3) && \ + !defined(BSP_USING_TIMER4) && !defined(BSP_USING_TIMER5) && !defined(BSP_USING_TIMER6) && \ + !defined(BSP_USING_TIMER7) && !defined(BSP_USING_TIMER8) && !defined(BSP_USING_TIMER9) && \ + !defined(BSP_USING_TIMER10) && !defined(BSP_USING_TIMER11) && !defined(BSP_USING_TIMER12) +#error "Please define at least one BSP_USING_TIMERx" +/* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable TIMER */ +#endif + +#include "drv_hwtimer.h" +#include "drv_irq.h" + +enum +{ +#ifdef BSP_USING_TIMER1 + TIMER1_INDEX, +#endif +#ifdef BSP_USING_TIMER2 + TIMER2_INDEX, +#endif +#ifdef BSP_USING_TIMER3 + TIMER3_INDEX, +#endif +#ifdef BSP_USING_TIMER4 + TIMER4_INDEX, +#endif +#ifdef BSP_USING_TIMER5 + TIMER5_INDEX, +#endif +#ifdef BSP_USING_TIMER6 + TIMER6_INDEX, +#endif +#ifdef BSP_USING_TIMER7 + TIMER7_INDEX, +#endif +#ifdef BSP_USING_TIMER8 + TIMER8_INDEX, +#endif +#ifdef BSP_USING_TIMER9 + TIMER9_INDEX, +#endif +#ifdef BSP_USING_TIMER10 + TIMER10_INDEX, +#endif +#ifdef BSP_USING_TIMER11 + TIMER11_INDEX, +#endif +#ifdef BSP_USING_TIMER12 + TIMER12_INDEX, +#endif +}; + +#ifdef BSP_USING_TIMER1 +static void timer1_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER2 +static void timer2_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER3 +static void timer3_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER4 +static void timer4_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER5 +static void timer5_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER6 +static void timer6_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER7 +static void timer7_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER8 +static void timer8_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER9 +static void timer9_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER10 +static void timer10_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER11 +static void timer11_irq_handler(void); +#endif +#ifdef BSP_USING_TIMER12 +static void timer12_irq_handler(void); +#endif + +struct hc32_hwtimer_config +{ + rt_hwtimer_t time_device; + M4_TMRA_TypeDef *timer_periph; + struct hc32_irq_config irq_config; + func_ptr_t irq_callback; + uint32_t extend_div; + uint32_t extend_cnt; + char *name; +}; + +#ifndef HC32_TIMER_CONFIG +#define HC32_TIMER_CONFIG(periph, irq, label, src, irq_info) \ + { \ + .timer_periph = periph, \ + .irq_callback = irq, \ + .name = label, \ + .irq_config = irq_info, \ + .irq_config.int_src = src, \ + } +#endif /* HC32_TIMER_CONFIG */ + +static struct hc32_hwtimer_config hwtimer_obj[] = +{ +#ifdef BSP_USING_TIMER1 + HC32_TIMER_CONFIG(M4_TMRA_1, timer1_irq_handler, "timer1", INT_TMRA_1_OVF, TIMER1_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER2 + HC32_TIMER_CONFIG(M4_TMRA_2, timer2_irq_handler, "timer2", INT_TMRA_2_OVF, TIMER2_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER3 + HC32_TIMER_CONFIG(M4_TMRA_3, timer3_irq_handler, "timer3", INT_TMRA_3_OVF, TIMER3_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER4 + HC32_TIMER_CONFIG(M4_TMRA_4, timer4_irq_handler, "timer4", INT_TMRA_4_OVF, TIMER4_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER5 + HC32_TIMER_CONFIG(M4_TMRA_5, timer5_irq_handler, "timer5", INT_TMRA_5_OVF, TIMER5_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER6 + HC32_TIMER_CONFIG(M4_TMRA_6, timer6_irq_handler, "timer6", INT_TMRA_6_OVF, TIMER6_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER7 + HC32_TIMER_CONFIG(M4_TMRA_7, timer7_irq_handler, "timer7", INT_TMRA_7_OVF, TIMER7_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER8 + HC32_TIMER_CONFIG(M4_TMRA_8, timer8_irq_handler, "timer8", INT_TMRA_8_OVF, TIMER8_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER9 + HC32_TIMER_CONFIG(M4_TMRA_9, timer9_irq_handler, "timer9", INT_TMRA_9_OVF, TIMER9_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER10 + HC32_TIMER_CONFIG(M4_TMRA_10, timer10_irq_handler, "timer10", INT_TMRA_10_OVF, TIMER10_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER11 + HC32_TIMER_CONFIG(M4_TMRA_11, timer11_irq_handler, "timer11", INT_TMRA_11_OVF, TIMER11_IRQ_CONFIG), +#endif +#ifdef BSP_USING_TIMER12 + HC32_TIMER_CONFIG(M4_TMRA_12, timer12_irq_handler, "timer12", INT_TMRA_12_OVF, TIMER12_IRQ_CONFIG), +#endif +}; + +static void hc32_timer_irq_handler(struct hc32_hwtimer_config *timer_config) +{ + if ((++timer_config->extend_cnt) >= timer_config->extend_div) + { + timer_config->extend_cnt = 0; + rt_device_hwtimer_isr(&timer_config->time_device); + } + TMRA_ClrStatus(timer_config->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UNF)); +} + +#ifdef BSP_USING_TIMER1 +static void timer1_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER1_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER2 +static void timer2_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER2_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER3 +static void timer3_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER3_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER4 +static void timer4_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER4_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER5 +static void timer5_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER5_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER6 +static void timer6_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER6_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER7 +static void timer7_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER7_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER8 +static void timer8_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER8_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER9 +static void timer9_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER9_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER10 +static void timer10_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER10_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER11 +static void timer11_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER11_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_TIMER12 +static void timer12_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_timer_irq_handler(&hwtimer_obj[TIMER12_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static rt_uint16_t hc32_timer_get_unit_number(M4_TMRA_TypeDef *TMRAx) +{ + rt_uint16_t unit_num; + const rt_uint32_t unit_step = 0x400U; + + if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)M4_TMRA_1)) + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_1)) / unit_step; + } + else + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_5)) / unit_step + 4; + } + + return unit_num; +} + +static void hc32_timer_clock_config(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + rt_uint32_t timer_periph; + rt_uint16_t unit_num; + + unit_num = hc32_timer_get_unit_number(TMRAx); + timer_periph = PWC_FCG2_TMRA_1 << unit_num; + PWC_Fcg2PeriphClockCmd(timer_periph, enNewState); +} + +static void hc32_timer_get_div_value(M4_TMRA_TypeDef *TMRAx, uint32_t freq, uint16_t *div, uint32_t *extend_div) +{ + stc_clk_freq_t stcClkFreq; + rt_uint32_t divisor, remainder; + rt_uint16_t div_val; + rt_uint32_t clk_freq; + rt_uint16_t unit_num; + + CLK_GetClockFreq(&stcClkFreq); + unit_num = hc32_timer_get_unit_number(TMRAx); + if (unit_num >= 4) + { + clk_freq = stcClkFreq.pclk1Freq; + } + else + { + clk_freq = stcClkFreq.pclk0Freq; + } + divisor = clk_freq / freq; + remainder = clk_freq % freq; + for (div_val=1; div_val<=1024; div_val<<=1) + { + if (((divisor % 2) == 0) && (remainder == 0)) + { + remainder = divisor % 2; + divisor = divisor / 2; + } + else + { + break; + } + } + *extend_div = divisor; + *div = (__CLZ(__RBIT(div_val))) << TMRA_BCSTR_CKDIV_POS; +} + +static void hc32_timer_interrupt_config(struct rt_hwtimer_device *timer, en_functional_state_t enNewState) +{ + struct hc32_hwtimer_config *timer_config = RT_NULL; + + timer_config = (struct hc32_hwtimer_config *)timer; + if (INT_MAX == timer_config->irq_config.int_src) + { + LOG_D("%s interrupt init failed", timer_config->name); + return; + } + + if (Enable == enNewState) + { + /* Enable the specified interrupts of Timer */ + hc32_install_irq_handler(&timer_config->irq_config, timer_config->irq_callback, RT_FALSE); + NVIC_EnableIRQ(timer_config->irq_config.irq); + TMRA_IntCmd(timer_config->timer_periph, TMRA_INT_OVF, Enable); + } + else + { + /* Disable the specified interrupts of Timer */ + TMRA_IntCmd(timer_config->timer_periph, TMRA_INT_OVF, Disable); + NVIC_DisableIRQ(timer_config->irq_config.irq); + } +} + +static void hc32_timer_init(struct rt_hwtimer_device *timer, rt_uint32_t state) +{ + stc_tmra_init_t stcTmraInit; + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + if (state) + { + /* Enable Timer peripheral clock. */ + hc32_timer_clock_config(timer_config->timer_periph, Enable); + TMRA_DeInit(timer_config->timer_periph); + TMRA_StructInit(&stcTmraInit); + stcTmraInit.u32CntDir = TMRA_DIR_UP; + TMRA_Init(timer_config->timer_periph, &stcTmraInit); + LOG_D("%s init success", timer_config->name); + } + else + { + TMRA_DeInit(timer_config->timer_periph); + hc32_timer_interrupt_config(timer, Disable); + /* Disable Timer peripheral clock. */ + hc32_timer_clock_config(timer_config->timer_periph, Disable); + } +} + +static rt_err_t hc32_timer_start(struct rt_hwtimer_device *timer, rt_uint32_t cnt, rt_hwtimer_mode_t mode) +{ + rt_err_t result = RT_EOK; + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + if (mode == HWTIMER_MODE_ONESHOT) + { + TMRA_SetOvfOperation(timer_config->timer_periph, TMRA_OVF_CNT_STOP); + } + else + { + TMRA_SetOvfOperation(timer_config->timer_periph, TMRA_OVF_CNT_CONTINUE); + } + timer_config->extend_cnt = 0; + TMRA_SetCntVal(timer_config->timer_periph, 0); + TMRA_SetPeriodVal(timer_config->timer_periph, cnt - 1); + hc32_timer_interrupt_config(timer, Enable); + TMRA_Start(timer_config->timer_periph); + + return result; +} + +static void hc32_timer_stop(struct rt_hwtimer_device *timer) +{ + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + /* stop timer */ + TMRA_Stop(timer_config->timer_periph); + hc32_timer_interrupt_config(timer, Disable); + TMRA_SetCntVal(timer_config->timer_periph, 0); +} + +static rt_uint32_t hc32_timer_get_counter(struct rt_hwtimer_device *timer) +{ + rt_uint32_t count_val; + rt_uint32_t period_val; + float temp; + struct hc32_hwtimer_config *timer_config = RT_NULL; + + RT_ASSERT(timer != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + period_val = TMRA_GetPeriodVal(timer_config->timer_periph); + count_val = TMRA_GetCntVal(timer_config->timer_periph); + temp = (timer_config->extend_cnt * period_val + count_val); + temp = temp / (timer_config->extend_div * period_val) * period_val; + count_val = (rt_uint32_t)temp; + + return count_val; +} + +static rt_err_t hc32_timer_ctrl(struct rt_hwtimer_device *timer, rt_uint32_t cmd, void *args) +{ + struct hc32_hwtimer_config *timer_config = RT_NULL; + rt_err_t result = RT_EOK; + + RT_ASSERT(timer != RT_NULL); + RT_ASSERT(args != RT_NULL); + timer_config = (struct hc32_hwtimer_config *)timer; + switch (cmd) + { + case HWTIMER_CTRL_FREQ_SET: + { + rt_uint32_t freq; + rt_uint16_t div_val; + rt_uint32_t extend_div_val; + + /* set timer frequency */ + freq = *((rt_uint32_t *)args); + hc32_timer_get_div_value(timer_config->timer_periph, freq, &div_val, &extend_div_val); + TMRA_SetPCLKDiv(timer_config->timer_periph, div_val); + timer_config->extend_div = extend_div_val; + } + break; + default: + { + result = -RT_ENOSYS; + } + break; + } + + return result; +} + +static const struct rt_hwtimer_ops hwtimer_ops = +{ + .init = hc32_timer_init, + .start = hc32_timer_start, + .stop = hc32_timer_stop, + .count_get = hc32_timer_get_counter, + .control = hc32_timer_ctrl, +}; + +static const struct rt_hwtimer_info hwtimer_info = +{ + .maxfreq = 30000000, + .minfreq = 1000, + .maxcnt = 0xFFFF, + .cntmode = HWTIMER_CNTMODE_UP, +}; + +static int rt_hwtimer_init(void) +{ + int i = 0; + int result = RT_EOK; + + for (i = 0; i < sizeof(hwtimer_obj) / sizeof(hwtimer_obj[0]); i++) + { + hwtimer_obj[i].time_device.info = &hwtimer_info; + hwtimer_obj[i].time_device.ops = &hwtimer_ops; + if (rt_device_hwtimer_register(&hwtimer_obj[i].time_device, hwtimer_obj[i].name, hwtimer_obj[i].timer_periph) == RT_EOK) + { + LOG_D("%s register success", hwtimer_obj[i].name); + } + else + { + LOG_E("%s register failed", hwtimer_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(rt_hwtimer_init); + +#endif /* RT_USING_HWTIMER */ diff --git a/bsp/hc32f4a0/drivers/drv_hwtimer.h b/bsp/hc32f4a0/drivers/drv_hwtimer.h new file mode 100644 index 0000000000000000000000000000000000000000..730c3ad447c857e56793a82d1daf771360ba3644 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_hwtimer.h @@ -0,0 +1,145 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_HWTIMER_H__ +#define __DRV_HWTIMER_H__ + +#include +#include "board_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_TIMER1 +#ifndef TIMER1_IRQ_CONFIG +#define TIMER1_IRQ_CONFIG \ + { \ + .irq = TIMER1_CNT_INT_IRQn, \ + .irq_prio = TIMER1_CNT_INT_PRIO, \ + } +#endif /* TIMER1_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER1 */ + +#ifdef BSP_USING_TIMER2 +#ifndef TIMER2_IRQ_CONFIG +#define TIMER2_IRQ_CONFIG \ + { \ + .irq = TIMER2_CNT_INT_IRQn, \ + .irq_prio = TIMER2_CNT_INT_PRIO, \ + } +#endif /* TIMER2_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER2 */ + +#ifdef BSP_USING_TIMER3 +#ifndef TIMER3_IRQ_CONFIG +#define TIMER3_IRQ_CONFIG \ + { \ + .irq = TIMER3_CNT_INT_IRQn, \ + .irq_prio = TIMER3_CNT_INT_PRIO, \ + } +#endif /* TIMER3_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER3 */ + +#ifdef BSP_USING_TIMER4 +#ifndef TIMER4_IRQ_CONFIG +#define TIMER4_IRQ_CONFIG \ + { \ + .irq = TIMER4_CNT_INT_IRQn, \ + .irq_prio = TIMER4_CNT_INT_PRIO, \ + } +#endif /* TIMER4_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER4 */ + +#ifdef BSP_USING_TIMER5 +#ifndef TIMER5_IRQ_CONFIG +#define TIMER5_IRQ_CONFIG \ + { \ + .irq = TIMER5_CNT_INT_IRQn, \ + .irq_prio = TIMER5_CNT_INT_PRIO, \ + } +#endif /* TIMER5_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER5 */ + +#ifdef BSP_USING_TIMER6 +#ifndef TIMER6_IRQ_CONFIG +#define TIMER6_IRQ_CONFIG \ + { \ + .irq = TIMER6_CNT_INT_IRQn, \ + .irq_prio = TIMER6_CNT_INT_PRIO, \ + } +#endif /* TIMER6_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER6 */ + +#ifdef BSP_USING_TIMER7 +#ifndef TIMER7_IRQ_CONFIG +#define TIMER7_IRQ_CONFIG \ + { \ + .irq = TIMER7_CNT_INT_IRQn, \ + .irq_prio = TIMER7_CNT_INT_PRIO, \ + } +#endif /* TIMER7_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER7 */ + +#ifdef BSP_USING_TIMER8 +#ifndef TIMER8_IRQ_CONFIG +#define TIMER8_IRQ_CONFIG \ + { \ + .irq = TIMER8_CNT_INT_IRQn, \ + .irq_prio = TIMER8_CNT_INT_PRIO, \ + } +#endif /* TIMER8_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER8 */ + +#ifdef BSP_USING_TIMER9 +#ifndef TIMER9_IRQ_CONFIG +#define TIMER9_IRQ_CONFIG \ + { \ + .irq = TIMER9_CNT_INT_IRQn, \ + .irq_prio = TIMER9_CNT_INT_PRIO, \ + } +#endif /* TIMER9_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER9 */ + +#ifdef BSP_USING_TIMER10 +#ifndef TIMER10_IRQ_CONFIG +#define TIMER10_IRQ_CONFIG \ + { \ + .irq = TIMER10_CNT_INT_IRQn, \ + .irq_prio = TIMER10_CNT_INT_PRIO, \ + } +#endif /* TIMER10_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER10 */ + +#ifdef BSP_USING_TIMER11 +#ifndef TIMER11_IRQ_CONFIG +#define TIMER11_IRQ_CONFIG \ + { \ + .irq = TIMER11_CNT_INT_IRQn, \ + .irq_prio = TIMER11_CNT_INT_PRIO, \ + } +#endif /* TIMER11_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER11 */ + +#ifdef BSP_USING_TIMER12 +#ifndef TIMER12_IRQ_CONFIG +#define TIMER12_IRQ_CONFIG \ + { \ + .irq = TIMER12_CNT_INT_IRQn, \ + .irq_prio = TIMER12_CNT_INT_PRIO, \ + } +#endif /* TIMER12_IRQ_CONFIG */ +#endif /* BSP_USING_TIMER12 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_HWTIMER_H__ */ diff --git a/bsp/hc32f4a0/drivers/drv_irq.c b/bsp/hc32f4a0/drivers/drv_irq.c new file mode 100644 index 0000000000000000000000000000000000000000..661cbe6fcb3d039d675c7bd14ffe5bd5da4c96b4 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_irq.c @@ -0,0 +1,79 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include + +#include "drv_irq.h" + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable) +{ + rt_err_t result = -RT_ERROR; + stc_irq_signin_config_t irq_signin; + + RT_ASSERT(RT_NULL != irq_config); + RT_ASSERT(RT_NULL != irq_hdr); + + irq_signin.enIRQn = irq_config->irq; + irq_signin.enIntSrc = irq_config->int_src; + irq_signin.pfnCallback= irq_hdr; + if (Ok == INTC_IrqSignIn(&irq_signin)) + { + NVIC_ClearPendingIRQ(irq_signin.enIRQn); + NVIC_SetPriority(irq_signin.enIRQn, irq_config->irq_prio); + + if (RT_TRUE == irq_enable) + { + NVIC_EnableIRQ(irq_signin.enIRQn); + } + else + { + NVIC_DisableIRQ(irq_signin.enIRQn); + } + + result = RT_EOK; + } + + RT_ASSERT(RT_EOK == result); + + return result; +} + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/drivers/drv_irq.h b/bsp/hc32f4a0/drivers/drv_irq.h new file mode 100644 index 0000000000000000000000000000000000000000..8beb17868f21550385599a72dfb50a99296b3992 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_irq.h @@ -0,0 +1,59 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_IRQ_H__ +#define __DRV_IRQ_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "hc32_ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_irq_config +{ + IRQn_Type irq; + uint32_t irq_prio; + en_int_src_t int_src; +}; + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +rt_err_t hc32_install_irq_handler(struct hc32_irq_config *irq_config, + void (*irq_hdr)(void), + rt_bool_t irq_enable); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_IRQ_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/drivers/drv_pulse_encoder.c b/bsp/hc32f4a0/drivers/drv_pulse_encoder.c new file mode 100644 index 0000000000000000000000000000000000000000..ee68f5e80894005e903d327fdd11a4543608589e --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_pulse_encoder.c @@ -0,0 +1,471 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#include +#include + +#ifdef RT_USING_PULSE_ENCODER + +#if !defined(BSP_USING_PULSE_ENCODER1) && !defined(BSP_USING_PULSE_ENCODER2) && !defined(BSP_USING_PULSE_ENCODER3) && \ + !defined(BSP_USING_PULSE_ENCODER4) && !defined(BSP_USING_PULSE_ENCODER5) && !defined(BSP_USING_PULSE_ENCODER6) && \ + !defined(BSP_USING_PULSE_ENCODER7) && !defined(BSP_USING_PULSE_ENCODER8) && !defined(BSP_USING_PULSE_ENCODER9) && \ + !defined(BSP_USING_PULSE_ENCODER10) && !defined(BSP_USING_PULSE_ENCODER11) && !defined(BSP_USING_PULSE_ENCODER12) +#error "Please define at least one BSP_USING_PULSE_ENCODERx" +/* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable Pulse Encoder */ +#endif + +#include "drv_pulse_encoder.h" +#include "drv_irq.h" + +#define TIMER_AUTO_RELOAD_VALUE (0xFFFFU) + +enum +{ +#ifdef BSP_USING_PULSE_ENCODER1 + PULSE_ENCODER1_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER2 + PULSE_ENCODER2_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER3 + PULSE_ENCODER3_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER4 + PULSE_ENCODER4_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER5 + PULSE_ENCODER5_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER6 + PULSE_ENCODER6_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER7 + PULSE_ENCODER7_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER8 + PULSE_ENCODER8_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER9 + PULSE_ENCODER9_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER10 + PULSE_ENCODER10_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER11 + PULSE_ENCODER11_INDEX, +#endif +#ifdef BSP_USING_PULSE_ENCODER12 + PULSE_ENCODER12_INDEX, +#endif +}; + +#ifdef BSP_USING_PULSE_ENCODER1 +static void pulse_encoder1_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER2 +static void pulse_encoder2_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER3 +static void pulse_encoder3_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER4 +static void pulse_encoder4_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER5 +static void pulse_encoder5_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER6 +static void pulse_encoder6_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER7 +static void pulse_encoder7_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER8 +static void pulse_encoder8_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER9 +static void pulse_encoder9_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER10 +static void pulse_encoder10_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER11 +static void pulse_encoder11_irq_handler(void); +#endif +#ifdef BSP_USING_PULSE_ENCODER12 +static void pulse_encoder12_irq_handler(void); +#endif + +struct hc32_pulse_encoder_config +{ + struct rt_pulse_encoder_device pulse_encoder; + M4_TMRA_TypeDef *timer_periph; + struct hc32_irq_config ovf_irq_config; + struct hc32_irq_config udf_irq_config; + func_ptr_t irq_callback; + rt_int32_t ovf_udf_count; + char *name; +}; + +#ifndef HC32_PULSE_ENCODER_CONFIG +#define HC32_PULSE_ENCODER_CONFIG(periph, irq, label, ovf_src, udf_src, \ + ovf_irq_info, udf_irq_info) \ + { \ + .timer_periph = periph, \ + .irq_callback = irq, \ + .name = label, \ + .ovf_irq_config = ovf_irq_info, \ + .udf_irq_config = udf_irq_info, \ + .ovf_irq_config.int_src = ovf_src, \ + .udf_irq_config.int_src = udf_src, \ + } +#endif /* HC32_PULSE_ENCODER_CONFIG */ + +static struct hc32_pulse_encoder_config pulse_encoder_obj[] = +{ +#ifdef BSP_USING_PULSE_ENCODER1 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_1, pulse_encoder1_irq_handler, "pulse1", INT_TMRA_1_OVF, INT_TMRA_1_UDF, + PULSE_ENCODER1_OVF_IRQ_CONFIG, PULSE_ENCODER1_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER2 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_2, pulse_encoder2_irq_handler, "pulse2", INT_TMRA_2_OVF, INT_TMRA_2_UDF, + PULSE_ENCODER2_OVF_IRQ_CONFIG, PULSE_ENCODER2_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER3 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_3, pulse_encoder3_irq_handler, "pulse3", INT_TMRA_3_OVF, INT_TMRA_3_UDF, + PULSE_ENCODER3_OVF_IRQ_CONFIG, PULSE_ENCODER3_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER4 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_4, pulse_encoder4_irq_handler, "pulse4", INT_TMRA_4_OVF, INT_TMRA_4_UDF, + PULSE_ENCODER4_OVF_IRQ_CONFIG, PULSE_ENCODER4_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER5 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_5, pulse_encoder5_irq_handler, "pulse5", INT_TMRA_5_OVF, INT_TMRA_5_UDF, + PULSE_ENCODER5_OVF_IRQ_CONFIG, PULSE_ENCODER5_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER6 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_6, pulse_encoder6_irq_handler, "pulse6", INT_TMRA_6_OVF, INT_TMRA_6_UDF, + PULSE_ENCODER6_OVF_IRQ_CONFIG, PULSE_ENCODER6_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER7 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_7, pulse_encoder7_irq_handler, "pulse7", INT_TMRA_7_OVF, INT_TMRA_7_UDF, + PULSE_ENCODER7_OVF_IRQ_CONFIG, PULSE_ENCODER7_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER8 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_8, pulse_encoder8_irq_handler, "pulse8", INT_TMRA_8_OVF, INT_TMRA_8_UDF, + PULSE_ENCODER8_OVF_IRQ_CONFIG, PULSE_ENCODER8_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER9 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_9, pulse_encoder9_irq_handler, "pulse9", INT_TMRA_9_OVF, INT_TMRA_9_UDF, + PULSE_ENCODER9_OVF_IRQ_CONFIG, PULSE_ENCODER9_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER10 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_10, pulse_encoder10_irq_handler, "pulse10", INT_TMRA_10_OVF, INT_TMRA_10_UDF, + PULSE_ENCODER10_OVF_IRQ_CONFIG, PULSE_ENCODER10_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER11 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_11, pulse_encoder11_irq_handler, "pulse11", INT_TMRA_11_OVF, INT_TMRA_11_UDF, + PULSE_ENCODER11_OVF_IRQ_CONFIG, PULSE_ENCODER11_UDF_IRQ_CONFIG), +#endif +#ifdef BSP_USING_PULSE_ENCODER12 + HC32_PULSE_ENCODER_CONFIG(M4_TMRA_12, pulse_encoder12_irq_handler, "pulse12", INT_TMRA_12_OVF, INT_TMRA_12_UDF, + PULSE_ENCODER12_OVF_IRQ_CONFIG, PULSE_ENCODER12_UDF_IRQ_CONFIG), +#endif +}; + +static void hc32_pulse_encoder_irq_handler(struct hc32_pulse_encoder_config *pulse_encoder_config) +{ + if (Set == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF)) + { + pulse_encoder_config->ovf_udf_count++; + TMRA_ClrStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_OVF); + } + if (Set == TMRA_GetStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UNF)) + { + pulse_encoder_config->ovf_udf_count--; + TMRA_ClrStatus(pulse_encoder_config->timer_periph, TMRA_FLAG_UNF); + } +} + +#ifdef BSP_USING_PULSE_ENCODER1 +static void pulse_encoder1_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER1_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER2 +static void pulse_encoder2_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER2_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER3 +static void pulse_encoder3_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER3_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER4 +static void pulse_encoder4_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER4_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER5 +static void pulse_encoder5_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER5_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER6 +static void pulse_encoder6_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER6_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER7 +static void pulse_encoder7_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER7_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER8 +static void pulse_encoder8_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER8_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER9 +static void pulse_encoder9_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER9_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER10 +static void pulse_encoder10_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER10_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER11 +static void pulse_encoder11_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER11_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +#ifdef BSP_USING_PULSE_ENCODER12 +static void pulse_encoder12_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + hc32_pulse_encoder_irq_handler(&pulse_encoder_obj[PULSE_ENCODER12_INDEX]); + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif + +static rt_uint16_t hc32_timer_get_unit_number(M4_TMRA_TypeDef *TMRAx) +{ + rt_uint16_t unit_num; + const rt_uint32_t unit_step = 0x400U; + + if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)M4_TMRA_1)) + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_1)) / unit_step; + } + else + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_5)) / unit_step + 4; + } + + return unit_num; +} + +static void hc32_timer_clock_config(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + rt_uint32_t timer_periph; + rt_uint16_t unit_num; + + unit_num = hc32_timer_get_unit_number(TMRAx); + timer_periph = PWC_FCG2_TMRA_1 << unit_num; + PWC_Fcg2PeriphClockCmd(timer_periph, enNewState); +} + +extern rt_err_t rt_hw_board_pulse_encoder_init(M4_TMRA_TypeDef *TMRAx); + +rt_err_t hc32_pulse_encoder_init(struct rt_pulse_encoder_device *pulse_encoder) +{ + struct hc32_pulse_encoder_config *pulse_encoder_device; + stc_tmra_init_t stcTmraInit; + rt_err_t result; + + RT_ASSERT(pulse_encoder != RT_NULL); + pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder; + /* Enable Timer peripheral clock. */ + hc32_timer_clock_config(pulse_encoder_device->timer_periph, Enable); + /* pwm pin configuration */ + result = rt_hw_board_pulse_encoder_init(pulse_encoder_device->timer_periph); + if (RT_EOK == result) + { + TMRA_DeInit(pulse_encoder_device->timer_periph); + TMRA_StructInit(&stcTmraInit); + stcTmraInit.u32PeriodVal = TIMER_AUTO_RELOAD_VALUE; + stcTmraInit.u32ClkSrc = TMRA_CLK_HW_UP_CLKBH_CLKAR | TMRA_CLK_HW_DOWN_CLKBL_CLKAR; + TMRA_Init(pulse_encoder_device->timer_periph, &stcTmraInit); + LOG_D("%s init success", pulse_encoder_device->name); + + hc32_install_irq_handler(&pulse_encoder_device->ovf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE); + NVIC_EnableIRQ(pulse_encoder_device->ovf_irq_config.irq); + hc32_install_irq_handler(&pulse_encoder_device->udf_irq_config, pulse_encoder_device->irq_callback, RT_FALSE); + NVIC_EnableIRQ(pulse_encoder_device->udf_irq_config.irq); + /* clear update flag */ + TMRA_ClrStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UNF)); + } + + return result; +} + +rt_err_t hc32_pulse_encoder_clear_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + struct hc32_pulse_encoder_config *pulse_encoder_device; + + pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder; + pulse_encoder_device->ovf_udf_count = 0; + TMRA_Stop(pulse_encoder_device->timer_periph); + TMRA_SetCntVal(pulse_encoder_device->timer_periph, 0); + TMRA_ClrStatus(pulse_encoder_device->timer_periph, (TMRA_FLAG_OVF | TMRA_FLAG_UNF)); + TMRA_Start(pulse_encoder_device->timer_periph); + + return RT_EOK; +} + +rt_int32_t hc32_pulse_encoder_get_count(struct rt_pulse_encoder_device *pulse_encoder) +{ + struct hc32_pulse_encoder_config *pulse_encoder_device; + rt_int32_t period_val; + rt_int32_t count_val; + + pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder; + period_val = TMRA_GetCntVal(pulse_encoder_device->timer_periph); + count_val = period_val + pulse_encoder_device->ovf_udf_count * TIMER_AUTO_RELOAD_VALUE; + + return count_val; +} + +rt_err_t hc32_pulse_encoder_control(struct rt_pulse_encoder_device *pulse_encoder, rt_uint32_t cmd, void *args) +{ + rt_err_t result = RT_EOK; + struct hc32_pulse_encoder_config *pulse_encoder_device; + pulse_encoder_device = (struct hc32_pulse_encoder_config*)pulse_encoder; + + switch (cmd) + { + case PULSE_ENCODER_CMD_ENABLE: + TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UNF), Enable); + TMRA_Start(pulse_encoder_device->timer_periph); + break; + case PULSE_ENCODER_CMD_DISABLE: + TMRA_Stop(pulse_encoder_device->timer_periph); + TMRA_IntCmd(pulse_encoder_device->timer_periph, (TMRA_INT_OVF | TMRA_INT_UNF), Disable); + break; + default: + result = -RT_ENOSYS; + break; + } + + return result; +} + +static const struct rt_pulse_encoder_ops pulse_encoder_ops = +{ + .init = hc32_pulse_encoder_init, + .get_count = hc32_pulse_encoder_get_count, + .clear_count = hc32_pulse_encoder_clear_count, + .control = hc32_pulse_encoder_control, +}; + +int hw_pulse_encoder_init(void) +{ + int i; + int result; + + result = RT_EOK; + for (i = 0; i < sizeof(pulse_encoder_obj) / sizeof(pulse_encoder_obj[0]); i++) + { + pulse_encoder_obj[i].pulse_encoder.type = AB_PHASE_PULSE_ENCODER; + pulse_encoder_obj[i].pulse_encoder.ops = &pulse_encoder_ops; + + if (rt_device_pulse_encoder_register(&pulse_encoder_obj[i].pulse_encoder, pulse_encoder_obj[i].name, pulse_encoder_obj[i].timer_periph) != RT_EOK) + { + LOG_E("%s register failed", pulse_encoder_obj[i].name); + result = -RT_ERROR; + } + } + + return result; +} +INIT_BOARD_EXPORT(hw_pulse_encoder_init); + +#endif diff --git a/bsp/hc32f4a0/drivers/drv_pulse_encoder.h b/bsp/hc32f4a0/drivers/drv_pulse_encoder.h new file mode 100644 index 0000000000000000000000000000000000000000..b338f14e64b41b79dce171143a29651905f7fc68 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_pulse_encoder.h @@ -0,0 +1,241 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#ifndef __DRV_PULSE_ENCODER_H__ +#define __DRV_PULSE_ENCODER_H__ + +#include +#include "board_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_PULSE_ENCODER1 +#ifndef PULSE_ENCODER1_OVF_IRQ_CONFIG +#define PULSE_ENCODER1_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER1_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER1_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER1_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER1_UDF_IRQ_CONFIG +#define PULSE_ENCODER1_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER1_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER1_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER1_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER1 */ + +#ifdef BSP_USING_PULSE_ENCODER2 +#ifndef PULSE_ENCODER2_OVF_IRQ_CONFIG +#define PULSE_ENCODER2_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER2_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER2_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER2_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER2_UDF_IRQ_CONFIG +#define PULSE_ENCODER2_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER2_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER2_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER2_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER2 */ + +#ifdef BSP_USING_PULSE_ENCODER3 +#ifndef PULSE_ENCODER3_OVF_IRQ_CONFIG +#define PULSE_ENCODER3_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER3_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER3_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER3_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER3_UDF_IRQ_CONFIG +#define PULSE_ENCODER3_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER3_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER3_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER3_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER3 */ + +#ifdef BSP_USING_PULSE_ENCODER4 +#ifndef PULSE_ENCODER4_OVF_IRQ_CONFIG +#define PULSE_ENCODER4_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER4_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER4_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER4_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER4_UDF_IRQ_CONFIG +#define PULSE_ENCODER4_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER4_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER4_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER4_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER4 */ + +#ifdef BSP_USING_PULSE_ENCODER5 +#ifndef PULSE_ENCODER5_OVF_IRQ_CONFIG +#define PULSE_ENCODER5_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER5_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER5_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER5_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER5_UDF_IRQ_CONFIG +#define PULSE_ENCODER5_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER5_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER5_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER5_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER5 */ + +#ifdef BSP_USING_PULSE_ENCODER6 +#ifndef PULSE_ENCODER6_OVF_IRQ_CONFIG +#define PULSE_ENCODER6_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER6_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER6_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER6_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER6_UDF_IRQ_CONFIG +#define PULSE_ENCODER6_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER6_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER6_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER6_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER6 */ + +#ifdef BSP_USING_PULSE_ENCODER7 +#ifndef PULSE_ENCODER7_OVF_IRQ_CONFIG +#define PULSE_ENCODER7_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER7_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER7_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER7_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER7_UDF_IRQ_CONFIG +#define PULSE_ENCODER7_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER7_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER7_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER7_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER7 */ + +#ifdef BSP_USING_PULSE_ENCODER8 +#ifndef PULSE_ENCODER8_OVF_IRQ_CONFIG +#define PULSE_ENCODER8_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER8_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER8_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER8_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER8_UDF_IRQ_CONFIG +#define PULSE_ENCODER8_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER8_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER8_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER8_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER8 */ + +#ifdef BSP_USING_PULSE_ENCODER9 +#ifndef PULSE_ENCODER9_OVF_IRQ_CONFIG +#define PULSE_ENCODER9_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER9_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER9_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER9_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER9_UDF_IRQ_CONFIG +#define PULSE_ENCODER9_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER9_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER9_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER9_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER9 */ + +#ifdef BSP_USING_PULSE_ENCODER10 +#ifndef PULSE_ENCODER10_OVF_IRQ_CONFIG +#define PULSE_ENCODER10_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER10_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER10_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER10_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER10_UDF_IRQ_CONFIG +#define PULSE_ENCODER10_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER10_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER10_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER10_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER10 */ + +#ifdef BSP_USING_PULSE_ENCODER11 +#ifndef PULSE_ENCODER11_OVF_IRQ_CONFIG +#define PULSE_ENCODER11_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER11_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER11_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER11_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER11_UDF_IRQ_CONFIG +#define PULSE_ENCODER11_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER11_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER11_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER11_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER11 */ + +#ifdef BSP_USING_PULSE_ENCODER12 +#ifndef PULSE_ENCODER12_OVF_IRQ_CONFIG +#define PULSE_ENCODER12_OVF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER12_OVF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER12_OVF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER12_OVF_IRQ_CONFIG */ + +#ifndef PULSE_ENCODER12_UDF_IRQ_CONFIG +#define PULSE_ENCODER12_UDF_IRQ_CONFIG \ + { \ + .irq = PULSE_ENCODER12_UNF_INT_IRQn, \ + .irq_prio = PULSE_ENCODER12_UNF_INT_PRIO, \ + } +#endif /* PULSE_ENCODER12_UDF_IRQ_CONFIG */ +#endif /* BSP_USING_PULSE_ENCODER12 */ + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_PULSE_ENCODER_H__ */ diff --git a/bsp/hc32f4a0/drivers/drv_pwm.c b/bsp/hc32f4a0/drivers/drv_pwm.c new file mode 100644 index 0000000000000000000000000000000000000000..a13560e16ee3c9df60e7a73dc4c9015744f1bc84 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_pwm.c @@ -0,0 +1,528 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#include +#include + +#ifdef RT_USING_PWM + +#if !defined(BSP_USING_PWM1) && !defined(BSP_USING_PWM2) && !defined(BSP_USING_PWM3) && \ + !defined(BSP_USING_PWM4) && !defined(BSP_USING_PWM5) && !defined(BSP_USING_PWM6) && \ + !defined(BSP_USING_PWM7) && !defined(BSP_USING_PWM8) && !defined(BSP_USING_PWM9) && \ + !defined(BSP_USING_PWM10) && !defined(BSP_USING_PWM11) && !defined(BSP_USING_PWM12) +#error "Please define at least one BSP_USING_PWMx" +/* this driver can be disabled at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable PWM */ +#endif + +#define PWM_MAX_PERIOD (65535U) +#define PWM_MIN_PERIOD (1U) +#define PWM_MIN_PULSE (1U) + +#define PWM_MAX_CHANNEL (TMRA_CH_4) + +enum +{ +#ifdef BSP_USING_PWM1 + PWM1_INDEX, +#endif +#ifdef BSP_USING_PWM2 + PWM2_INDEX, +#endif +#ifdef BSP_USING_PWM3 + PWM3_INDEX, +#endif +#ifdef BSP_USING_PWM4 + PWM4_INDEX, +#endif +#ifdef BSP_USING_PWM5 + PWM5_INDEX, +#endif +#ifdef BSP_USING_PWM6 + PWM6_INDEX, +#endif +#ifdef BSP_USING_PWM7 + PWM7_INDEX, +#endif +#ifdef BSP_USING_PWM8 + PWM8_INDEX, +#endif +#ifdef BSP_USING_PWM9 + PWM9_INDEX, +#endif +#ifdef BSP_USING_PWM10 + PWM10_INDEX, +#endif +#ifdef BSP_USING_PWM11 + PWM11_INDEX, +#endif +#ifdef BSP_USING_PWM12 + PWM12_INDEX, +#endif +}; + +struct hc32_pwm_config +{ + struct rt_device_pwm pwm_device; + M4_TMRA_TypeDef *timer_periph; + rt_uint8_t channel; + char *name; +}; + +#ifndef HC32_PWM_CONFIG +#define HC32_PWM_CONFIG(periph, ch, label) \ + { \ + .timer_periph = periph, \ + .channel = ch, \ + .name = label \ + } +#endif /* HC32_PWM_CONFIG */ + +static struct hc32_pwm_config pwm_obj[] = +{ +#ifdef BSP_USING_PWM1 + HC32_PWM_CONFIG(M4_TMRA_1 , 0, "pwm1"), +#endif +#ifdef BSP_USING_PWM2 + HC32_PWM_CONFIG(M4_TMRA_2 , 0, "pwm2"), +#endif +#ifdef BSP_USING_PWM3 + HC32_PWM_CONFIG(M4_TMRA_3 , 0, "pwm3"), +#endif +#ifdef BSP_USING_PWM4 + HC32_PWM_CONFIG(M4_TMRA_4 , 0, "pwm4"), +#endif +#ifdef BSP_USING_PWM5 + HC32_PWM_CONFIG(M4_TMRA_5 , 0, "pwm5"), +#endif +#ifdef BSP_USING_PWM6 + HC32_PWM_CONFIG(M4_TMRA_6 , 0, "pwm6"), +#endif +#ifdef BSP_USING_PWM7 + HC32_PWM_CONFIG(M4_TMRA_7 , 0, "pwm7"), +#endif +#ifdef BSP_USING_PWM8 + HC32_PWM_CONFIG(M4_TMRA_8 , 0, "pwm8"), +#endif +#ifdef BSP_USING_PWM9 + HC32_PWM_CONFIG(M4_TMRA_9 , 0, "pwm9"), +#endif +#ifdef BSP_USING_PWM10 + HC32_PWM_CONFIG(M4_TMRA_10 , 0, "pwm10"), +#endif +#ifdef BSP_USING_PWM11 + HC32_PWM_CONFIG(M4_TMRA_11 , 0, "pwm11"), +#endif +#ifdef BSP_USING_PWM12 + HC32_PWM_CONFIG(M4_TMRA_12 , 0, "pwm12"), +#endif +}; + +static rt_uint16_t hc32_pwm_get_unit_number(M4_TMRA_TypeDef *TMRAx) +{ + rt_uint16_t unit_num; + const rt_uint32_t unit_step = 0x400U; + + if (((rt_uint32_t)TMRAx) >= ((rt_uint32_t)M4_TMRA_1)) + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_1)) / unit_step; + } + else + { + unit_num = (((rt_uint32_t)TMRAx) - ((rt_uint32_t)M4_TMRA_5)) / unit_step + 4; + } + + return unit_num; +} + +static void hc32_pwm_clock_config(M4_TMRA_TypeDef *TMRAx, en_functional_state_t enNewState) +{ + rt_uint32_t timer_periph; + rt_uint16_t unit_num; + + unit_num = hc32_pwm_get_unit_number(TMRAx); + timer_periph = PWC_FCG2_TMRA_1 << unit_num; + PWC_Fcg2PeriphClockCmd(timer_periph, enNewState); +} + +static rt_err_t hc32_pwm_enable(M4_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration, rt_bool_t enable) +{ + if (configuration->channel > PWM_MAX_CHANNEL) + { + return RT_EINVAL; + } + + if (!enable) + { + TMRA_PWM_Cmd(TMRAx, configuration->channel, Disable); + } + else + { + TMRA_PWM_Cmd(TMRAx, configuration->channel, Enable); + } + + return RT_EOK; +} + +static rt_err_t hc32_pwm_get(M4_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration) +{ + stc_clk_freq_t stcClkFreq; + rt_uint32_t clk_freq; + rt_uint16_t unit_num; + rt_uint16_t div_val; + + CLK_GetClockFreq(&stcClkFreq); + unit_num = hc32_pwm_get_unit_number(TMRAx); + if (unit_num >= 4) + { + clk_freq = stcClkFreq.pclk1Freq; + } + else + { + clk_freq = stcClkFreq.pclk0Freq; + } + + /* Convert nanosecond to frequency and duty cycle */ + div_val = 0x01 << (READ_REG32_BIT(TMRAx->BCSTR, TMRA_BCSTR_CKDIV) >> TMRA_BCSTR_CKDIV_POS); + clk_freq /= 1000000UL; + configuration->period = (TMRA_GetPeriodVal(TMRAx) + 1) * div_val * 1000UL / clk_freq; + configuration->pulse = (TMRA_GetCmpVal(TMRAx, configuration->channel) + 1) * div_val * 1000UL / clk_freq; + + return RT_EOK; +} + +static rt_err_t hc32_pwm_set(M4_TMRA_TypeDef *TMRAx, struct rt_pwm_configuration *configuration) +{ + rt_uint32_t period, pulse; + rt_uint64_t clk_div; + stc_clk_freq_t stcClkFreq; + rt_uint32_t clk_freq; + rt_uint16_t unit_num; + rt_uint16_t div_val; + + CLK_GetClockFreq(&stcClkFreq); + unit_num = hc32_pwm_get_unit_number(TMRAx); + if (unit_num >= 4) + { + clk_freq = stcClkFreq.pclk1Freq; + } + else + { + clk_freq = stcClkFreq.pclk0Freq; + } + /* Convert nanosecond to frequency and duty cycle */ + clk_freq /= 1000000UL; + period = (unsigned long long)configuration->period * clk_freq / 1000UL; + clk_div = period / PWM_MAX_PERIOD + 1; + + if (clk_div > 1024) + { + return RT_EINVAL; + } + else if (clk_div != 1) + { + for (div_val=512; div_val>1; div_val>>=1) + { + if (clk_div > div_val) + { + clk_div = div_val << 1; + break; + } + } + } + period = period / clk_div; + TMRA_SetPCLKDiv(TMRAx, ((__CLZ(__RBIT(clk_div))) << TMRA_BCSTR_CKDIV_POS)); + + if (period < PWM_MIN_PERIOD) + { + period = PWM_MIN_PERIOD; + } + TMRA_SetPeriodVal(TMRAx, period - 1); + + pulse = (unsigned long long)configuration->pulse * clk_freq / clk_div / 1000UL; + if (pulse < PWM_MIN_PULSE) + { + pulse = PWM_MIN_PULSE; + } + else if (pulse > period) + { + pulse = period; + } + TMRA_SetCmpVal(TMRAx, configuration->channel, pulse - 1); + TMRA_SetCntVal(TMRAx, 0); + + return RT_EOK; +} + +static rt_err_t hc32_pwm_control(struct rt_device_pwm *device, int cmd, void *arg) +{ + struct rt_pwm_configuration *configuration = (struct rt_pwm_configuration *)arg; + M4_TMRA_TypeDef *timer_periph = (M4_TMRA_TypeDef *)device->parent.user_data; + + switch (cmd) + { + case PWM_CMD_ENABLE: + return hc32_pwm_enable(timer_periph, configuration, RT_TRUE); + case PWM_CMD_DISABLE: + return hc32_pwm_enable(timer_periph, configuration, RT_FALSE); + case PWM_CMD_SET: + return hc32_pwm_set(timer_periph, configuration); + case PWM_CMD_GET: + return hc32_pwm_get(timer_periph, configuration); + default: + return RT_EINVAL; + } +} + +extern rt_err_t rt_hw_board_pwm_init(M4_TMRA_TypeDef *TMRAx); + +static rt_err_t hc32_pwm_init(struct hc32_pwm_config *device) +{ + rt_err_t result = RT_EOK; + stc_tmra_init_t stcTmraInit; + stc_tmra_pwm_cfg_t stcPwmCfg; + + RT_ASSERT(device != RT_NULL); + + /* Enable Timer peripheral clock. */ + hc32_pwm_clock_config(device->timer_periph, Enable); + /* pwm pin configuration */ + result = rt_hw_board_pwm_init(device->timer_periph); + if (RT_EOK == result) + { + TMRA_DeInit(device->timer_periph); + TMRA_StructInit(&stcTmraInit); + stcTmraInit.u32PCLKDiv = TMRA_PCLK_DIV1; + stcTmraInit.u32CntOvfOp = TMRA_OVF_CNT_CONTINUE; + stcTmraInit.u32PeriodVal = 0xFFFF; + stcTmraInit.u32CntVal = 0; + TMRA_Init(device->timer_periph, &stcTmraInit); + + /* Set the comparison reference value */ + TMRA_PWM_StructInit(&stcPwmCfg); + stcPwmCfg.u32StartPolarity = TMRA_PWM_START_HIGH; + stcPwmCfg.u32StopPolarity = TMRA_PWM_STOP_LOW; + stcPwmCfg.u32CmpPolarity = TMRA_PWM_CMP_LOW; + stcPwmCfg.u32PeriodPolarity = TMRA_PWM_PERIOD_HIGH; + + /* config pwm channel */ + if (0 != (device->channel & 0x01)) + { + TMRA_PWM_Config(device->timer_periph, TMRA_CH_1, &stcPwmCfg); + TMRA_SetCmpVal(device->timer_periph, TMRA_CH_1, 0x7FFF); + } + if (0 != (device->channel & 0x02)) + { + TMRA_PWM_Config(device->timer_periph, TMRA_CH_2, &stcPwmCfg); + TMRA_SetCmpVal(device->timer_periph, TMRA_CH_2, 0x7FFF); + } + if (0 != (device->channel & 0x04)) + { + TMRA_PWM_Config(device->timer_periph, TMRA_CH_3, &stcPwmCfg); + TMRA_SetCmpVal(device->timer_periph, TMRA_CH_3, 0x7FFF); + } + if (0 != (device->channel & 0x08)) + { + TMRA_PWM_Config(device->timer_periph, TMRA_CH_4, &stcPwmCfg); + TMRA_SetCmpVal(device->timer_periph, TMRA_CH_4, 0x7FFF); + } + /* start timer */ + TMRA_Start(device->timer_periph); + } + + return result; +} + +static void hc32_pwm_get_channel(void) +{ +#ifdef BSP_USING_PWM1_CH1 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM1_CH2 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM1_CH3 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM1_CH4 + pwm_obj[PWM1_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM2_CH1 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM2_CH2 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM2_CH3 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM2_CH4 + pwm_obj[PWM2_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM3_CH1 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM3_CH2 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM3_CH3 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM3_CH4 + pwm_obj[PWM3_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM4_CH1 + pwm_obj[PWM4_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM4_CH2 + pwm_obj[PWM4_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM4_CH3 + pwm_obj[PWM4_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM4_CH4 + pwm_obj[PWM4_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM5_CH1 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM5_CH2 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM5_CH3 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM5_CH4 + pwm_obj[PWM5_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM6_CH1 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM6_CH2 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM6_CH3 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM6_CH4 + pwm_obj[PWM6_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM7_CH1 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM7_CH2 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM7_CH3 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM7_CH4 + pwm_obj[PWM7_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM8_CH1 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM8_CH2 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM8_CH3 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM8_CH4 + pwm_obj[PWM8_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM9_CH1 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM9_CH2 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM9_CH3 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM9_CH4 + pwm_obj[PWM9_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM10_CH1 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM10_CH2 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM10_CH3 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM10_CH4 + pwm_obj[PWM10_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM11_CH1 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM11_CH2 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM11_CH3 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM11_CH4 + pwm_obj[PWM11_INDEX].channel |= (0x01 << 3); +#endif +#ifdef BSP_USING_PWM12_CH1 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 0); +#endif +#ifdef BSP_USING_PWM12_CH2 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 1); +#endif +#ifdef BSP_USING_PWM12_CH3 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 2); +#endif +#ifdef BSP_USING_PWM12_CH4 + pwm_obj[PWM12_INDEX].channel |= (0x01 << 3); +#endif +} + +static struct rt_pwm_ops pwm_ops = +{ + .control = hc32_pwm_control +}; + +static int rt_hw_pwm_init(void) +{ + int i = 0; + int result = RT_EOK; + + hc32_pwm_get_channel(); + for (i = 0; i < sizeof(pwm_obj) / sizeof(pwm_obj[0]); i++) + { + if (hc32_pwm_init(&pwm_obj[i]) != RT_EOK) + { + LOG_E("%s init failed", pwm_obj[i].name); + result = -RT_ERROR; + } + else + { + LOG_D("%s init success", pwm_obj[i].name); + /* register pwm device */ + if (rt_device_pwm_register(&pwm_obj[i].pwm_device, pwm_obj[i].name, &pwm_ops, pwm_obj[i].timer_periph) == RT_EOK) + { + LOG_D("%s register success", pwm_obj[i].name); + } + else + { + LOG_E("%s register failed", pwm_obj[i].name); + result = -RT_ERROR; + } + } + } + + return result; +} +INIT_DEVICE_EXPORT(rt_hw_pwm_init); + +#endif /* RT_USING_PWM */ diff --git a/bsp/hc32f4a0/drivers/drv_rtc.c b/bsp/hc32f4a0/drivers/drv_rtc.c new file mode 100644 index 0000000000000000000000000000000000000000..4ccaa4625345ac19088273b9ac4fb75e52fa3f16 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_rtc.c @@ -0,0 +1,192 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +#include "board.h" +#include + +#ifdef BSP_USING_RTC + +static struct rt_device rtc; + +static time_t hc32_rtc_get_time_stamp(void) +{ + stc_rtc_time_t stcRtcTime = {0}; + stc_rtc_date_t stcRtcDate = {0}; + struct tm tm_new = {0}; + + RTC_GetTime(RTC_DATA_FORMAT_DEC, &stcRtcTime); + RTC_GetDate(RTC_DATA_FORMAT_DEC, &stcRtcDate); + + tm_new.tm_sec = stcRtcTime.u8Second; + tm_new.tm_min = stcRtcTime.u8Minute; + tm_new.tm_hour = stcRtcTime.u8Hour; + tm_new.tm_mday = stcRtcDate.u8Day; + tm_new.tm_mon = stcRtcDate.u8Month - 1; + tm_new.tm_year = stcRtcDate.u8Year + 100; + tm_new.tm_wday = stcRtcDate.u8Weekday; + + LOG_D("get rtc time."); + return mktime(&tm_new); +} + +static rt_err_t hc32_rtc_set_time_stamp(time_t time_stamp) +{ + stc_rtc_time_t stcRtcTime = {0}; + stc_rtc_date_t stcRtcDate = {0}; + struct tm *p_tm; + + p_tm = localtime(&time_stamp); + if (p_tm->tm_year < 100) + { + return -RT_ERROR; + } + + stcRtcTime.u8Second = p_tm->tm_sec ; + stcRtcTime.u8Minute = p_tm->tm_min ; + stcRtcTime.u8Hour = p_tm->tm_hour; + stcRtcDate.u8Day = p_tm->tm_mday; + stcRtcDate.u8Month = p_tm->tm_mon + 1 ; + stcRtcDate.u8Year = p_tm->tm_year - 100; + stcRtcDate.u8Weekday = p_tm->tm_wday; + + if (Ok != RTC_SetTime(RTC_DATA_FORMAT_DEC, &stcRtcTime)) + { + return -RT_ERROR; + } + if (Ok != RTC_SetDate(RTC_DATA_FORMAT_DEC, &stcRtcDate)) + { + return -RT_ERROR; + } + + LOG_D("set rtc time."); + return RT_EOK; +} + +static rt_err_t hc32_rtc_init(struct rt_device *dev) +{ + stc_rtc_init_t stcRtcInit; + +#ifdef BSP_RTC_USING_XTAL32 + stc_clk_xtal32_init_t stcXtal32Init; + + /* Xtal32 config */ + stcXtal32Init.u8Xtal32State = CLK_XTAL32_ON; + stcXtal32Init.u8Xtal32Drv = CLK_XTAL32DRV_HIGH; + stcXtal32Init.u8Xtal32NF = CLK_XTAL32NF_PART; + (void)CLK_Xtal32Init(&stcXtal32Init); + /* Waiting for XTAL32 stabilization */ + rt_thread_delay(1000); +#endif + + /* Reset RTC counter */ + if (ErrorTimeout == RTC_DeInit()) + { + return -RT_ERROR; + } + else + { + /* Configure structure initialization */ + (void)RTC_StructInit(&stcRtcInit); + /* Configuration RTC structure */ +#ifdef BSP_RTC_USING_XTAL32 + stcRtcInit.u8ClockSource = RTC_CLOCK_SOURCE_XTAL32; +#else + stcRtcInit.u8ClockSource = RTC_CLOCK_SOURCE_RTCLRC; +#endif + stcRtcInit.u8HourFormat = RTC_HOUR_FORMAT_24; + (void)RTC_Init(&stcRtcInit); + /* Startup RTC count */ + RTC_Cmd(Enable); + } + + return RT_EOK; +} + +static rt_err_t hc32_rtc_control(rt_device_t dev, int cmd, void *args) +{ + rt_err_t result = RT_EOK; + + RT_ASSERT(dev != RT_NULL); + switch (cmd) + { + case RT_DEVICE_CTRL_RTC_GET_TIME: + *(rt_uint32_t *)args = hc32_rtc_get_time_stamp(); + LOG_D("RTC: get rtc_time %x\n", *(rt_uint32_t *)args); + break; + + case RT_DEVICE_CTRL_RTC_SET_TIME: + if (hc32_rtc_set_time_stamp(*(rt_uint32_t *)args)) + { + result = -RT_ERROR; + } + LOG_D("RTC: set rtc_time %x\n", *(rt_uint32_t *)args); + break; + default: + return RT_EINVAL; + } + + return result; +} + +#ifdef RT_USING_DEVICE_OPS +const static struct rt_device_ops rtc_ops = +{ + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + RT_NULL, + hc32_rtc_control +}; +#endif + +static rt_err_t rt_hw_rtc_register(rt_device_t device, const char *name, rt_uint32_t flag) +{ + RT_ASSERT(device != RT_NULL); + + if (hc32_rtc_init(device) != RT_EOK) + { + return -RT_ERROR; + } +#ifdef RT_USING_DEVICE_OPS + device->ops = &rtc_ops; +#else + device->init = RT_NULL; + device->open = RT_NULL; + device->close = RT_NULL; + device->read = RT_NULL; + device->write = RT_NULL; + device->control = hc32_rtc_control; +#endif + device->type = RT_Device_Class_RTC; + device->rx_indicate = RT_NULL; + device->tx_complete = RT_NULL; + device->user_data = RT_NULL; + + /* register a character device */ + return rt_device_register(device, name, flag); +} + +int rt_hw_rtc_init(void) +{ + rt_err_t result; + + result = rt_hw_rtc_register(&rtc, "rtc", RT_DEVICE_FLAG_RDWR); + if (result != RT_EOK) + { + LOG_E("rtc register err code: %d", result); + return result; + } + LOG_D("rtc init success"); + return RT_EOK; +} +INIT_DEVICE_EXPORT(rt_hw_rtc_init); + +#endif /* BSP_USING_RTC */ diff --git a/bsp/hc32f4a0/drivers/drv_soft_i2c.c b/bsp/hc32f4a0/drivers/drv_soft_i2c.c new file mode 100644 index 0000000000000000000000000000000000000000..38258ba7eebb7b31f1796c02674feb68ca10c4ff --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_soft_i2c.c @@ -0,0 +1,218 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include "drv_soft_i2c.h" +#include "board.h" + +#if defined RT_USING_I2C + +#if !defined(BSP_USING_I2C1) && !defined(BSP_USING_I2C2) && \ + !defined(BSP_USING_I2C3) && !defined(BSP_USING_I2C4) && \ + !defined(BSP_USING_I2C5) && !defined(BSP_USING_I2C6) +#error "Please define at least one BSP_USING_I2Cx" +#endif + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ + +static const struct hc32_soft_i2c_config soft_i2c_config[] = +{ +#ifdef BSP_USING_I2C1 + I2C1_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C2 + I2C2_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C3 + I2C3_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C4 + I2C4_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C5 + I2C5_BUS_CONFIG, +#endif +#ifdef BSP_USING_I2C6 + I2C6_BUS_CONFIG, +#endif +}; + + +static struct hc32_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; + + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +/** + * This function initializes the i2c pin. + * + * @param Hc32 i2c dirver class. + */ +static void hc32_i2c_gpio_init(struct hc32_i2c *i2c) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)i2c->ops.data; + + rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT); + rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT); + + rt_pin_write(cfg->scl_pin, PIN_HIGH); + rt_pin_write(cfg->sda_pin, PIN_HIGH); +} + +/** + * This function sets the sda pin. + * + * @param Hc32 config class. + * @param The sda pin state. + */ +static void hc32_set_sda(void *data, rt_int32_t state) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + rt_pin_mode(cfg->sda_pin, PIN_MODE_OUTPUT); + + if (state) + rt_pin_write(cfg->sda_pin, PIN_HIGH); + else + rt_pin_write(cfg->sda_pin, PIN_LOW); +} + +/** + * This function sets the scl pin. + * + * @param Hc32 config class. + * @param The scl pin state. + */ +static void hc32_set_scl(void *data, rt_int32_t state) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + rt_pin_mode(cfg->scl_pin, PIN_MODE_OUTPUT); + + if (state) + rt_pin_write(cfg->scl_pin, PIN_HIGH); + else + rt_pin_write(cfg->scl_pin, PIN_LOW); +} + +/** + * This function gets the sda pin state. + * + * @param The sda pin state. + */ +static rt_int32_t hc32_get_sda(void *data) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + rt_pin_mode(cfg->sda_pin, PIN_MODE_INPUT); + + return rt_pin_read(cfg->sda_pin); +} + +/** + * This function gets the scl pin state. + * + * @param The scl pin state. + */ +static rt_int32_t hc32_get_scl(void *data) +{ + struct hc32_soft_i2c_config* cfg = (struct hc32_soft_i2c_config*)data; + + rt_pin_mode(cfg->scl_pin, PIN_MODE_INPUT); + + return rt_pin_read(cfg->scl_pin); +} + +static void hc32_udelay(rt_uint32_t us) +{ + rt_hw_us_delay(us); +} + +static const struct rt_i2c_bit_ops hc32_bit_ops = +{ + .data = RT_NULL, + .set_sda = hc32_set_sda, + .set_scl = hc32_set_scl, + .get_sda = hc32_get_sda, + .get_scl = hc32_get_scl, + .udelay = hc32_udelay, + .delay_us = 1, + .timeout = 100 +}; + +static rt_err_t hc32_i2c_bus_unlock(const struct hc32_soft_i2c_config *cfg) +{ + rt_uint32_t i = 0; + + if (PIN_LOW == rt_pin_read(cfg->sda_pin)) + { + while (i++ < 9) + { + rt_pin_write(cfg->scl_pin, PIN_HIGH); + //HC32_udelay(100); + rt_pin_write(cfg->scl_pin, PIN_LOW); + //hc32_udelay(100); + } + } + if(PIN_LOW == rt_pin_read(cfg->sda_pin)) + return RT_ERROR; + + return RT_EOK; +} + +/* I2C initialization function */ +int hc32_hw_i2c_init(void) +{ + rt_size_t obj_num = sizeof(i2c_obj) / sizeof(struct hc32_i2c); + rt_err_t result; + + for (int i = 0; i < obj_num; i++) + { + i2c_obj[i].ops = hc32_bit_ops; + i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; + i2c_obj[i].i2c1_bus.priv = &i2c_obj[i].ops; + hc32_i2c_gpio_init(&i2c_obj[i]); + result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c1_bus, soft_i2c_config[i].bus_name); + RT_ASSERT(result == RT_EOK); + hc32_i2c_bus_unlock(&soft_i2c_config[i]); + } + + return RT_EOK; +} +INIT_BOARD_EXPORT(hc32_hw_i2c_init); + + +#endif /* RT_USING_I2C */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/drivers/drv_soft_i2c.h b/bsp/hc32f4a0/drivers/drv_soft_i2c.h new file mode 100644 index 0000000000000000000000000000000000000000..64dec1184b43187d0d7f1647e36cf802ca983204 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_soft_i2c.h @@ -0,0 +1,128 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __DRV_I2C_H__ +#define __DRV_I2C_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "hc32_ddl.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ +struct hc32_soft_i2c_config +{ + rt_uint16_t scl_pin; + rt_uint16_t sda_pin; + const char *bus_name; +}; + +#ifdef BSP_USING_I2C1 +#define I2C1_BUS_CONFIG \ + { \ + .scl_pin = BSP_I2C1_SCL_PIN, \ + .sda_pin = BSP_I2C1_SDA_PIN, \ + .bus_name = "i2c1", \ + } +#endif + +#ifdef BSP_USING_I2C2 +#define I2C2_BUS_CONFIG \ + { \ + .scl = BSP_I2C2_SCL_PIN, \ + .sda = BSP_I2C2_SDA_PIN, \ + .bus_name = "i2c2", \ + } +#endif + +#ifdef BSP_USING_I2C3 +#define I2C3_BUS_CONFIG \ + { \ + .scl = BSP_I2C3_SCL_PIN, \ + .sda = BSP_I2C3_SDA_PIN, \ + .bus_name = "i2c3", \ + } +#endif + +#ifdef BSP_USING_I2C4 +#define I2C4_BUS_CONFIG \ + { \ + .scl = BSP_I2C4_SCL_PIN, \ + .sda = BSP_I2C4_SDA_PIN, \ + .bus_name = "i2c4", \ + } +#endif + +#ifdef BSP_USING_I2C5 +#define I2C5_BUS_CONFIG \ + { \ + .scl = BSP_I2C5_SCL_PIN, \ + .sda = BSP_I2C5_SDA_PIN, \ + .bus_name = "i2c5", \ + } +#endif + +#ifdef BSP_USING_I2C6 +#define I2C6_BUS_CONFIG \ + { \ + .scl = BSP_I2C6_SCL_PIN, \ + .sda = BSP_I2C6_SDA_PIN, \ + .bus_name = "i2c6", \ + } +#endif + +/** + ******************************************************************************* + ** \brief Open parameters. + ******************************************************************************* + */ +struct hc32_i2c_config +{ + rt_uint8_t scl; + rt_uint8_t sda; + const char *bus_name; +}; + +struct hc32_i2c +{ + struct rt_i2c_bit_ops ops; + struct rt_i2c_bus_device i2c1_bus; +}; + + +typedef struct hc32_i2c_instance +{ + rt_uint32_t id; + void *handle; + stc_i2c_init_t init; +} hc32_i2c_instance_t; + + +int hc32_hw_i2c_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_I2C_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/drivers/drv_spi.c b/bsp/hc32f4a0/drivers/drv_spi.c new file mode 100644 index 0000000000000000000000000000000000000000..e4e29f6910e93ef1012dec753ff3588a00616035 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_spi.c @@ -0,0 +1,1004 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "drv_spi.h" + + +#if defined(RT_USING_SPI) && defined(RT_USING_PIN) +#include + +#if !defined(BSP_USING_SPI1) && !defined(BSP_USING_SPI2) && \ + !defined(BSP_USING_SPI3) && !defined(BSP_USING_SPI4) && \ + !defined(BSP_USING_SPI5) && !defined(BSP_USING_SPI6) +#error "Please define at least one SPIx" +#endif + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +/* #define DEBUG */ +#ifndef HC32_SPI_DEBUG +#define SPI_PRINT_DBG(fmt, args...) +#define SPI_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args); +#else +#define SPI_PRINT_DBG(fmt, args...) rt_kprintf(fmt, ##args); +#define SPI_PRINT_ERR(fmt, args...) rt_kprintf(fmt, ##args); +#endif + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ + +/* private rt-thread spi ops function */ +static rt_err_t hc32_spi_configure(struct rt_spi_device* device, + struct rt_spi_configuration* configuration); +static rt_uint32_t hc32_spi_xfer(struct rt_spi_device* device, + struct rt_spi_message* message); + +#if defined(BSP_USING_SPI1) +static void spi1_rx_dma_irq_handle(void); +static void spi1_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI1 */ + +#if defined(BSP_USING_SPI2) +static void spi2_rx_dma_irq_handle(void); +static void spi2_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI2 */ + +#if defined(BSP_USING_SPI3) +static void spi3_rx_dma_irq_handle(void); +static void spi3_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI3 */ + +#if defined(BSP_USING_SPI4) +static void spi4_rx_dma_irq_handle(void); +static void spi4_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI4 */ + +#if defined(BSP_USING_SPI5) +static void spi5_rx_dma_irq_handle(void); +static void spi5_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI5 */ + +#if defined(BSP_USING_SPI6) +static void spi6_rx_dma_irq_handle(void); +static void spi6_tx_dma_irq_handle(void); +#endif /* BSP_USING_SPI6 */ + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +enum +{ +#ifdef BSP_USING_SPI1 + SPI1_INDEX, +#endif +#ifdef BSP_USING_SPI2 + SPI2_INDEX, +#endif +#ifdef BSP_USING_SPI3 + SPI3_INDEX, +#endif +#ifdef BSP_USING_SPI4 + SPI4_INDEX, +#endif +#ifdef BSP_USING_SPI5 + SPI5_INDEX, +#endif +#ifdef BSP_USING_SPI6 + SPI6_INDEX, +#endif + SPI_INDEX_MAX, +}; + +static const struct spi_index spi_map[] = +{ +#ifdef BSP_USING_SPI1 + {SPI1_INDEX, M4_SPI1}, +#endif +#ifdef BSP_USING_SPI2 + {SPI2_INDEX, M4_SPI2}, +#endif +#ifdef BSP_USING_SPI3 + {SPI3_INDEX, M4_SPI3}, +#endif +#ifdef BSP_USING_SPI4 + {SPI4_INDEX, M4_SPI4}, +#endif +#ifdef BSP_USING_SPI5 + {SPI5_INDEX, M4_SPI5}, +#endif +#ifdef BSP_USING_SPI6 + {SPI6_INDEX, M4_SPI6}, +#endif +}; + +static struct hc32_spi_config spi_config[] = +{ +#ifdef BSP_USING_SPI1 + SPI1_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI2 + SPI2_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI3 + SPI3_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI4 + SPI4_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI5 + SPI5_BUS_CONFIG, +#endif + +#ifdef BSP_USING_SPI6 + SPI6_BUS_CONFIG, +#endif +}; + +static const struct spi_irq_handler spi_irq_handlers[] = +{ +#ifdef BSP_USING_SPI1 + {spi1_rx_dma_irq_handle, spi1_tx_dma_irq_handle}, +#endif + +#ifdef BSP_USING_SPI2 + {spi2_rx_dma_irq_handle, spi2_tx_dma_irq_handle}, +#endif + +#ifdef BSP_USING_SPI3 + {spi3_rx_dma_irq_handle, spi3_tx_dma_irq_handle}, +#endif + +#ifdef BSP_USING_SPI4 + {spi4_rx_dma_irq_handle, spi4_tx_dma_irq_handle}, +#endif + +#ifdef BSP_USING_SPI5 + {spi5_rx_dma_irq_handle, spi5_tx_dma_irq_handle}, +#endif + +#ifdef BSP_USING_SPI6 + {spi6_rx_dma_irq_handle, spi6_tx_dma_irq_handle}, +#endif +}; + +static struct hc32_spi spi_bus_obj[sizeof(spi_config) / sizeof(spi_config[0])] = {0}; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ +extern void hc32_board_spi_init(M4_SPI_TypeDef *M4_SPIx, rt_uint8_t mode); + +/** + * @brief This function gets index for specific SPI_Instance. + * @param Instance + * @retval index + */ +static uint32_t get_spi_index(M4_SPI_TypeDef *Instance) +{ + uint32_t index = SPI_INDEX_MAX; + + for (uint8_t i = 0U; i < ARRAY_SZ(spi_map); i++) + { + if (spi_map[i].Instance == Instance) + { + index = spi_map[i].index; + RT_ASSERT(index < SPI_INDEX_MAX) + break; + } + } + + return index; +} + +static uint32_t get_spi_fcg(M4_SPI_TypeDef *Instance) +{ + return (PWC_FCG1_SPI1 << get_spi_index(Instance)); +} + +rt_err_t hc32_spi_init(struct hc32_spi *spi_drv, struct rt_spi_configuration *cfg) +{ + RT_ASSERT(spi_drv != RT_NULL); + RT_ASSERT(cfg != RT_NULL); + + stc_spi_init_t stcSpiInit; + stc_clk_freq_t stcClkFreq; + + M4_SPI_TypeDef *spi_handle = spi_drv->handle.Instance; + + /* Enable spi clock gate */ + PWC_Fcg1PeriphClockCmd(get_spi_fcg(spi_handle), Enable); + + /* Init spi struct as default value */ + SPI_StructInit(&stcSpiInit); + + /* Slave or master mode */ + if (cfg->mode & RT_SPI_SLAVE) + { + stcSpiInit.u32MasterSlave = SPI_SLAVE; + } + else + { + stcSpiInit.u32MasterSlave = SPI_MASTER; + } + /* 3 wire or 4 wire mode */ + if (cfg->mode & RT_SPI_3WIRE) + { + stcSpiInit.u32WireMode = SPI_WIRE_3; + } + else + { + stcSpiInit.u32WireMode = SPI_WIRE_4; + } + /* spi mode */ + if (0x00 == (cfg->mode & (RT_SPI_CPHA | RT_SPI_CPOL))) + { + stcSpiInit.u32SpiMode = SPI_MODE_0; + } + else if (0x01 == (cfg->mode & (RT_SPI_CPHA | RT_SPI_CPOL))) + { + stcSpiInit.u32SpiMode = SPI_MODE_1; + } + else if (0x02 == (cfg->mode & (RT_SPI_CPHA | RT_SPI_CPOL))) + { + stcSpiInit.u32SpiMode = SPI_MODE_2; + } + else if (0x03 == (cfg->mode & (RT_SPI_CPHA | RT_SPI_CPOL))) + { + stcSpiInit.u32SpiMode = SPI_MODE_3; + } + /* LSB or MSB */ + if (cfg->mode & RT_SPI_MSB) + { + stcSpiInit.u32FirstBit = SPI_FIRST_MSB; + } + else + { + stcSpiInit.u32FirstBit = SPI_FIRST_LSB; + } + + /* config data width 4~16, 20, 24, 32 */ + if (4u > cfg->data_width) + { + return RT_EIO; + } + else if (16u >= cfg->data_width) + { + stcSpiInit.u32DataBits = ((cfg->data_width - 4u) << 8u); + } + else if (20u == cfg->data_width) + { + stcSpiInit.u32DataBits = SPI_DATA_SIZE_20BIT; + } + else if (24u == cfg->data_width) + { + stcSpiInit.u32DataBits = SPI_DATA_SIZE_24BIT; + } + else if (32u == cfg->data_width) + { + stcSpiInit.u32DataBits = SPI_DATA_SIZE_32BIT; + } + else + { + return RT_EIO; + } + + /* Get APB clock */ + CLK_GetClockFreq(&stcClkFreq); + if (cfg->max_hz >= stcClkFreq.pclk1Freq / 2u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV2; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 4u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV4; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 8u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV8; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 16u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV16; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 32u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV32; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 64u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV64; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 128u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV128; + } + else if (cfg->max_hz >= stcClkFreq.pclk1Freq / 256u) + { + stcSpiInit.u32BaudRatePrescaler = SPI_BR_PCLK1_DIV256; + } + + /* spi port init */ + hc32_board_spi_init(spi_handle, cfg->mode); + + if (Ok != SPI_Init(spi_handle, &stcSpiInit)) + { + return RT_EIO; + } + + /* DMA configuration */ + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + struct dma_config *spi_dma; + stc_dma_init_t stcDmaInit; + + /* Get spi dma_rx */ + spi_dma = spi_drv->config->dma_rx; + + /* Config Dma */ + DMA_StructInit(&stcDmaInit); + stcDmaInit.u32IntEn = DMA_INT_ENABLE; + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32TransCnt = 0; + stcDmaInit.u32DestAddr = 0; + stcDmaInit.u32SrcAddr = (uint32_t)(&spi_handle->DR); + stcDmaInit.u32SrcInc = DMA_SRC_ADDR_FIX; + stcDmaInit.u32DestInc = DMA_DEST_ADDR_INC; + + if (8u >= cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + } + else if (16u >= cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + } + else + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_32BIT; + } + /* Enable Dma clock gate */ + if (M4_DMA1 == spi_dma->Instance) + { + PWC_Fcg0PeriphClockCmd(PWC_FCG0_DMA1, Enable); + } + else + { + PWC_Fcg0PeriphClockCmd(PWC_FCG0_DMA2, Enable); + } + /* Init Dma */ + if (Ok != DMA_Init(spi_dma->Instance, spi_dma->channel, &stcDmaInit)) + { + return RT_EIO; + } + + /* register interrupt */ + hc32_install_irq_handler(&spi_dma->irq_config, + spi_irq_handlers[get_spi_index(spi_handle)].rx_dma_irq_handler, + RT_TRUE); + + /* Enable Dma */ + DMA_Cmd(spi_dma->Instance, Enable); + } + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + struct dma_config *spi_dma; + stc_dma_init_t stcDmaInit; + + /* Get spi dma_tx */ + spi_dma = spi_drv->config->dma_tx; + + /* Config Dma */ + DMA_StructInit(&stcDmaInit); + stcDmaInit.u32IntEn = DMA_INT_ENABLE; + stcDmaInit.u32BlockSize = 1UL; + stcDmaInit.u32TransCnt = 0; + stcDmaInit.u32DestAddr = (uint32_t)(&spi_handle->DR);; + stcDmaInit.u32SrcAddr = 0; + stcDmaInit.u32SrcInc = DMA_SRC_ADDR_INC; + stcDmaInit.u32DestInc = DMA_DEST_ADDR_FIX; + + if (8u >= cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_8BIT; + } + else if (16u >= cfg->data_width) + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_16BIT; + } + else + { + stcDmaInit.u32DataWidth = DMA_DATAWIDTH_32BIT; + } + /* Enable Dma clock gate */ + if (M4_DMA1 == spi_dma->Instance) + { + PWC_Fcg0PeriphClockCmd(PWC_FCG0_DMA1 | PWC_FCG0_AOS, Enable); + } + else + { + PWC_Fcg0PeriphClockCmd(PWC_FCG0_DMA2 | PWC_FCG0_AOS, Enable); + } + /* Init Dma */ + if (Ok != DMA_Init(spi_dma->Instance, spi_dma->channel, &stcDmaInit)) + { + return RT_EIO; + } + + /* register interrupt */ + hc32_install_irq_handler(&spi_dma->irq_config, + spi_irq_handlers[get_spi_index(spi_handle)].tx_dma_irq_handler, + RT_TRUE); + + /* Enable Dma */ + DMA_Cmd(spi_dma->Instance, Enable); + } + + return RT_EOK; +} + +static void hc32_spi_deinit(struct hc32_spi *spi_drv) +{ + M4_SPI_TypeDef *spi_handle = spi_drv->handle.Instance; + + SPI_DeInit(spi_handle); + + /* Disable spi clock gate */ + PWC_Fcg1PeriphClockCmd(get_spi_fcg(spi_handle), Disable); +} + +static rt_err_t hc32_spi_dma(struct hc32_spi_config *spi_dma, const uint8_t *pvTxBuf, void *pvRxBuf, uint32_t u32Length) +{ + if (RT_NULL == pvTxBuf) + { + DMA_SetDestAddr(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel, (uint32_t)pvRxBuf); + DMA_SetTransCnt(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel, u32Length); + DMA_SetTriggerSrc(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel,spi_dma->dma_rx->trigger_evt_src); + DMA_ChannelCmd(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel, Enable); + } + else if (RT_NULL == pvRxBuf) + { + DMA_SetSrcAddr(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel, (uint32_t)pvTxBuf); + DMA_SetTransCnt(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel, u32Length); + DMA_SetTriggerSrc(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel,spi_dma->dma_tx->trigger_evt_src); + DMA_ChannelCmd(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel, Enable); + } + else + { + DMA_SetDestAddr(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel, (uint32_t)pvRxBuf); + DMA_SetTransCnt(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel, u32Length); + DMA_SetTriggerSrc(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel,spi_dma->dma_rx->trigger_evt_src); + + DMA_SetSrcAddr(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel, (uint32_t)pvTxBuf); + DMA_SetTransCnt(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel, u32Length); + DMA_SetTriggerSrc(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel,spi_dma->dma_tx->trigger_evt_src); + + DMA_ChannelCmd(spi_dma->dma_tx->Instance, spi_dma->dma_tx->channel, Enable); + DMA_ChannelCmd(spi_dma->dma_rx->Instance, spi_dma->dma_rx->channel, Enable); + } + + SPI_FunctionCmd(spi_dma->Instance, Enable); + + return RT_EOK; +} + +static struct rt_spi_ops hc32_spi_ops = +{ + .configure = hc32_spi_configure, + .xfer = hc32_spi_xfer, +}; + +static rt_err_t hc32_spi_configure(struct rt_spi_device *device, + struct rt_spi_configuration *configuration) +{ + RT_ASSERT(device != RT_NULL); + RT_ASSERT(configuration != RT_NULL); + + struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); + spi_drv->cfg = configuration; + return hc32_spi_init(spi_drv, configuration); +} + +static rt_uint32_t hc32_spi_xfer(struct rt_spi_device *device, struct rt_spi_message *message) +{ + rt_uint8_t state; + rt_size_t message_length, already_send_length; + rt_uint16_t send_length; + rt_uint8_t *recv_buf; + const rt_uint8_t *send_buf; + + RT_ASSERT(device != RT_NULL); + RT_ASSERT(device->bus != RT_NULL); + RT_ASSERT(device->bus->parent.user_data != RT_NULL); + RT_ASSERT(message != RT_NULL); + + struct hc32_spi *spi_drv = rt_container_of(device->bus, struct hc32_spi, spi_bus); + SPI_HandleType *spi_handle = &spi_drv->handle; + struct hc32_hw_spi_cs *cs = device->parent.user_data; + + if (message->cs_take) + { + GPIO_ResetPins(cs->port, cs->pin); + } + message_length = message->length; + recv_buf = message->recv_buf; + send_buf = message->send_buf; + while (message_length) + { + if (message_length > 65535) + { + send_length = 65535; + message_length = message_length - 65535; + } + else + { + send_length = message_length; + message_length = 0; + } + + /* calculate the start address */ + already_send_length = message->length - send_length - message_length; + send_buf = (rt_uint8_t *)message->send_buf + already_send_length; + recv_buf = (rt_uint8_t *)message->recv_buf + already_send_length; + + if(message->send_buf && message->recv_buf) + { + if ((spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) && (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX)) + { + state = hc32_spi_dma(spi_drv->config, send_buf, recv_buf, send_length); + } + else + { + SPI_FunctionCmd(spi_handle->Instance, Enable); + state = SPI_TransmitReceive(spi_handle->Instance, send_buf, recv_buf, send_length); + } + } + else if(message->send_buf) + { + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_TX) + { + state = hc32_spi_dma(spi_drv->config, send_buf, RT_NULL, send_length); + } + else + { + SPI_FunctionCmd(spi_handle->Instance, Enable); + state = SPI_Transmit(spi_handle->Instance, send_buf, send_length); + } + if (message->cs_release && (device->config.mode & RT_SPI_3WIRE)) + { + SPI_FunctionCmd(spi_handle->Instance, Disable); + } + } + else + { + rt_memset((uint8_t *)recv_buf, 0xff, send_length); + if (spi_drv->spi_dma_flag & RT_DEVICE_FLAG_DMA_RX) + { + state = hc32_spi_dma(spi_drv->config, RT_NULL, recv_buf, send_length); + } + else + { + SPI_FunctionCmd(spi_handle->Instance, Enable); + state = SPI_Receive(spi_handle->Instance, recv_buf, send_length); + } + } + if(state != RT_EOK) + { + message->length = 0; + } + /* wait spi transfer complete */ + while(Reset != SPI_GetStatus(spi_handle->Instance, SPI_FLAG_IDLE)); + } + + if (message->cs_release) + { + GPIO_SetPins(cs->port, cs->pin); + } + + return message->length; +} + +/** + * Attach the spi device to SPI bus, this function must be used after initialization. + */ +rt_err_t hc32_hw_spi_device_attach(const char *bus_name, + const char *device_name, + uint8_t cs_gpio_port, + uint16_t cs_gpio_pin) +{ + RT_ASSERT(bus_name != RT_NULL); + RT_ASSERT(device_name != RT_NULL); + + rt_err_t result; + struct rt_spi_device *spi_device; + struct hc32_hw_spi_cs *cs_pin; + stc_gpio_init_t stcGpioInit; + + GPIO_StructInit(&stcGpioInit); + stcGpioInit.u16PinState = PIN_STATE_SET; + stcGpioInit.u16PinDir = PIN_DIR_OUT; + stcGpioInit.u16PullUp = PIN_PU_ON; + stcGpioInit.u16PinDrv = PIN_DRV_HIGH; + GPIO_Init(SPI1_NSS_PORT, SPI1_NSS_PIN, &stcGpioInit); + + /* attach the device to spi bus*/ + spi_device = (struct rt_spi_device *)rt_malloc(sizeof(struct rt_spi_device)); + RT_ASSERT(spi_device != RT_NULL); + cs_pin = (struct hc32_hw_spi_cs *)rt_malloc(sizeof(struct hc32_hw_spi_cs)); + RT_ASSERT(cs_pin != RT_NULL); + cs_pin->port = cs_gpio_port; + cs_pin->pin = cs_gpio_pin; + result = rt_spi_bus_attach_device(spi_device, device_name, bus_name, (void *)cs_pin); + + return result; +} + +static int hc32_hw_spi_bus_init(void) +{ + rt_err_t result; + + for (int i = 0; i < sizeof(spi_config) / sizeof(spi_config[0]); i++) + { + spi_bus_obj[i].config = &spi_config[i]; + spi_bus_obj[i].spi_bus.parent.user_data = &spi_config[i]; + spi_bus_obj[i].handle.Instance = spi_config[i].Instance; + result = rt_spi_bus_register(&spi_bus_obj[i].spi_bus, spi_config[i].bus_name, &hc32_spi_ops); + } + return result; +} + +/** + * @brief Clear DMA transfer complete flag. + * @param dma specific dam witch spi used. + * @retval None + */ +static void hc32_dma_irq_handle(struct dma_config *dma) +{ + dma->Instance->INTCLR1 |= (1u << dma->channel); +} + + +#if defined(BSP_USING_SPI1) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi1_rx_dma_irq_handle(void) +{ + #if defined(BSP_SPI1_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI1_INDEX].dma_rx); + SPI_FunctionCmd(spi_config[SPI1_INDEX].Instance, Disable); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI1_RX_USING_DMA */ +} + +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi1_tx_dma_irq_handle(void) +{ + #if defined(BSP_SPI1_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI1_INDEX].dma_tx); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI1_TX_USING_DMA */ +} +#endif /* BSP_USING_SPI1 */ + +#if defined(BSP_USING_SPI2) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi2_rx_dma_irq_handle(void) +{ + #if defined(BSP_SPI2_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI2_INDEX].dma_rx); + SPI_FunctionCmd(spi_config[SPI2_INDEX].Instance, Disable); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI2_RX_USING_DMA */ +} + +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi2_tx_dma_irq_handle(void) +{ + #if defined(BSP_SPI2_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI2_INDEX].dma_tx); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI2_TX_USING_DMA */ +} +#endif /* BSP_USING_SPI2 */ + +#if defined(BSP_USING_SPI3) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi3_rx_dma_irq_handle(void) +{ + #if defined(BSP_SPI3_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI3_INDEX].dma_rx); + SPI_FunctionCmd(spi_config[SPI3_INDEX].Instance, Disable); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI3_RX_USING_DMA */ +} + +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi3_tx_dma_irq_handle(void) +{ + #if defined(BSP_SPI3_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI3_INDEX].dma_tx); + + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI3_TX_USING_DMA */ +} +#endif /* BSP_USING_SPI3 */ + +#if defined(BSP_USING_SPI4) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi4_rx_dma_irq_handle(void) +{ + #if defined(BSP_SPI4_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI4_INDEX].dma_rx); + SPI_FunctionCmd(spi_config[SPI4_INDEX].Instance, Disable); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI4_RX_USING_DMA */ +} + +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi4_tx_dma_irq_handle(void) +{ + #if defined(BSP_SPI4_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI4_INDEX].dma_tx); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI4_TX_USING_DMA */ +} +#endif /* BSP_USING_SPI4 */ + +#if defined(BSP_USING_SPI5) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi5_rx_dma_irq_handle(void) +{ + #if defined(BSP_SPI5_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI5_INDEX].dma_rx); + SPI_FunctionCmd(spi_config[SPI5_INDEX].Instance, Disable); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI5_RX_USING_DMA */ +} + +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi5_tx_dma_irq_handle(void) +{ + #if defined(BSP_SPI5_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI5_INDEX].dma_tx); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI5_TX_USING_DMA */ +} +#endif /* BSP_USING_SPI5 */ + +#if defined(BSP_USING_SPI6) +/** + * @brief This function handles DMA Rx complete interrupt request. + * @param None + * @retval None + */ +static void spi6_rx_dma_irq_handle(void) +{ + #if defined(BSP_SPI6_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI6_INDEX].dma_rx); + SPI_FunctionCmd(spi_config[SPI6_INDEX].Instance, Disable); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI6_RX_USING_DMA */ +} + +/** + * @brief This function handles DMA Tx complete interrupt request. + * @param None + * @retval None + */ +static void spi6_tx_dma_irq_handle(void) +{ + #if defined(BSP_SPI6_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_dma_irq_handle(spi_config[SPI6_INDEX].dma_tx); + + /* leave interrupt */ + rt_interrupt_leave(); + #endif /* BSP_SPI6_TX_USING_DMA */ +} +#endif /* BSP_USING_SPI6 */ + +/** + * @brief This function gets dma witch spi used infomation include unit, + * channel, interrupt etc. + * @param None + * @retval None + */ +static void hc32_get_dma_info(void) +{ +#ifdef BSP_SPI1_RX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi1_dma_rx = SPI1_RX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_rx = &spi1_dma_rx; +#endif +#ifdef BSP_SPI1_TX_USING_DMA + spi_bus_obj[SPI1_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi1_dma_tx = SPI1_TX_DMA_CONFIG; + spi_config[SPI1_INDEX].dma_tx = &spi1_dma_tx; +#endif + +#ifdef BSP_SPI2_RX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi2_dma_rx = SPI2_RX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_rx = &spi2_dma_rx; +#endif +#ifdef BSP_SPI2_TX_USING_DMA + spi_bus_obj[SPI2_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi2_dma_tx = SPI2_TX_DMA_CONFIG; + spi_config[SPI2_INDEX].dma_tx = &spi2_dma_tx; +#endif + +#ifdef BSP_SPI3_RX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi3_dma_rx = SPI3_RX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_rx = &spi3_dma_rx; +#endif +#ifdef BSP_SPI3_TX_USING_DMA + spi_bus_obj[SPI3_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi3_dma_tx = SPI3_TX_DMA_CONFIG; + spi_config[SPI3_INDEX].dma_tx = &spi3_dma_tx; +#endif + +#ifdef BSP_SPI4_RX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi4_dma_rx = SPI4_RX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_rx = &spi4_dma_rx; +#endif +#ifdef BSP_SPI4_TX_USING_DMA + spi_bus_obj[SPI4_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi4_dma_tx = SPI4_TX_DMA_CONFIG; + spi_config[SPI4_INDEX].dma_tx = &spi4_dma_tx; +#endif + +#ifdef BSP_SPI5_RX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi5_dma_rx = SPI5_RX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_rx = &spi5_dma_rx; +#endif +#ifdef BSP_SPI5_TX_USING_DMA + spi_bus_obj[SPI5_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi5_dma_tx = SPI5_TX_DMA_CONFIG; + spi_config[SPI5_INDEX].dma_tx = &spi5_dma_tx; +#endif + +#ifdef BSP_SPI6_RX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + static struct dma_config spi6_dma_rx = SPI6_RX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_rx = &spi6_dma_rx; +#endif +#ifdef BSP_SPI6_TX_USING_DMA + spi_bus_obj[SPI6_INDEX].spi_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + static struct dma_config spi6_dma_tx = SPI6_TX_DMA_CONFIG; + spi_config[SPI6_INDEX].dma_tx = &spi6_dma_tx; +#endif +} + +int hc32_hw_spi_init(void) +{ + hc32_get_dma_info(); + return hc32_hw_spi_bus_init(); +} + +INIT_BOARD_EXPORT(hc32_hw_spi_init); + +#endif /* BSP_USING_SPI */ diff --git a/bsp/hc32f4a0/drivers/drv_spi.h b/bsp/hc32f4a0/drivers/drv_spi.h new file mode 100644 index 0000000000000000000000000000000000000000..64583252221c3ecd3d1a36cebdb6317362d8fcd0 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_spi.h @@ -0,0 +1,377 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __DRV_SPI_H__ +#define __DRV_SPI_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" +#include "drv_dma.h" +#include "board_config.h" + +#ifdef __cplusplus +extern "C" { +#endif + +#ifdef BSP_USING_SPI1 +#define SPI1_BUS_NAME "spi1" +#define SPI1_BUS_MUTEX_NAME "spi1_bus_mutex" +#endif +#ifdef BSP_USING_SPI2 +#define SPI2_BUS_NAME "spi2" +#define SPI2_BUS_MUTEX_NAME "spi2_bus_mutex" +#endif +#ifdef BSP_USING_SPI3 +#define SPI3_BUS_NAME "spi3" +#define SPI3_BUS_MUTEX_NAME "spi3_bus_mutex" +#endif +#ifdef BSP_USING_SPI4 +#define SPI4_BUS_NAME "spi4" +#define SPI4_BUS_MUTEX_NAME "spi4_bus_mutex" +#endif +#ifdef BSP_USING_SPI5 +#define SPI4_BUS_NAME "spi5" +#define SPI4_BUS_MUTEX_NAME "spi5_bus_mutex" +#endif +#ifdef BSP_USING_SPI6 +#define SPI4_BUS_NAME "spi6" +#define SPI4_BUS_MUTEX_NAME "spi6_bus_mutex" +#endif + +#ifdef BSP_USING_SPI1 +#ifndef SPI1_BUS_CONFIG +#define SPI1_BUS_CONFIG \ + { \ + .Instance = M4_SPI1, \ + .bus_name = SPI1_BUS_NAME, \ + } +#endif /* SPI1_BUS_CONFIG */ +#endif /* BSP_USING_SPI1 */ + +#ifdef BSP_SPI1_TX_USING_DMA +#ifndef SPI1_TX_DMA_CONFIG +#define SPI1_TX_DMA_CONFIG \ + { \ + .Instance = SPI1_TX_DMA_INSTANCE, \ + .channel = SPI1_TX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI1_SPTI, \ + .irq_config = \ + { \ + .irq = SPI1_TX_DMA_IRQn, \ + .irq_prio = SPI1_TX_DMA_INT_PRIO, \ + .int_src = SPI1_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_TX_DMA_CONFIG */ +#endif /* BSP_SPI1_TX_USING_DMA */ + +#ifdef BSP_SPI1_RX_USING_DMA +#ifndef SPI1_RX_DMA_CONFIG +#define SPI1_RX_DMA_CONFIG \ + { \ + .Instance = SPI1_RX_DMA_INSTANCE, \ + .channel = SPI1_RX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI1_SPRI, \ + .irq_config = \ + { \ + .irq = SPI1_RX_DMA_IRQn, \ + .irq_prio = SPI1_RX_DMA_INT_PRIO, \ + .int_src = SPI1_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI1_RX_DMA_CONFIG */ +#endif /* BSP_SPI1_RX_USING_DMA */ + +#ifdef BSP_USING_SPI2 +#ifndef SPI2_BUS_CONFIG +#define SPI2_BUS_CONFIG \ + { \ + .Instance = M4_SPI2, \ + .bus_name = SPI2_BUS_NAME, \ + } +#endif /* SPI2_BUS_CONFIG */ +#endif /* BSP_USING_SPI2 */ + +#ifdef BSP_SPI2_TX_USING_DMA +#ifndef SPI2_TX_DMA_CONFIG +#define SPI2_TX_DMA_CONFIG \ + { \ + .Instance = SPI2_TX_DMA_INSTANCE, \ + .channel = SPI2_TX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI2_SPTI, \ + .irq_config = \ + { \ + .irq = SPI2_TX_DMA_IRQn, \ + .irq_prio = SPI2_TX_DMA_INT_PRIO, \ + .int_src = SPI2_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_TX_DMA_CONFIG */ +#endif /* BSP_SPI2_TX_USING_DMA */ + +#ifdef BSP_SPI2_RX_USING_DMA +#ifndef SPI2_RX_DMA_CONFIG +#define SPI2_RX_DMA_CONFIG \ + { \ + .Instance = SPI2_RX_DMA_INSTANCE, \ + .channel = SPI2_RX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI2_SPRI, \ + .irq_config = \ + { \ + .irq = SPI2_RX_DMA_IRQn, \ + .irq_prio = SPI2_RX_DMA_INT_PRIO, \ + .int_src = SPI2_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI2_RX_DMA_CONFIG */ +#endif /* BSP_SPI2_RX_USING_DMA */ + +#ifdef BSP_USING_SPI3 +#ifndef SPI3_BUS_CONFIG +#define SPI3_BUS_CONFIG \ + { \ + .Instance = M4_SPI3, \ + .bus_name = SPI3_BUS_NAME, \ + } +#endif /* SPI3_BUS_CONFIG */ +#endif /* BSP_USING_SPI3 */ + +#ifdef BSP_SPI3_TX_USING_DMA +#ifndef SPI3_TX_DMA_CONFIG +#define SPI3_TX_DMA_CONFIG \ + { \ + .Instance = SPI3_TX_DMA_INSTANCE, \ + .channel = SPI3_TX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI3_SPTI, \ + .irq_config = \ + { \ + .irq = SPI3_TX_DMA_IRQn, \ + .irq_prio = SPI3_TX_DMA_INT_PRIO, \ + .int_src = SPI3_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_TX_DMA_CONFIG */ +#endif /* BSP_SPI3_TX_USING_DMA */ + +#ifdef BSP_SPI3_RX_USING_DMA +#ifndef SPI3_RX_DMA_CONFIG +#define SPI3_RX_DMA_CONFIG \ + { \ + .Instance = SPI3_RX_DMA_INSTANCE, \ + .channel = SPI3_RX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI3_SPRI, \ + .irq_config = \ + { \ + .irq = SPI3_RX_DMA_IRQn, \ + .irq_prio = SPI3_RX_DMA_INT_PRIO, \ + .int_src = SPI3_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI3_RX_DMA_CONFIG */ +#endif /* BSP_SPI3_RX_USING_DMA */ + +#ifdef BSP_USING_SPI4 +#ifndef SPI4_BUS_CONFIG +#define SPI4_BUS_CONFIG \ + { \ + .Instance = M4_SPI4, \ + .bus_name = SPI4_BUS_NAME, \ + } +#endif /* SPI4_BUS_CONFIG */ +#endif /* BSP_USING_SPI4 */ + +#ifdef BSP_SPI4_TX_USING_DMA +#ifndef SPI4_TX_DMA_CONFIG +#define SPI4_TX_DMA_CONFIG \ + { \ + .Instance = SPI4_TX_DMA_INSTANCE, \ + .channel = SPI4_TX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI4_SPTI, \ + .irq_config = \ + { \ + .irq = SPI4_TX_DMA_IRQn, \ + .irq_prio = SPI4_TX_DMA_INT_PRIO, \ + .int_src = SPI4_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_TX_DMA_CONFIG */ +#endif /* BSP_SPI4_TX_USING_DMA */ + +#ifdef BSP_SPI4_RX_USING_DMA +#ifndef SPI4_RX_DMA_CONFIG +#define SPI4_RX_DMA_CONFIG \ + { \ + .Instance = SPI4_RX_DMA_INSTANCE, \ + .channel = SPI4_RX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI4_SPRI, \ + .irq_config = \ + { \ + .irq = SPI4_RX_DMA_IRQn, \ + .irq_prio = SPI4_RX_DMA_INT_PRIO, \ + .int_src = SPI4_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI4_RX_DMA_CONFIG */ +#endif /* BSP_SPI4_RX_USING_DMA */ + +#ifdef BSP_USING_SPI5 +#ifndef SPI5_BUS_CONFIG +#define SPI5_BUS_CONFIG \ + { \ + .Instance = M4_SPI5, \ + .bus_name = SPI5_BUS_NAME, \ + } +#endif /* SPI5_BUS_CONFIG */ +#endif /* BSP_USING_SPI5 */ + +#ifdef BSP_SPI5_TX_USING_DMA +#ifndef SPI5_TX_DMA_CONFIG +#define SPI5_TX_DMA_CONFIG \ + { \ + .Instance = SPI5_TX_DMA_INSTANCE, \ + .channel = SPI5_TX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI5_SPTI, \ + .irq_config = \ + { \ + .irq = SPI5_TX_DMA_IRQn, \ + .irq_prio = SPI5_TX_DMA_INT_PRIO, \ + .int_src = SPI5_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_TX_DMA_CONFIG */ +#endif /* BSP_SPI5_TX_USING_DMA */ + +#ifdef BSP_SPI5_RX_USING_DMA +#ifndef SPI5_RX_DMA_CONFIG +#define SPI5_RX_DMA_CONFIG \ + { \ + .Instance = SPI5_RX_DMA_INSTANCE, \ + .channel = SPI5_RX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI5_SPRI, \ + .irq_config = \ + { \ + .irq = SPI5_RX_DMA_IRQn, \ + .irq_prio = SPI5_RX_DMA_INT_PRIO, \ + .int_src = SPI5_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI5_RX_DMA_CONFIG */ +#endif /* BSP_SPI5_RX_USING_DMA */ + +#ifdef BSP_USING_SPI6 +#ifndef SPI6_BUS_CONFIG +#define SPI6_BUS_CONFIG \ + { \ + .Instance = M4_SPI6, \ + .bus_name = SPI6_BUS_NAME, \ + } +#endif /* SPI6_BUS_CONFIG */ +#endif /* BSP_USING_SPI6 */ + +#ifdef BSP_SPI6_TX_USING_DMA +#ifndef SPI6_TX_DMA_CONFIG +#define SPI6_TX_DMA_CONFIG \ + { \ + .Instance = SPI6_TX_DMA_INSTANCE, \ + .channel = SPI6_TX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI6_SPTI, \ + .irq_config = \ + { \ + .irq = SPI6_TX_DMA_IRQn, \ + .irq_prio = SPI6_TX_DMA_INT_PRIO, \ + .int_src = SPI6_TX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_TX_DMA_CONFIG */ +#endif /* BSP_SPI6_TX_USING_DMA */ + +#ifdef BSP_SPI6_RX_USING_DMA +#ifndef SPI6_RX_DMA_CONFIG +#define SPI6_RX_DMA_CONFIG \ + { \ + .Instance = SPI6_RX_DMA_INSTANCE, \ + .channel = SPI6_RX_DMA_CHANNEL, \ + .trigger_evt_src = EVT_SPI6_SPRI, \ + .irq_config = \ + { \ + .irq = SPI6_RX_DMA_IRQn, \ + .irq_prio = SPI6_RX_DMA_INT_PRIO, \ + .int_src = SPI6_RX_DMA_INT_SRC, \ + } \ + } +#endif /* SPI6_RX_DMA_CONFIG */ +#endif /* BSP_SPI6_RX_USING_DMA */ + +typedef struct __SPI_HandleType +{ + M4_SPI_TypeDef *Instance; /* SPI registers base address */ + stc_spi_init_t Init; /* SPI communication parameters */ +}SPI_HandleType; + +struct hc32_hw_spi_cs +{ + rt_uint8_t port; + rt_uint16_t pin; +}; + +struct hc32_spi_config +{ + M4_SPI_TypeDef *Instance; + char *bus_name; + struct dma_config *dma_rx; + struct dma_config *dma_tx; +}; + +struct stm32_spi_device +{ + rt_uint32_t pin; + char *bus_name; + char *device_name; +}; + +/* HC32 SPI index */ +struct spi_index +{ + rt_uint32_t index; + M4_SPI_TypeDef *Instance; +}; + +struct hc32_spi +{ + struct rt_spi_bus spi_bus; + SPI_HandleType handle; + struct hc32_spi_config *config; + struct rt_spi_configuration *cfg; + rt_uint16_t spi_dma_flag; +}; + +/* HC32 SPI irq handler */ +struct spi_irq_handler +{ + void (*rx_dma_irq_handler)(void); + void (*tx_dma_irq_handler)(void); +}; + +rt_err_t hc32_hw_spi_device_attach(const char *bus_name, + const char *device_name, + uint8_t cs_gpio_port, + uint16_t cs_gpio_pin); + + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_SPI_H__ */ + diff --git a/bsp/hc32f4a0/drivers/drv_usart.c b/bsp/hc32f4a0/drivers/drv_usart.c new file mode 100644 index 0000000000000000000000000000000000000000..b6b75cd281e1506f8a8281c6fb69dfdd47529391 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_usart.c @@ -0,0 +1,1546 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include + +#include "drv_usart.h" +#include "board_config.h" + +#ifdef RT_USING_SERIAL + +#if !defined(BSP_USING_UART1) && !defined(BSP_USING_UART2) && !defined(BSP_USING_UART3) && \ + !defined(BSP_USING_UART4) && !defined(BSP_USING_UART5) && !defined(BSP_USING_UART6) && \ + !defined(BSP_USING_UART7) && !defined(BSP_USING_UART8) && !defined(BSP_USING_UART9) && \ + !defined(BSP_USING_UART10) +#error "Please define at least one BSP_USING_UARTx" +/* UART instance can be selected at menuconfig -> Hardware Drivers Config -> On-chip Peripheral Drivers -> Enable UART */ +#endif + +/******************************************************************************* + * Local type definitions ('typedef') + ******************************************************************************/ +/* HC32 config Rx timeout */ +struct hc32_uart_rxto +{ + M4_TMR0_TypeDef *TMR0_Instance; + rt_uint32_t channel; + + rt_size_t timeout_bits; + + struct hc32_irq_config irq_config; +}; + +/* HC32 config uart class */ +struct hc32_uart_config +{ + struct hc32_irq_config rxerr_irq_config; + + struct hc32_irq_config rx_irq_config; + + struct hc32_irq_config tx_irq_config; + +#ifdef RT_SERIAL_USING_DMA + struct hc32_uart_rxto *rx_timeout; + struct dma_config *dma_rx; + + struct dma_config *dma_tx; +#endif +}; + +/* HC32 UART index */ +struct uart_index +{ + rt_uint32_t index; + M4_USART_TypeDef *Instance; +}; + +/* HC32 UART irq handler */ +struct uart_irq_handler +{ + void (*rxerr_irq_handler)(void); + void (*rx_irq_handler)(void); + void (*tx_irq_handler)(void); + void (*tc_irq_handler)(void); + void (*rxto_irq_handler)(void); + void (*dma_rx_irq_handler)(void); +}; + +/* HC32 uart dirver class */ +struct hc32_uart +{ + struct rt_serial_device serial; + + const char *name; + + M4_USART_TypeDef *Instance; + + struct hc32_uart_config config; + +#ifdef RT_SERIAL_USING_DMA + rt_size_t dma_rx_last_index; +#endif + + rt_uint16_t uart_dma_flag; +}; + +/******************************************************************************* + * Local pre-processor symbols/macros ('#define') + ******************************************************************************/ +#ifndef UART_CONFIG +#define UART_CONFIG(uart_name, USART) \ + { \ + .name = uart_name, \ + .Instance = M4_##USART, \ + .config = { \ + .rxerr_irq_config = { \ + .irq = USART##_RXERR_INT_IRQn, \ + .irq_prio = USART##_RXERR_INT_PRIO, \ + .int_src = INT_##USART##_EI, \ + }, \ + .rx_irq_config = { \ + .irq = USART##_RX_INT_IRQn, \ + .irq_prio = USART##_RX_INT_PRIO, \ + .int_src = INT_##USART##_RI, \ + }, \ + .tx_irq_config = { \ + .irq = USART##_TX_INT_IRQn, \ + .irq_prio = USART##_TX_INT_PRIO, \ + .int_src = INT_##USART##_TI, \ + }, \ + }, \ + } +#endif /* UART_CONFIG */ + +#ifndef UART_RXTO_CONFIG +#define UART_RXTO_CONFIG(USART) \ + { \ + .TMR0_Instance = USART##_RXTO_TMR0_UNIT, \ + .channel = USART##_RXTO_TMR0_CH, \ + .timeout_bits = 20UL, \ + .irq_config = { \ + .irq = USART##_RXTO_INT_IRQn, \ + .irq_prio = USART##_RXTO_INT_PRIO, \ + .int_src = INT_##USART##_RTO, \ + } \ + } +#endif /* UART_RXTO_CONFIG */ + +#ifndef UART_DMA_RX_CONFIG +#define UART_DMA_RX_CONFIG(USART) \ + { \ + .Instance = USART##_RX_DMA_UNIT, \ + .channel = USART##_RX_DMA_CH, \ + .trigger_evt_src = EVT_##USART##_RI, \ + .irq_config = { \ + .irq = USART##_RX_DMA_INT_IRQn, \ + .irq_prio = USART##_RX_DMA_INT_PRIO, \ + .int_src = USART##_RX_DMA_INT_SRC, \ + } \ + } +#endif /* UART_DMA_RX_CONFIG */ + +#ifndef UART_DMA_TX_CONFIG +#define UART_DMA_TX_CONFIG(USART) \ + { \ + .Instance = USART##_TX_DMA_UNIT, \ + .channel = USART##_TX_DMA_CH, \ + .trigger_evt_src = EVT_##USART##_TI, \ + .irq_config = { \ + .irq = USART##_TC_INT_IRQn, \ + .irq_prio = USART##_TC_INT_PRIO, \ + .int_src = INT_##USART##_TCI, \ + } \ + } +#endif /* UART_DMA_TX_CONFIG */ + +#define DMA_CH_REG(reg_base, ch) \ + (*(uint32_t *)((uint32_t)(&(reg_base)) + ((ch) * 0x40UL))) + +#define DMA_TRANS_CNT(unit, ch) \ + (READ_REG32(DMA_CH_REG((unit)->MONDTCTL0, (ch))) >> DMA_DTCTL_CNT_POS) + +#define USART_TCI_ENABLE(unit) \ + SET_REG32_BIT(unit->CR1, USART_INT_TC) + +/******************************************************************************* + * Global variable definitions (declared in header file with 'extern') + ******************************************************************************/ + +/******************************************************************************* + * Local function prototypes ('static') + ******************************************************************************/ +#ifdef RT_SERIAL_USING_DMA +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag); +#endif + +/******************************************************************************* + * Local variable definitions ('static') + ******************************************************************************/ +enum +{ +#ifdef BSP_USING_UART1 + UART1_INDEX, +#endif +#ifdef BSP_USING_UART2 + UART2_INDEX, +#endif +#ifdef BSP_USING_UART3 + UART3_INDEX, +#endif +#ifdef BSP_USING_UART4 + UART4_INDEX, +#endif +#ifdef BSP_USING_UART5 + UART5_INDEX, +#endif +#ifdef BSP_USING_UART6 + UART6_INDEX, +#endif +#ifdef BSP_USING_UART7 + UART7_INDEX, +#endif +#ifdef BSP_USING_UART8 + UART8_INDEX, +#endif +#ifdef BSP_USING_UART9 + UART9_INDEX, +#endif +#ifdef BSP_USING_UART10 + UART10_INDEX, +#endif + UART_INDEX_MAX, +}; + +static const struct uart_index uart_map[] = +{ +#ifdef BSP_USING_UART1 + {UART1_INDEX, M4_USART1}, +#endif +#ifdef BSP_USING_UART2 + {UART2_INDEX, M4_USART2}, +#endif +#ifdef BSP_USING_UART3 + {UART3_INDEX, M4_USART3}, +#endif +#ifdef BSP_USING_UART4 + {UART4_INDEX, M4_USART4}, +#endif +#ifdef BSP_USING_UART5 + {UART5_INDEX, M4_USART5}, +#endif +#ifdef BSP_USING_UART6 + {UART6_INDEX, M4_USART6}, +#endif +#ifdef BSP_USING_UART7 + {UART7_INDEX, M4_USART7}, +#endif +#ifdef BSP_USING_UART8 + {UART8_INDEX, M4_USART8}, +#endif +#ifdef BSP_USING_UART9 + {UART9_INDEX, M4_USART9}, +#endif +#ifdef BSP_USING_UART10 + {UART10_INDEX, M4_USART10}, +#endif +}; + +static struct hc32_uart uart_obj[] = +{ +#ifdef BSP_USING_UART1 + UART_CONFIG("uart1", USART1), +#endif +#ifdef BSP_USING_UART2 + UART_CONFIG("uart2", USART2), +#endif +#ifdef BSP_USING_UART3 + UART_CONFIG("uart3", USART3), +#endif +#ifdef BSP_USING_UART4 + UART_CONFIG("uart4", USART4), +#endif +#ifdef BSP_USING_UART5 + UART_CONFIG("uart5", USART5), +#endif +#ifdef BSP_USING_UART6 + UART_CONFIG("uart6", USART6), +#endif +#ifdef BSP_USING_UART7 + UART_CONFIG("uart7", USART7), +#endif +#ifdef BSP_USING_UART8 + UART_CONFIG("uart8", USART8), +#endif +#ifdef BSP_USING_UART9 + UART_CONFIG("uart9", USART9), +#endif +#ifdef BSP_USING_UART10 + UART_CONFIG("uart10", USART10), +#endif +}; + +static const struct uart_irq_handler uart_irq_handlers[sizeof(uart_obj) / sizeof(uart_obj[0])]; + +/******************************************************************************* + * Function implementation - global ('extern') and local ('static') + ******************************************************************************/ + +static uint32_t hc32_get_uart_index(M4_USART_TypeDef *Instance) +{ + uint32_t index = UART_INDEX_MAX; + + for (uint8_t i = 0U; i < ARRAY_SZ(uart_map); i++) + { + if (uart_map[i].Instance == Instance) + { + index = uart_map[i].index; + RT_ASSERT(index < UART_INDEX_MAX) + break; + } + } + + return index; +} + +static uint32_t hc32_get_usart_fcg(M4_USART_TypeDef *Instance) +{ + return (PWC_FCG3_USART1 << hc32_get_uart_index(Instance)); +} + +static rt_err_t hc32_configure(struct rt_serial_device *serial, + struct serial_configure *cfg) +{ + struct hc32_uart *uart; + stc_usart_uart_init_t uart_init; + + RT_ASSERT(RT_NULL != cfg); + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + /* Configure USART initialization structure */ + USART_UartStructInit(&uart_init); + uart_init.u32OversamplingBits = USART_OVERSAMPLING_8BIT; + uart_init.u32Baudrate = cfg->baud_rate; + if ((M4_USART1 == uart->Instance) || \ + (M4_USART2 == uart->Instance) || \ + (M4_USART6 == uart->Instance) || \ + (M4_USART7 == uart->Instance)) + { + uart_init.u32ClkMode = USART_INTERNCLK_OUTPUT; + } + + if(BIT_ORDER_LSB == cfg->bit_order) + { + uart_init.u32BitDirection = USART_LSB; + } + else + { + uart_init.u32BitDirection = USART_MSB; + } + + switch(cfg->stop_bits) + { + case STOP_BITS_1: + uart_init.u32StopBit = USART_STOPBIT_1BIT; + break; + case STOP_BITS_2: + uart_init.u32StopBit = USART_STOPBIT_2BIT; + break; + default: + uart_init.u32StopBit = USART_STOPBIT_1BIT; + break; + } + + switch(cfg->parity) + { + case PARITY_NONE: + uart_init.u32Parity = USART_PARITY_NONE; + break; + case PARITY_EVEN: + uart_init.u32Parity = USART_PARITY_EVEN; + break; + case PARITY_ODD: + uart_init.u32Parity = USART_PARITY_ODD; + break; + default: + uart_init.u32Parity = USART_PARITY_NONE; + break; + } + + switch(cfg->data_bits) + { + case DATA_BITS_8: + uart_init.u32DataWidth = USART_DATA_LENGTH_8BIT; + break; + default: + return -RT_ERROR; + } + + /* Enable USART clock */ + PWC_Fcg3PeriphClockCmd(hc32_get_usart_fcg(uart->Instance), Enable); + + rt_err_t rt_hw_board_uart_init(M4_USART_TypeDef *USARTx); + if (RT_EOK != rt_hw_board_uart_init(uart->Instance)) + { + return -RT_ERROR; + } + + USART_DeInit(uart->Instance); + if (Error == USART_UartInit(uart->Instance, &uart_init)) + { + return -RT_ERROR; + } + + /* Register RX error interrupt */ + hc32_install_irq_handler(&uart->config.rxerr_irq_config, + uart_irq_handlers[hc32_get_uart_index(uart->Instance)].rxerr_irq_handler, + RT_TRUE); + + USART_FuncCmd(uart->Instance, USART_INT_RX, Enable); + + if ((serial->parent.flag & RT_DEVICE_FLAG_RDWR) || \ + (serial->parent.flag & RT_DEVICE_FLAG_RDONLY)) + { + USART_FuncCmd(uart->Instance, USART_RX, Enable); + } + + if ((serial->parent.flag & RT_DEVICE_FLAG_RDWR) || \ + (serial->parent.flag & RT_DEVICE_FLAG_WRONLY)) + { + USART_FuncCmd(uart->Instance, USART_TX, Enable); + } + + return RT_EOK; +} + +static rt_err_t hc32_control(struct rt_serial_device *serial, int cmd, void *arg) +{ + struct hc32_uart *uart; + uint32_t uart_index; +#ifdef RT_SERIAL_USING_DMA + rt_ubase_t ctrl_arg = (rt_ubase_t)arg; +#endif + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + switch (cmd) + { + /* Disable interrupt */ + case RT_DEVICE_CTRL_CLR_INT: + if(RT_DEVICE_FLAG_INT_RX == ctrl_arg) + { + /* Disable RX irq */ + NVIC_DisableIRQ(uart->config.rx_irq_config.irq); + INTC_IrqSignOut(uart->config.rx_irq_config.irq); + } + else + { + /* Disable TX irq */ + NVIC_DisableIRQ(uart->config.tx_irq_config.irq); + USART_FuncCmd(uart->Instance, USART_INT_TC, Disable); + INTC_IrqSignOut(uart->config.tx_irq_config.irq); + } + break; + + /* Enable interrupt */ + case RT_DEVICE_CTRL_SET_INT: + uart_index = hc32_get_uart_index(uart->Instance); + + if(RT_DEVICE_FLAG_INT_RX == ctrl_arg) + { + /* Install RX irq handler */ + hc32_install_irq_handler(&uart->config.rx_irq_config, + uart_irq_handlers[uart_index].rx_irq_handler, + RT_TRUE); + } + else + { + /* Enable TX interrupt */ + USART_FuncCmd(uart->Instance, USART_INT_TXE, Enable); + + /* Install TX irq handler */ + hc32_install_irq_handler(&uart->config.tx_irq_config, + uart_irq_handlers[uart_index].tx_irq_handler, + RT_TRUE); + } + break; + +#ifdef RT_SERIAL_USING_DMA + case RT_DEVICE_CTRL_CONFIG: + hc32_dma_config(serial, ctrl_arg); + + if (RT_DEVICE_FLAG_DMA_TX == ctrl_arg) + { + USART_FuncCmd(uart->Instance, (USART_TX | USART_INT_TC), Disable); + + /* Install TC irq handler */ + uart_index = hc32_get_uart_index(uart->Instance); + hc32_install_irq_handler(&uart->config.dma_tx->irq_config, + uart_irq_handlers[uart_index].tc_irq_handler, + RT_TRUE); + } + break; +#endif + + case RT_DEVICE_CTRL_CLOSE: + USART_DeInit(uart->Instance); + break; + } + + return RT_EOK; +} + +static int hc32_putc(struct rt_serial_device *serial, char c) +{ + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + if(serial->parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + if (USART_GetStatus(uart->Instance, USART_FLAG_TXE) != Set) + { + return -1; + } + } + else + { + /* Polling mode. */ + while (USART_GetStatus(uart->Instance, USART_FLAG_TXE) != Set); + } + + USART_SendData(uart->Instance, c); + + return 1; +} + +static int hc32_getc(struct rt_serial_device *serial) +{ + int ch= -1; + struct hc32_uart *uart; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + if(Set == USART_GetStatus(uart->Instance, USART_FLAG_RXNE)) + { + ch = (rt_uint8_t)USART_RecData(uart->Instance); + } + + return ch; +} + +static rt_size_t hc32_dma_transmit(struct rt_serial_device *serial, + rt_uint8_t *buf, + rt_size_t size, + int direction) +{ + struct hc32_uart *uart; + M4_DMA_TypeDef *DMA_Instance; + uint8_t ch; + + RT_ASSERT(RT_NULL != serial); + RT_ASSERT(RT_NULL != buf); + + if (size == 0) + { + return 0; + } + + uart = rt_container_of(serial, struct hc32_uart, serial); + + if (RT_SERIAL_DMA_TX == direction) + { + DMA_Instance = uart->config.dma_tx->Instance; + ch = uart->config.dma_tx->channel; + + if (Reset == USART_GetStatus(uart->Instance, USART_FLAG_TC)) + { + RT_ASSERT(0); + } + + DMA_SetSrcAddr(DMA_Instance, ch, (uint32_t)buf); + DMA_SetTransCnt(DMA_Instance, ch, size); + DMA_ChannelCmd(DMA_Instance, ch, Enable); + + USART_FuncCmd(uart->Instance, USART_TX, Enable); + USART_TCI_ENABLE(uart->Instance); + return size; + } + return 0; +} + +static void hc32_uart_rx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_IND); +} + +static void hc32_uart_tx_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + + if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_INT_TX) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DONE); + } +} + +static void hc32_uart_rxerr_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->Instance); + + if (Set == USART_GetStatus(uart->Instance, (USART_FLAG_PE | USART_FLAG_FE))) + { + USART_RecData(uart->Instance); + } + + USART_ClearStatus(uart->Instance, (USART_CLEAR_FLAG_PE | \ + USART_CLEAR_FLAG_FE | \ + USART_CLEAR_FLAG_ORE)); +} + +#ifdef RT_SERIAL_USING_DMA +static void hc32_uart_rx_timeout(struct rt_serial_device *serial) +{ + struct hc32_uart *uart; + uint32_t cmp_val; + uint32_t timeout_bits; + M4_TMR0_TypeDef* TMR0_Instance; + uint8_t ch; + stc_tmr0_init_t stcTmr0Init; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + TMR0_Instance = uart->config.rx_timeout->TMR0_Instance; + ch = uart->config.rx_timeout->channel; + timeout_bits = uart->config.rx_timeout->timeout_bits; + + if ((M4_USART1 == uart->Instance) || (M4_USART6 == uart->Instance)) + { + RT_ASSERT(TMR0_CH_A == ch); + } + else if ((M4_USART2 == uart->Instance) || (M4_USART7 == uart->Instance)) + { + RT_ASSERT(TMR0_CH_B == ch); + } + + if ((M4_USART1 == uart->Instance) || (M4_USART2 == uart->Instance)) + { + RT_ASSERT(M4_TMR0_1 == TMR0_Instance); + PWC_Fcg2PeriphClockCmd(PWC_FCG2_TMR0_1, Enable); + } + else if ((M4_USART6 == uart->Instance) || (M4_USART7 == uart->Instance)) + { + RT_ASSERT(M4_TMR0_2 == TMR0_Instance); + PWC_Fcg2PeriphClockCmd(PWC_FCG2_TMR0_2, Enable); + } + + /* De-initialize TMR0 */ + TMR0_DeInit(TMR0_Instance); + + /* Clear CNTAR register */ + TMR0_SetCntVal(TMR0_Instance, ch, 0U); + + /* TIMER0 basetimer function initialize */ + TMR0_StructInit(&stcTmr0Init); + stcTmr0Init.u32ClockDivision = TMR0_CLK_DIV1; + stcTmr0Init.u32ClockSource = TMR0_CLK_SRC_XTAL32; + stcTmr0Init.u32HwTrigFunc = (TMR0_BT_HWTRG_FUNC_START | TMR0_BT_HWTRG_FUNC_CLEAR); + if (TMR0_CLK_DIV1 == stcTmr0Init.u32ClockDivision) + { + cmp_val = (timeout_bits - 4UL); + } + else if (TMR0_CLK_DIV2 == stcTmr0Init.u32ClockDivision) + { + cmp_val = (timeout_bits/2UL - 2UL); + } + else + { + cmp_val = (timeout_bits / (1UL << (stcTmr0Init.u32ClockDivision >> TMR0_BCONR_CKDIVA_POS)) - 1UL); + } + DDL_ASSERT(cmp_val <= 0xFFFFUL); + stcTmr0Init.u16CmpValue = (uint16_t)(cmp_val); + TMR0_Init(TMR0_Instance, ch, &stcTmr0Init); + + /* Clear compare flag */ + TMR0_ClearStatus(TMR0_Instance, ch); + + /* Register RTO interrupt */ + hc32_install_irq_handler(&uart->config.rx_timeout->irq_config, + uart_irq_handlers[hc32_get_uart_index(uart->Instance)].rxto_irq_handler, + RT_TRUE); + + USART_ClearStatus(uart->Instance, USART_CLEAR_FLAG_RTOF); + USART_FuncCmd(uart->Instance, (USART_RTO | USART_INT_RTO), Enable); +} + +static void hc32_dma_config(struct rt_serial_device *serial, rt_ubase_t flag) +{ + struct hc32_uart *uart; + stc_dma_init_t dma_init; + M4_DMA_TypeDef *DMA_Instance; + uint32_t DMA_ch; + uint32_t u32Fcg0Periph = PWC_FCG0_AOS; + + RT_ASSERT(RT_NULL != serial); + + uart = rt_container_of(serial, struct hc32_uart, serial); + RT_ASSERT(RT_NULL != uart->Instance); + + if (RT_DEVICE_FLAG_DMA_RX == flag) + { + stc_dma_llp_init_t llp_init; + struct rt_serial_rx_fifo *rx_fifo = (struct rt_serial_rx_fifo *)serial->serial_rx; + + RT_ASSERT(RT_NULL != uart->config.rx_timeout->TMR0_Instance); + RT_ASSERT(RT_NULL != uart->config.dma_rx->Instance); + + /* Initialization uart rx timeout for DMA */ + hc32_uart_rx_timeout(serial); + + uart->dma_rx_last_index = 0UL; + + /* Get DMA unit&channel */ + DMA_Instance = uart->config.dma_rx->Instance; + DMA_ch = uart->config.dma_rx->channel; + + /* Enable DMA clock */ + u32Fcg0Periph |= (M4_DMA1 == DMA_Instance) ? PWC_FCG0_DMA1:PWC_FCG0_DMA2; + PWC_Fcg0PeriphClockCmd(u32Fcg0Periph, Enable); + + /* Disable DMA */ + DMA_ChannelCmd(DMA_Instance, DMA_ch, Disable); + + /* Initialize DMA */ + DMA_StructInit(&dma_init); + dma_init.u32IntEn = DMA_INT_ENABLE; + dma_init.u32SrcAddr = ((uint32_t)(&uart->Instance->DR) + 2UL); + dma_init.u32DestAddr = (uint32_t)rx_fifo->buffer; + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCnt = serial->config.bufsz; + dma_init.u32SrcInc = DMA_SRC_ADDR_FIX; + dma_init.u32DestInc = DMA_DEST_ADDR_INC; + DMA_Init(DMA_Instance, DMA_ch, &dma_init); + + /* Initialize LLP */ + static stc_dma_llp_descriptor_t llp_desc; + llp_init.u32LlpEn = DMA_LLP_ENABLE; + llp_init.u32LlpRun = DMA_LLP_WAIT; + llp_init.u32LlpAddr= (uint32_t)&llp_desc; + DMA_LlpInit(DMA_Instance, DMA_ch, &llp_init); + + /* Configure LLP descriptor */ + llp_desc.SARx = dma_init.u32SrcAddr; + llp_desc.DARx = dma_init.u32DestAddr; + llp_desc.DTCTLx= (dma_init.u32TransCnt << DMA_DTCTL_CNT_POS) | (dma_init.u32BlockSize << DMA_DTCTL_BLKSIZE_POS); + llp_desc.LLPx = (uint32_t)&llp_desc; + llp_desc.CHCTLx= (dma_init.u32SrcInc | dma_init.u32DestInc | dma_init.u32DataWidth | \ + llp_init.u32LlpEn | llp_init.u32LlpRun | dma_init.u32IntEn); + + /* Register DMA interrupt */ + hc32_install_irq_handler(&uart->config.dma_rx->irq_config, + uart_irq_handlers[hc32_get_uart_index(uart->Instance)].dma_rx_irq_handler, + RT_TRUE); + + /* Enable DMA module */ + DMA_Cmd(DMA_Instance, Enable); + DMA_TransIntCmd(DMA_Instance, (DMA_TC_INT_CH0 << DMA_ch), Enable); + DMA_SetTriggerSrc(DMA_Instance, DMA_ch, uart->config.dma_rx->trigger_evt_src); + DMA_ChannelCmd(DMA_Instance, DMA_ch, Enable); + } + else if (RT_DEVICE_FLAG_DMA_TX == flag) + { + RT_ASSERT(RT_NULL != uart->config.dma_tx->Instance); + + DMA_Instance = uart->config.dma_tx->Instance; + DMA_ch = uart->config.dma_tx->channel; + + /* Enable DMA clock */ + u32Fcg0Periph |= (M4_DMA1 == DMA_Instance) ? PWC_FCG0_DMA1:PWC_FCG0_DMA2; + PWC_Fcg0PeriphClockCmd(u32Fcg0Periph, Enable); + + /* Disable DMA */ + DMA_ChannelCmd(DMA_Instance, DMA_ch, Disable); + + /* Initialize DMA */ + DMA_StructInit(&dma_init); + dma_init.u32IntEn = DMA_INT_DISABLE; + dma_init.u32SrcAddr = 0UL; + dma_init.u32DestAddr = (uint32_t)(&uart->Instance->DR); + dma_init.u32DataWidth = DMA_DATAWIDTH_8BIT; + dma_init.u32BlockSize = 1UL; + dma_init.u32TransCnt = 0UL; + dma_init.u32SrcInc = DMA_SRC_ADDR_INC; + dma_init.u32DestInc = DMA_DEST_ADDR_FIX; + DMA_Init(DMA_Instance, DMA_ch, &dma_init); + + /* Enable DMA module */ + DMA_Cmd(DMA_Instance, Enable); + DMA_SetTriggerSrc(DMA_Instance, DMA_ch, uart->config.dma_tx->trigger_evt_src); + } +} + +static void hc32_uart_tc_irq_handler(struct hc32_uart *uart) +{ + RT_ASSERT(uart != RT_NULL); + + USART_FuncCmd(uart->Instance, (USART_TX|USART_INT_TC), Disable); + + if (uart->serial.parent.open_flag & RT_DEVICE_FLAG_DMA_TX) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_TX_DMADONE); + } +} + +static void hc32_uart_dma_rx_irq_handler(struct hc32_uart *uart) +{ + struct rt_serial_device *serial; + rt_size_t recv_len; + rt_base_t level; + + RT_ASSERT(RT_NULL != uart); + RT_ASSERT(RT_NULL != uart->Instance); + + serial = &uart->serial; + + level = rt_hw_interrupt_disable(); + recv_len = serial->config.bufsz - uart->dma_rx_last_index; + uart->dma_rx_last_index = 0UL; + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } +} + +static void hc32_uart_rxto_irq_handler(struct hc32_uart *uart) +{ + rt_base_t level; + rt_size_t cnt; + rt_size_t recv_len; + rt_size_t recv_total_index; + + cnt = DMA_TRANS_CNT(uart->config.dma_rx->Instance , uart->config.dma_rx->channel); + recv_total_index = uart->serial.config.bufsz - cnt; + if (0UL != recv_total_index) + { + level = rt_hw_interrupt_disable(); + recv_len = recv_total_index - uart->dma_rx_last_index; + uart->dma_rx_last_index = recv_total_index; + rt_hw_interrupt_enable(level); + + if (recv_len) + { + rt_hw_serial_isr(&uart->serial, RT_SERIAL_EVENT_RX_DMADONE | (recv_len << 8)); + } + } + + TMR0_Cmd(uart->config.rx_timeout->TMR0_Instance, uart->config.rx_timeout->channel, Disable); + USART_ClearStatus(uart->Instance, USART_CLEAR_FLAG_RTOF); +} +#endif + +#if defined(BSP_USING_UART1) +static void hc32_uart1_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart1_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +static void hc32_uart1_tc_irq_handler(void) +{ +#if defined(BSP_UART1_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart1_rxto_irq_handler(void) +{ +#if defined(BSP_UART1_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart1_dma_rx_irq_handler(void) +{ +#if defined(BSP_UART1_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART1_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART1 */ + +#if defined(BSP_USING_UART2) +static void hc32_uart2_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart2_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart2_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +static void hc32_uart2_tc_irq_handler(void) +{ +#if defined(BSP_UART2_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart2_rxto_irq_handler(void) +{ +#if defined(BSP_UART2_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart2_dma_rx_irq_handler(void) +{ +#if defined(BSP_UART2_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART2_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART2 */ + +#if defined(BSP_USING_UART3) +static void hc32_uart3_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart3_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart3_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART3_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART3 */ + +#if defined(BSP_USING_UART4) +static void hc32_uart4_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart4_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart4_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART4_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART4 */ + +#if defined(BSP_USING_UART5) +static void hc32_uart5_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart5_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart5_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART5_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART5 */ + +#if defined(BSP_USING_UART6) +static void hc32_uart6_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart6_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart6_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +static void hc32_uart6_tc_irq_handler(void) +{ +#if defined(BSP_UART6_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart6_rxto_irq_handler(void) +{ +#if defined(BSP_UART6_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart6_dma_rx_irq_handler(void) +{ +#if defined(BSP_UART6_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART6_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART6 */ + +#if defined(BSP_USING_UART7) +static void hc32_uart7_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart7_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart7_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +#if defined(RT_SERIAL_USING_DMA) +static void hc32_uart7_tc_irq_handler(void) +{ +#if defined(BSP_UART7_TX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tc_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart7_rxto_irq_handler(void) +{ +#if defined(BSP_UART7_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxto_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} + +static void hc32_uart7_dma_rx_irq_handler(void) +{ +#if defined(BSP_UART7_RX_USING_DMA) + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_dma_rx_irq_handler(&uart_obj[UART7_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +#endif +} +#endif /* RT_SERIAL_USING_DMA */ +#endif /* BSP_USING_UART7 */ + +#if defined(BSP_USING_UART8) +static void hc32_uart8_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart8_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart8_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART8_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART8 */ + +#if defined(BSP_USING_UART9) +static void hc32_uart9_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart9_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart9_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART9_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART9 */ + +#if defined(BSP_USING_UART10) +static void hc32_uart10_rx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rx_irq_handler(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart10_tx_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_tx_irq_handler(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} + +static void hc32_uart10_rxerr_irq_handler(void) +{ + /* enter interrupt */ + rt_interrupt_enter(); + + hc32_uart_rxerr_irq_handler(&uart_obj[UART10_INDEX]); + + /* leave interrupt */ + rt_interrupt_leave(); +} +#endif /* BSP_USING_UART10 */ + +static const struct uart_irq_handler uart_irq_handlers[] = +{ +#ifdef BSP_USING_UART1 + {hc32_uart1_rxerr_irq_handler, hc32_uart1_rx_irq_handler, hc32_uart1_tx_irq_handler, + hc32_uart1_tc_irq_handler, hc32_uart1_rxto_irq_handler, hc32_uart1_dma_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART2 + {hc32_uart2_rxerr_irq_handler, hc32_uart2_rx_irq_handler, hc32_uart2_tx_irq_handler, + hc32_uart2_tc_irq_handler, hc32_uart2_rxto_irq_handler, hc32_uart2_dma_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART3 + {hc32_uart3_rxerr_irq_handler, hc32_uart3_rx_irq_handler, hc32_uart3_tx_irq_handler}, +#endif +#ifdef BSP_USING_UART4 + {hc32_uart4_rxerr_irq_handler, hc32_uart4_rx_irq_handler, hc32_uart4_tx_irq_handler}, +#endif +#ifdef BSP_USING_UART5 + {hc32_uart5_rxerr_irq_handler, hc32_uart5_rx_irq_handler, hc32_uart5_tx_irq_handler}, +#endif +#ifdef BSP_USING_UART6 + {hc32_uart6_rxerr_irq_handler, hc32_uart6_rx_irq_handler, hc32_uart6_tx_irq_handler, + hc32_uart6_tc_irq_handler, hc32_uart6_rxto_irq_handler, hc32_uart6_dma_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART7 + {hc32_uart7_rxerr_irq_handler, hc32_uart7_rx_irq_handler, hc32_uart7_tx_irq_handler, + hc32_uart7_tc_irq_handler, hc32_uart7_rxto_irq_handler, hc32_uart7_dma_rx_irq_handler}, +#endif +#ifdef BSP_USING_UART8 + {hc32_uart8_rxerr_irq_handler, hc32_uart8_rx_irq_handler, hc32_uart8_tx_irq_handler}, +#endif +#ifdef BSP_USING_UART9 + {hc32_uart9_rxerr_irq_handler, hc32_uart9_rx_irq_handler, hc32_uart9_tx_irq_handler}, +#endif +#ifdef BSP_USING_UART10 + {hc32_uart10_rxerr_irq_handler, hc32_uart10_rx_irq_handler, hc32_uart10_tx_irq_handler}, +#endif +}; + +static void hc32_uart_get_dma_config(void) +{ +#ifdef BSP_USING_UART1 + uart_obj[UART1_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART1_RX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + + static struct hc32_uart_rxto uart1_rx_timeout = UART_RXTO_CONFIG(USART1); + uart_obj[UART1_INDEX].config.rx_timeout = &uart1_rx_timeout; + + static struct dma_config uart1_dma_rx = UART_DMA_RX_CONFIG(USART1); + uart_obj[UART1_INDEX].config.dma_rx = &uart1_dma_rx; +#endif +#ifdef BSP_UART1_TX_USING_DMA + uart_obj[UART1_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + + static struct dma_config uart1_dma_tx = UART_DMA_TX_CONFIG(USART1); + uart_obj[UART1_INDEX].config.dma_tx = &uart1_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART2 + uart_obj[UART2_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART2_RX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + + static struct hc32_uart_rxto uart2_rx_timeout = UART_RXTO_CONFIG(USART2); + uart_obj[UART2_INDEX].config.rx_timeout = &uart2_rx_timeout; + + static struct dma_config uart2_dma_rx = UART_DMA_RX_CONFIG(USART2); + uart_obj[UART2_INDEX].config.dma_rx = &uart2_dma_rx; +#endif +#ifdef BSP_UART2_TX_USING_DMA + uart_obj[UART2_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + + static struct dma_config uart2_dma_tx = UART_DMA_TX_CONFIG(USART2); + uart_obj[UART2_INDEX].config.dma_tx = &uart2_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART6 + uart_obj[UART6_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART6_RX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + + static struct hc32_uart_rxto uart6_rx_timeout = UART_RXTO_CONFIG(USART6); + uart_obj[UART6_INDEX].config.rx_timeout = &uart6_rx_timeout; + + static struct dma_config uart6_dma_rx = UART_DMA_RX_CONFIG(USART6); + uart_obj[UART6_INDEX].config.dma_rx = &uart6_dma_rx; +#endif +#ifdef BSP_UART6_TX_USING_DMA + uart_obj[UART6_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + + static struct dma_config uart6_dma_tx = UART_DMA_TX_CONFIG(USART6); + uart_obj[UART6_INDEX].config.dma_tx = &uart6_dma_tx; +#endif +#endif + +#ifdef BSP_USING_UART7 + uart_obj[UART7_INDEX].uart_dma_flag = 0; +#ifdef BSP_UART7_RX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_RX; + + static struct hc32_uart_rxto uart7_rx_timeout = UART_RXTO_CONFIG(USART7); + uart_obj[UART7_INDEX].config.rx_timeout = &uart7_rx_timeout; + + static struct dma_config uart7_dma_rx = UART_DMA_RX_CONFIG(USART7); + uart_obj[UART7_INDEX].config.dma_rx = &uart7_dma_rx; +#endif +#ifdef BSP_UART7_TX_USING_DMA + uart_obj[UART7_INDEX].uart_dma_flag |= RT_DEVICE_FLAG_DMA_TX; + + static struct dma_config uart7_dma_tx = UART_DMA_TX_CONFIG(USART7); + uart_obj[UART7_INDEX].config.dma_tx = &uart7_dma_tx; +#endif +#endif +} + +static const struct rt_uart_ops hc32_uart_ops = +{ + .configure = hc32_configure, + .control = hc32_control, + .putc = hc32_putc, + .getc = hc32_getc, + .dma_transmit = hc32_dma_transmit +}; + +int hc32_hw_uart_init(void) +{ + rt_err_t result = RT_EOK; + rt_size_t obj_num = sizeof(uart_obj) / sizeof(struct hc32_uart); + struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; + + hc32_uart_get_dma_config(); + + for (int i = 0; i < obj_num; i++) + { + /* init UART object */ + uart_obj[i].serial.ops = &hc32_uart_ops; + uart_obj[i].serial.config = config; + + /* register UART device */ + result = rt_hw_serial_register(&uart_obj[i].serial, + uart_obj[i].name, + (RT_DEVICE_FLAG_RDWR | + RT_DEVICE_FLAG_INT_RX | + RT_DEVICE_FLAG_INT_TX | + uart_obj[i].uart_dma_flag), + &uart_obj[i]); + RT_ASSERT(result == RT_EOK); + } + + return result; +} + +INIT_BOARD_EXPORT(hc32_hw_uart_init); + +#endif /* RT_USING_SERIAL */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/drivers/drv_usart.h b/bsp/hc32f4a0/drivers/drv_usart.h new file mode 100644 index 0000000000000000000000000000000000000000..ba45e1dd411ecbce291d557c4c289bee8ad34f84 --- /dev/null +++ b/bsp/hc32f4a0/drivers/drv_usart.h @@ -0,0 +1,56 @@ +/* + * Copyright (C) 2020, Huada Semiconductor Co., Ltd. + * + * SPDX-License-Identifier: Apache-2.0 + * + * Change Logs: + * Date Author Notes + * 2020-10-30 CDT first version + */ + + +#ifndef __DRV_USART_H__ +#define __DRV_USART_H__ + +/******************************************************************************* + * Include files + ******************************************************************************/ +#include +#include "rtdevice.h" + +#include "hc32_ddl.h" +#include "drv_irq.h" +#include "drv_dma.h" + +/* C binding of definitions if building with C++ compiler */ +#ifdef __cplusplus +extern "C" +{ +#endif + +/******************************************************************************* + * Global type definitions ('typedef') + ******************************************************************************/ + +/******************************************************************************* + * Global pre-processor symbols/macros ('#define') + ******************************************************************************/ + +/******************************************************************************* + * Global variable definitions ('extern') + ******************************************************************************/ + +/******************************************************************************* + * Global function prototypes (definition in C source) + ******************************************************************************/ +int rt_hw_uart_init(void); + +#ifdef __cplusplus +} +#endif + +#endif /* __DRV_USART_H__ */ + +/******************************************************************************* + * EOF (not truncated) + ******************************************************************************/ diff --git a/bsp/hc32f4a0/figures/board.jpg b/bsp/hc32f4a0/figures/board.jpg new file mode 100644 index 0000000000000000000000000000000000000000..e0b1988d82d82bc44b93da9e1c82c66c4ae34dba Binary files /dev/null and b/bsp/hc32f4a0/figures/board.jpg differ diff --git a/bsp/hc32f4a0/project.ewd b/bsp/hc32f4a0/project.ewd new file mode 100644 index 0000000000000000000000000000000000000000..6b666cfa95d50b5747b68df8341146c2756e8381 --- /dev/null +++ b/bsp/hc32f4a0/project.ewd @@ -0,0 +1,3269 @@ + + + + 2 + + Release + + ARM + + 0 + + C-SPY + 2 + + 28 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ARMSIM_ID + 2 + + 1 + 1 + 0 + + + + + + + + ANGEL_ID + 2 + + 0 + 1 + 0 + + + + + + + + + + + + CADI_ID + 2 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$PROJ_DIR$\..\..\libcpu\arm\cortex-m4\cpuport.c + + + $PROJ_DIR$\..\..\libcpu\arm\cortex-m4\context_iar.S + + + + DeviceDrivers + + $PROJ_DIR$\..\..\components\drivers\misc\pin.c + + + $PROJ_DIR$\..\..\components\drivers\serial\serial.c + + + $PROJ_DIR$\..\..\components\drivers\src\completion.c + + + $PROJ_DIR$\..\..\components\drivers\src\dataqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\pipe.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringblk_buf.c + + + $PROJ_DIR$\..\..\components\drivers\src\ringbuffer.c + + + $PROJ_DIR$\..\..\components\drivers\src\waitqueue.c + + + $PROJ_DIR$\..\..\components\drivers\src\workqueue.c + + + + dlib + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\environ.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\libc.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\rmtx.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\stdio.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_close.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_lseek.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_mem.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_open.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_read.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_remove.c + + + $PROJ_DIR$\..\..\components\libc\compilers\dlib\syscall_write.c + + + + Drivers + + $PROJ_DIR$\board\board.c + + + $PROJ_DIR$\board\board_config.c + + + $PROJ_DIR$\drivers\drv_irq.c + + + $PROJ_DIR$\drivers\drv_gpio.c + + + $PROJ_DIR$\drivers\drv_usart.c + + + + Filesystem + + $PROJ_DIR$\..\..\components\dfs\src\dfs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_file.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_fs.c + + + $PROJ_DIR$\..\..\components\dfs\src\dfs_posix.c + + + $PROJ_DIR$\..\..\components\dfs\src\poll.c + + + $PROJ_DIR$\..\..\components\dfs\src\select.c + + + $PROJ_DIR$\..\..\components\dfs\filesystems\devfs\devfs.c + + + + finsh + + $PROJ_DIR$\..\..\components\finsh\shell.c + + + $PROJ_DIR$\..\..\components\finsh\cmd.c + + + $PROJ_DIR$\..\..\components\finsh\msh.c + + + $PROJ_DIR$\..\..\components\finsh\msh_file.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_compiler.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_error.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_heap.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_init.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_node.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_ops.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_parser.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_var.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_vm.c + + + $PROJ_DIR$\..\..\components\finsh\finsh_token.c + + + + HC32_StdPeriph + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32F4A0\Source\system_hc32f4a0.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_clk.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_dma.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_efm.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_gpio.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_icg.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_interrupts.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_pwc.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_sram.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_utility.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_usart.c + + + $PROJ_DIR$\Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_tmr0.c + + + $PROJ_DIR$\Libraries\CMSIS\Device\HDSC\HC32F4A0\Source\IAR\startup_hc32f4a0.s + + + + Kernel + + $PROJ_DIR$\..\..\src\clock.c + + + $PROJ_DIR$\..\..\src\components.c + + + $PROJ_DIR$\..\..\src\device.c + + + $PROJ_DIR$\..\..\src\idle.c + + + $PROJ_DIR$\..\..\src\ipc.c + + + $PROJ_DIR$\..\..\src\irq.c + + + $PROJ_DIR$\..\..\src\kservice.c + + + $PROJ_DIR$\..\..\src\mem.c + + + $PROJ_DIR$\..\..\src\mempool.c + + + $PROJ_DIR$\..\..\src\object.c + + + $PROJ_DIR$\..\..\src\scheduler.c + + + $PROJ_DIR$\..\..\src\signal.c + + + $PROJ_DIR$\..\..\src\thread.c + + + $PROJ_DIR$\..\..\src\timer.c + + + + libc + + $PROJ_DIR$\..\..\components\libc\compilers\common\time.c + + + $PROJ_DIR$\..\..\components\libc\compilers\common\unistd.c + + + diff --git a/bsp/hc32f4a0/project.eww b/bsp/hc32f4a0/project.eww new file mode 100644 index 0000000000000000000000000000000000000000..c2cb02eb1e89d73e24183274c1c886ddf74f9537 --- /dev/null +++ b/bsp/hc32f4a0/project.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\project.ewp + + + + + diff --git a/bsp/hc32f4a0/project.uvoptx b/bsp/hc32f4a0/project.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..916421140c711c39258e6f5e554d92d4d3a37d4e --- /dev/null +++ b/bsp/hc32f4a0/project.uvoptx @@ -0,0 +1,170 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + + + 0 + JL2CM3 + -U158007610 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + 1 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32f4a0/project.uvprojx b/bsp/hc32f4a0/project.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..1717d8b352e9126d9022cad7e84fd1db1c23f16f --- /dev/null +++ b/bsp/hc32f4a0/project.uvprojx @@ -0,0 +1,961 @@ + + + 2.1 +
### uVision Project, (C) Keil Software
+ + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + + + HC32F4A0SITB + HDSC + HDSC.HC32F4A0.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + 0 + $$Device:HC32F4A0SITB$Device\Include\HC32F4A0SITB.h + + + + + + + + + + $$Device:HC32F4A0SITB$CMSIS\SVD\hdsc_hc32f4a0.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x8000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x8000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + RT_USING_ARM_LIBC, USE_DDL_DRIVER, __DEBUG, HC32F4A0, __RTTHREAD__ + + applications;.;..\..\libcpu\arm\common;..\..\libcpu\arm\cortex-m4;..\..\components\drivers\include;..\..\components\drivers\include;..\..\components\drivers\include;board;drivers;..\..\components\dfs\include;..\..\components\dfs\filesystems\devfs;..\..\components\finsh;Libraries\CMSIS\Include;Libraries\CMSIS\Device\HDSC\HC32F4A0\Include;Libraries\HC32F4A0_StdPeriph_Driver\inc;.;..\..\include;..\..\components\libc\compilers\armlibc;..\..\components\libc\compilers\common + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + + + + + + + + + Applications + + + main.c + 1 + applications\main.c + + + + + cpu + + + backtrace.c + 1 + ..\..\libcpu\arm\common\backtrace.c + + + + + div0.c + 1 + ..\..\libcpu\arm\common\div0.c + + + + + showmem.c + 1 + ..\..\libcpu\arm\common\showmem.c + + + + + cpuport.c + 1 + ..\..\libcpu\arm\cortex-m4\cpuport.c + + + + + context_rvds.S + 2 + ..\..\libcpu\arm\cortex-m4\context_rvds.S + + + + + DeviceDrivers + + + pin.c + 1 + ..\..\components\drivers\misc\pin.c + + + + + serial.c + 1 + ..\..\components\drivers\serial\serial.c + + + + + completion.c + 1 + ..\..\components\drivers\src\completion.c + + + + + dataqueue.c + 1 + ..\..\components\drivers\src\dataqueue.c + + + + + pipe.c + 1 + ..\..\components\drivers\src\pipe.c + + + + + ringblk_buf.c + 1 + ..\..\components\drivers\src\ringblk_buf.c + + + + + ringbuffer.c + 1 + ..\..\components\drivers\src\ringbuffer.c + + + + + waitqueue.c + 1 + ..\..\components\drivers\src\waitqueue.c + + + + + workqueue.c + 1 + ..\..\components\drivers\src\workqueue.c + + + + + Drivers + + + board.c + 1 + board\board.c + + + + + board_config.c + 1 + board\board_config.c + + + + + drv_irq.c + 1 + drivers\drv_irq.c + + + + + drv_gpio.c + 1 + drivers\drv_gpio.c + + + + + drv_usart.c + 1 + drivers\drv_usart.c + + + + + Filesystem + + + dfs.c + 1 + ..\..\components\dfs\src\dfs.c + + + + + dfs_file.c + 1 + ..\..\components\dfs\src\dfs_file.c + + + + + dfs_fs.c + 1 + ..\..\components\dfs\src\dfs_fs.c + + + + + dfs_posix.c + 1 + ..\..\components\dfs\src\dfs_posix.c + + + + + poll.c + 1 + ..\..\components\dfs\src\poll.c + + + + + select.c + 1 + ..\..\components\dfs\src\select.c + + + + + devfs.c + 1 + ..\..\components\dfs\filesystems\devfs\devfs.c + + + + + finsh + + + shell.c + 1 + ..\..\components\finsh\shell.c + + + + + cmd.c + 1 + ..\..\components\finsh\cmd.c + + + + + msh.c + 1 + ..\..\components\finsh\msh.c + + + + + msh_file.c + 1 + ..\..\components\finsh\msh_file.c + + + + + finsh_compiler.c + 1 + ..\..\components\finsh\finsh_compiler.c + + + + + finsh_error.c + 1 + ..\..\components\finsh\finsh_error.c + + + + + finsh_heap.c + 1 + ..\..\components\finsh\finsh_heap.c + + + + + finsh_init.c + 1 + ..\..\components\finsh\finsh_init.c + + + + + finsh_node.c + 1 + ..\..\components\finsh\finsh_node.c + + + + + finsh_ops.c + 1 + ..\..\components\finsh\finsh_ops.c + + + + + finsh_parser.c + 1 + ..\..\components\finsh\finsh_parser.c + + + + + finsh_var.c + 1 + ..\..\components\finsh\finsh_var.c + + + + + finsh_vm.c + 1 + ..\..\components\finsh\finsh_vm.c + + + + + finsh_token.c + 1 + ..\..\components\finsh\finsh_token.c + + + + + HC32_StdPeriph + + + system_hc32f4a0.c + 1 + Libraries\CMSIS\Device\HDSC\HC32F4A0\Source\system_hc32f4a0.c + + + + + hc32f4a0_clk.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_clk.c + + + + + hc32f4a0_dma.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_dma.c + + + + + hc32f4a0_efm.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_efm.c + + + + + hc32f4a0_gpio.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_gpio.c + + + + + hc32f4a0_icg.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_icg.c + + + + + hc32f4a0_interrupts.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_interrupts.c + + + + + hc32f4a0_pwc.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_pwc.c + + + + + hc32f4a0_sram.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_sram.c + + + + + hc32f4a0_utility.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_utility.c + + + + + hc32f4a0_usart.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_usart.c + + + + + hc32f4a0_tmr0.c + 1 + Libraries\HC32F4A0_StdPeriph_Driver\src\hc32f4a0_tmr0.c + + + + + startup_hc32f4a0.s + 2 + Libraries\CMSIS\Device\HDSC\HC32F4A0\Source\ARM\startup_hc32f4a0.s + + + + + Kernel + + + clock.c + 1 + ..\..\src\clock.c + + + + + components.c + 1 + ..\..\src\components.c + + + + + device.c + 1 + ..\..\src\device.c + + + + + idle.c + 1 + ..\..\src\idle.c + + + + + ipc.c + 1 + ..\..\src\ipc.c + + + + + irq.c + 1 + ..\..\src\irq.c + + + + + kservice.c + 1 + ..\..\src\kservice.c + + + + + mem.c + 1 + ..\..\src\mem.c + + + + + mempool.c + 1 + ..\..\src\mempool.c + + + + + object.c + 1 + ..\..\src\object.c + + + + + scheduler.c + 1 + ..\..\src\scheduler.c + + + + + signal.c + 1 + ..\..\src\signal.c + + + + + thread.c + 1 + ..\..\src\thread.c + + + + + timer.c + 1 + ..\..\src\timer.c + + + + + libc + + + libc.c + 1 + ..\..\components\libc\compilers\armlibc\libc.c + + + + + mem_std.c + 1 + ..\..\components\libc\compilers\armlibc\mem_std.c + + + + + stdio.c + 1 + ..\..\components\libc\compilers\armlibc\stdio.c + + + + + stubs.c + 1 + ..\..\components\libc\compilers\armlibc\stubs.c + + + + + time.c + 1 + ..\..\components\libc\compilers\common\time.c + + + + + unistd.c + 1 + ..\..\components\libc\compilers\common\unistd.c + + + + + + + diff --git a/bsp/hc32f4a0/rtconfig.h b/bsp/hc32f4a0/rtconfig.h new file mode 100644 index 0000000000000000000000000000000000000000..dc456da17e4598cc0d85260a616a0742f16d9bce --- /dev/null +++ b/bsp/hc32f4a0/rtconfig.h @@ -0,0 +1,184 @@ +#ifndef RT_CONFIG_H__ +#define RT_CONFIG_H__ + +/* Automatically generated file; DO NOT EDIT. */ +/* RT-Thread Project Configuration */ + +/* RT-Thread Kernel */ + +#define RT_NAME_MAX 8 +#define RT_ALIGN_SIZE 4 +#define RT_THREAD_PRIORITY_32 +#define RT_THREAD_PRIORITY_MAX 32 +#define RT_TICK_PER_SECOND 1000 +#define RT_USING_OVERFLOW_CHECK +#define RT_USING_HOOK +#define RT_USING_IDLE_HOOK +#define RT_IDLE_HOOK_LIST_SIZE 4 +#define IDLE_THREAD_STACK_SIZE 256 +#define RT_USING_TIMER_SOFT +#define RT_TIMER_THREAD_PRIO 4 +#define RT_TIMER_THREAD_STACK_SIZE 512 +#define RT_DEBUG + +/* Inter-Thread communication */ + +#define RT_USING_SEMAPHORE +#define RT_USING_MUTEX +#define RT_USING_EVENT +#define RT_USING_MAILBOX +#define RT_USING_MESSAGEQUEUE + +/* Memory Management */ + +#define RT_USING_MEMPOOL +#define RT_USING_SMALL_MEM +#define RT_USING_HEAP + +/* Kernel Device Object */ + +#define RT_USING_DEVICE +#define RT_USING_CONSOLE +#define RT_CONSOLEBUF_SIZE 128 +#define RT_CONSOLE_DEVICE_NAME "uart1" +#define RT_VER_NUM 0x40003 +#define ARCH_ARM +#define RT_USING_CPU_FFS +#define ARCH_ARM_CORTEX_M +#define ARCH_ARM_CORTEX_M4 + +/* RT-Thread Components */ + +#define RT_USING_COMPONENTS_INIT +#define RT_USING_USER_MAIN +#define RT_MAIN_THREAD_STACK_SIZE 2048 +#define RT_MAIN_THREAD_PRIORITY 10 + +/* C++ features */ + + +/* Command shell */ + +#define RT_USING_FINSH +#define FINSH_THREAD_NAME "tshell" +#define FINSH_USING_HISTORY +#define FINSH_HISTORY_LINES 5 +#define FINSH_USING_SYMTAB +#define FINSH_USING_DESCRIPTION +#define FINSH_THREAD_PRIORITY 20 +#define FINSH_THREAD_STACK_SIZE 4096 +#define FINSH_CMD_SIZE 80 +#define FINSH_USING_MSH +#define FINSH_USING_MSH_DEFAULT +#define FINSH_ARG_MAX 10 + +/* Device virtual file system */ + +#define RT_USING_DFS +#define DFS_USING_WORKDIR +#define DFS_FILESYSTEMS_MAX 2 +#define DFS_FILESYSTEM_TYPES_MAX 2 +#define DFS_FD_MAX 16 +#define RT_USING_DFS_DEVFS + +/* Device Drivers */ + +#define RT_USING_DEVICE_IPC +#define RT_PIPE_BUFSZ 512 +#define RT_USING_SERIAL +#define RT_SERIAL_USING_DMA +#define RT_SERIAL_RB_BUFSZ 64 +#define RT_USING_PIN + +/* Using USB */ + + +/* POSIX layer and C standard library */ + +#define RT_USING_LIBC +#define RT_USING_POSIX + +/* Network */ + +/* Socket abstraction layer */ + + +/* Network interface device */ + + +/* light weight TCP/IP stack */ + + +/* AT commands */ + + +/* VBUS(Virtual Software BUS) */ + + +/* Utilities */ + + +/* RT-Thread online packages */ + +/* IoT - internet of things */ + + +/* Wi-Fi */ + +/* Marvell WiFi */ + + +/* Wiced WiFi */ + + +/* IoT Cloud */ + + +/* security packages */ + + +/* language packages */ + + +/* multimedia packages */ + + +/* tools packages */ + + +/* system packages */ + + +/* Micrium: Micrium software products porting for RT-Thread */ + + +/* peripheral libraries and drivers */ + + +/* miscellaneous packages */ + + +/* samples: kernel and components samples */ + + +/* games: games run on RT-Thread console */ + + +/* Hardware Drivers Config */ + +#define MCU_HC32F4A0 + +/* Onboard Peripheral Drivers */ + +/* On-chip Peripheral Drivers */ + +#define BSP_USING_GPIO +#define BSP_USING_UART +#define BSP_USING_UART1 +#define BSP_UART1_RX_USING_DMA +#define BSP_UART1_TX_USING_DMA + +/* Board extended module Drivers */ + + +#endif diff --git a/bsp/hc32f4a0/rtconfig.py b/bsp/hc32f4a0/rtconfig.py new file mode 100644 index 0000000000000000000000000000000000000000..5a57c9a84e0595e515047c15ebdf2438747755b0 --- /dev/null +++ b/bsp/hc32f4a0/rtconfig.py @@ -0,0 +1,132 @@ +import os + +# toolchains options +ARCH='arm' +CPU='cortex-m4' +CROSS_TOOL='iar' + +print "############rtconfig##############" + +if os.getenv('RTT_CC'): + CROSS_TOOL = os.getenv('RTT_CC') + +print "CROSS_TOOL: " + CROSS_TOOL + +# cross_tool provides the cross compiler +# EXEC_PATH is the compiler execute path, for example, CodeSourcery, Keil MDK, IAR +if CROSS_TOOL == 'gcc': + PLATFORM = 'gcc' + EXEC_PATH = r'E:/Program Files/CodeSourcery/Sourcery G++ Lite/bin' +elif CROSS_TOOL == 'keil': + PLATFORM = 'armcc' + EXEC_PATH = r'D:\03_software\Program Files\Keil_v5' +elif CROSS_TOOL == 'iar': + PLATFORM = 'iar' + EXEC_PATH = r'D:\03_software\Program Files\IAR Systems\Embedded Workbench 7.5' + +if os.getenv('RTT_EXEC_PATH'): + EXEC_PATH = os.getenv('RTT_EXEC_PATH') + +BUILD = 'debug' +MCU_TYPE = 'HC32F4A0' + +if PLATFORM == 'gcc': + # toolchains + PREFIX = 'arm-none-eabi-' + CC = PREFIX + 'gcc' + AS = PREFIX + 'gcc' + AR = PREFIX + 'ar' + LINK = PREFIX + 'gcc' + TARGET_EXT = 'elf' + SIZE = PREFIX + 'size' + OBJDUMP = PREFIX + 'objdump' + OBJCPY = PREFIX + 'objcopy' + + DEVICE = ' -mcpu=cortex-m4 -mthumb -mfpu=fpv4-sp-d16 -mfloat-abi=hard -ffunction-sections -fdata-sections' + CFLAGS = DEVICE + ' -g -Wall -DHC32F4A0 -D__DEBUG -DUSE_DDL_DRIVER -D__ASSEMBLY__ -D__FPU_USED' + AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp -Wa,-mimplicit-it=thumb ' + LFLAGS = DEVICE + ' -lm -lgcc -lc' + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,Reset_Handler -T board/linker_scripts/link.lds' + + CPATH = '' + LPATH = '' + + if BUILD == 'debug': + CFLAGS += ' -O0 -gdwarf-2' + AFLAGS += ' -gdwarf-2' + else: + CFLAGS += ' -O2' + + POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n' + +elif PLATFORM == 'armcc': + # toolchains + CC = 'armcc' + AS = 'armasm' + AR = 'armar' + LINK = 'armlink' + TARGET_EXT = 'axf' + + DEVICE = ' --cpu=cortex-m4.fp' + CFLAGS = DEVICE + ' --apcs=interwork -DUSE_DDL_DRIVER -DHC32F4A0 -D__DEBUG' + AFLAGS = DEVICE + LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread.map --scatter "board/linker_scripts/link.sct"' + + CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC' + LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB' + + EXEC_PATH += '/arm/bin40/' + + if BUILD == 'debug': + CFLAGS += ' -g -O0' + AFLAGS += ' -g' + else: + CFLAGS += ' -O2' + + POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET' + +elif PLATFORM == 'iar': + # toolchains + CC = 'iccarm' + AS = 'iasmarm' + AR = 'iarchive' + LINK = 'ilinkarm' + TARGET_EXT = 'out' + + DEVICE = ' -D __DEBUG' + ' -D USE_DDL_DRIVER' + ' -D HC32F4A0' + + CFLAGS = DEVICE + CFLAGS += ' --diag_suppress Pa050' + CFLAGS += ' --no_cse' + CFLAGS += ' --no_unroll' + CFLAGS += ' --no_inline' + CFLAGS += ' --no_code_motion' + CFLAGS += ' --no_tbaa' + CFLAGS += ' --no_clustering' + CFLAGS += ' --no_scheduling' + CFLAGS += ' --endian=little' + CFLAGS += ' --cpu=Cortex-M4' + CFLAGS += ' -e' + CFLAGS += ' --fpu=None' + CFLAGS += ' --dlib_config "' + EXEC_PATH + '/arm/INC/c/DLib_Config_Normal.h"' + CFLAGS += ' -Ol' + CFLAGS += ' --use_c++_inline' + + AFLAGS = '' + AFLAGS += ' -s+' + AFLAGS += ' -w+' + AFLAGS += ' -r' + AFLAGS += ' --cpu Cortex-M4' + AFLAGS += ' --fpu None' + if BUILD == 'debug': + CFLAGS += ' --debug' + CFLAGS += ' -On' + else: + CFLAGS += ' -Oh' + + LFLAGS = ' --config "board/linker_scripts/link.icf"' + LFLAGS += ' --redirect _Printf=_PrintfTiny' + LFLAGS += ' --redirect _Scanf=_ScanfSmall' + LFLAGS += ' --entry __iar_program_start' + + EXEC_PATH = EXEC_PATH + '/arm/bin/' + POST_ACTION = '' diff --git a/bsp/hc32f4a0/template.ewp b/bsp/hc32f4a0/template.ewp new file mode 100644 index 0000000000000000000000000000000000000000..1f8117173871aa7a2dfb7ee4aeba04c2c095bd45 --- /dev/null +++ b/bsp/hc32f4a0/template.ewp @@ -0,0 +1,1925 @@ + + + + 2 + + Release + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + Debug + + ARM + + 0 + + General + 3 + + 24 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + ICCARM + 2 + + 31 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + AARM + 2 + + 9 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + OBJCOPY + 0 + + 1 + 1 + 0 + + + + + + + + + CUSTOM + 3 + + + + 0 + + + + BICOMP + 0 + + + + BUILDACTION + 1 + + + + + + + ILINK + 0 + + 17 + 1 + 0 + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + IARCHIVE + 0 + + 0 + 1 + 0 + + + + + + + BILINK + 0 + + + + + + diff --git a/bsp/hc32f4a0/template.eww b/bsp/hc32f4a0/template.eww new file mode 100644 index 0000000000000000000000000000000000000000..bd036bb4c98c1598f04b85f64b0dff37f6ec6028 --- /dev/null +++ b/bsp/hc32f4a0/template.eww @@ -0,0 +1,10 @@ + + + + + $WS_DIR$\template.ewp + + + + + diff --git a/bsp/hc32f4a0/template.uvoptx b/bsp/hc32f4a0/template.uvoptx new file mode 100644 index 0000000000000000000000000000000000000000..916421140c711c39258e6f5e554d92d4d3a37d4e --- /dev/null +++ b/bsp/hc32f4a0/template.uvoptx @@ -0,0 +1,170 @@ + + + + 1.0 + +
### uVision Project, (C) Keil Software
+ + + *.c + *.s*; *.src; *.a* + *.obj; *.o + *.lib + *.txt; *.h; *.inc + *.plm + *.cpp + 0 + + + + 0 + 0 + + + + rt-thread + 0x4 + ARM-ADS + + 12000000 + + 1 + 1 + 0 + 1 + 0 + + + 1 + 65535 + 0 + 0 + 0 + + + 79 + 66 + 8 + .\build\ + + + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 0 + 0 + 0 + 0 + + + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + + + 0 + 0 + 1 + + 255 + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + 1 + 0 + 0 + 6 + + + + + + + + + + + Segger\JL2CM3.dll + + + + 0 + UL2CM3 + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + + + 0 + JL2CM3 + -U158007610 -O78 -S2 -ZTIFSpeedSel5000 -A0 -C0 -JU1 -JI127.0.0.1 -JP0 -RST2 -N00("ARM CoreSight SW-DP") -D00(2BA01477) -L00(0) -TO18 -TC10000000 -TP21 -TDS8007 -TDT0 -TDC1F -TIEFFFFFFFF -TIP8 -TB1 -TFE0 -FO7 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM) + + + + + 0 + + + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + 0 + + 1 + 0 + 2 + 1000000 + + + + + diff --git a/bsp/hc32f4a0/template.uvprojx b/bsp/hc32f4a0/template.uvprojx new file mode 100644 index 0000000000000000000000000000000000000000..a684e588ed2253838d0d23ecf2ca504e624008d9 --- /dev/null +++ b/bsp/hc32f4a0/template.uvprojx @@ -0,0 +1,418 @@ + + + + 2.1 + +
### uVision Project, (C) Keil Software
+ + + + rt-thread + 0x4 + ARM-ADS + 5060020::V5.06 (build 20)::ARMCC + + + HC32F4A0SITB + HDSC + HDSC.HC32F4A0.1.0.0 + https://raw.githubusercontent.com/hdscmcu/pack/master/ + IROM(0x00000000,0x200000) IRAM(0x1FFE0000,0x80000) IRAM2(0X200F0000,0x1000) CPUTYPE("Cortex-M4") FPU2 CLOCK(240000000) ESEL ELITTLE + + + UL2CM3(-S0 -C0 -P0 -FD1FFE0000 -FC1000 -FN1 -FF0HC32F4A0 -FS00 -FL0200000 -FP0($$Device:HC32F4A0SITB$FlashARM\HC32F4A0_2M.FLM)) + 0 + $$Device:HC32F4A0SITB$Device\Include\HC32F4A0SITB.h + + + + + + + + + + $$Device:HC32F4A0SITB$CMSIS\SVD\hdsc_hc32f4a0.SFR + 1 + 0 + + + + + + + 0 + 0 + 0 + 0 + 1 + + .\build\keil\Obj\ + rtthread + 1 + 0 + 0 + 1 + 0 + .\build\ + 1 + 0 + 0 + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 0 + 0 + + + 0 + 0 + 0 + 0 + + + 1 + 0 + fromelf --bin !L --output rtthread.bin + + 0 + 0 + 0 + 0 + + 0 + + + + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 3 + + + 1 + + + SARMCM3.DLL + -MPU + DCM.DLL + -pCM4 + SARMCM3.DLL + -MPU + TCM.DLL + -pCM4 + + + + 1 + 0 + 0 + 0 + 16 + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + + + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 1 + + 0 + 6 + + + + + + + + + + + + + + Segger\JL2CM3.dll + + + + + 1 + 0 + 0 + 1 + 1 + 4096 + + 1 + BIN\UL2CM3.DLL + "" () + + + + + 0 + + + + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 1 + 1 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 1 + 0 + 0 + "Cortex-M4" + + 0 + 0 + 0 + 1 + 1 + 0 + 0 + 1 + 1 + 0 + 8 + 0 + 0 + 0 + 0 + 3 + 3 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 1 + 0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x8000 + + + 1 + 0x0 + 0x80000 + + + 0 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x0 + + + 1 + 0x0 + 0x80000 + + + 1 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x0 + 0x0 + + + 0 + 0x1fff8000 + 0x8000 + + + 0 + 0x20000000 + 0x10000 + + + + + + 1 + 1 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 1 + 0 + 0 + 0 + 0 + 0 + + --diag_suppress=186,66 + __DEBUG,HC32F4A0,USE_DDL_DRIVER + + + + + + 1 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + 0 + + + + + + + + + 0 + 0 + 0 + 0 + 1 + 0 + 0x00000000 + 0x1FFF8000 + + .\board\linker_scripts\link.sct + + + --keep=*Handler + + + + + + + + +